Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8355935	1			T1	30		T3	10		T5	6
all_levels[1]	2528959	1			T1	6		T9	37393		T13	31
all_levels[2]	416962	1			T9	775		T13	18		T14	53
all_levels[3]	400688	1			T5	1		T9	775		T13	38
all_levels[4]	579785	1			T5	1		T9	763		T13	32
all_levels[5]	305208	1			T5	2		T9	739		T13	24
all_levels[6]	257557	1			T5	1		T9	534		T13	24
all_levels[7]	372872	1			T5	2		T9	420		T13	21
all_levels[8]	373709	1			T5	1		T9	503		T13	21
all_levels[9]	379879	1			T5	2		T9	481		T12	3
all_levels[10]	237140	1			T3	7		T5	1		T9	479
all_levels[11]	244498	1			T3	2		T5	2		T9	468
all_levels[12]	360632	1			T5	2		T9	485		T13	328
all_levels[13]	689745	1			T9	9269		T13	12		T14	58
all_levels[14]	313667	1			T1	3		T3	1		T9	27129
all_levels[15]	221580	1			T9	463		T13	4		T14	65
all_levels[16]	428658	1			T9	490		T13	1		T14	69
all_levels[17]	229530	1			T9	494		T13	3		T14	70
all_levels[18]	278684	1			T3	2		T9	481		T13	116
all_levels[19]	225469	1			T9	488		T13	2		T14	52
all_levels[20]	280950	1			T9	548		T14	61		T23	1
all_levels[21]	692647	1			T9	557		T12	1		T13	8
all_levels[22]	249550	1			T9	491		T13	4		T14	50
all_levels[23]	434905	1			T9	535		T13	1		T14	63
all_levels[24]	283671	1			T9	549		T14	45		T23	2
all_levels[25]	244684	1			T9	561		T14	65		T111	3
all_levels[26]	229879	1			T9	560		T14	61		T23	103
all_levels[27]	349019	1			T9	519		T13	2		T14	66
all_levels[28]	366299	1			T5	65		T9	548		T14	67
all_levels[29]	403968	1			T9	7007		T13	2		T14	50
all_levels[30]	235150	1			T9	790		T13	15		T14	70
all_levels[31]	899561	1			T9	802		T13	20		T14	1170
all_levels[32]	14695546	1			T1	7		T5	59		T8	3

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36562729

1

T1

39

T3

22

T5

144

auto[1]

4257

1

T1

7

T5

1

T7

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8353651	1			T1	29		T3	10		T5	6
all_levels[0]	auto[1]	2284	1			T1	1		T7	1		T8	3
all_levels[1]	auto[0]	2528552	1			T1	3		T9	37391		T13	31
all_levels[1]	auto[1]	407	1			T1	3		T9	2		T84	6
all_levels[2]	auto[0]	416928	1			T9	774		T13	18		T14	53
all_levels[2]	auto[1]	34	1			T9	1		T34	2		T161	3
all_levels[3]	auto[0]	400525	1			T5	1		T9	775		T13	38
all_levels[3]	auto[1]	163	1			T276	1		T309	12		T327	20
all_levels[4]	auto[0]	579755	1			T5	1		T9	763		T13	32
all_levels[4]	auto[1]	30	1			T152	1		T218	1		T160	3
all_levels[5]	auto[0]	305172	1			T5	2		T9	739		T13	24
all_levels[5]	auto[1]	36	1			T132	3		T153	2		T270	2
all_levels[6]	auto[0]	257534	1			T5	1		T9	534		T13	24
all_levels[6]	auto[1]	23	1			T134	1		T328	1		T329	1
all_levels[7]	auto[0]	372782	1			T5	2		T9	420		T13	21
all_levels[7]	auto[1]	90	1			T23	4		T135	1		T19	2
all_levels[8]	auto[0]	373677	1			T5	1		T9	503		T13	21
all_levels[8]	auto[1]	32	1			T303	1		T54	1		T179	2
all_levels[9]	auto[0]	379847	1			T5	2		T9	481		T12	2
all_levels[9]	auto[1]	32	1			T12	1		T266	1		T102	1
all_levels[10]	auto[0]	237115	1			T3	7		T5	1		T9	479
all_levels[10]	auto[1]	25	1			T40	1		T293	1		T135	2
all_levels[11]	auto[0]	244469	1			T3	2		T5	2		T9	468
all_levels[11]	auto[1]	29	1			T123	1		T24	1		T19	1
all_levels[12]	auto[0]	360602	1			T5	2		T9	485		T13	328
all_levels[12]	auto[1]	30	1			T182	1		T330	1		T331	1
all_levels[13]	auto[0]	689722	1			T9	9268		T13	12		T14	58
all_levels[13]	auto[1]	23	1			T9	1		T260	1		T101	1
all_levels[14]	auto[0]	313651	1			T1	2		T3	1		T9	27129
all_levels[14]	auto[1]	16	1			T1	1		T23	1		T135	1
all_levels[15]	auto[0]	221416	1			T9	463		T13	4		T14	65
all_levels[15]	auto[1]	164	1			T23	8		T17	12		T34	3
all_levels[16]	auto[0]	428637	1			T9	490		T13	1		T14	69
all_levels[16]	auto[1]	21	1			T182	2		T185	2		T189	1
all_levels[17]	auto[0]	229515	1			T9	494		T13	3		T14	70
all_levels[17]	auto[1]	15	1			T191	1		T188	2		T332	1
all_levels[18]	auto[0]	278665	1			T3	2		T9	481		T13	116
all_levels[18]	auto[1]	19	1			T139	2		T221	1		T333	1
all_levels[19]	auto[0]	225440	1			T9	488		T13	2		T14	52
all_levels[19]	auto[1]	29	1			T19	1		T274	1		T255	1
all_levels[20]	auto[0]	280928	1			T9	548		T14	61		T23	1
all_levels[20]	auto[1]	22	1			T255	1		T334	1		T171	1
all_levels[21]	auto[0]	692624	1			T9	557		T12	1		T13	7
all_levels[21]	auto[1]	23	1			T13	1		T24	1		T37	1
all_levels[22]	auto[0]	249523	1			T9	491		T13	4		T14	50
all_levels[22]	auto[1]	27	1			T112	5		T185	1		T335	2
all_levels[23]	auto[0]	434877	1			T9	535		T13	1		T14	63
all_levels[23]	auto[1]	28	1			T254	1		T113	2		T101	1
all_levels[24]	auto[0]	283653	1			T9	549		T14	45		T23	2
all_levels[24]	auto[1]	18	1			T113	1		T265	1		T139	3
all_levels[25]	auto[0]	244666	1			T9	561		T14	65		T111	3
all_levels[25]	auto[1]	18	1			T126	2		T308	2		T336	1
all_levels[26]	auto[0]	229864	1			T9	560		T14	61		T23	103
all_levels[26]	auto[1]	15	1			T288	1		T337	1		T338	1
all_levels[27]	auto[0]	349012	1			T9	519		T13	2		T14	66
all_levels[27]	auto[1]	7	1			T123	2		T295	1		T339	1
all_levels[28]	auto[0]	366283	1			T5	65		T9	548		T14	67
all_levels[28]	auto[1]	16	1			T126	2		T182	1		T340	1
all_levels[29]	auto[0]	403926	1			T9	7007		T13	2		T14	50
all_levels[29]	auto[1]	42	1			T33	13		T54	2		T341	1
all_levels[30]	auto[0]	235131	1			T9	790		T13	15		T14	70
all_levels[30]	auto[1]	19	1			T280	1		T139	1		T131	3
all_levels[31]	auto[0]	899547	1			T9	802		T13	20		T14	1170
all_levels[31]	auto[1]	14	1			T319	1		T342	1		T343	1
all_levels[32]	auto[0]	14695040	1			T1	5		T5	58		T8	1
all_levels[32]	auto[1]	506	1			T1	2		T5	1		T8	2