Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	796	1			T9	4		T21	4		T31	11
all_values[1]	796	1			T9	4		T21	4		T31	11
all_values[2]	796	1			T9	4		T21	4		T31	11
all_values[3]	796	1			T9	4		T21	4		T31	11
all_values[4]	796	1			T9	4		T21	4		T31	11
all_values[5]	796	1			T9	4		T21	4		T31	11
all_values[6]	796	1			T9	4		T21	4		T31	11
all_values[7]	796	1			T9	4		T21	4		T31	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3423

1

T9

17

T21

14

T31

41

auto[1]

2945

1

T9

15

T21

18

T31

47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2374

1

T9

13

T21

13

T31

38

auto[1]

3994

1

T9

19

T21

19

T31

50

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3813

1

T9

21

T21

21

T31

54

auto[1]

2555

1

T9

11

T21

11

T31

34

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	252	1			T9	2		T21	1		T31	1
all_values[0]	auto[0]	auto[1]	auto[1]	214	1			T9	2		T21	3		T31	4
all_values[0]	auto[1]	auto[0]	auto[1]	193	1			T31	3		T34	3		T36	1
all_values[0]	auto[1]	auto[1]	auto[1]	137	1			T31	3		T101	2		T120	2
all_values[1]	auto[0]	auto[0]	auto[0]	243	1			T9	1		T21	1		T31	6
all_values[1]	auto[0]	auto[1]	auto[0]	225	1			T9	1		T21	1		T31	3
all_values[1]	auto[1]	auto[0]	auto[1]	180	1			T31	2		T34	2		T101	1
all_values[1]	auto[1]	auto[1]	auto[1]	148	1			T9	2		T21	2		T36	1
all_values[2]	auto[0]	auto[0]	auto[0]	168	1			T21	1		T31	5		T34	1
all_values[2]	auto[0]	auto[0]	auto[1]	86	1			T9	1		T34	2		T36	3
all_values[2]	auto[0]	auto[1]	auto[0]	150	1			T21	1		T31	3		T101	3
all_values[2]	auto[0]	auto[1]	auto[1]	76	1			T9	1		T31	1		T54	2
all_values[2]	auto[1]	auto[0]	auto[1]	153	1			T34	1		T101	1		T54	2
all_values[2]	auto[1]	auto[1]	auto[1]	163	1			T9	2		T21	2		T31	2
all_values[3]	auto[0]	auto[0]	auto[0]	199	1			T9	1		T31	6		T36	4
all_values[3]	auto[0]	auto[0]	auto[1]	85	1			T31	1		T34	1		T101	2
all_values[3]	auto[0]	auto[1]	auto[0]	127	1			T21	1		T101	2		T110	2
all_values[3]	auto[0]	auto[1]	auto[1]	74	1			T9	2		T54	1		T55	1
all_values[3]	auto[1]	auto[0]	auto[1]	180	1			T9	1		T21	2		T31	3
all_values[3]	auto[1]	auto[1]	auto[1]	131	1			T21	1		T31	1		T54	1
all_values[4]	auto[0]	auto[0]	auto[0]	165	1			T9	2		T36	1		T101	3
all_values[4]	auto[0]	auto[0]	auto[1]	92	1			T21	1		T31	1		T34	1
all_values[4]	auto[0]	auto[1]	auto[0]	144	1			T9	1		T36	2		T101	1
all_values[4]	auto[0]	auto[1]	auto[1]	70	1			T21	2		T31	2		T34	1
all_values[4]	auto[1]	auto[0]	auto[1]	176	1			T9	1		T21	1		T31	4
all_values[4]	auto[1]	auto[1]	auto[1]	149	1			T31	4		T34	1		T36	1
all_values[5]	auto[0]	auto[0]	auto[0]	175	1			T9	2		T21	2		T31	2
all_values[5]	auto[0]	auto[0]	auto[1]	77	1			T31	1		T55	1		T110	1
all_values[5]	auto[0]	auto[1]	auto[0]	154	1			T9	1		T21	2		T31	5
all_values[5]	auto[0]	auto[1]	auto[1]	81	1			T34	1		T36	1		T101	1
all_values[5]	auto[1]	auto[0]	auto[1]	169	1			T31	1		T34	1		T36	1
all_values[5]	auto[1]	auto[1]	auto[1]	140	1			T9	1		T31	2		T34	1
all_values[6]	auto[0]	auto[0]	auto[0]	177	1			T9	2		T21	2		T31	3
all_values[6]	auto[0]	auto[0]	auto[1]	59	1			T36	1		T101	2		T110	1
all_values[6]	auto[0]	auto[1]	auto[0]	131	1			T9	1		T21	1		T31	2
all_values[6]	auto[0]	auto[1]	auto[1]	109	1			T31	2		T54	1		T55	2
all_values[6]	auto[1]	auto[0]	auto[1]	177	1			T9	1		T21	1		T36	2
all_values[6]	auto[1]	auto[1]	auto[1]	143	1			T31	4		T101	2		T55	3
all_values[7]	auto[0]	auto[0]	auto[0]	177	1			T9	1		T21	1		T31	1
all_values[7]	auto[0]	auto[0]	auto[1]	74	1			T36	2		T54	2		T55	2
all_values[7]	auto[0]	auto[1]	auto[0]	139	1			T31	2		T101	3		T120	1
all_values[7]	auto[0]	auto[1]	auto[1]	90	1			T21	1		T31	3		T101	1
all_values[7]	auto[1]	auto[0]	auto[1]	166	1			T9	2		T21	1		T31	1
all_values[7]	auto[1]	auto[1]	auto[1]	150	1			T9	1		T21	1		T31	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal