Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.27 99.27 97.95 100.00 98.80 100.00 99.59


Total test records in report: 1317
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T90 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1895913935 May 19 12:25:16 PM PDT 24 May 19 12:25:25 PM PDT 24 87367065 ps
T1254 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.427863489 May 19 12:18:48 PM PDT 24 May 19 12:18:50 PM PDT 24 74412293 ps
T1255 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3220644222 May 19 12:25:17 PM PDT 24 May 19 12:25:25 PM PDT 24 21411853 ps
T1256 /workspace/coverage/cover_reg_top/6.uart_csr_rw.3484958409 May 19 12:24:00 PM PDT 24 May 19 12:24:08 PM PDT 24 17789205 ps
T1257 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.343790236 May 19 12:21:50 PM PDT 24 May 19 12:21:54 PM PDT 24 96934636 ps
T1258 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1716500526 May 19 12:24:00 PM PDT 24 May 19 12:24:09 PM PDT 24 26554336 ps
T1259 /workspace/coverage/cover_reg_top/36.uart_intr_test.663446757 May 19 12:25:18 PM PDT 24 May 19 12:25:26 PM PDT 24 16141105 ps
T1260 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3334811688 May 19 12:23:27 PM PDT 24 May 19 12:23:47 PM PDT 24 16818159 ps
T1261 /workspace/coverage/cover_reg_top/5.uart_tl_errors.2192761868 May 19 12:19:29 PM PDT 24 May 19 12:19:31 PM PDT 24 707434412 ps
T1262 /workspace/coverage/cover_reg_top/1.uart_intr_test.1780610178 May 19 12:18:59 PM PDT 24 May 19 12:19:01 PM PDT 24 13656990 ps
T1263 /workspace/coverage/cover_reg_top/9.uart_tl_errors.3329068013 May 19 12:23:35 PM PDT 24 May 19 12:23:58 PM PDT 24 194188027 ps
T1264 /workspace/coverage/cover_reg_top/12.uart_tl_errors.4097888116 May 19 12:25:17 PM PDT 24 May 19 12:25:26 PM PDT 24 120079882 ps
T1265 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2422549581 May 19 12:20:51 PM PDT 24 May 19 12:20:53 PM PDT 24 23071485 ps
T1266 /workspace/coverage/cover_reg_top/41.uart_intr_test.663908507 May 19 12:25:13 PM PDT 24 May 19 12:25:22 PM PDT 24 18002582 ps
T1267 /workspace/coverage/cover_reg_top/26.uart_intr_test.3463324358 May 19 12:25:25 PM PDT 24 May 19 12:25:29 PM PDT 24 32341602 ps
T1268 /workspace/coverage/cover_reg_top/39.uart_intr_test.1087187443 May 19 12:25:12 PM PDT 24 May 19 12:25:21 PM PDT 24 18504771 ps
T1269 /workspace/coverage/cover_reg_top/31.uart_intr_test.2369384329 May 19 12:25:17 PM PDT 24 May 19 12:25:24 PM PDT 24 109814553 ps
T1270 /workspace/coverage/cover_reg_top/17.uart_tl_errors.703211320 May 19 12:25:15 PM PDT 24 May 19 12:25:24 PM PDT 24 101511859 ps
T1271 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.722005401 May 19 12:25:13 PM PDT 24 May 19 12:25:23 PM PDT 24 52793483 ps
T1272 /workspace/coverage/cover_reg_top/3.uart_csr_rw.4132397810 May 19 12:23:26 PM PDT 24 May 19 12:23:47 PM PDT 24 16129439 ps
T1273 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3291367384 May 19 12:20:53 PM PDT 24 May 19 12:20:55 PM PDT 24 23807176 ps
T1274 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.157143570 May 19 12:23:56 PM PDT 24 May 19 12:24:06 PM PDT 24 53947491 ps
T1275 /workspace/coverage/cover_reg_top/5.uart_intr_test.257873934 May 19 12:22:04 PM PDT 24 May 19 12:22:06 PM PDT 24 55320845 ps
T1276 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3241712396 May 19 12:21:19 PM PDT 24 May 19 12:21:23 PM PDT 24 42345944 ps
T1277 /workspace/coverage/cover_reg_top/2.uart_intr_test.2508889293 May 19 12:20:37 PM PDT 24 May 19 12:20:41 PM PDT 24 38329083 ps
T1278 /workspace/coverage/cover_reg_top/24.uart_intr_test.1039750935 May 19 12:25:06 PM PDT 24 May 19 12:25:14 PM PDT 24 37575398 ps
T1279 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2160294301 May 19 12:20:07 PM PDT 24 May 19 12:20:09 PM PDT 24 123373071 ps
T1280 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1632465172 May 19 12:23:02 PM PDT 24 May 19 12:23:04 PM PDT 24 85578613 ps
T1281 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1620432185 May 19 12:23:36 PM PDT 24 May 19 12:23:57 PM PDT 24 165538263 ps
T1282 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1167470613 May 19 12:24:00 PM PDT 24 May 19 12:24:08 PM PDT 24 99518442 ps
T1283 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.920583865 May 19 12:19:27 PM PDT 24 May 19 12:19:29 PM PDT 24 17903542 ps
T1284 /workspace/coverage/cover_reg_top/1.uart_csr_rw.58560292 May 19 12:23:56 PM PDT 24 May 19 12:24:06 PM PDT 24 48665163 ps
T1285 /workspace/coverage/cover_reg_top/47.uart_intr_test.4229889351 May 19 12:25:18 PM PDT 24 May 19 12:25:26 PM PDT 24 13236458 ps
T1286 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1751016819 May 19 12:23:06 PM PDT 24 May 19 12:23:09 PM PDT 24 83673655 ps
T1287 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1911711039 May 19 12:25:16 PM PDT 24 May 19 12:25:24 PM PDT 24 60144266 ps
T1288 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3122831422 May 19 12:21:21 PM PDT 24 May 19 12:21:23 PM PDT 24 46020877 ps
T1289 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3180598977 May 19 12:25:48 PM PDT 24 May 19 12:25:50 PM PDT 24 54028905 ps
T1290 /workspace/coverage/cover_reg_top/35.uart_intr_test.1873853140 May 19 12:25:25 PM PDT 24 May 19 12:25:29 PM PDT 24 75278698 ps
T1291 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.572170634 May 19 12:22:09 PM PDT 24 May 19 12:22:11 PM PDT 24 181734771 ps
T1292 /workspace/coverage/cover_reg_top/8.uart_csr_rw.144093291 May 19 12:23:27 PM PDT 24 May 19 12:23:48 PM PDT 24 13496607 ps
T1293 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3684557568 May 19 12:18:41 PM PDT 24 May 19 12:18:44 PM PDT 24 181850039 ps
T1294 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3742804385 May 19 12:25:17 PM PDT 24 May 19 12:25:25 PM PDT 24 22175058 ps
T1295 /workspace/coverage/cover_reg_top/7.uart_csr_rw.535793214 May 19 12:19:29 PM PDT 24 May 19 12:19:30 PM PDT 24 28083979 ps
T1296 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3519165328 May 19 12:21:49 PM PDT 24 May 19 12:21:52 PM PDT 24 44734029 ps
T1297 /workspace/coverage/cover_reg_top/9.uart_csr_rw.2714886676 May 19 12:23:32 PM PDT 24 May 19 12:23:53 PM PDT 24 12270784 ps
T1298 /workspace/coverage/cover_reg_top/18.uart_tl_errors.797218521 May 19 12:25:35 PM PDT 24 May 19 12:25:38 PM PDT 24 47477447 ps
T1299 /workspace/coverage/cover_reg_top/0.uart_tl_errors.587373893 May 19 12:23:27 PM PDT 24 May 19 12:23:48 PM PDT 24 61740814 ps
T1300 /workspace/coverage/cover_reg_top/49.uart_intr_test.1137037044 May 19 12:25:16 PM PDT 24 May 19 12:25:24 PM PDT 24 77313647 ps
T1301 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.532134827 May 19 12:18:35 PM PDT 24 May 19 12:18:39 PM PDT 24 92980774 ps
T1302 /workspace/coverage/cover_reg_top/8.uart_intr_test.3040191075 May 19 12:23:18 PM PDT 24 May 19 12:23:25 PM PDT 24 11973786 ps
T1303 /workspace/coverage/cover_reg_top/18.uart_intr_test.1706430777 May 19 12:25:18 PM PDT 24 May 19 12:25:26 PM PDT 24 11683345 ps
T1304 /workspace/coverage/cover_reg_top/19.uart_intr_test.2239701874 May 19 12:25:24 PM PDT 24 May 19 12:25:29 PM PDT 24 42433787 ps
T67 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2842144394 May 19 12:19:29 PM PDT 24 May 19 12:19:30 PM PDT 24 17530798 ps
T1305 /workspace/coverage/cover_reg_top/44.uart_intr_test.1113607256 May 19 12:25:26 PM PDT 24 May 19 12:25:29 PM PDT 24 10961550 ps
T1306 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2423436205 May 19 12:20:44 PM PDT 24 May 19 12:20:46 PM PDT 24 48494517 ps
T68 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1714662675 May 19 12:18:35 PM PDT 24 May 19 12:18:38 PM PDT 24 111356302 ps
T1307 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3519847371 May 19 12:25:09 PM PDT 24 May 19 12:25:19 PM PDT 24 87463690 ps
T1308 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.861476059 May 19 12:25:05 PM PDT 24 May 19 12:25:12 PM PDT 24 17189744 ps
T1309 /workspace/coverage/cover_reg_top/48.uart_intr_test.2712601857 May 19 12:25:12 PM PDT 24 May 19 12:25:20 PM PDT 24 27018617 ps
T1310 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.168257512 May 19 12:25:26 PM PDT 24 May 19 12:25:29 PM PDT 24 54412718 ps
T1311 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3921010403 May 19 12:25:31 PM PDT 24 May 19 12:25:33 PM PDT 24 30314967 ps
T1312 /workspace/coverage/cover_reg_top/7.uart_intr_test.44865528 May 19 12:19:39 PM PDT 24 May 19 12:19:40 PM PDT 24 11049960 ps
T1313 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.489744505 May 19 12:19:41 PM PDT 24 May 19 12:19:43 PM PDT 24 333076298 ps
T1314 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2760230396 May 19 12:19:22 PM PDT 24 May 19 12:19:24 PM PDT 24 599881296 ps
T1315 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3052723114 May 19 12:25:16 PM PDT 24 May 19 12:25:24 PM PDT 24 28507040 ps
T1316 /workspace/coverage/cover_reg_top/33.uart_intr_test.1959106304 May 19 12:25:21 PM PDT 24 May 19 12:25:30 PM PDT 24 29893986 ps
T1317 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.215604902 May 19 12:23:43 PM PDT 24 May 19 12:24:00 PM PDT 24 26061777 ps

Test location /workspace/coverage/default/6.uart_stress_all.67827978
Short name T9
Test name
Test status
Simulation time 276801297590 ps
CPU time 242.23 seconds
Started May 19 12:29:21 PM PDT 24
Finished May 19 12:33:24 PM PDT 24
Peak memory 200324 kb
Host smart-e707ec87-d0b9-4489-808a-b41a7b659502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67827978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.67827978
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.4119335966
Short name T24
Test name
Test status
Simulation time 328119853203 ps
CPU time 804.25 seconds
Started May 19 12:31:09 PM PDT 24
Finished May 19 12:44:35 PM PDT 24
Peak memory 212740 kb
Host smart-7f903fce-d163-4363-87c3-977907d15c49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119335966 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.4119335966
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2039474901
Short name T19
Test name
Test status
Simulation time 217921250492 ps
CPU time 930.5 seconds
Started May 19 12:29:24 PM PDT 24
Finished May 19 12:44:55 PM PDT 24
Peak memory 225352 kb
Host smart-0ef8af08-2b43-4d2b-9bf3-604591f68113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039474901 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2039474901
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all.4265358558
Short name T14
Test name
Test status
Simulation time 561528381967 ps
CPU time 613.06 seconds
Started May 19 12:29:40 PM PDT 24
Finished May 19 12:39:55 PM PDT 24
Peak memory 200228 kb
Host smart-23efc5b8-d132-4867-8cd9-c964c10e11c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265358558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.4265358558
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.4089394368
Short name T31
Test name
Test status
Simulation time 109405584956 ps
CPU time 412.68 seconds
Started May 19 12:31:11 PM PDT 24
Finished May 19 12:38:06 PM PDT 24
Peak memory 216836 kb
Host smart-ca4a5a9f-b5c7-42cf-8e28-cd9b79b2d652
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089394368 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.4089394368
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.4015502686
Short name T36
Test name
Test status
Simulation time 241964130093 ps
CPU time 787.94 seconds
Started May 19 12:30:41 PM PDT 24
Finished May 19 12:43:52 PM PDT 24
Peak memory 216740 kb
Host smart-2627991a-6ac9-44cf-a697-ebfd26d84524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015502686 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.4015502686
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2171218219
Short name T28
Test name
Test status
Simulation time 499835332 ps
CPU time 0.96 seconds
Started May 19 12:29:16 PM PDT 24
Finished May 19 12:29:18 PM PDT 24
Peak memory 219264 kb
Host smart-2f8b6a7b-1024-412f-b4fd-b394f92802d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171218219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2171218219
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/27.uart_stress_all.2211966514
Short name T23
Test name
Test status
Simulation time 468783965641 ps
CPU time 868.4 seconds
Started May 19 12:29:59 PM PDT 24
Finished May 19 12:44:35 PM PDT 24
Peak memory 200728 kb
Host smart-4ac7021e-0d95-4cee-9249-5a9fd16fbe94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211966514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2211966514
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.418859565
Short name T151
Test name
Test status
Simulation time 186700958132 ps
CPU time 471.31 seconds
Started May 19 12:31:12 PM PDT 24
Finished May 19 12:39:05 PM PDT 24
Peak memory 216844 kb
Host smart-a70adc03-c581-45c0-98fd-71eee947e766
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418859565 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.418859565
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3111096605
Short name T34
Test name
Test status
Simulation time 138611921410 ps
CPU time 461.89 seconds
Started May 19 12:31:14 PM PDT 24
Finished May 19 12:38:58 PM PDT 24
Peak memory 225648 kb
Host smart-f4d32150-4396-4f7f-9c4f-a8038f249749
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111096605 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3111096605
Directory /workspace/99.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3867521003
Short name T142
Test name
Test status
Simulation time 281659772458 ps
CPU time 86 seconds
Started May 19 12:29:16 PM PDT 24
Finished May 19 12:30:43 PM PDT 24
Peak memory 200604 kb
Host smart-638e6038-4c67-40ae-99bc-7f45b7181fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867521003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3867521003
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.172902007
Short name T51
Test name
Test status
Simulation time 106753707615 ps
CPU time 788.41 seconds
Started May 19 12:30:47 PM PDT 24
Finished May 19 12:43:57 PM PDT 24
Peak memory 200288 kb
Host smart-d1cbb1b6-7796-47f1-8b53-ccbf3bf15998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172902007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.172902007
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1574147647
Short name T270
Test name
Test status
Simulation time 302625587239 ps
CPU time 767.66 seconds
Started May 19 12:30:06 PM PDT 24
Finished May 19 12:43:00 PM PDT 24
Peak memory 217172 kb
Host smart-d820dab7-21ae-427f-a2e3-a76d64068a1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574147647 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1574147647
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3756279170
Short name T91
Test name
Test status
Simulation time 189729060 ps
CPU time 1.24 seconds
Started May 19 12:23:19 PM PDT 24
Finished May 19 12:23:27 PM PDT 24
Peak memory 198696 kb
Host smart-29213af6-7bf8-494d-b3ef-24827f375f43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756279170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3756279170
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.2176446156
Short name T56
Test name
Test status
Simulation time 219833513812 ps
CPU time 735.69 seconds
Started May 19 12:31:09 PM PDT 24
Finished May 19 12:43:27 PM PDT 24
Peak memory 225244 kb
Host smart-af3fe9d0-ef34-421c-aa48-81ffb38ea088
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176446156 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2176446156
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all.3354691285
Short name T237
Test name
Test status
Simulation time 455245047036 ps
CPU time 258.84 seconds
Started May 19 12:30:42 PM PDT 24
Finished May 19 12:35:05 PM PDT 24
Peak memory 200620 kb
Host smart-48d678f2-eecd-495b-90f9-7fb3a2a2dc0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354691285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3354691285
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_alert_test.2883932454
Short name T26
Test name
Test status
Simulation time 14571779 ps
CPU time 0.54 seconds
Started May 19 12:29:59 PM PDT 24
Finished May 19 12:30:07 PM PDT 24
Peak memory 195696 kb
Host smart-e7a48c6f-2135-4a67-b204-327dfd038244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883932454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2883932454
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_stress_all.2426478017
Short name T283
Test name
Test status
Simulation time 182152741585 ps
CPU time 172.35 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:33:02 PM PDT 24
Peak memory 200152 kb
Host smart-7e12d026-3c47-43a6-bcf7-988a1b364764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426478017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2426478017
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all.495723462
Short name T42
Test name
Test status
Simulation time 265673571168 ps
CPU time 764.7 seconds
Started May 19 12:30:56 PM PDT 24
Finished May 19 12:43:43 PM PDT 24
Peak memory 200368 kb
Host smart-cc606612-150e-4d5e-a1c4-cf9f9d9f5b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495723462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.495723462
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all.3594978746
Short name T262
Test name
Test status
Simulation time 193811130538 ps
CPU time 204.37 seconds
Started May 19 12:29:50 PM PDT 24
Finished May 19 12:33:22 PM PDT 24
Peak memory 199876 kb
Host smart-d8027b51-3b7a-4155-ac3e-61ae0130dc6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594978746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3594978746
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all.707365769
Short name T150
Test name
Test status
Simulation time 528007460568 ps
CPU time 470.87 seconds
Started May 19 12:30:02 PM PDT 24
Finished May 19 12:38:00 PM PDT 24
Peak memory 208892 kb
Host smart-3aee274a-2021-4483-8c4b-981ed9cd601f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707365769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.707365769
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1448225770
Short name T130
Test name
Test status
Simulation time 100610837908 ps
CPU time 43.58 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:40 PM PDT 24
Peak memory 200332 kb
Host smart-d024f467-71dd-42cf-b810-2abc7171e124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448225770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1448225770
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1714662675
Short name T68
Test name
Test status
Simulation time 111356302 ps
CPU time 0.59 seconds
Started May 19 12:18:35 PM PDT 24
Finished May 19 12:18:38 PM PDT 24
Peak memory 195052 kb
Host smart-4f52ffa6-2928-41f8-ae21-f969106dda3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714662675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1714662675
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3745235500
Short name T80
Test name
Test status
Simulation time 334519368 ps
CPU time 0.8 seconds
Started May 19 12:22:04 PM PDT 24
Finished May 19 12:22:06 PM PDT 24
Peak memory 197068 kb
Host smart-18b664b5-2562-4a30-8ca3-9808d31adb6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745235500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3745235500
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1156060036
Short name T33
Test name
Test status
Simulation time 220938613191 ps
CPU time 927.26 seconds
Started May 19 12:31:07 PM PDT 24
Finished May 19 12:46:36 PM PDT 24
Peak memory 216124 kb
Host smart-e24b57e4-df32-4df5-873d-88ab81e81db9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156060036 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1156060036
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.333632192
Short name T728
Test name
Test status
Simulation time 179168408821 ps
CPU time 122.66 seconds
Started May 19 12:31:30 PM PDT 24
Finished May 19 12:33:34 PM PDT 24
Peak memory 200336 kb
Host smart-b81821c8-0898-41d8-8e42-ca420ffb176a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333632192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.333632192
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3556219156
Short name T54
Test name
Test status
Simulation time 227440855885 ps
CPU time 220.8 seconds
Started May 19 12:31:06 PM PDT 24
Finished May 19 12:34:48 PM PDT 24
Peak memory 217056 kb
Host smart-296c469d-20f8-48ed-bae2-45b9069c2740
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556219156 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3556219156
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.654339287
Short name T170
Test name
Test status
Simulation time 105575184108 ps
CPU time 52 seconds
Started May 19 12:31:42 PM PDT 24
Finished May 19 12:32:35 PM PDT 24
Peak memory 200276 kb
Host smart-8d04b8d2-4f0f-42fd-b32b-10c762120fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654339287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.654339287
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2348764374
Short name T191
Test name
Test status
Simulation time 161010787434 ps
CPU time 250.14 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:34:08 PM PDT 24
Peak memory 200248 kb
Host smart-b69accda-f919-40b7-88bf-3b96a3e516f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348764374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2348764374
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1712468299
Short name T182
Test name
Test status
Simulation time 243208514882 ps
CPU time 500.71 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:39:44 PM PDT 24
Peak memory 200288 kb
Host smart-42c9904a-0f2d-4557-b5c6-35a017a2d753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712468299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1712468299
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_stress_all.3174545655
Short name T163
Test name
Test status
Simulation time 291234226624 ps
CPU time 361.02 seconds
Started May 19 12:29:31 PM PDT 24
Finished May 19 12:35:34 PM PDT 24
Peak memory 200180 kb
Host smart-81a11d84-71bd-4f28-9e11-439962771914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174545655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3174545655
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4041087226
Short name T89
Test name
Test status
Simulation time 82774421 ps
CPU time 1 seconds
Started May 19 12:25:17 PM PDT 24
Finished May 19 12:25:25 PM PDT 24
Peak memory 198792 kb
Host smart-350aa084-995c-43a7-87b2-326d02b19e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041087226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.4041087226
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.387910041
Short name T176
Test name
Test status
Simulation time 10151320094 ps
CPU time 9.08 seconds
Started May 19 12:31:27 PM PDT 24
Finished May 19 12:31:37 PM PDT 24
Peak memory 200228 kb
Host smart-efc6783a-7373-4da0-83f4-edc87e85fc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387910041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.387910041
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all.1305696948
Short name T102
Test name
Test status
Simulation time 369716360888 ps
CPU time 248.97 seconds
Started May 19 12:29:45 PM PDT 24
Finished May 19 12:33:58 PM PDT 24
Peak memory 216320 kb
Host smart-8fb496c0-3c83-4878-8419-ce0b4360271a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305696948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1305696948
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.795969223
Short name T155
Test name
Test status
Simulation time 178516870314 ps
CPU time 106.38 seconds
Started May 19 12:28:53 PM PDT 24
Finished May 19 12:30:40 PM PDT 24
Peak memory 200284 kb
Host smart-adb3952f-fbfb-4982-803a-3a57d38d7a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795969223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.795969223
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1142755295
Short name T147
Test name
Test status
Simulation time 146437548797 ps
CPU time 30.62 seconds
Started May 19 12:31:36 PM PDT 24
Finished May 19 12:32:07 PM PDT 24
Peak memory 200288 kb
Host smart-354e8ce1-c8ab-45f6-b8b7-7432d37072f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142755295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1142755295
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2631605917
Short name T35
Test name
Test status
Simulation time 130950695748 ps
CPU time 324.12 seconds
Started May 19 12:30:55 PM PDT 24
Finished May 19 12:36:20 PM PDT 24
Peak memory 216648 kb
Host smart-bdf43c2b-2294-4c8e-8e81-d581b28f832c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631605917 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2631605917
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3985425593
Short name T808
Test name
Test status
Simulation time 79104807679 ps
CPU time 37.22 seconds
Started May 19 12:29:45 PM PDT 24
Finished May 19 12:30:25 PM PDT 24
Peak memory 200328 kb
Host smart-f0d5dd5a-a18d-432e-8777-c3299e295c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985425593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3985425593
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3312016139
Short name T276
Test name
Test status
Simulation time 83571957047 ps
CPU time 75.77 seconds
Started May 19 12:29:42 PM PDT 24
Finished May 19 12:30:59 PM PDT 24
Peak memory 199964 kb
Host smart-2c392411-31ad-42bd-b99d-1b5782331016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312016139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3312016139
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.982109308
Short name T152
Test name
Test status
Simulation time 31398820877 ps
CPU time 25.91 seconds
Started May 19 12:31:49 PM PDT 24
Finished May 19 12:32:17 PM PDT 24
Peak memory 200360 kb
Host smart-9f54afe8-4447-4b8e-a45d-27f74663e3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982109308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.982109308
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3861445870
Short name T139
Test name
Test status
Simulation time 100391897966 ps
CPU time 40.53 seconds
Started May 19 12:31:50 PM PDT 24
Finished May 19 12:32:32 PM PDT 24
Peak memory 200232 kb
Host smart-e88744c2-7ad5-4f5b-a260-fbbc66b86578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861445870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3861445870
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_perf.1229103031
Short name T254
Test name
Test status
Simulation time 17381373006 ps
CPU time 877.81 seconds
Started May 19 12:29:16 PM PDT 24
Finished May 19 12:43:55 PM PDT 24
Peak memory 200232 kb
Host smart-57632bcf-9fc4-45cc-858b-c60f95740817
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1229103031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1229103031
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1490688962
Short name T168
Test name
Test status
Simulation time 135329036900 ps
CPU time 15.97 seconds
Started May 19 12:29:34 PM PDT 24
Finished May 19 12:29:53 PM PDT 24
Peak memory 200300 kb
Host smart-fa8f25d6-f1d1-4537-8c53-981cc832707a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490688962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1490688962
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3540269846
Short name T134
Test name
Test status
Simulation time 15830376574 ps
CPU time 30.6 seconds
Started May 19 12:31:33 PM PDT 24
Finished May 19 12:32:05 PM PDT 24
Peak memory 200240 kb
Host smart-01eadd91-6957-4fab-b0b9-1ce6aea35491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540269846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3540269846
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2092367557
Short name T308
Test name
Test status
Simulation time 23607524443 ps
CPU time 56.73 seconds
Started May 19 12:31:16 PM PDT 24
Finished May 19 12:32:13 PM PDT 24
Peak memory 200236 kb
Host smart-54811380-9aa8-44fc-97fa-2b6e0e00f31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092367557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2092367557
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1090359466
Short name T247
Test name
Test status
Simulation time 41120040373 ps
CPU time 63.2 seconds
Started May 19 12:31:22 PM PDT 24
Finished May 19 12:32:27 PM PDT 24
Peak memory 200340 kb
Host smart-8dc2c10f-a134-4cba-b6d5-7e02a991873e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090359466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1090359466
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.30520161
Short name T228
Test name
Test status
Simulation time 130686031461 ps
CPU time 124.21 seconds
Started May 19 12:31:19 PM PDT 24
Finished May 19 12:33:24 PM PDT 24
Peak memory 200312 kb
Host smart-1e2a1001-a053-4b3c-9cec-2a537fcead1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30520161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.30520161
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.1015791390
Short name T115
Test name
Test status
Simulation time 311823871095 ps
CPU time 771.25 seconds
Started May 19 12:29:44 PM PDT 24
Finished May 19 12:42:37 PM PDT 24
Peak memory 200292 kb
Host smart-d74dbb7a-ee33-4079-adfc-7fccdec44517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015791390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1015791390
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3769299566
Short name T148
Test name
Test status
Simulation time 40050007652 ps
CPU time 19.79 seconds
Started May 19 12:31:24 PM PDT 24
Finished May 19 12:31:45 PM PDT 24
Peak memory 200220 kb
Host smart-95417ad7-644a-4ab5-a80e-bf4161a81a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769299566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3769299566
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1892804228
Short name T244
Test name
Test status
Simulation time 253400191875 ps
CPU time 726.88 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:42:03 PM PDT 24
Peak memory 225596 kb
Host smart-e56d702e-66e2-411e-84a6-b467049dfdf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892804228 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1892804228
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2177806238
Short name T199
Test name
Test status
Simulation time 44931727466 ps
CPU time 20.26 seconds
Started May 19 12:31:30 PM PDT 24
Finished May 19 12:31:51 PM PDT 24
Peak memory 200352 kb
Host smart-4ea98375-f613-474a-b7ff-258086d1be73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177806238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2177806238
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1258342655
Short name T202
Test name
Test status
Simulation time 185973992215 ps
CPU time 70.51 seconds
Started May 19 12:31:34 PM PDT 24
Finished May 19 12:32:46 PM PDT 24
Peak memory 200280 kb
Host smart-4f643d2d-25c6-49e5-8a53-62d58dc911f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258342655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1258342655
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3798558593
Short name T223
Test name
Test status
Simulation time 439411498506 ps
CPU time 44.88 seconds
Started May 19 12:29:10 PM PDT 24
Finished May 19 12:29:55 PM PDT 24
Peak memory 200180 kb
Host smart-22636c1f-a855-45ed-b228-d0609df4831d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798558593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3798558593
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1931393234
Short name T197
Test name
Test status
Simulation time 42735293501 ps
CPU time 28.79 seconds
Started May 19 12:31:13 PM PDT 24
Finished May 19 12:31:44 PM PDT 24
Peak memory 200232 kb
Host smart-2917f7cc-9af1-40da-986c-045abd9a86e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931393234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1931393234
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.956718792
Short name T121
Test name
Test status
Simulation time 26328528728 ps
CPU time 11.91 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:58 PM PDT 24
Peak memory 199880 kb
Host smart-5e079b16-345d-4636-b99b-abc8b841c920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956718792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.956718792
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1435741989
Short name T212
Test name
Test status
Simulation time 94625030897 ps
CPU time 46.52 seconds
Started May 19 12:23:33 PM PDT 24
Finished May 19 12:24:40 PM PDT 24
Peak memory 199988 kb
Host smart-ac6a91ff-63e2-4e4a-9610-2eb4bb82aecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435741989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1435741989
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.565708384
Short name T48
Test name
Test status
Simulation time 2723834237 ps
CPU time 10.25 seconds
Started May 19 12:23:29 PM PDT 24
Finished May 19 12:23:59 PM PDT 24
Peak memory 199140 kb
Host smart-be5febc2-1023-40f2-9566-dda142f3107e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=565708384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.565708384
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1489608590
Short name T124
Test name
Test status
Simulation time 13860968507 ps
CPU time 6 seconds
Started May 19 12:31:19 PM PDT 24
Finished May 19 12:31:26 PM PDT 24
Peak memory 200232 kb
Host smart-f68ab584-d605-429b-99e2-3ad44f3366ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489608590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1489608590
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3800654871
Short name T549
Test name
Test status
Simulation time 31145135706 ps
CPU time 347.12 seconds
Started May 19 12:29:35 PM PDT 24
Finished May 19 12:35:25 PM PDT 24
Peak memory 216176 kb
Host smart-60b5ee6c-5851-479a-b28e-5008e94a7b19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800654871 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3800654871
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.462954411
Short name T239
Test name
Test status
Simulation time 48838887642 ps
CPU time 22.22 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:31:46 PM PDT 24
Peak memory 200320 kb
Host smart-38008cc8-8779-4949-bd96-9f9a2ecbe3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462954411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.462954411
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2933414476
Short name T939
Test name
Test status
Simulation time 62579434065 ps
CPU time 28.32 seconds
Started May 19 12:31:15 PM PDT 24
Finished May 19 12:31:45 PM PDT 24
Peak memory 200236 kb
Host smart-a18719c5-bfb8-48a2-93d4-e479aec7fbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933414476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2933414476
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2815255068
Short name T153
Test name
Test status
Simulation time 104338208018 ps
CPU time 28.18 seconds
Started May 19 12:31:19 PM PDT 24
Finished May 19 12:31:48 PM PDT 24
Peak memory 200372 kb
Host smart-e4daa037-858c-489f-99be-7d228ee84250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815255068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2815255068
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1425387616
Short name T220
Test name
Test status
Simulation time 51859794019 ps
CPU time 29.72 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:31:53 PM PDT 24
Peak memory 200316 kb
Host smart-c5d221bc-3bcf-4614-9cd6-d01deba339c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425387616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1425387616
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.4270249976
Short name T179
Test name
Test status
Simulation time 168611735440 ps
CPU time 81.49 seconds
Started May 19 12:31:18 PM PDT 24
Finished May 19 12:32:40 PM PDT 24
Peak memory 200288 kb
Host smart-9ade1f28-7e49-4847-98cc-7c5c48ee3ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270249976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.4270249976
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.195147656
Short name T217
Test name
Test status
Simulation time 25846514415 ps
CPU time 6.9 seconds
Started May 19 12:31:29 PM PDT 24
Finished May 19 12:31:37 PM PDT 24
Peak memory 200300 kb
Host smart-e2057d3a-2806-4e3b-9e6b-658ba3a3a318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195147656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.195147656
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3446839130
Short name T161
Test name
Test status
Simulation time 74929459320 ps
CPU time 159.69 seconds
Started May 19 12:31:35 PM PDT 24
Finished May 19 12:34:16 PM PDT 24
Peak memory 200272 kb
Host smart-0278e77a-76da-4f55-bdb0-0dbd6c0014a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446839130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3446839130
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.287675328
Short name T156
Test name
Test status
Simulation time 119930203770 ps
CPU time 256.39 seconds
Started May 19 12:29:51 PM PDT 24
Finished May 19 12:34:15 PM PDT 24
Peak memory 200344 kb
Host smart-bd4ac718-c891-4951-9620-ac3a1ac3700e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287675328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.287675328
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3927727222
Short name T230
Test name
Test status
Simulation time 24248126715 ps
CPU time 36.64 seconds
Started May 19 12:31:48 PM PDT 24
Finished May 19 12:32:27 PM PDT 24
Peak memory 200272 kb
Host smart-68387795-ebaf-4c82-ae7d-f804652afcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927727222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3927727222
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3319269023
Short name T235
Test name
Test status
Simulation time 46266502385 ps
CPU time 18.9 seconds
Started May 19 12:31:47 PM PDT 24
Finished May 19 12:32:08 PM PDT 24
Peak memory 200312 kb
Host smart-fe9ed951-51e8-49c5-93ba-c0f08f0b7b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319269023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3319269023
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.327684337
Short name T112
Test name
Test status
Simulation time 26384005540 ps
CPU time 15.08 seconds
Started May 19 12:31:47 PM PDT 24
Finished May 19 12:32:05 PM PDT 24
Peak memory 200352 kb
Host smart-403099a0-0eba-432f-9e91-892b5f3df595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327684337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.327684337
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.364682912
Short name T242
Test name
Test status
Simulation time 101593308564 ps
CPU time 35.33 seconds
Started May 19 12:31:57 PM PDT 24
Finished May 19 12:32:33 PM PDT 24
Peak memory 200316 kb
Host smart-bb89bac9-e88c-403e-a413-32bc9584eba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364682912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.364682912
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.4285137573
Short name T221
Test name
Test status
Simulation time 22473873374 ps
CPU time 38.29 seconds
Started May 19 12:31:10 PM PDT 24
Finished May 19 12:31:50 PM PDT 24
Peak memory 200280 kb
Host smart-3feee1eb-44ac-4830-849f-63b44f55e381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285137573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.4285137573
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3657466475
Short name T135
Test name
Test status
Simulation time 218460727891 ps
CPU time 79.34 seconds
Started May 19 12:31:03 PM PDT 24
Finished May 19 12:32:23 PM PDT 24
Peak memory 200320 kb
Host smart-a1e7ee08-32e1-4f6f-9610-b22589a89e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657466475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3657466475
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2942518571
Short name T236
Test name
Test status
Simulation time 145494843825 ps
CPU time 105.94 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:33:09 PM PDT 24
Peak memory 200284 kb
Host smart-fdb79741-6e56-4b53-bc82-e465266aafa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942518571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2942518571
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3208161039
Short name T1197
Test name
Test status
Simulation time 26300671 ps
CPU time 0.7 seconds
Started May 19 12:21:30 PM PDT 24
Finished May 19 12:21:32 PM PDT 24
Peak memory 195212 kb
Host smart-e794e717-74d4-4b7a-a2f8-7cb0886b299a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208161039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3208161039
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.532134827
Short name T1301
Test name
Test status
Simulation time 92980774 ps
CPU time 1.49 seconds
Started May 19 12:18:35 PM PDT 24
Finished May 19 12:18:39 PM PDT 24
Peak memory 197340 kb
Host smart-78593853-976d-48d7-bc20-4d00a915a5e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532134827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.532134827
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.157143570
Short name T1274
Test name
Test status
Simulation time 53947491 ps
CPU time 0.93 seconds
Started May 19 12:23:56 PM PDT 24
Finished May 19 12:24:06 PM PDT 24
Peak memory 199120 kb
Host smart-a4492e8a-5558-4541-9bb6-8d295a416bc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157143570 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.157143570
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3326666117
Short name T1237
Test name
Test status
Simulation time 13299834 ps
CPU time 0.56 seconds
Started May 19 12:23:28 PM PDT 24
Finished May 19 12:23:49 PM PDT 24
Peak memory 194840 kb
Host smart-01f8126e-6103-44ed-860a-1c4b5d60fd9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326666117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3326666117
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2932897122
Short name T1228
Test name
Test status
Simulation time 25389405 ps
CPU time 0.64 seconds
Started May 19 12:23:24 PM PDT 24
Finished May 19 12:23:40 PM PDT 24
Peak memory 193288 kb
Host smart-e527c092-65b0-455a-872c-cd9e65a1f56b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932897122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2932897122
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.427863489
Short name T1254
Test name
Test status
Simulation time 74412293 ps
CPU time 0.74 seconds
Started May 19 12:18:48 PM PDT 24
Finished May 19 12:18:50 PM PDT 24
Peak memory 197256 kb
Host smart-ca21eb81-5fee-4184-ac40-9a44df146bd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427863489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.427863489
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.587373893
Short name T1299
Test name
Test status
Simulation time 61740814 ps
CPU time 1.58 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:48 PM PDT 24
Peak memory 198908 kb
Host smart-015360d1-8d25-4be9-b770-3c2bab66e395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587373893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.587373893
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2422585682
Short name T92
Test name
Test status
Simulation time 190719712 ps
CPU time 0.98 seconds
Started May 19 12:23:36 PM PDT 24
Finished May 19 12:23:57 PM PDT 24
Peak memory 198500 kb
Host smart-50031394-50da-4912-8f04-113fb9050954
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422585682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2422585682
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.700261616
Short name T73
Test name
Test status
Simulation time 34386905 ps
CPU time 0.66 seconds
Started May 19 12:18:58 PM PDT 24
Finished May 19 12:19:00 PM PDT 24
Peak memory 194932 kb
Host smart-dc54aac1-0808-41c2-9f35-55a32332e243
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700261616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.700261616
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3684557568
Short name T1293
Test name
Test status
Simulation time 181850039 ps
CPU time 2.49 seconds
Started May 19 12:18:41 PM PDT 24
Finished May 19 12:18:44 PM PDT 24
Peak memory 197328 kb
Host smart-13356ca0-eb02-4dc7-88bd-7747598d780a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684557568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3684557568
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.246485487
Short name T1222
Test name
Test status
Simulation time 13214181 ps
CPU time 0.64 seconds
Started May 19 12:18:19 PM PDT 24
Finished May 19 12:18:21 PM PDT 24
Peak memory 195068 kb
Host smart-18a8097f-758e-405e-92b3-4c3772909822
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246485487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.246485487
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.489744505
Short name T1313
Test name
Test status
Simulation time 333076298 ps
CPU time 1.41 seconds
Started May 19 12:19:41 PM PDT 24
Finished May 19 12:19:43 PM PDT 24
Peak memory 199756 kb
Host smart-eb300cb7-a2ed-4503-9ce5-4aec06e39b5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489744505 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.489744505
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.58560292
Short name T1284
Test name
Test status
Simulation time 48665163 ps
CPU time 0.57 seconds
Started May 19 12:23:56 PM PDT 24
Finished May 19 12:24:06 PM PDT 24
Peak memory 194640 kb
Host smart-30bbe799-6ed9-4081-abd3-ca2a51848bfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58560292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.58560292
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1780610178
Short name T1262
Test name
Test status
Simulation time 13656990 ps
CPU time 0.6 seconds
Started May 19 12:18:59 PM PDT 24
Finished May 19 12:19:01 PM PDT 24
Peak memory 194484 kb
Host smart-938e4481-ab97-45b7-957c-517b49270be8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780610178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1780610178
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3510971388
Short name T1236
Test name
Test status
Simulation time 44153912 ps
CPU time 2.03 seconds
Started May 19 12:19:09 PM PDT 24
Finished May 19 12:19:14 PM PDT 24
Peak memory 199740 kb
Host smart-87c985f2-4084-4470-a9b1-f93f5029e407
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510971388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3510971388
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3122831422
Short name T1288
Test name
Test status
Simulation time 46020877 ps
CPU time 0.96 seconds
Started May 19 12:21:21 PM PDT 24
Finished May 19 12:21:23 PM PDT 24
Peak memory 198512 kb
Host smart-9c12fada-623d-40e0-a1d3-537838e770ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122831422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3122831422
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.276557232
Short name T1205
Test name
Test status
Simulation time 31413122 ps
CPU time 0.81 seconds
Started May 19 12:25:07 PM PDT 24
Finished May 19 12:25:15 PM PDT 24
Peak memory 199972 kb
Host smart-3deb404f-c5bc-4cac-b658-634180d444dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276557232 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.276557232
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2842144394
Short name T67
Test name
Test status
Simulation time 17530798 ps
CPU time 0.63 seconds
Started May 19 12:19:29 PM PDT 24
Finished May 19 12:19:30 PM PDT 24
Peak memory 195260 kb
Host smart-1955b407-d512-47b8-9057-43b64cfa6439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842144394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2842144394
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.227834016
Short name T1238
Test name
Test status
Simulation time 20355606 ps
CPU time 0.54 seconds
Started May 19 12:23:38 PM PDT 24
Finished May 19 12:23:57 PM PDT 24
Peak memory 193696 kb
Host smart-d18a97a9-f254-4eae-8b76-528ff53c7663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227834016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.227834016
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3291367384
Short name T1273
Test name
Test status
Simulation time 23807176 ps
CPU time 0.64 seconds
Started May 19 12:20:53 PM PDT 24
Finished May 19 12:20:55 PM PDT 24
Peak memory 195288 kb
Host smart-be8ccdec-2585-4c5d-bd25-d68a1e057622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291367384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3291367384
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3241712396
Short name T1276
Test name
Test status
Simulation time 42345944 ps
CPU time 2.12 seconds
Started May 19 12:21:19 PM PDT 24
Finished May 19 12:21:23 PM PDT 24
Peak memory 200120 kb
Host smart-f8845514-9c27-46d9-85e0-db43571de872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241712396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3241712396
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.46110284
Short name T86
Test name
Test status
Simulation time 165837699 ps
CPU time 0.87 seconds
Started May 19 12:23:38 PM PDT 24
Finished May 19 12:23:58 PM PDT 24
Peak memory 198108 kb
Host smart-1640f199-813e-489a-a5dd-777ae85409b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46110284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.46110284
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.930425141
Short name T1203
Test name
Test status
Simulation time 224529702 ps
CPU time 1.15 seconds
Started May 19 12:25:07 PM PDT 24
Finished May 19 12:25:15 PM PDT 24
Peak memory 199732 kb
Host smart-4d9cb9d6-d52b-4fdf-86c3-62521b08d415
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930425141 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.930425141
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3601418928
Short name T1250
Test name
Test status
Simulation time 22216102 ps
CPU time 0.56 seconds
Started May 19 12:25:14 PM PDT 24
Finished May 19 12:25:23 PM PDT 24
Peak memory 195028 kb
Host smart-6e269e5a-6ebb-4fcf-b9ca-70052fa78588
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601418928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3601418928
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2218530518
Short name T1207
Test name
Test status
Simulation time 13130720 ps
CPU time 0.56 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:31 PM PDT 24
Peak memory 194040 kb
Host smart-08ed88b4-e3a2-4d40-b200-7faeff5ac5d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218530518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2218530518
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1911711039
Short name T1287
Test name
Test status
Simulation time 60144266 ps
CPU time 0.65 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:24 PM PDT 24
Peak memory 195504 kb
Host smart-7c33e4de-1291-46f2-8db2-053364e30284
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911711039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1911711039
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3493642214
Short name T1229
Test name
Test status
Simulation time 51718131 ps
CPU time 1.32 seconds
Started May 19 12:25:13 PM PDT 24
Finished May 19 12:25:23 PM PDT 24
Peak memory 199736 kb
Host smart-bcc52d12-8b37-4312-98ad-fc46059494da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493642214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3493642214
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.100126159
Short name T1218
Test name
Test status
Simulation time 41183327 ps
CPU time 0.76 seconds
Started May 19 12:25:19 PM PDT 24
Finished May 19 12:25:26 PM PDT 24
Peak memory 197780 kb
Host smart-38234c24-13f4-4802-906a-cff05bed701b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100126159 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.100126159
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.286215146
Short name T1252
Test name
Test status
Simulation time 16956537 ps
CPU time 0.62 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 195140 kb
Host smart-88b87c23-c3d5-4fc6-8d26-0df391becce6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286215146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.286215146
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3090878931
Short name T1202
Test name
Test status
Simulation time 21395229 ps
CPU time 0.57 seconds
Started May 19 12:25:27 PM PDT 24
Finished May 19 12:25:30 PM PDT 24
Peak memory 194528 kb
Host smart-894bc717-60d6-4a54-a862-c8478a28c534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090878931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3090878931
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.861476059
Short name T1308
Test name
Test status
Simulation time 17189744 ps
CPU time 0.62 seconds
Started May 19 12:25:05 PM PDT 24
Finished May 19 12:25:12 PM PDT 24
Peak memory 195248 kb
Host smart-b6e375d7-de06-4e24-b877-40cb4fdf5b7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861476059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr
_outstanding.861476059
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.4097888116
Short name T1264
Test name
Test status
Simulation time 120079882 ps
CPU time 1.46 seconds
Started May 19 12:25:17 PM PDT 24
Finished May 19 12:25:26 PM PDT 24
Peak memory 199740 kb
Host smart-2067b091-719a-455d-a856-a670d52bb281
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097888116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.4097888116
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.404028418
Short name T94
Test name
Test status
Simulation time 433527274 ps
CPU time 1.28 seconds
Started May 19 12:25:10 PM PDT 24
Finished May 19 12:25:19 PM PDT 24
Peak memory 199060 kb
Host smart-2306ac7d-3839-432c-9e07-54c88ecffe89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404028418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.404028418
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.168257512
Short name T1310
Test name
Test status
Simulation time 54412718 ps
CPU time 0.66 seconds
Started May 19 12:25:26 PM PDT 24
Finished May 19 12:25:29 PM PDT 24
Peak memory 197692 kb
Host smart-8f97f769-f8b4-4023-acbe-86ec9a0ef2bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168257512 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.168257512
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1821055834
Short name T82
Test name
Test status
Simulation time 26667700 ps
CPU time 0.56 seconds
Started May 19 12:25:42 PM PDT 24
Finished May 19 12:25:43 PM PDT 24
Peak memory 194996 kb
Host smart-1408718a-c384-40b1-8d8f-332c02fa9487
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821055834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1821055834
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.4159240678
Short name T1224
Test name
Test status
Simulation time 11845142 ps
CPU time 0.59 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:24 PM PDT 24
Peak memory 193968 kb
Host smart-1285db9f-5136-461f-978d-eca0bdee31fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159240678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.4159240678
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3742804385
Short name T1294
Test name
Test status
Simulation time 22175058 ps
CPU time 0.63 seconds
Started May 19 12:25:17 PM PDT 24
Finished May 19 12:25:25 PM PDT 24
Peak memory 195060 kb
Host smart-735f6364-9b61-45e0-9780-d73cb2b99da7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742804385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3742804385
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3519847371
Short name T1307
Test name
Test status
Simulation time 87463690 ps
CPU time 1.74 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:25:19 PM PDT 24
Peak memory 199704 kb
Host smart-fb21c8e6-f638-4673-994c-5a03bf12dff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519847371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3519847371
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1708159271
Short name T87
Test name
Test status
Simulation time 160633582 ps
CPU time 0.87 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 198372 kb
Host smart-9091d096-7bef-4e50-890b-1f3d3c552b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708159271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1708159271
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.744491167
Short name T1246
Test name
Test status
Simulation time 26743695 ps
CPU time 0.71 seconds
Started May 19 12:25:08 PM PDT 24
Finished May 19 12:25:17 PM PDT 24
Peak memory 198296 kb
Host smart-594750d7-7809-43c0-86db-8016d85def76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744491167 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.744491167
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.4121344763
Short name T1200
Test name
Test status
Simulation time 39981122 ps
CPU time 0.58 seconds
Started May 19 12:25:20 PM PDT 24
Finished May 19 12:25:27 PM PDT 24
Peak memory 195164 kb
Host smart-877c955f-e38c-4ea5-b532-e7bdfec62ca1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121344763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.4121344763
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.828468633
Short name T1206
Test name
Test status
Simulation time 43011557 ps
CPU time 0.54 seconds
Started May 19 12:25:07 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 194020 kb
Host smart-1824356c-8791-4d3c-b1e4-9475213dd5e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828468633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.828468633
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1673231681
Short name T1227
Test name
Test status
Simulation time 36282685 ps
CPU time 0.63 seconds
Started May 19 12:25:01 PM PDT 24
Finished May 19 12:25:06 PM PDT 24
Peak memory 194520 kb
Host smart-c56ce37a-3141-4346-9aa4-70259a7dd05b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673231681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1673231681
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1640545033
Short name T1188
Test name
Test status
Simulation time 105816294 ps
CPU time 2.02 seconds
Started May 19 12:25:18 PM PDT 24
Finished May 19 12:25:27 PM PDT 24
Peak memory 199836 kb
Host smart-39a11653-59eb-41f3-be10-6339bdaaa1f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640545033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1640545033
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.395937182
Short name T85
Test name
Test status
Simulation time 107965346 ps
CPU time 1.26 seconds
Started May 19 12:25:08 PM PDT 24
Finished May 19 12:25:17 PM PDT 24
Peak memory 198936 kb
Host smart-5152015d-2e98-457d-be01-4b68ff489f67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395937182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.395937182
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2609219855
Short name T1184
Test name
Test status
Simulation time 87395205 ps
CPU time 1.09 seconds
Started May 19 12:25:07 PM PDT 24
Finished May 19 12:25:15 PM PDT 24
Peak memory 199768 kb
Host smart-a7963d66-28dc-4c84-85d7-2287f8cdb22d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609219855 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2609219855
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3180598977
Short name T1289
Test name
Test status
Simulation time 54028905 ps
CPU time 0.6 seconds
Started May 19 12:25:48 PM PDT 24
Finished May 19 12:25:50 PM PDT 24
Peak memory 195076 kb
Host smart-60272b99-d87f-429a-993f-6fe07b142109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180598977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3180598977
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2324389814
Short name T1217
Test name
Test status
Simulation time 40646859 ps
CPU time 0.55 seconds
Started May 19 12:25:10 PM PDT 24
Finished May 19 12:25:18 PM PDT 24
Peak memory 193964 kb
Host smart-425f1a06-c0ec-423e-a2e1-c6923d4b4fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324389814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2324389814
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3814358088
Short name T1243
Test name
Test status
Simulation time 14969460 ps
CPU time 0.68 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:25:17 PM PDT 24
Peak memory 196516 kb
Host smart-43101f19-42a6-4b16-97b9-0bf5338e74fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814358088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3814358088
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2792843140
Short name T1220
Test name
Test status
Simulation time 107780376 ps
CPU time 1.21 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 199712 kb
Host smart-661bbbeb-9633-4dba-b1da-ce69b5ee4b32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792843140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2792843140
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3195139476
Short name T119
Test name
Test status
Simulation time 165067217 ps
CPU time 0.89 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:24 PM PDT 24
Peak memory 198500 kb
Host smart-efbab2f0-64d6-4784-a5db-224cbf93aa6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195139476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3195139476
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1226083325
Short name T1191
Test name
Test status
Simulation time 24223847 ps
CPU time 0.75 seconds
Started May 19 12:25:22 PM PDT 24
Finished May 19 12:25:28 PM PDT 24
Peak memory 197656 kb
Host smart-da23ba62-1811-4f32-b514-6af1d62d6834
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226083325 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1226083325
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3052723114
Short name T1315
Test name
Test status
Simulation time 28507040 ps
CPU time 0.58 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:24 PM PDT 24
Peak memory 195024 kb
Host smart-86e7ba26-e0ca-4f48-8504-fb386aaa6640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052723114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3052723114
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1241972208
Short name T1211
Test name
Test status
Simulation time 15812761 ps
CPU time 0.56 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:25:17 PM PDT 24
Peak memory 194056 kb
Host smart-0f839c4b-2d08-4eef-9427-87a827f5bbb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241972208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1241972208
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.130235817
Short name T81
Test name
Test status
Simulation time 21266719 ps
CPU time 0.61 seconds
Started May 19 12:25:18 PM PDT 24
Finished May 19 12:25:26 PM PDT 24
Peak memory 194188 kb
Host smart-d70dee60-465b-4f35-a94c-03a62bf7d592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130235817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.130235817
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1855269195
Short name T1185
Test name
Test status
Simulation time 71992831 ps
CPU time 1.34 seconds
Started May 19 12:25:08 PM PDT 24
Finished May 19 12:25:17 PM PDT 24
Peak memory 199680 kb
Host smart-77458425-cc65-4eaf-b096-34024292dc4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855269195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1855269195
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1895913935
Short name T90
Test name
Test status
Simulation time 87367065 ps
CPU time 1.2 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:25 PM PDT 24
Peak memory 198732 kb
Host smart-cfb2d877-99be-4e0d-8b61-450bfee0375c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895913935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1895913935
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3921010403
Short name T1311
Test name
Test status
Simulation time 30314967 ps
CPU time 0.8 seconds
Started May 19 12:25:31 PM PDT 24
Finished May 19 12:25:33 PM PDT 24
Peak memory 199516 kb
Host smart-79a754bf-3b58-4e18-be64-c464bcfe9e15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921010403 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3921010403
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3710722233
Short name T1210
Test name
Test status
Simulation time 27688805 ps
CPU time 0.58 seconds
Started May 19 12:25:26 PM PDT 24
Finished May 19 12:25:30 PM PDT 24
Peak memory 195160 kb
Host smart-23c15163-49a3-4f2e-b799-c81d7b07291f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710722233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3710722233
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.4059084352
Short name T1190
Test name
Test status
Simulation time 42800643 ps
CPU time 0.59 seconds
Started May 19 12:25:07 PM PDT 24
Finished May 19 12:25:15 PM PDT 24
Peak memory 194416 kb
Host smart-c8af1982-adc1-4c75-919a-8b2c9e973cc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059084352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.4059084352
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2684017473
Short name T1221
Test name
Test status
Simulation time 27232713 ps
CPU time 0.72 seconds
Started May 19 12:25:12 PM PDT 24
Finished May 19 12:25:21 PM PDT 24
Peak memory 196604 kb
Host smart-1bdf9ae7-9ec1-4dfa-aa05-fc021bf129b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684017473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2684017473
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.703211320
Short name T1270
Test name
Test status
Simulation time 101511859 ps
CPU time 1.25 seconds
Started May 19 12:25:15 PM PDT 24
Finished May 19 12:25:24 PM PDT 24
Peak memory 199680 kb
Host smart-fcc92b7c-15d4-4be8-b6c0-3054feab76b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703211320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.703211320
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.722005401
Short name T1271
Test name
Test status
Simulation time 52793483 ps
CPU time 0.93 seconds
Started May 19 12:25:13 PM PDT 24
Finished May 19 12:25:23 PM PDT 24
Peak memory 198676 kb
Host smart-0aca635c-a075-4daf-b225-a55aa76bf9d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722005401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.722005401
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3897093548
Short name T1192
Test name
Test status
Simulation time 91120862 ps
CPU time 1.2 seconds
Started May 19 12:25:20 PM PDT 24
Finished May 19 12:25:27 PM PDT 24
Peak memory 199760 kb
Host smart-348b414b-eacc-40d3-9413-11bab31a5eab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897093548 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3897093548
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.4206628404
Short name T66
Test name
Test status
Simulation time 31214729 ps
CPU time 0.61 seconds
Started May 19 12:25:38 PM PDT 24
Finished May 19 12:25:39 PM PDT 24
Peak memory 195140 kb
Host smart-901b4770-000f-4868-b299-d86147d4b1a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206628404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.4206628404
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1706430777
Short name T1303
Test name
Test status
Simulation time 11683345 ps
CPU time 0.56 seconds
Started May 19 12:25:18 PM PDT 24
Finished May 19 12:25:26 PM PDT 24
Peak memory 193968 kb
Host smart-b58a24ae-81ae-45b1-96aa-ac0894b05d85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706430777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1706430777
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2636064480
Short name T78
Test name
Test status
Simulation time 35161697 ps
CPU time 0.76 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:24 PM PDT 24
Peak memory 196716 kb
Host smart-ebb00204-e19d-4f24-b6bb-9c2e2fcb5511
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636064480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2636064480
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.797218521
Short name T1298
Test name
Test status
Simulation time 47477447 ps
CPU time 2.34 seconds
Started May 19 12:25:35 PM PDT 24
Finished May 19 12:25:38 PM PDT 24
Peak memory 199720 kb
Host smart-7ad3c3a7-c4b8-4b70-95fd-959a0c6c66bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797218521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.797218521
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3952275161
Short name T1226
Test name
Test status
Simulation time 62485223 ps
CPU time 0.93 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 198132 kb
Host smart-ca944a91-b72e-426d-bbf9-2a6902a60b1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952275161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3952275161
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3220644222
Short name T1255
Test name
Test status
Simulation time 21411853 ps
CPU time 0.71 seconds
Started May 19 12:25:17 PM PDT 24
Finished May 19 12:25:25 PM PDT 24
Peak memory 198496 kb
Host smart-74e619da-5a41-4547-9d52-9d0fc78fe49d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220644222 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3220644222
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1283028467
Short name T77
Test name
Test status
Simulation time 17699178 ps
CPU time 0.59 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:25:23 PM PDT 24
Peak memory 195084 kb
Host smart-028ce182-95d8-465d-95d8-8ba2e8d50d6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283028467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1283028467
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2239701874
Short name T1304
Test name
Test status
Simulation time 42433787 ps
CPU time 0.56 seconds
Started May 19 12:25:24 PM PDT 24
Finished May 19 12:25:29 PM PDT 24
Peak memory 194044 kb
Host smart-9acc5b5f-4b78-4221-a784-fbb4e3905821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239701874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2239701874
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.4087693385
Short name T1232
Test name
Test status
Simulation time 33313406 ps
CPU time 0.75 seconds
Started May 19 12:25:20 PM PDT 24
Finished May 19 12:25:27 PM PDT 24
Peak memory 196556 kb
Host smart-945d76d4-e917-4989-b980-75e3fc796af1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087693385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.4087693385
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3942113027
Short name T1201
Test name
Test status
Simulation time 362516956 ps
CPU time 1.94 seconds
Started May 19 12:25:25 PM PDT 24
Finished May 19 12:25:33 PM PDT 24
Peak memory 199732 kb
Host smart-61046294-0385-42bf-9960-407e17aebd7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942113027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3942113027
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.4118643309
Short name T88
Test name
Test status
Simulation time 140159907 ps
CPU time 1.22 seconds
Started May 19 12:25:17 PM PDT 24
Finished May 19 12:25:25 PM PDT 24
Peak memory 199180 kb
Host smart-e0f75de5-92de-4a6c-8447-eb7ed98425c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118643309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.4118643309
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3519165328
Short name T1296
Test name
Test status
Simulation time 44734029 ps
CPU time 0.69 seconds
Started May 19 12:21:49 PM PDT 24
Finished May 19 12:21:52 PM PDT 24
Peak memory 194972 kb
Host smart-0c5da2be-4b45-4dba-a8e5-ea4ec6ad8ef0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519165328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3519165328
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1387938614
Short name T1209
Test name
Test status
Simulation time 181715133 ps
CPU time 2.38 seconds
Started May 19 12:23:31 PM PDT 24
Finished May 19 12:23:53 PM PDT 24
Peak memory 197044 kb
Host smart-60202ca3-b121-47fa-bb48-ba6cb599a329
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387938614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1387938614
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.215604902
Short name T1317
Test name
Test status
Simulation time 26061777 ps
CPU time 0.6 seconds
Started May 19 12:23:43 PM PDT 24
Finished May 19 12:24:00 PM PDT 24
Peak memory 194852 kb
Host smart-7398cee6-4f5a-4d30-8478-436cc7983bf0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215604902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.215604902
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.920583865
Short name T1283
Test name
Test status
Simulation time 17903542 ps
CPU time 0.83 seconds
Started May 19 12:19:27 PM PDT 24
Finished May 19 12:19:29 PM PDT 24
Peak memory 198212 kb
Host smart-33872e45-d52c-48e1-8c52-99b3e7b06328
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920583865 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.920583865
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2794761076
Short name T1230
Test name
Test status
Simulation time 22153576 ps
CPU time 0.58 seconds
Started May 19 12:23:32 PM PDT 24
Finished May 19 12:23:53 PM PDT 24
Peak memory 194752 kb
Host smart-cc531005-67ca-4e77-999d-35d1d8ba4c2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794761076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2794761076
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2508889293
Short name T1277
Test name
Test status
Simulation time 38329083 ps
CPU time 0.6 seconds
Started May 19 12:20:37 PM PDT 24
Finished May 19 12:20:41 PM PDT 24
Peak memory 194496 kb
Host smart-62146c51-4389-400f-acfd-035ab6acde1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508889293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2508889293
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1912594884
Short name T76
Test name
Test status
Simulation time 55267449 ps
CPU time 0.7 seconds
Started May 19 12:23:21 PM PDT 24
Finished May 19 12:23:30 PM PDT 24
Peak memory 196448 kb
Host smart-59321a30-9dae-48a5-937c-800729e18536
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912594884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1912594884
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3665161911
Short name T1186
Test name
Test status
Simulation time 522245154 ps
CPU time 2.59 seconds
Started May 19 12:18:33 PM PDT 24
Finished May 19 12:18:36 PM PDT 24
Peak memory 199700 kb
Host smart-57b717e5-ac5a-4cf2-b8be-478700c3cf90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665161911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3665161911
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2840602990
Short name T93
Test name
Test status
Simulation time 91969655 ps
CPU time 1.33 seconds
Started May 19 12:19:04 PM PDT 24
Finished May 19 12:19:06 PM PDT 24
Peak memory 199068 kb
Host smart-0523ad7e-2b35-40b5-81c1-11a8f1990787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840602990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2840602990
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1264604349
Short name T1245
Test name
Test status
Simulation time 25986442 ps
CPU time 0.56 seconds
Started May 19 12:25:27 PM PDT 24
Finished May 19 12:25:30 PM PDT 24
Peak memory 194108 kb
Host smart-6ea66cb8-0582-4205-a344-3eb7f221a795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264604349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1264604349
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1731973176
Short name T1181
Test name
Test status
Simulation time 32456648 ps
CPU time 0.55 seconds
Started May 19 12:25:10 PM PDT 24
Finished May 19 12:25:19 PM PDT 24
Peak memory 194108 kb
Host smart-9c2b47ed-ad90-4b8e-b049-7472428b2db5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731973176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1731973176
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2653934387
Short name T1215
Test name
Test status
Simulation time 12677261 ps
CPU time 0.55 seconds
Started May 19 12:25:25 PM PDT 24
Finished May 19 12:25:29 PM PDT 24
Peak memory 194516 kb
Host smart-5b7257b5-2e35-45cd-b160-cff922148735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653934387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2653934387
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.636318400
Short name T1208
Test name
Test status
Simulation time 13778231 ps
CPU time 0.57 seconds
Started May 19 12:25:10 PM PDT 24
Finished May 19 12:25:20 PM PDT 24
Peak memory 193996 kb
Host smart-36e7f5b6-a4b9-41a2-9603-75439475f8b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636318400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.636318400
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1039750935
Short name T1278
Test name
Test status
Simulation time 37575398 ps
CPU time 0.56 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 194000 kb
Host smart-540052c2-ead6-4f99-a666-5fb77780ff2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039750935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1039750935
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3160557076
Short name T1193
Test name
Test status
Simulation time 25152774 ps
CPU time 0.57 seconds
Started May 19 12:25:14 PM PDT 24
Finished May 19 12:25:23 PM PDT 24
Peak memory 194032 kb
Host smart-c43a9e74-d1d2-46ec-a4d8-b0c6cb15ae81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160557076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3160557076
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3463324358
Short name T1267
Test name
Test status
Simulation time 32341602 ps
CPU time 0.54 seconds
Started May 19 12:25:25 PM PDT 24
Finished May 19 12:25:29 PM PDT 24
Peak memory 194028 kb
Host smart-3486b3a1-14eb-4027-88d2-559743a425c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463324358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3463324358
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.4188367517
Short name T1183
Test name
Test status
Simulation time 26104439 ps
CPU time 0.56 seconds
Started May 19 12:25:13 PM PDT 24
Finished May 19 12:25:22 PM PDT 24
Peak memory 193964 kb
Host smart-b8f712ca-11fe-4896-a912-532571acca51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188367517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.4188367517
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3203373189
Short name T1189
Test name
Test status
Simulation time 45835025 ps
CPU time 0.59 seconds
Started May 19 12:25:08 PM PDT 24
Finished May 19 12:25:17 PM PDT 24
Peak memory 194496 kb
Host smart-844d887d-43f1-4f02-ab3b-ee9f11b4cd4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203373189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3203373189
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1574751769
Short name T1231
Test name
Test status
Simulation time 12820470 ps
CPU time 0.55 seconds
Started May 19 12:25:28 PM PDT 24
Finished May 19 12:25:30 PM PDT 24
Peak memory 194088 kb
Host smart-e4c99604-d4d0-4ef2-9b80-d268e49d6dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574751769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1574751769
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2423436205
Short name T1306
Test name
Test status
Simulation time 48494517 ps
CPU time 0.66 seconds
Started May 19 12:20:44 PM PDT 24
Finished May 19 12:20:46 PM PDT 24
Peak memory 194432 kb
Host smart-adc29aa7-1d09-45de-bd23-a7d5bca0e72f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423436205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2423436205
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.572170634
Short name T1291
Test name
Test status
Simulation time 181734771 ps
CPU time 1.5 seconds
Started May 19 12:22:09 PM PDT 24
Finished May 19 12:22:11 PM PDT 24
Peak memory 197688 kb
Host smart-9a2e6abf-91da-4942-b013-849f2b896edb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572170634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.572170634
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3870834156
Short name T72
Test name
Test status
Simulation time 51249772 ps
CPU time 0.58 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:47 PM PDT 24
Peak memory 194752 kb
Host smart-a7652de5-99ab-4569-b5c1-7c0f127ee3b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870834156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3870834156
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4200927417
Short name T1194
Test name
Test status
Simulation time 29639408 ps
CPU time 0.75 seconds
Started May 19 12:23:29 PM PDT 24
Finished May 19 12:23:50 PM PDT 24
Peak memory 198836 kb
Host smart-3f07fc0c-789f-484a-83e4-31604a2f4be4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200927417 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.4200927417
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.4132397810
Short name T1272
Test name
Test status
Simulation time 16129439 ps
CPU time 0.59 seconds
Started May 19 12:23:26 PM PDT 24
Finished May 19 12:23:47 PM PDT 24
Peak memory 194716 kb
Host smart-0b0cf1bd-6c62-4702-8902-f4007940c72a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132397810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.4132397810
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2250668055
Short name T1187
Test name
Test status
Simulation time 26898481 ps
CPU time 0.57 seconds
Started May 19 12:21:58 PM PDT 24
Finished May 19 12:21:59 PM PDT 24
Peak memory 194036 kb
Host smart-b069c16a-5cfe-4a31-8950-eb8eb10ac615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250668055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2250668055
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.4114308902
Short name T74
Test name
Test status
Simulation time 83186765 ps
CPU time 0.72 seconds
Started May 19 12:20:44 PM PDT 24
Finished May 19 12:20:46 PM PDT 24
Peak memory 196704 kb
Host smart-5068f944-84b8-44d6-b93e-359ed6c1f6e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114308902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.4114308902
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2760230396
Short name T1314
Test name
Test status
Simulation time 599881296 ps
CPU time 1.5 seconds
Started May 19 12:19:22 PM PDT 24
Finished May 19 12:19:24 PM PDT 24
Peak memory 199704 kb
Host smart-9dc26587-c008-4687-a093-3e4d26fba18b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760230396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2760230396
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.858715483
Short name T117
Test name
Test status
Simulation time 205495263 ps
CPU time 1.43 seconds
Started May 19 12:21:07 PM PDT 24
Finished May 19 12:21:09 PM PDT 24
Peak memory 199584 kb
Host smart-592b6ec9-74de-4ba0-bde6-a80609b36e6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858715483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.858715483
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2358457840
Short name T1219
Test name
Test status
Simulation time 13868033 ps
CPU time 0.58 seconds
Started May 19 12:25:18 PM PDT 24
Finished May 19 12:25:25 PM PDT 24
Peak memory 194068 kb
Host smart-01bb5ec9-5583-4bca-9e51-1fea81de49e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358457840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2358457840
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2369384329
Short name T1269
Test name
Test status
Simulation time 109814553 ps
CPU time 0.54 seconds
Started May 19 12:25:17 PM PDT 24
Finished May 19 12:25:24 PM PDT 24
Peak memory 194012 kb
Host smart-36a040e8-88cc-4daa-9834-70f2703376f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369384329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2369384329
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3767254970
Short name T1234
Test name
Test status
Simulation time 51673930 ps
CPU time 0.56 seconds
Started May 19 12:25:21 PM PDT 24
Finished May 19 12:25:27 PM PDT 24
Peak memory 194460 kb
Host smart-d5024c73-48f4-48c8-a4e8-ed3bf7b70e8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767254970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3767254970
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1959106304
Short name T1316
Test name
Test status
Simulation time 29893986 ps
CPU time 0.55 seconds
Started May 19 12:25:21 PM PDT 24
Finished May 19 12:25:30 PM PDT 24
Peak memory 194084 kb
Host smart-1cbaf29a-e8a7-46d7-be83-cd2ff76f7f89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959106304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1959106304
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3378891973
Short name T1214
Test name
Test status
Simulation time 50670849 ps
CPU time 0.56 seconds
Started May 19 12:25:29 PM PDT 24
Finished May 19 12:25:32 PM PDT 24
Peak memory 194136 kb
Host smart-a88e6432-13aa-4082-a614-bfb6798a5c8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378891973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3378891973
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1873853140
Short name T1290
Test name
Test status
Simulation time 75278698 ps
CPU time 0.56 seconds
Started May 19 12:25:25 PM PDT 24
Finished May 19 12:25:29 PM PDT 24
Peak memory 193988 kb
Host smart-0d15ff05-ba03-4249-b9a8-be371d21b528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873853140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1873853140
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.663446757
Short name T1259
Test name
Test status
Simulation time 16141105 ps
CPU time 0.58 seconds
Started May 19 12:25:18 PM PDT 24
Finished May 19 12:25:26 PM PDT 24
Peak memory 194016 kb
Host smart-7811d953-d814-4109-8a47-1e1f1e6ef5bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663446757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.663446757
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.4073382552
Short name T1240
Test name
Test status
Simulation time 69850515 ps
CPU time 0.56 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:24 PM PDT 24
Peak memory 194060 kb
Host smart-1463cc82-a483-4837-9b9a-4e4c8602f1cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073382552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.4073382552
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.265045531
Short name T1199
Test name
Test status
Simulation time 80529339 ps
CPU time 0.55 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:25:18 PM PDT 24
Peak memory 193960 kb
Host smart-16d1313b-25f7-474d-891b-dfba8a868315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265045531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.265045531
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1087187443
Short name T1268
Test name
Test status
Simulation time 18504771 ps
CPU time 0.55 seconds
Started May 19 12:25:12 PM PDT 24
Finished May 19 12:25:21 PM PDT 24
Peak memory 194020 kb
Host smart-4cd17190-6c65-4d19-9a82-66d5033c0af2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087187443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1087187443
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1167470613
Short name T1282
Test name
Test status
Simulation time 99518442 ps
CPU time 0.67 seconds
Started May 19 12:24:00 PM PDT 24
Finished May 19 12:24:08 PM PDT 24
Peak memory 194612 kb
Host smart-3511bd33-a438-4d0a-8190-6a6622907e23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167470613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1167470613
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.343790236
Short name T1257
Test name
Test status
Simulation time 96934636 ps
CPU time 1.64 seconds
Started May 19 12:21:50 PM PDT 24
Finished May 19 12:21:54 PM PDT 24
Peak memory 198072 kb
Host smart-59b6f010-f79d-49f8-8ffa-fc144a9d51e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343790236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.343790236
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.775441731
Short name T1196
Test name
Test status
Simulation time 16910591 ps
CPU time 0.57 seconds
Started May 19 12:24:01 PM PDT 24
Finished May 19 12:24:09 PM PDT 24
Peak memory 194748 kb
Host smart-e7dfd873-4d92-42d5-937d-90af19ebe13b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775441731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.775441731
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1716500526
Short name T1258
Test name
Test status
Simulation time 26554336 ps
CPU time 0.76 seconds
Started May 19 12:24:00 PM PDT 24
Finished May 19 12:24:09 PM PDT 24
Peak memory 198856 kb
Host smart-29ee21b0-68f4-4434-9f76-2508503ef82d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716500526 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1716500526
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2247289962
Short name T1247
Test name
Test status
Simulation time 42510789 ps
CPU time 0.63 seconds
Started May 19 12:23:04 PM PDT 24
Finished May 19 12:23:06 PM PDT 24
Peak memory 194472 kb
Host smart-4e963632-b39f-4da4-b3bb-a9e994123557
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247289962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2247289962
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1602368271
Short name T1244
Test name
Test status
Simulation time 43034208 ps
CPU time 0.6 seconds
Started May 19 12:20:36 PM PDT 24
Finished May 19 12:20:40 PM PDT 24
Peak memory 194560 kb
Host smart-1b5d3947-093c-454f-bc6d-8b22935d3e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602368271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1602368271
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.527564413
Short name T79
Test name
Test status
Simulation time 90426982 ps
CPU time 0.64 seconds
Started May 19 12:24:00 PM PDT 24
Finished May 19 12:24:08 PM PDT 24
Peak memory 195080 kb
Host smart-ea52552d-e9ff-4997-9a11-41108d3bb448
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527564413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.527564413
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3612172311
Short name T1204
Test name
Test status
Simulation time 304614208 ps
CPU time 1.6 seconds
Started May 19 12:21:17 PM PDT 24
Finished May 19 12:21:19 PM PDT 24
Peak memory 199756 kb
Host smart-b8f47419-b8f9-485d-8ed7-892e1d083e3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612172311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3612172311
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1533303288
Short name T1241
Test name
Test status
Simulation time 260292783 ps
CPU time 1.32 seconds
Started May 19 12:20:42 PM PDT 24
Finished May 19 12:20:44 PM PDT 24
Peak memory 199512 kb
Host smart-81807405-a471-43d1-83f7-7d69a6f69051
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533303288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1533303288
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3045999320
Short name T1216
Test name
Test status
Simulation time 12180813 ps
CPU time 0.57 seconds
Started May 19 12:25:35 PM PDT 24
Finished May 19 12:25:36 PM PDT 24
Peak memory 194060 kb
Host smart-52559490-0b03-44ee-9b5a-ab4d6ba70001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045999320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3045999320
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.663908507
Short name T1266
Test name
Test status
Simulation time 18002582 ps
CPU time 0.55 seconds
Started May 19 12:25:13 PM PDT 24
Finished May 19 12:25:22 PM PDT 24
Peak memory 194020 kb
Host smart-00c2a1a3-378e-48bd-ada4-cdcc18c460b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663908507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.663908507
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1262873663
Short name T1213
Test name
Test status
Simulation time 25514757 ps
CPU time 0.53 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:13 PM PDT 24
Peak memory 194032 kb
Host smart-e28e86fa-51aa-42ec-b09f-a1a9e5340777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262873663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1262873663
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3568238100
Short name T1248
Test name
Test status
Simulation time 29609579 ps
CPU time 0.54 seconds
Started May 19 12:25:27 PM PDT 24
Finished May 19 12:25:30 PM PDT 24
Peak memory 193996 kb
Host smart-e438d1c8-6f6f-4e07-b188-e5e0c48773e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568238100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3568238100
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1113607256
Short name T1305
Test name
Test status
Simulation time 10961550 ps
CPU time 0.55 seconds
Started May 19 12:25:26 PM PDT 24
Finished May 19 12:25:29 PM PDT 24
Peak memory 193960 kb
Host smart-8c60bfcd-8ca8-4766-8a70-5668acc7febb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113607256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1113607256
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2837189723
Short name T1242
Test name
Test status
Simulation time 29962042 ps
CPU time 0.57 seconds
Started May 19 12:25:10 PM PDT 24
Finished May 19 12:25:19 PM PDT 24
Peak memory 194040 kb
Host smart-bb1d1d91-ff3a-42bf-a801-b53b8f54d3d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837189723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2837189723
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1846256971
Short name T1195
Test name
Test status
Simulation time 11077987 ps
CPU time 0.54 seconds
Started May 19 12:25:20 PM PDT 24
Finished May 19 12:25:27 PM PDT 24
Peak memory 194020 kb
Host smart-106e76fa-809e-4726-8dd1-fd60967c3b5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846256971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1846256971
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.4229889351
Short name T1285
Test name
Test status
Simulation time 13236458 ps
CPU time 0.55 seconds
Started May 19 12:25:18 PM PDT 24
Finished May 19 12:25:26 PM PDT 24
Peak memory 194028 kb
Host smart-6d4cb603-ab0f-4ad5-a3cf-fadbbf71aa27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229889351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.4229889351
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2712601857
Short name T1309
Test name
Test status
Simulation time 27018617 ps
CPU time 0.54 seconds
Started May 19 12:25:12 PM PDT 24
Finished May 19 12:25:20 PM PDT 24
Peak memory 194092 kb
Host smart-59b6ceb6-372b-4d83-86be-20605ae04a95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712601857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2712601857
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1137037044
Short name T1300
Test name
Test status
Simulation time 77313647 ps
CPU time 0.53 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:24 PM PDT 24
Peak memory 193996 kb
Host smart-1e0f7f30-e674-4608-aa27-2e6a31dcab20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137037044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1137037044
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3393210390
Short name T1253
Test name
Test status
Simulation time 45860998 ps
CPU time 0.73 seconds
Started May 19 12:20:35 PM PDT 24
Finished May 19 12:20:39 PM PDT 24
Peak memory 198076 kb
Host smart-52a53de1-f6c2-4398-8e60-b38ee050da97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393210390 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3393210390
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3334811688
Short name T1260
Test name
Test status
Simulation time 16818159 ps
CPU time 0.6 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:47 PM PDT 24
Peak memory 194752 kb
Host smart-3fb71ebc-bf32-4a27-8dcc-641b1db76b96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334811688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3334811688
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.257873934
Short name T1275
Test name
Test status
Simulation time 55320845 ps
CPU time 0.6 seconds
Started May 19 12:22:04 PM PDT 24
Finished May 19 12:22:06 PM PDT 24
Peak memory 194500 kb
Host smart-74591b90-3524-48c0-8951-a4e1ceba9d03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257873934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.257873934
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1281808631
Short name T75
Test name
Test status
Simulation time 14442574 ps
CPU time 0.61 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:47 PM PDT 24
Peak memory 194988 kb
Host smart-6f3bd14c-5e44-4b44-a6b1-aaa266c24b2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281808631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1281808631
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2192761868
Short name T1261
Test name
Test status
Simulation time 707434412 ps
CPU time 1.2 seconds
Started May 19 12:19:29 PM PDT 24
Finished May 19 12:19:31 PM PDT 24
Peak memory 199736 kb
Host smart-a0014bf2-0e01-47cc-9e20-1cf02f408e5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192761868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2192761868
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1751016819
Short name T1286
Test name
Test status
Simulation time 83673655 ps
CPU time 0.94 seconds
Started May 19 12:23:06 PM PDT 24
Finished May 19 12:23:09 PM PDT 24
Peak memory 198356 kb
Host smart-d011dd15-5800-427e-80ad-02c97d5b8496
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751016819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1751016819
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2422549581
Short name T1265
Test name
Test status
Simulation time 23071485 ps
CPU time 0.78 seconds
Started May 19 12:20:51 PM PDT 24
Finished May 19 12:20:53 PM PDT 24
Peak memory 198972 kb
Host smart-f9150a14-b28e-4a91-b465-7cbf8dee9d8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422549581 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2422549581
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3484958409
Short name T1256
Test name
Test status
Simulation time 17789205 ps
CPU time 0.63 seconds
Started May 19 12:24:00 PM PDT 24
Finished May 19 12:24:08 PM PDT 24
Peak memory 194740 kb
Host smart-77144a0a-ac2c-439b-ba21-7d82ac3a09b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484958409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3484958409
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.4066494878
Short name T1235
Test name
Test status
Simulation time 65693198 ps
CPU time 0.54 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:47 PM PDT 24
Peak memory 193700 kb
Host smart-521ceef8-ac0b-48f7-87b3-c8e9e51dae0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066494878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.4066494878
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1620432185
Short name T1281
Test name
Test status
Simulation time 165538263 ps
CPU time 0.63 seconds
Started May 19 12:23:36 PM PDT 24
Finished May 19 12:23:57 PM PDT 24
Peak memory 195188 kb
Host smart-ac9c89da-a806-4c55-8cef-46920c79a9b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620432185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1620432185
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.143623326
Short name T1198
Test name
Test status
Simulation time 83974780 ps
CPU time 1.97 seconds
Started May 19 12:19:55 PM PDT 24
Finished May 19 12:19:57 PM PDT 24
Peak memory 199684 kb
Host smart-eefc5915-e072-4229-98b7-918f7a8b08fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143623326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.143623326
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3096413603
Short name T118
Test name
Test status
Simulation time 88664796 ps
CPU time 1.26 seconds
Started May 19 12:23:26 PM PDT 24
Finished May 19 12:23:47 PM PDT 24
Peak memory 198212 kb
Host smart-0f7a4c5c-f663-412f-ae2c-2806a3d0fa84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096413603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3096413603
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2095971350
Short name T1249
Test name
Test status
Simulation time 71586422 ps
CPU time 0.62 seconds
Started May 19 12:23:19 PM PDT 24
Finished May 19 12:23:26 PM PDT 24
Peak memory 196572 kb
Host smart-3b60b75c-d939-4f5a-a415-21ee14256191
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095971350 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2095971350
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.535793214
Short name T1295
Test name
Test status
Simulation time 28083979 ps
CPU time 0.62 seconds
Started May 19 12:19:29 PM PDT 24
Finished May 19 12:19:30 PM PDT 24
Peak memory 195100 kb
Host smart-58238e81-3721-4f54-979b-a75c76b65787
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535793214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.535793214
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.44865528
Short name T1312
Test name
Test status
Simulation time 11049960 ps
CPU time 0.63 seconds
Started May 19 12:19:39 PM PDT 24
Finished May 19 12:19:40 PM PDT 24
Peak memory 194448 kb
Host smart-69241e47-7da4-490b-88c6-88d010ed3b3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44865528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.44865528
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2160294301
Short name T1279
Test name
Test status
Simulation time 123373071 ps
CPU time 0.78 seconds
Started May 19 12:20:07 PM PDT 24
Finished May 19 12:20:09 PM PDT 24
Peak memory 196796 kb
Host smart-28f2085d-2818-4af4-884b-962ddf75af8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160294301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2160294301
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3390048235
Short name T1223
Test name
Test status
Simulation time 55569120 ps
CPU time 2.43 seconds
Started May 19 12:21:24 PM PDT 24
Finished May 19 12:21:28 PM PDT 24
Peak memory 199820 kb
Host smart-59e0003e-41e2-447d-811b-bc2d6bea1ec3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390048235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3390048235
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.820386241
Short name T1251
Test name
Test status
Simulation time 24162566 ps
CPU time 1.01 seconds
Started May 19 12:23:20 PM PDT 24
Finished May 19 12:23:27 PM PDT 24
Peak memory 199440 kb
Host smart-3c876a5b-c700-4cd3-bf4d-d31d41bc3924
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820386241 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.820386241
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.144093291
Short name T1292
Test name
Test status
Simulation time 13496607 ps
CPU time 0.56 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:48 PM PDT 24
Peak memory 195000 kb
Host smart-0dd93548-3141-4d84-88a4-123f61be8a4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144093291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.144093291
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3040191075
Short name T1302
Test name
Test status
Simulation time 11973786 ps
CPU time 0.55 seconds
Started May 19 12:23:18 PM PDT 24
Finished May 19 12:23:25 PM PDT 24
Peak memory 193332 kb
Host smart-7f2f0f60-8af2-44a5-8470-47b695795134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040191075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3040191075
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2348979322
Short name T83
Test name
Test status
Simulation time 19994300 ps
CPU time 0.72 seconds
Started May 19 12:22:16 PM PDT 24
Finished May 19 12:22:17 PM PDT 24
Peak memory 195740 kb
Host smart-6942a410-0315-4f79-87a3-d7b1b0aeff12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348979322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2348979322
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.200340068
Short name T1225
Test name
Test status
Simulation time 262138904 ps
CPU time 1.35 seconds
Started May 19 12:23:13 PM PDT 24
Finished May 19 12:23:18 PM PDT 24
Peak memory 199412 kb
Host smart-aca0d86a-f23f-43af-ad0c-0cb9c7eeff4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200340068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.200340068
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4205445540
Short name T1212
Test name
Test status
Simulation time 813384300 ps
CPU time 0.95 seconds
Started May 19 12:23:18 PM PDT 24
Finished May 19 12:23:25 PM PDT 24
Peak memory 196872 kb
Host smart-4b5fc87f-a035-4ef6-a8a7-093941a84b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205445540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.4205445540
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.251609302
Short name T1182
Test name
Test status
Simulation time 68257980 ps
CPU time 0.73 seconds
Started May 19 12:20:45 PM PDT 24
Finished May 19 12:20:47 PM PDT 24
Peak memory 198652 kb
Host smart-9f38d63d-5dff-4784-a455-dd27a587a7a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251609302 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.251609302
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2714886676
Short name T1297
Test name
Test status
Simulation time 12270784 ps
CPU time 0.57 seconds
Started May 19 12:23:32 PM PDT 24
Finished May 19 12:23:53 PM PDT 24
Peak memory 194792 kb
Host smart-e38f527c-8722-477a-a393-5340382c2f05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714886676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2714886676
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.315053998
Short name T1233
Test name
Test status
Simulation time 28672279 ps
CPU time 0.58 seconds
Started May 19 12:23:28 PM PDT 24
Finished May 19 12:23:48 PM PDT 24
Peak memory 193996 kb
Host smart-340f4554-b8b5-4a6e-9d43-dc48e1c2f182
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315053998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.315053998
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3687519260
Short name T1239
Test name
Test status
Simulation time 39659928 ps
CPU time 0.69 seconds
Started May 19 12:23:32 PM PDT 24
Finished May 19 12:23:52 PM PDT 24
Peak memory 195744 kb
Host smart-3a011c73-9a48-4a55-b413-389659537874
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687519260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3687519260
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3329068013
Short name T1263
Test name
Test status
Simulation time 194188027 ps
CPU time 1.41 seconds
Started May 19 12:23:35 PM PDT 24
Finished May 19 12:23:58 PM PDT 24
Peak memory 199288 kb
Host smart-1ffdd3c5-0713-4ed5-9e27-1938f5c8c5a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329068013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3329068013
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1632465172
Short name T1280
Test name
Test status
Simulation time 85578613 ps
CPU time 0.94 seconds
Started May 19 12:23:02 PM PDT 24
Finished May 19 12:23:04 PM PDT 24
Peak memory 198760 kb
Host smart-c20ca6c0-81a7-4b1e-b0c3-e3945ee383c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632465172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1632465172
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1358004099
Short name T353
Test name
Test status
Simulation time 34739381 ps
CPU time 0.53 seconds
Started May 19 12:28:49 PM PDT 24
Finished May 19 12:28:50 PM PDT 24
Peak memory 194732 kb
Host smart-e6815d98-f61a-4eb6-9cde-5a139777cd3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358004099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1358004099
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.78978482
Short name T53
Test name
Test status
Simulation time 50158145020 ps
CPU time 97.52 seconds
Started May 19 12:21:15 PM PDT 24
Finished May 19 12:22:53 PM PDT 24
Peak memory 200284 kb
Host smart-24eace8c-b19b-4638-8a28-03979fdc2751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78978482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.78978482
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_intr.3747407189
Short name T309
Test name
Test status
Simulation time 29733763807 ps
CPU time 14.49 seconds
Started May 19 12:21:50 PM PDT 24
Finished May 19 12:22:06 PM PDT 24
Peak memory 200036 kb
Host smart-92dd5f1e-c32a-4dfb-9a0b-2ddec1af86d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747407189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3747407189
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2429080431
Short name T356
Test name
Test status
Simulation time 113261289222 ps
CPU time 177.29 seconds
Started May 19 12:30:10 PM PDT 24
Finished May 19 12:33:12 PM PDT 24
Peak memory 199428 kb
Host smart-0fcecb1b-e4d7-4c14-bbaa-66791ead922d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2429080431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2429080431
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2472706948
Short name T850
Test name
Test status
Simulation time 8495508033 ps
CPU time 6.94 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:30:16 PM PDT 24
Peak memory 197336 kb
Host smart-fccf57e1-293c-43f9-8c07-80606ba9d6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472706948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2472706948
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.691373430
Short name T248
Test name
Test status
Simulation time 69837480926 ps
CPU time 129.9 seconds
Started May 19 12:23:32 PM PDT 24
Finished May 19 12:26:02 PM PDT 24
Peak memory 208428 kb
Host smart-a58c0124-4cd8-4054-a2c4-441d89c25eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691373430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.691373430
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2001628892
Short name T619
Test name
Test status
Simulation time 20593402491 ps
CPU time 42.02 seconds
Started May 19 12:21:19 PM PDT 24
Finished May 19 12:22:03 PM PDT 24
Peak memory 200708 kb
Host smart-13115989-e7ce-4a56-a494-45f0be2d14b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001628892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2001628892
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3565786428
Short name T100
Test name
Test status
Simulation time 1598039157 ps
CPU time 3.23 seconds
Started May 19 12:23:32 PM PDT 24
Finished May 19 12:23:56 PM PDT 24
Peak memory 195620 kb
Host smart-cae3eb43-31d8-466a-bcfd-42d679d9fa82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565786428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3565786428
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1754463445
Short name T30
Test name
Test status
Simulation time 218273788 ps
CPU time 0.85 seconds
Started May 19 12:30:16 PM PDT 24
Finished May 19 12:30:19 PM PDT 24
Peak memory 218272 kb
Host smart-019cbc46-d76d-45aa-8c44-0df90ff7075d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754463445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1754463445
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.3274295465
Short name T400
Test name
Test status
Simulation time 887771867 ps
CPU time 3.63 seconds
Started May 19 12:22:07 PM PDT 24
Finished May 19 12:22:12 PM PDT 24
Peak memory 199876 kb
Host smart-4cbd4a8e-1aa6-4145-9363-63145605e677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274295465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3274295465
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2980788688
Short name T778
Test name
Test status
Simulation time 114211349801 ps
CPU time 345.47 seconds
Started May 19 12:30:02 PM PDT 24
Finished May 19 12:35:55 PM PDT 24
Peak memory 216564 kb
Host smart-21a286f4-ad11-4c33-84e8-21c2603018dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980788688 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2980788688
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.233310664
Short name T18
Test name
Test status
Simulation time 6573214271 ps
CPU time 8.86 seconds
Started May 19 12:30:17 PM PDT 24
Finished May 19 12:30:29 PM PDT 24
Peak memory 200220 kb
Host smart-6ed13ea6-6953-4ab9-856e-7e719cc832fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233310664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.233310664
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1393535221
Short name T1092
Test name
Test status
Simulation time 87253729408 ps
CPU time 80.52 seconds
Started May 19 12:21:02 PM PDT 24
Finished May 19 12:22:23 PM PDT 24
Peak memory 200644 kb
Host smart-6294f01a-ddba-4075-aa4b-993f26108024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393535221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1393535221
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.572914975
Short name T417
Test name
Test status
Simulation time 42202940 ps
CPU time 0.53 seconds
Started May 19 12:28:51 PM PDT 24
Finished May 19 12:28:52 PM PDT 24
Peak memory 195644 kb
Host smart-a42b497d-3269-4a4c-97e2-05299b23cdf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572914975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.572914975
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2244770151
Short name T447
Test name
Test status
Simulation time 143310780305 ps
CPU time 346.58 seconds
Started May 19 12:29:03 PM PDT 24
Finished May 19 12:34:50 PM PDT 24
Peak memory 200276 kb
Host smart-aceff7c0-765e-4954-a73f-cfcad3e2b95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244770151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2244770151
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.210760044
Short name T289
Test name
Test status
Simulation time 29591244354 ps
CPU time 47.14 seconds
Started May 19 12:29:17 PM PDT 24
Finished May 19 12:30:06 PM PDT 24
Peak memory 200280 kb
Host smart-a216eed0-3b8c-4ae6-90fe-af06799e5867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210760044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.210760044
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2219996706
Short name T306
Test name
Test status
Simulation time 110482881477 ps
CPU time 82.28 seconds
Started May 19 12:29:17 PM PDT 24
Finished May 19 12:30:41 PM PDT 24
Peak memory 200040 kb
Host smart-b007b143-71cf-4196-beed-93e6fb825734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219996706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2219996706
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.83515109
Short name T830
Test name
Test status
Simulation time 27748418167 ps
CPU time 14.53 seconds
Started May 19 12:29:15 PM PDT 24
Finished May 19 12:29:30 PM PDT 24
Peak memory 200224 kb
Host smart-dedbfcf6-93b6-4d06-9f2b-eea6eecf39ce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83515109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.83515109
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.4214840904
Short name T1043
Test name
Test status
Simulation time 90174188767 ps
CPU time 195.68 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:33:25 PM PDT 24
Peak memory 197536 kb
Host smart-13d67967-0d01-4944-91aa-35734f3c47c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4214840904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.4214840904
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1641650447
Short name T690
Test name
Test status
Simulation time 3389112216 ps
CPU time 3.28 seconds
Started May 19 12:29:12 PM PDT 24
Finished May 19 12:29:16 PM PDT 24
Peak memory 198724 kb
Host smart-aa689738-116a-4dcf-8bb9-436d4ea1e4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641650447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1641650447
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2130563109
Short name T530
Test name
Test status
Simulation time 77787090005 ps
CPU time 122.08 seconds
Started May 19 12:29:17 PM PDT 24
Finished May 19 12:31:21 PM PDT 24
Peak memory 200268 kb
Host smart-a5082e13-4274-4539-8627-8dc25fec2dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130563109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2130563109
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1759349706
Short name T965
Test name
Test status
Simulation time 8251433623 ps
CPU time 189.01 seconds
Started May 19 12:28:55 PM PDT 24
Finished May 19 12:32:15 PM PDT 24
Peak memory 200336 kb
Host smart-c6669369-11f7-4542-a231-2b1fe12523f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1759349706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1759349706
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.416372747
Short name T709
Test name
Test status
Simulation time 6560933072 ps
CPU time 25.41 seconds
Started May 19 12:28:50 PM PDT 24
Finished May 19 12:29:16 PM PDT 24
Peak memory 199500 kb
Host smart-e8cbb454-def8-42be-ab32-4a5ff9cfeb69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=416372747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.416372747
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.438914358
Short name T727
Test name
Test status
Simulation time 38993986676 ps
CPU time 31.21 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:30:40 PM PDT 24
Peak memory 196392 kb
Host smart-0c34af99-e24d-4081-8a1d-ca593d51768c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438914358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.438914358
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2166134513
Short name T538
Test name
Test status
Simulation time 41551647036 ps
CPU time 15.64 seconds
Started May 19 12:29:27 PM PDT 24
Finished May 19 12:29:44 PM PDT 24
Peak memory 196012 kb
Host smart-ac7dad26-4e13-469d-bc3a-8ea208a7eb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166134513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2166134513
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.400776582
Short name T29
Test name
Test status
Simulation time 238812373 ps
CPU time 0.76 seconds
Started May 19 12:29:13 PM PDT 24
Finished May 19 12:29:14 PM PDT 24
Peak memory 218652 kb
Host smart-c524c19f-9bdc-45f0-b69e-c5ecf10b8317
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400776582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.400776582
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1721152728
Short name T324
Test name
Test status
Simulation time 277666303 ps
CPU time 1.21 seconds
Started May 19 12:29:02 PM PDT 24
Finished May 19 12:29:04 PM PDT 24
Peak memory 198880 kb
Host smart-04a51f38-12c2-4aa6-b739-3e08ca1d2da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721152728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1721152728
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1863370223
Short name T141
Test name
Test status
Simulation time 155919588193 ps
CPU time 1198.45 seconds
Started May 19 12:29:13 PM PDT 24
Finished May 19 12:49:12 PM PDT 24
Peak memory 200212 kb
Host smart-267f7f8d-bcf9-41e1-a97b-0e9d1815a1b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863370223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1863370223
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2779650916
Short name T1138
Test name
Test status
Simulation time 312434113265 ps
CPU time 826.51 seconds
Started May 19 12:29:19 PM PDT 24
Finished May 19 12:43:06 PM PDT 24
Peak memory 214584 kb
Host smart-662219b0-30d2-4431-8e16-3369ddd02cef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779650916 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2779650916
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2624379922
Short name T438
Test name
Test status
Simulation time 7731639002 ps
CPU time 15.23 seconds
Started May 19 12:29:13 PM PDT 24
Finished May 19 12:29:29 PM PDT 24
Peak memory 199936 kb
Host smart-ecafbf73-a12d-4252-ae27-37657a460d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624379922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2624379922
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3496857549
Short name T754
Test name
Test status
Simulation time 16838886555 ps
CPU time 26.65 seconds
Started May 19 12:29:14 PM PDT 24
Finished May 19 12:29:41 PM PDT 24
Peak memory 199564 kb
Host smart-0d355365-e144-46df-a530-8d7aa8959173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496857549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3496857549
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3884894444
Short name T704
Test name
Test status
Simulation time 107556829037 ps
CPU time 206.53 seconds
Started May 19 12:29:34 PM PDT 24
Finished May 19 12:33:03 PM PDT 24
Peak memory 200772 kb
Host smart-2a77d240-6a49-4815-a634-0dcb02d62e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884894444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3884894444
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.79589773
Short name T917
Test name
Test status
Simulation time 25228213996 ps
CPU time 60.13 seconds
Started May 19 12:29:20 PM PDT 24
Finished May 19 12:30:21 PM PDT 24
Peak memory 200296 kb
Host smart-b8036531-35cc-400e-9c42-4d3d2ab6b5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79589773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.79589773
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.628251329
Short name T643
Test name
Test status
Simulation time 18845414195 ps
CPU time 31.23 seconds
Started May 19 12:29:29 PM PDT 24
Finished May 19 12:30:02 PM PDT 24
Peak memory 200336 kb
Host smart-b3a675fa-578c-48b1-938e-196bc448ced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628251329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.628251329
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.63403647
Short name T989
Test name
Test status
Simulation time 4478040860 ps
CPU time 2.45 seconds
Started May 19 12:29:58 PM PDT 24
Finished May 19 12:30:07 PM PDT 24
Peak memory 196160 kb
Host smart-ae61707b-7753-46fa-b917-3ba007cac71b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63403647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.63403647
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1971943774
Short name T475
Test name
Test status
Simulation time 116982378791 ps
CPU time 1058.17 seconds
Started May 19 12:29:35 PM PDT 24
Finished May 19 12:47:16 PM PDT 24
Peak memory 200200 kb
Host smart-05383505-90b2-4df6-b7c7-b03ca82cd3f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971943774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1971943774
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2280867210
Short name T445
Test name
Test status
Simulation time 14592907776 ps
CPU time 9.28 seconds
Started May 19 12:29:35 PM PDT 24
Finished May 19 12:29:47 PM PDT 24
Peak memory 198708 kb
Host smart-f61b1fba-1c0d-4980-948d-c463818bed71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280867210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2280867210
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2355307684
Short name T730
Test name
Test status
Simulation time 241629143691 ps
CPU time 58.11 seconds
Started May 19 12:29:26 PM PDT 24
Finished May 19 12:30:25 PM PDT 24
Peak memory 200548 kb
Host smart-11391e8c-96bf-47e5-9d57-cb15cf69cb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355307684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2355307684
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.461117147
Short name T561
Test name
Test status
Simulation time 13582376658 ps
CPU time 74.56 seconds
Started May 19 12:29:30 PM PDT 24
Finished May 19 12:30:46 PM PDT 24
Peak memory 200136 kb
Host smart-418ef0c3-6282-4f14-9e8f-9874028059bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461117147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.461117147
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2625078261
Short name T776
Test name
Test status
Simulation time 6516399211 ps
CPU time 11.88 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:08 PM PDT 24
Peak memory 198972 kb
Host smart-55287d33-91ce-4754-ba87-64b0cee1af90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625078261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2625078261
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3480301006
Short name T731
Test name
Test status
Simulation time 112457454010 ps
CPU time 317.56 seconds
Started May 19 12:29:28 PM PDT 24
Finished May 19 12:34:46 PM PDT 24
Peak memory 200312 kb
Host smart-d73f32a9-90c3-4c9f-8d81-bb2ef7243bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480301006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3480301006
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2345064171
Short name T853
Test name
Test status
Simulation time 4803232781 ps
CPU time 2.56 seconds
Started May 19 12:29:23 PM PDT 24
Finished May 19 12:29:26 PM PDT 24
Peak memory 196292 kb
Host smart-a7726802-6179-4247-96bd-aa22192509ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345064171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2345064171
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.4243972237
Short name T970
Test name
Test status
Simulation time 5374074804 ps
CPU time 14.97 seconds
Started May 19 12:29:57 PM PDT 24
Finished May 19 12:30:19 PM PDT 24
Peak memory 200128 kb
Host smart-1462d860-e4ab-45c2-8914-8bceb1a4529d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243972237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.4243972237
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3915410673
Short name T65
Test name
Test status
Simulation time 179317510597 ps
CPU time 283.41 seconds
Started May 19 12:29:32 PM PDT 24
Finished May 19 12:34:17 PM PDT 24
Peak memory 216980 kb
Host smart-3d044990-e8d8-437a-ae94-cc80c4eac18b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915410673 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3915410673
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1601704225
Short name T986
Test name
Test status
Simulation time 1839286598 ps
CPU time 2.2 seconds
Started May 19 12:29:35 PM PDT 24
Finished May 19 12:29:40 PM PDT 24
Peak memory 198736 kb
Host smart-3ad3af0d-9aed-4c58-bdfd-977d589970fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601704225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1601704225
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1489710815
Short name T842
Test name
Test status
Simulation time 17233704940 ps
CPU time 28.75 seconds
Started May 19 12:29:23 PM PDT 24
Finished May 19 12:29:53 PM PDT 24
Peak memory 200276 kb
Host smart-5807ff49-bae1-4a26-a1c8-d38825b70ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489710815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1489710815
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2796194731
Short name T1005
Test name
Test status
Simulation time 44055129928 ps
CPU time 130.62 seconds
Started May 19 12:31:23 PM PDT 24
Finished May 19 12:33:35 PM PDT 24
Peak memory 200276 kb
Host smart-98fb7998-b4aa-4a13-9f20-c0b38514524b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796194731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2796194731
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2616910541
Short name T319
Test name
Test status
Simulation time 57254151985 ps
CPU time 20.87 seconds
Started May 19 12:31:15 PM PDT 24
Finished May 19 12:31:37 PM PDT 24
Peak memory 198844 kb
Host smart-9984fe8a-0e11-4131-9d2f-66290eca42ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616910541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2616910541
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.414246304
Short name T207
Test name
Test status
Simulation time 56065615792 ps
CPU time 13.86 seconds
Started May 19 12:31:24 PM PDT 24
Finished May 19 12:31:39 PM PDT 24
Peak memory 199012 kb
Host smart-3d60985d-6d81-46a4-bb95-58b332e91e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414246304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.414246304
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.4146067072
Short name T684
Test name
Test status
Simulation time 109371174314 ps
CPU time 135.11 seconds
Started May 19 12:31:15 PM PDT 24
Finished May 19 12:33:31 PM PDT 24
Peak memory 200628 kb
Host smart-05096317-6277-4016-9df5-1bbe63ee03d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146067072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.4146067072
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.4153731537
Short name T1143
Test name
Test status
Simulation time 15908365383 ps
CPU time 23.96 seconds
Started May 19 12:31:14 PM PDT 24
Finished May 19 12:31:39 PM PDT 24
Peak memory 199948 kb
Host smart-214f4228-ccc0-4768-8e0f-dfa62d344126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153731537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.4153731537
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1962026204
Short name T188
Test name
Test status
Simulation time 18094578993 ps
CPU time 31.07 seconds
Started May 19 12:31:13 PM PDT 24
Finished May 19 12:31:46 PM PDT 24
Peak memory 200324 kb
Host smart-572d8e32-8038-40f7-905e-a5232b9c8cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962026204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1962026204
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1317309437
Short name T241
Test name
Test status
Simulation time 89530426347 ps
CPU time 40.97 seconds
Started May 19 12:31:14 PM PDT 24
Finished May 19 12:31:56 PM PDT 24
Peak memory 200732 kb
Host smart-b2074b09-2676-4c0c-8704-9c1537aebf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317309437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1317309437
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.345756545
Short name T497
Test name
Test status
Simulation time 20686028 ps
CPU time 0.54 seconds
Started May 19 12:29:51 PM PDT 24
Finished May 19 12:30:00 PM PDT 24
Peak memory 195180 kb
Host smart-e3c0704b-33c3-477b-9321-3ec25e3b4a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345756545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.345756545
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.4073178887
Short name T723
Test name
Test status
Simulation time 122788335888 ps
CPU time 43.13 seconds
Started May 19 12:29:22 PM PDT 24
Finished May 19 12:30:06 PM PDT 24
Peak memory 200300 kb
Host smart-842d7058-0cd8-4038-b169-414ec91a88e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073178887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.4073178887
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2537819539
Short name T255
Test name
Test status
Simulation time 103158574181 ps
CPU time 173.4 seconds
Started May 19 12:29:40 PM PDT 24
Finished May 19 12:32:35 PM PDT 24
Peak memory 200236 kb
Host smart-b010e853-4e61-4190-95e4-a6c75d47d67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537819539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2537819539
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2879442557
Short name T116
Test name
Test status
Simulation time 38445807410 ps
CPU time 32.93 seconds
Started May 19 12:29:19 PM PDT 24
Finished May 19 12:29:53 PM PDT 24
Peak memory 200340 kb
Host smart-f989d9fd-224c-49c2-94d3-5c280d814822
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879442557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2879442557
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1424552622
Short name T995
Test name
Test status
Simulation time 93437872413 ps
CPU time 443.87 seconds
Started May 19 12:29:38 PM PDT 24
Finished May 19 12:37:04 PM PDT 24
Peak memory 200372 kb
Host smart-c9d0d5de-c3b3-4b4a-a5b0-9de8f48a238b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1424552622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1424552622
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1238173268
Short name T767
Test name
Test status
Simulation time 3864538749 ps
CPU time 3.88 seconds
Started May 19 12:29:57 PM PDT 24
Finished May 19 12:30:08 PM PDT 24
Peak memory 198792 kb
Host smart-7e71dff5-3db4-4a0a-a502-5c89fe8a70cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238173268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1238173268
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2892594501
Short name T961
Test name
Test status
Simulation time 65045793896 ps
CPU time 108.97 seconds
Started May 19 12:29:26 PM PDT 24
Finished May 19 12:31:16 PM PDT 24
Peak memory 200544 kb
Host smart-8a939ef5-0db6-435a-85c6-411993c3a986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892594501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2892594501
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.930276502
Short name T716
Test name
Test status
Simulation time 8004080498 ps
CPU time 355.75 seconds
Started May 19 12:29:18 PM PDT 24
Finished May 19 12:35:15 PM PDT 24
Peak memory 200200 kb
Host smart-87a110e8-6f42-4d03-b78d-ae72a302be94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=930276502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.930276502
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.706324243
Short name T1148
Test name
Test status
Simulation time 4655132515 ps
CPU time 7.52 seconds
Started May 19 12:29:23 PM PDT 24
Finished May 19 12:29:32 PM PDT 24
Peak memory 199452 kb
Host smart-4d47fff3-4cf7-4434-acd8-8e70efd9a6ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706324243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.706324243
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2728972988
Short name T1137
Test name
Test status
Simulation time 49926696580 ps
CPU time 22.71 seconds
Started May 19 12:29:14 PM PDT 24
Finished May 19 12:29:38 PM PDT 24
Peak memory 200224 kb
Host smart-a345f5fb-b341-4d25-a8e0-8aa863eb61f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728972988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2728972988
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3296740817
Short name T4
Test name
Test status
Simulation time 6303476316 ps
CPU time 3.14 seconds
Started May 19 12:29:27 PM PDT 24
Finished May 19 12:29:31 PM PDT 24
Peak memory 196372 kb
Host smart-b9aa0913-ab83-4990-a39f-2bae8b9af2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296740817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3296740817
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3526093475
Short name T983
Test name
Test status
Simulation time 887995845 ps
CPU time 3.59 seconds
Started May 19 12:29:32 PM PDT 24
Finished May 19 12:29:37 PM PDT 24
Peak memory 200136 kb
Host smart-e53f116d-7d1f-4a2b-bc5d-e75c5d200e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526093475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3526093475
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3366857356
Short name T774
Test name
Test status
Simulation time 357937725677 ps
CPU time 297.78 seconds
Started May 19 12:29:53 PM PDT 24
Finished May 19 12:34:58 PM PDT 24
Peak memory 216392 kb
Host smart-be7831c5-051b-4b02-83df-a01d086ba897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366857356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3366857356
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3535900876
Short name T893
Test name
Test status
Simulation time 982240122 ps
CPU time 3.52 seconds
Started May 19 12:29:36 PM PDT 24
Finished May 19 12:29:42 PM PDT 24
Peak memory 199756 kb
Host smart-9c7ba176-fdec-4228-840a-3aaaabecd5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535900876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3535900876
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2810396798
Short name T331
Test name
Test status
Simulation time 32599136769 ps
CPU time 56.83 seconds
Started May 19 12:29:58 PM PDT 24
Finished May 19 12:31:02 PM PDT 24
Peak memory 200332 kb
Host smart-0cc6a0f6-98dc-4679-b249-a98318a2b4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810396798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2810396798
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3151866940
Short name T855
Test name
Test status
Simulation time 13947408444 ps
CPU time 22.44 seconds
Started May 19 12:31:16 PM PDT 24
Finished May 19 12:31:39 PM PDT 24
Peak memory 200232 kb
Host smart-f473f0ed-5641-459d-b3d4-d8a0adbec0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151866940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3151866940
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.4117089890
Short name T543
Test name
Test status
Simulation time 137253275303 ps
CPU time 94.18 seconds
Started May 19 12:31:13 PM PDT 24
Finished May 19 12:32:48 PM PDT 24
Peak memory 200332 kb
Host smart-49a8051d-3e62-4588-9f85-2942b12b9438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117089890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.4117089890
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3992721483
Short name T1004
Test name
Test status
Simulation time 44803300295 ps
CPU time 40.31 seconds
Started May 19 12:31:15 PM PDT 24
Finished May 19 12:31:56 PM PDT 24
Peak memory 200056 kb
Host smart-917b1ac5-f7c5-4aa8-91a0-e34bf2e55bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992721483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3992721483
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.512700405
Short name T428
Test name
Test status
Simulation time 78752739644 ps
CPU time 34.57 seconds
Started May 19 12:31:20 PM PDT 24
Finished May 19 12:31:56 PM PDT 24
Peak memory 200208 kb
Host smart-3b7cc63d-def3-46c8-b695-b94428d5fe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512700405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.512700405
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.468007597
Short name T802
Test name
Test status
Simulation time 111596592050 ps
CPU time 26.49 seconds
Started May 19 12:31:20 PM PDT 24
Finished May 19 12:31:48 PM PDT 24
Peak memory 200356 kb
Host smart-c37ce1bb-75f5-46d4-b682-568b4838964d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468007597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.468007597
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1946354440
Short name T203
Test name
Test status
Simulation time 23053365467 ps
CPU time 35.31 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:31:58 PM PDT 24
Peak memory 200152 kb
Host smart-c53a3b77-0f85-4825-8048-deb20df96588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946354440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1946354440
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.4096532420
Short name T554
Test name
Test status
Simulation time 124577707522 ps
CPU time 113.68 seconds
Started May 19 12:31:14 PM PDT 24
Finished May 19 12:33:09 PM PDT 24
Peak memory 200300 kb
Host smart-3e55c240-ff4f-44ba-b4d8-493eb6b9f89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096532420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.4096532420
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3269212730
Short name T761
Test name
Test status
Simulation time 80897265339 ps
CPU time 13.52 seconds
Started May 19 12:31:20 PM PDT 24
Finished May 19 12:31:36 PM PDT 24
Peak memory 199968 kb
Host smart-5c4a45f9-f8a2-4b2a-b178-74d5dcf1558a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269212730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3269212730
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3247895534
Short name T158
Test name
Test status
Simulation time 311287186569 ps
CPU time 45.23 seconds
Started May 19 12:31:19 PM PDT 24
Finished May 19 12:32:05 PM PDT 24
Peak memory 200240 kb
Host smart-4bca0f18-fca1-49b9-855d-d449cc08f5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247895534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3247895534
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2611509759
Short name T752
Test name
Test status
Simulation time 36406736 ps
CPU time 0.57 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:29:51 PM PDT 24
Peak memory 195684 kb
Host smart-0f7068a9-705b-498a-89e4-68e3328fa165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611509759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2611509759
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3647238767
Short name T145
Test name
Test status
Simulation time 256644583934 ps
CPU time 295.43 seconds
Started May 19 12:29:15 PM PDT 24
Finished May 19 12:34:11 PM PDT 24
Peak memory 200248 kb
Host smart-69bd4e94-a757-4f4f-b9c0-2f9eeede7643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647238767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3647238767
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3202047515
Short name T578
Test name
Test status
Simulation time 35213042438 ps
CPU time 40.69 seconds
Started May 19 12:30:32 PM PDT 24
Finished May 19 12:31:16 PM PDT 24
Peak memory 198312 kb
Host smart-53a1d3fb-5093-45bc-9fc6-a2eea5a08c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202047515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3202047515
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2770014946
Short name T17
Test name
Test status
Simulation time 232972498737 ps
CPU time 103.42 seconds
Started May 19 12:29:29 PM PDT 24
Finished May 19 12:31:13 PM PDT 24
Peak memory 200260 kb
Host smart-edc71396-7b32-4876-9a15-4d2e40376326
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770014946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2770014946
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1709315214
Short name T646
Test name
Test status
Simulation time 97211925409 ps
CPU time 205.75 seconds
Started May 19 12:29:22 PM PDT 24
Finished May 19 12:32:48 PM PDT 24
Peak memory 200340 kb
Host smart-50824657-7948-4480-8cd3-f21aa81cf228
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709315214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1709315214
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1029225700
Short name T1028
Test name
Test status
Simulation time 7575627099 ps
CPU time 4.49 seconds
Started May 19 12:29:37 PM PDT 24
Finished May 19 12:29:44 PM PDT 24
Peak memory 199684 kb
Host smart-2a409d43-6196-4dff-a92d-f550d51821b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029225700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1029225700
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1819484595
Short name T479
Test name
Test status
Simulation time 48019555551 ps
CPU time 42.24 seconds
Started May 19 12:29:27 PM PDT 24
Finished May 19 12:30:10 PM PDT 24
Peak memory 200524 kb
Host smart-3961cd0f-8ad9-474b-b622-b59fc5fd3caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819484595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1819484595
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3993987599
Short name T332
Test name
Test status
Simulation time 18618071246 ps
CPU time 458.26 seconds
Started May 19 12:29:33 PM PDT 24
Finished May 19 12:37:13 PM PDT 24
Peak memory 200216 kb
Host smart-94cc41c2-1495-4038-8d72-4e22c8acd79e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3993987599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3993987599
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2238593498
Short name T667
Test name
Test status
Simulation time 5587340307 ps
CPU time 12.81 seconds
Started May 19 12:30:45 PM PDT 24
Finished May 19 12:31:01 PM PDT 24
Peak memory 199408 kb
Host smart-492a8df9-d359-4059-851d-51c7aa7e4a83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2238593498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2238593498
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2170087028
Short name T930
Test name
Test status
Simulation time 58093345821 ps
CPU time 21.13 seconds
Started May 19 12:29:58 PM PDT 24
Finished May 19 12:30:26 PM PDT 24
Peak memory 200284 kb
Host smart-ffd3d2e7-ba38-48e7-9e32-0054a27be7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170087028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2170087028
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1472679274
Short name T434
Test name
Test status
Simulation time 3248321031 ps
CPU time 5.63 seconds
Started May 19 12:29:40 PM PDT 24
Finished May 19 12:29:48 PM PDT 24
Peak memory 196608 kb
Host smart-201a209e-d61c-4709-97b9-96b7b98d3397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472679274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1472679274
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2233729801
Short name T1151
Test name
Test status
Simulation time 5735541187 ps
CPU time 9.19 seconds
Started May 19 12:29:43 PM PDT 24
Finished May 19 12:29:54 PM PDT 24
Peak memory 200264 kb
Host smart-f2d175a6-513f-4d63-be68-8ed63008ae18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233729801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2233729801
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.4209605916
Short name T1074
Test name
Test status
Simulation time 24837494634 ps
CPU time 353.08 seconds
Started May 19 12:30:47 PM PDT 24
Finished May 19 12:36:41 PM PDT 24
Peak memory 208756 kb
Host smart-8457b278-b866-48b8-bce8-7314276aac2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209605916 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.4209605916
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1636537254
Short name T652
Test name
Test status
Simulation time 667449518 ps
CPU time 2.73 seconds
Started May 19 12:29:33 PM PDT 24
Finished May 19 12:29:38 PM PDT 24
Peak memory 199904 kb
Host smart-37696640-1014-433e-9837-e69598634251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636537254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1636537254
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1634405538
Short name T390
Test name
Test status
Simulation time 59578646996 ps
CPU time 25.91 seconds
Started May 19 12:29:34 PM PDT 24
Finished May 19 12:30:03 PM PDT 24
Peak memory 200348 kb
Host smart-a688cb1f-bccb-481a-bbd1-2e1b53197e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634405538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1634405538
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3930376239
Short name T201
Test name
Test status
Simulation time 33723545640 ps
CPU time 57.62 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:32:21 PM PDT 24
Peak memory 200376 kb
Host smart-55440711-db29-4400-9c75-6ab7d4a1d8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930376239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3930376239
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.810935183
Short name T679
Test name
Test status
Simulation time 116163186268 ps
CPU time 201.77 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:34:45 PM PDT 24
Peak memory 200296 kb
Host smart-0c5681e7-b7fd-4690-8764-a334e2a793b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810935183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.810935183
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.577651774
Short name T469
Test name
Test status
Simulation time 297926844763 ps
CPU time 141.11 seconds
Started May 19 12:31:23 PM PDT 24
Finished May 19 12:33:46 PM PDT 24
Peak memory 200384 kb
Host smart-05e7ccbb-2ac8-4671-8c7a-1b69fff93174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577651774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.577651774
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.4207273649
Short name T144
Test name
Test status
Simulation time 14081194664 ps
CPU time 11.84 seconds
Started May 19 12:31:19 PM PDT 24
Finished May 19 12:31:32 PM PDT 24
Peak memory 200272 kb
Host smart-950bf51a-7df4-4a31-a2a1-4eb40517a62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207273649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.4207273649
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3105681544
Short name T1017
Test name
Test status
Simulation time 25265868646 ps
CPU time 20.38 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:31:44 PM PDT 24
Peak memory 200204 kb
Host smart-7cb67a87-eb11-4641-9653-0fe1d7031c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105681544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3105681544
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3007702063
Short name T520
Test name
Test status
Simulation time 178239616212 ps
CPU time 73.26 seconds
Started May 19 12:31:22 PM PDT 24
Finished May 19 12:32:37 PM PDT 24
Peak memory 200260 kb
Host smart-ea2b8294-c0fc-4047-9a0c-af98fb5feb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007702063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3007702063
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1568652318
Short name T810
Test name
Test status
Simulation time 26050901030 ps
CPU time 23.66 seconds
Started May 19 12:31:19 PM PDT 24
Finished May 19 12:31:44 PM PDT 24
Peak memory 200240 kb
Host smart-a33b5da9-cff9-4cf6-9fae-865468421561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568652318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1568652318
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2883709326
Short name T562
Test name
Test status
Simulation time 26970542031 ps
CPU time 21.28 seconds
Started May 19 12:31:20 PM PDT 24
Finished May 19 12:31:43 PM PDT 24
Peak memory 200276 kb
Host smart-6cddbd33-ee2d-481a-bf9e-c4d5c99de39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883709326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2883709326
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3349124859
Short name T923
Test name
Test status
Simulation time 41290337 ps
CPU time 0.57 seconds
Started May 19 12:29:54 PM PDT 24
Finished May 19 12:30:02 PM PDT 24
Peak memory 195680 kb
Host smart-fb1ed305-86f5-4f78-aa01-a2cead022b63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349124859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3349124859
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2939522884
Short name T149
Test name
Test status
Simulation time 44879052284 ps
CPU time 41.64 seconds
Started May 19 12:29:31 PM PDT 24
Finished May 19 12:30:14 PM PDT 24
Peak memory 200364 kb
Host smart-523ef2a4-c5ae-4612-b3f2-b9e68b22cee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939522884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2939522884
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.190324570
Short name T833
Test name
Test status
Simulation time 82982589521 ps
CPU time 69.73 seconds
Started May 19 12:29:34 PM PDT 24
Finished May 19 12:30:47 PM PDT 24
Peak memory 200324 kb
Host smart-569ee57f-0514-4c9c-859d-8bd7c0027a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190324570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.190324570
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.473139043
Short name T1081
Test name
Test status
Simulation time 207916273128 ps
CPU time 89.19 seconds
Started May 19 12:29:56 PM PDT 24
Finished May 19 12:31:32 PM PDT 24
Peak memory 200288 kb
Host smart-2da536dd-ad98-4631-977e-054bd04c80d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473139043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.473139043
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3212208741
Short name T594
Test name
Test status
Simulation time 513836085212 ps
CPU time 226.66 seconds
Started May 19 12:29:18 PM PDT 24
Finished May 19 12:33:06 PM PDT 24
Peak memory 199288 kb
Host smart-73d2c33c-f0ce-4bfb-8453-2c68effce52f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212208741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3212208741
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3418802942
Short name T261
Test name
Test status
Simulation time 62739228787 ps
CPU time 288.73 seconds
Started May 19 12:29:50 PM PDT 24
Finished May 19 12:34:47 PM PDT 24
Peak memory 200312 kb
Host smart-2dbb178a-afbc-480a-9082-3c1a495cbf6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3418802942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3418802942
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3663622768
Short name T2
Test name
Test status
Simulation time 368566792 ps
CPU time 0.85 seconds
Started May 19 12:29:31 PM PDT 24
Finished May 19 12:29:34 PM PDT 24
Peak memory 195764 kb
Host smart-90b7c469-2655-4086-ad82-7e33d2972754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663622768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3663622768
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.584680250
Short name T103
Test name
Test status
Simulation time 33008121119 ps
CPU time 55.88 seconds
Started May 19 12:29:35 PM PDT 24
Finished May 19 12:30:33 PM PDT 24
Peak memory 199008 kb
Host smart-460654b7-378d-4ea2-a364-5633d617f6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584680250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.584680250
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3742269536
Short name T249
Test name
Test status
Simulation time 19117534962 ps
CPU time 669.41 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:41:06 PM PDT 24
Peak memory 200208 kb
Host smart-4a0b9a33-8ec1-4a73-b9db-96e754a1c540
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3742269536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3742269536
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3585320195
Short name T405
Test name
Test status
Simulation time 4826539373 ps
CPU time 10.5 seconds
Started May 19 12:30:32 PM PDT 24
Finished May 19 12:30:46 PM PDT 24
Peak memory 197764 kb
Host smart-47c460a1-fd71-4cd8-b25c-05a73679e675
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585320195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3585320195
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.426953739
Short name T925
Test name
Test status
Simulation time 10430066059 ps
CPU time 15.22 seconds
Started May 19 12:29:39 PM PDT 24
Finished May 19 12:29:56 PM PDT 24
Peak memory 200048 kb
Host smart-c0bac1e1-d60e-4135-af11-24102bcccbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426953739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.426953739
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.369844517
Short name T1041
Test name
Test status
Simulation time 3900248362 ps
CPU time 3.96 seconds
Started May 19 12:29:31 PM PDT 24
Finished May 19 12:29:37 PM PDT 24
Peak memory 196300 kb
Host smart-f22792b6-1929-4944-9eb2-a771070724a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369844517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.369844517
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.382139566
Short name T1085
Test name
Test status
Simulation time 482501212 ps
CPU time 1.24 seconds
Started May 19 12:30:05 PM PDT 24
Finished May 19 12:30:13 PM PDT 24
Peak memory 200188 kb
Host smart-31e5768d-48dc-431b-9f26-9dccfe49e719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382139566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.382139566
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2962451265
Short name T1013
Test name
Test status
Simulation time 240885971861 ps
CPU time 709.81 seconds
Started May 19 12:29:24 PM PDT 24
Finished May 19 12:41:15 PM PDT 24
Peak memory 200592 kb
Host smart-175f521f-f174-45a4-ab73-7acd8f60cc5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962451265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2962451265
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.4129328208
Short name T458
Test name
Test status
Simulation time 26316192756 ps
CPU time 196.25 seconds
Started May 19 12:30:45 PM PDT 24
Finished May 19 12:34:04 PM PDT 24
Peak memory 216388 kb
Host smart-072de88a-abf9-401b-bced-829924dbc35e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129328208 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.4129328208
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.65065883
Short name T981
Test name
Test status
Simulation time 1521732660 ps
CPU time 2.64 seconds
Started May 19 12:29:33 PM PDT 24
Finished May 19 12:29:38 PM PDT 24
Peak memory 200192 kb
Host smart-cc1477c6-34b8-4fa9-9db5-99fc16ecfad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65065883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.65065883
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.4269389262
Short name T531
Test name
Test status
Simulation time 64466124634 ps
CPU time 127.83 seconds
Started May 19 12:29:59 PM PDT 24
Finished May 19 12:32:14 PM PDT 24
Peak memory 200320 kb
Host smart-d410c079-1d2e-46e5-800a-b0f76c1c3914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269389262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.4269389262
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1113177659
Short name T990
Test name
Test status
Simulation time 203791387556 ps
CPU time 44.05 seconds
Started May 19 12:31:26 PM PDT 24
Finished May 19 12:32:11 PM PDT 24
Peak memory 200212 kb
Host smart-35bb5cba-30cd-498a-8ff6-17f8a3e9357d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113177659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1113177659
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.4046821921
Short name T483
Test name
Test status
Simulation time 118941872504 ps
CPU time 108.73 seconds
Started May 19 12:31:18 PM PDT 24
Finished May 19 12:33:07 PM PDT 24
Peak memory 200272 kb
Host smart-233e6afd-5a04-4444-ab99-a011a86064eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046821921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.4046821921
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1437727523
Short name T915
Test name
Test status
Simulation time 109551227723 ps
CPU time 106.52 seconds
Started May 19 12:31:20 PM PDT 24
Finished May 19 12:33:08 PM PDT 24
Peak memory 200368 kb
Host smart-1c02d94c-774b-4dde-9b51-04d804eb38fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437727523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1437727523
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1565735517
Short name T910
Test name
Test status
Simulation time 51174162190 ps
CPU time 64.99 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:32:29 PM PDT 24
Peak memory 200300 kb
Host smart-2dd24bc2-5b48-4477-97ae-8e3fb9ebed0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565735517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1565735517
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.4167570590
Short name T186
Test name
Test status
Simulation time 119826590766 ps
CPU time 95.62 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:32:59 PM PDT 24
Peak memory 200276 kb
Host smart-b3f05564-8c99-47ef-9946-8710384c7a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167570590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4167570590
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1798479381
Short name T189
Test name
Test status
Simulation time 29216506013 ps
CPU time 53.73 seconds
Started May 19 12:31:19 PM PDT 24
Finished May 19 12:32:13 PM PDT 24
Peak memory 200340 kb
Host smart-d4af7249-88d6-4126-836f-dc9dcb435e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798479381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1798479381
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1064126387
Short name T387
Test name
Test status
Simulation time 24346334894 ps
CPU time 39.78 seconds
Started May 19 12:31:22 PM PDT 24
Finished May 19 12:32:04 PM PDT 24
Peak memory 200544 kb
Host smart-56c5af84-f95c-4937-ac5c-f375a8347f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064126387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1064126387
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2996322439
Short name T1112
Test name
Test status
Simulation time 10056764281 ps
CPU time 7.5 seconds
Started May 19 12:31:23 PM PDT 24
Finished May 19 12:31:32 PM PDT 24
Peak memory 200300 kb
Host smart-97159dfe-1505-4e8f-9ce7-d61cc018f1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996322439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2996322439
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3386984590
Short name T1164
Test name
Test status
Simulation time 162453365070 ps
CPU time 361.26 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:37:24 PM PDT 24
Peak memory 200308 kb
Host smart-08f1223b-2cb5-4978-b471-61e4e72d3dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386984590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3386984590
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.4005743968
Short name T885
Test name
Test status
Simulation time 19916952 ps
CPU time 0.56 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:29:53 PM PDT 24
Peak memory 195684 kb
Host smart-8f7cb28b-fc54-42c1-b257-c04c4045ddb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005743968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.4005743968
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1392313150
Short name T431
Test name
Test status
Simulation time 41870086091 ps
CPU time 34.77 seconds
Started May 19 12:29:11 PM PDT 24
Finished May 19 12:29:46 PM PDT 24
Peak memory 200280 kb
Host smart-bf90a7a8-6640-4fe1-9d4a-209cda18d49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392313150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1392313150
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1380348739
Short name T584
Test name
Test status
Simulation time 82575563993 ps
CPU time 134.91 seconds
Started May 19 12:29:35 PM PDT 24
Finished May 19 12:31:52 PM PDT 24
Peak memory 200708 kb
Host smart-5815ad1c-3ace-487e-800f-5b36981cddbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380348739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1380348739
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1665524552
Short name T546
Test name
Test status
Simulation time 20695382288 ps
CPU time 18.03 seconds
Started May 19 12:29:37 PM PDT 24
Finished May 19 12:29:57 PM PDT 24
Peak memory 200036 kb
Host smart-387fec1c-a21a-4179-8641-afd07d55ca02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665524552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1665524552
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.321556563
Short name T104
Test name
Test status
Simulation time 186736228517 ps
CPU time 342.14 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:35:35 PM PDT 24
Peak memory 200252 kb
Host smart-ddec7eb1-4c74-4096-8f52-735c5510251e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321556563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.321556563
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.863605082
Short name T624
Test name
Test status
Simulation time 99471893701 ps
CPU time 766.37 seconds
Started May 19 12:29:41 PM PDT 24
Finished May 19 12:42:29 PM PDT 24
Peak memory 200324 kb
Host smart-1a1886fe-8d9b-4364-97db-c35dd19deb43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=863605082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.863605082
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.4042009949
Short name T967
Test name
Test status
Simulation time 5148114129 ps
CPU time 3.6 seconds
Started May 19 12:29:38 PM PDT 24
Finished May 19 12:29:44 PM PDT 24
Peak memory 199904 kb
Host smart-1992e815-12e7-4bc7-b1fd-fc819c2963aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042009949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.4042009949
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2808600756
Short name T869
Test name
Test status
Simulation time 79984587716 ps
CPU time 51.23 seconds
Started May 19 12:29:37 PM PDT 24
Finished May 19 12:30:30 PM PDT 24
Peak memory 200552 kb
Host smart-27d3edf8-b2ab-46bb-a514-0c54df82e844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808600756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2808600756
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.2686816846
Short name T980
Test name
Test status
Simulation time 5822653331 ps
CPU time 339.44 seconds
Started May 19 12:29:36 PM PDT 24
Finished May 19 12:35:18 PM PDT 24
Peak memory 200320 kb
Host smart-65e6fd7e-13da-47cf-a71b-ec2ca9d2d24f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2686816846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2686816846
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.699249879
Short name T837
Test name
Test status
Simulation time 2927783214 ps
CPU time 24.2 seconds
Started May 19 12:29:23 PM PDT 24
Finished May 19 12:29:48 PM PDT 24
Peak memory 198608 kb
Host smart-bb8ffd35-8e51-489c-8d0f-9d72933b24f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=699249879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.699249879
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3993494120
Short name T648
Test name
Test status
Simulation time 31926864991 ps
CPU time 30.86 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:30:25 PM PDT 24
Peak memory 200168 kb
Host smart-5dcc209d-0169-49d6-9dc2-de0530895474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993494120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3993494120
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.697407028
Short name T744
Test name
Test status
Simulation time 2981296224 ps
CPU time 1.1 seconds
Started May 19 12:29:43 PM PDT 24
Finished May 19 12:29:46 PM PDT 24
Peak memory 196240 kb
Host smart-7784479b-ba69-493f-a833-b949059ca35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697407028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.697407028
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3950528740
Short name T912
Test name
Test status
Simulation time 629823125 ps
CPU time 3.32 seconds
Started May 19 12:29:22 PM PDT 24
Finished May 19 12:29:26 PM PDT 24
Peak memory 199780 kb
Host smart-8c92e1c7-d31e-45bc-9aef-cf6b9a041f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950528740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3950528740
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3030068519
Short name T907
Test name
Test status
Simulation time 14017950169 ps
CPU time 45.27 seconds
Started May 19 12:29:41 PM PDT 24
Finished May 19 12:30:28 PM PDT 24
Peak memory 200244 kb
Host smart-83e31cdb-4f32-4e92-9f1d-72c9da702795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030068519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3030068519
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3310496506
Short name T807
Test name
Test status
Simulation time 66597781704 ps
CPU time 889.13 seconds
Started May 19 12:29:34 PM PDT 24
Finished May 19 12:44:26 PM PDT 24
Peak memory 216804 kb
Host smart-81b74a92-2318-4bec-addb-e15408796704
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310496506 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3310496506
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1713343888
Short name T528
Test name
Test status
Simulation time 1662716200 ps
CPU time 1.75 seconds
Started May 19 12:29:42 PM PDT 24
Finished May 19 12:29:46 PM PDT 24
Peak memory 199032 kb
Host smart-9099e7d2-6483-4a77-8ccc-bb7580aafd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713343888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1713343888
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2950463971
Short name T1102
Test name
Test status
Simulation time 56385651842 ps
CPU time 170.49 seconds
Started May 19 12:29:28 PM PDT 24
Finished May 19 12:32:20 PM PDT 24
Peak memory 200244 kb
Host smart-bc181819-dcac-4ac1-b69c-f13d3e5fe100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950463971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2950463971
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2493674330
Short name T233
Test name
Test status
Simulation time 57412816999 ps
CPU time 49.95 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:32:13 PM PDT 24
Peak memory 200252 kb
Host smart-446eae48-7d6f-431e-bca9-bd5e6e712ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493674330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2493674330
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3833340030
Short name T1135
Test name
Test status
Simulation time 37424710563 ps
CPU time 27.4 seconds
Started May 19 12:31:25 PM PDT 24
Finished May 19 12:31:53 PM PDT 24
Peak memory 200368 kb
Host smart-e648da94-25e5-4640-92ae-e886dccb5691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833340030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3833340030
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3439941441
Short name T651
Test name
Test status
Simulation time 152602554006 ps
CPU time 95.67 seconds
Started May 19 12:31:22 PM PDT 24
Finished May 19 12:33:00 PM PDT 24
Peak memory 200248 kb
Host smart-39f378c4-92cf-499e-bde5-0e85cd8a46c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439941441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3439941441
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3657387675
Short name T206
Test name
Test status
Simulation time 61693341792 ps
CPU time 28.26 seconds
Started May 19 12:31:19 PM PDT 24
Finished May 19 12:31:49 PM PDT 24
Peak memory 200216 kb
Host smart-25aae29b-bc96-416b-b8d5-7bbfb712b4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657387675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3657387675
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1402341495
Short name T196
Test name
Test status
Simulation time 56332839020 ps
CPU time 45.7 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:32:09 PM PDT 24
Peak memory 200400 kb
Host smart-6bd18b78-447d-47cd-9036-cc6cddfd1a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402341495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1402341495
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.372336693
Short name T132
Test name
Test status
Simulation time 37340802853 ps
CPU time 15.88 seconds
Started May 19 12:31:18 PM PDT 24
Finished May 19 12:31:36 PM PDT 24
Peak memory 200332 kb
Host smart-89f4c05b-5490-4aa3-b2b9-bd245a2f8710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372336693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.372336693
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1586828140
Short name T340
Test name
Test status
Simulation time 20721471246 ps
CPU time 48.6 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:32:11 PM PDT 24
Peak memory 200200 kb
Host smart-b13695a0-3b62-4440-9b94-d6c6c64ee4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586828140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1586828140
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.477502420
Short name T214
Test name
Test status
Simulation time 111769345499 ps
CPU time 48.07 seconds
Started May 19 12:31:30 PM PDT 24
Finished May 19 12:32:19 PM PDT 24
Peak memory 200268 kb
Host smart-d44d32f6-3df2-48b5-b717-4d28ebc21b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477502420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.477502420
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2129415711
Short name T355
Test name
Test status
Simulation time 12268909 ps
CPU time 0.57 seconds
Started May 19 12:29:50 PM PDT 24
Finished May 19 12:29:59 PM PDT 24
Peak memory 195700 kb
Host smart-54bf10a9-211a-407d-893b-33c05155d69e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129415711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2129415711
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1021981306
Short name T1126
Test name
Test status
Simulation time 108305303553 ps
CPU time 55.35 seconds
Started May 19 12:29:42 PM PDT 24
Finished May 19 12:30:40 PM PDT 24
Peak memory 200248 kb
Host smart-58d24e56-f352-4a58-8bcb-b4f3f9813289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021981306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1021981306
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2100897685
Short name T114
Test name
Test status
Simulation time 115405992365 ps
CPU time 160.35 seconds
Started May 19 12:29:30 PM PDT 24
Finished May 19 12:32:12 PM PDT 24
Peak memory 200244 kb
Host smart-c7c05313-d487-4961-b176-248898dd180b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100897685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2100897685
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1568347443
Short name T954
Test name
Test status
Simulation time 85497009099 ps
CPU time 169.82 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:32:46 PM PDT 24
Peak memory 200256 kb
Host smart-3c83e799-56ae-48a6-b67f-edabfb5f2078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568347443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1568347443
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1184403155
Short name T573
Test name
Test status
Simulation time 202853077911 ps
CPU time 207.22 seconds
Started May 19 12:29:28 PM PDT 24
Finished May 19 12:32:57 PM PDT 24
Peak memory 199812 kb
Host smart-2ce2ba57-8c12-483b-8ca1-e701cef5d017
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184403155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1184403155
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2971721941
Short name T755
Test name
Test status
Simulation time 44974571103 ps
CPU time 165.04 seconds
Started May 19 12:29:43 PM PDT 24
Finished May 19 12:32:30 PM PDT 24
Peak memory 200244 kb
Host smart-2e1c60d2-9c1d-4f9e-b3cb-0ea89ed2a4a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2971721941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2971721941
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.555926787
Short name T498
Test name
Test status
Simulation time 6645019344 ps
CPU time 3.18 seconds
Started May 19 12:30:32 PM PDT 24
Finished May 19 12:30:39 PM PDT 24
Peak memory 197296 kb
Host smart-ac01e863-5a18-41af-aa79-dfc8990332d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555926787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.555926787
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3712742972
Short name T694
Test name
Test status
Simulation time 59772951552 ps
CPU time 92.01 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:31:26 PM PDT 24
Peak memory 200956 kb
Host smart-41b14ead-7b73-4816-ae84-6ef2af6c41cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712742972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3712742972
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3595797360
Short name T792
Test name
Test status
Simulation time 13164855186 ps
CPU time 489.94 seconds
Started May 19 12:29:34 PM PDT 24
Finished May 19 12:37:47 PM PDT 24
Peak memory 200216 kb
Host smart-01762449-d39c-432b-b03d-2481bdbe09ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595797360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3595797360
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2814433535
Short name T977
Test name
Test status
Simulation time 5897969508 ps
CPU time 29.19 seconds
Started May 19 12:29:41 PM PDT 24
Finished May 19 12:30:12 PM PDT 24
Peak memory 198440 kb
Host smart-75319a88-7b87-4d9c-a7a8-519d0db77cc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2814433535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2814433535
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3557528084
Short name T740
Test name
Test status
Simulation time 82280295972 ps
CPU time 35.19 seconds
Started May 19 12:29:45 PM PDT 24
Finished May 19 12:30:24 PM PDT 24
Peak memory 200312 kb
Host smart-68f923f4-df4f-4888-8996-3a65168af020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557528084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3557528084
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2682890023
Short name T271
Test name
Test status
Simulation time 37049690364 ps
CPU time 8.06 seconds
Started May 19 12:29:41 PM PDT 24
Finished May 19 12:29:51 PM PDT 24
Peak memory 195984 kb
Host smart-d42c0048-f901-470c-a291-dd9990508665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682890023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2682890023
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2882614880
Short name T979
Test name
Test status
Simulation time 6054777783 ps
CPU time 8.47 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:30:01 PM PDT 24
Peak memory 200264 kb
Host smart-4e5d85f7-bcca-4134-99f8-a00cc1d92581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882614880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2882614880
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1602838638
Short name T696
Test name
Test status
Simulation time 494727115786 ps
CPU time 742.49 seconds
Started May 19 12:29:42 PM PDT 24
Finished May 19 12:42:07 PM PDT 24
Peak memory 230216 kb
Host smart-d4ecfee5-6277-4a49-9a0b-8fc208a50042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602838638 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1602838638
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.502082123
Short name T1000
Test name
Test status
Simulation time 7527453368 ps
CPU time 1.89 seconds
Started May 19 12:29:35 PM PDT 24
Finished May 19 12:29:39 PM PDT 24
Peak memory 199372 kb
Host smart-17240169-84a4-4222-9fc4-525748f4a417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502082123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.502082123
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2395821578
Short name T1046
Test name
Test status
Simulation time 80515076153 ps
CPU time 145.3 seconds
Started May 19 12:30:43 PM PDT 24
Finished May 19 12:33:12 PM PDT 24
Peak memory 200276 kb
Host smart-d6c231da-74e0-4121-9fad-0881585e82d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395821578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2395821578
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3227508813
Short name T167
Test name
Test status
Simulation time 49203621723 ps
CPU time 14.01 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:31:37 PM PDT 24
Peak memory 199968 kb
Host smart-d86d1a6e-d08c-494a-aaf8-9218c251e0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227508813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3227508813
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1531928288
Short name T876
Test name
Test status
Simulation time 15985437255 ps
CPU time 15.23 seconds
Started May 19 12:31:22 PM PDT 24
Finished May 19 12:31:40 PM PDT 24
Peak memory 200280 kb
Host smart-30d32f7e-c854-4aff-97a6-fe97bfb93e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531928288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1531928288
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3618947292
Short name T640
Test name
Test status
Simulation time 159623309653 ps
CPU time 90.12 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:32:54 PM PDT 24
Peak memory 200320 kb
Host smart-9ecefc90-1755-480f-b078-1afcf9849f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618947292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3618947292
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.4180227706
Short name T851
Test name
Test status
Simulation time 86361196476 ps
CPU time 15.42 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:31:38 PM PDT 24
Peak memory 200364 kb
Host smart-a6c26646-9898-4645-94e2-fa6ae31a0091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180227706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.4180227706
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1275802934
Short name T299
Test name
Test status
Simulation time 111204102997 ps
CPU time 27.17 seconds
Started May 19 12:31:19 PM PDT 24
Finished May 19 12:31:48 PM PDT 24
Peak memory 200348 kb
Host smart-d8996c00-097a-4026-b8e0-bfb038c811f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275802934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1275802934
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3098390531
Short name T154
Test name
Test status
Simulation time 24424529699 ps
CPU time 21.67 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:31:45 PM PDT 24
Peak memory 200364 kb
Host smart-716fa05e-a562-4848-a21c-4addab0f5d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098390531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3098390531
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3910778213
Short name T529
Test name
Test status
Simulation time 56313825325 ps
CPU time 32.74 seconds
Started May 19 12:31:26 PM PDT 24
Finished May 19 12:32:00 PM PDT 24
Peak memory 200276 kb
Host smart-491fa35e-5ef0-4158-848b-bce576ce520e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910778213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3910778213
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3628558636
Short name T303
Test name
Test status
Simulation time 69534984999 ps
CPU time 105.93 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:33:10 PM PDT 24
Peak memory 200332 kb
Host smart-590e2318-5895-4591-a209-18ef0393ae5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628558636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3628558636
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3217614427
Short name T1044
Test name
Test status
Simulation time 23441764404 ps
CPU time 53.73 seconds
Started May 19 12:31:18 PM PDT 24
Finished May 19 12:32:13 PM PDT 24
Peak memory 200220 kb
Host smart-815e2dce-5254-488b-aa34-9075a2de7a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217614427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3217614427
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.430059330
Short name T429
Test name
Test status
Simulation time 42238848 ps
CPU time 0.57 seconds
Started May 19 12:29:39 PM PDT 24
Finished May 19 12:29:41 PM PDT 24
Peak memory 195660 kb
Host smart-93d4c494-0a35-408f-800a-fc4888d3602f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430059330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.430059330
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.780699942
Short name T817
Test name
Test status
Simulation time 28036786621 ps
CPU time 23.62 seconds
Started May 19 12:30:46 PM PDT 24
Finished May 19 12:31:12 PM PDT 24
Peak memory 200224 kb
Host smart-2a4d3bb3-3eb2-49ea-959a-7e03b66c3c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780699942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.780699942
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1148868577
Short name T454
Test name
Test status
Simulation time 57887296310 ps
CPU time 51.98 seconds
Started May 19 12:29:24 PM PDT 24
Finished May 19 12:30:17 PM PDT 24
Peak memory 200264 kb
Host smart-8a183d5f-e9cd-4951-b094-55f46dcfb40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148868577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1148868577
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.3833957413
Short name T435
Test name
Test status
Simulation time 6105617733 ps
CPU time 3.02 seconds
Started May 19 12:29:43 PM PDT 24
Finished May 19 12:29:48 PM PDT 24
Peak memory 197048 kb
Host smart-d773d924-06a4-4cb1-9537-c6e369d3d958
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833957413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3833957413
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1247260770
Short name T868
Test name
Test status
Simulation time 65036160386 ps
CPU time 133.3 seconds
Started May 19 12:29:36 PM PDT 24
Finished May 19 12:31:52 PM PDT 24
Peak memory 200264 kb
Host smart-2ca9eefe-774f-41fa-92e2-a6e8e97bdb90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1247260770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1247260770
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3279460573
Short name T1168
Test name
Test status
Simulation time 10626462525 ps
CPU time 4.01 seconds
Started May 19 12:29:38 PM PDT 24
Finished May 19 12:29:44 PM PDT 24
Peak memory 200176 kb
Host smart-12fae8df-7f90-45c8-a0dc-ae6a8590fc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279460573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3279460573
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1251998038
Short name T260
Test name
Test status
Simulation time 63276739163 ps
CPU time 97.8 seconds
Started May 19 12:29:44 PM PDT 24
Finished May 19 12:31:23 PM PDT 24
Peak memory 200136 kb
Host smart-97701b26-01c4-44e2-95b9-21cc31fb85e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251998038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1251998038
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.17788655
Short name T300
Test name
Test status
Simulation time 16882758858 ps
CPU time 551.12 seconds
Started May 19 12:29:50 PM PDT 24
Finished May 19 12:39:09 PM PDT 24
Peak memory 199960 kb
Host smart-a6f4bc12-b428-4428-975b-a6f00e94c067
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17788655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.17788655
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3230458962
Short name T420
Test name
Test status
Simulation time 3441136719 ps
CPU time 3.29 seconds
Started May 19 12:29:42 PM PDT 24
Finished May 19 12:29:47 PM PDT 24
Peak memory 198480 kb
Host smart-f6b60621-3ff9-4653-816a-860ed8f874fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3230458962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3230458962
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1639145432
Short name T480
Test name
Test status
Simulation time 64892422273 ps
CPU time 133.68 seconds
Started May 19 12:29:32 PM PDT 24
Finished May 19 12:31:48 PM PDT 24
Peak memory 200276 kb
Host smart-40640278-a41c-4dfb-8f0c-70c61689693e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639145432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1639145432
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1037660192
Short name T1144
Test name
Test status
Simulation time 1612394098 ps
CPU time 3.28 seconds
Started May 19 12:29:39 PM PDT 24
Finished May 19 12:29:44 PM PDT 24
Peak memory 195924 kb
Host smart-197a051b-be71-4ed6-94ee-c65b3e9d0fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037660192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1037660192
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.4023292582
Short name T519
Test name
Test status
Simulation time 706949442 ps
CPU time 1.63 seconds
Started May 19 12:30:45 PM PDT 24
Finished May 19 12:30:49 PM PDT 24
Peak memory 198908 kb
Host smart-aa7947f7-33ec-45b5-bfe2-3312ba2ab2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023292582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.4023292582
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2848159869
Short name T953
Test name
Test status
Simulation time 110422043431 ps
CPU time 697.24 seconds
Started May 19 12:29:56 PM PDT 24
Finished May 19 12:41:41 PM PDT 24
Peak memory 225288 kb
Host smart-a6d1d831-c90f-4a82-a1f8-68edf6208760
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848159869 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2848159869
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3585711518
Short name T292
Test name
Test status
Simulation time 1646590237 ps
CPU time 1.47 seconds
Started May 19 12:29:42 PM PDT 24
Finished May 19 12:29:46 PM PDT 24
Peak memory 198880 kb
Host smart-8d907357-b4c2-472b-96b5-17a5d3066d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585711518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3585711518
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3350721726
Short name T282
Test name
Test status
Simulation time 96645164592 ps
CPU time 91.36 seconds
Started May 19 12:29:39 PM PDT 24
Finished May 19 12:31:12 PM PDT 24
Peak memory 200672 kb
Host smart-4441a0f9-92fa-431e-ad9b-31c7e6398dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350721726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3350721726
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2540884116
Short name T256
Test name
Test status
Simulation time 213136258687 ps
CPU time 133.37 seconds
Started May 19 12:31:19 PM PDT 24
Finished May 19 12:33:34 PM PDT 24
Peak memory 200288 kb
Host smart-10c58f35-6f30-4593-8f72-f7e553b080dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540884116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2540884116
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.874325749
Short name T133
Test name
Test status
Simulation time 126040067575 ps
CPU time 117.96 seconds
Started May 19 12:31:23 PM PDT 24
Finished May 19 12:33:23 PM PDT 24
Peak memory 200224 kb
Host smart-42d0c725-76eb-4b5d-95d9-e2bf75dc2aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874325749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.874325749
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2446510749
Short name T1014
Test name
Test status
Simulation time 36147209413 ps
CPU time 74.32 seconds
Started May 19 12:31:24 PM PDT 24
Finished May 19 12:32:40 PM PDT 24
Peak memory 200660 kb
Host smart-b0b48571-53a5-46b9-802b-1d1b01817641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446510749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2446510749
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1903057497
Short name T257
Test name
Test status
Simulation time 148799267228 ps
CPU time 24.43 seconds
Started May 19 12:31:24 PM PDT 24
Finished May 19 12:31:50 PM PDT 24
Peak memory 200360 kb
Host smart-b6d9a138-1db2-4f9d-b67f-baca5035092d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903057497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1903057497
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1885660846
Short name T1166
Test name
Test status
Simulation time 130069895873 ps
CPU time 554.79 seconds
Started May 19 12:31:30 PM PDT 24
Finished May 19 12:40:46 PM PDT 24
Peak memory 200320 kb
Host smart-fa081510-4de0-4548-be50-72bbc9c26c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885660846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1885660846
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3892144650
Short name T1136
Test name
Test status
Simulation time 9257267335 ps
CPU time 17.31 seconds
Started May 19 12:31:26 PM PDT 24
Finished May 19 12:31:45 PM PDT 24
Peak memory 200264 kb
Host smart-a409ea87-e206-4767-9b16-acf315219478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892144650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3892144650
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2883739221
Short name T1057
Test name
Test status
Simulation time 104548699965 ps
CPU time 204.86 seconds
Started May 19 12:31:24 PM PDT 24
Finished May 19 12:34:50 PM PDT 24
Peak memory 200324 kb
Host smart-e6ea2515-3e6d-4707-87c9-1751174961fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883739221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2883739221
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.4138568275
Short name T889
Test name
Test status
Simulation time 28701454562 ps
CPU time 13.91 seconds
Started May 19 12:31:24 PM PDT 24
Finished May 19 12:31:39 PM PDT 24
Peak memory 200336 kb
Host smart-261ec021-7192-4b42-8ce6-f03c3cdb4639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138568275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.4138568275
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2207151171
Short name T1053
Test name
Test status
Simulation time 18175780435 ps
CPU time 30.24 seconds
Started May 19 12:31:29 PM PDT 24
Finished May 19 12:32:01 PM PDT 24
Peak memory 200248 kb
Host smart-ec6880f2-ea37-4542-bb87-a06340cb5c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207151171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2207151171
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1143254968
Short name T625
Test name
Test status
Simulation time 103725137700 ps
CPU time 118.67 seconds
Started May 19 12:31:25 PM PDT 24
Finished May 19 12:33:24 PM PDT 24
Peak memory 200412 kb
Host smart-9ea0f016-122b-4539-afb1-b58ca3d9efb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143254968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1143254968
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.105936083
Short name T901
Test name
Test status
Simulation time 27142465 ps
CPU time 0.59 seconds
Started May 19 12:29:42 PM PDT 24
Finished May 19 12:29:45 PM PDT 24
Peak memory 196088 kb
Host smart-da2e04cc-c0f0-47f0-966a-b8210bf6bf82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105936083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.105936083
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.4107430537
Short name T1036
Test name
Test status
Simulation time 63744774524 ps
CPU time 63.03 seconds
Started May 19 12:30:32 PM PDT 24
Finished May 19 12:31:38 PM PDT 24
Peak memory 198296 kb
Host smart-1b87bfcd-06d9-4b57-bc3a-c5c413dbc0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107430537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.4107430537
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1972162710
Short name T988
Test name
Test status
Simulation time 34641891320 ps
CPU time 61.95 seconds
Started May 19 12:29:44 PM PDT 24
Finished May 19 12:30:48 PM PDT 24
Peak memory 200188 kb
Host smart-2b96b7eb-38f7-4d01-a52d-424a4204da42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972162710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1972162710
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.53622484
Short name T742
Test name
Test status
Simulation time 78172963114 ps
CPU time 31.35 seconds
Started May 19 12:29:59 PM PDT 24
Finished May 19 12:30:39 PM PDT 24
Peak memory 200188 kb
Host smart-d866d3f4-f79c-4a64-b881-d75f5857d636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53622484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.53622484
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1926842797
Short name T296
Test name
Test status
Simulation time 7278333285 ps
CPU time 14.36 seconds
Started May 19 12:29:54 PM PDT 24
Finished May 19 12:30:15 PM PDT 24
Peak memory 199736 kb
Host smart-95a61e12-a0db-4e6b-8e38-66ebe2a49497
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926842797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1926842797
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3096899760
Short name T419
Test name
Test status
Simulation time 82137887284 ps
CPU time 364.11 seconds
Started May 19 12:29:28 PM PDT 24
Finished May 19 12:35:34 PM PDT 24
Peak memory 200268 kb
Host smart-bf4554ca-dee5-48bc-a3d7-38acd9cdcd3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3096899760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3096899760
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3334350310
Short name T805
Test name
Test status
Simulation time 1825392348 ps
CPU time 1.46 seconds
Started May 19 12:29:45 PM PDT 24
Finished May 19 12:29:50 PM PDT 24
Peak memory 196272 kb
Host smart-f82b167d-cf76-4dce-a94a-b4b7abb4a54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334350310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3334350310
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3566660048
Short name T1068
Test name
Test status
Simulation time 53876604017 ps
CPU time 23.33 seconds
Started May 19 12:30:00 PM PDT 24
Finished May 19 12:30:31 PM PDT 24
Peak memory 200756 kb
Host smart-1792a68d-4704-4804-9c9b-f00ed65df88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566660048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3566660048
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.302192483
Short name T924
Test name
Test status
Simulation time 12638208879 ps
CPU time 96.8 seconds
Started May 19 12:30:31 PM PDT 24
Finished May 19 12:32:11 PM PDT 24
Peak memory 200016 kb
Host smart-87c4d71f-742a-4bcc-bb58-d21e6b6897f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302192483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.302192483
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2802323548
Short name T719
Test name
Test status
Simulation time 5028327470 ps
CPU time 11.45 seconds
Started May 19 12:29:59 PM PDT 24
Finished May 19 12:30:17 PM PDT 24
Peak memory 198432 kb
Host smart-aeb33797-595a-4568-9fa0-ef694bf55191
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2802323548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2802323548
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3023608475
Short name T1106
Test name
Test status
Simulation time 56448746766 ps
CPU time 64.29 seconds
Started May 19 12:29:37 PM PDT 24
Finished May 19 12:30:43 PM PDT 24
Peak memory 200260 kb
Host smart-aa6ccabe-f5ab-4a48-9273-edf31b1abca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023608475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3023608475
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.4023250847
Short name T962
Test name
Test status
Simulation time 2081112637 ps
CPU time 1.36 seconds
Started May 19 12:30:31 PM PDT 24
Finished May 19 12:30:36 PM PDT 24
Peak memory 195388 kb
Host smart-e7b60884-8abf-4f9c-b7b1-a8ef13932de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023250847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4023250847
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2399864370
Short name T478
Test name
Test status
Simulation time 668954599 ps
CPU time 3 seconds
Started May 19 12:29:41 PM PDT 24
Finished May 19 12:29:46 PM PDT 24
Peak memory 198964 kb
Host smart-86fd50ab-5163-4f20-aa46-4eff271d1c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399864370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2399864370
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2101050909
Short name T1010
Test name
Test status
Simulation time 25543572872 ps
CPU time 40.32 seconds
Started May 19 12:29:42 PM PDT 24
Finished May 19 12:30:24 PM PDT 24
Peak memory 200248 kb
Host smart-759f07d5-23ed-4b73-b35d-4091ff18d14d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101050909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2101050909
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1895876034
Short name T507
Test name
Test status
Simulation time 21733598343 ps
CPU time 156.11 seconds
Started May 19 12:30:31 PM PDT 24
Finished May 19 12:33:11 PM PDT 24
Peak memory 211352 kb
Host smart-fb02e092-6a76-4285-a309-a966e5b7d60c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895876034 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1895876034
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2839866584
Short name T444
Test name
Test status
Simulation time 749452388 ps
CPU time 2.96 seconds
Started May 19 12:29:59 PM PDT 24
Finished May 19 12:30:11 PM PDT 24
Peak memory 199380 kb
Host smart-1a14ca34-65f2-4731-8d0c-ea34f621f71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839866584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2839866584
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1245766149
Short name T883
Test name
Test status
Simulation time 39155074636 ps
CPU time 42.23 seconds
Started May 19 12:30:43 PM PDT 24
Finished May 19 12:31:29 PM PDT 24
Peak memory 200248 kb
Host smart-dcc0a2aa-cae9-46d5-acfe-d8205515af48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245766149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1245766149
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2137033724
Short name T113
Test name
Test status
Simulation time 8528610334 ps
CPU time 8.66 seconds
Started May 19 12:31:24 PM PDT 24
Finished May 19 12:31:34 PM PDT 24
Peak memory 200308 kb
Host smart-a51f00c1-a7b4-4153-be06-b99e26fd2d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137033724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2137033724
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1795311064
Short name T845
Test name
Test status
Simulation time 119331177187 ps
CPU time 47.83 seconds
Started May 19 12:31:28 PM PDT 24
Finished May 19 12:32:17 PM PDT 24
Peak memory 200304 kb
Host smart-b0826b1a-2789-46de-9e58-d76f970ccc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795311064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1795311064
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1614718559
Short name T785
Test name
Test status
Simulation time 17078334861 ps
CPU time 26.49 seconds
Started May 19 12:31:29 PM PDT 24
Finished May 19 12:31:57 PM PDT 24
Peak memory 200212 kb
Host smart-1e28ed07-04d1-4d99-9a27-1786461f2526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614718559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1614718559
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.620406158
Short name T146
Test name
Test status
Simulation time 47984025860 ps
CPU time 45.38 seconds
Started May 19 12:31:25 PM PDT 24
Finished May 19 12:32:12 PM PDT 24
Peak memory 200288 kb
Host smart-18b7d1af-8349-4a24-987c-4d7dd34924ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620406158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.620406158
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.552717188
Short name T1162
Test name
Test status
Simulation time 84418297868 ps
CPU time 65.11 seconds
Started May 19 12:31:27 PM PDT 24
Finished May 19 12:32:33 PM PDT 24
Peak memory 200400 kb
Host smart-56b337f0-fde2-4eb9-9feb-fba373515bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552717188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.552717188
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1333265444
Short name T225
Test name
Test status
Simulation time 54784053541 ps
CPU time 30.87 seconds
Started May 19 12:31:29 PM PDT 24
Finished May 19 12:32:01 PM PDT 24
Peak memory 200324 kb
Host smart-6a2bc57f-b8a0-4d36-8ee9-38bf19c220d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333265444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1333265444
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2361363471
Short name T205
Test name
Test status
Simulation time 48747617979 ps
CPU time 80.76 seconds
Started May 19 12:31:29 PM PDT 24
Finished May 19 12:32:51 PM PDT 24
Peak memory 200308 kb
Host smart-44ec7a0f-7c4a-4884-a2b5-6d83e73767a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361363471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2361363471
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3116642585
Short name T1066
Test name
Test status
Simulation time 91826863 ps
CPU time 0.53 seconds
Started May 19 12:29:41 PM PDT 24
Finished May 19 12:29:43 PM PDT 24
Peak memory 195664 kb
Host smart-d1ecb5e7-e2bd-4fea-b774-00e4bcc5bf11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116642585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3116642585
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3135151802
Short name T559
Test name
Test status
Simulation time 51969362328 ps
CPU time 36.96 seconds
Started May 19 12:29:44 PM PDT 24
Finished May 19 12:30:23 PM PDT 24
Peak memory 200280 kb
Host smart-6648af8b-7c9f-4d76-a120-1f47704533e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135151802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3135151802
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.526507344
Short name T1171
Test name
Test status
Simulation time 56292111621 ps
CPU time 42.94 seconds
Started May 19 12:29:36 PM PDT 24
Finished May 19 12:30:22 PM PDT 24
Peak memory 200312 kb
Host smart-bcceceec-af62-4317-b513-836463af682f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526507344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.526507344
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.431388808
Short name T491
Test name
Test status
Simulation time 7645500509 ps
CPU time 12.22 seconds
Started May 19 12:30:30 PM PDT 24
Finished May 19 12:30:46 PM PDT 24
Peak memory 200096 kb
Host smart-f4bdc61e-c947-407e-b129-3a313b2c3029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431388808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.431388808
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1091195203
Short name T1156
Test name
Test status
Simulation time 37959398368 ps
CPU time 62.31 seconds
Started May 19 12:29:39 PM PDT 24
Finished May 19 12:30:44 PM PDT 24
Peak memory 200180 kb
Host smart-a64cf2f9-f46c-4ea7-9252-f0c9d2c8de29
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091195203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1091195203
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2279772619
Short name T246
Test name
Test status
Simulation time 109746534065 ps
CPU time 492.49 seconds
Started May 19 12:29:34 PM PDT 24
Finished May 19 12:37:49 PM PDT 24
Peak memory 200216 kb
Host smart-3b1ee704-e0a7-48bb-b422-b531bbaaaa5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2279772619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2279772619
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1510637006
Short name T485
Test name
Test status
Simulation time 1102005885 ps
CPU time 2.55 seconds
Started May 19 12:29:54 PM PDT 24
Finished May 19 12:30:04 PM PDT 24
Peak memory 196320 kb
Host smart-2cfcea8a-7c9f-4beb-b853-48c19c8bbf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510637006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1510637006
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1194773481
Short name T574
Test name
Test status
Simulation time 142975624216 ps
CPU time 31.2 seconds
Started May 19 12:30:24 PM PDT 24
Finished May 19 12:30:57 PM PDT 24
Peak memory 198996 kb
Host smart-bad0c473-e37c-49d9-af0a-93d95b353dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194773481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1194773481
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1619160320
Short name T281
Test name
Test status
Simulation time 12318348171 ps
CPU time 303.73 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:34:57 PM PDT 24
Peak memory 200312 kb
Host smart-586c4013-ee34-4ad1-ac56-cacf08ad1dce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619160320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1619160320
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1713723295
Short name T440
Test name
Test status
Simulation time 1496743119 ps
CPU time 3.31 seconds
Started May 19 12:30:31 PM PDT 24
Finished May 19 12:30:38 PM PDT 24
Peak memory 198008 kb
Host smart-a00a8e3b-f993-4a37-9cfa-69ca24cffa33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713723295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1713723295
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2419751613
Short name T127
Test name
Test status
Simulation time 67328215481 ps
CPU time 63.84 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:30:58 PM PDT 24
Peak memory 200300 kb
Host smart-1180142e-46f5-4ff0-8112-4b01642bff31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419751613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2419751613
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2251834857
Short name T644
Test name
Test status
Simulation time 3020233253 ps
CPU time 5.19 seconds
Started May 19 12:30:08 PM PDT 24
Finished May 19 12:30:19 PM PDT 24
Peak memory 196124 kb
Host smart-0f5e99ed-a690-4a42-ac02-8fcdcc67cd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251834857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2251834857
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.282486092
Short name T533
Test name
Test status
Simulation time 5753759533 ps
CPU time 14.59 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:11 PM PDT 24
Peak memory 200136 kb
Host smart-66bc89e1-7981-4097-ad20-96c36f9b7133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282486092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.282486092
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.442995378
Short name T69
Test name
Test status
Simulation time 85517305389 ps
CPU time 474.5 seconds
Started May 19 12:30:31 PM PDT 24
Finished May 19 12:38:29 PM PDT 24
Peak memory 224932 kb
Host smart-6ec47fa2-212b-4a6d-bf98-c096d4b2cdcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442995378 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.442995378
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1454629724
Short name T1158
Test name
Test status
Simulation time 1042386677 ps
CPU time 3.59 seconds
Started May 19 12:29:33 PM PDT 24
Finished May 19 12:29:39 PM PDT 24
Peak memory 198780 kb
Host smart-55e7290c-6bc7-4e69-bee0-a3137a112717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454629724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1454629724
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.910471572
Short name T882
Test name
Test status
Simulation time 7278906373 ps
CPU time 4.67 seconds
Started May 19 12:29:37 PM PDT 24
Finished May 19 12:29:44 PM PDT 24
Peak memory 200692 kb
Host smart-1cd0934e-1ce7-45e9-87b4-55f46e65f896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910471572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.910471572
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1382519094
Short name T943
Test name
Test status
Simulation time 42387403719 ps
CPU time 13.12 seconds
Started May 19 12:31:29 PM PDT 24
Finished May 19 12:31:43 PM PDT 24
Peak memory 200364 kb
Host smart-f75326a2-3cd9-4ae3-b3ac-e4f1c3576b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382519094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1382519094
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1298436145
Short name T821
Test name
Test status
Simulation time 66762561508 ps
CPU time 159.55 seconds
Started May 19 12:31:26 PM PDT 24
Finished May 19 12:34:06 PM PDT 24
Peak memory 200216 kb
Host smart-39dd6311-7b00-4469-865f-3c239d946a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298436145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1298436145
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1151006649
Short name T745
Test name
Test status
Simulation time 68776304912 ps
CPU time 145.53 seconds
Started May 19 12:31:32 PM PDT 24
Finished May 19 12:33:59 PM PDT 24
Peak memory 200684 kb
Host smart-8d2868ab-0fac-4ec2-9ea0-16afd061d61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151006649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1151006649
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.211885405
Short name T430
Test name
Test status
Simulation time 73248957318 ps
CPU time 30.52 seconds
Started May 19 12:31:24 PM PDT 24
Finished May 19 12:31:56 PM PDT 24
Peak memory 200264 kb
Host smart-2b600f26-3834-4f98-83a0-0280fc05f785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211885405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.211885405
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2882500455
Short name T1009
Test name
Test status
Simulation time 94483641992 ps
CPU time 42.94 seconds
Started May 19 12:31:29 PM PDT 24
Finished May 19 12:32:13 PM PDT 24
Peak memory 200432 kb
Host smart-64f13021-17bf-4cd0-8afc-ef2af6f1d77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882500455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2882500455
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2006732576
Short name T862
Test name
Test status
Simulation time 35911133789 ps
CPU time 32 seconds
Started May 19 12:31:27 PM PDT 24
Finished May 19 12:32:00 PM PDT 24
Peak memory 200324 kb
Host smart-333db3d1-190b-471b-b69d-0957197297fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006732576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2006732576
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2488530045
Short name T771
Test name
Test status
Simulation time 100238613703 ps
CPU time 80.67 seconds
Started May 19 12:31:25 PM PDT 24
Finished May 19 12:32:47 PM PDT 24
Peak memory 200276 kb
Host smart-dbc13526-d19a-40cb-82cb-b7342692f386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488530045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2488530045
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1875351663
Short name T231
Test name
Test status
Simulation time 53192679669 ps
CPU time 50.33 seconds
Started May 19 12:31:32 PM PDT 24
Finished May 19 12:32:24 PM PDT 24
Peak memory 200236 kb
Host smart-4664e016-c09b-4dc4-96a7-07252beb35e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875351663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1875351663
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3155966926
Short name T1101
Test name
Test status
Simulation time 104643656720 ps
CPU time 33.69 seconds
Started May 19 12:31:31 PM PDT 24
Finished May 19 12:32:05 PM PDT 24
Peak memory 200200 kb
Host smart-f851b989-4c41-4bb5-89ff-5d7d001c4c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155966926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3155966926
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.251287044
Short name T1155
Test name
Test status
Simulation time 80619152685 ps
CPU time 154.18 seconds
Started May 19 12:31:33 PM PDT 24
Finished May 19 12:34:08 PM PDT 24
Peak memory 200260 kb
Host smart-8231d4cb-f6aa-4e35-a4aa-e4a5474fad4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251287044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.251287044
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.703713537
Short name T25
Test name
Test status
Simulation time 15422345 ps
CPU time 0.56 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:01 PM PDT 24
Peak memory 195616 kb
Host smart-eb354e65-549d-4797-bba2-050f773d7338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703713537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.703713537
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.719800816
Short name T1054
Test name
Test status
Simulation time 63297023822 ps
CPU time 71.38 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:31:06 PM PDT 24
Peak memory 200260 kb
Host smart-444db43e-7e93-4788-bc7a-9e4ae29246a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719800816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.719800816
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.525912575
Short name T685
Test name
Test status
Simulation time 294243172950 ps
CPU time 39.7 seconds
Started May 19 12:29:40 PM PDT 24
Finished May 19 12:30:22 PM PDT 24
Peak memory 200408 kb
Host smart-bac97f50-0f04-481a-92fa-d9b543d297b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525912575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.525912575
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1610354314
Short name T12
Test name
Test status
Simulation time 53521410310 ps
CPU time 23.36 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:30:14 PM PDT 24
Peak memory 200232 kb
Host smart-d5dbd216-c4cb-481c-a1fe-e199b8826546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610354314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1610354314
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1666213557
Short name T452
Test name
Test status
Simulation time 23625533132 ps
CPU time 11.84 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:30:05 PM PDT 24
Peak memory 200080 kb
Host smart-6a1f8638-c9c8-4411-b8f3-4f7882b24e87
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666213557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1666213557
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2578217409
Short name T1001
Test name
Test status
Simulation time 99600426320 ps
CPU time 837.52 seconds
Started May 19 12:29:42 PM PDT 24
Finished May 19 12:43:42 PM PDT 24
Peak memory 200316 kb
Host smart-931358e5-3f70-45f0-afbc-daf6d433119f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2578217409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2578217409
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.765063969
Short name T484
Test name
Test status
Simulation time 105731514 ps
CPU time 0.71 seconds
Started May 19 12:30:31 PM PDT 24
Finished May 19 12:30:36 PM PDT 24
Peak memory 196084 kb
Host smart-25d65ed0-77e8-453f-af9b-7cc7ff94b5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765063969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.765063969
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.3154652104
Short name T280
Test name
Test status
Simulation time 16570993739 ps
CPU time 212.51 seconds
Started May 19 12:29:45 PM PDT 24
Finished May 19 12:33:20 PM PDT 24
Peak memory 200416 kb
Host smart-0f3a9e2c-d18a-4ee5-b7ae-466c31238011
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3154652104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3154652104
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3007925059
Short name T502
Test name
Test status
Simulation time 2872136704 ps
CPU time 20.36 seconds
Started May 19 12:30:00 PM PDT 24
Finished May 19 12:30:28 PM PDT 24
Peak memory 199260 kb
Host smart-73bff664-63b6-4eb3-badd-b1de943b8c57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3007925059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3007925059
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.410266962
Short name T496
Test name
Test status
Simulation time 27995182286 ps
CPU time 41.38 seconds
Started May 19 12:30:02 PM PDT 24
Finished May 19 12:30:51 PM PDT 24
Peak memory 200364 kb
Host smart-e884b675-901e-48ae-aa8d-fe1b998ed995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410266962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.410266962
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1939998468
Short name T451
Test name
Test status
Simulation time 34328850706 ps
CPU time 12.58 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:30:04 PM PDT 24
Peak memory 196600 kb
Host smart-78a8476c-3854-4970-9013-564e168b9b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939998468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1939998468
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.665433767
Short name T511
Test name
Test status
Simulation time 6052636283 ps
CPU time 22.38 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:18 PM PDT 24
Peak memory 200316 kb
Host smart-78750504-c9b4-4c41-9e63-52df0402b21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665433767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.665433767
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3824930141
Short name T610
Test name
Test status
Simulation time 465620486884 ps
CPU time 226.56 seconds
Started May 19 12:29:42 PM PDT 24
Finished May 19 12:33:31 PM PDT 24
Peak memory 200268 kb
Host smart-583a3eb0-392e-4484-bddb-8b7e4c4f078b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824930141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3824930141
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.4096655160
Short name T881
Test name
Test status
Simulation time 879170233 ps
CPU time 1.57 seconds
Started May 19 12:30:30 PM PDT 24
Finished May 19 12:30:35 PM PDT 24
Peak memory 198476 kb
Host smart-fb53db97-7057-4330-94e5-2eb9477e854d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096655160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.4096655160
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1422305755
Short name T556
Test name
Test status
Simulation time 35917902305 ps
CPU time 16.13 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:12 PM PDT 24
Peak memory 200084 kb
Host smart-a80ac1cb-48f5-4d5b-9076-59f71e4b0a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422305755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1422305755
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2195307329
Short name T712
Test name
Test status
Simulation time 28911049882 ps
CPU time 13.75 seconds
Started May 19 12:31:43 PM PDT 24
Finished May 19 12:31:58 PM PDT 24
Peak memory 200072 kb
Host smart-2f9dc15f-2131-4987-ac14-e1bea2832bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195307329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2195307329
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3603590188
Short name T937
Test name
Test status
Simulation time 9867531984 ps
CPU time 16.08 seconds
Started May 19 12:31:31 PM PDT 24
Finished May 19 12:31:49 PM PDT 24
Peak memory 200384 kb
Host smart-c7d1b20a-ae7d-4c1d-abc9-292d1b337dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603590188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3603590188
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3496335739
Short name T1091
Test name
Test status
Simulation time 79915028121 ps
CPU time 31.64 seconds
Started May 19 12:31:47 PM PDT 24
Finished May 19 12:32:21 PM PDT 24
Peak memory 200280 kb
Host smart-e99506e7-0153-4f07-aa29-d0f0d55b252e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496335739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3496335739
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2072272090
Short name T1050
Test name
Test status
Simulation time 29133010305 ps
CPU time 58.41 seconds
Started May 19 12:31:31 PM PDT 24
Finished May 19 12:32:30 PM PDT 24
Peak memory 200304 kb
Host smart-08fecf05-d6f3-4973-8a14-5e44ac31e005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072272090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2072272090
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.121181215
Short name T819
Test name
Test status
Simulation time 62018230405 ps
CPU time 28.72 seconds
Started May 19 12:31:32 PM PDT 24
Finished May 19 12:32:02 PM PDT 24
Peak memory 200320 kb
Host smart-5851e82a-b8e0-49cf-b992-01950451f635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121181215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.121181215
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2188437429
Short name T1033
Test name
Test status
Simulation time 56157881760 ps
CPU time 94.87 seconds
Started May 19 12:31:31 PM PDT 24
Finished May 19 12:33:08 PM PDT 24
Peak memory 200704 kb
Host smart-ef3125ee-e0f1-4aba-9d39-c332051c97e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188437429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2188437429
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.177362039
Short name T295
Test name
Test status
Simulation time 37689867085 ps
CPU time 44.64 seconds
Started May 19 12:31:30 PM PDT 24
Finished May 19 12:32:16 PM PDT 24
Peak memory 200364 kb
Host smart-9644c053-bb44-4dff-b128-8b1ae68f2a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177362039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.177362039
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2270084558
Short name T1079
Test name
Test status
Simulation time 11970930 ps
CPU time 0.56 seconds
Started May 19 12:28:52 PM PDT 24
Finished May 19 12:28:53 PM PDT 24
Peak memory 195648 kb
Host smart-1032c6cc-62fe-4f72-8f46-1c295800e901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270084558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2270084558
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.431089988
Short name T1172
Test name
Test status
Simulation time 76306835169 ps
CPU time 35.32 seconds
Started May 19 12:29:15 PM PDT 24
Finished May 19 12:29:51 PM PDT 24
Peak memory 200300 kb
Host smart-5fbf9313-e832-483f-9b33-de37431e9b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431089988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.431089988
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.977188546
Short name T253
Test name
Test status
Simulation time 25241823704 ps
CPU time 23.9 seconds
Started May 19 12:29:01 PM PDT 24
Finished May 19 12:29:25 PM PDT 24
Peak memory 200312 kb
Host smart-8b707b18-5c39-45c9-8b14-b581125002e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977188546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.977188546
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.4041573228
Short name T336
Test name
Test status
Simulation time 47874412848 ps
CPU time 57.7 seconds
Started May 19 12:28:55 PM PDT 24
Finished May 19 12:29:53 PM PDT 24
Peak memory 200220 kb
Host smart-e07c49ee-2e61-4c1c-8984-cac88059ae32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041573228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.4041573228
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3101969680
Short name T84
Test name
Test status
Simulation time 7685144188 ps
CPU time 14.84 seconds
Started May 19 12:29:23 PM PDT 24
Finished May 19 12:29:39 PM PDT 24
Peak memory 200212 kb
Host smart-ddacb031-f254-4977-a0bc-bcd3f5c2e324
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101969680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3101969680
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3816628828
Short name T534
Test name
Test status
Simulation time 94150338663 ps
CPU time 834.06 seconds
Started May 19 12:29:14 PM PDT 24
Finished May 19 12:43:09 PM PDT 24
Peak memory 200328 kb
Host smart-9cf96494-fd5e-4814-b4f2-98aab734fd78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3816628828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3816628828
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1583854279
Short name T636
Test name
Test status
Simulation time 24500371 ps
CPU time 0.71 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:30:10 PM PDT 24
Peak memory 192200 kb
Host smart-571fc15d-6727-487d-8b24-5191d5fa67ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583854279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1583854279
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3691020711
Short name T582
Test name
Test status
Simulation time 202898225327 ps
CPU time 96.11 seconds
Started May 19 12:28:56 PM PDT 24
Finished May 19 12:30:33 PM PDT 24
Peak memory 215968 kb
Host smart-0d1414a2-a6a4-4e9e-8d31-a4c10208f53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691020711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3691020711
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3244421737
Short name T587
Test name
Test status
Simulation time 11766483344 ps
CPU time 258.18 seconds
Started May 19 12:29:17 PM PDT 24
Finished May 19 12:33:36 PM PDT 24
Peak memory 200324 kb
Host smart-be129a06-7161-450e-8b48-a64f0dc2beb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244421737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3244421737
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2157753524
Short name T1034
Test name
Test status
Simulation time 7119499130 ps
CPU time 66.9 seconds
Started May 19 12:29:00 PM PDT 24
Finished May 19 12:30:08 PM PDT 24
Peak memory 199520 kb
Host smart-ddc2b2da-c4f3-4acd-a4a2-b5b9d606716a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2157753524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2157753524
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.529110783
Short name T585
Test name
Test status
Simulation time 1900533917 ps
CPU time 1.32 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:30:10 PM PDT 24
Peak memory 195192 kb
Host smart-26854ce5-be98-41ad-a3af-c2ee864e793e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529110783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.529110783
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1716531033
Short name T95
Test name
Test status
Simulation time 214526607 ps
CPU time 0.87 seconds
Started May 19 12:29:21 PM PDT 24
Finished May 19 12:29:22 PM PDT 24
Peak memory 218928 kb
Host smart-fd5b89a9-8e39-475a-90b4-073e762b7721
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716531033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1716531033
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.600554786
Short name T887
Test name
Test status
Simulation time 933450493 ps
CPU time 3.5 seconds
Started May 19 12:29:13 PM PDT 24
Finished May 19 12:29:17 PM PDT 24
Peak memory 199076 kb
Host smart-b6183913-db0f-4a10-9d9d-7dfdd7e56ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600554786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.600554786
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1447794373
Short name T1086
Test name
Test status
Simulation time 290577882998 ps
CPU time 150.79 seconds
Started May 19 12:29:23 PM PDT 24
Finished May 19 12:31:55 PM PDT 24
Peak memory 200648 kb
Host smart-84f5e00c-bfe5-4db7-9ab4-304190b992b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447794373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1447794373
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2795654851
Short name T187
Test name
Test status
Simulation time 783170027134 ps
CPU time 833.79 seconds
Started May 19 12:28:57 PM PDT 24
Finished May 19 12:42:52 PM PDT 24
Peak memory 225244 kb
Host smart-f3fd9efa-1708-4995-8de6-312c95e5bfe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795654851 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2795654851
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3066441897
Short name T1075
Test name
Test status
Simulation time 770533878 ps
CPU time 2.62 seconds
Started May 19 12:29:12 PM PDT 24
Finished May 19 12:29:15 PM PDT 24
Peak memory 199060 kb
Host smart-20d8d217-bac4-4c6c-8b6d-8c2de78ca70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066441897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3066441897
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1186775801
Short name T974
Test name
Test status
Simulation time 63871385406 ps
CPU time 117.91 seconds
Started May 19 12:29:30 PM PDT 24
Finished May 19 12:31:30 PM PDT 24
Peak memory 200688 kb
Host smart-a4ed4905-48f4-4e45-97c6-2965237623a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186775801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1186775801
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1373729906
Short name T1174
Test name
Test status
Simulation time 30613191 ps
CPU time 0.53 seconds
Started May 19 12:29:42 PM PDT 24
Finished May 19 12:29:45 PM PDT 24
Peak memory 195124 kb
Host smart-69877234-9881-46f8-a90a-cd25c76c65a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373729906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1373729906
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3087296433
Short name T5
Test name
Test status
Simulation time 75643574813 ps
CPU time 105.93 seconds
Started May 19 12:29:38 PM PDT 24
Finished May 19 12:31:26 PM PDT 24
Peak memory 200316 kb
Host smart-7fd1b17a-5061-4d91-91b3-1cec68421c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087296433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3087296433
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3227473080
Short name T136
Test name
Test status
Simulation time 17277589155 ps
CPU time 29.93 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:30:38 PM PDT 24
Peak memory 200264 kb
Host smart-dde2e951-2a9a-4933-afdf-4dc52c7da873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227473080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3227473080
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.2975297748
Short name T414
Test name
Test status
Simulation time 21272440495 ps
CPU time 10.03 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:30:02 PM PDT 24
Peak memory 199420 kb
Host smart-1aaca471-f64b-4e50-9516-b469f460d5f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975297748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2975297748
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.585568726
Short name T922
Test name
Test status
Simulation time 70656251945 ps
CPU time 304.59 seconds
Started May 19 12:29:42 PM PDT 24
Finished May 19 12:34:49 PM PDT 24
Peak memory 200416 kb
Host smart-444145ae-a3e7-4353-9ff5-b8ad4778f73e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585568726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.585568726
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3875519399
Short name T609
Test name
Test status
Simulation time 3899095420 ps
CPU time 2.39 seconds
Started May 19 12:29:56 PM PDT 24
Finished May 19 12:30:05 PM PDT 24
Peak memory 199220 kb
Host smart-ed55697e-2bd7-410b-8884-a07881af9d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875519399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3875519399
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3827371813
Short name T786
Test name
Test status
Simulation time 105245739711 ps
CPU time 56.86 seconds
Started May 19 12:29:42 PM PDT 24
Finished May 19 12:30:41 PM PDT 24
Peak memory 200624 kb
Host smart-ec6b30ab-7bb8-4916-8266-6e9ac5605056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827371813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3827371813
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.94416121
Short name T514
Test name
Test status
Simulation time 26827842147 ps
CPU time 1495.92 seconds
Started May 19 12:29:45 PM PDT 24
Finished May 19 12:54:45 PM PDT 24
Peak memory 200352 kb
Host smart-11adcb41-d2eb-4143-8db3-622059c24129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94416121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.94416121
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2517987526
Short name T41
Test name
Test status
Simulation time 2767004446 ps
CPU time 5.12 seconds
Started May 19 12:30:00 PM PDT 24
Finished May 19 12:30:13 PM PDT 24
Peak memory 198960 kb
Host smart-29989ff1-c052-4c26-9d4c-9e017fed25cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517987526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2517987526
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1488224304
Short name T373
Test name
Test status
Simulation time 13594878278 ps
CPU time 22.67 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:30:15 PM PDT 24
Peak memory 200232 kb
Host smart-f660b661-73f2-4d53-b288-913aa80e5a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488224304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1488224304
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1909350091
Short name T608
Test name
Test status
Simulation time 403006385 ps
CPU time 1.28 seconds
Started May 19 12:29:43 PM PDT 24
Finished May 19 12:29:47 PM PDT 24
Peak memory 195668 kb
Host smart-178fc1ef-3789-4a59-8c45-18dc243709ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909350091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1909350091
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3630372205
Short name T834
Test name
Test status
Simulation time 5873153132 ps
CPU time 14.3 seconds
Started May 19 12:29:33 PM PDT 24
Finished May 19 12:29:50 PM PDT 24
Peak memory 200036 kb
Host smart-70acbfdd-c172-49d2-9f45-372d348fa90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630372205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3630372205
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.153911504
Short name T763
Test name
Test status
Simulation time 391331797628 ps
CPU time 367.3 seconds
Started May 19 12:29:50 PM PDT 24
Finished May 19 12:36:06 PM PDT 24
Peak memory 216996 kb
Host smart-1d220a27-771d-4eda-940f-d2f9d97d78b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153911504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.153911504
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2955553589
Short name T1082
Test name
Test status
Simulation time 50988631151 ps
CPU time 494.79 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:38:11 PM PDT 24
Peak memory 225344 kb
Host smart-80b0f617-7433-414c-abcf-59f09fc6a17e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955553589 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2955553589
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3516492903
Short name T477
Test name
Test status
Simulation time 1948136033 ps
CPU time 2.89 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:29:57 PM PDT 24
Peak memory 199864 kb
Host smart-ca9245e1-6bbf-493d-942e-4b7aefbb71ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516492903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3516492903
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3812581782
Short name T749
Test name
Test status
Simulation time 104242736757 ps
CPU time 76.24 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:31:09 PM PDT 24
Peak memory 200260 kb
Host smart-e91fba0b-8dfd-4b4d-b955-1e08c8df853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812581782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3812581782
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3298427025
Short name T227
Test name
Test status
Simulation time 96168735149 ps
CPU time 105.38 seconds
Started May 19 12:31:31 PM PDT 24
Finished May 19 12:33:18 PM PDT 24
Peak memory 200300 kb
Host smart-b25196ea-a712-464b-8f84-e8f9d321b1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298427025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3298427025
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3425743599
Short name T1170
Test name
Test status
Simulation time 54620885910 ps
CPU time 46.17 seconds
Started May 19 12:31:41 PM PDT 24
Finished May 19 12:32:28 PM PDT 24
Peak memory 200220 kb
Host smart-8f0225f0-900f-42b0-b792-da0aaab28e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425743599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3425743599
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1670489577
Short name T992
Test name
Test status
Simulation time 16234612690 ps
CPU time 28.77 seconds
Started May 19 12:31:33 PM PDT 24
Finished May 19 12:32:03 PM PDT 24
Peak memory 200312 kb
Host smart-ceef0493-6a35-4561-b3b5-687304c74fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670489577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1670489577
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2276169559
Short name T597
Test name
Test status
Simulation time 99075957926 ps
CPU time 84.2 seconds
Started May 19 12:31:30 PM PDT 24
Finished May 19 12:32:56 PM PDT 24
Peak memory 200332 kb
Host smart-41a3cbb3-fd89-4c31-a5df-53ddf8ec5633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276169559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2276169559
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1545868078
Short name T844
Test name
Test status
Simulation time 153950091245 ps
CPU time 66.34 seconds
Started May 19 12:31:33 PM PDT 24
Finished May 19 12:32:40 PM PDT 24
Peak memory 200216 kb
Host smart-f757c27e-ba17-4fc5-9b30-106dbfb39927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545868078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1545868078
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2556875855
Short name T1012
Test name
Test status
Simulation time 11613574331 ps
CPU time 17.09 seconds
Started May 19 12:31:45 PM PDT 24
Finished May 19 12:32:03 PM PDT 24
Peak memory 200332 kb
Host smart-b4d077cf-9805-4ec7-8d31-a1e69f2d762f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556875855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2556875855
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3076392506
Short name T1065
Test name
Test status
Simulation time 20217344479 ps
CPU time 15.45 seconds
Started May 19 12:31:34 PM PDT 24
Finished May 19 12:31:51 PM PDT 24
Peak memory 200256 kb
Host smart-ba1e1287-cc28-42e7-8e20-2d1df9b7360f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076392506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3076392506
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2514834207
Short name T1062
Test name
Test status
Simulation time 101174144497 ps
CPU time 58.47 seconds
Started May 19 12:31:33 PM PDT 24
Finished May 19 12:32:33 PM PDT 24
Peak memory 200276 kb
Host smart-d6e407cb-b026-4f66-bffd-7fe97f5d74ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514834207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2514834207
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2610336265
Short name T804
Test name
Test status
Simulation time 37142122280 ps
CPU time 34.18 seconds
Started May 19 12:31:32 PM PDT 24
Finished May 19 12:32:07 PM PDT 24
Peak memory 200284 kb
Host smart-6741ddd7-ce2d-4030-8f3c-afb654affa0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610336265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2610336265
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1357311270
Short name T650
Test name
Test status
Simulation time 39099331 ps
CPU time 0.54 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:29:58 PM PDT 24
Peak memory 195684 kb
Host smart-8fce5ecb-d6cb-4e08-9423-ff5e0d93ef7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357311270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1357311270
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2337517853
Short name T812
Test name
Test status
Simulation time 79592870051 ps
CPU time 74.27 seconds
Started May 19 12:29:44 PM PDT 24
Finished May 19 12:31:01 PM PDT 24
Peak memory 200272 kb
Host smart-7d0e131c-a408-4011-b2de-13fcef355d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337517853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2337517853
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3164249470
Short name T734
Test name
Test status
Simulation time 107888189658 ps
CPU time 155.32 seconds
Started May 19 12:29:41 PM PDT 24
Finished May 19 12:32:19 PM PDT 24
Peak memory 200304 kb
Host smart-9419dc86-3331-4a6d-aa5c-36e349ecc454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164249470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3164249470
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2767155648
Short name T402
Test name
Test status
Simulation time 30407068381 ps
CPU time 14.22 seconds
Started May 19 12:30:03 PM PDT 24
Finished May 19 12:30:24 PM PDT 24
Peak memory 200316 kb
Host smart-ac25c585-8b42-47fa-b0e8-8da513960e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767155648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2767155648
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3355168319
Short name T758
Test name
Test status
Simulation time 17611794247 ps
CPU time 4.31 seconds
Started May 19 12:29:50 PM PDT 24
Finished May 19 12:30:03 PM PDT 24
Peak memory 199740 kb
Host smart-01008125-e2d8-48e5-ba4e-40f997389130
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355168319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3355168319
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1430612469
Short name T47
Test name
Test status
Simulation time 113646542806 ps
CPU time 170.65 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:32:48 PM PDT 24
Peak memory 200280 kb
Host smart-adb2f7ee-255e-4847-b4b4-3535485a10ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1430612469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1430612469
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.4212848035
Short name T894
Test name
Test status
Simulation time 7031478251 ps
CPU time 13.82 seconds
Started May 19 12:29:39 PM PDT 24
Finished May 19 12:29:55 PM PDT 24
Peak memory 200348 kb
Host smart-c7c98ffa-67b4-4227-bbc8-d74d7ed7efe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212848035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.4212848035
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.615195823
Short name T735
Test name
Test status
Simulation time 232231885650 ps
CPU time 55.72 seconds
Started May 19 12:29:43 PM PDT 24
Finished May 19 12:30:41 PM PDT 24
Peak memory 200400 kb
Host smart-5648e9c9-f63a-4e17-a995-087abae2bc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615195823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.615195823
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2582037912
Short name T381
Test name
Test status
Simulation time 23419462307 ps
CPU time 747.25 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:42:24 PM PDT 24
Peak memory 200252 kb
Host smart-5ad4d401-9362-4682-b3a5-c8bf3741703c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2582037912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2582037912
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1505029655
Short name T897
Test name
Test status
Simulation time 6907543138 ps
CPU time 10.92 seconds
Started May 19 12:29:44 PM PDT 24
Finished May 19 12:29:58 PM PDT 24
Peak memory 198528 kb
Host smart-e3dfeaf5-bd60-4a8c-967a-57dbf143bad7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505029655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1505029655
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2094137170
Short name T848
Test name
Test status
Simulation time 34182584080 ps
CPU time 67.66 seconds
Started May 19 12:29:51 PM PDT 24
Finished May 19 12:31:11 PM PDT 24
Peak memory 200304 kb
Host smart-79d6a336-0f93-4d52-a45b-ec4108e54565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094137170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2094137170
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3972461015
Short name T866
Test name
Test status
Simulation time 45311442243 ps
CPU time 74.33 seconds
Started May 19 12:29:53 PM PDT 24
Finished May 19 12:31:15 PM PDT 24
Peak memory 196028 kb
Host smart-172ecf0d-fcf2-4556-9233-dd37dbf08803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972461015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3972461015
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1860868601
Short name T43
Test name
Test status
Simulation time 318784486 ps
CPU time 1.08 seconds
Started May 19 12:29:54 PM PDT 24
Finished May 19 12:30:05 PM PDT 24
Peak memory 199832 kb
Host smart-57e4613d-5233-4c39-bab6-5d76db66608b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860868601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1860868601
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.11440055
Short name T1142
Test name
Test status
Simulation time 242343135947 ps
CPU time 218.13 seconds
Started May 19 12:29:50 PM PDT 24
Finished May 19 12:33:36 PM PDT 24
Peak memory 200588 kb
Host smart-f104003f-2756-49ae-843b-5e64663c9bad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11440055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.11440055
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2213191862
Short name T1045
Test name
Test status
Simulation time 58795673492 ps
CPU time 673.38 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:41:09 PM PDT 24
Peak memory 216836 kb
Host smart-a493002e-ceb4-4738-8a29-5dac0d4441b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213191862 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2213191862
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.4009247050
Short name T500
Test name
Test status
Simulation time 650394732 ps
CPU time 2.45 seconds
Started May 19 12:29:34 PM PDT 24
Finished May 19 12:29:39 PM PDT 24
Peak memory 199020 kb
Host smart-b2420746-c847-4620-ad09-5e244a92a516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009247050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.4009247050
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3951181445
Short name T516
Test name
Test status
Simulation time 58047001305 ps
CPU time 24.58 seconds
Started May 19 12:30:00 PM PDT 24
Finished May 19 12:30:32 PM PDT 24
Peak memory 200256 kb
Host smart-147b9c51-bde3-4f8f-b3af-6effac3aa731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951181445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3951181445
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1909019029
Short name T877
Test name
Test status
Simulation time 16673394484 ps
CPU time 27.27 seconds
Started May 19 12:31:33 PM PDT 24
Finished May 19 12:32:02 PM PDT 24
Peak memory 200036 kb
Host smart-1c10df72-b23b-422f-ada5-0c9e98bba478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909019029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1909019029
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3233657754
Short name T793
Test name
Test status
Simulation time 89435572734 ps
CPU time 132.4 seconds
Started May 19 12:31:41 PM PDT 24
Finished May 19 12:33:54 PM PDT 24
Peak memory 200340 kb
Host smart-f0055e5c-8ca8-4c45-b156-9a7a02f4c501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233657754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3233657754
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2544134831
Short name T411
Test name
Test status
Simulation time 169216534094 ps
CPU time 21.53 seconds
Started May 19 12:31:33 PM PDT 24
Finished May 19 12:31:55 PM PDT 24
Peak memory 200288 kb
Host smart-64d1fcea-ed1b-43ec-b35a-a2f6ca36f0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544134831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2544134831
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2175822891
Short name T269
Test name
Test status
Simulation time 15269800825 ps
CPU time 30.2 seconds
Started May 19 12:31:32 PM PDT 24
Finished May 19 12:32:03 PM PDT 24
Peak memory 200204 kb
Host smart-82a56166-b1c7-4bde-aedb-a398e39eadf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175822891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2175822891
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2790894765
Short name T219
Test name
Test status
Simulation time 72496334047 ps
CPU time 29.31 seconds
Started May 19 12:31:33 PM PDT 24
Finished May 19 12:32:03 PM PDT 24
Peak memory 200316 kb
Host smart-ee01130c-7d79-477c-a3b0-e047ae1a1963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790894765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2790894765
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3502726652
Short name T211
Test name
Test status
Simulation time 23269390015 ps
CPU time 17.45 seconds
Started May 19 12:31:32 PM PDT 24
Finished May 19 12:31:51 PM PDT 24
Peak memory 199996 kb
Host smart-943d86cf-6ce3-44bf-853c-f9b62f5305b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502726652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3502726652
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1913581308
Short name T288
Test name
Test status
Simulation time 63060969115 ps
CPU time 28.56 seconds
Started May 19 12:31:32 PM PDT 24
Finished May 19 12:32:02 PM PDT 24
Peak memory 200244 kb
Host smart-f95a9976-9325-4e53-a534-9dd73d17f5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913581308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1913581308
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.203307466
Short name T618
Test name
Test status
Simulation time 25301233906 ps
CPU time 37.43 seconds
Started May 19 12:31:44 PM PDT 24
Finished May 19 12:32:22 PM PDT 24
Peak memory 200276 kb
Host smart-fd0d4d30-c512-4748-aa5c-95549e4fd487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203307466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.203307466
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1365245064
Short name T1015
Test name
Test status
Simulation time 12391780980 ps
CPU time 22.3 seconds
Started May 19 12:31:42 PM PDT 24
Finished May 19 12:32:05 PM PDT 24
Peak memory 200228 kb
Host smart-8cc13865-9094-429c-b73e-9fb52478c94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365245064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1365245064
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2018043369
Short name T361
Test name
Test status
Simulation time 51178166 ps
CPU time 0.55 seconds
Started May 19 12:29:50 PM PDT 24
Finished May 19 12:29:59 PM PDT 24
Peak memory 195636 kb
Host smart-809db8de-be01-4d53-8fdb-6cbfbc85e8aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018043369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2018043369
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1902818462
Short name T505
Test name
Test status
Simulation time 17402327002 ps
CPU time 8.82 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:05 PM PDT 24
Peak memory 200348 kb
Host smart-277a222a-590a-49f0-bcac-cfdb92858ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902818462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1902818462
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.280584801
Short name T973
Test name
Test status
Simulation time 90247085658 ps
CPU time 174.09 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:32:48 PM PDT 24
Peak memory 200312 kb
Host smart-4804852a-3191-4bb9-8859-af12fad10fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280584801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.280584801
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_intr.4190433617
Short name T97
Test name
Test status
Simulation time 23744259048 ps
CPU time 8.38 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:30:05 PM PDT 24
Peak memory 200268 kb
Host smart-f1d6444e-815d-4d0d-858d-ca80a69b6854
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190433617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.4190433617
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3229439516
Short name T264
Test name
Test status
Simulation time 52541705619 ps
CPU time 422.69 seconds
Started May 19 12:29:44 PM PDT 24
Finished May 19 12:36:49 PM PDT 24
Peak memory 200304 kb
Host smart-61b5dfc9-be78-48d3-ab1a-fbb333e04e9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229439516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3229439516
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.4049131594
Short name T863
Test name
Test status
Simulation time 4899949082 ps
CPU time 5.64 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:30:03 PM PDT 24
Peak memory 198840 kb
Host smart-f30b35c0-42ca-463c-a575-dbc2e1f1a1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049131594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.4049131594
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3889893978
Short name T279
Test name
Test status
Simulation time 146824048287 ps
CPU time 68.06 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:31:02 PM PDT 24
Peak memory 199888 kb
Host smart-c8773fed-6ff8-445e-9830-c92731620edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889893978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3889893978
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1675432148
Short name T846
Test name
Test status
Simulation time 12816604193 ps
CPU time 321.87 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:35:15 PM PDT 24
Peak memory 200336 kb
Host smart-204aef92-58cf-4032-adfa-e7ee92d1d098
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1675432148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1675432148
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.446232594
Short name T488
Test name
Test status
Simulation time 3394595148 ps
CPU time 6.16 seconds
Started May 19 12:29:52 PM PDT 24
Finished May 19 12:30:06 PM PDT 24
Peak memory 199576 kb
Host smart-2087f492-d6fd-49e0-89eb-b6cc43322e2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=446232594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.446232594
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1301288563
Short name T1108
Test name
Test status
Simulation time 34861289020 ps
CPU time 15.05 seconds
Started May 19 12:29:51 PM PDT 24
Finished May 19 12:30:14 PM PDT 24
Peak memory 200272 kb
Host smart-3f9f312e-b6f8-4c44-b01c-99d1870b8f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301288563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1301288563
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.894136856
Short name T494
Test name
Test status
Simulation time 43246224823 ps
CPU time 36.79 seconds
Started May 19 12:29:42 PM PDT 24
Finished May 19 12:30:21 PM PDT 24
Peak memory 196312 kb
Host smart-19addf83-5fe6-4e82-b2d7-c76e91c094de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894136856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.894136856
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1230929308
Short name T1022
Test name
Test status
Simulation time 5354450233 ps
CPU time 11.38 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:30:04 PM PDT 24
Peak memory 200328 kb
Host smart-fe6bda6c-57ef-4daa-beb2-28ca68a24824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230929308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1230929308
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3038966646
Short name T499
Test name
Test status
Simulation time 161589509465 ps
CPU time 58.52 seconds
Started May 19 12:29:51 PM PDT 24
Finished May 19 12:30:58 PM PDT 24
Peak memory 200288 kb
Host smart-f742b880-61d7-4315-81d0-39a2af4fd280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038966646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3038966646
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1468634233
Short name T70
Test name
Test status
Simulation time 74772214567 ps
CPU time 726.12 seconds
Started May 19 12:29:59 PM PDT 24
Finished May 19 12:42:13 PM PDT 24
Peak memory 225264 kb
Host smart-7385187b-fb1b-4b72-a65d-627cc784d2dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468634233 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1468634233
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.4233050795
Short name T544
Test name
Test status
Simulation time 6829578366 ps
CPU time 18.95 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:15 PM PDT 24
Peak memory 200180 kb
Host smart-a4a8baa3-6b9d-471f-9933-c12c9247de72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233050795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.4233050795
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1819667070
Short name T362
Test name
Test status
Simulation time 2215772691 ps
CPU time 3.62 seconds
Started May 19 12:29:53 PM PDT 24
Finished May 19 12:30:04 PM PDT 24
Peak memory 200108 kb
Host smart-257cdd77-5280-4908-9fcc-a0ad1c09605b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819667070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1819667070
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3224719020
Short name T535
Test name
Test status
Simulation time 81045555268 ps
CPU time 75.4 seconds
Started May 19 12:31:36 PM PDT 24
Finished May 19 12:32:52 PM PDT 24
Peak memory 200324 kb
Host smart-727254a7-cc4b-482c-bb5d-b6def35e69f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224719020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3224719020
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2500234080
Short name T547
Test name
Test status
Simulation time 109138458391 ps
CPU time 171.32 seconds
Started May 19 12:31:45 PM PDT 24
Finished May 19 12:34:38 PM PDT 24
Peak memory 200312 kb
Host smart-4f4e649e-603b-443d-9ea4-5da980f2b240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500234080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2500234080
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.4055578944
Short name T172
Test name
Test status
Simulation time 17661287512 ps
CPU time 34.45 seconds
Started May 19 12:31:35 PM PDT 24
Finished May 19 12:32:10 PM PDT 24
Peak memory 200132 kb
Host smart-0d477473-e66a-4869-80ee-aa7ca2d78eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055578944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.4055578944
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1520145874
Short name T487
Test name
Test status
Simulation time 126973586611 ps
CPU time 273.03 seconds
Started May 19 12:31:36 PM PDT 24
Finished May 19 12:36:10 PM PDT 24
Peak memory 200324 kb
Host smart-7a6676f8-88e3-4d94-b269-216dfde1533d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520145874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1520145874
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.518205554
Short name T713
Test name
Test status
Simulation time 92348226908 ps
CPU time 123.07 seconds
Started May 19 12:31:36 PM PDT 24
Finished May 19 12:33:40 PM PDT 24
Peak memory 200280 kb
Host smart-daed3789-9831-49af-9d70-aa4b27f642a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518205554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.518205554
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2214511085
Short name T335
Test name
Test status
Simulation time 93198790605 ps
CPU time 44.75 seconds
Started May 19 12:31:37 PM PDT 24
Finished May 19 12:32:23 PM PDT 24
Peak memory 200328 kb
Host smart-a3810d6c-06c9-4ab2-96a1-aef4e4f1adbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214511085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2214511085
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.590553572
Short name T1145
Test name
Test status
Simulation time 5193549815 ps
CPU time 9.44 seconds
Started May 19 12:31:37 PM PDT 24
Finished May 19 12:31:47 PM PDT 24
Peak memory 200164 kb
Host smart-33093fd6-9e1c-4ec2-aac5-b108188c5787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590553572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.590553572
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1860835275
Short name T171
Test name
Test status
Simulation time 34521923205 ps
CPU time 54.1 seconds
Started May 19 12:31:47 PM PDT 24
Finished May 19 12:32:42 PM PDT 24
Peak memory 200264 kb
Host smart-d0b35329-2339-4ecb-af47-c16df7a9804e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860835275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1860835275
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3508974255
Short name T551
Test name
Test status
Simulation time 16672186 ps
CPU time 0.52 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:29:55 PM PDT 24
Peak memory 195712 kb
Host smart-72c49fa5-2274-4758-86e2-73f1f4c25b42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508974255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3508974255
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1871863125
Short name T512
Test name
Test status
Simulation time 81305236506 ps
CPU time 32.49 seconds
Started May 19 12:29:44 PM PDT 24
Finished May 19 12:30:19 PM PDT 24
Peak memory 200256 kb
Host smart-c12868d0-9669-4e76-bf9e-748f6eca0c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871863125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1871863125
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1573761551
Short name T138
Test name
Test status
Simulation time 38565282782 ps
CPU time 66.88 seconds
Started May 19 12:29:53 PM PDT 24
Finished May 19 12:31:07 PM PDT 24
Peak memory 200004 kb
Host smart-8abe0380-c24b-49bf-a2c8-7b0459a045f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573761551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1573761551
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3793285896
Short name T768
Test name
Test status
Simulation time 11118339068 ps
CPU time 9.37 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:05 PM PDT 24
Peak memory 199652 kb
Host smart-23d5d861-6522-401b-9aec-fe3c11bc822a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793285896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3793285896
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1937887811
Short name T1087
Test name
Test status
Simulation time 60245774504 ps
CPU time 137.59 seconds
Started May 19 12:30:00 PM PDT 24
Finished May 19 12:32:26 PM PDT 24
Peak memory 200324 kb
Host smart-01fc27b0-a054-4de5-a16b-f186e1755a64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937887811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1937887811
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2066730401
Short name T375
Test name
Test status
Simulation time 7678455318 ps
CPU time 4.75 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:30:14 PM PDT 24
Peak memory 199692 kb
Host smart-702ef05b-1b37-41d0-887d-2afbe9695a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066730401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2066730401
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3532561537
Short name T569
Test name
Test status
Simulation time 24687613349 ps
CPU time 45.44 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:42 PM PDT 24
Peak memory 200556 kb
Host smart-b400e33d-c184-47c9-a3e1-3d0cca23506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532561537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3532561537
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1483898148
Short name T1125
Test name
Test status
Simulation time 9275114789 ps
CPU time 246.49 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:34:16 PM PDT 24
Peak memory 200264 kb
Host smart-fa1eb59b-3afb-4d93-9ab2-571e6d4c9cc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483898148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1483898148
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.664136979
Short name T545
Test name
Test status
Simulation time 4225449162 ps
CPU time 6.1 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:03 PM PDT 24
Peak memory 198456 kb
Host smart-043801d0-f052-4112-89a5-7e2160c6bf20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=664136979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.664136979
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3813101559
Short name T660
Test name
Test status
Simulation time 41086412674 ps
CPU time 26.56 seconds
Started May 19 12:29:44 PM PDT 24
Finished May 19 12:30:12 PM PDT 24
Peak memory 200128 kb
Host smart-224dd479-4525-4249-873a-801881de2bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813101559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3813101559
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3652996406
Short name T443
Test name
Test status
Simulation time 23193946165 ps
CPU time 35.19 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:30:29 PM PDT 24
Peak memory 196376 kb
Host smart-87ea35ef-b2ea-47ba-ba71-1701473d300d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652996406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3652996406
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.4127720233
Short name T349
Test name
Test status
Simulation time 87498212 ps
CPU time 0.88 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:29:53 PM PDT 24
Peak memory 197412 kb
Host smart-482c12de-85bf-4a1e-9112-a6f6ab23d3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127720233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4127720233
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.4167639092
Short name T338
Test name
Test status
Simulation time 153840034993 ps
CPU time 270.78 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:34:23 PM PDT 24
Peak memory 208720 kb
Host smart-e9e73961-07c9-42a3-9470-43c4d1a0e2ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167639092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4167639092
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1985416434
Short name T1176
Test name
Test status
Simulation time 43195919361 ps
CPU time 245.89 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:34:00 PM PDT 24
Peak memory 216908 kb
Host smart-3a7c6db6-6781-438a-8215-717d5a5b9852
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985416434 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1985416434
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2193664761
Short name T795
Test name
Test status
Simulation time 3244581220 ps
CPU time 2.14 seconds
Started May 19 12:30:12 PM PDT 24
Finished May 19 12:30:18 PM PDT 24
Peak memory 199168 kb
Host smart-9939e246-11bb-4ca3-8598-bc98b65106b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193664761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2193664761
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2311020722
Short name T302
Test name
Test status
Simulation time 51170696442 ps
CPU time 85.46 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:31:20 PM PDT 24
Peak memory 200184 kb
Host smart-10f62744-33dc-4772-887d-8c77b5a407b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311020722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2311020722
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2056356181
Short name T918
Test name
Test status
Simulation time 92080723554 ps
CPU time 141.53 seconds
Started May 19 12:31:40 PM PDT 24
Finished May 19 12:34:02 PM PDT 24
Peak memory 200060 kb
Host smart-4ae9278b-0727-4ba1-9476-30b03e665498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056356181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2056356181
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.4282280853
Short name T1
Test name
Test status
Simulation time 113398638462 ps
CPU time 46.69 seconds
Started May 19 12:31:39 PM PDT 24
Finished May 19 12:32:27 PM PDT 24
Peak memory 200120 kb
Host smart-eaf0a790-6d5e-4b43-8886-e7c1c9d475a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282280853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.4282280853
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1578351448
Short name T568
Test name
Test status
Simulation time 114570462077 ps
CPU time 144.69 seconds
Started May 19 12:31:46 PM PDT 24
Finished May 19 12:34:11 PM PDT 24
Peak memory 200260 kb
Host smart-44343936-8187-4f13-a827-e67f35f76156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578351448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1578351448
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1857386509
Short name T1113
Test name
Test status
Simulation time 23030339855 ps
CPU time 40.45 seconds
Started May 19 12:31:35 PM PDT 24
Finished May 19 12:32:17 PM PDT 24
Peak memory 200272 kb
Host smart-6cf547d2-f50f-4cca-ae90-473d2d774ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857386509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1857386509
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3744417559
Short name T825
Test name
Test status
Simulation time 78263261219 ps
CPU time 31.3 seconds
Started May 19 12:31:48 PM PDT 24
Finished May 19 12:32:22 PM PDT 24
Peak memory 200248 kb
Host smart-16f7ee45-1f8c-4a87-8165-13c9273fbebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744417559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3744417559
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2251805023
Short name T840
Test name
Test status
Simulation time 44519164773 ps
CPU time 109.47 seconds
Started May 19 12:31:48 PM PDT 24
Finished May 19 12:33:40 PM PDT 24
Peak memory 200240 kb
Host smart-e030c4ed-d2dd-4ed0-a6ae-6f749328e41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251805023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2251805023
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3825778960
Short name T611
Test name
Test status
Simulation time 165495785757 ps
CPU time 15.77 seconds
Started May 19 12:31:36 PM PDT 24
Finished May 19 12:31:53 PM PDT 24
Peak memory 200228 kb
Host smart-6f37f817-a8a8-4e23-bbc7-369edd23d557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825778960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3825778960
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1199326670
Short name T184
Test name
Test status
Simulation time 102327290666 ps
CPU time 21.55 seconds
Started May 19 12:31:35 PM PDT 24
Finished May 19 12:31:58 PM PDT 24
Peak memory 200256 kb
Host smart-57986859-3843-465c-a48e-bd66b666aa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199326670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1199326670
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2896773068
Short name T208
Test name
Test status
Simulation time 116666465062 ps
CPU time 11.91 seconds
Started May 19 12:31:47 PM PDT 24
Finished May 19 12:32:02 PM PDT 24
Peak memory 200308 kb
Host smart-a2fd3e1f-3d39-443f-b7b7-6b7f09840814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896773068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2896773068
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1144589821
Short name T509
Test name
Test status
Simulation time 36576545 ps
CPU time 0.53 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:29:58 PM PDT 24
Peak memory 195716 kb
Host smart-ff70b5ff-4a46-4e40-8cb9-e6dc3aa70bf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144589821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1144589821
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3482737967
Short name T820
Test name
Test status
Simulation time 27740342456 ps
CPU time 12.97 seconds
Started May 19 12:30:02 PM PDT 24
Finished May 19 12:30:23 PM PDT 24
Peak memory 200280 kb
Host smart-014c7e69-3a54-4b30-99a3-c894c9ef4027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482737967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3482737967
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2624380877
Short name T928
Test name
Test status
Simulation time 34009436445 ps
CPU time 27.51 seconds
Started May 19 12:29:55 PM PDT 24
Finished May 19 12:30:30 PM PDT 24
Peak memory 200276 kb
Host smart-c002f8a5-2ca9-4872-86b5-28015f4a1c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624380877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2624380877
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3889727587
Short name T898
Test name
Test status
Simulation time 88423540137 ps
CPU time 69.2 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:31:06 PM PDT 24
Peak memory 200328 kb
Host smart-271f7d12-fd81-442e-a4f0-703098523077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889727587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3889727587
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3434893755
Short name T560
Test name
Test status
Simulation time 4430547798 ps
CPU time 1.35 seconds
Started May 19 12:30:00 PM PDT 24
Finished May 19 12:30:09 PM PDT 24
Peak memory 196204 kb
Host smart-75dcd28a-bcc2-47d0-bfec-4bfc12037133
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434893755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3434893755
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2573596751
Short name T590
Test name
Test status
Simulation time 109300352585 ps
CPU time 934.94 seconds
Started May 19 12:30:00 PM PDT 24
Finished May 19 12:45:42 PM PDT 24
Peak memory 200248 kb
Host smart-76593221-2e5a-4f76-a9b7-0953ae2669ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573596751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2573596751
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3126035151
Short name T522
Test name
Test status
Simulation time 12177687570 ps
CPU time 9.54 seconds
Started May 19 12:29:53 PM PDT 24
Finished May 19 12:30:10 PM PDT 24
Peak memory 200256 kb
Host smart-057f61a5-757f-4650-8747-18555f6d918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126035151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3126035151
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2418953507
Short name T903
Test name
Test status
Simulation time 40699457590 ps
CPU time 64.7 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:30:58 PM PDT 24
Peak memory 200592 kb
Host smart-36b3dabe-0f57-4b40-ae9b-821a1c19df36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418953507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2418953507
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.4253610855
Short name T705
Test name
Test status
Simulation time 15305182388 ps
CPU time 316.89 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:35:11 PM PDT 24
Peak memory 200256 kb
Host smart-27a920a0-4b7d-4c76-b581-b81cb56ef826
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4253610855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.4253610855
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1714187961
Short name T1118
Test name
Test status
Simulation time 2321663962 ps
CPU time 12.11 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:30:05 PM PDT 24
Peak memory 198704 kb
Host smart-12e9aadb-1d01-4664-b5e6-3d262432fd26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1714187961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1714187961
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1001102553
Short name T1175
Test name
Test status
Simulation time 45878613794 ps
CPU time 79.79 seconds
Started May 19 12:29:51 PM PDT 24
Finished May 19 12:31:19 PM PDT 24
Peak memory 200244 kb
Host smart-db0020a1-f74a-4d73-8a91-679b9c85e005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001102553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1001102553
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2502592043
Short name T687
Test name
Test status
Simulation time 87182258221 ps
CPU time 32.69 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:30:30 PM PDT 24
Peak memory 196012 kb
Host smart-4207f8f6-5f08-4ae6-b5ef-0c159c81c05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502592043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2502592043
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1408762980
Short name T588
Test name
Test status
Simulation time 275974056 ps
CPU time 1 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:29:57 PM PDT 24
Peak memory 198712 kb
Host smart-d3083305-16b2-4cb4-a808-138712e55983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408762980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1408762980
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2636434001
Short name T13
Test name
Test status
Simulation time 123217704398 ps
CPU time 225.78 seconds
Started May 19 12:29:56 PM PDT 24
Finished May 19 12:33:49 PM PDT 24
Peak memory 208688 kb
Host smart-8ed1c21e-c739-4434-9d18-12bd10bbc35b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636434001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2636434001
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3816907250
Short name T62
Test name
Test status
Simulation time 134000100262 ps
CPU time 505 seconds
Started May 19 12:30:44 PM PDT 24
Finished May 19 12:39:12 PM PDT 24
Peak memory 216464 kb
Host smart-eac561ab-8dd3-48a2-a7c5-4a2463e6ab21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816907250 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3816907250
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2953816530
Short name T806
Test name
Test status
Simulation time 9290694250 ps
CPU time 7.13 seconds
Started May 19 12:29:57 PM PDT 24
Finished May 19 12:30:11 PM PDT 24
Peak memory 199720 kb
Host smart-e963f76f-a9b6-49bc-8907-69455b36fc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953816530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2953816530
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1085020173
Short name T1147
Test name
Test status
Simulation time 4920071908 ps
CPU time 8.86 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:30:17 PM PDT 24
Peak memory 198716 kb
Host smart-fe9f9b24-3565-4ad5-bda5-71c46071d58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085020173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1085020173
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1429590742
Short name T329
Test name
Test status
Simulation time 148295467187 ps
CPU time 243.71 seconds
Started May 19 12:31:48 PM PDT 24
Finished May 19 12:35:54 PM PDT 24
Peak memory 200356 kb
Host smart-7a12bfec-59c3-4f53-a8fe-ed51f8c3eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429590742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1429590742
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2046232193
Short name T1129
Test name
Test status
Simulation time 81310247613 ps
CPU time 39.86 seconds
Started May 19 12:31:36 PM PDT 24
Finished May 19 12:32:16 PM PDT 24
Peak memory 200188 kb
Host smart-695ded74-e916-4ca7-8b9d-acaf43a284d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046232193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2046232193
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1507830627
Short name T234
Test name
Test status
Simulation time 98372261977 ps
CPU time 166.96 seconds
Started May 19 12:31:50 PM PDT 24
Finished May 19 12:34:39 PM PDT 24
Peak memory 200144 kb
Host smart-3dab8d15-3c38-4433-9cac-73f1e79033f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507830627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1507830627
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3542723210
Short name T963
Test name
Test status
Simulation time 66898829637 ps
CPU time 27.83 seconds
Started May 19 12:31:41 PM PDT 24
Finished May 19 12:32:10 PM PDT 24
Peak memory 199940 kb
Host smart-0d5de08a-47c1-4be2-b662-4416a87b9c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542723210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3542723210
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1678069342
Short name T1098
Test name
Test status
Simulation time 39535168708 ps
CPU time 17.84 seconds
Started May 19 12:31:47 PM PDT 24
Finished May 19 12:32:08 PM PDT 24
Peak memory 200344 kb
Host smart-8a8c7ea3-9a66-401f-bec6-9409310bc628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678069342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1678069342
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.595530208
Short name T1180
Test name
Test status
Simulation time 18634192556 ps
CPU time 27.39 seconds
Started May 19 12:31:44 PM PDT 24
Finished May 19 12:32:13 PM PDT 24
Peak memory 200336 kb
Host smart-3d3917fd-cf52-4778-9144-27f4d2eb31fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595530208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.595530208
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.277170157
Short name T944
Test name
Test status
Simulation time 133163333521 ps
CPU time 54.08 seconds
Started May 19 12:31:43 PM PDT 24
Finished May 19 12:32:38 PM PDT 24
Peak memory 200292 kb
Host smart-70a2f28a-3cd0-473e-a66e-fe580973bc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277170157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.277170157
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1052014838
Short name T521
Test name
Test status
Simulation time 20278681 ps
CPU time 0.53 seconds
Started May 19 12:30:04 PM PDT 24
Finished May 19 12:30:12 PM PDT 24
Peak memory 195692 kb
Host smart-e1f456de-5a05-46de-bed2-f9cef88bba14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052014838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1052014838
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2961117740
Short name T1177
Test name
Test status
Simulation time 132715218461 ps
CPU time 67.25 seconds
Started May 19 12:29:44 PM PDT 24
Finished May 19 12:31:04 PM PDT 24
Peak memory 200408 kb
Host smart-cce3bf18-698a-4422-8fbc-d93b38dacc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961117740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2961117740
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1648624260
Short name T169
Test name
Test status
Simulation time 70367926519 ps
CPU time 30.05 seconds
Started May 19 12:29:43 PM PDT 24
Finished May 19 12:30:15 PM PDT 24
Peak memory 200260 kb
Host smart-4b93d8e7-ce9d-4d42-9ce1-3b752f7570ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648624260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1648624260
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3351036523
Short name T226
Test name
Test status
Simulation time 141128319265 ps
CPU time 207.87 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:33:21 PM PDT 24
Peak memory 200364 kb
Host smart-40f772f5-79cb-498a-8d03-948d341e1806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351036523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3351036523
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.44343502
Short name T327
Test name
Test status
Simulation time 68075419770 ps
CPU time 117.37 seconds
Started May 19 12:30:06 PM PDT 24
Finished May 19 12:32:09 PM PDT 24
Peak memory 200304 kb
Host smart-280fb383-8f41-44c3-9d50-3c978ac9b200
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44343502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.44343502
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2657413218
Short name T843
Test name
Test status
Simulation time 131864573887 ps
CPU time 327.14 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:35:23 PM PDT 24
Peak memory 200352 kb
Host smart-6e30ec76-044c-41a7-a7aa-b0e9fbbe4c27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2657413218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2657413218
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2202212846
Short name T396
Test name
Test status
Simulation time 3176598242 ps
CPU time 5.47 seconds
Started May 19 12:30:44 PM PDT 24
Finished May 19 12:30:53 PM PDT 24
Peak memory 197236 kb
Host smart-48a01842-1c96-4cfd-b899-4c681d155e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202212846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2202212846
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1234031781
Short name T268
Test name
Test status
Simulation time 44255134167 ps
CPU time 41.64 seconds
Started May 19 12:29:53 PM PDT 24
Finished May 19 12:30:42 PM PDT 24
Peak memory 200596 kb
Host smart-87529d14-377f-4f27-b7a6-0bac4139b669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234031781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1234031781
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1666747958
Short name T360
Test name
Test status
Simulation time 15069169179 ps
CPU time 874.08 seconds
Started May 19 12:30:35 PM PDT 24
Finished May 19 12:45:13 PM PDT 24
Peak memory 199508 kb
Host smart-4a87926b-aa71-47fb-ab6d-ac2155ed9a01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1666747958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1666747958
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.915269166
Short name T911
Test name
Test status
Simulation time 4222823660 ps
CPU time 7.24 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:29:59 PM PDT 24
Peak memory 198476 kb
Host smart-a0555929-4140-44bc-8382-5c779488f54b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=915269166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.915269166
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2423866873
Short name T672
Test name
Test status
Simulation time 21135442817 ps
CPU time 36.41 seconds
Started May 19 12:30:09 PM PDT 24
Finished May 19 12:30:50 PM PDT 24
Peak memory 200160 kb
Host smart-1fb351d2-b90b-451d-adb1-7711c1d14ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423866873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2423866873
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3460791206
Short name T379
Test name
Test status
Simulation time 6655524412 ps
CPU time 11.45 seconds
Started May 19 12:30:02 PM PDT 24
Finished May 19 12:30:21 PM PDT 24
Peak memory 196292 kb
Host smart-234c7a3c-0aa6-4e06-a579-8b84b7b450b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460791206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3460791206
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3530151356
Short name T46
Test name
Test status
Simulation time 10577952905 ps
CPU time 8.44 seconds
Started May 19 12:29:45 PM PDT 24
Finished May 19 12:29:59 PM PDT 24
Peak memory 200120 kb
Host smart-96f21d7d-bbaa-4d2d-b54f-619f13db684b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530151356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3530151356
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.127708821
Short name T788
Test name
Test status
Simulation time 102287697754 ps
CPU time 90.61 seconds
Started May 19 12:30:44 PM PDT 24
Finished May 19 12:32:18 PM PDT 24
Peak memory 199636 kb
Host smart-488c1fd2-03d9-45d7-862f-b52e527ffe15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127708821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.127708821
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.913154228
Short name T604
Test name
Test status
Simulation time 6729164438 ps
CPU time 28.49 seconds
Started May 19 12:30:00 PM PDT 24
Finished May 19 12:30:36 PM PDT 24
Peak memory 199996 kb
Host smart-47496ab2-644f-4259-96fa-bceb3ba946b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913154228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.913154228
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2416113334
Short name T783
Test name
Test status
Simulation time 24364338949 ps
CPU time 14.18 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:30:08 PM PDT 24
Peak memory 200176 kb
Host smart-0871a4f2-839b-4e35-90e6-fd74d051b203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416113334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2416113334
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1033256460
Short name T637
Test name
Test status
Simulation time 117017922653 ps
CPU time 31.53 seconds
Started May 19 12:31:43 PM PDT 24
Finished May 19 12:32:15 PM PDT 24
Peak memory 200316 kb
Host smart-349be2a3-3c01-44a5-b833-bc8e11028784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033256460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1033256460
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.4049739466
Short name T40
Test name
Test status
Simulation time 92127245951 ps
CPU time 18.68 seconds
Started May 19 12:31:41 PM PDT 24
Finished May 19 12:32:01 PM PDT 24
Peak memory 200332 kb
Host smart-9180f284-b0ae-49b0-bf9e-8bfa5568255c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049739466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.4049739466
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3304041009
Short name T960
Test name
Test status
Simulation time 46569130799 ps
CPU time 75.26 seconds
Started May 19 12:31:43 PM PDT 24
Finished May 19 12:32:59 PM PDT 24
Peak memory 200340 kb
Host smart-ac2d1815-556a-4a7c-b1d1-380f910bd233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304041009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3304041009
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.4266757040
Short name T490
Test name
Test status
Simulation time 83543425422 ps
CPU time 151.86 seconds
Started May 19 12:31:44 PM PDT 24
Finished May 19 12:34:17 PM PDT 24
Peak memory 200616 kb
Host smart-6638f3f2-c59b-4743-a6d2-1b123ca9359a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266757040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.4266757040
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2109552769
Short name T1154
Test name
Test status
Simulation time 61373918852 ps
CPU time 57.84 seconds
Started May 19 12:31:46 PM PDT 24
Finished May 19 12:32:45 PM PDT 24
Peak memory 200376 kb
Host smart-b4bcef3d-3acd-4a6b-9475-680b2c650dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109552769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2109552769
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1938386257
Short name T1163
Test name
Test status
Simulation time 18761711958 ps
CPU time 31.45 seconds
Started May 19 12:31:43 PM PDT 24
Finished May 19 12:32:16 PM PDT 24
Peak memory 200344 kb
Host smart-e337dc38-040e-470a-9b73-98f69f15181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938386257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1938386257
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1905527555
Short name T1116
Test name
Test status
Simulation time 34038065258 ps
CPU time 24.12 seconds
Started May 19 12:31:42 PM PDT 24
Finished May 19 12:32:07 PM PDT 24
Peak memory 199308 kb
Host smart-861c1c3d-ed7b-4ce1-95e7-5a71ae09fb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905527555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1905527555
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2748552559
Short name T305
Test name
Test status
Simulation time 124117437888 ps
CPU time 73.39 seconds
Started May 19 12:31:43 PM PDT 24
Finished May 19 12:32:58 PM PDT 24
Peak memory 200300 kb
Host smart-60c7700d-5864-481a-9359-1c5b4a21520c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748552559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2748552559
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3282980709
Short name T123
Test name
Test status
Simulation time 22699707554 ps
CPU time 10.89 seconds
Started May 19 12:31:41 PM PDT 24
Finished May 19 12:31:53 PM PDT 24
Peak memory 200152 kb
Host smart-19789f7b-a0a9-4805-8893-94e0b02f73f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282980709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3282980709
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1799287070
Short name T194
Test name
Test status
Simulation time 34039344543 ps
CPU time 17.91 seconds
Started May 19 12:31:47 PM PDT 24
Finished May 19 12:32:08 PM PDT 24
Peak memory 200312 kb
Host smart-c81b574b-63cd-48c4-ae09-255148115fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799287070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1799287070
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3380963431
Short name T985
Test name
Test status
Simulation time 14321532 ps
CPU time 0.64 seconds
Started May 19 12:30:13 PM PDT 24
Finished May 19 12:30:17 PM PDT 24
Peak memory 195664 kb
Host smart-1e9a298e-b420-4163-a98d-e67b543c2465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380963431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3380963431
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1562673807
Short name T164
Test name
Test status
Simulation time 42889749979 ps
CPU time 28.7 seconds
Started May 19 12:30:44 PM PDT 24
Finished May 19 12:31:16 PM PDT 24
Peak memory 199788 kb
Host smart-bff470e0-7013-4a51-836d-b913d9bea18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562673807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1562673807
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2176647145
Short name T111
Test name
Test status
Simulation time 22669026364 ps
CPU time 40.66 seconds
Started May 19 12:30:00 PM PDT 24
Finished May 19 12:30:48 PM PDT 24
Peak memory 200396 kb
Host smart-872a1a90-aef2-489b-ac10-86bdbab5453c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176647145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2176647145
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1542780118
Short name T828
Test name
Test status
Simulation time 94054103105 ps
CPU time 47 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:30:44 PM PDT 24
Peak memory 200336 kb
Host smart-f1a0781d-dad8-4d38-95f3-7780a0e3a259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542780118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1542780118
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1743822670
Short name T1141
Test name
Test status
Simulation time 21195683059 ps
CPU time 22.87 seconds
Started May 19 12:30:03 PM PDT 24
Finished May 19 12:30:34 PM PDT 24
Peak memory 200156 kb
Host smart-28cd18b7-740e-4331-8dea-94d7c152cd98
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743822670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1743822670
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.4216087656
Short name T1173
Test name
Test status
Simulation time 46852965416 ps
CPU time 474.36 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:37:48 PM PDT 24
Peak memory 200316 kb
Host smart-6f5c9276-0d69-43f3-b67d-c021d98afa88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4216087656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.4216087656
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.4134058295
Short name T874
Test name
Test status
Simulation time 5009426947 ps
CPU time 8.76 seconds
Started May 19 12:29:53 PM PDT 24
Finished May 19 12:30:09 PM PDT 24
Peak memory 196464 kb
Host smart-1e1cad16-796b-465a-8eb9-b7ac55acb1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134058295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.4134058295
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3516444725
Short name T460
Test name
Test status
Simulation time 21630499508 ps
CPU time 10.34 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:30:19 PM PDT 24
Peak memory 197388 kb
Host smart-203a42c8-2c1e-45c5-a312-c7a63b4db890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516444725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3516444725
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1178550893
Short name T322
Test name
Test status
Simulation time 14025007450 ps
CPU time 383.22 seconds
Started May 19 12:29:59 PM PDT 24
Finished May 19 12:36:30 PM PDT 24
Peak memory 200288 kb
Host smart-21c5f1bf-709e-4baf-a877-42819912035a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178550893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1178550893
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4273926172
Short name T413
Test name
Test status
Simulation time 6439813060 ps
CPU time 63.13 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:58 PM PDT 24
Peak memory 199420 kb
Host smart-32e6b2ce-869c-45f4-96a8-d5efe6f52f55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4273926172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4273926172
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2030533339
Short name T174
Test name
Test status
Simulation time 32870373990 ps
CPU time 57.88 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:31:07 PM PDT 24
Peak memory 199960 kb
Host smart-41172cba-53a8-4826-9a8d-85d99a9d2626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030533339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2030533339
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3815513850
Short name T285
Test name
Test status
Simulation time 33413850880 ps
CPU time 9.73 seconds
Started May 19 12:30:09 PM PDT 24
Finished May 19 12:30:24 PM PDT 24
Peak memory 196280 kb
Host smart-10d2d6bb-2b89-4ee5-b086-a145fd49db36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815513850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3815513850
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2641766570
Short name T698
Test name
Test status
Simulation time 112176248 ps
CPU time 0.77 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:29:52 PM PDT 24
Peak memory 197448 kb
Host smart-d7711a30-232d-4ac3-bfac-d36a4c77f8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641766570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2641766570
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3850116650
Short name T818
Test name
Test status
Simulation time 58585152565 ps
CPU time 26.28 seconds
Started May 19 12:30:12 PM PDT 24
Finished May 19 12:30:42 PM PDT 24
Peak memory 200380 kb
Host smart-327f4969-7416-48e6-84aa-5cdf5c7cedd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850116650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3850116650
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3175983477
Short name T852
Test name
Test status
Simulation time 48265930195 ps
CPU time 226.44 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:33:37 PM PDT 24
Peak memory 208544 kb
Host smart-4e20562d-b326-4026-a074-940e17ef6990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175983477 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3175983477
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2571576534
Short name T1133
Test name
Test status
Simulation time 894526697 ps
CPU time 3.48 seconds
Started May 19 12:30:04 PM PDT 24
Finished May 19 12:30:15 PM PDT 24
Peak memory 198740 kb
Host smart-a80a76e8-fc67-4767-ba22-561e3b46c9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571576534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2571576534
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3162073293
Short name T579
Test name
Test status
Simulation time 62853747588 ps
CPU time 72.61 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:31:22 PM PDT 24
Peak memory 200328 kb
Host smart-55890231-f4a3-4e87-9704-b753b3150fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162073293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3162073293
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2702885829
Short name T854
Test name
Test status
Simulation time 172734411083 ps
CPU time 71.54 seconds
Started May 19 12:31:52 PM PDT 24
Finished May 19 12:33:05 PM PDT 24
Peak memory 200264 kb
Host smart-00800924-d8d5-4528-848c-3b9388a5ff7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702885829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2702885829
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2728615414
Short name T934
Test name
Test status
Simulation time 26912857135 ps
CPU time 31.4 seconds
Started May 19 12:31:54 PM PDT 24
Finished May 19 12:32:26 PM PDT 24
Peak memory 200272 kb
Host smart-137fb5dc-c140-4056-a5a3-eb6fe6773243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728615414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2728615414
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1886993750
Short name T777
Test name
Test status
Simulation time 40861667288 ps
CPU time 79.71 seconds
Started May 19 12:31:52 PM PDT 24
Finished May 19 12:33:12 PM PDT 24
Peak memory 200280 kb
Host smart-0b9eaa13-2486-4a2c-99a2-6322f9bb3374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886993750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1886993750
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2096011519
Short name T204
Test name
Test status
Simulation time 327260062851 ps
CPU time 82.28 seconds
Started May 19 12:31:48 PM PDT 24
Finished May 19 12:33:13 PM PDT 24
Peak memory 200320 kb
Host smart-e96fe849-b21a-4490-a558-73f23cbe6ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096011519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2096011519
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3099896702
Short name T1056
Test name
Test status
Simulation time 9529334331 ps
CPU time 16.5 seconds
Started May 19 12:31:59 PM PDT 24
Finished May 19 12:32:16 PM PDT 24
Peak memory 200324 kb
Host smart-6105ccf7-bcf6-4657-ba48-e6f24a085449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099896702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3099896702
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.874813354
Short name T940
Test name
Test status
Simulation time 172570398202 ps
CPU time 66.1 seconds
Started May 19 12:31:52 PM PDT 24
Finished May 19 12:32:59 PM PDT 24
Peak memory 200116 kb
Host smart-3ad0c852-b99c-472c-b096-bb722e3a65fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874813354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.874813354
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2110279103
Short name T210
Test name
Test status
Simulation time 25482083155 ps
CPU time 13.62 seconds
Started May 19 12:31:48 PM PDT 24
Finished May 19 12:32:04 PM PDT 24
Peak memory 200304 kb
Host smart-22cdaaa6-cba2-489d-b792-21e41a1fafd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110279103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2110279103
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.22267405
Short name T947
Test name
Test status
Simulation time 65619814637 ps
CPU time 202.5 seconds
Started May 19 12:31:52 PM PDT 24
Finished May 19 12:35:15 PM PDT 24
Peak memory 200304 kb
Host smart-25b5ac75-f904-40f6-9578-ec713a74e40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22267405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.22267405
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1279785651
Short name T218
Test name
Test status
Simulation time 107114769762 ps
CPU time 48.03 seconds
Started May 19 12:31:48 PM PDT 24
Finished May 19 12:32:38 PM PDT 24
Peak memory 200356 kb
Host smart-66a0343d-352d-4495-88ce-310d922cdfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279785651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1279785651
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1227472713
Short name T185
Test name
Test status
Simulation time 143485932650 ps
CPU time 269.83 seconds
Started May 19 12:31:59 PM PDT 24
Finished May 19 12:36:29 PM PDT 24
Peak memory 200312 kb
Host smart-60543a99-3dbc-4675-a2e8-4ebbd47519b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227472713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1227472713
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2597649402
Short name T978
Test name
Test status
Simulation time 18472217 ps
CPU time 0.55 seconds
Started May 19 12:29:58 PM PDT 24
Finished May 19 12:30:05 PM PDT 24
Peak memory 195644 kb
Host smart-15899575-9e06-4c75-93d0-650fca1b3088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597649402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2597649402
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3755307834
Short name T959
Test name
Test status
Simulation time 29875806809 ps
CPU time 22.53 seconds
Started May 19 12:30:07 PM PDT 24
Finished May 19 12:30:35 PM PDT 24
Peak memory 200744 kb
Host smart-48995f4d-ed22-43a2-abbd-719e15ef3226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755307834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3755307834
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1945239642
Short name T1060
Test name
Test status
Simulation time 25594354846 ps
CPU time 67.07 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:31:04 PM PDT 24
Peak memory 200284 kb
Host smart-290ce8c4-a009-4109-80f4-b9e438ce1278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945239642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1945239642
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1357875392
Short name T190
Test name
Test status
Simulation time 49542855349 ps
CPU time 43.55 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:30:37 PM PDT 24
Peak memory 200296 kb
Host smart-3cb90b13-c97f-4206-b0fc-02acf8c8e0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357875392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1357875392
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3113944081
Short name T1029
Test name
Test status
Simulation time 64174289070 ps
CPU time 96.78 seconds
Started May 19 12:29:56 PM PDT 24
Finished May 19 12:31:39 PM PDT 24
Peak memory 200332 kb
Host smart-7b140a1c-d8fe-4bab-8bdb-3d03c6b86e06
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113944081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3113944081
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1562889926
Short name T878
Test name
Test status
Simulation time 75903996347 ps
CPU time 259.55 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:34:17 PM PDT 24
Peak memory 200264 kb
Host smart-b02da4d6-217a-4d19-8e3c-3000f541ffce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1562889926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1562889926
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3366202597
Short name T446
Test name
Test status
Simulation time 2512534426 ps
CPU time 2.51 seconds
Started May 19 12:29:56 PM PDT 24
Finished May 19 12:30:05 PM PDT 24
Peak memory 199460 kb
Host smart-cded86f1-11eb-4255-a5a4-deb7f5aef524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366202597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3366202597
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3290392947
Short name T622
Test name
Test status
Simulation time 19765963411 ps
CPU time 91.07 seconds
Started May 19 12:30:03 PM PDT 24
Finished May 19 12:31:42 PM PDT 24
Peak memory 199464 kb
Host smart-ac118c1c-839d-448b-bf85-ab00157f2e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290392947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3290392947
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.206743810
Short name T525
Test name
Test status
Simulation time 14258435327 ps
CPU time 154.83 seconds
Started May 19 12:30:00 PM PDT 24
Finished May 19 12:32:42 PM PDT 24
Peak memory 200264 kb
Host smart-03598583-ce88-430a-b306-7635ea7c25cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=206743810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.206743810
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.353965485
Short name T408
Test name
Test status
Simulation time 3054615730 ps
CPU time 6.04 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:29:59 PM PDT 24
Peak memory 198120 kb
Host smart-8f02acc5-2b71-4b3e-b7ec-52e9a01cee44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=353965485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.353965485
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3193922119
Short name T721
Test name
Test status
Simulation time 66779834267 ps
CPU time 116.02 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:31:49 PM PDT 24
Peak memory 200276 kb
Host smart-07ad20e8-6562-40b5-bf97-1a905e784f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193922119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3193922119
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2996046890
Short name T316
Test name
Test status
Simulation time 93785588443 ps
CPU time 144.81 seconds
Started May 19 12:30:05 PM PDT 24
Finished May 19 12:32:36 PM PDT 24
Peak memory 196016 kb
Host smart-ddfe5b94-29e0-4ba4-8c92-090fe5b9a7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996046890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2996046890
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2831130209
Short name T263
Test name
Test status
Simulation time 934140427 ps
CPU time 3.71 seconds
Started May 19 12:29:45 PM PDT 24
Finished May 19 12:29:54 PM PDT 24
Peak memory 200136 kb
Host smart-5a715e87-40e9-45b0-a5ec-038528e53fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831130209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2831130209
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2101140833
Short name T527
Test name
Test status
Simulation time 51838210098 ps
CPU time 1060.02 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:47:37 PM PDT 24
Peak memory 225180 kb
Host smart-a8731ea6-ad13-4ac5-9c33-3a91d935a67d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101140833 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2101140833
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.4162313590
Short name T601
Test name
Test status
Simulation time 6991180522 ps
CPU time 30.69 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:26 PM PDT 24
Peak memory 200104 kb
Host smart-7d522255-3ae3-4c5c-977d-92bffba17577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162313590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.4162313590
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.4080228476
Short name T1094
Test name
Test status
Simulation time 40023550538 ps
CPU time 68.68 seconds
Started May 19 12:29:51 PM PDT 24
Finished May 19 12:31:08 PM PDT 24
Peak memory 200292 kb
Host smart-0c6fd0d5-c482-40e9-b6ab-c96ccb19e6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080228476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.4080228476
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1532137619
Short name T600
Test name
Test status
Simulation time 27686452820 ps
CPU time 46.75 seconds
Started May 19 12:32:01 PM PDT 24
Finished May 19 12:32:48 PM PDT 24
Peak memory 200184 kb
Host smart-8dcca6a1-6104-4a96-a1c0-5e0dbae1bbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532137619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1532137619
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3477320489
Short name T213
Test name
Test status
Simulation time 157323034120 ps
CPU time 50.32 seconds
Started May 19 12:31:55 PM PDT 24
Finished May 19 12:32:46 PM PDT 24
Peak memory 200108 kb
Host smart-ba15ad98-6671-4e40-9607-da824998115a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477320489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3477320489
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2424278090
Short name T126
Test name
Test status
Simulation time 36197181929 ps
CPU time 28.78 seconds
Started May 19 12:31:57 PM PDT 24
Finished May 19 12:32:27 PM PDT 24
Peak memory 200172 kb
Host smart-226e926e-c4d1-4924-8596-fd80ced37694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424278090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2424278090
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3086640293
Short name T595
Test name
Test status
Simulation time 112703592956 ps
CPU time 97.09 seconds
Started May 19 12:31:48 PM PDT 24
Finished May 19 12:33:28 PM PDT 24
Peak memory 200276 kb
Host smart-535fd536-2a88-4054-b45a-abee7cedf78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086640293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3086640293
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3270618686
Short name T198
Test name
Test status
Simulation time 38259565807 ps
CPU time 81.45 seconds
Started May 19 12:31:49 PM PDT 24
Finished May 19 12:33:13 PM PDT 24
Peak memory 200592 kb
Host smart-7ee5c767-9830-4ac0-bbf1-18ee95b64697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270618686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3270618686
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.590005411
Short name T372
Test name
Test status
Simulation time 159733993753 ps
CPU time 68.05 seconds
Started May 19 12:31:52 PM PDT 24
Finished May 19 12:33:01 PM PDT 24
Peak memory 200424 kb
Host smart-4132b078-7408-4de5-94b2-e37d332caa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590005411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.590005411
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1015427753
Short name T224
Test name
Test status
Simulation time 134811309042 ps
CPU time 255.06 seconds
Started May 19 12:32:03 PM PDT 24
Finished May 19 12:36:19 PM PDT 24
Peak memory 200324 kb
Host smart-318e1146-9f08-44ea-b3ff-fe514bafccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015427753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1015427753
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.826078843
Short name T822
Test name
Test status
Simulation time 31630867520 ps
CPU time 50.61 seconds
Started May 19 12:31:56 PM PDT 24
Finished May 19 12:32:47 PM PDT 24
Peak memory 200064 kb
Host smart-af02f39a-b22f-41da-882e-0870c9f543cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826078843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.826078843
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1868073491
Short name T1090
Test name
Test status
Simulation time 50405969492 ps
CPU time 199.79 seconds
Started May 19 12:31:57 PM PDT 24
Finished May 19 12:35:18 PM PDT 24
Peak memory 200340 kb
Host smart-a5c4a9ce-3635-4247-a1cd-408561e42c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868073491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1868073491
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3091510590
Short name T951
Test name
Test status
Simulation time 15944695385 ps
CPU time 8.08 seconds
Started May 19 12:31:57 PM PDT 24
Finished May 19 12:32:06 PM PDT 24
Peak memory 200404 kb
Host smart-8cea0edb-4d16-4f3d-a283-5bba79149363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091510590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3091510590
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3477757134
Short name T693
Test name
Test status
Simulation time 40649030 ps
CPU time 0.55 seconds
Started May 19 12:30:07 PM PDT 24
Finished May 19 12:30:13 PM PDT 24
Peak memory 195628 kb
Host smart-03ad0697-57ea-4368-9a5f-6f16cf2dfee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477757134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3477757134
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2668596971
Short name T627
Test name
Test status
Simulation time 17557249640 ps
CPU time 37.07 seconds
Started May 19 12:30:07 PM PDT 24
Finished May 19 12:30:50 PM PDT 24
Peak memory 200244 kb
Host smart-37803559-06e7-4680-84d0-1440d8a39b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668596971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2668596971
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.26646227
Short name T701
Test name
Test status
Simulation time 81626878231 ps
CPU time 34.15 seconds
Started May 19 12:30:06 PM PDT 24
Finished May 19 12:30:47 PM PDT 24
Peak memory 200332 kb
Host smart-98ca1b4a-f769-4999-9d6d-89dd3a3810c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26646227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.26646227
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.190965787
Short name T183
Test name
Test status
Simulation time 88821959881 ps
CPU time 140.17 seconds
Started May 19 12:30:12 PM PDT 24
Finished May 19 12:32:36 PM PDT 24
Peak memory 200328 kb
Host smart-d48df6f2-0c04-402a-aeee-1b340ab41cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190965787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.190965787
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2985672936
Short name T949
Test name
Test status
Simulation time 22440748158 ps
CPU time 38.66 seconds
Started May 19 12:29:53 PM PDT 24
Finished May 19 12:30:40 PM PDT 24
Peak memory 199848 kb
Host smart-7911fbc0-b4bd-461b-8d71-f532559886a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985672936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2985672936
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3773224874
Short name T836
Test name
Test status
Simulation time 82744253769 ps
CPU time 526.53 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:38:38 PM PDT 24
Peak memory 200144 kb
Host smart-4cefba5c-14ce-4e78-afbc-e0cb8795211b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3773224874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3773224874
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2105651318
Short name T406
Test name
Test status
Simulation time 9594478243 ps
CPU time 5.96 seconds
Started May 19 12:29:55 PM PDT 24
Finished May 19 12:30:08 PM PDT 24
Peak memory 200180 kb
Host smart-222787fa-881b-4821-825c-67bded0c2bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105651318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2105651318
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2220987988
Short name T386
Test name
Test status
Simulation time 25781357208 ps
CPU time 46.17 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:43 PM PDT 24
Peak memory 198192 kb
Host smart-0249f58a-3fff-4350-80ab-1deb511955d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220987988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2220987988
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1252123637
Short name T1038
Test name
Test status
Simulation time 7346793011 ps
CPU time 322.03 seconds
Started May 19 12:30:44 PM PDT 24
Finished May 19 12:36:09 PM PDT 24
Peak memory 199732 kb
Host smart-e45ebd74-4c4b-424e-a8cd-7c8058104184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1252123637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1252123637
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.740480379
Short name T686
Test name
Test status
Simulation time 4792961486 ps
CPU time 19.44 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:30:17 PM PDT 24
Peak memory 199436 kb
Host smart-e680cb0d-e954-43ca-a85d-7b63d6401047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=740480379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.740480379
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3908146833
Short name T689
Test name
Test status
Simulation time 13631733374 ps
CPU time 12.91 seconds
Started May 19 12:30:03 PM PDT 24
Finished May 19 12:30:24 PM PDT 24
Peak memory 200180 kb
Host smart-48085095-aa87-48a8-b577-c1843cbd4f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908146833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3908146833
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3829289613
Short name T856
Test name
Test status
Simulation time 30821602282 ps
CPU time 12.68 seconds
Started May 19 12:29:56 PM PDT 24
Finished May 19 12:30:15 PM PDT 24
Peak memory 196340 kb
Host smart-1bd36553-ca9d-44aa-b0b3-90764bfe2c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829289613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3829289613
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3552456389
Short name T376
Test name
Test status
Simulation time 456453783 ps
CPU time 1.19 seconds
Started May 19 12:30:45 PM PDT 24
Finished May 19 12:30:49 PM PDT 24
Peak memory 198364 kb
Host smart-7e766a91-1678-4b01-996e-cabdfcfdcf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552456389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3552456389
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.745373329
Short name T770
Test name
Test status
Simulation time 53935402799 ps
CPU time 86.93 seconds
Started May 19 12:30:05 PM PDT 24
Finished May 19 12:31:39 PM PDT 24
Peak memory 200240 kb
Host smart-09047bd9-6fc2-4eaf-838a-4cd9f43a7011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745373329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.745373329
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3354937442
Short name T71
Test name
Test status
Simulation time 163093931836 ps
CPU time 742.54 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:42:14 PM PDT 24
Peak memory 216696 kb
Host smart-69f72de0-83a4-48e1-9098-b6e017f9c3ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354937442 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3354937442
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.30314169
Short name T946
Test name
Test status
Simulation time 2161055668 ps
CPU time 2.17 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:29:59 PM PDT 24
Peak memory 199780 kb
Host smart-6c0f47e4-205b-4b21-84a9-9ceb324bf53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30314169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.30314169
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3848531989
Short name T815
Test name
Test status
Simulation time 171719302296 ps
CPU time 39.01 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:30:36 PM PDT 24
Peak memory 200328 kb
Host smart-9e4e5110-9602-4449-9583-bec4b17cece7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848531989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3848531989
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2641230412
Short name T905
Test name
Test status
Simulation time 114428000611 ps
CPU time 180.94 seconds
Started May 19 12:31:48 PM PDT 24
Finished May 19 12:34:51 PM PDT 24
Peak memory 200256 kb
Host smart-10bdfef7-4099-4f68-9db1-ec7d012bfa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641230412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2641230412
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1743124571
Short name T592
Test name
Test status
Simulation time 46693108914 ps
CPU time 16.03 seconds
Started May 19 12:31:48 PM PDT 24
Finished May 19 12:32:07 PM PDT 24
Peak memory 200212 kb
Host smart-4dcd12f3-9b51-4e33-860c-74bf20594964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743124571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1743124571
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2868018860
Short name T683
Test name
Test status
Simulation time 87593999632 ps
CPU time 112.9 seconds
Started May 19 12:31:49 PM PDT 24
Finished May 19 12:33:44 PM PDT 24
Peak memory 200096 kb
Host smart-e7f0c806-ab2b-4b94-ab05-825727d45006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868018860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2868018860
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.965634354
Short name T576
Test name
Test status
Simulation time 36698994808 ps
CPU time 64.53 seconds
Started May 19 12:31:57 PM PDT 24
Finished May 19 12:33:03 PM PDT 24
Peak memory 200320 kb
Host smart-1f29ac17-ca73-49cb-ab79-1d114b8cf90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965634354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.965634354
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2984085266
Short name T339
Test name
Test status
Simulation time 94684745871 ps
CPU time 156.88 seconds
Started May 19 12:31:57 PM PDT 24
Finished May 19 12:34:35 PM PDT 24
Peak memory 200412 kb
Host smart-77a56950-4465-4184-8e5c-a1afe6bbf5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984085266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2984085266
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2812734723
Short name T8
Test name
Test status
Simulation time 63029626815 ps
CPU time 29.22 seconds
Started May 19 12:31:58 PM PDT 24
Finished May 19 12:32:28 PM PDT 24
Peak memory 200220 kb
Host smart-fdca1118-3726-4ca2-b2d7-cd1064a302f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812734723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2812734723
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.262859291
Short name T293
Test name
Test status
Simulation time 9619798271 ps
CPU time 18.58 seconds
Started May 19 12:31:49 PM PDT 24
Finished May 19 12:32:10 PM PDT 24
Peak memory 200340 kb
Host smart-62c459a8-f799-47bc-8ed6-1079b4c7dc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262859291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.262859291
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1444831220
Short name T216
Test name
Test status
Simulation time 514104353251 ps
CPU time 159.91 seconds
Started May 19 12:31:50 PM PDT 24
Finished May 19 12:34:32 PM PDT 24
Peak memory 200260 kb
Host smart-9d51b807-fd2f-460b-87d6-bc934e66e235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444831220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1444831220
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3553224553
Short name T682
Test name
Test status
Simulation time 64334538195 ps
CPU time 33.99 seconds
Started May 19 12:31:52 PM PDT 24
Finished May 19 12:32:27 PM PDT 24
Peak memory 200272 kb
Host smart-2b392e51-e01c-4a4e-a59b-b95407e6e648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553224553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3553224553
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2910858064
Short name T998
Test name
Test status
Simulation time 14451362 ps
CPU time 0.54 seconds
Started May 19 12:29:52 PM PDT 24
Finished May 19 12:30:00 PM PDT 24
Peak memory 195612 kb
Host smart-d9c36eeb-419c-4c3e-9e70-a37407767fa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910858064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2910858064
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1051483749
Short name T706
Test name
Test status
Simulation time 91843580205 ps
CPU time 42.21 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:30:37 PM PDT 24
Peak memory 200332 kb
Host smart-c79197b9-0bb9-4a3f-99a7-713f9010fb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051483749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1051483749
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1352388872
Short name T870
Test name
Test status
Simulation time 175590404419 ps
CPU time 85.38 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:31:34 PM PDT 24
Peak memory 200288 kb
Host smart-91f10034-bd6e-4f2f-b72b-84ffc7c28454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352388872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1352388872
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3565252814
Short name T1178
Test name
Test status
Simulation time 31481792849 ps
CPU time 51.71 seconds
Started May 19 12:30:14 PM PDT 24
Finished May 19 12:31:09 PM PDT 24
Peak memory 200324 kb
Host smart-a770e0a4-91c5-4ff9-afd4-7337d9fd7b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565252814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3565252814
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2701615180
Short name T865
Test name
Test status
Simulation time 19839623880 ps
CPU time 13.52 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:30:07 PM PDT 24
Peak memory 197036 kb
Host smart-5305d2fd-daab-47c9-aa82-66a63fcb63aa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701615180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2701615180
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2735980968
Short name T369
Test name
Test status
Simulation time 120149037900 ps
CPU time 972.8 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:46:08 PM PDT 24
Peak memory 200256 kb
Host smart-af80350d-450f-41dc-bc0b-61d3dde3e96e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2735980968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2735980968
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.606191768
Short name T354
Test name
Test status
Simulation time 8277713315 ps
CPU time 17.99 seconds
Started May 19 12:30:11 PM PDT 24
Finished May 19 12:30:33 PM PDT 24
Peak memory 199416 kb
Host smart-3798b035-b59f-4606-bf28-facd6999589f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606191768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.606191768
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3970380776
Short name T274
Test name
Test status
Simulation time 65161271284 ps
CPU time 49.45 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:30:44 PM PDT 24
Peak memory 199112 kb
Host smart-1ebbf7a8-2a9f-463b-be3e-23e85d0b1977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970380776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3970380776
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2399889878
Short name T265
Test name
Test status
Simulation time 12695424665 ps
CPU time 686.34 seconds
Started May 19 12:29:46 PM PDT 24
Finished May 19 12:41:18 PM PDT 24
Peak memory 200148 kb
Host smart-7d2fe2d6-7d4f-44c2-b355-3ee6709b5975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399889878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2399889878
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1418957449
Short name T486
Test name
Test status
Simulation time 6603468122 ps
CPU time 55.74 seconds
Started May 19 12:29:50 PM PDT 24
Finished May 19 12:30:54 PM PDT 24
Peak memory 198408 kb
Host smart-be9c1246-c140-41a5-b11e-94834f35d63f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418957449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1418957449
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3027450203
Short name T715
Test name
Test status
Simulation time 122483349534 ps
CPU time 28.55 seconds
Started May 19 12:30:10 PM PDT 24
Finished May 19 12:30:43 PM PDT 24
Peak memory 200192 kb
Host smart-8aa5b38d-6254-4288-8227-fb16c841aa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027450203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3027450203
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2867327541
Short name T504
Test name
Test status
Simulation time 3630224014 ps
CPU time 6.7 seconds
Started May 19 12:29:51 PM PDT 24
Finished May 19 12:30:06 PM PDT 24
Peak memory 196520 kb
Host smart-3fcff504-cb80-4f1f-a75c-5fad41740dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867327541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2867327541
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2305611941
Short name T1026
Test name
Test status
Simulation time 10586360883 ps
CPU time 38.64 seconds
Started May 19 12:29:57 PM PDT 24
Finished May 19 12:30:42 PM PDT 24
Peak memory 199864 kb
Host smart-f2383590-0446-4762-9db4-04706facb9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305611941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2305611941
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2420222266
Short name T245
Test name
Test status
Simulation time 155762624464 ps
CPU time 261.5 seconds
Started May 19 12:30:00 PM PDT 24
Finished May 19 12:34:30 PM PDT 24
Peak memory 200316 kb
Host smart-ad3c4fcc-da46-4ecb-bb95-cad9e27e0890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420222266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2420222266
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2502274450
Short name T1011
Test name
Test status
Simulation time 2312921450 ps
CPU time 3.03 seconds
Started May 19 12:30:02 PM PDT 24
Finished May 19 12:30:13 PM PDT 24
Peak memory 199260 kb
Host smart-b84b6f1e-2d49-434f-9f28-76420e390d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502274450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2502274450
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3149026110
Short name T397
Test name
Test status
Simulation time 6278405895 ps
CPU time 6.09 seconds
Started May 19 12:30:08 PM PDT 24
Finished May 19 12:30:20 PM PDT 24
Peak memory 198128 kb
Host smart-b3ec7dbc-e6d0-43b6-97af-ead0022f865d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149026110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3149026110
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2391728980
Short name T809
Test name
Test status
Simulation time 72347547034 ps
CPU time 40.58 seconds
Started May 19 12:31:49 PM PDT 24
Finished May 19 12:32:32 PM PDT 24
Peak memory 200320 kb
Host smart-f3c87c28-4d35-4c7c-ad99-f5f09457a903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391728980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2391728980
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1224025100
Short name T193
Test name
Test status
Simulation time 12922119695 ps
CPU time 5.18 seconds
Started May 19 12:31:52 PM PDT 24
Finished May 19 12:31:58 PM PDT 24
Peak memory 200328 kb
Host smart-f98af177-9413-4dde-b637-29a3d4d4b014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224025100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1224025100
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1491441178
Short name T442
Test name
Test status
Simulation time 23750758077 ps
CPU time 15.55 seconds
Started May 19 12:31:50 PM PDT 24
Finished May 19 12:32:07 PM PDT 24
Peak memory 200224 kb
Host smart-74f25a64-191f-45d0-ae85-034c49326272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491441178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1491441178
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1521231822
Short name T748
Test name
Test status
Simulation time 50433477039 ps
CPU time 14.05 seconds
Started May 19 12:31:53 PM PDT 24
Finished May 19 12:32:08 PM PDT 24
Peak memory 200404 kb
Host smart-cba1eee8-7150-4109-8cba-941f02098d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521231822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1521231822
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2361619163
Short name T252
Test name
Test status
Simulation time 259109756902 ps
CPU time 504.85 seconds
Started May 19 12:31:57 PM PDT 24
Finished May 19 12:40:22 PM PDT 24
Peak memory 200284 kb
Host smart-44036c6a-e6c1-4c4c-a664-579ca037e85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361619163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2361619163
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2889965171
Short name T839
Test name
Test status
Simulation time 228255266803 ps
CPU time 46.81 seconds
Started May 19 12:31:53 PM PDT 24
Finished May 19 12:32:41 PM PDT 24
Peak memory 200260 kb
Host smart-1b103c13-e029-4159-8c07-aa6384e12545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889965171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2889965171
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3269931507
Short name T750
Test name
Test status
Simulation time 28072013761 ps
CPU time 102.9 seconds
Started May 19 12:31:57 PM PDT 24
Finished May 19 12:33:41 PM PDT 24
Peak memory 200248 kb
Host smart-578b5493-6b7e-4bf8-a030-8da84a298f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269931507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3269931507
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1535282404
Short name T157
Test name
Test status
Simulation time 176929390435 ps
CPU time 85.53 seconds
Started May 19 12:31:55 PM PDT 24
Finished May 19 12:33:21 PM PDT 24
Peak memory 200212 kb
Host smart-2f2845dd-3c6e-4070-a3e7-aedc73c32783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535282404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1535282404
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3604271087
Short name T105
Test name
Test status
Simulation time 86486623666 ps
CPU time 39.83 seconds
Started May 19 12:32:01 PM PDT 24
Finished May 19 12:32:41 PM PDT 24
Peak memory 200212 kb
Host smart-5080f7af-899e-4f96-a7e0-03f5ae81d39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604271087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3604271087
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3705569293
Short name T781
Test name
Test status
Simulation time 14292277 ps
CPU time 0.56 seconds
Started May 19 12:29:02 PM PDT 24
Finished May 19 12:29:03 PM PDT 24
Peak memory 195612 kb
Host smart-2954391c-c9fd-445b-84aa-afcdb8ed6f39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705569293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3705569293
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2503051612
Short name T1161
Test name
Test status
Simulation time 29272354806 ps
CPU time 48.74 seconds
Started May 19 12:28:56 PM PDT 24
Finished May 19 12:29:46 PM PDT 24
Peak memory 200276 kb
Host smart-17421d88-d3cd-4e95-9e6a-523358e9dcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503051612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2503051612
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.4143363240
Short name T623
Test name
Test status
Simulation time 34183919995 ps
CPU time 78.61 seconds
Started May 19 12:28:54 PM PDT 24
Finished May 19 12:30:13 PM PDT 24
Peak memory 200268 kb
Host smart-fdb49cd0-1d29-456c-8dee-6801501c9690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143363240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.4143363240
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_intr.1127779133
Short name T972
Test name
Test status
Simulation time 383084249391 ps
CPU time 575.27 seconds
Started May 19 12:28:53 PM PDT 24
Finished May 19 12:38:28 PM PDT 24
Peak memory 199872 kb
Host smart-6937b25f-daed-4d5b-94b5-632ca53d48c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127779133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1127779133
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1341995635
Short name T523
Test name
Test status
Simulation time 84370496901 ps
CPU time 693.34 seconds
Started May 19 12:28:53 PM PDT 24
Finished May 19 12:40:27 PM PDT 24
Peak memory 200284 kb
Host smart-27e57906-4d23-4d93-bf15-2e1801507520
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1341995635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1341995635
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.4060210247
Short name T888
Test name
Test status
Simulation time 2051870118 ps
CPU time 1.75 seconds
Started May 19 12:29:25 PM PDT 24
Finished May 19 12:29:28 PM PDT 24
Peak memory 199836 kb
Host smart-dd18f898-6056-4219-a774-5a22e28c8aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060210247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.4060210247
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3700840720
Short name T99
Test name
Test status
Simulation time 113384884396 ps
CPU time 666.1 seconds
Started May 19 12:29:18 PM PDT 24
Finished May 19 12:40:26 PM PDT 24
Peak memory 200880 kb
Host smart-b94cb526-7008-40a4-a2bb-6b86c7ed87e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700840720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3700840720
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.824573446
Short name T52
Test name
Test status
Simulation time 23437712543 ps
CPU time 191.29 seconds
Started May 19 12:29:16 PM PDT 24
Finished May 19 12:32:29 PM PDT 24
Peak memory 200240 kb
Host smart-613cd341-ba85-45ab-9783-97287347cd1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824573446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.824573446
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3605904431
Short name T11
Test name
Test status
Simulation time 3381772478 ps
CPU time 9.2 seconds
Started May 19 12:29:11 PM PDT 24
Finished May 19 12:29:21 PM PDT 24
Peak memory 199080 kb
Host smart-8da7ef2a-2bf3-450b-864e-edfdf63c3f9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605904431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3605904431
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3527886810
Short name T1067
Test name
Test status
Simulation time 78550558916 ps
CPU time 114.97 seconds
Started May 19 12:28:54 PM PDT 24
Finished May 19 12:30:50 PM PDT 24
Peak memory 200104 kb
Host smart-9f95a80f-2e03-4065-bf7b-69a13f3b82ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527886810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3527886810
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2215360140
Short name T714
Test name
Test status
Simulation time 3527831855 ps
CPU time 6.41 seconds
Started May 19 12:29:29 PM PDT 24
Finished May 19 12:29:37 PM PDT 24
Peak memory 196544 kb
Host smart-d332406d-622b-4818-aafa-a98f50e6427e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215360140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2215360140
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_smoke.2426417236
Short name T421
Test name
Test status
Simulation time 507526782 ps
CPU time 1.78 seconds
Started May 19 12:28:54 PM PDT 24
Finished May 19 12:28:57 PM PDT 24
Peak memory 198524 kb
Host smart-3f7258d1-4deb-4877-814c-1fdc5ed1418b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426417236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2426417236
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.702150043
Short name T900
Test name
Test status
Simulation time 457208553225 ps
CPU time 705.71 seconds
Started May 19 12:28:53 PM PDT 24
Finished May 19 12:40:42 PM PDT 24
Peak memory 200320 kb
Host smart-b2359c35-04ad-427f-ae68-f96729f9e1ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702150043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.702150043
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2043823816
Short name T311
Test name
Test status
Simulation time 28355171286 ps
CPU time 382.26 seconds
Started May 19 12:29:30 PM PDT 24
Finished May 19 12:35:54 PM PDT 24
Peak memory 216964 kb
Host smart-40207506-b7da-4dd5-9b8f-29843bd899cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043823816 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2043823816
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.854228218
Short name T464
Test name
Test status
Simulation time 925977808 ps
CPU time 2.02 seconds
Started May 19 12:28:57 PM PDT 24
Finished May 19 12:29:00 PM PDT 24
Peak memory 198980 kb
Host smart-3ba725c5-69fd-4bf6-a791-92ee545c0048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854228218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.854228218
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1905707844
Short name T886
Test name
Test status
Simulation time 187812353 ps
CPU time 1.01 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:30:10 PM PDT 24
Peak memory 193908 kb
Host smart-15e6353c-96e8-4eda-beaa-a96392cdd432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905707844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1905707844
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3367201577
Short name T663
Test name
Test status
Simulation time 41210356 ps
CPU time 0.54 seconds
Started May 19 12:29:59 PM PDT 24
Finished May 19 12:30:08 PM PDT 24
Peak memory 195752 kb
Host smart-222a0a63-04ce-4a07-80b0-ee1c153ee774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367201577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3367201577
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.4070381628
Short name T799
Test name
Test status
Simulation time 110505199007 ps
CPU time 18.4 seconds
Started May 19 12:30:03 PM PDT 24
Finished May 19 12:30:29 PM PDT 24
Peak memory 200296 kb
Host smart-77a2dadc-fef9-4b0a-a0ed-ba10c51a655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070381628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.4070381628
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3285958706
Short name T764
Test name
Test status
Simulation time 13001197656 ps
CPU time 22.21 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:30:17 PM PDT 24
Peak memory 200260 kb
Host smart-5737c307-f3f7-44a0-9201-4c1af647d1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285958706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3285958706
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.916376361
Short name T739
Test name
Test status
Simulation time 32174839022 ps
CPU time 34.03 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:31 PM PDT 24
Peak memory 200700 kb
Host smart-c1b8d025-bf4e-48fb-9a9d-16e835367a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916376361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.916376361
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3996595495
Short name T325
Test name
Test status
Simulation time 15353617626 ps
CPU time 26.58 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:30:20 PM PDT 24
Peak memory 198072 kb
Host smart-f51dbfaa-d61d-4149-87b9-c535bd8d1fb1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996595495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3996595495
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3532724903
Short name T524
Test name
Test status
Simulation time 189396277847 ps
CPU time 415.64 seconds
Started May 19 12:29:59 PM PDT 24
Finished May 19 12:37:03 PM PDT 24
Peak memory 200664 kb
Host smart-03d8605e-dc66-401e-8960-7fa029224960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3532724903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3532724903
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3761211694
Short name T607
Test name
Test status
Simulation time 8168548828 ps
CPU time 16.38 seconds
Started May 19 12:29:57 PM PDT 24
Finished May 19 12:30:21 PM PDT 24
Peak memory 200376 kb
Host smart-d4bb27a7-a24f-44af-b935-3b7ae7c05f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761211694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3761211694
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.925208561
Short name T328
Test name
Test status
Simulation time 6891450432 ps
CPU time 5.4 seconds
Started May 19 12:29:59 PM PDT 24
Finished May 19 12:30:12 PM PDT 24
Peak memory 195020 kb
Host smart-1332aca5-8712-427b-b775-7bce10ab9c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925208561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.925208561
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2055459310
Short name T415
Test name
Test status
Simulation time 31787012856 ps
CPU time 153.29 seconds
Started May 19 12:30:23 PM PDT 24
Finished May 19 12:32:58 PM PDT 24
Peak memory 200268 kb
Host smart-52baedf8-f130-4353-bd9a-3b3819b3f8ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055459310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2055459310
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1444196074
Short name T351
Test name
Test status
Simulation time 6815141773 ps
CPU time 8.43 seconds
Started May 19 12:30:03 PM PDT 24
Finished May 19 12:30:19 PM PDT 24
Peak memory 198480 kb
Host smart-4fd9e710-33d9-4ed4-b91a-eb5dfd89e240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1444196074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1444196074
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.150207912
Short name T1117
Test name
Test status
Simulation time 67220143231 ps
CPU time 40.72 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:37 PM PDT 24
Peak memory 200224 kb
Host smart-4332671e-2dca-400d-af87-7db4ba4332c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150207912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.150207912
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3536889237
Short name T1021
Test name
Test status
Simulation time 30883408983 ps
CPU time 8.04 seconds
Started May 19 12:30:03 PM PDT 24
Finished May 19 12:30:19 PM PDT 24
Peak memory 196272 kb
Host smart-dbe8232b-9f52-436e-accb-9bd4d6fbe849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536889237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3536889237
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3746361166
Short name T548
Test name
Test status
Simulation time 660389879 ps
CPU time 1.39 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:29:59 PM PDT 24
Peak memory 199988 kb
Host smart-ab990883-aaae-491b-a7b0-1757b25ee081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746361166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3746361166
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1942329794
Short name T110
Test name
Test status
Simulation time 149010537785 ps
CPU time 893.49 seconds
Started May 19 12:30:06 PM PDT 24
Finished May 19 12:45:06 PM PDT 24
Peak memory 200272 kb
Host smart-564b2000-fc68-4823-aadc-ce121d2039d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942329794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1942329794
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1661269040
Short name T645
Test name
Test status
Simulation time 33368278044 ps
CPU time 356.36 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:35:52 PM PDT 24
Peak memory 216136 kb
Host smart-f2e010d7-27e5-40a8-9f31-2458bb8071c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661269040 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1661269040
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3225414300
Short name T10
Test name
Test status
Simulation time 326022977 ps
CPU time 1.49 seconds
Started May 19 12:29:59 PM PDT 24
Finished May 19 12:30:08 PM PDT 24
Peak memory 198524 kb
Host smart-1ec551bb-b246-4144-9b27-88f77ab7e7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225414300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3225414300
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2515622299
Short name T337
Test name
Test status
Simulation time 5248177862 ps
CPU time 1.7 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:30:00 PM PDT 24
Peak memory 197388 kb
Host smart-602c49ec-7d3c-4611-8c1e-549ff677bbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515622299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2515622299
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2723413945
Short name T495
Test name
Test status
Simulation time 13380954 ps
CPU time 0.62 seconds
Started May 19 12:30:11 PM PDT 24
Finished May 19 12:30:15 PM PDT 24
Peak memory 196088 kb
Host smart-d9f61ada-b013-430c-9bc5-295c0dfc306a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723413945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2723413945
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2173187648
Short name T697
Test name
Test status
Simulation time 23184157198 ps
CPU time 11.26 seconds
Started May 19 12:30:05 PM PDT 24
Finished May 19 12:30:23 PM PDT 24
Peak memory 200344 kb
Host smart-6000c2a2-c9b2-4578-9b4f-f0302e77b545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173187648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2173187648
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.517353253
Short name T39
Test name
Test status
Simulation time 17136196442 ps
CPU time 16.88 seconds
Started May 19 12:30:20 PM PDT 24
Finished May 19 12:30:39 PM PDT 24
Peak memory 200236 kb
Host smart-59783428-2ba0-4466-9fe6-8b91683d3cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517353253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.517353253
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2205285515
Short name T1051
Test name
Test status
Simulation time 225056453495 ps
CPU time 112.63 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:31:46 PM PDT 24
Peak memory 200248 kb
Host smart-d7e6e0ce-a86d-4a71-bb26-d30a9c7971c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205285515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2205285515
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2084685806
Short name T466
Test name
Test status
Simulation time 12189528990 ps
CPU time 20.66 seconds
Started May 19 12:29:54 PM PDT 24
Finished May 19 12:30:22 PM PDT 24
Peak memory 200168 kb
Host smart-b482026d-1b12-4994-a8d6-e0cf932982f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084685806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2084685806
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1606312959
Short name T633
Test name
Test status
Simulation time 105498547130 ps
CPU time 223.78 seconds
Started May 19 12:30:08 PM PDT 24
Finished May 19 12:33:57 PM PDT 24
Peak memory 200368 kb
Host smart-9690abb0-6b77-41cd-bef9-1ce00c474e2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606312959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1606312959
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1866254698
Short name T617
Test name
Test status
Simulation time 3445717105 ps
CPU time 6.06 seconds
Started May 19 12:29:51 PM PDT 24
Finished May 19 12:30:05 PM PDT 24
Peak memory 196480 kb
Host smart-47c95620-4d26-43fd-92f6-0b5759a915a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866254698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1866254698
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2274395583
Short name T827
Test name
Test status
Simulation time 209595701366 ps
CPU time 148.95 seconds
Started May 19 12:30:07 PM PDT 24
Finished May 19 12:32:42 PM PDT 24
Peak memory 200496 kb
Host smart-bad5ef11-6cb9-4c08-b616-396ad7d2d94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274395583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2274395583
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.296308719
Short name T1093
Test name
Test status
Simulation time 25528865884 ps
CPU time 1478.37 seconds
Started May 19 12:30:13 PM PDT 24
Finished May 19 12:54:55 PM PDT 24
Peak memory 200332 kb
Host smart-9d6f99ef-db65-47ea-9f5f-3857c092de98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=296308719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.296308719
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.4050936440
Short name T439
Test name
Test status
Simulation time 5146930340 ps
CPU time 10.71 seconds
Started May 19 12:30:08 PM PDT 24
Finished May 19 12:30:24 PM PDT 24
Peak memory 199460 kb
Host smart-4915ef41-97d6-431b-b4d1-0fa1625d7369
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050936440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.4050936440
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.33467701
Short name T557
Test name
Test status
Simulation time 82553500840 ps
CPU time 59.64 seconds
Started May 19 12:29:51 PM PDT 24
Finished May 19 12:30:59 PM PDT 24
Peak memory 200376 kb
Host smart-ad20aa68-b0e8-411a-acbe-1ae07724d632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33467701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.33467701
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2759343115
Short name T506
Test name
Test status
Simulation time 1912654063 ps
CPU time 3.69 seconds
Started May 19 12:29:55 PM PDT 24
Finished May 19 12:30:06 PM PDT 24
Peak memory 195928 kb
Host smart-01dcec7b-1d64-472f-9e67-1151563a0f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759343115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2759343115
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2906688225
Short name T398
Test name
Test status
Simulation time 690979837 ps
CPU time 2.47 seconds
Started May 19 12:30:20 PM PDT 24
Finished May 19 12:30:24 PM PDT 24
Peak memory 199956 kb
Host smart-e6ef80aa-0b51-4316-8272-328e2196f000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906688225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2906688225
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2104058229
Short name T769
Test name
Test status
Simulation time 203055533562 ps
CPU time 33.82 seconds
Started May 19 12:30:02 PM PDT 24
Finished May 19 12:30:43 PM PDT 24
Peak memory 200344 kb
Host smart-90d87f3c-46f5-43a7-a605-1dcf7a07216f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104058229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2104058229
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2386164704
Short name T32
Test name
Test status
Simulation time 121979559790 ps
CPU time 165.77 seconds
Started May 19 12:30:15 PM PDT 24
Finished May 19 12:33:03 PM PDT 24
Peak memory 216728 kb
Host smart-90b3eb83-552c-4c60-9a0a-625685b41f6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386164704 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2386164704
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3954566614
Short name T307
Test name
Test status
Simulation time 7880829294 ps
CPU time 12.58 seconds
Started May 19 12:30:07 PM PDT 24
Finished May 19 12:30:25 PM PDT 24
Peak memory 200112 kb
Host smart-e7d9c663-3479-486c-b94f-37a9a594e7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954566614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3954566614
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3502122963
Short name T1130
Test name
Test status
Simulation time 108403789853 ps
CPU time 196.4 seconds
Started May 19 12:29:47 PM PDT 24
Finished May 19 12:33:11 PM PDT 24
Peak memory 200716 kb
Host smart-f14a5f96-1e95-434d-95f3-155d7bc341c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502122963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3502122963
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1947756134
Short name T908
Test name
Test status
Simulation time 16039404 ps
CPU time 0.55 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:30:10 PM PDT 24
Peak memory 195664 kb
Host smart-ec4d6ba3-3de2-4c81-a521-c824ce5ae0fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947756134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1947756134
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1505697744
Short name T1042
Test name
Test status
Simulation time 117378660610 ps
CPU time 195.92 seconds
Started May 19 12:29:52 PM PDT 24
Finished May 19 12:33:15 PM PDT 24
Peak memory 200256 kb
Host smart-fb767c61-2d51-455a-8862-a9f88878efe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505697744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1505697744
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.493802341
Short name T1020
Test name
Test status
Simulation time 190587765431 ps
CPU time 23.21 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:30:19 PM PDT 24
Peak memory 200332 kb
Host smart-67bc5d51-e1fb-47ca-a122-7d25f04c11b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493802341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.493802341
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3254882297
Short name T671
Test name
Test status
Simulation time 32191097180 ps
CPU time 13.16 seconds
Started May 19 12:30:21 PM PDT 24
Finished May 19 12:30:36 PM PDT 24
Peak memory 200208 kb
Host smart-b6912743-6401-4994-ada1-e0b130839271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254882297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3254882297
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2825162567
Short name T565
Test name
Test status
Simulation time 260152849543 ps
CPU time 87.23 seconds
Started May 19 12:30:07 PM PDT 24
Finished May 19 12:31:40 PM PDT 24
Peak memory 200100 kb
Host smart-65deb1f1-d39b-4dd0-a0ed-82a6cf0b452c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825162567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2825162567
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1737512419
Short name T1018
Test name
Test status
Simulation time 106162312580 ps
CPU time 563.84 seconds
Started May 19 12:30:14 PM PDT 24
Finished May 19 12:39:41 PM PDT 24
Peak memory 200320 kb
Host smart-4078b62a-27bc-4377-9c06-00b7eb301026
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737512419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1737512419
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1589900314
Short name T380
Test name
Test status
Simulation time 369109408 ps
CPU time 0.8 seconds
Started May 19 12:30:13 PM PDT 24
Finished May 19 12:30:17 PM PDT 24
Peak memory 196356 kb
Host smart-2ea6b7bc-e599-4b95-9185-524e62ecbf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589900314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1589900314
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.197611649
Short name T1110
Test name
Test status
Simulation time 10257588498 ps
CPU time 17.73 seconds
Started May 19 12:30:18 PM PDT 24
Finished May 19 12:30:38 PM PDT 24
Peak memory 200652 kb
Host smart-503521b7-c204-4230-8d22-7011b0eab6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197611649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.197611649
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1011322329
Short name T294
Test name
Test status
Simulation time 13119812467 ps
CPU time 48.82 seconds
Started May 19 12:30:26 PM PDT 24
Finished May 19 12:31:17 PM PDT 24
Peak memory 200212 kb
Host smart-9d7f1902-3f72-4ef6-b653-b994f2c37c44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1011322329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1011322329
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2197932213
Short name T371
Test name
Test status
Simulation time 5677292822 ps
CPU time 11.53 seconds
Started May 19 12:30:04 PM PDT 24
Finished May 19 12:30:23 PM PDT 24
Peak memory 199436 kb
Host smart-646fe670-5412-4892-98b6-75c7fd8d7ced
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2197932213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2197932213
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.985088727
Short name T422
Test name
Test status
Simulation time 27818679224 ps
CPU time 13.51 seconds
Started May 19 12:30:08 PM PDT 24
Finished May 19 12:30:27 PM PDT 24
Peak memory 200240 kb
Host smart-679607a6-eee4-4556-98a4-d3d113f5237c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985088727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.985088727
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3644334459
Short name T476
Test name
Test status
Simulation time 42725790307 ps
CPU time 34.91 seconds
Started May 19 12:29:56 PM PDT 24
Finished May 19 12:30:37 PM PDT 24
Peak memory 196532 kb
Host smart-0457c104-19a9-4151-a85b-8ba242ad56b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644334459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3644334459
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1657969641
Short name T803
Test name
Test status
Simulation time 268297247 ps
CPU time 1.63 seconds
Started May 19 12:30:21 PM PDT 24
Finished May 19 12:30:25 PM PDT 24
Peak memory 200096 kb
Host smart-0d29ff97-d53c-4d82-977a-1c572bbc4ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657969641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1657969641
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.956185319
Short name T919
Test name
Test status
Simulation time 318431967857 ps
CPU time 1230.36 seconds
Started May 19 12:30:15 PM PDT 24
Finished May 19 12:50:49 PM PDT 24
Peak memory 216096 kb
Host smart-5ff1787d-312c-44a3-b7cf-faad987869db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956185319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.956185319
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3085072089
Short name T481
Test name
Test status
Simulation time 42363885370 ps
CPU time 655.6 seconds
Started May 19 12:30:10 PM PDT 24
Finished May 19 12:41:10 PM PDT 24
Peak memory 215944 kb
Host smart-84a561d4-2f03-4320-bfbf-e2cc35b64ea8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085072089 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3085072089
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.716785406
Short name T895
Test name
Test status
Simulation time 8037095003 ps
CPU time 16.37 seconds
Started May 19 12:30:09 PM PDT 24
Finished May 19 12:30:30 PM PDT 24
Peak memory 200116 kb
Host smart-5130e478-b32a-4de9-84c2-660e422f0f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716785406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.716785406
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3828889805
Short name T266
Test name
Test status
Simulation time 67918745812 ps
CPU time 165.75 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:32:43 PM PDT 24
Peak memory 200308 kb
Host smart-e65b36b1-5a3e-4b47-821a-de5b6f4183eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828889805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3828889805
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2135792135
Short name T678
Test name
Test status
Simulation time 12970296 ps
CPU time 0.54 seconds
Started May 19 12:30:10 PM PDT 24
Finished May 19 12:30:15 PM PDT 24
Peak memory 195708 kb
Host smart-23fb371a-3b31-4daa-b958-dfdaa9afe255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135792135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2135792135
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1971027823
Short name T128
Test name
Test status
Simulation time 85509603982 ps
CPU time 33.34 seconds
Started May 19 12:30:18 PM PDT 24
Finished May 19 12:30:53 PM PDT 24
Peak memory 200220 kb
Host smart-fbe601e2-e060-4457-9615-9e01ed1467f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971027823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1971027823
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.448458223
Short name T634
Test name
Test status
Simulation time 82284682940 ps
CPU time 79.59 seconds
Started May 19 12:30:12 PM PDT 24
Finished May 19 12:31:35 PM PDT 24
Peak memory 200240 kb
Host smart-e383e67e-aeb1-4d8a-99e2-71e58234cd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448458223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.448458223
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.42859330
Short name T162
Test name
Test status
Simulation time 16059043081 ps
CPU time 27.83 seconds
Started May 19 12:30:21 PM PDT 24
Finished May 19 12:30:51 PM PDT 24
Peak memory 200316 kb
Host smart-655f2348-5323-43d9-8e06-a1fb27c5d47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42859330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.42859330
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3179010802
Short name T437
Test name
Test status
Simulation time 47196815893 ps
CPU time 89.97 seconds
Started May 19 12:29:48 PM PDT 24
Finished May 19 12:31:26 PM PDT 24
Peak memory 200260 kb
Host smart-f0f50298-0bb1-48b4-b34a-de56e43f07f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179010802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3179010802
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2310700382
Short name T904
Test name
Test status
Simulation time 135015391741 ps
CPU time 668.75 seconds
Started May 19 12:30:19 PM PDT 24
Finished May 19 12:41:30 PM PDT 24
Peak memory 200396 kb
Host smart-b07b760b-e748-4f3f-8887-8fa56c5128f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310700382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2310700382
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2385115804
Short name T639
Test name
Test status
Simulation time 9747914950 ps
CPU time 9.08 seconds
Started May 19 12:30:04 PM PDT 24
Finished May 19 12:30:20 PM PDT 24
Peak memory 199572 kb
Host smart-47518bac-b21d-40a1-a456-5b939370054c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385115804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2385115804
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1585718416
Short name T909
Test name
Test status
Simulation time 164173680309 ps
CPU time 65.33 seconds
Started May 19 12:30:08 PM PDT 24
Finished May 19 12:31:18 PM PDT 24
Peak memory 199992 kb
Host smart-fed6e655-93b3-4a4e-918a-b2a7a7ddcdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585718416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1585718416
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3469460089
Short name T675
Test name
Test status
Simulation time 12335573946 ps
CPU time 741.25 seconds
Started May 19 12:30:09 PM PDT 24
Finished May 19 12:42:35 PM PDT 24
Peak memory 200216 kb
Host smart-bd7a0818-dd8a-4f99-a760-33c1fb2ddc5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3469460089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3469460089
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2003974701
Short name T1035
Test name
Test status
Simulation time 5940731773 ps
CPU time 56 seconds
Started May 19 12:29:52 PM PDT 24
Finished May 19 12:31:01 PM PDT 24
Peak memory 198532 kb
Host smart-d5b0d786-155e-48c6-9084-82fd5aabc848
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2003974701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2003974701
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2746681840
Short name T762
Test name
Test status
Simulation time 184865493817 ps
CPU time 75.65 seconds
Started May 19 12:30:21 PM PDT 24
Finished May 19 12:31:38 PM PDT 24
Peak memory 200172 kb
Host smart-e20549bd-575c-4903-821f-cd16788fc5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746681840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2746681840
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2737556007
Short name T673
Test name
Test status
Simulation time 755628175 ps
CPU time 1.77 seconds
Started May 19 12:29:49 PM PDT 24
Finished May 19 12:29:59 PM PDT 24
Peak memory 195948 kb
Host smart-c90fd923-4b35-43df-b443-acce81224aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737556007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2737556007
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3315317358
Short name T365
Test name
Test status
Simulation time 6040670074 ps
CPU time 10.27 seconds
Started May 19 12:29:51 PM PDT 24
Finished May 19 12:30:09 PM PDT 24
Peak memory 200332 kb
Host smart-3e587ff5-0f7e-4cd8-82da-3b40e3f7677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315317358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3315317358
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.1758874705
Short name T1061
Test name
Test status
Simulation time 324380242667 ps
CPU time 1649.41 seconds
Started May 19 12:30:02 PM PDT 24
Finished May 19 12:57:39 PM PDT 24
Peak memory 208804 kb
Host smart-9a27413b-3bd4-4872-aeda-4db11d012e83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758874705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1758874705
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1787543114
Short name T1111
Test name
Test status
Simulation time 16129644637 ps
CPU time 185.46 seconds
Started May 19 12:30:03 PM PDT 24
Finished May 19 12:33:16 PM PDT 24
Peak memory 216284 kb
Host smart-fbe0ce16-19a3-4828-8a0e-4d177552bda5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787543114 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1787543114
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.134733682
Short name T98
Test name
Test status
Simulation time 1784313055 ps
CPU time 1.77 seconds
Started May 19 12:30:03 PM PDT 24
Finished May 19 12:30:13 PM PDT 24
Peak memory 199584 kb
Host smart-db6bf7fe-a810-4e93-9812-a6ba2678e8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134733682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.134733682
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.68793249
Short name T318
Test name
Test status
Simulation time 99570876922 ps
CPU time 149.92 seconds
Started May 19 12:30:06 PM PDT 24
Finished May 19 12:32:42 PM PDT 24
Peak memory 200316 kb
Host smart-52833635-1829-4907-bd10-9ae5b3b01b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68793249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.68793249
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3577150246
Short name T453
Test name
Test status
Simulation time 16234475 ps
CPU time 0.6 seconds
Started May 19 12:30:27 PM PDT 24
Finished May 19 12:30:29 PM PDT 24
Peak memory 195520 kb
Host smart-3a1070f4-e89f-466c-9ed8-71a24f18199d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577150246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3577150246
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2845261391
Short name T278
Test name
Test status
Simulation time 124375781543 ps
CPU time 50.18 seconds
Started May 19 12:30:21 PM PDT 24
Finished May 19 12:31:13 PM PDT 24
Peak memory 200336 kb
Host smart-066733d9-4dc1-47ba-b284-1316bb7098c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845261391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2845261391
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.339850680
Short name T861
Test name
Test status
Simulation time 123461233237 ps
CPU time 163.68 seconds
Started May 19 12:30:17 PM PDT 24
Finished May 19 12:33:03 PM PDT 24
Peak memory 200080 kb
Host smart-0bb84709-0eb8-4666-aba4-f5190d7cd968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339850680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.339850680
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3343567029
Short name T1131
Test name
Test status
Simulation time 239314128507 ps
CPU time 455.01 seconds
Started May 19 12:30:15 PM PDT 24
Finished May 19 12:37:52 PM PDT 24
Peak memory 200324 kb
Host smart-22438a7b-8d4f-4819-a8d7-c0dedbcc1282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343567029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3343567029
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2568605696
Short name T357
Test name
Test status
Simulation time 8869855320 ps
CPU time 3.05 seconds
Started May 19 12:30:14 PM PDT 24
Finished May 19 12:30:20 PM PDT 24
Peak memory 197312 kb
Host smart-29ea924f-9285-434c-8175-4dc4f6460aee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568605696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2568605696
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2528407354
Short name T49
Test name
Test status
Simulation time 229733107170 ps
CPU time 345.45 seconds
Started May 19 12:30:03 PM PDT 24
Finished May 19 12:35:56 PM PDT 24
Peak memory 200160 kb
Host smart-bd5170fc-2a8c-40e1-a384-413f8f4717c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528407354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2528407354
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1035537835
Short name T902
Test name
Test status
Simulation time 9658988170 ps
CPU time 2.46 seconds
Started May 19 12:30:04 PM PDT 24
Finished May 19 12:30:14 PM PDT 24
Peak memory 199976 kb
Host smart-4101576f-545f-4386-bcd5-c615c78c4a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035537835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1035537835
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2274451414
Short name T314
Test name
Test status
Simulation time 115681302032 ps
CPU time 139.52 seconds
Started May 19 12:29:54 PM PDT 24
Finished May 19 12:32:21 PM PDT 24
Peak memory 198648 kb
Host smart-8181b3fb-e6ad-4d74-b6bc-ba1e1c9fa234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274451414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2274451414
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1155056978
Short name T473
Test name
Test status
Simulation time 4355175138 ps
CPU time 105.85 seconds
Started May 19 12:30:15 PM PDT 24
Finished May 19 12:32:04 PM PDT 24
Peak memory 200268 kb
Host smart-0e6e84bf-7d7a-4772-9a80-b2b0a4e417f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155056978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1155056978
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.591084832
Short name T620
Test name
Test status
Simulation time 5958025069 ps
CPU time 27.17 seconds
Started May 19 12:30:18 PM PDT 24
Finished May 19 12:30:48 PM PDT 24
Peak memory 199728 kb
Host smart-9221e9ca-f773-46db-a467-fa8839d2395a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=591084832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.591084832
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.58267299
Short name T920
Test name
Test status
Simulation time 169840630921 ps
CPU time 263.21 seconds
Started May 19 12:30:15 PM PDT 24
Finished May 19 12:34:41 PM PDT 24
Peak memory 200648 kb
Host smart-04245156-7319-497f-a4aa-490e12961a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58267299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.58267299
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1277990585
Short name T472
Test name
Test status
Simulation time 3235775657 ps
CPU time 5.65 seconds
Started May 19 12:30:16 PM PDT 24
Finished May 19 12:30:24 PM PDT 24
Peak memory 196360 kb
Host smart-317ec24a-3dba-4a65-99db-66ba72163306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277990585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1277990585
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3970587750
Short name T474
Test name
Test status
Simulation time 496605762 ps
CPU time 1.4 seconds
Started May 19 12:30:26 PM PDT 24
Finished May 19 12:30:29 PM PDT 24
Peak memory 199968 kb
Host smart-b1d79fef-4c06-41bd-82b3-b5159fa7da5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970587750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3970587750
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2996811504
Short name T1007
Test name
Test status
Simulation time 263419448149 ps
CPU time 176.43 seconds
Started May 19 12:30:21 PM PDT 24
Finished May 19 12:33:20 PM PDT 24
Peak memory 200312 kb
Host smart-1f16676e-330d-4f13-b5d1-027f4ee6c9e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996811504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2996811504
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2048974395
Short name T1008
Test name
Test status
Simulation time 211991196043 ps
CPU time 725.9 seconds
Started May 19 12:30:24 PM PDT 24
Finished May 19 12:42:31 PM PDT 24
Peak memory 225248 kb
Host smart-14b61482-3e2f-42cd-b7aa-9ac5cdc52eab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048974395 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2048974395
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.74135310
Short name T926
Test name
Test status
Simulation time 11735321873 ps
CPU time 12.94 seconds
Started May 19 12:30:08 PM PDT 24
Finished May 19 12:30:27 PM PDT 24
Peak memory 199708 kb
Host smart-81f34e90-82b8-429c-8543-fd63301763d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74135310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.74135310
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1280995116
Short name T297
Test name
Test status
Simulation time 17234199277 ps
CPU time 29.03 seconds
Started May 19 12:30:03 PM PDT 24
Finished May 19 12:30:40 PM PDT 24
Peak memory 200344 kb
Host smart-8e729748-b66b-445d-b2e0-e4f5c6893cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280995116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1280995116
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.734524550
Short name T710
Test name
Test status
Simulation time 95957463 ps
CPU time 0.54 seconds
Started May 19 12:30:10 PM PDT 24
Finished May 19 12:30:15 PM PDT 24
Peak memory 195664 kb
Host smart-45e2c35c-9c9e-41ea-bb80-dc88fb06ace7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734524550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.734524550
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3670593505
Short name T377
Test name
Test status
Simulation time 130216839754 ps
CPU time 58.58 seconds
Started May 19 12:30:24 PM PDT 24
Finished May 19 12:31:24 PM PDT 24
Peak memory 200272 kb
Host smart-f8ca00e5-a152-4343-a016-0e5021e33778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670593505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3670593505
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2761406649
Short name T317
Test name
Test status
Simulation time 77969875255 ps
CPU time 29.21 seconds
Started May 19 12:30:10 PM PDT 24
Finished May 19 12:30:44 PM PDT 24
Peak memory 199776 kb
Host smart-c9f3df83-c2de-4d6e-9b3c-573b42cdb8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761406649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2761406649
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1781682441
Short name T433
Test name
Test status
Simulation time 18312293189 ps
CPU time 15.21 seconds
Started May 19 12:30:25 PM PDT 24
Finished May 19 12:30:42 PM PDT 24
Peak memory 200064 kb
Host smart-b1a7a1c5-dee8-4298-9535-9f6799f87621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781682441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1781682441
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3887871782
Short name T492
Test name
Test status
Simulation time 74519256990 ps
CPU time 6.57 seconds
Started May 19 12:30:19 PM PDT 24
Finished May 19 12:30:28 PM PDT 24
Peak memory 196440 kb
Host smart-b10c27eb-4f0f-43c7-a157-a13b48258868
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887871782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3887871782
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2206515064
Short name T790
Test name
Test status
Simulation time 33690671299 ps
CPU time 138.84 seconds
Started May 19 12:30:09 PM PDT 24
Finished May 19 12:32:33 PM PDT 24
Peak memory 200340 kb
Host smart-83937a93-c4d9-43af-b478-2d30ec480a50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206515064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2206515064
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3292113099
Short name T571
Test name
Test status
Simulation time 7524045617 ps
CPU time 5.19 seconds
Started May 19 12:30:13 PM PDT 24
Finished May 19 12:30:22 PM PDT 24
Peak memory 199208 kb
Host smart-bf165cac-4898-4ae7-aac9-b668966fc3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292113099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3292113099
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1266127497
Short name T647
Test name
Test status
Simulation time 220364331625 ps
CPU time 129.58 seconds
Started May 19 12:30:18 PM PDT 24
Finished May 19 12:32:30 PM PDT 24
Peak memory 199348 kb
Host smart-2b5a3dab-4b59-44eb-af17-9bb96f69572f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266127497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1266127497
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.173836426
Short name T692
Test name
Test status
Simulation time 14532149154 ps
CPU time 381.46 seconds
Started May 19 12:30:26 PM PDT 24
Finished May 19 12:36:49 PM PDT 24
Peak memory 200276 kb
Host smart-6c6f46e8-c52c-490e-b4fc-c938de30d538
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=173836426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.173836426
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3964623376
Short name T321
Test name
Test status
Simulation time 5157349390 ps
CPU time 22.97 seconds
Started May 19 12:30:17 PM PDT 24
Finished May 19 12:30:42 PM PDT 24
Peak memory 198440 kb
Host smart-4a353a37-40af-486f-b3eb-6200cc3c60ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3964623376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3964623376
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3076391855
Short name T1123
Test name
Test status
Simulation time 49965386419 ps
CPU time 85.58 seconds
Started May 19 12:30:25 PM PDT 24
Finished May 19 12:31:52 PM PDT 24
Peak memory 200304 kb
Host smart-6588b0bb-e6fd-4441-880d-e19f99f82464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076391855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3076391855
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2326196253
Short name T969
Test name
Test status
Simulation time 34227387888 ps
CPU time 55.71 seconds
Started May 19 12:30:03 PM PDT 24
Finished May 19 12:31:07 PM PDT 24
Peak memory 196044 kb
Host smart-8efc4018-7a93-4c81-9d53-557770d03db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326196253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2326196253
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.511725286
Short name T1023
Test name
Test status
Simulation time 87412636 ps
CPU time 0.81 seconds
Started May 19 12:30:02 PM PDT 24
Finished May 19 12:30:10 PM PDT 24
Peak memory 197132 kb
Host smart-7200f847-cdcf-4b8c-bbf1-9ea401fc6f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511725286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.511725286
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3734968899
Short name T816
Test name
Test status
Simulation time 103945819938 ps
CPU time 51.33 seconds
Started May 19 12:30:22 PM PDT 24
Finished May 19 12:31:15 PM PDT 24
Peak memory 200388 kb
Host smart-b1d35a46-c3c1-443f-a755-057f4ebdab81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734968899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3734968899
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2840141478
Short name T896
Test name
Test status
Simulation time 148858321065 ps
CPU time 707.2 seconds
Started May 19 12:30:18 PM PDT 24
Finished May 19 12:42:08 PM PDT 24
Peak memory 217016 kb
Host smart-2afcbad1-b299-47b8-84e1-dd2fa0bddbef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840141478 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2840141478
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3221345399
Short name T267
Test name
Test status
Simulation time 865521034 ps
CPU time 3.36 seconds
Started May 19 12:30:15 PM PDT 24
Finished May 19 12:30:21 PM PDT 24
Peak memory 198896 kb
Host smart-643a6cad-6808-42d4-b89e-66f3270b8c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221345399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3221345399
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.930213235
Short name T1055
Test name
Test status
Simulation time 4303998598 ps
CPU time 7.14 seconds
Started May 19 12:30:11 PM PDT 24
Finished May 19 12:30:22 PM PDT 24
Peak memory 197952 kb
Host smart-ddb84034-40ee-4cc2-b9f2-bee3c8368a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930213235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.930213235
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2260254715
Short name T724
Test name
Test status
Simulation time 34779194 ps
CPU time 0.61 seconds
Started May 19 12:30:22 PM PDT 24
Finished May 19 12:30:24 PM PDT 24
Peak memory 195616 kb
Host smart-2570c644-1156-46cc-a977-6d7895cb1589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260254715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2260254715
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3590132887
Short name T756
Test name
Test status
Simulation time 24263751096 ps
CPU time 46.14 seconds
Started May 19 12:30:20 PM PDT 24
Finished May 19 12:31:08 PM PDT 24
Peak memory 200264 kb
Host smart-7779668c-f8df-434c-9f40-5e19e2971fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590132887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3590132887
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1639333188
Short name T691
Test name
Test status
Simulation time 115233357449 ps
CPU time 203.3 seconds
Started May 19 12:30:20 PM PDT 24
Finished May 19 12:33:46 PM PDT 24
Peak memory 200164 kb
Host smart-67dbac78-f7f5-4ff6-a0f8-85ba2810af34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639333188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1639333188
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.4101936541
Short name T950
Test name
Test status
Simulation time 36542637817 ps
CPU time 21.19 seconds
Started May 19 12:30:23 PM PDT 24
Finished May 19 12:30:46 PM PDT 24
Peak memory 200228 kb
Host smart-5775505c-a295-451c-8776-9786bc1bbdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101936541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.4101936541
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1093224962
Short name T997
Test name
Test status
Simulation time 14345941319 ps
CPU time 6.2 seconds
Started May 19 12:30:14 PM PDT 24
Finished May 19 12:30:23 PM PDT 24
Peak memory 199932 kb
Host smart-449cd1e5-91ce-4d88-a9e8-1fea640796d3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093224962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1093224962
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3364585130
Short name T602
Test name
Test status
Simulation time 55438014723 ps
CPU time 275.17 seconds
Started May 19 12:30:16 PM PDT 24
Finished May 19 12:34:54 PM PDT 24
Peak memory 200320 kb
Host smart-891dca19-be02-4e4e-bcad-89fa1ba8a3a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364585130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3364585130
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.773467178
Short name T399
Test name
Test status
Simulation time 3139502506 ps
CPU time 3.61 seconds
Started May 19 12:30:17 PM PDT 24
Finished May 19 12:30:23 PM PDT 24
Peak memory 196104 kb
Host smart-7331e6a2-51d2-49d4-a3fe-81c5636b1420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773467178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.773467178
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1427446959
Short name T892
Test name
Test status
Simulation time 43566334711 ps
CPU time 74.34 seconds
Started May 19 12:30:19 PM PDT 24
Finished May 19 12:31:35 PM PDT 24
Peak memory 200576 kb
Host smart-777ee25a-4487-4cc7-8232-51e23b8b4907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427446959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1427446959
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.2353451778
Short name T669
Test name
Test status
Simulation time 27362041831 ps
CPU time 1493.45 seconds
Started May 19 12:30:20 PM PDT 24
Finished May 19 12:55:15 PM PDT 24
Peak memory 200332 kb
Host smart-ac8a9647-86f8-4c1c-a16c-5c2b494300e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353451778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2353451778
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1146189519
Short name T424
Test name
Test status
Simulation time 4674518488 ps
CPU time 22.58 seconds
Started May 19 12:30:09 PM PDT 24
Finished May 19 12:30:36 PM PDT 24
Peak memory 198440 kb
Host smart-90793f52-2bce-4d82-9e6c-3ab0fbcb4fcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1146189519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1146189519
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.124947110
Short name T143
Test name
Test status
Simulation time 33378807869 ps
CPU time 55.87 seconds
Started May 19 12:30:14 PM PDT 24
Finished May 19 12:31:13 PM PDT 24
Peak memory 200296 kb
Host smart-e4a82725-ae79-47f9-8e09-33da98cd2e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124947110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.124947110
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.558405070
Short name T747
Test name
Test status
Simulation time 5606780504 ps
CPU time 9.3 seconds
Started May 19 12:30:24 PM PDT 24
Finished May 19 12:30:35 PM PDT 24
Peak memory 196316 kb
Host smart-c167a8ac-1627-46c2-b16d-da457f39bc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558405070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.558405070
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3374347529
Short name T1070
Test name
Test status
Simulation time 675405661 ps
CPU time 2.01 seconds
Started May 19 12:30:16 PM PDT 24
Finished May 19 12:30:21 PM PDT 24
Peak memory 199848 kb
Host smart-aed6f65f-0d77-4590-8415-cc94f29721f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374347529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3374347529
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.91221793
Short name T178
Test name
Test status
Simulation time 228408888876 ps
CPU time 286.21 seconds
Started May 19 12:30:23 PM PDT 24
Finished May 19 12:35:11 PM PDT 24
Peak memory 200224 kb
Host smart-706b3755-a494-4ae3-a084-6d5f67176419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91221793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.91221793
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1055118074
Short name T463
Test name
Test status
Simulation time 60379872331 ps
CPU time 295.8 seconds
Started May 19 12:30:19 PM PDT 24
Finished May 19 12:35:17 PM PDT 24
Peak memory 215912 kb
Host smart-85fab13d-3982-4b59-a54d-fe47a27c929f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055118074 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1055118074
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.56291428
Short name T676
Test name
Test status
Simulation time 1689831862 ps
CPU time 2.78 seconds
Started May 19 12:30:30 PM PDT 24
Finished May 19 12:30:36 PM PDT 24
Peak memory 198864 kb
Host smart-1ad7f96d-c1ee-41d7-be7a-d357b85743ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56291428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.56291428
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2749871712
Short name T929
Test name
Test status
Simulation time 119372640926 ps
CPU time 47.63 seconds
Started May 19 12:30:16 PM PDT 24
Finished May 19 12:31:06 PM PDT 24
Peak memory 200236 kb
Host smart-b30b5701-fd68-40db-969e-28743cde5d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749871712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2749871712
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1529202041
Short name T1064
Test name
Test status
Simulation time 22357810 ps
CPU time 0.55 seconds
Started May 19 12:30:31 PM PDT 24
Finished May 19 12:30:34 PM PDT 24
Peak memory 195668 kb
Host smart-4153ca9c-794b-40ac-a951-30f045ab1266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529202041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1529202041
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2060280838
Short name T1025
Test name
Test status
Simulation time 55230538432 ps
CPU time 52.19 seconds
Started May 19 12:30:18 PM PDT 24
Finished May 19 12:31:13 PM PDT 24
Peak memory 200352 kb
Host smart-8a592602-a911-4b8e-a767-646743797613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060280838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2060280838
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.966755946
Short name T129
Test name
Test status
Simulation time 46145511135 ps
CPU time 81.53 seconds
Started May 19 12:30:22 PM PDT 24
Finished May 19 12:31:46 PM PDT 24
Peak memory 200324 kb
Host smart-07a5b00b-bd97-472c-b15e-eb8ceb6a084e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966755946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.966755946
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3405540841
Short name T298
Test name
Test status
Simulation time 110536946088 ps
CPU time 45.52 seconds
Started May 19 12:30:17 PM PDT 24
Finished May 19 12:31:05 PM PDT 24
Peak memory 199832 kb
Host smart-532fcda1-69ab-4e69-89fd-3e8b7b0fd3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405540841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3405540841
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2510642099
Short name T1114
Test name
Test status
Simulation time 41775213891 ps
CPU time 40.02 seconds
Started May 19 12:30:18 PM PDT 24
Finished May 19 12:31:00 PM PDT 24
Peak memory 200136 kb
Host smart-47a7bff9-1524-461c-b0e3-b243f721fdc7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510642099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2510642099
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2391660734
Short name T794
Test name
Test status
Simulation time 47292087003 ps
CPU time 325.77 seconds
Started May 19 12:30:22 PM PDT 24
Finished May 19 12:35:50 PM PDT 24
Peak memory 200368 kb
Host smart-33abad8f-aa8e-4d40-a526-7b8b9474df84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391660734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2391660734
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1375649391
Short name T823
Test name
Test status
Simulation time 1975102418 ps
CPU time 1.06 seconds
Started May 19 12:30:18 PM PDT 24
Finished May 19 12:30:21 PM PDT 24
Peak memory 197640 kb
Host smart-6530858a-565a-49e3-a919-596d45893e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375649391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1375649391
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.24836129
Short name T1134
Test name
Test status
Simulation time 463420640117 ps
CPU time 82.93 seconds
Started May 19 12:30:14 PM PDT 24
Finished May 19 12:31:40 PM PDT 24
Peak memory 199332 kb
Host smart-5608d02c-614b-41e1-9ed2-a54587dafc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24836129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.24836129
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2183111370
Short name T540
Test name
Test status
Simulation time 21076854960 ps
CPU time 1299.23 seconds
Started May 19 12:30:20 PM PDT 24
Finished May 19 12:52:01 PM PDT 24
Peak memory 200236 kb
Host smart-04ac4af6-c6b1-4a58-8080-fe60b028ed44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2183111370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2183111370
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3169708765
Short name T589
Test name
Test status
Simulation time 5054794258 ps
CPU time 11.85 seconds
Started May 19 12:30:17 PM PDT 24
Finished May 19 12:30:31 PM PDT 24
Peak memory 199756 kb
Host smart-7dd44a17-eed5-475b-902e-6c3af7137809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169708765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3169708765
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1088397189
Short name T658
Test name
Test status
Simulation time 32162480511 ps
CPU time 16.26 seconds
Started May 19 12:30:22 PM PDT 24
Finished May 19 12:30:40 PM PDT 24
Peak memory 200256 kb
Host smart-d0799d26-be61-400c-95ef-3ef3d2e6c4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088397189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1088397189
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3995781561
Short name T1019
Test name
Test status
Simulation time 36886685082 ps
CPU time 54.3 seconds
Started May 19 12:30:19 PM PDT 24
Finished May 19 12:31:15 PM PDT 24
Peak memory 196024 kb
Host smart-5b8b5806-c0e2-4140-bcd3-9149b923b04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995781561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3995781561
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1266849929
Short name T470
Test name
Test status
Simulation time 270560144 ps
CPU time 1.66 seconds
Started May 19 12:30:26 PM PDT 24
Finished May 19 12:30:29 PM PDT 24
Peak memory 199044 kb
Host smart-e6471639-711d-4dd0-b45c-43b2dae4154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266849929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1266849929
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3539632129
Short name T838
Test name
Test status
Simulation time 251221907345 ps
CPU time 398.53 seconds
Started May 19 12:30:26 PM PDT 24
Finished May 19 12:37:07 PM PDT 24
Peak memory 200288 kb
Host smart-989e61fc-e913-4dea-aac1-d9cf5d21b82d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539632129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3539632129
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.4109014339
Short name T341
Test name
Test status
Simulation time 107294997233 ps
CPU time 708.75 seconds
Started May 19 12:30:24 PM PDT 24
Finished May 19 12:42:15 PM PDT 24
Peak memory 225296 kb
Host smart-06ddc0b5-340b-44ce-a5d1-084201a989af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109014339 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.4109014339
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.990368085
Short name T388
Test name
Test status
Simulation time 559333873 ps
CPU time 2.53 seconds
Started May 19 12:30:15 PM PDT 24
Finished May 19 12:30:21 PM PDT 24
Peak memory 199472 kb
Host smart-97001519-49e3-409b-8ee3-febdc0a686bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990368085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.990368085
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3549009822
Short name T1077
Test name
Test status
Simulation time 102403374701 ps
CPU time 68.15 seconds
Started May 19 12:30:14 PM PDT 24
Finished May 19 12:31:25 PM PDT 24
Peak memory 200264 kb
Host smart-ac9867a4-60b2-46b3-a810-7759d0d0e791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549009822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3549009822
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.616205513
Short name T873
Test name
Test status
Simulation time 17633983 ps
CPU time 0.55 seconds
Started May 19 12:30:23 PM PDT 24
Finished May 19 12:30:25 PM PDT 24
Peak memory 195112 kb
Host smart-93eab4fa-9397-4123-a249-361dffb822f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616205513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.616205513
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3506897796
Short name T718
Test name
Test status
Simulation time 132928928950 ps
CPU time 71.87 seconds
Started May 19 12:30:21 PM PDT 24
Finished May 19 12:31:35 PM PDT 24
Peak memory 200276 kb
Host smart-35c0aede-56ea-4d49-b57b-6aa02667461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506897796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3506897796
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.362629078
Short name T284
Test name
Test status
Simulation time 176919919850 ps
CPU time 329.97 seconds
Started May 19 12:30:21 PM PDT 24
Finished May 19 12:35:52 PM PDT 24
Peak memory 200284 kb
Host smart-907007a6-949c-4058-b1e3-06476d0e61ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362629078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.362629078
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.4045992226
Short name T800
Test name
Test status
Simulation time 53773057107 ps
CPU time 38.66 seconds
Started May 19 12:30:22 PM PDT 24
Finished May 19 12:31:02 PM PDT 24
Peak memory 200360 kb
Host smart-529524f8-3d2a-4b7f-821b-ab029e07c987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045992226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.4045992226
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1975322687
Short name T16
Test name
Test status
Simulation time 24195932812 ps
CPU time 46.74 seconds
Started May 19 12:30:23 PM PDT 24
Finished May 19 12:31:11 PM PDT 24
Peak memory 199788 kb
Host smart-3cfed770-4619-4044-9130-18881b26825f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975322687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1975322687
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.118430390
Short name T350
Test name
Test status
Simulation time 237017388567 ps
CPU time 243.01 seconds
Started May 19 12:30:18 PM PDT 24
Finished May 19 12:34:24 PM PDT 24
Peak memory 200264 kb
Host smart-1adba369-87e7-462a-b01e-cc851a7f2d20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=118430390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.118430390
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.823650583
Short name T603
Test name
Test status
Simulation time 750553411 ps
CPU time 1.46 seconds
Started May 19 12:30:26 PM PDT 24
Finished May 19 12:30:29 PM PDT 24
Peak memory 198128 kb
Host smart-38664742-e607-44cb-8002-bad47db5acf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823650583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.823650583
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3108568716
Short name T287
Test name
Test status
Simulation time 134116209618 ps
CPU time 59.75 seconds
Started May 19 12:30:29 PM PDT 24
Finished May 19 12:31:31 PM PDT 24
Peak memory 200548 kb
Host smart-c8a16b90-5bf8-4c15-a3c1-6c4f37f0de15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108568716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3108568716
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2757583899
Short name T363
Test name
Test status
Simulation time 5559777009 ps
CPU time 103.98 seconds
Started May 19 12:30:27 PM PDT 24
Finished May 19 12:32:13 PM PDT 24
Peak memory 200356 kb
Host smart-4cf46854-7ca3-4efe-9abe-7b5e07f0d0e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2757583899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2757583899
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3767416343
Short name T409
Test name
Test status
Simulation time 6266787588 ps
CPU time 14.19 seconds
Started May 19 12:30:27 PM PDT 24
Finished May 19 12:30:43 PM PDT 24
Peak memory 199464 kb
Host smart-f4f46d85-e321-46a9-be45-6812ad3862be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3767416343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3767416343
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.890501833
Short name T425
Test name
Test status
Simulation time 89712499534 ps
CPU time 38.82 seconds
Started May 19 12:30:25 PM PDT 24
Finished May 19 12:31:06 PM PDT 24
Peak memory 200172 kb
Host smart-78600805-1192-4b78-a885-f9d5f4e536a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890501833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.890501833
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3887372655
Short name T367
Test name
Test status
Simulation time 1912499719 ps
CPU time 1.7 seconds
Started May 19 12:30:26 PM PDT 24
Finished May 19 12:30:30 PM PDT 24
Peak memory 195672 kb
Host smart-3e729d07-f11e-495a-859e-8f809cbf6a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887372655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3887372655
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3242429080
Short name T392
Test name
Test status
Simulation time 631665117 ps
CPU time 2.09 seconds
Started May 19 12:30:25 PM PDT 24
Finished May 19 12:30:29 PM PDT 24
Peak memory 200192 kb
Host smart-51579344-5783-4642-9006-a85604f3e01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242429080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3242429080
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.768800292
Short name T461
Test name
Test status
Simulation time 59422559373 ps
CPU time 1289.78 seconds
Started May 19 12:30:29 PM PDT 24
Finished May 19 12:52:02 PM PDT 24
Peak memory 200324 kb
Host smart-ef366757-f35f-440d-9b10-328c4a27adf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768800292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.768800292
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2095153799
Short name T668
Test name
Test status
Simulation time 56086069591 ps
CPU time 328.04 seconds
Started May 19 12:30:27 PM PDT 24
Finished May 19 12:35:57 PM PDT 24
Peak memory 216756 kb
Host smart-03330377-dad1-4b4a-a7b5-bd9b7b2dd37e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095153799 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2095153799
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.55169905
Short name T741
Test name
Test status
Simulation time 6378277413 ps
CPU time 12.26 seconds
Started May 19 12:30:27 PM PDT 24
Finished May 19 12:30:41 PM PDT 24
Peak memory 200096 kb
Host smart-b2212d08-c442-4071-8ee7-ebeb8591849c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55169905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.55169905
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3615521163
Short name T450
Test name
Test status
Simulation time 34255155611 ps
CPU time 57.22 seconds
Started May 19 12:30:24 PM PDT 24
Finished May 19 12:31:23 PM PDT 24
Peak memory 200248 kb
Host smart-b5c0cf2a-f575-4119-839a-34a9cb676e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615521163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3615521163
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1522516293
Short name T385
Test name
Test status
Simulation time 11264753 ps
CPU time 0.53 seconds
Started May 19 12:30:29 PM PDT 24
Finished May 19 12:30:32 PM PDT 24
Peak memory 194692 kb
Host smart-8c18a10f-c76b-4a85-ba67-89187d18acc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522516293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1522516293
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.4049431088
Short name T1169
Test name
Test status
Simulation time 161507170126 ps
CPU time 40.7 seconds
Started May 19 12:30:23 PM PDT 24
Finished May 19 12:31:05 PM PDT 24
Peak memory 200368 kb
Host smart-d6f51981-56c8-4d19-833e-176436610616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049431088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.4049431088
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3617355363
Short name T831
Test name
Test status
Simulation time 68799384381 ps
CPU time 7.44 seconds
Started May 19 12:30:24 PM PDT 24
Finished May 19 12:30:33 PM PDT 24
Peak memory 198132 kb
Host smart-680fc42b-0437-49cc-9ef8-37f6867dc123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617355363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3617355363
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.52918855
Short name T811
Test name
Test status
Simulation time 32065713182 ps
CPU time 46.64 seconds
Started May 19 12:30:28 PM PDT 24
Finished May 19 12:31:18 PM PDT 24
Peak memory 200352 kb
Host smart-fc47456d-199c-4826-9913-c0cae58cbb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52918855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.52918855
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.580507538
Short name T471
Test name
Test status
Simulation time 9302510182 ps
CPU time 7.28 seconds
Started May 19 12:30:29 PM PDT 24
Finished May 19 12:30:40 PM PDT 24
Peak memory 200240 kb
Host smart-c9651b4d-94f4-4f74-89ee-68ece85353aa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580507538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.580507538
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3525261501
Short name T513
Test name
Test status
Simulation time 139097595920 ps
CPU time 304.03 seconds
Started May 19 12:30:31 PM PDT 24
Finished May 19 12:35:38 PM PDT 24
Peak memory 200272 kb
Host smart-3ddce490-d824-4a5e-a5fb-6625a32b8b7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525261501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3525261501
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1119223814
Short name T1069
Test name
Test status
Simulation time 7026785173 ps
CPU time 13.54 seconds
Started May 19 12:30:29 PM PDT 24
Finished May 19 12:30:45 PM PDT 24
Peak memory 200148 kb
Host smart-7d546027-e94c-4343-bad3-0ce23bddd91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119223814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1119223814
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.4271342791
Short name T630
Test name
Test status
Simulation time 288063514870 ps
CPU time 130.74 seconds
Started May 19 12:30:32 PM PDT 24
Finished May 19 12:32:46 PM PDT 24
Peak memory 199392 kb
Host smart-c898aa77-faa1-4489-ac29-bdb6d46595ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271342791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.4271342791
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3506806802
Short name T508
Test name
Test status
Simulation time 15618772076 ps
CPU time 506.76 seconds
Started May 19 12:30:29 PM PDT 24
Finished May 19 12:39:00 PM PDT 24
Peak memory 200708 kb
Host smart-0c70ea07-e47d-4d40-973c-c6c756d3f67c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3506806802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3506806802
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.462897247
Short name T352
Test name
Test status
Simulation time 6527951616 ps
CPU time 13.7 seconds
Started May 19 12:30:29 PM PDT 24
Finished May 19 12:30:46 PM PDT 24
Peak memory 199080 kb
Host smart-6cd7d988-2cbc-4673-bce6-8cfef1d5c95c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=462897247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.462897247
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.331910652
Short name T15
Test name
Test status
Simulation time 156649466327 ps
CPU time 26.39 seconds
Started May 19 12:30:26 PM PDT 24
Finished May 19 12:30:54 PM PDT 24
Peak memory 200288 kb
Host smart-137b21dd-9a5e-46ea-8d10-5f0125f59d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331910652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.331910652
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3878500137
Short name T465
Test name
Test status
Simulation time 44422877303 ps
CPU time 15.92 seconds
Started May 19 12:30:25 PM PDT 24
Finished May 19 12:30:43 PM PDT 24
Peak memory 196028 kb
Host smart-102c8196-539a-41bd-b0a6-62d7d13408ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878500137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3878500137
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3113257708
Short name T775
Test name
Test status
Simulation time 6042968768 ps
CPU time 11.46 seconds
Started May 19 12:30:29 PM PDT 24
Finished May 19 12:30:44 PM PDT 24
Peak memory 200080 kb
Host smart-9d30cf4b-3217-4dff-9af4-014ea5a1f0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113257708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3113257708
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2671780874
Short name T847
Test name
Test status
Simulation time 408841374461 ps
CPU time 578.17 seconds
Started May 19 12:30:31 PM PDT 24
Finished May 19 12:40:12 PM PDT 24
Peak memory 209288 kb
Host smart-f0797fa1-897b-42fa-8323-08dac6ef662b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671780874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2671780874
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2987229160
Short name T107
Test name
Test status
Simulation time 65059021247 ps
CPU time 145.8 seconds
Started May 19 12:30:27 PM PDT 24
Finished May 19 12:32:55 PM PDT 24
Peak memory 216272 kb
Host smart-b7d60ba8-90a7-4149-b1b6-30a57a01cce2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987229160 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2987229160
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.267029382
Short name T501
Test name
Test status
Simulation time 3082327307 ps
CPU time 1.37 seconds
Started May 19 12:30:29 PM PDT 24
Finished May 19 12:30:33 PM PDT 24
Peak memory 199444 kb
Host smart-5bb64b24-55ef-46cc-a070-a481702977ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267029382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.267029382
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2675996609
Short name T664
Test name
Test status
Simulation time 22559524346 ps
CPU time 39.77 seconds
Started May 19 12:30:21 PM PDT 24
Finished May 19 12:31:03 PM PDT 24
Peak memory 200672 kb
Host smart-2955ffff-f7fa-42d4-b6a6-de197337137e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675996609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2675996609
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2560878528
Short name T1115
Test name
Test status
Simulation time 37739297 ps
CPU time 0.57 seconds
Started May 19 12:28:53 PM PDT 24
Finished May 19 12:28:54 PM PDT 24
Peak memory 195664 kb
Host smart-de05f284-7497-4591-a82c-4dec25d54482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560878528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2560878528
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1901564496
Short name T746
Test name
Test status
Simulation time 26489126314 ps
CPU time 39.02 seconds
Started May 19 12:29:22 PM PDT 24
Finished May 19 12:30:02 PM PDT 24
Peak memory 200376 kb
Host smart-e2cf160b-5a00-46e4-99de-fdaba6aac726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901564496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1901564496
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.447539564
Short name T996
Test name
Test status
Simulation time 17527760598 ps
CPU time 27.07 seconds
Started May 19 12:29:18 PM PDT 24
Finished May 19 12:29:46 PM PDT 24
Peak memory 199924 kb
Host smart-ffc0e278-a95c-4d3e-a716-fe709aa48d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447539564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.447539564
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3275527443
Short name T859
Test name
Test status
Simulation time 19747594732 ps
CPU time 37.12 seconds
Started May 19 12:29:16 PM PDT 24
Finished May 19 12:29:54 PM PDT 24
Peak memory 200748 kb
Host smart-4f678e3f-8171-4d52-bf40-ee3a3cf9d54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275527443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3275527443
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.168355398
Short name T681
Test name
Test status
Simulation time 63786746756 ps
CPU time 110.57 seconds
Started May 19 12:28:57 PM PDT 24
Finished May 19 12:30:48 PM PDT 24
Peak memory 200216 kb
Host smart-71d117d4-f621-4dce-b454-e777b118cd31
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168355398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.168355398
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.791472444
Short name T674
Test name
Test status
Simulation time 58439583270 ps
CPU time 290.03 seconds
Started May 19 12:28:52 PM PDT 24
Finished May 19 12:33:43 PM PDT 24
Peak memory 200216 kb
Host smart-511462e3-ed40-42ae-a480-738512bcabc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791472444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.791472444
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.223938022
Short name T860
Test name
Test status
Simulation time 7869549971 ps
CPU time 6.15 seconds
Started May 19 12:29:16 PM PDT 24
Finished May 19 12:29:24 PM PDT 24
Peak memory 200204 kb
Host smart-62d6f119-50fa-4837-91e9-00d9e0917b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223938022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.223938022
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2528284171
Short name T858
Test name
Test status
Simulation time 77894648450 ps
CPU time 45.26 seconds
Started May 19 12:29:12 PM PDT 24
Finished May 19 12:29:57 PM PDT 24
Peak memory 200360 kb
Host smart-77f58491-fe42-44fc-a6a6-526d24f1ab79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528284171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2528284171
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2800662577
Short name T976
Test name
Test status
Simulation time 17173091375 ps
CPU time 907.17 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:45:16 PM PDT 24
Peak memory 199888 kb
Host smart-a07e4adc-5ba9-476b-9a32-7a9dd21b47d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2800662577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2800662577
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2198025194
Short name T791
Test name
Test status
Simulation time 2841861888 ps
CPU time 4.7 seconds
Started May 19 12:29:18 PM PDT 24
Finished May 19 12:29:24 PM PDT 24
Peak memory 198340 kb
Host smart-016e4392-6a8b-436f-a372-e798026433a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198025194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2198025194
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2342754374
Short name T175
Test name
Test status
Simulation time 49826697449 ps
CPU time 93.49 seconds
Started May 19 12:29:19 PM PDT 24
Finished May 19 12:30:54 PM PDT 24
Peak memory 200352 kb
Host smart-cf7320e1-f255-4999-86de-8df058ccf6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342754374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2342754374
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3407548204
Short name T455
Test name
Test status
Simulation time 668684675 ps
CPU time 0.89 seconds
Started May 19 12:29:22 PM PDT 24
Finished May 19 12:29:28 PM PDT 24
Peak memory 195684 kb
Host smart-ebd67a8b-9573-4d3e-a105-34ec581175dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407548204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3407548204
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3955968278
Short name T96
Test name
Test status
Simulation time 72106355 ps
CPU time 0.75 seconds
Started May 19 12:29:17 PM PDT 24
Finished May 19 12:29:19 PM PDT 24
Peak memory 218480 kb
Host smart-09b7e970-dc13-4dee-8fb0-35093cd17647
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955968278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3955968278
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.149049030
Short name T702
Test name
Test status
Simulation time 87591307 ps
CPU time 0.86 seconds
Started May 19 12:29:27 PM PDT 24
Finished May 19 12:29:28 PM PDT 24
Peak memory 197372 kb
Host smart-d4f952ff-8282-40a2-babd-10d7e577f5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149049030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.149049030
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3462599063
Short name T688
Test name
Test status
Simulation time 192614485104 ps
CPU time 962.77 seconds
Started May 19 12:28:55 PM PDT 24
Finished May 19 12:44:58 PM PDT 24
Peak memory 200296 kb
Host smart-c83ef962-5949-426f-9080-71b4e00cf07a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462599063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3462599063
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2485431844
Short name T313
Test name
Test status
Simulation time 249729203868 ps
CPU time 1891.8 seconds
Started May 19 12:29:22 PM PDT 24
Finished May 19 01:00:55 PM PDT 24
Peak memory 225304 kb
Host smart-aebda26f-b73a-4538-8c33-2d64d67acf07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485431844 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2485431844
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2456118554
Short name T733
Test name
Test status
Simulation time 7746779948 ps
CPU time 9.02 seconds
Started May 19 12:28:54 PM PDT 24
Finished May 19 12:29:04 PM PDT 24
Peak memory 200164 kb
Host smart-76144459-8d0c-43c8-aada-ec128f9d1820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456118554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2456118554
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1642261462
Short name T482
Test name
Test status
Simulation time 10154202311 ps
CPU time 16.73 seconds
Started May 19 12:29:10 PM PDT 24
Finished May 19 12:29:27 PM PDT 24
Peak memory 199804 kb
Host smart-f0cdd63d-88e3-466e-9b3a-ae4151aeaef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642261462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1642261462
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2402366028
Short name T832
Test name
Test status
Simulation time 51758340 ps
CPU time 0.59 seconds
Started May 19 12:30:34 PM PDT 24
Finished May 19 12:30:37 PM PDT 24
Peak memory 195688 kb
Host smart-feddd0a8-c512-4ef5-a5b8-dd83125d51ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402366028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2402366028
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2041590051
Short name T418
Test name
Test status
Simulation time 31915799425 ps
CPU time 56.16 seconds
Started May 19 12:30:25 PM PDT 24
Finished May 19 12:31:23 PM PDT 24
Peak memory 200232 kb
Host smart-9658a2bd-41bc-4add-abf1-723e268dcc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041590051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2041590051
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2908067869
Short name T1032
Test name
Test status
Simulation time 166532481564 ps
CPU time 55.91 seconds
Started May 19 12:30:30 PM PDT 24
Finished May 19 12:31:29 PM PDT 24
Peak memory 200176 kb
Host smart-b3ae602c-f718-4261-9fdf-f411adff92b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908067869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2908067869
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1702464107
Short name T563
Test name
Test status
Simulation time 32480995540 ps
CPU time 17.73 seconds
Started May 19 12:30:27 PM PDT 24
Finished May 19 12:30:47 PM PDT 24
Peak memory 200336 kb
Host smart-103731da-cd7f-416e-b6fd-12ac3a1ea644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702464107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1702464107
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.610151241
Short name T564
Test name
Test status
Simulation time 35760482365 ps
CPU time 57.07 seconds
Started May 19 12:30:28 PM PDT 24
Finished May 19 12:31:26 PM PDT 24
Peak memory 200204 kb
Host smart-16262ceb-a2e5-45fe-b31c-75166e3b4aa7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610151241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.610151241
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1179552780
Short name T659
Test name
Test status
Simulation time 66827400994 ps
CPU time 423.25 seconds
Started May 19 12:30:36 PM PDT 24
Finished May 19 12:37:43 PM PDT 24
Peak memory 200232 kb
Host smart-5501759c-470f-4705-8e49-064bf5bea16f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179552780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1179552780
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.171677916
Short name T378
Test name
Test status
Simulation time 5127387693 ps
CPU time 3.4 seconds
Started May 19 12:30:30 PM PDT 24
Finished May 19 12:30:37 PM PDT 24
Peak memory 199184 kb
Host smart-c43a1dc9-2517-4cfa-8e34-e175c31c6023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171677916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.171677916
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2298349128
Short name T593
Test name
Test status
Simulation time 234432985798 ps
CPU time 97.7 seconds
Started May 19 12:30:31 PM PDT 24
Finished May 19 12:32:12 PM PDT 24
Peak memory 199872 kb
Host smart-b58d3a32-0b0e-4d09-9c3e-60c205eb6674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298349128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2298349128
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1510460900
Short name T537
Test name
Test status
Simulation time 17175473659 ps
CPU time 969.44 seconds
Started May 19 12:30:27 PM PDT 24
Finished May 19 12:46:38 PM PDT 24
Peak memory 200292 kb
Host smart-09dc33f8-acf0-4860-a33d-4c75f47476a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1510460900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1510460900
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3732617299
Short name T22
Test name
Test status
Simulation time 2869392797 ps
CPU time 17.54 seconds
Started May 19 12:30:34 PM PDT 24
Finished May 19 12:30:55 PM PDT 24
Peak memory 199236 kb
Host smart-b1867618-2851-4dca-b733-3b038dd73e89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732617299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3732617299
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.493756431
Short name T708
Test name
Test status
Simulation time 74283657872 ps
CPU time 22.7 seconds
Started May 19 12:30:32 PM PDT 24
Finished May 19 12:30:59 PM PDT 24
Peak memory 199956 kb
Host smart-53fe48b1-fecd-4a2b-a7af-f524e4357908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493756431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.493756431
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3340508257
Short name T1165
Test name
Test status
Simulation time 43158915679 ps
CPU time 4.59 seconds
Started May 19 12:30:26 PM PDT 24
Finished May 19 12:30:33 PM PDT 24
Peak memory 196264 kb
Host smart-5591bd79-3ebe-40d7-8e43-d4f4d7d2106c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340508257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3340508257
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.436796633
Short name T1031
Test name
Test status
Simulation time 508474980 ps
CPU time 3.18 seconds
Started May 19 12:30:29 PM PDT 24
Finished May 19 12:30:35 PM PDT 24
Peak memory 199648 kb
Host smart-83707941-c5b1-497f-b822-af6253589d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436796633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.436796633
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.4212039225
Short name T677
Test name
Test status
Simulation time 51040769367 ps
CPU time 545.28 seconds
Started May 19 12:30:36 PM PDT 24
Finished May 19 12:39:45 PM PDT 24
Peak memory 200288 kb
Host smart-54775717-9ad6-4a06-8d97-6bbdade61e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212039225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.4212039225
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.105460868
Short name T61
Test name
Test status
Simulation time 313411321731 ps
CPU time 744.89 seconds
Started May 19 12:30:32 PM PDT 24
Finished May 19 12:43:00 PM PDT 24
Peak memory 230312 kb
Host smart-a9131955-dd8f-4935-b30a-b12a32ff82ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105460868 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.105460868
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2395065299
Short name T358
Test name
Test status
Simulation time 1224098295 ps
CPU time 3.88 seconds
Started May 19 12:30:28 PM PDT 24
Finished May 19 12:30:33 PM PDT 24
Peak memory 198812 kb
Host smart-00f1c387-31d5-4906-8378-827cd3b8a67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395065299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2395065299
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3709993358
Short name T635
Test name
Test status
Simulation time 90059879810 ps
CPU time 125.23 seconds
Started May 19 12:30:27 PM PDT 24
Finished May 19 12:32:34 PM PDT 24
Peak memory 200692 kb
Host smart-09b90857-ae6d-4739-8068-0c60945c6024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709993358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3709993358
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.4040307331
Short name T933
Test name
Test status
Simulation time 12662459 ps
CPU time 0.56 seconds
Started May 19 12:30:30 PM PDT 24
Finished May 19 12:30:34 PM PDT 24
Peak memory 195684 kb
Host smart-9bc843ee-707f-4c18-8958-c09c0662259d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040307331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.4040307331
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3012337759
Short name T642
Test name
Test status
Simulation time 156305002488 ps
CPU time 39.85 seconds
Started May 19 12:30:29 PM PDT 24
Finished May 19 12:31:12 PM PDT 24
Peak memory 200068 kb
Host smart-45132656-2589-4517-8f22-c56aa6bcbbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012337759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3012337759
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3658247052
Short name T766
Test name
Test status
Simulation time 30929721712 ps
CPU time 14.55 seconds
Started May 19 12:30:30 PM PDT 24
Finished May 19 12:30:48 PM PDT 24
Peak memory 200268 kb
Host smart-996396ff-0055-4272-9351-be4fa6678145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658247052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3658247052
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3733253655
Short name T209
Test name
Test status
Simulation time 18795852066 ps
CPU time 9.21 seconds
Started May 19 12:30:40 PM PDT 24
Finished May 19 12:30:52 PM PDT 24
Peak memory 200304 kb
Host smart-a085ad80-06cb-4ad6-b772-674baf70c79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733253655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3733253655
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.474823783
Short name T1122
Test name
Test status
Simulation time 181072994314 ps
CPU time 155.31 seconds
Started May 19 12:30:35 PM PDT 24
Finished May 19 12:33:13 PM PDT 24
Peak memory 200272 kb
Host smart-cd1fb1d2-4025-4e4d-abaa-25dbac5b65df
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474823783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.474823783
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3825912327
Short name T966
Test name
Test status
Simulation time 92319156257 ps
CPU time 303.98 seconds
Started May 19 12:30:34 PM PDT 24
Finished May 19 12:35:41 PM PDT 24
Peak memory 200320 kb
Host smart-75d984b7-5195-4b86-a971-27e8febd79d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3825912327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3825912327
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.943946771
Short name T798
Test name
Test status
Simulation time 5328320204 ps
CPU time 5.4 seconds
Started May 19 12:30:34 PM PDT 24
Finished May 19 12:30:42 PM PDT 24
Peak memory 199260 kb
Host smart-55f4fa5f-d2e1-4c23-97e5-a8ffa5023f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943946771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.943946771
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3057583369
Short name T467
Test name
Test status
Simulation time 88344758402 ps
CPU time 80.44 seconds
Started May 19 12:30:30 PM PDT 24
Finished May 19 12:31:54 PM PDT 24
Peak memory 208732 kb
Host smart-585e8235-d96a-4992-8b56-a072b2b9316d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057583369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3057583369
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1230525023
Short name T948
Test name
Test status
Simulation time 3763959006 ps
CPU time 120.82 seconds
Started May 19 12:30:34 PM PDT 24
Finished May 19 12:32:38 PM PDT 24
Peak memory 200644 kb
Host smart-7a1b1321-8283-46f2-b1d5-d28f6dfdcd87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230525023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1230525023
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2417279912
Short name T459
Test name
Test status
Simulation time 6994609319 ps
CPU time 66.39 seconds
Started May 19 12:30:31 PM PDT 24
Finished May 19 12:31:41 PM PDT 24
Peak memory 199332 kb
Host smart-8015d93b-30fd-46d7-9260-d42e763f40e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2417279912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2417279912
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.4042343822
Short name T1002
Test name
Test status
Simulation time 107585203289 ps
CPU time 343.26 seconds
Started May 19 12:30:28 PM PDT 24
Finished May 19 12:36:14 PM PDT 24
Peak memory 200248 kb
Host smart-47b6425b-7e2e-4e97-a99d-67d57b63debd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042343822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.4042343822
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2682208714
Short name T301
Test name
Test status
Simulation time 25459458166 ps
CPU time 11.39 seconds
Started May 19 12:30:35 PM PDT 24
Finished May 19 12:30:50 PM PDT 24
Peak memory 196304 kb
Host smart-6110d957-ccb9-47bd-997f-b8071cc261b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682208714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2682208714
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2304851063
Short name T1024
Test name
Test status
Simulation time 664846757 ps
CPU time 2.4 seconds
Started May 19 12:30:39 PM PDT 24
Finished May 19 12:30:43 PM PDT 24
Peak memory 198524 kb
Host smart-ec9ff5ad-9ec6-409b-aa83-cda2ce993213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304851063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2304851063
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2474340891
Short name T539
Test name
Test status
Simulation time 102374911446 ps
CPU time 417.71 seconds
Started May 19 12:30:35 PM PDT 24
Finished May 19 12:37:37 PM PDT 24
Peak memory 208828 kb
Host smart-300a530c-b8ad-48fd-9d22-18223a6eaa3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474340891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2474340891
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3371245696
Short name T782
Test name
Test status
Simulation time 48807363073 ps
CPU time 640.03 seconds
Started May 19 12:30:34 PM PDT 24
Finished May 19 12:41:17 PM PDT 24
Peak memory 217096 kb
Host smart-f595f3ce-d704-49d7-a158-2ebcd4ba32e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371245696 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3371245696
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2217104920
Short name T526
Test name
Test status
Simulation time 680967422 ps
CPU time 2.35 seconds
Started May 19 12:30:30 PM PDT 24
Finished May 19 12:30:35 PM PDT 24
Peak memory 198536 kb
Host smart-703915fd-086e-4ff6-adff-7bf4b6b21cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217104920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2217104920
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3860017192
Short name T931
Test name
Test status
Simulation time 19581624428 ps
CPU time 16.95 seconds
Started May 19 12:30:33 PM PDT 24
Finished May 19 12:30:53 PM PDT 24
Peak memory 200328 kb
Host smart-ff60a810-12f4-4e07-a5a5-0ed909351f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860017192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3860017192
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1406211833
Short name T801
Test name
Test status
Simulation time 14550226 ps
CPU time 0.55 seconds
Started May 19 12:30:37 PM PDT 24
Finished May 19 12:30:40 PM PDT 24
Peak memory 195720 kb
Host smart-bb2126d5-510d-44c9-b089-4f4561a552ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406211833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1406211833
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.4194586516
Short name T726
Test name
Test status
Simulation time 58062985100 ps
CPU time 14.7 seconds
Started May 19 12:30:35 PM PDT 24
Finished May 19 12:30:53 PM PDT 24
Peak memory 200304 kb
Host smart-d94ec701-6290-47a1-8b26-eb69a195efdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194586516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.4194586516
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.938646908
Short name T759
Test name
Test status
Simulation time 83742863121 ps
CPU time 138.7 seconds
Started May 19 12:30:39 PM PDT 24
Finished May 19 12:33:00 PM PDT 24
Peak memory 200176 kb
Host smart-dc8bde28-a61b-4176-97e5-7056154fbf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938646908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.938646908
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1115143027
Short name T555
Test name
Test status
Simulation time 233577106299 ps
CPU time 83.65 seconds
Started May 19 12:30:41 PM PDT 24
Finished May 19 12:32:08 PM PDT 24
Peak memory 200404 kb
Host smart-214d7ae6-1dbf-43db-a56c-2cd82f06c744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115143027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1115143027
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.292992634
Short name T932
Test name
Test status
Simulation time 48229944308 ps
CPU time 54.69 seconds
Started May 19 12:30:40 PM PDT 24
Finished May 19 12:31:38 PM PDT 24
Peak memory 200292 kb
Host smart-47ef78ed-1161-4817-9fab-202d40073b1f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292992634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.292992634
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3274151966
Short name T1084
Test name
Test status
Simulation time 170679323482 ps
CPU time 434.37 seconds
Started May 19 12:30:35 PM PDT 24
Finished May 19 12:37:53 PM PDT 24
Peak memory 200336 kb
Host smart-eca91220-fc62-4908-b716-e7458463e0b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3274151966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3274151966
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2923125469
Short name T586
Test name
Test status
Simulation time 5041951648 ps
CPU time 11.47 seconds
Started May 19 12:30:34 PM PDT 24
Finished May 19 12:30:49 PM PDT 24
Peak memory 199824 kb
Host smart-5609add3-49cd-4c21-b451-42d52d3117be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923125469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2923125469
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3070900015
Short name T258
Test name
Test status
Simulation time 41702015764 ps
CPU time 40.18 seconds
Started May 19 12:30:34 PM PDT 24
Finished May 19 12:31:18 PM PDT 24
Peak memory 200628 kb
Host smart-ac28d760-b8e6-41ca-a80d-9b1eeef2cd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070900015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3070900015
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3811236876
Short name T938
Test name
Test status
Simulation time 29906720983 ps
CPU time 1216.64 seconds
Started May 19 12:30:36 PM PDT 24
Finished May 19 12:50:56 PM PDT 24
Peak memory 200192 kb
Host smart-120f595b-06e5-492e-a16b-90213f43a64f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3811236876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3811236876
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.628723731
Short name T655
Test name
Test status
Simulation time 1483491440 ps
CPU time 2.01 seconds
Started May 19 12:30:36 PM PDT 24
Finished May 19 12:30:41 PM PDT 24
Peak memory 197280 kb
Host smart-50646084-fb94-400c-a1be-3a4b168108ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=628723731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.628723731
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.4059121168
Short name T722
Test name
Test status
Simulation time 91731778458 ps
CPU time 98.56 seconds
Started May 19 12:30:37 PM PDT 24
Finished May 19 12:32:19 PM PDT 24
Peak memory 200252 kb
Host smart-dcb49ea9-d037-4863-ab40-9ce330cb408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059121168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.4059121168
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.4213251181
Short name T824
Test name
Test status
Simulation time 4134010648 ps
CPU time 1.41 seconds
Started May 19 12:30:40 PM PDT 24
Finished May 19 12:30:43 PM PDT 24
Peak memory 196252 kb
Host smart-abfdf5cd-d5ca-4900-a930-bb2b663dd0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213251181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4213251181
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1267559971
Short name T891
Test name
Test status
Simulation time 696163947 ps
CPU time 1.62 seconds
Started May 19 12:30:30 PM PDT 24
Finished May 19 12:30:36 PM PDT 24
Peak memory 199008 kb
Host smart-5c242298-b22c-45c9-803b-194b94db0bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267559971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1267559971
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.97861175
Short name T577
Test name
Test status
Simulation time 224292105849 ps
CPU time 1472.1 seconds
Started May 19 12:30:36 PM PDT 24
Finished May 19 12:55:11 PM PDT 24
Peak memory 200644 kb
Host smart-e431bc6a-2ee5-4f03-a9fc-11a2fa3dc430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97861175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.97861175
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3492669469
Short name T37
Test name
Test status
Simulation time 129291544015 ps
CPU time 390.38 seconds
Started May 19 12:30:37 PM PDT 24
Finished May 19 12:37:10 PM PDT 24
Peak memory 217048 kb
Host smart-a70ba3e9-6498-447d-a775-ac6f5a300cf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492669469 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3492669469
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1613310768
Short name T1139
Test name
Test status
Simulation time 3338170296 ps
CPU time 2.04 seconds
Started May 19 12:30:37 PM PDT 24
Finished May 19 12:30:42 PM PDT 24
Peak memory 199480 kb
Host smart-d0677766-5f6c-4ed9-93d8-dbff79c08978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613310768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1613310768
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1558386106
Short name T426
Test name
Test status
Simulation time 35686026267 ps
CPU time 32.86 seconds
Started May 19 12:30:35 PM PDT 24
Finished May 19 12:31:11 PM PDT 24
Peak memory 200064 kb
Host smart-132654a9-6114-4847-8614-a4b04fdf1ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558386106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1558386106
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1210493685
Short name T432
Test name
Test status
Simulation time 22407914 ps
CPU time 0.59 seconds
Started May 19 12:30:42 PM PDT 24
Finished May 19 12:30:46 PM PDT 24
Peak memory 195644 kb
Host smart-f9bda545-fb65-42cb-95e2-63219f0ab761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210493685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1210493685
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.100443736
Short name T680
Test name
Test status
Simulation time 55325692854 ps
CPU time 25.65 seconds
Started May 19 12:30:35 PM PDT 24
Finished May 19 12:31:05 PM PDT 24
Peak memory 200400 kb
Host smart-2442a8df-d2f2-4f2b-88a1-2eabb53b145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100443736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.100443736
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.267821686
Short name T122
Test name
Test status
Simulation time 52841650764 ps
CPU time 100.33 seconds
Started May 19 12:30:35 PM PDT 24
Finished May 19 12:32:18 PM PDT 24
Peak memory 200196 kb
Host smart-23b01ccc-7418-4a7b-9e2d-67f24420b443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267821686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.267821686
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3923674137
Short name T787
Test name
Test status
Simulation time 45409483384 ps
CPU time 19.91 seconds
Started May 19 12:30:37 PM PDT 24
Finished May 19 12:31:00 PM PDT 24
Peak memory 200300 kb
Host smart-afc5e52e-3219-425e-904c-3a4bdd52b37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923674137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3923674137
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1274587347
Short name T552
Test name
Test status
Simulation time 5869792767 ps
CPU time 9.13 seconds
Started May 19 12:30:37 PM PDT 24
Finished May 19 12:30:49 PM PDT 24
Peak memory 200228 kb
Host smart-3d3c65c9-7989-439b-aad4-47e03bfbe0ba
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274587347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1274587347
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.2746210441
Short name T250
Test name
Test status
Simulation time 91323931993 ps
CPU time 205.68 seconds
Started May 19 12:30:40 PM PDT 24
Finished May 19 12:34:08 PM PDT 24
Peak memory 200216 kb
Host smart-ff419330-5eed-4ae9-8cdf-ca07b7ce376b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746210441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2746210441
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1457300187
Short name T345
Test name
Test status
Simulation time 6251458654 ps
CPU time 20.69 seconds
Started May 19 12:30:35 PM PDT 24
Finished May 19 12:30:59 PM PDT 24
Peak memory 199960 kb
Host smart-ef831006-3d7b-4dfe-9813-fb328fb83f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457300187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1457300187
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2353559348
Short name T394
Test name
Test status
Simulation time 108095740990 ps
CPU time 137.45 seconds
Started May 19 12:30:40 PM PDT 24
Finished May 19 12:33:00 PM PDT 24
Peak memory 200680 kb
Host smart-d7b73104-4c69-4d64-810d-a814f6629f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353559348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2353559348
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.581296412
Short name T591
Test name
Test status
Simulation time 37131875076 ps
CPU time 177.77 seconds
Started May 19 12:30:38 PM PDT 24
Finished May 19 12:33:38 PM PDT 24
Peak memory 200336 kb
Host smart-15cf668e-2ffe-4528-875f-a325a80f9d54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=581296412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.581296412
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1909779093
Short name T368
Test name
Test status
Simulation time 3321070956 ps
CPU time 20.52 seconds
Started May 19 12:30:35 PM PDT 24
Finished May 19 12:30:59 PM PDT 24
Peak memory 198608 kb
Host smart-64129e41-dbc8-450e-8012-1e6a98640c56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1909779093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1909779093
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3381879459
Short name T323
Test name
Test status
Simulation time 56566826186 ps
CPU time 43.66 seconds
Started May 19 12:30:36 PM PDT 24
Finished May 19 12:31:23 PM PDT 24
Peak memory 200228 kb
Host smart-db60ee83-48b6-450a-b8c0-b3e53e269d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381879459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3381879459
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1502589960
Short name T542
Test name
Test status
Simulation time 40071011569 ps
CPU time 7.16 seconds
Started May 19 12:30:41 PM PDT 24
Finished May 19 12:30:51 PM PDT 24
Peak memory 196088 kb
Host smart-d3e72ddb-92e1-4fae-8c81-6026aa997714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502589960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1502589960
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.376668595
Short name T789
Test name
Test status
Simulation time 687911652 ps
CPU time 2.06 seconds
Started May 19 12:30:40 PM PDT 24
Finished May 19 12:30:45 PM PDT 24
Peak memory 199588 kb
Host smart-3ce06c7d-20f5-44e5-bc06-ad485ab8c066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376668595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.376668595
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.836228869
Short name T159
Test name
Test status
Simulation time 511928428584 ps
CPU time 630.2 seconds
Started May 19 12:30:42 PM PDT 24
Finished May 19 12:41:16 PM PDT 24
Peak memory 209668 kb
Host smart-5865a12f-b655-45c9-a883-c62da3513b7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836228869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.836228869
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.540745752
Short name T1027
Test name
Test status
Simulation time 45990597522 ps
CPU time 558.85 seconds
Started May 19 12:30:36 PM PDT 24
Finished May 19 12:39:59 PM PDT 24
Peak memory 225280 kb
Host smart-5b2f9c83-2b0c-4dbf-b807-1cffd909f300
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540745752 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.540745752
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2782785878
Short name T1127
Test name
Test status
Simulation time 637946847 ps
CPU time 2.17 seconds
Started May 19 12:30:35 PM PDT 24
Finished May 19 12:30:41 PM PDT 24
Peak memory 200160 kb
Host smart-472e5a40-cdf2-4517-be38-4e868020e2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782785878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2782785878
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1555444653
Short name T290
Test name
Test status
Simulation time 19542703441 ps
CPU time 21.7 seconds
Started May 19 12:30:35 PM PDT 24
Finished May 19 12:31:01 PM PDT 24
Peak memory 200360 kb
Host smart-a49cd9d5-97b8-4879-8ca2-9db0402023f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555444653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1555444653
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.710877330
Short name T348
Test name
Test status
Simulation time 12128364 ps
CPU time 0.55 seconds
Started May 19 12:30:40 PM PDT 24
Finished May 19 12:30:43 PM PDT 24
Peak memory 195664 kb
Host smart-f50aed67-7f29-4dc3-9eda-19a6e0ad71a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710877330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.710877330
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3366714836
Short name T1109
Test name
Test status
Simulation time 175746270006 ps
CPU time 336.42 seconds
Started May 19 12:30:39 PM PDT 24
Finished May 19 12:36:17 PM PDT 24
Peak memory 200112 kb
Host smart-7cbeeadc-4c36-4ac0-9f4f-b656751a38db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366714836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3366714836
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3953298913
Short name T864
Test name
Test status
Simulation time 20416326778 ps
CPU time 38.26 seconds
Started May 19 12:30:43 PM PDT 24
Finished May 19 12:31:25 PM PDT 24
Peak memory 199900 kb
Host smart-820e1f0e-b03b-40ec-9ca5-cb4c40e60c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953298913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3953298913
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.562427066
Short name T232
Test name
Test status
Simulation time 89901556324 ps
CPU time 73.97 seconds
Started May 19 12:30:42 PM PDT 24
Finished May 19 12:32:00 PM PDT 24
Peak memory 200268 kb
Host smart-5b071a7f-f90f-425a-a218-8a8264f31531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562427066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.562427066
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1242508162
Short name T567
Test name
Test status
Simulation time 33045821464 ps
CPU time 56.57 seconds
Started May 19 12:30:42 PM PDT 24
Finished May 19 12:31:42 PM PDT 24
Peak memory 199880 kb
Host smart-c4390739-9b40-43a0-80be-53e4f8ba7dbc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242508162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1242508162
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3576356626
Short name T784
Test name
Test status
Simulation time 68223196637 ps
CPU time 196.79 seconds
Started May 19 12:30:44 PM PDT 24
Finished May 19 12:34:04 PM PDT 24
Peak memory 200332 kb
Host smart-a0b8fdbb-96ea-4c30-9c1d-462b245c8f19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576356626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3576356626
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1697829560
Short name T757
Test name
Test status
Simulation time 2870960790 ps
CPU time 2.04 seconds
Started May 19 12:30:42 PM PDT 24
Finished May 19 12:30:47 PM PDT 24
Peak memory 196660 kb
Host smart-0605d8d5-766c-41c6-82ff-65e87040c369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697829560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1697829560
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2951286554
Short name T518
Test name
Test status
Simulation time 99582186793 ps
CPU time 86.5 seconds
Started May 19 12:30:43 PM PDT 24
Finished May 19 12:32:13 PM PDT 24
Peak memory 200156 kb
Host smart-71ad3bbb-afa7-4f42-80f1-c758030ab7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951286554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2951286554
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.494192819
Short name T1157
Test name
Test status
Simulation time 7737229820 ps
CPU time 109.5 seconds
Started May 19 12:30:41 PM PDT 24
Finished May 19 12:32:34 PM PDT 24
Peak memory 200224 kb
Host smart-02490c8b-452a-4a71-8afc-4fa55a76540b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=494192819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.494192819
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3583195241
Short name T626
Test name
Test status
Simulation time 4523251443 ps
CPU time 40.51 seconds
Started May 19 12:30:39 PM PDT 24
Finished May 19 12:31:22 PM PDT 24
Peak memory 199636 kb
Host smart-cc1d28bb-a4f9-4a12-8955-61e66622026e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3583195241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3583195241
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1289422564
Short name T945
Test name
Test status
Simulation time 174390676565 ps
CPU time 71.71 seconds
Started May 19 12:30:41 PM PDT 24
Finished May 19 12:31:56 PM PDT 24
Peak memory 200264 kb
Host smart-f6086d1b-624d-4479-acd2-8283de3aa348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289422564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1289422564
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2361935315
Short name T259
Test name
Test status
Simulation time 37099474743 ps
CPU time 62.47 seconds
Started May 19 12:30:42 PM PDT 24
Finished May 19 12:31:48 PM PDT 24
Peak memory 196032 kb
Host smart-4d898066-9b03-46c1-a9d4-261c39c5509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361935315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2361935315
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2764918420
Short name T1107
Test name
Test status
Simulation time 5527496904 ps
CPU time 9.54 seconds
Started May 19 12:30:40 PM PDT 24
Finished May 19 12:30:53 PM PDT 24
Peak memory 200720 kb
Host smart-3ff5347a-cfea-40b8-a18f-fc4a1b6baad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764918420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2764918420
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2776471349
Short name T867
Test name
Test status
Simulation time 1192798589 ps
CPU time 2.63 seconds
Started May 19 12:30:42 PM PDT 24
Finished May 19 12:30:49 PM PDT 24
Peak memory 199188 kb
Host smart-0ae55540-7f42-430d-88ad-1406f2fdf4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776471349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2776471349
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1067972017
Short name T999
Test name
Test status
Simulation time 52678287120 ps
CPU time 93.36 seconds
Started May 19 12:30:42 PM PDT 24
Finished May 19 12:32:18 PM PDT 24
Peak memory 200316 kb
Host smart-5cb50031-8353-413f-8d00-c80f44b63fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067972017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1067972017
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3220056887
Short name T1103
Test name
Test status
Simulation time 16896389 ps
CPU time 0.57 seconds
Started May 19 12:30:55 PM PDT 24
Finished May 19 12:30:57 PM PDT 24
Peak memory 195396 kb
Host smart-b15b8fc7-ec79-4549-8a81-b539c8da9df6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220056887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3220056887
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.320491536
Short name T510
Test name
Test status
Simulation time 178294597559 ps
CPU time 144.75 seconds
Started May 19 12:30:42 PM PDT 24
Finished May 19 12:33:10 PM PDT 24
Peak memory 200312 kb
Host smart-0626c2e3-33bb-4e74-82f0-7dc417c51c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320491536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.320491536
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3852821110
Short name T982
Test name
Test status
Simulation time 37100427963 ps
CPU time 26.17 seconds
Started May 19 12:30:45 PM PDT 24
Finished May 19 12:31:14 PM PDT 24
Peak memory 199892 kb
Host smart-3282a8b5-72c1-4acc-a55b-596effe58647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852821110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3852821110
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2596501856
Short name T412
Test name
Test status
Simulation time 114701328822 ps
CPU time 189.31 seconds
Started May 19 12:30:41 PM PDT 24
Finished May 19 12:33:54 PM PDT 24
Peak memory 200692 kb
Host smart-6e76bf07-da91-493a-8f59-6dac6fc32559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596501856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2596501856
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2522236165
Short name T566
Test name
Test status
Simulation time 65192750362 ps
CPU time 9.77 seconds
Started May 19 12:30:45 PM PDT 24
Finished May 19 12:30:58 PM PDT 24
Peak memory 199948 kb
Host smart-41dd8a3f-1487-40e8-bf9d-2cc4afcd9219
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522236165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2522236165
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1183345216
Short name T44
Test name
Test status
Simulation time 169339133746 ps
CPU time 1445.86 seconds
Started May 19 12:30:42 PM PDT 24
Finished May 19 12:54:52 PM PDT 24
Peak memory 200232 kb
Host smart-bf17eb87-9f54-4cca-9122-fe944aaf3394
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1183345216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1183345216
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1389877122
Short name T666
Test name
Test status
Simulation time 11925415265 ps
CPU time 5.45 seconds
Started May 19 12:30:40 PM PDT 24
Finished May 19 12:30:47 PM PDT 24
Peak memory 200236 kb
Host smart-e2dafe77-9886-4de2-96e8-444f6413f515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389877122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1389877122
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2880228549
Short name T884
Test name
Test status
Simulation time 49039130513 ps
CPU time 22.64 seconds
Started May 19 12:30:45 PM PDT 24
Finished May 19 12:31:10 PM PDT 24
Peak memory 200048 kb
Host smart-686e26cb-3867-48ab-bd07-5afaf8e48c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880228549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2880228549
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3568792914
Short name T913
Test name
Test status
Simulation time 21592322607 ps
CPU time 999.63 seconds
Started May 19 12:30:42 PM PDT 24
Finished May 19 12:47:26 PM PDT 24
Peak memory 200388 kb
Host smart-29a7d599-f743-48e7-b916-66a0a867537d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3568792914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3568792914
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2983648182
Short name T344
Test name
Test status
Simulation time 2021929426 ps
CPU time 11.67 seconds
Started May 19 12:30:41 PM PDT 24
Finished May 19 12:30:56 PM PDT 24
Peak memory 199344 kb
Host smart-49a8b82e-4ba4-4587-a7f3-f5ad38a2a6a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2983648182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2983648182
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3684649518
Short name T125
Test name
Test status
Simulation time 179008119296 ps
CPU time 91.54 seconds
Started May 19 12:30:45 PM PDT 24
Finished May 19 12:32:19 PM PDT 24
Peak memory 200200 kb
Host smart-2a963e89-51d7-4ca7-a530-9d3503324109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684649518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3684649518
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3158911125
Short name T665
Test name
Test status
Simulation time 40217490322 ps
CPU time 13.04 seconds
Started May 19 12:30:43 PM PDT 24
Finished May 19 12:31:00 PM PDT 24
Peak memory 196192 kb
Host smart-32426a82-574a-4a5f-8288-c06bd3f0f416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158911125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3158911125
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2401570148
Short name T975
Test name
Test status
Simulation time 637793199 ps
CPU time 1.82 seconds
Started May 19 12:30:43 PM PDT 24
Finished May 19 12:30:49 PM PDT 24
Peak memory 199120 kb
Host smart-2b3806b2-334e-4fd7-85c9-a505777c004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401570148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2401570148
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2051164982
Short name T964
Test name
Test status
Simulation time 229032595419 ps
CPU time 177.61 seconds
Started May 19 12:30:58 PM PDT 24
Finished May 19 12:33:58 PM PDT 24
Peak memory 200732 kb
Host smart-e73c7ade-dd68-4603-8ee1-180de95a47b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051164982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2051164982
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3017955374
Short name T137
Test name
Test status
Simulation time 158163856762 ps
CPU time 443.04 seconds
Started May 19 12:30:40 PM PDT 24
Finished May 19 12:38:06 PM PDT 24
Peak memory 226364 kb
Host smart-a2bd4e4e-5449-4f35-95ff-64478cfeee75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017955374 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3017955374
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2852446882
Short name T596
Test name
Test status
Simulation time 1074198885 ps
CPU time 3.89 seconds
Started May 19 12:30:41 PM PDT 24
Finished May 19 12:30:48 PM PDT 24
Peak memory 198812 kb
Host smart-97b4c2db-9a72-4f30-acc6-29b373f451b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852446882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2852446882
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2016344509
Short name T927
Test name
Test status
Simulation time 9947400986 ps
CPU time 7.5 seconds
Started May 19 12:30:43 PM PDT 24
Finished May 19 12:30:54 PM PDT 24
Peak memory 196868 kb
Host smart-db8c72e8-86de-4f2f-a2f1-504049d9d475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016344509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2016344509
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3903338192
Short name T1120
Test name
Test status
Simulation time 34824935 ps
CPU time 0.59 seconds
Started May 19 12:30:57 PM PDT 24
Finished May 19 12:31:00 PM PDT 24
Peak memory 195688 kb
Host smart-1b1bfeb7-b262-4f4a-9dae-7a1eecafc01d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903338192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3903338192
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1424592044
Short name T1152
Test name
Test status
Simulation time 64650616584 ps
CPU time 18.22 seconds
Started May 19 12:30:55 PM PDT 24
Finished May 19 12:31:15 PM PDT 24
Peak memory 200220 kb
Host smart-44f6817d-e5ee-4644-ba1c-7b9cfc9d9d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424592044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1424592044
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1469675727
Short name T304
Test name
Test status
Simulation time 111541551915 ps
CPU time 55.72 seconds
Started May 19 12:30:58 PM PDT 24
Finished May 19 12:31:56 PM PDT 24
Peak memory 200300 kb
Host smart-4347a519-d140-43e1-bca8-ee94b80db9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469675727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1469675727
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3726333989
Short name T921
Test name
Test status
Simulation time 33753264343 ps
CPU time 17.45 seconds
Started May 19 12:31:00 PM PDT 24
Finished May 19 12:31:19 PM PDT 24
Peak memory 200336 kb
Host smart-5a94e6f6-8d04-41b7-961e-37f2f8152f2c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726333989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3726333989
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.992043187
Short name T359
Test name
Test status
Simulation time 88303847842 ps
CPU time 270.8 seconds
Started May 19 12:30:55 PM PDT 24
Finished May 19 12:35:28 PM PDT 24
Peak memory 200396 kb
Host smart-b52787a3-3a76-4204-b0d8-38a2d3196db9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992043187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.992043187
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.975931032
Short name T1076
Test name
Test status
Simulation time 3661326963 ps
CPU time 8.17 seconds
Started May 19 12:30:56 PM PDT 24
Finished May 19 12:31:07 PM PDT 24
Peak memory 199664 kb
Host smart-3c4684c4-1bf1-4df1-b0a5-1df4e378c9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975931032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.975931032
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1370719123
Short name T517
Test name
Test status
Simulation time 72425977877 ps
CPU time 137.81 seconds
Started May 19 12:30:49 PM PDT 24
Finished May 19 12:33:08 PM PDT 24
Peak memory 208420 kb
Host smart-7ccb83dc-8fc0-4ecf-aff9-c1da4fe7c46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370719123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1370719123
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3927151595
Short name T738
Test name
Test status
Simulation time 9444345685 ps
CPU time 561.24 seconds
Started May 19 12:30:54 PM PDT 24
Finished May 19 12:40:17 PM PDT 24
Peak memory 200260 kb
Host smart-8ac2f411-f6fc-4577-807d-2755a138d578
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927151595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3927151595
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3053560315
Short name T1132
Test name
Test status
Simulation time 1789767752 ps
CPU time 6.39 seconds
Started May 19 12:30:48 PM PDT 24
Finished May 19 12:30:55 PM PDT 24
Peak memory 198220 kb
Host smart-0682a36a-9358-4b84-ad1b-c81020781703
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3053560315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3053560315
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2596480611
Short name T536
Test name
Test status
Simulation time 58956686270 ps
CPU time 13.51 seconds
Started May 19 12:30:57 PM PDT 24
Finished May 19 12:31:13 PM PDT 24
Peak memory 199564 kb
Host smart-d7f2573e-37ad-4147-83f6-660d836895c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596480611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2596480611
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2286266038
Short name T457
Test name
Test status
Simulation time 1983938516 ps
CPU time 3.69 seconds
Started May 19 12:30:50 PM PDT 24
Finished May 19 12:30:54 PM PDT 24
Peak memory 196004 kb
Host smart-c646e2a0-b971-4eff-91a4-c663189e3f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286266038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2286266038
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3381271649
Short name T835
Test name
Test status
Simulation time 528352963 ps
CPU time 1.06 seconds
Started May 19 12:30:55 PM PDT 24
Finished May 19 12:30:58 PM PDT 24
Peak memory 199504 kb
Host smart-d8b197bc-ce6e-4b36-b379-b8583c0515c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381271649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3381271649
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3520660846
Short name T780
Test name
Test status
Simulation time 149576149959 ps
CPU time 66.45 seconds
Started May 19 12:30:55 PM PDT 24
Finished May 19 12:32:04 PM PDT 24
Peak memory 200336 kb
Host smart-553bafb9-30ce-4764-be40-e7c5f2e0b18d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520660846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3520660846
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2428592749
Short name T1049
Test name
Test status
Simulation time 1102701503 ps
CPU time 3.59 seconds
Started May 19 12:30:53 PM PDT 24
Finished May 19 12:30:58 PM PDT 24
Peak memory 198500 kb
Host smart-7f6665ab-b79a-4185-bf01-9b2686673963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428592749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2428592749
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1839701835
Short name T1160
Test name
Test status
Simulation time 99572722760 ps
CPU time 192.4 seconds
Started May 19 12:30:49 PM PDT 24
Finished May 19 12:34:02 PM PDT 24
Peak memory 200276 kb
Host smart-312a5a1b-d8cd-4279-8ada-dc343dcad755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839701835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1839701835
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.701451403
Short name T50
Test name
Test status
Simulation time 11912669 ps
CPU time 0.55 seconds
Started May 19 12:30:55 PM PDT 24
Finished May 19 12:30:57 PM PDT 24
Peak memory 194664 kb
Host smart-53199de4-cae0-4758-a77d-319bddda0575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701451403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.701451403
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1246112882
Short name T703
Test name
Test status
Simulation time 36853261887 ps
CPU time 22.12 seconds
Started May 19 12:30:46 PM PDT 24
Finished May 19 12:31:10 PM PDT 24
Peak memory 200360 kb
Host smart-125423e0-1f9f-423d-ae5b-c39a964ef597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246112882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1246112882
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3937225539
Short name T880
Test name
Test status
Simulation time 53789321718 ps
CPU time 63.71 seconds
Started May 19 12:30:53 PM PDT 24
Finished May 19 12:31:58 PM PDT 24
Peak memory 200304 kb
Host smart-d57cffb8-8604-4204-ab91-ba99c33fa4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937225539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3937225539
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2302465429
Short name T1179
Test name
Test status
Simulation time 87030777599 ps
CPU time 65.22 seconds
Started May 19 12:30:50 PM PDT 24
Finished May 19 12:31:56 PM PDT 24
Peak memory 200268 kb
Host smart-92c61837-fedf-4985-a77f-32c8082068c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302465429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2302465429
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.131279512
Short name T1105
Test name
Test status
Simulation time 13798465458 ps
CPU time 20.27 seconds
Started May 19 12:30:53 PM PDT 24
Finished May 19 12:31:15 PM PDT 24
Peak memory 197076 kb
Host smart-09b28b96-3040-42aa-b4a7-6aff43e2f1c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131279512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.131279512
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.988997924
Short name T1095
Test name
Test status
Simulation time 58921593500 ps
CPU time 179.03 seconds
Started May 19 12:30:48 PM PDT 24
Finished May 19 12:33:48 PM PDT 24
Peak memory 200260 kb
Host smart-ab2dd78a-e383-4b89-afd1-a723d3341cd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988997924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.988997924
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3105470802
Short name T489
Test name
Test status
Simulation time 205109550 ps
CPU time 1.04 seconds
Started May 19 12:30:49 PM PDT 24
Finished May 19 12:30:50 PM PDT 24
Peak memory 197056 kb
Host smart-16ea9e98-0e37-4ef0-ac66-e782b019d687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105470802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3105470802
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1474776925
Short name T711
Test name
Test status
Simulation time 3737637404 ps
CPU time 3.67 seconds
Started May 19 12:30:48 PM PDT 24
Finished May 19 12:30:53 PM PDT 24
Peak memory 200312 kb
Host smart-f2d78ff4-4779-4480-8180-541452de9c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474776925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1474776925
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2455960746
Short name T1100
Test name
Test status
Simulation time 19232396361 ps
CPU time 530 seconds
Started May 19 12:30:53 PM PDT 24
Finished May 19 12:39:44 PM PDT 24
Peak memory 200360 kb
Host smart-7580cbe8-fd3e-4993-8cd2-0ea6a2eaefa2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2455960746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2455960746
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.146455495
Short name T391
Test name
Test status
Simulation time 6363463034 ps
CPU time 59.9 seconds
Started May 19 12:30:54 PM PDT 24
Finished May 19 12:31:55 PM PDT 24
Peak memory 199320 kb
Host smart-5bdfca79-1580-4f0d-8ba3-aef1847913f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=146455495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.146455495
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1303955691
Short name T657
Test name
Test status
Simulation time 21062420973 ps
CPU time 28.25 seconds
Started May 19 12:30:52 PM PDT 24
Finished May 19 12:31:22 PM PDT 24
Peak memory 200232 kb
Host smart-3cbb8722-52b5-48c1-ace3-0c8c1f84ae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303955691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1303955691
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2844046561
Short name T662
Test name
Test status
Simulation time 3084625973 ps
CPU time 1.85 seconds
Started May 19 12:30:54 PM PDT 24
Finished May 19 12:30:57 PM PDT 24
Peak memory 196044 kb
Host smart-54615774-04e3-47e6-aa25-82a55c0dbd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844046561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2844046561
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2173852425
Short name T1030
Test name
Test status
Simulation time 278877175 ps
CPU time 1.23 seconds
Started May 19 12:30:53 PM PDT 24
Finished May 19 12:30:55 PM PDT 24
Peak memory 198548 kb
Host smart-bd3f181d-b3ba-4c25-a16b-3970ab087304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173852425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2173852425
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.158181770
Short name T796
Test name
Test status
Simulation time 66153063420 ps
CPU time 624.86 seconds
Started May 19 12:30:47 PM PDT 24
Finished May 19 12:41:14 PM PDT 24
Peak memory 226788 kb
Host smart-7d66676b-4f52-4855-85eb-df4b911920d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158181770 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.158181770
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3849664372
Short name T441
Test name
Test status
Simulation time 1255014098 ps
CPU time 2.53 seconds
Started May 19 12:30:59 PM PDT 24
Finished May 19 12:31:03 PM PDT 24
Peak memory 198728 kb
Host smart-d478d5bc-e12f-4050-86f1-02dd5366ef63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849664372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3849664372
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1049317346
Short name T374
Test name
Test status
Simulation time 95747385913 ps
CPU time 102.68 seconds
Started May 19 12:30:47 PM PDT 24
Finished May 19 12:32:31 PM PDT 24
Peak memory 200124 kb
Host smart-636059c9-99bb-4977-a1e9-c0ae88e740b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049317346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1049317346
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3985062806
Short name T720
Test name
Test status
Simulation time 47145074 ps
CPU time 0.61 seconds
Started May 19 12:31:01 PM PDT 24
Finished May 19 12:31:03 PM PDT 24
Peak memory 195632 kb
Host smart-c809e40b-a1b0-435e-8f55-2f1bbfea72db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985062806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3985062806
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3710465671
Short name T583
Test name
Test status
Simulation time 101273919980 ps
CPU time 90.21 seconds
Started May 19 12:31:07 PM PDT 24
Finished May 19 12:32:39 PM PDT 24
Peak memory 200284 kb
Host smart-e21d9c33-f6e6-4023-9a0a-46558f3b3a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710465671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3710465671
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2907983824
Short name T1071
Test name
Test status
Simulation time 36152113989 ps
CPU time 20.8 seconds
Started May 19 12:31:00 PM PDT 24
Finished May 19 12:31:22 PM PDT 24
Peak memory 200660 kb
Host smart-e2d110c1-87ca-460b-930e-643488571906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907983824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2907983824
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.378085365
Short name T160
Test name
Test status
Simulation time 64707926296 ps
CPU time 27.63 seconds
Started May 19 12:30:57 PM PDT 24
Finished May 19 12:31:27 PM PDT 24
Peak memory 200396 kb
Host smart-87a10eec-f967-4024-b6cc-2189952d3df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378085365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.378085365
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1554312775
Short name T310
Test name
Test status
Simulation time 35182168091 ps
CPU time 17.2 seconds
Started May 19 12:30:57 PM PDT 24
Finished May 19 12:31:16 PM PDT 24
Peak memory 200088 kb
Host smart-edafe300-1122-444a-9949-4289234bd295
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554312775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1554312775
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1336865455
Short name T1083
Test name
Test status
Simulation time 44569383251 ps
CPU time 413.57 seconds
Started May 19 12:31:01 PM PDT 24
Finished May 19 12:37:55 PM PDT 24
Peak memory 200328 kb
Host smart-76ed85f1-3c77-4370-af1e-6add6fa0fc21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1336865455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1336865455
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1984536024
Short name T6
Test name
Test status
Simulation time 7347317647 ps
CPU time 2.57 seconds
Started May 19 12:30:55 PM PDT 24
Finished May 19 12:31:00 PM PDT 24
Peak memory 200320 kb
Host smart-0bb73e8a-6011-4194-9bb9-cab2c265df38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984536024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1984536024
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2373990002
Short name T275
Test name
Test status
Simulation time 51730705251 ps
CPU time 92.3 seconds
Started May 19 12:30:58 PM PDT 24
Finished May 19 12:32:33 PM PDT 24
Peak memory 200588 kb
Host smart-540b0999-b8e1-452b-a135-efe0b7cb7e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373990002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2373990002
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2696256542
Short name T879
Test name
Test status
Simulation time 10053702385 ps
CPU time 426.3 seconds
Started May 19 12:30:57 PM PDT 24
Finished May 19 12:38:06 PM PDT 24
Peak memory 200340 kb
Host smart-890e2d2d-e021-41b9-9170-9a4f4e37cf5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2696256542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2696256542
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.4279071080
Short name T572
Test name
Test status
Simulation time 4276055359 ps
CPU time 2.56 seconds
Started May 19 12:30:55 PM PDT 24
Finished May 19 12:30:59 PM PDT 24
Peak memory 198452 kb
Host smart-6c998501-e103-4e20-8233-cfaac223a4b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279071080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.4279071080
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1361048714
Short name T661
Test name
Test status
Simulation time 111335325099 ps
CPU time 18.07 seconds
Started May 19 12:31:08 PM PDT 24
Finished May 19 12:31:28 PM PDT 24
Peak memory 200168 kb
Host smart-5b370ef0-a769-475d-a4b9-92d9851332fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361048714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1361048714
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.639784156
Short name T580
Test name
Test status
Simulation time 24810966865 ps
CPU time 10.81 seconds
Started May 19 12:30:57 PM PDT 24
Finished May 19 12:31:11 PM PDT 24
Peak memory 196336 kb
Host smart-e7a062c6-5819-4b8a-98b0-e5798df7c82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639784156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.639784156
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3753775090
Short name T1104
Test name
Test status
Simulation time 6036650993 ps
CPU time 9.47 seconds
Started May 19 12:30:58 PM PDT 24
Finished May 19 12:31:10 PM PDT 24
Peak memory 199576 kb
Host smart-18f8e385-278b-4998-91a8-ee7beb6a3afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753775090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3753775090
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2362763419
Short name T1150
Test name
Test status
Simulation time 95188780568 ps
CPU time 273.8 seconds
Started May 19 12:30:56 PM PDT 24
Finished May 19 12:35:32 PM PDT 24
Peak memory 200376 kb
Host smart-397aaa93-30a4-4f38-bd9c-d0ad949fd8da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362763419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2362763419
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2407644786
Short name T732
Test name
Test status
Simulation time 111642059004 ps
CPU time 1309.08 seconds
Started May 19 12:30:56 PM PDT 24
Finished May 19 12:52:48 PM PDT 24
Peak memory 233320 kb
Host smart-67bae1d1-ed85-41d0-a724-436788ad5358
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407644786 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2407644786
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3332279153
Short name T366
Test name
Test status
Simulation time 1037124607 ps
CPU time 1.93 seconds
Started May 19 12:31:01 PM PDT 24
Finished May 19 12:31:04 PM PDT 24
Peak memory 198220 kb
Host smart-9e2b8e7a-8440-4fcd-b2fa-bab5a48541d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332279153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3332279153
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.4240627859
Short name T725
Test name
Test status
Simulation time 55839184123 ps
CPU time 27.63 seconds
Started May 19 12:31:02 PM PDT 24
Finished May 19 12:31:30 PM PDT 24
Peak memory 200276 kb
Host smart-4fe1452c-7c6d-4bd0-bcc2-057e82106846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240627859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.4240627859
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.231492119
Short name T27
Test name
Test status
Simulation time 30102375 ps
CPU time 0.59 seconds
Started May 19 12:30:57 PM PDT 24
Finished May 19 12:31:00 PM PDT 24
Peak memory 195656 kb
Host smart-3ec6931a-60d4-4d76-acd1-3c9ec9a6a1b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231492119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.231492119
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1932017918
Short name T760
Test name
Test status
Simulation time 181117552161 ps
CPU time 30.6 seconds
Started May 19 12:30:56 PM PDT 24
Finished May 19 12:31:29 PM PDT 24
Peak memory 200696 kb
Host smart-7b2609ea-a8ac-4eaf-b69f-d12d6e829c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932017918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1932017918
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.296416081
Short name T1096
Test name
Test status
Simulation time 87625500986 ps
CPU time 73.7 seconds
Started May 19 12:31:01 PM PDT 24
Finished May 19 12:32:15 PM PDT 24
Peak memory 200300 kb
Host smart-22f41eb2-e0aa-46f9-83f8-0b340ee04b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296416081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.296416081
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1708543990
Short name T427
Test name
Test status
Simulation time 92583077770 ps
CPU time 182.61 seconds
Started May 19 12:30:59 PM PDT 24
Finished May 19 12:34:03 PM PDT 24
Peak memory 200064 kb
Host smart-7b7cf800-0945-4430-9e7a-d3e3ce512e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708543990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1708543990
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1433583673
Short name T632
Test name
Test status
Simulation time 17234515625 ps
CPU time 12.44 seconds
Started May 19 12:30:56 PM PDT 24
Finished May 19 12:31:11 PM PDT 24
Peak memory 200076 kb
Host smart-0cac1337-c0d1-47f3-928d-3df8f046aa72
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433583673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1433583673
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.4276078721
Short name T1059
Test name
Test status
Simulation time 112967554952 ps
CPU time 773.3 seconds
Started May 19 12:31:01 PM PDT 24
Finished May 19 12:43:56 PM PDT 24
Peak memory 200316 kb
Host smart-c671d24a-91fb-4f79-b8cc-24dc583ab3f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4276078721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.4276078721
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.137607954
Short name T890
Test name
Test status
Simulation time 2760368961 ps
CPU time 5.85 seconds
Started May 19 12:30:58 PM PDT 24
Finished May 19 12:31:06 PM PDT 24
Peak memory 198452 kb
Host smart-f1bdd922-191c-4e96-bd26-66635a4700de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137607954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.137607954
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2590758954
Short name T1159
Test name
Test status
Simulation time 164177831647 ps
CPU time 288.42 seconds
Started May 19 12:30:56 PM PDT 24
Finished May 19 12:35:47 PM PDT 24
Peak memory 200620 kb
Host smart-50ab3464-1773-4f7d-a6bb-181e27d010da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590758954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2590758954
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.440295398
Short name T1097
Test name
Test status
Simulation time 36521788912 ps
CPU time 425.7 seconds
Started May 19 12:31:01 PM PDT 24
Finished May 19 12:38:08 PM PDT 24
Peak memory 200292 kb
Host smart-30f2f106-5e04-4f8d-838c-c3021e6260dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440295398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.440295398
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3489884133
Short name T503
Test name
Test status
Simulation time 4814198218 ps
CPU time 12.04 seconds
Started May 19 12:30:57 PM PDT 24
Finished May 19 12:31:11 PM PDT 24
Peak memory 199028 kb
Host smart-c0b501f2-4b04-453e-8273-01c9854067e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3489884133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3489884133
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1322072868
Short name T343
Test name
Test status
Simulation time 18274106759 ps
CPU time 29.59 seconds
Started May 19 12:31:01 PM PDT 24
Finished May 19 12:31:31 PM PDT 24
Peak memory 200092 kb
Host smart-140ece7d-0adc-432a-967c-b0e273ea71f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322072868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1322072868
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2541801021
Short name T1047
Test name
Test status
Simulation time 40368160049 ps
CPU time 65.14 seconds
Started May 19 12:30:58 PM PDT 24
Finished May 19 12:32:06 PM PDT 24
Peak memory 195936 kb
Host smart-b5fef60f-a9ab-490c-85b3-ae555f72e2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541801021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2541801021
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2216727823
Short name T736
Test name
Test status
Simulation time 256835299 ps
CPU time 1.25 seconds
Started May 19 12:30:59 PM PDT 24
Finished May 19 12:31:02 PM PDT 24
Peak memory 198772 kb
Host smart-296f4166-8754-4e29-baf6-27353cbfb5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216727823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2216727823
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2595464956
Short name T699
Test name
Test status
Simulation time 509150402250 ps
CPU time 125.81 seconds
Started May 19 12:31:00 PM PDT 24
Finished May 19 12:33:07 PM PDT 24
Peak memory 208832 kb
Host smart-5bd9b952-64b7-485b-87d5-9c89e4a32bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595464956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2595464956
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3745354706
Short name T55
Test name
Test status
Simulation time 168145872441 ps
CPU time 1202.97 seconds
Started May 19 12:31:02 PM PDT 24
Finished May 19 12:51:06 PM PDT 24
Peak memory 224988 kb
Host smart-114702c6-8aaf-4520-a83b-504b646d3dc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745354706 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3745354706
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1103180520
Short name T984
Test name
Test status
Simulation time 1962563832 ps
CPU time 1.9 seconds
Started May 19 12:30:56 PM PDT 24
Finished May 19 12:31:00 PM PDT 24
Peak memory 198752 kb
Host smart-08ac054a-7182-4c75-912f-daaa6c37990e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103180520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1103180520
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2859488201
Short name T393
Test name
Test status
Simulation time 36016068749 ps
CPU time 13.92 seconds
Started May 19 12:30:57 PM PDT 24
Finished May 19 12:31:14 PM PDT 24
Peak memory 199440 kb
Host smart-313ed925-0018-4a99-8c03-e6be2603eebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859488201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2859488201
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.215622504
Short name T456
Test name
Test status
Simulation time 45248568 ps
CPU time 0.58 seconds
Started May 19 12:29:15 PM PDT 24
Finished May 19 12:29:16 PM PDT 24
Peak memory 195728 kb
Host smart-5c7b6943-3300-4193-9350-7c3ef9d26d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215622504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.215622504
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1796955971
Short name T772
Test name
Test status
Simulation time 46573870451 ps
CPU time 20.34 seconds
Started May 19 12:29:00 PM PDT 24
Finished May 19 12:29:26 PM PDT 24
Peak memory 200216 kb
Host smart-55fe61a0-f79a-42dc-ba02-e53bca5c44a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796955971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1796955971
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1429635222
Short name T3
Test name
Test status
Simulation time 63087376313 ps
CPU time 24.12 seconds
Started May 19 12:29:22 PM PDT 24
Finished May 19 12:29:47 PM PDT 24
Peak memory 198972 kb
Host smart-bb003e46-47b6-428f-a28b-a5e268091147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429635222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1429635222
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.304046325
Short name T1128
Test name
Test status
Simulation time 41120678192 ps
CPU time 74.6 seconds
Started May 19 12:28:59 PM PDT 24
Finished May 19 12:30:14 PM PDT 24
Peak memory 200340 kb
Host smart-5819c553-a145-4717-8c25-3d51a348dbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304046325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.304046325
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1360512804
Short name T717
Test name
Test status
Simulation time 24150136952 ps
CPU time 8.81 seconds
Started May 19 12:29:16 PM PDT 24
Finished May 19 12:29:26 PM PDT 24
Peak memory 199872 kb
Host smart-6b4d7944-2577-42d8-b44f-915457bf4730
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360512804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1360512804
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.806883465
Short name T1072
Test name
Test status
Simulation time 133524671816 ps
CPU time 1241.02 seconds
Started May 19 12:29:10 PM PDT 24
Finished May 19 12:49:52 PM PDT 24
Peak memory 200328 kb
Host smart-f012893d-1378-492c-9db0-c0d9b377625d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806883465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.806883465
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.5528341
Short name T20
Test name
Test status
Simulation time 9295775460 ps
CPU time 9.62 seconds
Started May 19 12:29:33 PM PDT 24
Finished May 19 12:29:44 PM PDT 24
Peak memory 200228 kb
Host smart-c2eac3ca-484a-4f97-9fb6-b2c5dafbf052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5528341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.5528341
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.4064335748
Short name T670
Test name
Test status
Simulation time 53662815595 ps
CPU time 64.48 seconds
Started May 19 12:29:22 PM PDT 24
Finished May 19 12:30:27 PM PDT 24
Peak memory 200552 kb
Host smart-fafc4658-f7ef-4c31-8f81-99f3f106df2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064335748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.4064335748
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3050321223
Short name T1006
Test name
Test status
Simulation time 21065755241 ps
CPU time 956.22 seconds
Started May 19 12:28:55 PM PDT 24
Finished May 19 12:44:52 PM PDT 24
Peak memory 200276 kb
Host smart-84a6dc67-c017-450c-becc-0e8a3e073415
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3050321223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3050321223
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1776970971
Short name T384
Test name
Test status
Simulation time 6184535123 ps
CPU time 15.14 seconds
Started May 19 12:28:53 PM PDT 24
Finished May 19 12:29:13 PM PDT 24
Peak memory 199560 kb
Host smart-3fee0770-e801-4cd8-9c07-b4e03aa16d5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776970971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1776970971
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3830897550
Short name T272
Test name
Test status
Simulation time 156076217773 ps
CPU time 491.53 seconds
Started May 19 12:29:41 PM PDT 24
Finished May 19 12:37:54 PM PDT 24
Peak memory 200216 kb
Host smart-c838f052-36ef-4bfd-a722-e6f6ba43b8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830897550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3830897550
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1566800463
Short name T553
Test name
Test status
Simulation time 389585511 ps
CPU time 0.96 seconds
Started May 19 12:29:17 PM PDT 24
Finished May 19 12:29:19 PM PDT 24
Peak memory 195668 kb
Host smart-eaf14b4f-6677-41be-b44b-d2389a88357f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566800463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1566800463
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.103941528
Short name T370
Test name
Test status
Simulation time 505900409 ps
CPU time 2.42 seconds
Started May 19 12:29:24 PM PDT 24
Finished May 19 12:29:27 PM PDT 24
Peak memory 199812 kb
Host smart-91dc9c56-98c4-45e3-87a1-f88ead101308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103941528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.103941528
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1610904700
Short name T1099
Test name
Test status
Simulation time 307703913669 ps
CPU time 148.18 seconds
Started May 19 12:28:54 PM PDT 24
Finished May 19 12:31:23 PM PDT 24
Peak memory 200352 kb
Host smart-9f431352-1f4e-4e42-b63e-eef73dac7fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610904700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1610904700
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2664115300
Short name T826
Test name
Test status
Simulation time 165880727364 ps
CPU time 1248 seconds
Started May 19 12:29:26 PM PDT 24
Finished May 19 12:50:15 PM PDT 24
Peak memory 225616 kb
Host smart-4e1d71cc-ddd0-4e93-8cc3-bcd1e7e80c59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664115300 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2664115300
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3639645884
Short name T599
Test name
Test status
Simulation time 2245368509 ps
CPU time 2.2 seconds
Started May 19 12:29:21 PM PDT 24
Finished May 19 12:29:24 PM PDT 24
Peak memory 200284 kb
Host smart-52e567db-0e9a-4000-bd73-a8fce760dd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639645884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3639645884
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2618298209
Short name T1058
Test name
Test status
Simulation time 62884662511 ps
CPU time 30.25 seconds
Started May 19 12:30:01 PM PDT 24
Finished May 19 12:30:39 PM PDT 24
Peak memory 196320 kb
Host smart-c4858c5e-17bb-4906-b381-b8291f4b56f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618298209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2618298209
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2427309173
Short name T243
Test name
Test status
Simulation time 49084187707 ps
CPU time 14.26 seconds
Started May 19 12:30:56 PM PDT 24
Finished May 19 12:31:13 PM PDT 24
Peak memory 200312 kb
Host smart-d0db0449-aae9-4be2-98ba-ec476e7de54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427309173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2427309173
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.4021764170
Short name T1088
Test name
Test status
Simulation time 628373224799 ps
CPU time 918.2 seconds
Started May 19 12:31:01 PM PDT 24
Finished May 19 12:46:20 PM PDT 24
Peak memory 225308 kb
Host smart-7e2d9438-720d-485d-8ac4-9918725bc849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021764170 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.4021764170
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2981002310
Short name T628
Test name
Test status
Simulation time 141117331612 ps
CPU time 30.82 seconds
Started May 19 12:30:56 PM PDT 24
Finished May 19 12:31:30 PM PDT 24
Peak memory 200744 kb
Host smart-d9edba86-f27d-4e43-b754-bb022c9048ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981002310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2981002310
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2680122237
Short name T229
Test name
Test status
Simulation time 75720300090 ps
CPU time 637.26 seconds
Started May 19 12:30:55 PM PDT 24
Finished May 19 12:41:34 PM PDT 24
Peak memory 216708 kb
Host smart-f0d0c89d-11b4-49da-b340-c08bacc2eeeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680122237 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2680122237
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.4218649512
Short name T941
Test name
Test status
Simulation time 65775972004 ps
CPU time 122.8 seconds
Started May 19 12:30:56 PM PDT 24
Finished May 19 12:33:02 PM PDT 24
Peak memory 200372 kb
Host smart-85bbf66c-c9a2-4e66-aab8-29607af85cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218649512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.4218649512
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1664101921
Short name T382
Test name
Test status
Simulation time 19623462972 ps
CPU time 61.06 seconds
Started May 19 12:30:58 PM PDT 24
Finished May 19 12:32:01 PM PDT 24
Peak memory 215960 kb
Host smart-79973fee-cec2-49a3-85ae-62c13fc5a89f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664101921 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1664101921
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.418183276
Short name T416
Test name
Test status
Simulation time 38665666930 ps
CPU time 17.98 seconds
Started May 19 12:31:07 PM PDT 24
Finished May 19 12:31:27 PM PDT 24
Peak memory 200288 kb
Host smart-fff0d347-1faf-418a-965e-64161560f72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418183276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.418183276
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.372125864
Short name T1140
Test name
Test status
Simulation time 80231459327 ps
CPU time 1230.87 seconds
Started May 19 12:31:07 PM PDT 24
Finished May 19 12:51:40 PM PDT 24
Peak memory 216392 kb
Host smart-a4fd3b5c-4e53-41e2-a4b9-d858c6c52a4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372125864 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.372125864
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.720470503
Short name T968
Test name
Test status
Simulation time 11423099330 ps
CPU time 20.24 seconds
Started May 19 12:31:08 PM PDT 24
Finished May 19 12:31:30 PM PDT 24
Peak memory 200320 kb
Host smart-28b765aa-b2fc-40fe-9098-dfd098c0b2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720470503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.720470503
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3080680461
Short name T240
Test name
Test status
Simulation time 167257124402 ps
CPU time 151.67 seconds
Started May 19 12:31:08 PM PDT 24
Finished May 19 12:33:42 PM PDT 24
Peak memory 200316 kb
Host smart-cfeab0cd-a64a-4af6-a20c-6ca2fa75f878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080680461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3080680461
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1745405220
Short name T101
Test name
Test status
Simulation time 34287480821 ps
CPU time 361.81 seconds
Started May 19 12:31:06 PM PDT 24
Finished May 19 12:37:08 PM PDT 24
Peak memory 217108 kb
Host smart-fcfc14e6-7eda-4b61-a5ef-4f2f63bc21ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745405220 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1745405220
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1690238951
Short name T991
Test name
Test status
Simulation time 71198297365 ps
CPU time 29.7 seconds
Started May 19 12:31:04 PM PDT 24
Finished May 19 12:31:34 PM PDT 24
Peak memory 200316 kb
Host smart-1b036c00-5dc8-4b5a-b5d8-f85be391a6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690238951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1690238951
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2618010316
Short name T987
Test name
Test status
Simulation time 285437375905 ps
CPU time 956.05 seconds
Started May 19 12:31:06 PM PDT 24
Finished May 19 12:47:04 PM PDT 24
Peak memory 217228 kb
Host smart-68f7b1ed-1c8d-4463-8d30-d7cc125e8916
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618010316 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2618010316
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2768854713
Short name T797
Test name
Test status
Simulation time 11040177881 ps
CPU time 11.89 seconds
Started May 19 12:31:03 PM PDT 24
Finished May 19 12:31:15 PM PDT 24
Peak memory 200244 kb
Host smart-7d870c7c-224d-4a26-95f0-1a7a3fd61193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768854713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2768854713
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1624030304
Short name T936
Test name
Test status
Simulation time 55268051726 ps
CPU time 434.15 seconds
Started May 19 12:31:02 PM PDT 24
Finished May 19 12:38:17 PM PDT 24
Peak memory 216036 kb
Host smart-45c7e806-e5d7-4620-b9c8-e5d454497cc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624030304 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1624030304
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2642850589
Short name T215
Test name
Test status
Simulation time 39560677175 ps
CPU time 33.09 seconds
Started May 19 12:31:07 PM PDT 24
Finished May 19 12:31:41 PM PDT 24
Peak memory 199864 kb
Host smart-cdefef02-eeaf-45d5-bc40-f54e7c2db926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642850589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2642850589
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2279423345
Short name T1016
Test name
Test status
Simulation time 79255597537 ps
CPU time 1765.84 seconds
Started May 19 12:31:11 PM PDT 24
Finished May 19 01:00:39 PM PDT 24
Peak memory 225396 kb
Host smart-9f1a7a37-3a77-4413-a12a-4ffe155a1aa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279423345 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2279423345
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.673892157
Short name T1063
Test name
Test status
Simulation time 40714868 ps
CPU time 0.55 seconds
Started May 19 12:29:16 PM PDT 24
Finished May 19 12:29:17 PM PDT 24
Peak memory 195672 kb
Host smart-73dc2cec-c136-4552-95be-1828085386ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673892157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.673892157
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.187300027
Short name T291
Test name
Test status
Simulation time 173082738577 ps
CPU time 315.46 seconds
Started May 19 12:29:05 PM PDT 24
Finished May 19 12:34:21 PM PDT 24
Peak memory 200236 kb
Host smart-a1a83240-45d9-412c-bffa-843846918471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187300027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.187300027
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.108309123
Short name T1146
Test name
Test status
Simulation time 143630427348 ps
CPU time 58.02 seconds
Started May 19 12:29:26 PM PDT 24
Finished May 19 12:30:25 PM PDT 24
Peak memory 200304 kb
Host smart-325a32eb-b8e4-40db-b6c7-7a56d6f74e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108309123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.108309123
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.710702602
Short name T200
Test name
Test status
Simulation time 16919199041 ps
CPU time 14.72 seconds
Started May 19 12:29:25 PM PDT 24
Finished May 19 12:29:52 PM PDT 24
Peak memory 200284 kb
Host smart-a9693d25-34f7-443c-8335-c828edaeedb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710702602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.710702602
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1066530536
Short name T326
Test name
Test status
Simulation time 178601014239 ps
CPU time 330.45 seconds
Started May 19 12:28:55 PM PDT 24
Finished May 19 12:34:26 PM PDT 24
Peak memory 200028 kb
Host smart-228f2f59-0718-4d56-b8d5-3e831f421fc4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066530536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1066530536
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2728083154
Short name T621
Test name
Test status
Simulation time 128329136880 ps
CPU time 356.08 seconds
Started May 19 12:29:33 PM PDT 24
Finished May 19 12:35:31 PM PDT 24
Peak memory 200296 kb
Host smart-f4f8ccdf-c4cd-4986-b1e5-c6c8953fc5eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2728083154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2728083154
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1897522645
Short name T448
Test name
Test status
Simulation time 4724728785 ps
CPU time 8.65 seconds
Started May 19 12:29:27 PM PDT 24
Finished May 19 12:29:37 PM PDT 24
Peak memory 198908 kb
Host smart-bc6396d1-0881-4a45-9e4f-095970e017e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897522645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1897522645
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2264753644
Short name T615
Test name
Test status
Simulation time 2272724400 ps
CPU time 2.39 seconds
Started May 19 12:29:23 PM PDT 24
Finished May 19 12:29:26 PM PDT 24
Peak memory 195004 kb
Host smart-ca6fb8e9-94e0-47ba-8c65-9eaac4517168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264753644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2264753644
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1045578410
Short name T1124
Test name
Test status
Simulation time 13703093394 ps
CPU time 684.29 seconds
Started May 19 12:29:27 PM PDT 24
Finished May 19 12:40:52 PM PDT 24
Peak memory 200284 kb
Host smart-7e2b442a-d60e-489c-a031-0027b09ba9bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1045578410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1045578410
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2133574445
Short name T346
Test name
Test status
Simulation time 3590682419 ps
CPU time 18.25 seconds
Started May 19 12:29:21 PM PDT 24
Finished May 19 12:29:40 PM PDT 24
Peak memory 198484 kb
Host smart-3fc585c7-8492-4f7f-b7b4-dbbf6971916e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133574445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2133574445
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2946962688
Short name T532
Test name
Test status
Simulation time 28739867517 ps
CPU time 52.1 seconds
Started May 19 12:28:53 PM PDT 24
Finished May 19 12:29:46 PM PDT 24
Peak memory 200244 kb
Host smart-6a9b884d-d5ec-4e7e-ac28-7f067a9ba3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946962688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2946962688
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1515144695
Short name T1167
Test name
Test status
Simulation time 1242735599 ps
CPU time 2.53 seconds
Started May 19 12:29:34 PM PDT 24
Finished May 19 12:29:40 PM PDT 24
Peak memory 195580 kb
Host smart-b61712e6-b2b0-4eea-8bbc-b3c43980fdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515144695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1515144695
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3830941082
Short name T468
Test name
Test status
Simulation time 666945540 ps
CPU time 3.66 seconds
Started May 19 12:29:21 PM PDT 24
Finished May 19 12:29:25 PM PDT 24
Peak memory 199100 kb
Host smart-630ad04c-0cf7-43b8-b1d6-dcf0da9897ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830941082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3830941082
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2097900719
Short name T493
Test name
Test status
Simulation time 976837359 ps
CPU time 2.37 seconds
Started May 19 12:29:09 PM PDT 24
Finished May 19 12:29:11 PM PDT 24
Peak memory 199836 kb
Host smart-940db08d-b510-4c10-9106-97c5b5f10ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097900719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2097900719
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3978505793
Short name T333
Test name
Test status
Simulation time 14929890519 ps
CPU time 7.1 seconds
Started May 19 12:29:18 PM PDT 24
Finished May 19 12:29:37 PM PDT 24
Peak memory 197768 kb
Host smart-0fb205b5-f12f-4bb8-ae86-d1bb9a8b4f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978505793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3978505793
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.585761721
Short name T638
Test name
Test status
Simulation time 13453889723 ps
CPU time 11.7 seconds
Started May 19 12:31:11 PM PDT 24
Finished May 19 12:31:24 PM PDT 24
Peak memory 200128 kb
Host smart-cf241502-6403-4295-b5a9-adce048b07b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585761721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.585761721
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.4078325922
Short name T109
Test name
Test status
Simulation time 36260826133 ps
CPU time 641.8 seconds
Started May 19 12:31:08 PM PDT 24
Finished May 19 12:41:51 PM PDT 24
Peak memory 216996 kb
Host smart-c75839c2-2d8a-4e13-8d9e-3f69fccd2802
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078325922 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.4078325922
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2694514641
Short name T389
Test name
Test status
Simulation time 29031930530 ps
CPU time 11.66 seconds
Started May 19 12:31:05 PM PDT 24
Finished May 19 12:31:17 PM PDT 24
Peak memory 200016 kb
Host smart-62aa1bc7-2739-4aba-8ff1-863ebfe50760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694514641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2694514641
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3495912285
Short name T641
Test name
Test status
Simulation time 44982576568 ps
CPU time 93.18 seconds
Started May 19 12:31:10 PM PDT 24
Finished May 19 12:32:45 PM PDT 24
Peak memory 200268 kb
Host smart-0ff7d4c2-b85f-49ec-8593-0702c018e983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495912285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3495912285
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3743409540
Short name T57
Test name
Test status
Simulation time 24911624926 ps
CPU time 199.57 seconds
Started May 19 12:31:04 PM PDT 24
Finished May 19 12:34:25 PM PDT 24
Peak memory 216940 kb
Host smart-8f41c59f-072c-4e34-a647-82a1a6f9b545
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743409540 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3743409540
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3168119524
Short name T449
Test name
Test status
Simulation time 13743562277 ps
CPU time 21.06 seconds
Started May 19 12:31:06 PM PDT 24
Finished May 19 12:31:29 PM PDT 24
Peak memory 200276 kb
Host smart-7b457143-e3c2-4cf0-92e5-35bf861ab2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168119524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3168119524
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1054228183
Short name T140
Test name
Test status
Simulation time 240215387336 ps
CPU time 609.68 seconds
Started May 19 12:31:02 PM PDT 24
Finished May 19 12:41:13 PM PDT 24
Peak memory 216776 kb
Host smart-e8fb050b-f64d-40e7-8ba1-c00601804a07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054228183 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1054228183
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.457250642
Short name T606
Test name
Test status
Simulation time 104231272343 ps
CPU time 40.7 seconds
Started May 19 12:31:04 PM PDT 24
Finished May 19 12:31:46 PM PDT 24
Peak memory 199776 kb
Host smart-67c38e12-07d7-4af3-beba-68026df9e214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457250642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.457250642
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.811444515
Short name T813
Test name
Test status
Simulation time 42482455157 ps
CPU time 462.51 seconds
Started May 19 12:31:11 PM PDT 24
Finished May 19 12:38:56 PM PDT 24
Peak memory 216776 kb
Host smart-03d7860d-518e-42ee-b217-a7cadc6b9867
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811444515 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.811444515
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.76138963
Short name T1039
Test name
Test status
Simulation time 86684365951 ps
CPU time 35.4 seconds
Started May 19 12:31:03 PM PDT 24
Finished May 19 12:31:39 PM PDT 24
Peak memory 200284 kb
Host smart-fc5f1f24-cbbf-4999-b6ca-bc780f986ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76138963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.76138963
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.671853085
Short name T558
Test name
Test status
Simulation time 93368174352 ps
CPU time 1387.48 seconds
Started May 19 12:31:05 PM PDT 24
Finished May 19 12:54:13 PM PDT 24
Peak memory 219904 kb
Host smart-7983e69b-35b9-4c8e-898d-7dcab3c61f15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671853085 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.671853085
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2078167787
Short name T956
Test name
Test status
Simulation time 253427110367 ps
CPU time 59.41 seconds
Started May 19 12:31:07 PM PDT 24
Finished May 19 12:32:08 PM PDT 24
Peak memory 200220 kb
Host smart-b84f6867-5ed4-4506-ab62-bc8321b94dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078167787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2078167787
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3511487832
Short name T60
Test name
Test status
Simulation time 68136307264 ps
CPU time 469.9 seconds
Started May 19 12:31:07 PM PDT 24
Finished May 19 12:38:59 PM PDT 24
Peak memory 216708 kb
Host smart-0d0e5eff-626b-4290-8970-06bb82829559
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511487832 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3511487832
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3409601453
Short name T550
Test name
Test status
Simulation time 195838174732 ps
CPU time 82.07 seconds
Started May 19 12:31:06 PM PDT 24
Finished May 19 12:32:30 PM PDT 24
Peak memory 200304 kb
Host smart-3ff8b830-ad14-4a2e-992b-00e5647ca864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409601453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3409601453
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3993932445
Short name T649
Test name
Test status
Simulation time 24821930120 ps
CPU time 203.22 seconds
Started May 19 12:31:10 PM PDT 24
Finished May 19 12:34:35 PM PDT 24
Peak memory 216516 kb
Host smart-1d92c8c3-4565-4dc7-a480-d0a79f7e37a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993932445 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3993932445
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3305553976
Short name T993
Test name
Test status
Simulation time 124595005126 ps
CPU time 16.97 seconds
Started May 19 12:31:07 PM PDT 24
Finished May 19 12:31:25 PM PDT 24
Peak memory 199848 kb
Host smart-adbb1341-090b-42c6-b7ee-b1730b9b064a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305553976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3305553976
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3783997563
Short name T165
Test name
Test status
Simulation time 14909110014 ps
CPU time 29.03 seconds
Started May 19 12:31:08 PM PDT 24
Finished May 19 12:31:39 PM PDT 24
Peak memory 200288 kb
Host smart-034a9341-2df9-45df-9551-9fda911a06df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783997563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3783997563
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.169477070
Short name T575
Test name
Test status
Simulation time 24100059468 ps
CPU time 145.83 seconds
Started May 19 12:31:03 PM PDT 24
Finished May 19 12:33:30 PM PDT 24
Peak memory 216560 kb
Host smart-47095f7a-b306-4c38-8a58-e532139c0c6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169477070 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.169477070
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2455741191
Short name T841
Test name
Test status
Simulation time 13332212 ps
CPU time 0.56 seconds
Started May 19 12:29:21 PM PDT 24
Finished May 19 12:29:23 PM PDT 24
Peak memory 195700 kb
Host smart-4857e23d-cc98-4024-82b8-b8c487c6f30b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455741191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2455741191
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.759081156
Short name T45
Test name
Test status
Simulation time 78217831955 ps
CPU time 132.56 seconds
Started May 19 12:29:01 PM PDT 24
Finished May 19 12:31:14 PM PDT 24
Peak memory 200304 kb
Host smart-345774b1-a0c6-4206-ade9-105cec2f2131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759081156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.759081156
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2102453875
Short name T410
Test name
Test status
Simulation time 45810589665 ps
CPU time 70.55 seconds
Started May 19 12:29:09 PM PDT 24
Finished May 19 12:30:20 PM PDT 24
Peak memory 200064 kb
Host smart-04c877d2-554d-4030-a945-d17a485d3c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102453875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2102453875
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3988014387
Short name T958
Test name
Test status
Simulation time 29176758501 ps
CPU time 12.95 seconds
Started May 19 12:28:54 PM PDT 24
Finished May 19 12:29:07 PM PDT 24
Peak memory 200360 kb
Host smart-a198a295-fc83-4fd0-b231-088a3b2f6ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988014387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3988014387
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2878640763
Short name T541
Test name
Test status
Simulation time 153060434568 ps
CPU time 75.45 seconds
Started May 19 12:29:17 PM PDT 24
Finished May 19 12:30:34 PM PDT 24
Peak memory 196420 kb
Host smart-26d3b4fe-ed70-494b-a9d4-4eeb7170d626
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878640763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2878640763
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1313560019
Short name T631
Test name
Test status
Simulation time 39183364243 ps
CPU time 255.4 seconds
Started May 19 12:29:06 PM PDT 24
Finished May 19 12:33:22 PM PDT 24
Peak memory 200208 kb
Host smart-87f4b366-1291-4ec7-92c2-f4cf9024ae2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313560019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1313560019
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2458330859
Short name T629
Test name
Test status
Simulation time 1198977713 ps
CPU time 2.6 seconds
Started May 19 12:29:16 PM PDT 24
Finished May 19 12:29:20 PM PDT 24
Peak memory 195764 kb
Host smart-c684f654-0927-4fcf-98b0-074faa097ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458330859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2458330859
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.4249445146
Short name T779
Test name
Test status
Simulation time 75541571368 ps
CPU time 69.1 seconds
Started May 19 12:29:20 PM PDT 24
Finished May 19 12:30:30 PM PDT 24
Peak memory 208456 kb
Host smart-e211a7c7-9ea4-44b3-a6e2-2147a7ca1519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249445146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.4249445146
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2048488390
Short name T1121
Test name
Test status
Simulation time 12668774842 ps
CPU time 733.02 seconds
Started May 19 12:28:55 PM PDT 24
Finished May 19 12:41:09 PM PDT 24
Peak memory 200284 kb
Host smart-0451cc6f-8d69-41ad-b9bd-67c9884a58db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2048488390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2048488390
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.734871977
Short name T872
Test name
Test status
Simulation time 6071576637 ps
CPU time 54.62 seconds
Started May 19 12:29:17 PM PDT 24
Finished May 19 12:30:18 PM PDT 24
Peak memory 199672 kb
Host smart-3f44bb38-e834-4f18-b324-0f7da133feb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=734871977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.734871977
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.281749665
Short name T404
Test name
Test status
Simulation time 70043773066 ps
CPU time 115.26 seconds
Started May 19 12:29:18 PM PDT 24
Finished May 19 12:31:15 PM PDT 24
Peak memory 200280 kb
Host smart-5a9ed08f-fbe7-4ca5-bfc7-a64ecc2b1c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281749665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.281749665
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3231058800
Short name T829
Test name
Test status
Simulation time 38444092370 ps
CPU time 14.54 seconds
Started May 19 12:29:51 PM PDT 24
Finished May 19 12:30:13 PM PDT 24
Peak memory 196300 kb
Host smart-6a9c084a-b5a9-4812-85c5-4fc5a94e6570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231058800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3231058800
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1878518827
Short name T751
Test name
Test status
Simulation time 5354545818 ps
CPU time 11.21 seconds
Started May 19 12:28:59 PM PDT 24
Finished May 19 12:29:10 PM PDT 24
Peak memory 200436 kb
Host smart-04a4dd71-3f6a-4cfa-8c62-e97e14d57092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878518827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1878518827
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.808543250
Short name T765
Test name
Test status
Simulation time 233368999404 ps
CPU time 2326.19 seconds
Started May 19 12:29:18 PM PDT 24
Finished May 19 01:08:06 PM PDT 24
Peak memory 208808 kb
Host smart-2ea20496-dc84-4299-847c-090649ba1e77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808543250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.808543250
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3981949421
Short name T707
Test name
Test status
Simulation time 53420976792 ps
CPU time 747.01 seconds
Started May 19 12:29:35 PM PDT 24
Finished May 19 12:42:05 PM PDT 24
Peak memory 215144 kb
Host smart-2ded75a4-beb4-47c9-a916-8339371f3989
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981949421 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3981949421
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3873195434
Short name T436
Test name
Test status
Simulation time 1440471474 ps
CPU time 1.93 seconds
Started May 19 12:28:57 PM PDT 24
Finished May 19 12:28:59 PM PDT 24
Peak memory 200032 kb
Host smart-02e01368-e69e-48d7-a08d-155c283bbda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873195434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3873195434
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.4083401764
Short name T38
Test name
Test status
Simulation time 3358070423 ps
CPU time 1.26 seconds
Started May 19 12:29:18 PM PDT 24
Finished May 19 12:29:20 PM PDT 24
Peak memory 198460 kb
Host smart-733d780b-135a-442c-821c-ee3016ee942b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083401764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.4083401764
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.718550385
Short name T462
Test name
Test status
Simulation time 90540432843 ps
CPU time 41.04 seconds
Started May 19 12:31:04 PM PDT 24
Finished May 19 12:31:46 PM PDT 24
Peak memory 200348 kb
Host smart-d7568fa6-16af-4240-9631-fac940208249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718550385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.718550385
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3786803421
Short name T320
Test name
Test status
Simulation time 437462219006 ps
CPU time 583.74 seconds
Started May 19 12:31:09 PM PDT 24
Finished May 19 12:40:55 PM PDT 24
Peak memory 216800 kb
Host smart-3103a3bb-40e9-47af-9ece-9bd1a8334851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786803421 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3786803421
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2088814781
Short name T180
Test name
Test status
Simulation time 14145566807 ps
CPU time 24.32 seconds
Started May 19 12:31:03 PM PDT 24
Finished May 19 12:31:28 PM PDT 24
Peak memory 200008 kb
Host smart-6fb6c54e-4bb5-49bf-8307-aa1e8feb638c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088814781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2088814781
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1915746337
Short name T273
Test name
Test status
Simulation time 82795114005 ps
CPU time 324.93 seconds
Started May 19 12:31:06 PM PDT 24
Finished May 19 12:36:32 PM PDT 24
Peak memory 216728 kb
Host smart-050c13a1-ff1a-43d8-91f4-c237368ba6c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915746337 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1915746337
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3830915301
Short name T849
Test name
Test status
Simulation time 144402491023 ps
CPU time 43.94 seconds
Started May 19 12:31:05 PM PDT 24
Finished May 19 12:31:49 PM PDT 24
Peak memory 200236 kb
Host smart-06c9945b-53f3-40e7-9508-19e1022fc0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830915301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3830915301
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2667009566
Short name T773
Test name
Test status
Simulation time 31298586315 ps
CPU time 227.63 seconds
Started May 19 12:31:03 PM PDT 24
Finished May 19 12:34:52 PM PDT 24
Peak memory 216536 kb
Host smart-24de0530-b84f-4cf1-b1b7-08314652af28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667009566 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2667009566
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1797314381
Short name T1037
Test name
Test status
Simulation time 126033440225 ps
CPU time 89.9 seconds
Started May 19 12:31:10 PM PDT 24
Finished May 19 12:32:42 PM PDT 24
Peak memory 200240 kb
Host smart-0aef8124-dbf4-41d2-b298-415926f7b769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797314381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1797314381
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3008677296
Short name T737
Test name
Test status
Simulation time 61140185004 ps
CPU time 653.42 seconds
Started May 19 12:31:03 PM PDT 24
Finished May 19 12:41:58 PM PDT 24
Peak memory 217204 kb
Host smart-b8ca6e94-328f-42e5-a4fb-47175dbda595
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008677296 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3008677296
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1568354467
Short name T286
Test name
Test status
Simulation time 12049078677 ps
CPU time 14.48 seconds
Started May 19 12:31:11 PM PDT 24
Finished May 19 12:31:27 PM PDT 24
Peak memory 200300 kb
Host smart-2fe0d508-1e19-46da-b692-8e0af2c8a13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568354467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1568354467
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3780821245
Short name T653
Test name
Test status
Simulation time 64493556621 ps
CPU time 104.58 seconds
Started May 19 12:31:07 PM PDT 24
Finished May 19 12:32:53 PM PDT 24
Peak memory 200268 kb
Host smart-a88408d3-4278-4c24-9c3e-b83658089e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780821245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3780821245
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.533301322
Short name T222
Test name
Test status
Simulation time 10993075376 ps
CPU time 17.79 seconds
Started May 19 12:31:08 PM PDT 24
Finished May 19 12:31:28 PM PDT 24
Peak memory 200308 kb
Host smart-6bd81454-f050-45dd-aa70-6d7ad3a16dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533301322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.533301322
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2994628788
Short name T656
Test name
Test status
Simulation time 166184639515 ps
CPU time 599.22 seconds
Started May 19 12:31:08 PM PDT 24
Finished May 19 12:41:09 PM PDT 24
Peak memory 217132 kb
Host smart-df7ea8d0-563c-4d0a-a782-4985c6c22f23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994628788 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2994628788
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2498946137
Short name T195
Test name
Test status
Simulation time 143922648976 ps
CPU time 229.22 seconds
Started May 19 12:31:08 PM PDT 24
Finished May 19 12:34:59 PM PDT 24
Peak memory 200724 kb
Host smart-ad57cbfd-8c05-4d20-9f86-9f428d2692f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498946137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2498946137
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1916641312
Short name T581
Test name
Test status
Simulation time 78055252268 ps
CPU time 350.99 seconds
Started May 19 12:31:09 PM PDT 24
Finished May 19 12:37:02 PM PDT 24
Peak memory 209576 kb
Host smart-993fa164-37dc-4180-99e0-d6d47e1bce2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916641312 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1916641312
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.4085995297
Short name T906
Test name
Test status
Simulation time 61445256949 ps
CPU time 31.81 seconds
Started May 19 12:31:08 PM PDT 24
Finished May 19 12:31:42 PM PDT 24
Peak memory 200296 kb
Host smart-9c2926df-2948-4be8-8d7a-794fa099f2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085995297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.4085995297
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.924982042
Short name T177
Test name
Test status
Simulation time 1192501485042 ps
CPU time 1786.15 seconds
Started May 19 12:31:15 PM PDT 24
Finished May 19 01:01:03 PM PDT 24
Peak memory 241776 kb
Host smart-5ac7a10f-58f7-4c15-9cb1-eedbac7bb3d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924982042 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.924982042
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2017577795
Short name T347
Test name
Test status
Simulation time 20276909 ps
CPU time 0.54 seconds
Started May 19 12:29:28 PM PDT 24
Finished May 19 12:29:30 PM PDT 24
Peak memory 195604 kb
Host smart-7c013a45-7096-4323-b1de-fd00b5bc59ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017577795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2017577795
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2882471297
Short name T251
Test name
Test status
Simulation time 19667733526 ps
CPU time 37.96 seconds
Started May 19 12:29:34 PM PDT 24
Finished May 19 12:30:15 PM PDT 24
Peak memory 200272 kb
Host smart-786b3e13-3efa-415f-999e-34b559cc88a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882471297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2882471297
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.592199409
Short name T942
Test name
Test status
Simulation time 55667298384 ps
CPU time 81.11 seconds
Started May 19 12:29:31 PM PDT 24
Finished May 19 12:30:54 PM PDT 24
Peak memory 200188 kb
Host smart-441de7a4-0696-47f1-a27e-30fd9ef12c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592199409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.592199409
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.196745886
Short name T570
Test name
Test status
Simulation time 114257093022 ps
CPU time 467.14 seconds
Started May 19 12:29:31 PM PDT 24
Finished May 19 12:37:21 PM PDT 24
Peak memory 200228 kb
Host smart-27315ad8-87f8-4c50-a8ca-fe6c58b19839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196745886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.196745886
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3922835015
Short name T407
Test name
Test status
Simulation time 32126936470 ps
CPU time 35.95 seconds
Started May 19 12:29:25 PM PDT 24
Finished May 19 12:30:01 PM PDT 24
Peak memory 198840 kb
Host smart-1b791d30-2dd4-4258-9917-8b3c75628c3b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922835015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3922835015
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2677201545
Short name T616
Test name
Test status
Simulation time 131891281480 ps
CPU time 968.37 seconds
Started May 19 12:29:19 PM PDT 24
Finished May 19 12:45:28 PM PDT 24
Peak memory 200720 kb
Host smart-464a939e-163d-4a0c-91b0-451f5c7b4c6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2677201545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2677201545
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1836654302
Short name T383
Test name
Test status
Simulation time 8074689935 ps
CPU time 9.93 seconds
Started May 19 12:29:25 PM PDT 24
Finished May 19 12:29:36 PM PDT 24
Peak memory 199876 kb
Host smart-ad4bcbc8-7c8d-41b7-af9f-49199bcd87a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836654302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1836654302
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3665941368
Short name T330
Test name
Test status
Simulation time 247086351047 ps
CPU time 65.01 seconds
Started May 19 12:29:29 PM PDT 24
Finished May 19 12:30:35 PM PDT 24
Peak memory 200868 kb
Host smart-491c5988-cbc9-4d2f-be73-a4e1d8a9f1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665941368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3665941368
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.765881081
Short name T1073
Test name
Test status
Simulation time 22726537678 ps
CPU time 1197.05 seconds
Started May 19 12:29:25 PM PDT 24
Finished May 19 12:49:23 PM PDT 24
Peak memory 200308 kb
Host smart-fcc18ee3-39c2-4f4b-b49b-fd13303d96f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=765881081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.765881081
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.4103415723
Short name T1052
Test name
Test status
Simulation time 3909318296 ps
CPU time 8.21 seconds
Started May 19 12:29:30 PM PDT 24
Finished May 19 12:29:40 PM PDT 24
Peak memory 198376 kb
Host smart-46f8ec81-4f98-447c-a023-17f1ff8edc53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4103415723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.4103415723
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2645092879
Short name T916
Test name
Test status
Simulation time 11887193690 ps
CPU time 20.71 seconds
Started May 19 12:29:16 PM PDT 24
Finished May 19 12:29:37 PM PDT 24
Peak memory 200164 kb
Host smart-80506ca8-7882-4d11-b426-22a94ca464af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645092879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2645092879
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1099995472
Short name T364
Test name
Test status
Simulation time 1594007359 ps
CPU time 3.14 seconds
Started May 19 12:29:29 PM PDT 24
Finished May 19 12:29:34 PM PDT 24
Peak memory 195668 kb
Host smart-d2f214af-fbad-4742-bd44-0d419680aa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099995472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1099995472
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.587265137
Short name T605
Test name
Test status
Simulation time 103041061 ps
CPU time 1.13 seconds
Started May 19 12:29:14 PM PDT 24
Finished May 19 12:29:16 PM PDT 24
Peak memory 198416 kb
Host smart-edbc4b72-c17a-4a2f-bea9-78fa4e786300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587265137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.587265137
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.342966724
Short name T1149
Test name
Test status
Simulation time 104770777021 ps
CPU time 546.36 seconds
Started May 19 12:29:22 PM PDT 24
Finished May 19 12:38:29 PM PDT 24
Peak memory 229468 kb
Host smart-5a8ad4db-1c63-475b-808c-639e9e2d8690
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342966724 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.342966724
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3383301699
Short name T952
Test name
Test status
Simulation time 939138751 ps
CPU time 4.05 seconds
Started May 19 12:29:33 PM PDT 24
Finished May 19 12:29:40 PM PDT 24
Peak memory 200544 kb
Host smart-ffd24bfc-059a-428f-bbd7-1cdfe516f60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383301699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3383301699
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2765216840
Short name T871
Test name
Test status
Simulation time 56632176296 ps
CPU time 68.11 seconds
Started May 19 12:29:32 PM PDT 24
Finished May 19 12:30:42 PM PDT 24
Peak memory 200292 kb
Host smart-9ae0eebb-d4c0-48f7-84a2-f879337a35ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765216840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2765216840
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2426022384
Short name T342
Test name
Test status
Simulation time 91960695978 ps
CPU time 44.96 seconds
Started May 19 12:31:14 PM PDT 24
Finished May 19 12:32:00 PM PDT 24
Peak memory 200376 kb
Host smart-c20abc92-1568-4a94-a01e-d9543a18931b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426022384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2426022384
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1525935302
Short name T312
Test name
Test status
Simulation time 196646485632 ps
CPU time 503.66 seconds
Started May 19 12:31:07 PM PDT 24
Finished May 19 12:39:33 PM PDT 24
Peak memory 225312 kb
Host smart-265e8ca4-b96c-4312-9727-96e5349c9f93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525935302 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1525935302
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1348216722
Short name T729
Test name
Test status
Simulation time 33445346095 ps
CPU time 14.66 seconds
Started May 19 12:31:15 PM PDT 24
Finished May 19 12:31:31 PM PDT 24
Peak memory 200344 kb
Host smart-7f52bcf1-ab97-4ecf-b345-6822372b86f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348216722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1348216722
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2620691259
Short name T166
Test name
Test status
Simulation time 336909324323 ps
CPU time 425.71 seconds
Started May 19 12:31:08 PM PDT 24
Finished May 19 12:38:15 PM PDT 24
Peak memory 227060 kb
Host smart-53ff3f0e-3ae8-4039-8c5f-9489fce25a55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620691259 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2620691259
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2549654001
Short name T994
Test name
Test status
Simulation time 85257675908 ps
CPU time 80.6 seconds
Started May 19 12:31:08 PM PDT 24
Finished May 19 12:32:31 PM PDT 24
Peak memory 200304 kb
Host smart-05e13cce-2273-4b27-9c6c-5a806fd79941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549654001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2549654001
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.321388565
Short name T173
Test name
Test status
Simulation time 199878803231 ps
CPU time 550.54 seconds
Started May 19 12:31:07 PM PDT 24
Finished May 19 12:40:20 PM PDT 24
Peak memory 226952 kb
Host smart-ba25819a-1613-43aa-89e4-5455f73e1b05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321388565 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.321388565
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.235085671
Short name T935
Test name
Test status
Simulation time 75010602975 ps
CPU time 35.78 seconds
Started May 19 12:31:11 PM PDT 24
Finished May 19 12:31:49 PM PDT 24
Peak memory 200292 kb
Host smart-8f2d2ec6-48f6-40a9-b43d-f9d609a7c9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235085671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.235085671
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.605950811
Short name T21
Test name
Test status
Simulation time 176954426979 ps
CPU time 560.65 seconds
Started May 19 12:31:14 PM PDT 24
Finished May 19 12:40:36 PM PDT 24
Peak memory 225312 kb
Host smart-7e760296-bd9e-4fca-8f31-5367af65dfa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605950811 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.605950811
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3469250192
Short name T395
Test name
Test status
Simulation time 26218156915 ps
CPU time 41.47 seconds
Started May 19 12:31:06 PM PDT 24
Finished May 19 12:31:49 PM PDT 24
Peak memory 200216 kb
Host smart-f888e1b9-00af-40ff-bf2b-f1da520295a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469250192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3469250192
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3893314069
Short name T955
Test name
Test status
Simulation time 83634179083 ps
CPU time 497.66 seconds
Started May 19 12:31:16 PM PDT 24
Finished May 19 12:39:35 PM PDT 24
Peak memory 217040 kb
Host smart-23c4a217-5742-40c4-8755-86eafaae78ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893314069 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3893314069
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1669688531
Short name T614
Test name
Test status
Simulation time 38329922788 ps
CPU time 18.79 seconds
Started May 19 12:31:11 PM PDT 24
Finished May 19 12:31:31 PM PDT 24
Peak memory 200284 kb
Host smart-3b51a051-fd93-4990-b9e4-99e45793fdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669688531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1669688531
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1873963872
Short name T63
Test name
Test status
Simulation time 68703897106 ps
CPU time 509.13 seconds
Started May 19 12:31:10 PM PDT 24
Finished May 19 12:39:41 PM PDT 24
Peak memory 217008 kb
Host smart-b7a4132f-3dfa-42e9-b04c-b9761e5611c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873963872 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1873963872
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1303462252
Short name T743
Test name
Test status
Simulation time 40357157623 ps
CPU time 28.32 seconds
Started May 19 12:31:10 PM PDT 24
Finished May 19 12:31:40 PM PDT 24
Peak memory 200280 kb
Host smart-7971aea2-8b82-4efa-8286-b1b3ece14fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303462252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1303462252
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.283677380
Short name T1040
Test name
Test status
Simulation time 47791151901 ps
CPU time 615.77 seconds
Started May 19 12:31:08 PM PDT 24
Finished May 19 12:41:26 PM PDT 24
Peak memory 225304 kb
Host smart-9efa77cf-314e-4707-8767-00037a3c95b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283677380 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.283677380
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1327560622
Short name T1080
Test name
Test status
Simulation time 22953795192 ps
CPU time 37.83 seconds
Started May 19 12:31:06 PM PDT 24
Finished May 19 12:31:45 PM PDT 24
Peak memory 200304 kb
Host smart-f2a0af6f-432f-4af8-b0aa-bc522dfb72b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327560622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1327560622
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.687460000
Short name T106
Test name
Test status
Simulation time 29170147210 ps
CPU time 315.29 seconds
Started May 19 12:31:11 PM PDT 24
Finished May 19 12:36:28 PM PDT 24
Peak memory 215924 kb
Host smart-8501eeac-edb7-4c5a-8983-07253aa76582
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687460000 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.687460000
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.44212643
Short name T654
Test name
Test status
Simulation time 86432399226 ps
CPU time 78.18 seconds
Started May 19 12:31:11 PM PDT 24
Finished May 19 12:32:31 PM PDT 24
Peak memory 200372 kb
Host smart-92fcae41-a422-45ae-8e7e-776a49cabdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44212643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.44212643
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3893812797
Short name T1078
Test name
Test status
Simulation time 53221390680 ps
CPU time 652.08 seconds
Started May 19 12:31:08 PM PDT 24
Finished May 19 12:42:01 PM PDT 24
Peak memory 216988 kb
Host smart-a3336ce9-89fd-4b2f-9435-44792fc8ad46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893812797 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3893812797
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.381871
Short name T131
Test name
Test status
Simulation time 157205355349 ps
CPU time 94.71 seconds
Started May 19 12:31:10 PM PDT 24
Finished May 19 12:32:47 PM PDT 24
Peak memory 200292 kb
Host smart-8f270d7d-40d7-461f-8e9a-579ba1dd4fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.381871
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.190670105
Short name T58
Test name
Test status
Simulation time 100752821774 ps
CPU time 1548.29 seconds
Started May 19 12:31:14 PM PDT 24
Finished May 19 12:57:04 PM PDT 24
Peak memory 216788 kb
Host smart-6b383502-0a3d-4b26-9441-c6a6ff4676c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190670105 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.190670105
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.284762719
Short name T971
Test name
Test status
Simulation time 15971437 ps
CPU time 0.57 seconds
Started May 19 12:29:28 PM PDT 24
Finished May 19 12:29:30 PM PDT 24
Peak memory 196052 kb
Host smart-ce2f9ac3-f661-4fc7-b111-e6252220e319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284762719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.284762719
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2476602670
Short name T515
Test name
Test status
Simulation time 29816617953 ps
CPU time 26.36 seconds
Started May 19 12:29:25 PM PDT 24
Finished May 19 12:29:52 PM PDT 24
Peak memory 200208 kb
Host smart-90a08b06-bd90-4944-9aed-db4ae5fd4022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476602670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2476602670
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1761256889
Short name T914
Test name
Test status
Simulation time 42520011520 ps
CPU time 77.44 seconds
Started May 19 12:29:29 PM PDT 24
Finished May 19 12:30:47 PM PDT 24
Peak memory 200280 kb
Host smart-05f8e80f-1567-4ca6-9924-4f2517bc7c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761256889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1761256889
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2006083240
Short name T695
Test name
Test status
Simulation time 112141544831 ps
CPU time 50.88 seconds
Started May 19 12:29:19 PM PDT 24
Finished May 19 12:30:11 PM PDT 24
Peak memory 200200 kb
Host smart-acb3eee8-642b-40de-893c-dbc88a6ed932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006083240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2006083240
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3501412163
Short name T857
Test name
Test status
Simulation time 4608676531 ps
CPU time 1.66 seconds
Started May 19 12:29:13 PM PDT 24
Finished May 19 12:29:16 PM PDT 24
Peak memory 197052 kb
Host smart-3153cb43-3adf-40ff-a8c1-50d6a465fa7f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501412163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3501412163
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2819725455
Short name T277
Test name
Test status
Simulation time 78801862748 ps
CPU time 430.8 seconds
Started May 19 12:29:24 PM PDT 24
Finished May 19 12:36:36 PM PDT 24
Peak memory 200260 kb
Host smart-9b9e0861-84f0-4a7e-90e0-9b5700e61355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2819725455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2819725455
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2960433251
Short name T1153
Test name
Test status
Simulation time 3414551536 ps
CPU time 3.36 seconds
Started May 19 12:29:30 PM PDT 24
Finished May 19 12:29:35 PM PDT 24
Peak memory 196868 kb
Host smart-d7302eee-87c9-4e86-bfbb-20fbadde6367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960433251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2960433251
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.822149859
Short name T403
Test name
Test status
Simulation time 74309897415 ps
CPU time 25.2 seconds
Started May 19 12:29:31 PM PDT 24
Finished May 19 12:29:58 PM PDT 24
Peak memory 198720 kb
Host smart-e362bc85-1a2c-4b88-92f2-67eca89606ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822149859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.822149859
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3094034225
Short name T1048
Test name
Test status
Simulation time 15551263104 ps
CPU time 407.08 seconds
Started May 19 12:29:16 PM PDT 24
Finished May 19 12:36:10 PM PDT 24
Peak memory 200316 kb
Host smart-b03696e7-433a-4db2-b0cb-7468d8a6d1e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3094034225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3094034225
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1047619729
Short name T7
Test name
Test status
Simulation time 6404798809 ps
CPU time 54.68 seconds
Started May 19 12:29:31 PM PDT 24
Finished May 19 12:30:27 PM PDT 24
Peak memory 198432 kb
Host smart-0b1f116e-4aee-4fe5-8f8d-6756d62e5851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1047619729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1047619729
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1268867413
Short name T899
Test name
Test status
Simulation time 181945848126 ps
CPU time 44.49 seconds
Started May 19 12:29:18 PM PDT 24
Finished May 19 12:30:04 PM PDT 24
Peak memory 200288 kb
Host smart-ab117d6a-42e1-451c-aba2-d98d0452aa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268867413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1268867413
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3353072280
Short name T423
Test name
Test status
Simulation time 2917115402 ps
CPU time 5.68 seconds
Started May 19 12:29:24 PM PDT 24
Finished May 19 12:29:31 PM PDT 24
Peak memory 196076 kb
Host smart-4c5872d2-c01e-4409-8c60-55bf3d03828c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353072280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3353072280
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.489134209
Short name T315
Test name
Test status
Simulation time 432094410 ps
CPU time 1.86 seconds
Started May 19 12:29:29 PM PDT 24
Finished May 19 12:29:33 PM PDT 24
Peak memory 198948 kb
Host smart-f7e67bf2-da3e-4e4d-9051-2e9bd3b0bb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489134209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.489134209
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1241317938
Short name T1089
Test name
Test status
Simulation time 167451308864 ps
CPU time 652.78 seconds
Started May 19 12:29:40 PM PDT 24
Finished May 19 12:40:35 PM PDT 24
Peak memory 200264 kb
Host smart-6f05c473-7434-4987-b5f0-b0a5d9765d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241317938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1241317938
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2053767784
Short name T64
Test name
Test status
Simulation time 35730671486 ps
CPU time 1078.75 seconds
Started May 19 12:29:28 PM PDT 24
Finished May 19 12:47:27 PM PDT 24
Peak memory 208524 kb
Host smart-f4dd0777-e83e-453b-b312-20ba996b1a4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053767784 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2053767784
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2677692018
Short name T1003
Test name
Test status
Simulation time 907338533 ps
CPU time 3.19 seconds
Started May 19 12:29:54 PM PDT 24
Finished May 19 12:30:04 PM PDT 24
Peak memory 200164 kb
Host smart-7b657efe-d29e-4ff2-ae55-6bf0b9b492de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677692018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2677692018
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2873309948
Short name T334
Test name
Test status
Simulation time 80512502745 ps
CPU time 170.01 seconds
Started May 19 12:29:43 PM PDT 24
Finished May 19 12:32:35 PM PDT 24
Peak memory 200280 kb
Host smart-b92201fc-6bf5-4705-a3b6-7fb42fdd21f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873309948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2873309948
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3501712650
Short name T238
Test name
Test status
Simulation time 33032216333 ps
CPU time 25.62 seconds
Started May 19 12:31:14 PM PDT 24
Finished May 19 12:31:41 PM PDT 24
Peak memory 200332 kb
Host smart-8d2c702a-e23d-416a-a5d3-07425e5564ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501712650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3501712650
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2710357680
Short name T814
Test name
Test status
Simulation time 91083349361 ps
CPU time 891.95 seconds
Started May 19 12:31:20 PM PDT 24
Finished May 19 12:46:13 PM PDT 24
Peak memory 216724 kb
Host smart-65a01cc3-f869-4785-87ee-df50b3b055e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710357680 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2710357680
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.462287121
Short name T598
Test name
Test status
Simulation time 44587334542 ps
CPU time 33.41 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:31:56 PM PDT 24
Peak memory 200328 kb
Host smart-c77e5960-faf9-4e31-b3a9-278ba75529e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462287121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.462287121
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3728710500
Short name T1119
Test name
Test status
Simulation time 61291225867 ps
CPU time 92.92 seconds
Started May 19 12:31:19 PM PDT 24
Finished May 19 12:32:53 PM PDT 24
Peak memory 200204 kb
Host smart-2d4dd568-9373-4967-89cb-693b21d518cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728710500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3728710500
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.4272963638
Short name T120
Test name
Test status
Simulation time 151033705542 ps
CPU time 478.07 seconds
Started May 19 12:31:16 PM PDT 24
Finished May 19 12:39:15 PM PDT 24
Peak memory 225228 kb
Host smart-80f119b7-db69-46b8-9973-2bbb04177ca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272963638 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.4272963638
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1659313868
Short name T875
Test name
Test status
Simulation time 60456793819 ps
CPU time 151.22 seconds
Started May 19 12:31:12 PM PDT 24
Finished May 19 12:33:45 PM PDT 24
Peak memory 200280 kb
Host smart-89a3505d-39d8-4137-a63b-7f354962cd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659313868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1659313868
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3392224227
Short name T753
Test name
Test status
Simulation time 19483843662 ps
CPU time 232.1 seconds
Started May 19 12:31:14 PM PDT 24
Finished May 19 12:35:08 PM PDT 24
Peak memory 216472 kb
Host smart-a2fd3c94-2cd1-4cc2-b3b0-ac5151d4f635
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392224227 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3392224227
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3157678564
Short name T181
Test name
Test status
Simulation time 68726595465 ps
CPU time 101.3 seconds
Started May 19 12:31:13 PM PDT 24
Finished May 19 12:32:56 PM PDT 24
Peak memory 200260 kb
Host smart-70eb47e1-3977-4541-ab35-34db2a3b7b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157678564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3157678564
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.982585130
Short name T192
Test name
Test status
Simulation time 38552781823 ps
CPU time 507.72 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:39:51 PM PDT 24
Peak memory 208776 kb
Host smart-5a6da979-c681-41d7-81f8-4f5276b1d828
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982585130 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.982585130
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3017418462
Short name T401
Test name
Test status
Simulation time 65821536758 ps
CPU time 21.88 seconds
Started May 19 12:31:20 PM PDT 24
Finished May 19 12:31:43 PM PDT 24
Peak memory 200248 kb
Host smart-827889f0-ca83-435c-9ae1-5ac3a63ac5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017418462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3017418462
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3536995444
Short name T59
Test name
Test status
Simulation time 110146099327 ps
CPU time 490.96 seconds
Started May 19 12:31:15 PM PDT 24
Finished May 19 12:39:27 PM PDT 24
Peak memory 225220 kb
Host smart-4b73be9a-2462-4d47-bc48-3cb89f2b70cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536995444 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3536995444
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3110882685
Short name T612
Test name
Test status
Simulation time 185920489213 ps
CPU time 54.15 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:32:17 PM PDT 24
Peak memory 200252 kb
Host smart-7cc8c7a9-ac35-4418-8701-342e4ba9b261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110882685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3110882685
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3893492038
Short name T957
Test name
Test status
Simulation time 139794146197 ps
CPU time 534.02 seconds
Started May 19 12:31:16 PM PDT 24
Finished May 19 12:40:11 PM PDT 24
Peak memory 227504 kb
Host smart-aa039e4d-52af-4042-9e2b-c3d3b1663ac1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893492038 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3893492038
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.955870742
Short name T108
Test name
Test status
Simulation time 42214243930 ps
CPU time 366.92 seconds
Started May 19 12:31:21 PM PDT 24
Finished May 19 12:37:30 PM PDT 24
Peak memory 216668 kb
Host smart-133fd015-a953-4338-8312-057a6684e19b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955870742 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.955870742
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1877572395
Short name T700
Test name
Test status
Simulation time 71889849819 ps
CPU time 769.65 seconds
Started May 19 12:31:13 PM PDT 24
Finished May 19 12:44:04 PM PDT 24
Peak memory 216916 kb
Host smart-dfaa0843-7dfc-4f18-819e-dfc76b5d4d66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877572395 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1877572395
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2510970441
Short name T613
Test name
Test status
Simulation time 27469683410 ps
CPU time 26.42 seconds
Started May 19 12:31:13 PM PDT 24
Finished May 19 12:31:41 PM PDT 24
Peak memory 200272 kb
Host smart-ae623bc6-85ff-40e7-9ee1-6c34fc234f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510970441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2510970441
Directory /workspace/99.uart_fifo_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%