Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	113905	1			T1	41		T2	2		T3	1
all_values[1]	113905	1			T1	41		T2	2		T3	1
all_values[2]	113905	1			T1	41		T2	2		T3	1
all_values[3]	113905	1			T1	41		T2	2		T3	1
all_values[4]	113905	1			T1	41		T2	2		T3	1
all_values[5]	113905	1			T1	41		T2	2		T3	1
all_values[6]	113905	1			T1	41		T2	2		T3	1
all_values[7]	113905	1			T1	41		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

455937

1

T1

177

T2

16

T3

5

auto[1]

455303

1

T1

151

T3

3

T4

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

854376

1

T1

323

T2

13

T3

7

auto[1]

56864

1

T1

5

T2

3

T3

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	35775	1			T4	10		T5	7		T7	1
all_values[0]	auto[0]	auto[1]	22733	1			T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[0]	33089	1			T1	38		T4	1		T7	16
all_values[0]	auto[1]	auto[1]	22308	1			T1	1		T8	3		T9	24
all_values[1]	auto[0]	auto[0]	55564	1			T1	19		T2	2		T3	1
all_values[1]	auto[0]	auto[1]	1808	1			T17	5		T14	10		T15	2
all_values[1]	auto[1]	auto[0]	54736	1			T1	22		T4	12		T5	9
all_values[1]	auto[1]	auto[1]	1797	1			T14	1		T15	3		T16	2
all_values[2]	auto[0]	auto[0]	53232	1			T1	26		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2784	1			T2	1		T4	2		T6	1
all_values[2]	auto[1]	auto[0]	55376	1			T1	13		T5	6		T7	21
all_values[2]	auto[1]	auto[1]	2513	1			T1	2		T7	1		T8	1
all_values[3]	auto[0]	auto[0]	57516	1			T1	18		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	300	1			T8	2		T14	3		T15	1
all_values[3]	auto[1]	auto[0]	55734	1			T1	23		T5	1		T7	19
all_values[3]	auto[1]	auto[1]	355	1			T14	2		T15	3		T12	5
all_values[4]	auto[0]	auto[0]	55127	1			T1	35		T2	2		T3	1
all_values[4]	auto[0]	auto[1]	367	1			T14	2		T15	1		T20	11
all_values[4]	auto[1]	auto[0]	57904	1			T1	6		T4	13		T5	6
all_values[4]	auto[1]	auto[1]	507	1			T14	3		T16	6		T20	2
all_values[5]	auto[0]	auto[0]	62623	1			T1	27		T2	2		T5	3
all_values[5]	auto[0]	auto[1]	183	1			T14	2		T15	1		T20	2
all_values[5]	auto[1]	auto[0]	50894	1			T1	14		T3	1		T4	13
all_values[5]	auto[1]	auto[1]	205	1			T14	3		T15	1		T20	1
all_values[6]	auto[0]	auto[0]	54203	1			T1	26		T2	2		T4	13
all_values[6]	auto[0]	auto[1]	167	1			T34	1		T35	1		T21	4
all_values[6]	auto[1]	auto[0]	59365	1			T1	15		T3	1		T7	19
all_values[6]	auto[1]	auto[1]	170	1			T14	3		T20	3		T46	2
all_values[7]	auto[0]	auto[0]	53224	1			T1	24		T2	2		T4	13
all_values[7]	auto[0]	auto[1]	331	1			T14	1		T15	2		T16	6
all_values[7]	auto[1]	auto[0]	60014	1			T1	17		T3	1		T5	8
all_values[7]	auto[1]	auto[1]	336	1			T14	3		T15	1		T23	2