Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2571

1

T1

1

T2

1

T3

1

auto[UartRx]

2571

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4495	1			T1	2		T2	2		T3	2
values[1]	47	1			T14	2		T25	1		T33	2
values[2]	63	1			T14	1		T33	1		T21	2
values[3]	57	1			T24	1		T25	2		T33	1
values[4]	59	1			T14	1		T25	2		T33	1
values[5]	51	1			T33	2		T36	2		T37	1
values[6]	58	1			T14	1		T25	2		T34	3
values[7]	59	1			T33	1		T268	1		T287	2
values[8]	74	1			T14	2		T25	2		T33	2
values[9]	74	1			T14	1		T24	1		T33	1
values[10]	80	1			T14	1		T24	2		T34	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2328	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	16	1			T14	1		T33	2		T37	1
auto[UartTx]	values[2]	22	1			T14	1		T21	2		T314	1
auto[UartTx]	values[3]	20	1			T124	1		T109	2		T315	1
auto[UartTx]	values[4]	29	1			T14	1		T25	1		T33	1
auto[UartTx]	values[5]	16	1			T36	1		T107	1		T50	1
auto[UartTx]	values[6]	25	1			T25	1		T34	3		T35	1
auto[UartTx]	values[7]	21	1			T53	1		T121	1		T292	1
auto[UartTx]	values[8]	20	1			T25	1		T34	2		T38	2
auto[UartTx]	values[9]	27	1			T33	1		T37	1		T264	1
auto[UartTx]	values[10]	38	1			T24	1		T21	1		T287	1
auto[UartRx]	values[0]	2167	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	31	1			T14	1		T25	1		T34	1
auto[UartRx]	values[2]	41	1			T33	1		T37	1		T38	1
auto[UartRx]	values[3]	37	1			T24	1		T25	2		T33	1
auto[UartRx]	values[4]	30	1			T25	1		T276	1		T292	1
auto[UartRx]	values[5]	35	1			T33	2		T36	1		T37	1
auto[UartRx]	values[6]	33	1			T14	1		T25	1		T38	1
auto[UartRx]	values[7]	38	1			T33	1		T268	1		T287	2
auto[UartRx]	values[8]	54	1			T14	2		T25	1		T33	2
auto[UartRx]	values[9]	47	1			T14	1		T24	1		T36	1
auto[UartRx]	values[10]	42	1			T14	1		T24	1		T34	1