Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2444	1			T4	1		T7	1		T9	3
auto[BaudRate115200]	2128	1			T3	9		T8	1		T9	1
auto[BaudRate230400]	2083	1			T2	1		T3	3		T4	2
auto[BaudRate128Kbps]	2025	1			T3	6		T5	3		T7	2
auto[BaudRate256Kbps]	2322	1			T1	3		T2	1		T3	9
auto[BaudRate1Mbps]	1920	1			T3	9		T4	1		T5	1
auto[BaudRate1p5Mbps]	1363	1			T1	2		T5	2		T7	3

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1212	1			T2	2		T23	7		T270	2
freqs[25]	1414	1			T4	5		T19	32		T273	2
freqs[48]	460	1			T15	48		T316	7		T305	4
freqs[50]	685	1			T1	5		T14	52		T129	5
freqs[100]	913	1			T39	7		T317	27		T254	5

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	175	1			T143	1		T50	5		T184	1
auto[BaudRate9600]	freqs[25]	230	1			T4	1		T19	7		T279	3
auto[BaudRate9600]	freqs[48]	84	1			T15	6		T316	7		T305	1
auto[BaudRate9600]	freqs[50]	115	1			T14	8		T129	1		T260	2
auto[BaudRate9600]	freqs[100]	163	1			T39	2		T317	3		T261	3
auto[BaudRate115200]	freqs[24]	166	1			T23	1		T20	1		T265	1
auto[BaudRate115200]	freqs[25]	213	1			T19	8		T272	1		T279	4
auto[BaudRate115200]	freqs[48]	54	1			T15	3		T57	1		T318	2
auto[BaudRate115200]	freqs[50]	84	1			T14	2		T47	2		T260	2
auto[BaudRate115200]	freqs[100]	135	1			T39	1		T317	6		T261	1
auto[BaudRate230400]	freqs[24]	190	1			T2	1		T23	1		T270	1
auto[BaudRate230400]	freqs[25]	205	1			T4	2		T19	3		T273	1
auto[BaudRate230400]	freqs[48]	76	1			T15	17		T318	1		T319	2
auto[BaudRate230400]	freqs[50]	78	1			T14	8		T47	1		T267	2
auto[BaudRate230400]	freqs[100]	126	1			T317	12		T261	4		T276	2
auto[BaudRate128Kbps]	freqs[24]	168	1			T20	3		T265	1		T131	1
auto[BaudRate128Kbps]	freqs[25]	206	1			T19	5		T273	1		T279	4
auto[BaudRate128Kbps]	freqs[48]	62	1			T15	13		T318	1		T320	3
auto[BaudRate128Kbps]	freqs[50]	97	1			T14	13		T129	1		T267	1
auto[BaudRate128Kbps]	freqs[100]	114	1			T39	1		T317	3		T261	3
auto[BaudRate256Kbps]	freqs[24]	201	1			T2	1		T270	1		T20	2
auto[BaudRate256Kbps]	freqs[25]	232	1			T4	1		T19	2		T279	4
auto[BaudRate256Kbps]	freqs[48]	57	1			T15	1		T57	1		T318	3
auto[BaudRate256Kbps]	freqs[50]	122	1			T1	3		T14	6		T47	2
auto[BaudRate256Kbps]	freqs[100]	116	1			T39	1		T254	1		T257	2
auto[BaudRate1Mbps]	freqs[24]	194	1			T23	3		T131	1		T143	1
auto[BaudRate1Mbps]	freqs[25]	228	1			T4	1		T19	5		T279	2
auto[BaudRate1Mbps]	freqs[48]	68	1			T15	1		T305	2		T320	1
auto[BaudRate1Mbps]	freqs[50]	91	1			T14	6		T129	2		T47	2
auto[BaudRate1Mbps]	freqs[100]	138	1			T39	2		T317	3		T254	2
auto[BaudRate1p5Mbps]	freqs[25]	100	1			T19	2		T272	1		T279	1
auto[BaudRate1p5Mbps]	freqs[48]	59	1			T15	7		T305	1		T318	2
auto[BaudRate1p5Mbps]	freqs[50]	98	1			T1	2		T14	9		T129	1
auto[BaudRate1p5Mbps]	freqs[100]	121	1			T254	2		T261	4		T257	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded