Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	6	124	95.38

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	6	124	95.38	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	31063758	1			T1	86114		T3	3		T4	5
all_levels[1]	161879	1			T7	1		T8	1		T9	11
all_levels[2]	2479	1			T5	1		T7	2		T26	2
all_levels[3]	1183	1			T9	1		T115	2		T17	1
all_levels[4]	765	1			T9	1		T115	2		T42	3
all_levels[5]	575	1			T5	1		T8	2		T9	2
all_levels[6]	415	1			T5	1		T8	1		T9	1
all_levels[7]	356	1			T8	1		T42	1		T116	1
all_levels[8]	311	1			T5	1		T7	1		T9	1
all_levels[9]	296	1			T5	1		T8	1		T9	2
all_levels[10]	212	1			T42	1		T116	2		T19	3
all_levels[11]	171	1			T115	1		T14	1		T116	2
all_levels[12]	172	1			T5	1		T19	1		T125	1
all_levels[13]	154	1			T115	1		T14	1		T15	1
all_levels[14]	150	1			T4	3		T7	1		T15	1
all_levels[15]	122	1			T4	1		T15	2		T23	1
all_levels[16]	139	1			T4	1		T15	1		T116	1
all_levels[17]	98	1			T5	1		T115	1		T14	2
all_levels[18]	107	1			T115	1		T25	2		T117	1
all_levels[19]	98	1			T126	1		T110	1		T127	1
all_levels[20]	98	1			T4	1		T116	1		T128	1
all_levels[21]	68	1			T125	2		T119	1		T33	1
all_levels[22]	72	1			T116	1		T19	1		T25	1
all_levels[23]	57	1			T14	1		T25	1		T127	1
all_levels[24]	49	1			T127	1		T119	1		T33	1
all_levels[25]	62	1			T115	1		T33	1		T120	2
all_levels[26]	36	1			T129	1		T130	1		T33	2
all_levels[27]	45	1			T5	1		T115	1		T131	2
all_levels[28]	45	1			T8	1		T115	2		T132	1
all_levels[29]	50	1			T14	1		T120	1		T35	1
all_levels[30]	34	1			T115	1		T133	1		T134	1
all_levels[31]	39	1			T5	1		T115	1		T129	1
all_levels[32]	42	1			T12	2		T112	1		T107	2
all_levels[33]	26	1			T115	1		T117	1		T118	1
all_levels[34]	34	1			T23	1		T135	1		T136	1
all_levels[35]	33	1			T130	1		T137	1		T138	1
all_levels[36]	31	1			T15	1		T46	1		T21	1
all_levels[37]	24	1			T14	2		T139	1		T140	1
all_levels[38]	26	1			T7	1		T23	1		T120	2
all_levels[39]	23	1			T8	1		T115	1		T25	2
all_levels[40]	20	1			T117	1		T132	1		T135	1
all_levels[41]	15	1			T117	1		T141	2		T142	1
all_levels[42]	13	1			T134	1		T119	1		T143	1
all_levels[43]	21	1			T117	1		T132	1		T128	1
all_levels[44]	15	1			T144	1		T141	1		T145	1
all_levels[45]	14	1			T132	1		T140	1		T146	2
all_levels[46]	16	1			T7	1		T147	1		T148	1
all_levels[47]	22	1			T128	1		T121	1		T149	1
all_levels[48]	19	1			T14	1		T112	1		T130	4
all_levels[49]	11	1			T7	1		T150	2		T109	1
all_levels[50]	8	1			T25	1		T151	1		T146	1
all_levels[51]	9	1			T25	1		T36	1		T152	1
all_levels[52]	7	1			T130	1		T153	1		T154	1
all_levels[53]	14	1			T155	1		T55	1		T156	1
all_levels[54]	14	1			T135	1		T157	1		T158	1
all_levels[55]	15	1			T135	1		T119	1		T120	1
all_levels[56]	7	1			T149	2		T159	1		T160	1
all_levels[57]	10	1			T21	2		T56	1		T161	1
all_levels[58]	5	1			T135	1		T131	1		T36	1
all_levels[59]	8	1			T15	1		T156	1		T162	1
all_levels[60]	8	1			T155	1		T163	2		T164	1
all_levels[61]	9	1			T5	1		T144	1		T165	1
all_levels[62]	2	1			T25	1		T166	1		-	-
all_levels[63]	21	1			T19	2		T134	1		T21	1
all_levels[64]	132	1			T13	1		T44	1		T110	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31229932

1

T1

86114

T4

7

T5

28

auto[1]

4837

1

T3

3

T4

4

T5

6

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	6	124	95.38	6

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[40]]	[auto[1]]	0	1	1
[all_levels[50] , all_levels[51] , all_levels[52]]	[auto[1]]	--	--	3
[all_levels[58]]	[auto[1]]	0	1	1
[all_levels[62]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	31059377	1			T1	86114		T4	3		T5	18
all_levels[0]	auto[1]	4381	1			T3	3		T4	2		T5	6
all_levels[1]	auto[0]	161778	1			T7	1		T8	1		T9	11
all_levels[1]	auto[1]	101	1			T39	1		T130	1		T167	1
all_levels[2]	auto[0]	2441	1			T5	1		T7	2		T26	2
all_levels[2]	auto[1]	38	1			T126	1		T13	2		T111	2
all_levels[3]	auto[0]	1173	1			T9	1		T115	2		T17	1
all_levels[3]	auto[1]	10	1			T168	1		T109	2		T169	1
all_levels[4]	auto[0]	741	1			T9	1		T115	2		T42	3
all_levels[4]	auto[1]	24	1			T170	1		T171	2		T146	1
all_levels[5]	auto[0]	552	1			T5	1		T8	2		T9	2
all_levels[5]	auto[1]	23	1			T133	1		T168	2		T172	2
all_levels[6]	auto[0]	404	1			T5	1		T8	1		T9	1
all_levels[6]	auto[1]	11	1			T55	1		T173	1		T174	1
all_levels[7]	auto[0]	349	1			T8	1		T42	1		T116	1
all_levels[7]	auto[1]	7	1			T175	2		T176	1		T177	1
all_levels[8]	auto[0]	300	1			T5	1		T7	1		T9	1
all_levels[8]	auto[1]	11	1			T111	1		T46	1		T178	2
all_levels[9]	auto[0]	283	1			T5	1		T8	1		T9	2
all_levels[9]	auto[1]	13	1			T42	1		T179	1		T180	1
all_levels[10]	auto[0]	197	1			T42	1		T116	2		T19	3
all_levels[10]	auto[1]	15	1			T146	1		T181	3		T182	1
all_levels[11]	auto[0]	161	1			T115	1		T14	1		T116	2
all_levels[11]	auto[1]	10	1			T183	2		T184	2		T138	1
all_levels[12]	auto[0]	162	1			T5	1		T19	1		T125	1
all_levels[12]	auto[1]	10	1			T127	1		T150	2		T171	1
all_levels[13]	auto[0]	147	1			T115	1		T14	1		T15	1
all_levels[13]	auto[1]	7	1			T140	2		T185	1		T186	1
all_levels[14]	auto[0]	142	1			T4	1		T7	1		T15	1
all_levels[14]	auto[1]	8	1			T4	2		T134	1		T187	1
all_levels[15]	auto[0]	117	1			T4	1		T15	2		T23	1
all_levels[15]	auto[1]	5	1			T188	1		T189	1		T190	1
all_levels[16]	auto[0]	129	1			T4	1		T15	1		T116	1
all_levels[16]	auto[1]	10	1			T36	1		T191	3		T192	1
all_levels[17]	auto[0]	93	1			T5	1		T115	1		T14	2
all_levels[17]	auto[1]	5	1			T193	3		T194	1		T195	1
all_levels[18]	auto[0]	98	1			T115	1		T25	2		T117	1
all_levels[18]	auto[1]	9	1			T167	1		T196	1		T197	2
all_levels[19]	auto[0]	88	1			T126	1		T110	1		T127	1
all_levels[19]	auto[1]	10	1			T198	3		T199	1		T200	1
all_levels[20]	auto[0]	87	1			T4	1		T116	1		T128	1
all_levels[20]	auto[1]	11	1			T55	1		T201	1		T185	1
all_levels[21]	auto[0]	61	1			T125	1		T119	1		T33	1
all_levels[21]	auto[1]	7	1			T125	1		T55	1		T202	2
all_levels[22]	auto[0]	66	1			T116	1		T19	1		T25	1
all_levels[22]	auto[1]	6	1			T55	2		T191	1		T203	1
all_levels[23]	auto[0]	52	1			T14	1		T25	1		T127	1
all_levels[23]	auto[1]	5	1			T138	1		T204	3		T205	1
all_levels[24]	auto[0]	48	1			T127	1		T119	1		T33	1
all_levels[24]	auto[1]	1	1			T193	1		-	-		-	-
all_levels[25]	auto[0]	57	1			T115	1		T33	1		T120	1
all_levels[25]	auto[1]	5	1			T120	1		T206	3		T207	1
all_levels[26]	auto[0]	34	1			T129	1		T130	1		T33	2
all_levels[26]	auto[1]	2	1			T205	2		-	-		-	-
all_levels[27]	auto[0]	44	1			T5	1		T115	1		T131	1
all_levels[27]	auto[1]	1	1			T131	1		-	-		-	-
all_levels[28]	auto[0]	44	1			T8	1		T115	1		T132	1
all_levels[28]	auto[1]	1	1			T115	1		-	-		-	-
all_levels[29]	auto[0]	46	1			T14	1		T120	1		T35	1
all_levels[29]	auto[1]	4	1			T36	1		T208	1		T209	1
all_levels[30]	auto[0]	33	1			T115	1		T133	1		T134	1
all_levels[30]	auto[1]	1	1			T147	1		-	-		-	-
all_levels[31]	auto[0]	32	1			T5	1		T115	1		T129	1
all_levels[31]	auto[1]	7	1			T210	3		T211	4		-	-
all_levels[32]	auto[0]	40	1			T12	1		T112	1		T107	2
all_levels[32]	auto[1]	2	1			T12	1		T212	1		-	-
all_levels[33]	auto[0]	24	1			T115	1		T117	1		T118	1
all_levels[33]	auto[1]	2	1			T213	1		T214	1		-	-
all_levels[34]	auto[0]	30	1			T23	1		T135	1		T136	1
all_levels[34]	auto[1]	4	1			T148	1		T215	1		T216	2
all_levels[35]	auto[0]	29	1			T130	1		T137	1		T138	1
all_levels[35]	auto[1]	4	1			T217	3		T218	1		-	-
all_levels[36]	auto[0]	28	1			T15	1		T46	1		T21	1
all_levels[36]	auto[1]	3	1			T213	1		T219	1		T220	1
all_levels[37]	auto[0]	23	1			T14	2		T139	1		T140	1
all_levels[37]	auto[1]	1	1			T221	1		-	-		-	-
all_levels[38]	auto[0]	22	1			T7	1		T23	1		T120	2
all_levels[38]	auto[1]	4	1			T222	3		T223	1		-	-
all_levels[39]	auto[0]	22	1			T8	1		T115	1		T25	1
all_levels[39]	auto[1]	1	1			T25	1		-	-		-	-
all_levels[40]	auto[0]	20	1			T117	1		T132	1		T135	1
all_levels[41]	auto[0]	14	1			T117	1		T141	1		T142	1
all_levels[41]	auto[1]	1	1			T141	1		-	-		-	-
all_levels[42]	auto[0]	12	1			T134	1		T119	1		T143	1
all_levels[42]	auto[1]	1	1			T169	1		-	-		-	-
all_levels[43]	auto[0]	18	1			T117	1		T132	1		T128	1
all_levels[43]	auto[1]	3	1			T224	1		T225	2		-	-
all_levels[44]	auto[0]	14	1			T144	1		T141	1		T145	1
all_levels[44]	auto[1]	1	1			T226	1		-	-		-	-
all_levels[45]	auto[0]	13	1			T132	1		T140	1		T146	1
all_levels[45]	auto[1]	1	1			T146	1		-	-		-	-
all_levels[46]	auto[0]	14	1			T7	1		T147	1		T148	1
all_levels[46]	auto[1]	2	1			T172	1		T223	1		-	-
all_levels[47]	auto[0]	17	1			T128	1		T121	1		T149	1
all_levels[47]	auto[1]	5	1			T222	3		T227	1		T228	1
all_levels[48]	auto[0]	13	1			T14	1		T112	1		T130	1
all_levels[48]	auto[1]	6	1			T130	3		T229	3		-	-
all_levels[49]	auto[0]	8	1			T7	1		T150	1		T109	1
all_levels[49]	auto[1]	3	1			T150	1		T230	2		-	-
all_levels[50]	auto[0]	8	1			T25	1		T151	1		T146	1
all_levels[51]	auto[0]	9	1			T25	1		T36	1		T152	1
all_levels[52]	auto[0]	7	1			T130	1		T153	1		T154	1
all_levels[53]	auto[0]	11	1			T155	1		T55	1		T156	1
all_levels[53]	auto[1]	3	1			T193	3		-	-		-	-
all_levels[54]	auto[0]	10	1			T135	1		T157	1		T158	1
all_levels[54]	auto[1]	4	1			T231	1		T232	1		T233	2
all_levels[55]	auto[0]	12	1			T135	1		T119	1		T120	1
all_levels[55]	auto[1]	3	1			T234	1		T193	2		-	-
all_levels[56]	auto[0]	6	1			T149	1		T159	1		T160	1
all_levels[56]	auto[1]	1	1			T149	1		-	-		-	-
all_levels[57]	auto[0]	8	1			T21	2		T56	1		T161	1
all_levels[57]	auto[1]	2	1			T235	2		-	-		-	-
all_levels[58]	auto[0]	5	1			T135	1		T131	1		T36	1
all_levels[59]	auto[0]	7	1			T15	1		T156	1		T162	1
all_levels[59]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[60]	auto[0]	7	1			T155	1		T163	1		T164	1
all_levels[60]	auto[1]	1	1			T163	1		-	-		-	-
all_levels[61]	auto[0]	7	1			T5	1		T144	1		T165	1
all_levels[61]	auto[1]	2	1			T237	2		-	-		-	-
all_levels[62]	auto[0]	2	1			T25	1		T166	1		-	-
all_levels[63]	auto[0]	17	1			T19	2		T134	1		T21	1
all_levels[63]	auto[1]	4	1			T141	1		T238	1		T239	2
all_levels[64]	auto[0]	119	1			T13	1		T44	1		T110	1
all_levels[64]	auto[1]	13	1			T240	1		T161	1		T241	1