Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	113905	1			T1	41		T2	2		T3	1
all_pins[1]	113905	1			T1	41		T2	2		T3	1
all_pins[2]	113905	1			T1	41		T2	2		T3	1
all_pins[3]	113905	1			T1	41		T2	2		T3	1
all_pins[4]	113905	1			T1	41		T2	2		T3	1
all_pins[5]	113905	1			T1	41		T2	2		T3	1
all_pins[6]	113905	1			T1	41		T2	2		T3	1
all_pins[7]	113905	1			T1	41		T2	2		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	882135	1			T1	325		T2	16		T3	8
values[0x1]	29105	1			T1	3		T7	1		T8	7
transitions[0x0=>0x1]	27899	1			T1	3		T7	1		T8	7
transitions[0x1=>0x0]	27490	1			T1	2		T7	1		T8	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	91497	1			T1	40		T2	2		T3	1
all_pins[0]	values[0x1]	22408	1			T1	1		T8	3		T9	24
all_pins[0]	transitions[0x0=>0x1]	21777	1			T1	1		T8	3		T9	24
all_pins[0]	transitions[0x1=>0x0]	1159	1			T15	1		T16	2		T13	8
all_pins[1]	values[0x0]	112115	1			T1	41		T2	2		T3	1
all_pins[1]	values[0x1]	1790	1			T14	1		T15	3		T16	2
all_pins[1]	transitions[0x0=>0x1]	1648	1			T14	1		T15	3		T16	2
all_pins[1]	transitions[0x1=>0x0]	2433	1			T1	2		T7	1		T8	1
all_pins[2]	values[0x0]	111330	1			T1	39		T2	2		T3	1
all_pins[2]	values[0x1]	2575	1			T1	2		T7	1		T8	1
all_pins[2]	transitions[0x0=>0x1]	2501	1			T1	2		T7	1		T8	1
all_pins[2]	transitions[0x1=>0x0]	280	1			T14	2		T15	3		T12	5
all_pins[3]	values[0x0]	113551	1			T1	41		T2	2		T3	1
all_pins[3]	values[0x1]	354	1			T14	2		T15	3		T12	5
all_pins[3]	transitions[0x0=>0x1]	313	1			T14	2		T15	3		T12	5
all_pins[3]	transitions[0x1=>0x0]	466	1			T14	3		T16	6		T20	2
all_pins[4]	values[0x0]	113398	1			T1	41		T2	2		T3	1
all_pins[4]	values[0x1]	507	1			T14	3		T16	6		T20	2
all_pins[4]	transitions[0x0=>0x1]	434	1			T14	2		T16	6		T20	2
all_pins[4]	transitions[0x1=>0x0]	182	1			T14	2		T15	1		T20	1
all_pins[5]	values[0x0]	113650	1			T1	41		T2	2		T3	1
all_pins[5]	values[0x1]	255	1			T14	3		T15	1		T20	1
all_pins[5]	transitions[0x0=>0x1]	207	1			T14	2		T15	1		T20	1
all_pins[5]	transitions[0x1=>0x0]	832	1			T8	3		T9	1		T14	2
all_pins[6]	values[0x0]	113025	1			T1	41		T2	2		T3	1
all_pins[6]	values[0x1]	880	1			T8	3		T9	1		T14	3
all_pins[6]	transitions[0x0=>0x1]	827	1			T8	3		T9	1		T14	3
all_pins[6]	transitions[0x1=>0x0]	283	1			T14	3		T15	1		T23	2
all_pins[7]	values[0x0]	113569	1			T1	41		T2	2		T3	1
all_pins[7]	values[0x1]	336	1			T14	3		T15	1		T23	2
all_pins[7]	transitions[0x0=>0x1]	192	1			T14	3		T15	1		T23	2
all_pins[7]	transitions[0x1=>0x0]	21855	1			T8	2		T9	23		T115	23