Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7093357	1			T1	17571		T4	2		T5	12
all_levels[1]	1249705	1			T1	47		T5	7		T8	2
all_levels[2]	454878	1			T1	56		T9	3		T26	23
all_levels[3]	494797	1			T1	47		T26	19		T115	1
all_levels[4]	313422	1			T1	37		T8	1		T26	32
all_levels[5]	322794	1			T1	51		T9	2		T26	20
all_levels[6]	300111	1			T1	49		T26	27		T115	1
all_levels[7]	399721	1			T1	52		T8	1		T9	26
all_levels[8]	259666	1			T1	39		T26	22		T14	581
all_levels[9]	274917	1			T1	47		T5	7		T26	19
all_levels[10]	228958	1			T1	37		T26	22		T14	1142
all_levels[11]	428201	1			T1	42		T4	2		T5	4
all_levels[12]	355679	1			T1	46		T9	8		T26	20
all_levels[13]	230896	1			T1	49		T9	17		T26	26
all_levels[14]	352555	1			T1	46		T9	5		T26	34
all_levels[15]	348234	1			T1	41		T8	1		T9	1
all_levels[16]	263432	1			T1	45		T4	1		T9	3
all_levels[17]	239222	1			T1	40		T8	4		T9	1
all_levels[18]	442629	1			T1	40		T26	20		T15	1
all_levels[19]	197399	1			T1	49		T26	31		T14	1
all_levels[20]	305146	1			T1	47		T26	26		T14	3
all_levels[21]	616962	1			T1	56		T26	29		T14	2
all_levels[22]	433652	1			T1	46		T26	23		T14	1
all_levels[23]	207693	1			T1	42		T26	27		T14	1
all_levels[24]	735023	1			T1	41		T26	29		T19	671
all_levels[25]	318124	1			T1	50		T26	31		T15	2
all_levels[26]	255230	1			T1	50		T26	26		T19	669
all_levels[27]	172461	1			T1	41		T9	2		T26	33
all_levels[28]	175374	1			T1	46		T9	5		T26	25
all_levels[29]	243038	1			T1	42		T4	3		T26	24
all_levels[30]	230714	1			T1	44		T9	10		T26	33
all_levels[31]	470750	1			T1	827		T9	16		T26	633
all_levels[32]	12819565	1			T1	66352		T4	3		T5	7

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31229932

1

T1

86114

T4

7

T5

28

auto[1]

4373

1

T1

1

T4

4

T5

9

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7090973	1			T1	17571		T4	1		T5	7
all_levels[0]	auto[1]	2384	1			T4	1		T5	5		T8	2
all_levels[1]	auto[0]	1249377	1			T1	47		T5	7		T8	1
all_levels[1]	auto[1]	328	1			T8	1		T39	1		T126	5
all_levels[2]	auto[0]	454834	1			T1	56		T9	3		T26	23
all_levels[2]	auto[1]	44	1			T39	2		T45	2		T140	1
all_levels[3]	auto[0]	494631	1			T1	47		T26	19		T115	1
all_levels[3]	auto[1]	166	1			T167	2		T313	1		T152	1
all_levels[4]	auto[0]	313392	1			T1	37		T8	1		T26	32
all_levels[4]	auto[1]	30	1			T140	2		T323	1		T324	1
all_levels[5]	auto[0]	322756	1			T1	51		T9	2		T26	20
all_levels[5]	auto[1]	38	1			T279	1		T147	1		T325	2
all_levels[6]	auto[0]	300085	1			T1	49		T26	27		T115	1
all_levels[6]	auto[1]	26	1			T12	1		T133	1		T147	1
all_levels[7]	auto[0]	399513	1			T1	52		T8	1		T9	26
all_levels[7]	auto[1]	208	1			T40	6		T265	12		T34	9
all_levels[8]	auto[0]	259633	1			T1	39		T26	22		T14	581
all_levels[8]	auto[1]	33	1			T126	1		T120	1		T293	1
all_levels[9]	auto[0]	274892	1			T1	47		T5	6		T26	19
all_levels[9]	auto[1]	25	1			T5	1		T42	1		T326	1
all_levels[10]	auto[0]	228948	1			T1	37		T26	22		T14	1142
all_levels[10]	auto[1]	10	1			T36	1		T61	1		T327	1
all_levels[11]	auto[0]	428174	1			T1	42		T4	1		T5	3
all_levels[11]	auto[1]	27	1			T4	1		T5	1		T278	1
all_levels[12]	auto[0]	355637	1			T1	46		T9	8		T26	20
all_levels[12]	auto[1]	42	1			T14	1		T13	1		T277	1
all_levels[13]	auto[0]	230863	1			T1	49		T9	17		T26	26
all_levels[13]	auto[1]	33	1			T131	2		T257	1		T279	1
all_levels[14]	auto[0]	352533	1			T1	46		T9	5		T26	34
all_levels[14]	auto[1]	22	1			T134	1		T309	2		T166	2
all_levels[15]	auto[0]	348084	1			T1	41		T8	1		T9	1
all_levels[15]	auto[1]	150	1			T167	3		T289	11		T120	7
all_levels[16]	auto[0]	263410	1			T1	45		T4	1		T9	3
all_levels[16]	auto[1]	22	1			T111	1		T47	1		T328	2
all_levels[17]	auto[0]	239199	1			T1	40		T8	4		T9	1
all_levels[17]	auto[1]	23	1			T269	1		T221	1		T329	1
all_levels[18]	auto[0]	442607	1			T1	40		T26	20		T15	1
all_levels[18]	auto[1]	22	1			T126	2		T110	4		T118	1
all_levels[19]	auto[0]	197377	1			T1	49		T26	31		T14	1
all_levels[19]	auto[1]	22	1			T309	1		T330	1		T331	1
all_levels[20]	auto[0]	305116	1			T1	47		T26	26		T14	3
all_levels[20]	auto[1]	30	1			T120	1		T178	1		T332	1
all_levels[21]	auto[0]	616946	1			T1	56		T26	29		T14	2
all_levels[21]	auto[1]	16	1			T147	1		T202	1		T240	2
all_levels[22]	auto[0]	433635	1			T1	46		T26	23		T14	1
all_levels[22]	auto[1]	17	1			T184	1		T180	1		T182	1
all_levels[23]	auto[0]	207667	1			T1	42		T26	27		T14	1
all_levels[23]	auto[1]	26	1			T44	1		T46	1		T279	1
all_levels[24]	auto[0]	735004	1			T1	41		T26	29		T19	671
all_levels[24]	auto[1]	19	1			T13	1		T46	1		T184	2
all_levels[25]	auto[0]	318098	1			T1	50		T26	31		T15	2
all_levels[25]	auto[1]	26	1			T250	1		T259	1		T260	2
all_levels[26]	auto[0]	255203	1			T1	50		T26	26		T19	669
all_levels[26]	auto[1]	27	1			T261	1		T303	1		T333	4
all_levels[27]	auto[0]	172451	1			T1	41		T9	2		T26	33
all_levels[27]	auto[1]	10	1			T15	1		T45	1		T142	1
all_levels[28]	auto[0]	175355	1			T1	46		T9	5		T26	25
all_levels[28]	auto[1]	19	1			T279	4		T140	1		T166	1
all_levels[29]	auto[0]	243019	1			T1	42		T4	2		T26	24
all_levels[29]	auto[1]	19	1			T4	1		T127	1		T152	1
all_levels[30]	auto[0]	230705	1			T1	44		T9	9		T26	33
all_levels[30]	auto[1]	9	1			T9	1		T244	1		T334	4
all_levels[31]	auto[0]	470727	1			T1	827		T9	16		T26	633
all_levels[31]	auto[1]	23	1			T243	1		T138	3		T168	2
all_levels[32]	auto[0]	12819088	1			T1	66351		T4	2		T5	5
all_levels[32]	auto[1]	477	1			T1	1		T4	1		T5	2