Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	756	1			T14	7		T15	7		T20	7
all_values[1]	756	1			T14	7		T15	7		T20	7
all_values[2]	756	1			T14	7		T15	7		T20	7
all_values[3]	756	1			T14	7		T15	7		T20	7
all_values[4]	756	1			T14	7		T15	7		T20	7
all_values[5]	756	1			T14	7		T15	7		T20	7
all_values[6]	756	1			T14	7		T15	7		T20	7
all_values[7]	756	1			T14	7		T15	7		T20	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3201

1

T14

28

T15

28

T20

35

auto[1]

2847

1

T14

28

T15

28

T20

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2227

1

T14

21

T15

23

T20

21

auto[1]

3821

1

T14

35

T15

33

T20

35

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3599

1

T14

34

T15

33

T20

31

auto[1]

2449

1

T14

22

T15

23

T20

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	266	1			T14	2		T15	2		T20	2
all_values[0]	auto[0]	auto[1]	auto[1]	206	1			T14	2		T15	3		T20	1
all_values[0]	auto[1]	auto[0]	auto[1]	164	1			T14	2		T15	2		T20	2
all_values[0]	auto[1]	auto[1]	auto[1]	120	1			T14	1		T20	2		T34	2
all_values[1]	auto[0]	auto[0]	auto[0]	220	1			T14	5		T15	1		T20	2
all_values[1]	auto[0]	auto[1]	auto[0]	212	1			T15	1		T20	1		T46	2
all_values[1]	auto[1]	auto[0]	auto[1]	164	1			T14	2		T15	1		T20	2
all_values[1]	auto[1]	auto[1]	auto[1]	160	1			T15	4		T20	2		T46	1
all_values[2]	auto[0]	auto[0]	auto[0]	163	1			T14	3		T15	1		T20	3
all_values[2]	auto[0]	auto[0]	auto[1]	71	1			T15	2		T20	1		T21	3
all_values[2]	auto[0]	auto[1]	auto[0]	144	1			T15	3		T46	2		T34	1
all_values[2]	auto[0]	auto[1]	auto[1]	73	1			T14	2		T20	1		T107	1
all_values[2]	auto[1]	auto[0]	auto[1]	163	1			T14	1		T20	1		T46	1
all_values[2]	auto[1]	auto[1]	auto[1]	142	1			T14	1		T15	1		T20	1
all_values[3]	auto[0]	auto[0]	auto[0]	157	1			T14	1		T15	1		T20	2
all_values[3]	auto[0]	auto[0]	auto[1]	65	1			T14	1		T20	1		T107	1
all_values[3]	auto[0]	auto[1]	auto[0]	136	1			T14	1		T15	1		T20	1
all_values[3]	auto[0]	auto[1]	auto[1]	87	1			T15	1		T34	3		T21	3
all_values[3]	auto[1]	auto[0]	auto[1]	163	1			T14	3		T15	2		T20	2
all_values[3]	auto[1]	auto[1]	auto[1]	148	1			T14	1		T15	2		T20	1
all_values[4]	auto[0]	auto[0]	auto[0]	174	1			T14	1		T15	4		T20	2
all_values[4]	auto[0]	auto[0]	auto[1]	71	1			T14	1		T15	1		T20	1
all_values[4]	auto[0]	auto[1]	auto[0]	154	1			T15	1		T20	1		T35	1
all_values[4]	auto[0]	auto[1]	auto[1]	75	1			T14	2		T20	1		T34	3
all_values[4]	auto[1]	auto[0]	auto[1]	162	1			T14	1		T15	1		T20	2
all_values[4]	auto[1]	auto[1]	auto[1]	120	1			T14	2		T34	2		T35	1
all_values[5]	auto[0]	auto[0]	auto[0]	145	1			T20	3		T46	2		T21	5
all_values[5]	auto[0]	auto[0]	auto[1]	78	1			T34	1		T35	1		T21	1
all_values[5]	auto[0]	auto[1]	auto[0]	109	1			T14	1		T15	3		T34	1
all_values[5]	auto[0]	auto[1]	auto[1]	87	1			T14	1		T34	2		T21	1
all_values[5]	auto[1]	auto[0]	auto[1]	169	1			T14	2		T15	1		T20	4
all_values[5]	auto[1]	auto[1]	auto[1]	168	1			T14	3		T15	3		T34	2
all_values[6]	auto[0]	auto[0]	auto[0]	152	1			T14	1		T15	4		T20	1
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T21	3		T50	2		T124	1
all_values[6]	auto[0]	auto[1]	auto[0]	153	1			T14	2		T15	2		T20	2
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T14	2		T20	1		T46	1
all_values[6]	auto[1]	auto[0]	auto[1]	173	1			T20	1		T46	1		T34	3
all_values[6]	auto[1]	auto[1]	auto[1]	133	1			T14	2		T15	1		T20	2
all_values[7]	auto[0]	auto[0]	auto[0]	178	1			T14	1		T15	1		T20	2
all_values[7]	auto[0]	auto[0]	auto[1]	73	1			T15	1		T35	2		T21	2
all_values[7]	auto[0]	auto[1]	auto[0]	130	1			T14	5		T20	1		T46	1
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T20	1		T46	1		T21	1
all_values[7]	auto[1]	auto[0]	auto[1]	160	1			T14	1		T15	3		T20	1
all_values[7]	auto[1]	auto[1]	auto[1]	140	1			T15	2		T20	2		T46	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal