Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.28 99.27 97.95 100.00 98.80 100.00 99.68


Total test records in report: 1320
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T1256 /workspace/coverage/cover_reg_top/4.uart_tl_errors.998844374 May 21 12:35:17 PM PDT 24 May 21 12:35:48 PM PDT 24 125118744 ps
T1257 /workspace/coverage/cover_reg_top/45.uart_intr_test.2596523962 May 21 12:35:49 PM PDT 24 May 21 12:36:20 PM PDT 24 41802078 ps
T1258 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1372571341 May 21 12:35:34 PM PDT 24 May 21 12:36:06 PM PDT 24 730076733 ps
T1259 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2762592058 May 21 12:35:24 PM PDT 24 May 21 12:35:56 PM PDT 24 53029502 ps
T1260 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.174457397 May 21 12:35:33 PM PDT 24 May 21 12:36:04 PM PDT 24 65975161 ps
T1261 /workspace/coverage/cover_reg_top/1.uart_intr_test.2292956163 May 21 12:35:30 PM PDT 24 May 21 12:36:01 PM PDT 24 13724834 ps
T1262 /workspace/coverage/cover_reg_top/22.uart_intr_test.1432316490 May 21 12:35:31 PM PDT 24 May 21 12:36:02 PM PDT 24 38476161 ps
T1263 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3966379823 May 21 12:35:21 PM PDT 24 May 21 12:35:52 PM PDT 24 43586063 ps
T1264 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2058836175 May 21 12:35:14 PM PDT 24 May 21 12:35:42 PM PDT 24 313830784 ps
T1265 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.781928276 May 21 12:35:17 PM PDT 24 May 21 12:35:46 PM PDT 24 32221113 ps
T1266 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3301989974 May 21 12:35:27 PM PDT 24 May 21 12:35:59 PM PDT 24 149279974 ps
T1267 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.119479102 May 21 12:35:35 PM PDT 24 May 21 12:36:07 PM PDT 24 55265404 ps
T1268 /workspace/coverage/cover_reg_top/11.uart_tl_errors.243421037 May 21 12:35:19 PM PDT 24 May 21 12:35:51 PM PDT 24 146655817 ps
T1269 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4072763538 May 21 12:35:26 PM PDT 24 May 21 12:35:58 PM PDT 24 20399103 ps
T1270 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.489894990 May 21 12:35:45 PM PDT 24 May 21 12:36:15 PM PDT 24 75951389 ps
T1271 /workspace/coverage/cover_reg_top/3.uart_csr_rw.3057978918 May 21 12:35:19 PM PDT 24 May 21 12:35:49 PM PDT 24 16933147 ps
T1272 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3461122959 May 21 12:35:35 PM PDT 24 May 21 12:36:07 PM PDT 24 72610257 ps
T1273 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.112637959 May 21 12:35:28 PM PDT 24 May 21 12:36:00 PM PDT 24 91216998 ps
T1274 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3713883776 May 21 12:35:20 PM PDT 24 May 21 12:35:51 PM PDT 24 29820763 ps
T1275 /workspace/coverage/cover_reg_top/37.uart_intr_test.321216807 May 21 12:35:35 PM PDT 24 May 21 12:36:07 PM PDT 24 15713713 ps
T1276 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.260922463 May 21 12:35:16 PM PDT 24 May 21 12:35:46 PM PDT 24 136306823 ps
T1277 /workspace/coverage/cover_reg_top/31.uart_intr_test.2171265167 May 21 12:35:38 PM PDT 24 May 21 12:36:09 PM PDT 24 63976044 ps
T1278 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3110343654 May 21 12:35:18 PM PDT 24 May 21 12:35:48 PM PDT 24 68870648 ps
T1279 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3395742836 May 21 12:35:20 PM PDT 24 May 21 12:35:51 PM PDT 24 92192004 ps
T70 /workspace/coverage/cover_reg_top/10.uart_csr_rw.951972994 May 21 12:35:17 PM PDT 24 May 21 12:35:47 PM PDT 24 46638604 ps
T1280 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.949068787 May 21 12:35:29 PM PDT 24 May 21 12:36:00 PM PDT 24 22787978 ps
T1281 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2919303701 May 21 12:35:19 PM PDT 24 May 21 12:35:50 PM PDT 24 86414487 ps
T1282 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3152332958 May 21 12:35:29 PM PDT 24 May 21 12:36:01 PM PDT 24 73818162 ps
T1283 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2587966962 May 21 12:35:15 PM PDT 24 May 21 12:35:43 PM PDT 24 22329739 ps
T1284 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1737871974 May 21 12:35:26 PM PDT 24 May 21 12:35:59 PM PDT 24 189964580 ps
T1285 /workspace/coverage/cover_reg_top/16.uart_tl_errors.4113000823 May 21 12:35:30 PM PDT 24 May 21 12:36:02 PM PDT 24 40369858 ps
T1286 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.217711550 May 21 12:35:38 PM PDT 24 May 21 12:36:08 PM PDT 24 54269546 ps
T1287 /workspace/coverage/cover_reg_top/29.uart_intr_test.612445844 May 21 12:35:29 PM PDT 24 May 21 12:36:00 PM PDT 24 16854901 ps
T1288 /workspace/coverage/cover_reg_top/24.uart_intr_test.2432629272 May 21 12:35:34 PM PDT 24 May 21 12:36:05 PM PDT 24 42794767 ps
T1289 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1490283917 May 21 12:35:36 PM PDT 24 May 21 12:36:07 PM PDT 24 88968456 ps
T1290 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3791289147 May 21 12:35:22 PM PDT 24 May 21 12:35:54 PM PDT 24 109480957 ps
T1291 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3871731156 May 21 12:35:16 PM PDT 24 May 21 12:35:46 PM PDT 24 24070504 ps
T1292 /workspace/coverage/cover_reg_top/34.uart_intr_test.2729518764 May 21 12:35:47 PM PDT 24 May 21 12:36:19 PM PDT 24 14204879 ps
T1293 /workspace/coverage/cover_reg_top/49.uart_intr_test.434824439 May 21 12:35:42 PM PDT 24 May 21 12:36:12 PM PDT 24 14888599 ps
T1294 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1157219271 May 21 12:35:32 PM PDT 24 May 21 12:36:03 PM PDT 24 22684683 ps
T1295 /workspace/coverage/cover_reg_top/40.uart_intr_test.2314498632 May 21 12:35:39 PM PDT 24 May 21 12:36:10 PM PDT 24 14047812 ps
T1296 /workspace/coverage/cover_reg_top/8.uart_intr_test.3468904126 May 21 12:35:25 PM PDT 24 May 21 12:35:57 PM PDT 24 48959665 ps
T1297 /workspace/coverage/cover_reg_top/19.uart_intr_test.1668846598 May 21 12:35:43 PM PDT 24 May 21 12:36:13 PM PDT 24 14446763 ps
T71 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.4236329250 May 21 12:35:21 PM PDT 24 May 21 12:35:52 PM PDT 24 16160294 ps
T1298 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1424251821 May 21 12:35:24 PM PDT 24 May 21 12:35:57 PM PDT 24 437778154 ps
T1299 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.4231472047 May 21 12:35:24 PM PDT 24 May 21 12:35:56 PM PDT 24 227160624 ps
T1300 /workspace/coverage/cover_reg_top/11.uart_intr_test.4078020303 May 21 12:35:34 PM PDT 24 May 21 12:36:05 PM PDT 24 44051292 ps
T1301 /workspace/coverage/cover_reg_top/15.uart_intr_test.701340755 May 21 12:35:34 PM PDT 24 May 21 12:36:06 PM PDT 24 47423200 ps
T1302 /workspace/coverage/cover_reg_top/12.uart_intr_test.3812414630 May 21 12:35:34 PM PDT 24 May 21 12:36:05 PM PDT 24 40845133 ps
T1303 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1343647393 May 21 12:35:10 PM PDT 24 May 21 12:35:37 PM PDT 24 21339044 ps
T93 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3579705670 May 21 12:35:28 PM PDT 24 May 21 12:36:01 PM PDT 24 523368774 ps
T1304 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1032076930 May 21 12:35:20 PM PDT 24 May 21 12:35:52 PM PDT 24 301276182 ps
T1305 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.4248542691 May 21 12:35:41 PM PDT 24 May 21 12:36:12 PM PDT 24 18634638 ps
T1306 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1070317769 May 21 12:35:18 PM PDT 24 May 21 12:35:49 PM PDT 24 45371044 ps
T1307 /workspace/coverage/cover_reg_top/12.uart_tl_errors.2152909909 May 21 12:35:28 PM PDT 24 May 21 12:36:00 PM PDT 24 67322593 ps
T1308 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2475593474 May 21 12:35:29 PM PDT 24 May 21 12:36:02 PM PDT 24 248587129 ps
T1309 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.150502228 May 21 12:35:20 PM PDT 24 May 21 12:35:52 PM PDT 24 16730022 ps
T1310 /workspace/coverage/cover_reg_top/48.uart_intr_test.1618381300 May 21 12:35:42 PM PDT 24 May 21 12:36:13 PM PDT 24 15096178 ps
T1311 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4229671472 May 21 12:35:39 PM PDT 24 May 21 12:36:10 PM PDT 24 230954433 ps
T1312 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1040497032 May 21 12:35:21 PM PDT 24 May 21 12:35:52 PM PDT 24 51329092 ps
T1313 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1596816621 May 21 12:35:39 PM PDT 24 May 21 12:36:10 PM PDT 24 44241908 ps
T1314 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.739833803 May 21 12:35:36 PM PDT 24 May 21 12:36:08 PM PDT 24 77516871 ps
T95 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.15651723 May 21 12:35:40 PM PDT 24 May 21 12:36:13 PM PDT 24 49659332 ps
T1315 /workspace/coverage/cover_reg_top/16.uart_intr_test.2068889354 May 21 12:35:41 PM PDT 24 May 21 12:36:12 PM PDT 24 16022387 ps
T1316 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3008886411 May 21 12:35:17 PM PDT 24 May 21 12:35:47 PM PDT 24 100472212 ps
T1317 /workspace/coverage/cover_reg_top/33.uart_intr_test.1111821701 May 21 12:35:35 PM PDT 24 May 21 12:36:06 PM PDT 24 42366075 ps
T1318 /workspace/coverage/cover_reg_top/32.uart_intr_test.855803492 May 21 12:35:36 PM PDT 24 May 21 12:36:09 PM PDT 24 75400323 ps
T72 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.441043296 May 21 12:35:16 PM PDT 24 May 21 12:35:45 PM PDT 24 16779790 ps
T1319 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3595978657 May 21 12:35:15 PM PDT 24 May 21 12:35:45 PM PDT 24 179620452 ps
T1320 /workspace/coverage/cover_reg_top/30.uart_intr_test.2293048878 May 21 12:35:36 PM PDT 24 May 21 12:36:07 PM PDT 24 12383412 ps

Test location /workspace/coverage/default/258.uart_fifo_reset.123714039
Short name T8
Test name
Test status
Simulation time 15668577610 ps
CPU time 32.96 seconds
Started May 21 12:43:00 PM PDT 24
Finished May 21 12:43:35 PM PDT 24
Peak memory 200416 kb
Host smart-28d7434f-d338-4e86-a37b-2d979fe25102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123714039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.123714039
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2934818592
Short name T14
Test name
Test status
Simulation time 105002750972 ps
CPU time 804.23 seconds
Started May 21 12:40:51 PM PDT 24
Finished May 21 12:54:25 PM PDT 24
Peak memory 225428 kb
Host smart-acd5e906-a3c9-4645-ab14-16499210ee9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934818592 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2934818592
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1749277499
Short name T21
Test name
Test status
Simulation time 703596552025 ps
CPU time 720.68 seconds
Started May 21 12:42:03 PM PDT 24
Finished May 21 12:54:07 PM PDT 24
Peak memory 225464 kb
Host smart-13cacccb-bcd7-4215-a501-6440cbe7ea74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749277499 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1749277499
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2574986043
Short name T25
Test name
Test status
Simulation time 85738398666 ps
CPU time 1708.36 seconds
Started May 21 12:42:11 PM PDT 24
Finished May 21 01:10:44 PM PDT 24
Peak memory 233028 kb
Host smart-0cfebac1-de3f-4133-b01f-6d98b6b1e871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574986043 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2574986043
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_stress_all.3571555142
Short name T119
Test name
Test status
Simulation time 367811168735 ps
CPU time 356.07 seconds
Started May 21 12:39:46 PM PDT 24
Finished May 21 12:45:52 PM PDT 24
Peak memory 200472 kb
Host smart-5cfd60ec-cf0d-45bd-b1f8-76a34d44aa91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571555142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3571555142
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all.3414861844
Short name T137
Test name
Test status
Simulation time 464644000782 ps
CPU time 344.19 seconds
Started May 21 12:40:37 PM PDT 24
Finished May 21 12:46:30 PM PDT 24
Peak memory 200464 kb
Host smart-efec3a3e-d49f-4525-a36d-4b32b0910913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414861844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3414861844
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3376265982
Short name T24
Test name
Test status
Simulation time 64533813021 ps
CPU time 383.24 seconds
Started May 21 12:42:12 PM PDT 24
Finished May 21 12:48:40 PM PDT 24
Peak memory 216992 kb
Host smart-be55a441-3dd8-44ee-8698-46743db7bfbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376265982 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3376265982
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_stress_all.184352950
Short name T280
Test name
Test status
Simulation time 204300140855 ps
CPU time 436.34 seconds
Started May 21 12:41:13 PM PDT 24
Finished May 21 12:48:35 PM PDT 24
Peak memory 200480 kb
Host smart-98f7e2a1-10aa-441a-a46d-46be7af54949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184352950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.184352950
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1997299438
Short name T50
Test name
Test status
Simulation time 199345332114 ps
CPU time 305.23 seconds
Started May 21 12:42:11 PM PDT 24
Finished May 21 12:47:21 PM PDT 24
Peak memory 217208 kb
Host smart-5defbb00-bebc-4aae-ac2c-0730cc16d975
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997299438 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1997299438
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.611236126
Short name T107
Test name
Test status
Simulation time 227369272585 ps
CPU time 688.36 seconds
Started May 21 12:42:05 PM PDT 24
Finished May 21 12:53:36 PM PDT 24
Peak memory 216980 kb
Host smart-c1c432f1-d81f-4dc2-82c2-acf2314d36c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611236126 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.611236126
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1133065643
Short name T97
Test name
Test status
Simulation time 36446476 ps
CPU time 0.76 seconds
Started May 21 12:39:27 PM PDT 24
Finished May 21 12:39:37 PM PDT 24
Peak memory 219004 kb
Host smart-9eff3b5e-ca6e-4520-80cf-73af26fb1b36
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133065643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1133065643
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2818453014
Short name T264
Test name
Test status
Simulation time 36205996594 ps
CPU time 1195.01 seconds
Started May 21 12:41:59 PM PDT 24
Finished May 21 01:01:56 PM PDT 24
Peak memory 217208 kb
Host smart-b7675ab5-3a3b-44b5-8d7e-5e880d979779
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818453014 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2818453014
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3193608254
Short name T343
Test name
Test status
Simulation time 49489815 ps
CPU time 0.56 seconds
Started May 21 12:39:58 PM PDT 24
Finished May 21 12:40:07 PM PDT 24
Peak memory 195804 kb
Host smart-73acc389-cc3c-4d15-954a-63f406500421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193608254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3193608254
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_noise_filter.243255464
Short name T9
Test name
Test status
Simulation time 203366871407 ps
CPU time 75.2 seconds
Started May 21 12:40:40 PM PDT 24
Finished May 21 12:42:04 PM PDT 24
Peak memory 199420 kb
Host smart-e95ce25b-44e7-43db-b709-96b508b13d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243255464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.243255464
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_stress_all.235876578
Short name T19
Test name
Test status
Simulation time 258589446680 ps
CPU time 392.05 seconds
Started May 21 12:40:12 PM PDT 24
Finished May 21 12:46:48 PM PDT 24
Peak memory 200516 kb
Host smart-865353f9-d92e-4f06-a562-6de8063b4c62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235876578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.235876578
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3220367371
Short name T52
Test name
Test status
Simulation time 138842368460 ps
CPU time 286.01 seconds
Started May 21 12:41:13 PM PDT 24
Finished May 21 12:46:05 PM PDT 24
Peak memory 200536 kb
Host smart-e79a716d-4e1f-46d2-b612-139f02e72fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220367371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3220367371
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_stress_all.601664764
Short name T118
Test name
Test status
Simulation time 282988368393 ps
CPU time 318.72 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:46:24 PM PDT 24
Peak memory 200476 kb
Host smart-8542a618-ea6b-43ee-bc6a-96d11951055d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601664764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.601664764
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all.2191352521
Short name T279
Test name
Test status
Simulation time 246657559376 ps
CPU time 103.02 seconds
Started May 21 12:40:18 PM PDT 24
Finished May 21 12:42:06 PM PDT 24
Peak memory 200468 kb
Host smart-72844673-3811-4ae4-bf7e-b28e6eca7e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191352521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2191352521
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.797092591
Short name T88
Test name
Test status
Simulation time 171766466 ps
CPU time 1.3 seconds
Started May 21 12:35:17 PM PDT 24
Finished May 21 12:35:48 PM PDT 24
Peak memory 199284 kb
Host smart-abfb79f5-819a-4efb-baa3-1032f5afcd08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797092591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.797092591
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2967060718
Short name T161
Test name
Test status
Simulation time 344996888113 ps
CPU time 866.31 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:56:32 PM PDT 24
Peak memory 217280 kb
Host smart-1e8f6bd5-fb7b-4a54-a303-5128d384057b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967060718 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2967060718
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2536709647
Short name T248
Test name
Test status
Simulation time 112634712524 ps
CPU time 1094.82 seconds
Started May 21 12:39:41 PM PDT 24
Finished May 21 12:58:06 PM PDT 24
Peak memory 200472 kb
Host smart-e2933d7a-6bbb-4896-ba82-886437add477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2536709647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2536709647
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3627398423
Short name T135
Test name
Test status
Simulation time 182796803710 ps
CPU time 203.29 seconds
Started May 21 12:42:01 PM PDT 24
Finished May 21 12:45:28 PM PDT 24
Peak memory 200376 kb
Host smart-e3603345-d4d0-4664-97af-d69ada8038f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627398423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3627398423
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1047359321
Short name T38
Test name
Test status
Simulation time 71975815732 ps
CPU time 695 seconds
Started May 21 12:42:08 PM PDT 24
Finished May 21 12:53:46 PM PDT 24
Peak memory 216672 kb
Host smart-baaf035b-141c-412f-beeb-ea974f3aadd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047359321 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1047359321
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3404974672
Short name T133
Test name
Test status
Simulation time 73855367178 ps
CPU time 27.38 seconds
Started May 21 12:42:18 PM PDT 24
Finished May 21 12:42:49 PM PDT 24
Peak memory 200416 kb
Host smart-90dc38ca-12dc-4435-af64-1f0fd939a48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404974672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3404974672
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all.1195936039
Short name T140
Test name
Test status
Simulation time 515451889636 ps
CPU time 83.83 seconds
Started May 21 12:40:32 PM PDT 24
Finished May 21 12:42:03 PM PDT 24
Peak memory 200452 kb
Host smart-5c38ace4-f000-4901-bf4b-348e617a943e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195936039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1195936039
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all.769050219
Short name T15
Test name
Test status
Simulation time 24476703099 ps
CPU time 25.02 seconds
Started May 21 12:40:18 PM PDT 24
Finished May 21 12:40:48 PM PDT 24
Peak memory 200332 kb
Host smart-6e9bf220-e6e4-4ddb-b151-82b0bd70ceca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769050219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.769050219
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4215620029
Short name T80
Test name
Test status
Simulation time 76026687 ps
CPU time 0.66 seconds
Started May 21 12:35:20 PM PDT 24
Finished May 21 12:35:50 PM PDT 24
Peak memory 196660 kb
Host smart-cb30e007-bfa6-4ac7-a3c5-0136270cfd20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215620029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.4215620029
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.951972994
Short name T70
Test name
Test status
Simulation time 46638604 ps
CPU time 0.65 seconds
Started May 21 12:35:17 PM PDT 24
Finished May 21 12:35:47 PM PDT 24
Peak memory 195424 kb
Host smart-04f65f08-e038-4fcd-b7f0-f80473808972
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951972994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.951972994
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/default/7.uart_stress_all.1439829094
Short name T159
Test name
Test status
Simulation time 311071351475 ps
CPU time 214.26 seconds
Started May 21 12:39:38 PM PDT 24
Finished May 21 12:43:22 PM PDT 24
Peak memory 200412 kb
Host smart-c907e27e-19e2-42d1-b6a6-5cb8e7530531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439829094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1439829094
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3579705670
Short name T93
Test name
Test status
Simulation time 523368774 ps
CPU time 1.37 seconds
Started May 21 12:35:28 PM PDT 24
Finished May 21 12:36:01 PM PDT 24
Peak memory 199172 kb
Host smart-f3e1440a-99e3-4aaa-a307-ca8daf16da74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579705670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3579705670
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/16.uart_stress_all.600843289
Short name T46
Test name
Test status
Simulation time 220293887961 ps
CPU time 81.53 seconds
Started May 21 12:40:03 PM PDT 24
Finished May 21 12:41:29 PM PDT 24
Peak memory 200472 kb
Host smart-5674628f-09df-43e2-bab2-d4265703dddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600843289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.600843289
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2568457221
Short name T163
Test name
Test status
Simulation time 98504090821 ps
CPU time 313.46 seconds
Started May 21 12:42:29 PM PDT 24
Finished May 21 12:47:43 PM PDT 24
Peak memory 200420 kb
Host smart-f3adb27d-d4f0-4798-93e9-70d35c507541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568457221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2568457221
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all.442133691
Short name T138
Test name
Test status
Simulation time 278629009678 ps
CPU time 406.15 seconds
Started May 21 12:41:26 PM PDT 24
Finished May 21 12:48:17 PM PDT 24
Peak memory 200896 kb
Host smart-d6c40692-5cdd-4bbe-b591-b763428fde45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442133691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.442133691
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.946529966
Short name T230
Test name
Test status
Simulation time 46858960638 ps
CPU time 22.59 seconds
Started May 21 12:42:50 PM PDT 24
Finished May 21 12:43:17 PM PDT 24
Peak memory 200472 kb
Host smart-f5325cbc-e5b5-4e1d-b8da-04b284715a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946529966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.946529966
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1129598577
Short name T193
Test name
Test status
Simulation time 389979248675 ps
CPU time 1306.14 seconds
Started May 21 12:42:10 PM PDT 24
Finished May 21 01:04:00 PM PDT 24
Peak memory 233140 kb
Host smart-24224785-b3eb-41e2-9102-2c429f624974
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129598577 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1129598577
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1201092591
Short name T437
Test name
Test status
Simulation time 51958591369 ps
CPU time 17.31 seconds
Started May 21 12:43:07 PM PDT 24
Finished May 21 12:43:29 PM PDT 24
Peak memory 200376 kb
Host smart-ef0e9eb2-a17d-4dec-90a4-01ef7522d21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201092591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1201092591
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all.1603898429
Short name T250
Test name
Test status
Simulation time 208397250916 ps
CPU time 353.5 seconds
Started May 21 12:40:41 PM PDT 24
Finished May 21 12:46:45 PM PDT 24
Peak memory 209568 kb
Host smart-4fe09376-ac4d-4f78-b0cf-794225c0f0d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603898429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1603898429
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2199123893
Short name T36
Test name
Test status
Simulation time 209583584232 ps
CPU time 700.89 seconds
Started May 21 12:39:13 PM PDT 24
Finished May 21 12:51:04 PM PDT 24
Peak memory 225416 kb
Host smart-9968d338-9ac3-496f-bf76-9d5e1da871ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199123893 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2199123893
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3362764995
Short name T222
Test name
Test status
Simulation time 112444621050 ps
CPU time 82.9 seconds
Started May 21 12:42:23 PM PDT 24
Finished May 21 12:43:50 PM PDT 24
Peak memory 200396 kb
Host smart-53822d15-4e82-412e-b724-16ce648c5bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362764995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3362764995
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.1056723439
Short name T144
Test name
Test status
Simulation time 81036060842 ps
CPU time 127.69 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:41:31 PM PDT 24
Peak memory 200436 kb
Host smart-10bb6ddd-e898-4262-beb8-8f62e3e17297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056723439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1056723439
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1702952115
Short name T4
Test name
Test status
Simulation time 75251259167 ps
CPU time 75.13 seconds
Started May 21 12:41:00 PM PDT 24
Finished May 21 12:42:23 PM PDT 24
Peak memory 200468 kb
Host smart-f01986ce-822b-4d11-922e-3ae34b136fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702952115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1702952115
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2948799780
Short name T220
Test name
Test status
Simulation time 972049284943 ps
CPU time 1883.2 seconds
Started May 21 12:41:06 PM PDT 24
Finished May 21 01:12:36 PM PDT 24
Peak memory 233440 kb
Host smart-429bb269-30d9-4dae-85a3-3c33008e3af5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948799780 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2948799780
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1060139295
Short name T109
Test name
Test status
Simulation time 83031882755 ps
CPU time 875.88 seconds
Started May 21 12:41:11 PM PDT 24
Finished May 21 12:55:53 PM PDT 24
Peak memory 217128 kb
Host smart-036e9332-788d-45a9-b8f4-9c3edeca6c92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060139295 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1060139295
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.1214443424
Short name T120
Test name
Test status
Simulation time 106112018525 ps
CPU time 288.32 seconds
Started May 21 12:39:59 PM PDT 24
Finished May 21 12:44:54 PM PDT 24
Peak memory 200448 kb
Host smart-c0adf5e6-61b3-4098-96f0-5056db61c72e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214443424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1214443424
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1707935738
Short name T309
Test name
Test status
Simulation time 152288592084 ps
CPU time 325.28 seconds
Started May 21 12:42:36 PM PDT 24
Finished May 21 12:48:02 PM PDT 24
Peak memory 200412 kb
Host smart-8550b2b1-d123-4bb7-bcf2-68f868b05108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707935738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1707935738
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1103432111
Short name T55
Test name
Test status
Simulation time 53017795245 ps
CPU time 28.28 seconds
Started May 21 12:42:43 PM PDT 24
Finished May 21 12:43:14 PM PDT 24
Peak memory 200504 kb
Host smart-5f478374-0753-40c4-9483-1fc48f8c9c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103432111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1103432111
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2732718639
Short name T221
Test name
Test status
Simulation time 15781080736 ps
CPU time 23.11 seconds
Started May 21 12:42:51 PM PDT 24
Finished May 21 12:43:18 PM PDT 24
Peak memory 200512 kb
Host smart-fecca661-2bb8-4538-8189-db5cfd353950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732718639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2732718639
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.4024466508
Short name T182
Test name
Test status
Simulation time 44220850993 ps
CPU time 78.61 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:43:24 PM PDT 24
Peak memory 200516 kb
Host smart-fc3a63bb-c6f4-4bc8-a2f2-2fedc61a3006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024466508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.4024466508
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3233034073
Short name T131
Test name
Test status
Simulation time 60152060438 ps
CPU time 22.99 seconds
Started May 21 12:42:29 PM PDT 24
Finished May 21 12:42:54 PM PDT 24
Peak memory 200428 kb
Host smart-21b5272d-343a-43e9-b175-b76b5e24bb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233034073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3233034073
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.561593300
Short name T172
Test name
Test status
Simulation time 130591591323 ps
CPU time 120.22 seconds
Started May 21 12:42:51 PM PDT 24
Finished May 21 12:44:55 PM PDT 24
Peak memory 200504 kb
Host smart-c2709f31-9df3-4a68-b2e3-e1ac610403c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561593300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.561593300
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.1351555918
Short name T905
Test name
Test status
Simulation time 147564594697 ps
CPU time 66.79 seconds
Started May 21 12:40:40 PM PDT 24
Finished May 21 12:41:56 PM PDT 24
Peak memory 200416 kb
Host smart-30d96ecf-2fde-4980-a2cd-72304e1c4e36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351555918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1351555918
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.17848996
Short name T229
Test name
Test status
Simulation time 81604193244 ps
CPU time 545.49 seconds
Started May 21 12:40:46 PM PDT 24
Finished May 21 12:50:01 PM PDT 24
Peak memory 213672 kb
Host smart-a23a9c5a-046f-4144-ab3f-d0dd1103ae54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17848996 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.17848996
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3435231066
Short name T141
Test name
Test status
Simulation time 172872406776 ps
CPU time 111.95 seconds
Started May 21 12:41:39 PM PDT 24
Finished May 21 12:43:34 PM PDT 24
Peak memory 200680 kb
Host smart-b5ee7dcb-8c57-4cf9-b1f8-70080282abe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435231066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3435231066
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.4274160325
Short name T358
Test name
Test status
Simulation time 57872281253 ps
CPU time 100.21 seconds
Started May 21 12:42:11 PM PDT 24
Finished May 21 12:43:56 PM PDT 24
Peak memory 200388 kb
Host smart-0be3c353-e245-4d8e-8618-0b716e62e094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274160325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.4274160325
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2611873325
Short name T1082
Test name
Test status
Simulation time 22250629243 ps
CPU time 64.1 seconds
Started May 21 12:42:11 PM PDT 24
Finished May 21 12:43:20 PM PDT 24
Peak memory 199948 kb
Host smart-dba2a39b-f2f5-445c-8e2e-9063488383d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611873325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2611873325
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.936326817
Short name T150
Test name
Test status
Simulation time 69431731650 ps
CPU time 130.7 seconds
Started May 21 12:42:19 PM PDT 24
Finished May 21 12:44:33 PM PDT 24
Peak memory 200492 kb
Host smart-ba1d0f77-bd0f-4bcf-a374-8cdecc84d17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936326817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.936326817
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.773114209
Short name T225
Test name
Test status
Simulation time 68313076286 ps
CPU time 33.28 seconds
Started May 21 12:42:21 PM PDT 24
Finished May 21 12:42:57 PM PDT 24
Peak memory 200360 kb
Host smart-b0cd79d9-3d0b-45be-b2b6-7b9278068efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773114209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.773114209
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1322677549
Short name T235
Test name
Test status
Simulation time 131934012265 ps
CPU time 84.1 seconds
Started May 21 12:42:25 PM PDT 24
Finished May 21 12:43:52 PM PDT 24
Peak memory 200432 kb
Host smart-21eda39f-91f6-497d-b3f8-a51e2c65cf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322677549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1322677549
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2145355162
Short name T53
Test name
Test status
Simulation time 25933878212 ps
CPU time 343.58 seconds
Started May 21 12:39:56 PM PDT 24
Finished May 21 12:45:48 PM PDT 24
Peak memory 208776 kb
Host smart-652de739-7dfa-419b-a772-535a765740dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145355162 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2145355162
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3569464378
Short name T210
Test name
Test status
Simulation time 54809451383 ps
CPU time 23.71 seconds
Started May 21 12:42:23 PM PDT 24
Finished May 21 12:42:50 PM PDT 24
Peak memory 200456 kb
Host smart-57ca16b6-5cc5-487f-83c2-ef711a58ec2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569464378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3569464378
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3360254206
Short name T115
Test name
Test status
Simulation time 61769906652 ps
CPU time 101.17 seconds
Started May 21 12:42:30 PM PDT 24
Finished May 21 12:44:13 PM PDT 24
Peak memory 200440 kb
Host smart-6ae718ac-526c-4fe4-8f59-0822c09141d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360254206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3360254206
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.4093839728
Short name T200
Test name
Test status
Simulation time 57765084216 ps
CPU time 33.77 seconds
Started May 21 12:42:31 PM PDT 24
Finished May 21 12:43:06 PM PDT 24
Peak memory 200420 kb
Host smart-b96d9697-baad-48d5-875a-a5c7fe894e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093839728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.4093839728
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2955274631
Short name T147
Test name
Test status
Simulation time 66816062304 ps
CPU time 47.94 seconds
Started May 21 12:42:33 PM PDT 24
Finished May 21 12:43:22 PM PDT 24
Peak memory 200480 kb
Host smart-6516b3a0-ae52-46ad-a97b-c6640c416a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955274631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2955274631
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3482493367
Short name T169
Test name
Test status
Simulation time 68325653076 ps
CPU time 137.03 seconds
Started May 21 12:42:39 PM PDT 24
Finished May 21 12:44:57 PM PDT 24
Peak memory 200424 kb
Host smart-11544027-e68b-44da-b608-e2e2f882bc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482493367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3482493367
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.789370885
Short name T148
Test name
Test status
Simulation time 85430895103 ps
CPU time 126.16 seconds
Started May 21 12:42:35 PM PDT 24
Finished May 21 12:44:42 PM PDT 24
Peak memory 200516 kb
Host smart-8da7c0cf-160e-4c46-a1c7-d0a02b7eddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789370885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.789370885
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1543143471
Short name T177
Test name
Test status
Simulation time 136877983683 ps
CPU time 537.65 seconds
Started May 21 12:42:35 PM PDT 24
Finished May 21 12:51:33 PM PDT 24
Peak memory 200488 kb
Host smart-b48a97a0-b1b6-42fc-977d-bb770ce06a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543143471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1543143471
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2537158491
Short name T12
Test name
Test status
Simulation time 44766630347 ps
CPU time 16.65 seconds
Started May 21 12:42:42 PM PDT 24
Finished May 21 12:43:01 PM PDT 24
Peak memory 200496 kb
Host smart-4fd8f9b0-e5ac-4f62-b2b0-2c6aa7dc2c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537158491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2537158491
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.3248960071
Short name T213
Test name
Test status
Simulation time 22071445977 ps
CPU time 38.23 seconds
Started May 21 12:42:49 PM PDT 24
Finished May 21 12:43:29 PM PDT 24
Peak memory 200276 kb
Host smart-025bdc3a-a248-42c3-9fa3-3015a3811f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248960071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3248960071
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2160803193
Short name T232
Test name
Test status
Simulation time 84045378042 ps
CPU time 36.25 seconds
Started May 21 12:42:51 PM PDT 24
Finished May 21 12:43:31 PM PDT 24
Peak memory 200472 kb
Host smart-c82ad2a9-975a-4760-bcc6-91cea8e65a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160803193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2160803193
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2924555274
Short name T237
Test name
Test status
Simulation time 59968354644 ps
CPU time 54.43 seconds
Started May 21 12:42:58 PM PDT 24
Finished May 21 12:43:54 PM PDT 24
Peak memory 200652 kb
Host smart-c9cba359-940c-4750-bcba-cc5c2651ec35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924555274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2924555274
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3076714387
Short name T217
Test name
Test status
Simulation time 126628068853 ps
CPU time 207.48 seconds
Started May 21 12:40:34 PM PDT 24
Finished May 21 12:44:08 PM PDT 24
Peak memory 200648 kb
Host smart-8fa4a34a-4055-47e6-94f4-0812098ded01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076714387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3076714387
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.369792717
Short name T205
Test name
Test status
Simulation time 21205590526 ps
CPU time 27 seconds
Started May 21 12:41:26 PM PDT 24
Finished May 21 12:41:58 PM PDT 24
Peak memory 200272 kb
Host smart-9fa43cb1-6ead-406a-a627-34dbc41c3b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369792717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.369792717
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all.2843363715
Short name T226
Test name
Test status
Simulation time 115199214205 ps
CPU time 44.06 seconds
Started May 21 12:41:26 PM PDT 24
Finished May 21 12:42:15 PM PDT 24
Peak memory 200616 kb
Host smart-5143bb0b-dff4-4821-ab39-166d1a33496d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843363715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2843363715
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2730445276
Short name T149
Test name
Test status
Simulation time 43425978807 ps
CPU time 80.51 seconds
Started May 21 12:41:50 PM PDT 24
Finished May 21 12:43:13 PM PDT 24
Peak memory 200540 kb
Host smart-5a67b4c7-472f-43f4-8f45-9d8d4bbc3161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730445276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2730445276
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1312908303
Short name T146
Test name
Test status
Simulation time 131934514484 ps
CPU time 113.89 seconds
Started May 21 12:42:10 PM PDT 24
Finished May 21 12:44:09 PM PDT 24
Peak memory 200476 kb
Host smart-025affbb-638f-4315-ae2a-cd22e2efc39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312908303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1312908303
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.636484969
Short name T236
Test name
Test status
Simulation time 111558249784 ps
CPU time 54.71 seconds
Started May 21 12:42:10 PM PDT 24
Finished May 21 12:43:09 PM PDT 24
Peak memory 200476 kb
Host smart-53cf26e8-0d4a-4bfd-aedc-df1384598fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636484969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.636484969
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1343647393
Short name T1303
Test name
Test status
Simulation time 21339044 ps
CPU time 0.65 seconds
Started May 21 12:35:10 PM PDT 24
Finished May 21 12:35:37 PM PDT 24
Peak memory 194664 kb
Host smart-6fb08135-873f-4cd9-bfdc-bc7708d8a9cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343647393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1343647393
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1372571341
Short name T1258
Test name
Test status
Simulation time 730076733 ps
CPU time 1.47 seconds
Started May 21 12:35:34 PM PDT 24
Finished May 21 12:36:06 PM PDT 24
Peak memory 197000 kb
Host smart-b9374d3a-0820-4f22-a12b-db34f7afbb97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372571341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1372571341
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.500735117
Short name T1241
Test name
Test status
Simulation time 42991705 ps
CPU time 0.6 seconds
Started May 21 12:35:14 PM PDT 24
Finished May 21 12:35:41 PM PDT 24
Peak memory 195172 kb
Host smart-60718212-9b7f-429d-bf39-5a1f6b335a08
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500735117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.500735117
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2797525232
Short name T1222
Test name
Test status
Simulation time 45629856 ps
CPU time 0.76 seconds
Started May 21 12:35:20 PM PDT 24
Finished May 21 12:35:51 PM PDT 24
Peak memory 199612 kb
Host smart-c3cf1507-b66f-4126-8a34-18a0f8b83db5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797525232 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2797525232
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2946137045
Short name T76
Test name
Test status
Simulation time 20493618 ps
CPU time 0.56 seconds
Started May 21 12:35:16 PM PDT 24
Finished May 21 12:35:46 PM PDT 24
Peak memory 195232 kb
Host smart-29fe9e91-4c98-4d0a-8683-cd3b225e3695
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946137045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2946137045
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.613934561
Short name T1232
Test name
Test status
Simulation time 20094054 ps
CPU time 0.55 seconds
Started May 21 12:35:11 PM PDT 24
Finished May 21 12:35:38 PM PDT 24
Peak memory 194080 kb
Host smart-445596da-4c07-4149-aed3-63bd67db2a95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613934561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.613934561
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3535817472
Short name T1186
Test name
Test status
Simulation time 244471462 ps
CPU time 1.38 seconds
Started May 21 12:35:17 PM PDT 24
Finished May 21 12:35:47 PM PDT 24
Peak memory 199816 kb
Host smart-4f8afdb0-63ab-4f42-8524-2d42a76129b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535817472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3535817472
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1314968802
Short name T1235
Test name
Test status
Simulation time 69089845 ps
CPU time 0.68 seconds
Started May 21 12:35:21 PM PDT 24
Finished May 21 12:35:53 PM PDT 24
Peak memory 194548 kb
Host smart-0861c9bd-c835-4c57-bfa3-bd7647b6249c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314968802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1314968802
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3083417245
Short name T1197
Test name
Test status
Simulation time 397200969 ps
CPU time 1.47 seconds
Started May 21 12:35:19 PM PDT 24
Finished May 21 12:35:51 PM PDT 24
Peak memory 197428 kb
Host smart-5f98c1a8-701d-40ea-b636-182d8a59ce14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083417245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3083417245
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2867879696
Short name T1238
Test name
Test status
Simulation time 15616648 ps
CPU time 0.57 seconds
Started May 21 12:35:16 PM PDT 24
Finished May 21 12:35:45 PM PDT 24
Peak memory 195100 kb
Host smart-ac5cb53a-2f4e-4c69-ba72-5d2c0f687cbe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867879696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2867879696
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3791289147
Short name T1290
Test name
Test status
Simulation time 109480957 ps
CPU time 1.37 seconds
Started May 21 12:35:22 PM PDT 24
Finished May 21 12:35:54 PM PDT 24
Peak memory 199820 kb
Host smart-8a86f83a-6e17-48da-b0e9-027cee1583c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791289147 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3791289147
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3899326335
Short name T1217
Test name
Test status
Simulation time 40682583 ps
CPU time 0.58 seconds
Started May 21 12:35:14 PM PDT 24
Finished May 21 12:35:41 PM PDT 24
Peak memory 195252 kb
Host smart-6c0950fa-4404-484e-97da-99f35cd3816d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899326335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3899326335
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2292956163
Short name T1261
Test name
Test status
Simulation time 13724834 ps
CPU time 0.56 seconds
Started May 21 12:35:30 PM PDT 24
Finished May 21 12:36:01 PM PDT 24
Peak memory 194176 kb
Host smart-5bb94f82-5bf3-4762-b553-4414e8106270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292956163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2292956163
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3966379823
Short name T1263
Test name
Test status
Simulation time 43586063 ps
CPU time 0.61 seconds
Started May 21 12:35:21 PM PDT 24
Finished May 21 12:35:52 PM PDT 24
Peak memory 195364 kb
Host smart-4f8c2125-bf44-46d7-9f5a-08e9e84b2a7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966379823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3966379823
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2897042744
Short name T1187
Test name
Test status
Simulation time 28129645 ps
CPU time 1.38 seconds
Started May 21 12:35:18 PM PDT 24
Finished May 21 12:35:48 PM PDT 24
Peak memory 199828 kb
Host smart-23743549-ad9b-40f6-8bf4-9f3c99a85aab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897042744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2897042744
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3060551400
Short name T90
Test name
Test status
Simulation time 91278609 ps
CPU time 0.93 seconds
Started May 21 12:35:21 PM PDT 24
Finished May 21 12:35:53 PM PDT 24
Peak memory 198680 kb
Host smart-bec51773-3cb7-4683-8f97-0dda6ecffe8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060551400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3060551400
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.217711550
Short name T1286
Test name
Test status
Simulation time 54269546 ps
CPU time 0.65 seconds
Started May 21 12:35:38 PM PDT 24
Finished May 21 12:36:08 PM PDT 24
Peak memory 197396 kb
Host smart-927087c7-4bfe-4b37-82aa-821093467ee1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217711550 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.217711550
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3359921437
Short name T1233
Test name
Test status
Simulation time 15599416 ps
CPU time 0.59 seconds
Started May 21 12:35:29 PM PDT 24
Finished May 21 12:36:00 PM PDT 24
Peak memory 194184 kb
Host smart-9d943da0-9ea4-45e5-97c6-fa62c34daa5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359921437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3359921437
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1490283917
Short name T1289
Test name
Test status
Simulation time 88968456 ps
CPU time 0.74 seconds
Started May 21 12:35:36 PM PDT 24
Finished May 21 12:36:07 PM PDT 24
Peak memory 196748 kb
Host smart-6f3810ce-402e-4ec8-aab1-673146eb2db1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490283917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1490283917
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1424251821
Short name T1298
Test name
Test status
Simulation time 437778154 ps
CPU time 1.94 seconds
Started May 21 12:35:24 PM PDT 24
Finished May 21 12:35:57 PM PDT 24
Peak memory 199920 kb
Host smart-68a2297d-4206-4182-b322-81111f2a2991
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424251821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1424251821
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.119479102
Short name T1267
Test name
Test status
Simulation time 55265404 ps
CPU time 0.92 seconds
Started May 21 12:35:35 PM PDT 24
Finished May 21 12:36:07 PM PDT 24
Peak memory 198580 kb
Host smart-3b695969-8156-4d27-8e6c-75b4ca2da77f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119479102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.119479102
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.949068787
Short name T1280
Test name
Test status
Simulation time 22787978 ps
CPU time 0.7 seconds
Started May 21 12:35:29 PM PDT 24
Finished May 21 12:36:00 PM PDT 24
Peak memory 197488 kb
Host smart-55ea0a5c-bfe1-4b99-8c3b-1b1a0b68504f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949068787 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.949068787
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1465189087
Short name T74
Test name
Test status
Simulation time 28406643 ps
CPU time 0.59 seconds
Started May 21 12:35:47 PM PDT 24
Finished May 21 12:36:19 PM PDT 24
Peak memory 195304 kb
Host smart-52776c19-89d5-4663-b246-ac28533aba8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465189087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1465189087
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.4078020303
Short name T1300
Test name
Test status
Simulation time 44051292 ps
CPU time 0.55 seconds
Started May 21 12:35:34 PM PDT 24
Finished May 21 12:36:05 PM PDT 24
Peak memory 194144 kb
Host smart-f6cdcb02-92cc-4e5e-a314-4f7f4f4cc844
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078020303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.4078020303
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3472354502
Short name T1211
Test name
Test status
Simulation time 14579379 ps
CPU time 0.62 seconds
Started May 21 12:35:38 PM PDT 24
Finished May 21 12:36:09 PM PDT 24
Peak memory 195584 kb
Host smart-7559f1fa-9e15-4dad-ae65-ae7c678b2f6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472354502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3472354502
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.243421037
Short name T1268
Test name
Test status
Simulation time 146655817 ps
CPU time 1.99 seconds
Started May 21 12:35:19 PM PDT 24
Finished May 21 12:35:51 PM PDT 24
Peak memory 199948 kb
Host smart-b2773a07-4efb-49f2-a888-e8b95519e71e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243421037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.243421037
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.79794037
Short name T92
Test name
Test status
Simulation time 147340603 ps
CPU time 0.93 seconds
Started May 21 12:35:29 PM PDT 24
Finished May 21 12:36:01 PM PDT 24
Peak memory 198860 kb
Host smart-8f2414d6-a892-49da-86b4-ae94d9d7328a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79794037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.79794037
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.489894990
Short name T1270
Test name
Test status
Simulation time 75951389 ps
CPU time 0.75 seconds
Started May 21 12:35:45 PM PDT 24
Finished May 21 12:36:15 PM PDT 24
Peak memory 199184 kb
Host smart-767dcc09-e066-47c9-aad1-a213c2c960d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489894990 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.489894990
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.4277557169
Short name T78
Test name
Test status
Simulation time 39237068 ps
CPU time 0.58 seconds
Started May 21 12:35:20 PM PDT 24
Finished May 21 12:35:52 PM PDT 24
Peak memory 195356 kb
Host smart-3d75d421-6f77-44db-9612-1df9182845e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277557169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.4277557169
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3812414630
Short name T1302
Test name
Test status
Simulation time 40845133 ps
CPU time 0.56 seconds
Started May 21 12:35:34 PM PDT 24
Finished May 21 12:36:05 PM PDT 24
Peak memory 194232 kb
Host smart-0919ed17-3d06-4178-b43c-7a6b840b6395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812414630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3812414630
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1596816621
Short name T1313
Test name
Test status
Simulation time 44241908 ps
CPU time 0.63 seconds
Started May 21 12:35:39 PM PDT 24
Finished May 21 12:36:10 PM PDT 24
Peak memory 195472 kb
Host smart-120aa9ce-42b8-4353-bb49-78705adb8f86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596816621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1596816621
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2152909909
Short name T1307
Test name
Test status
Simulation time 67322593 ps
CPU time 1.42 seconds
Started May 21 12:35:28 PM PDT 24
Finished May 21 12:36:00 PM PDT 24
Peak memory 199924 kb
Host smart-460a9cfd-b4e2-486a-b9ee-7a41036d257d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152909909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2152909909
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.857311023
Short name T91
Test name
Test status
Simulation time 313209819 ps
CPU time 1.32 seconds
Started May 21 12:35:35 PM PDT 24
Finished May 21 12:36:07 PM PDT 24
Peak memory 199168 kb
Host smart-7cf54d04-224e-43c1-80be-3789251828b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857311023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.857311023
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1594688185
Short name T1213
Test name
Test status
Simulation time 18850491 ps
CPU time 0.87 seconds
Started May 21 12:35:21 PM PDT 24
Finished May 21 12:35:52 PM PDT 24
Peak memory 199680 kb
Host smart-374da68b-0154-4926-9aed-38eeb9aeaa56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594688185 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1594688185
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3937376099
Short name T1209
Test name
Test status
Simulation time 25555656 ps
CPU time 0.66 seconds
Started May 21 12:35:31 PM PDT 24
Finished May 21 12:36:02 PM PDT 24
Peak memory 195384 kb
Host smart-2a10c931-1d7e-4f15-b873-349c15767260
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937376099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3937376099
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2817353142
Short name T1212
Test name
Test status
Simulation time 44701646 ps
CPU time 0.61 seconds
Started May 21 12:35:39 PM PDT 24
Finished May 21 12:36:10 PM PDT 24
Peak memory 194200 kb
Host smart-fc78c83e-ae6a-4cf7-8da8-d9251912390f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817353142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2817353142
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.922328594
Short name T1237
Test name
Test status
Simulation time 44992144 ps
CPU time 0.69 seconds
Started May 21 12:35:41 PM PDT 24
Finished May 21 12:36:12 PM PDT 24
Peak memory 196520 kb
Host smart-1dfceb06-11f8-48d0-9d28-dabfcac7c9be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922328594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.922328594
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3152332958
Short name T1282
Test name
Test status
Simulation time 73818162 ps
CPU time 1.08 seconds
Started May 21 12:35:29 PM PDT 24
Finished May 21 12:36:01 PM PDT 24
Peak memory 199848 kb
Host smart-de00db34-8d58-4e07-94cc-bf24a3811956
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152332958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3152332958
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2329300253
Short name T122
Test name
Test status
Simulation time 41681817 ps
CPU time 0.9 seconds
Started May 21 12:35:40 PM PDT 24
Finished May 21 12:36:11 PM PDT 24
Peak memory 198732 kb
Host smart-34d05fb9-e665-44d0-8629-8ad63c4bab20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329300253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2329300253
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3812698298
Short name T1189
Test name
Test status
Simulation time 110371156 ps
CPU time 0.78 seconds
Started May 21 12:35:30 PM PDT 24
Finished May 21 12:36:01 PM PDT 24
Peak memory 199728 kb
Host smart-0bbe245f-cca0-4fd4-8941-436d24eff319
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812698298 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3812698298
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2762592058
Short name T1259
Test name
Test status
Simulation time 53029502 ps
CPU time 0.58 seconds
Started May 21 12:35:24 PM PDT 24
Finished May 21 12:35:56 PM PDT 24
Peak memory 195252 kb
Host smart-83039112-f159-45f5-a665-60748dc65fbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762592058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2762592058
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3290222504
Short name T1190
Test name
Test status
Simulation time 158785363 ps
CPU time 0.57 seconds
Started May 21 12:35:34 PM PDT 24
Finished May 21 12:36:05 PM PDT 24
Peak memory 194252 kb
Host smart-a4bd16e3-710e-457d-98c1-e6aafcafcc93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290222504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3290222504
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.80074384
Short name T1246
Test name
Test status
Simulation time 70143524 ps
CPU time 0.64 seconds
Started May 21 12:35:30 PM PDT 24
Finished May 21 12:36:01 PM PDT 24
Peak memory 195568 kb
Host smart-b96a6baf-17a4-4052-b5a4-f34393fe5eb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80074384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_
outstanding.80074384
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1377268935
Short name T1199
Test name
Test status
Simulation time 184984076 ps
CPU time 1.27 seconds
Started May 21 12:35:23 PM PDT 24
Finished May 21 12:35:55 PM PDT 24
Peak memory 199880 kb
Host smart-581a1fc8-f29e-4248-99d6-e159e42975f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377268935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1377268935
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.112637959
Short name T1273
Test name
Test status
Simulation time 91216998 ps
CPU time 1.28 seconds
Started May 21 12:35:28 PM PDT 24
Finished May 21 12:36:00 PM PDT 24
Peak memory 199136 kb
Host smart-f8d8916e-7e67-4df0-bbab-2bb35c612cd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112637959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.112637959
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3461122959
Short name T1272
Test name
Test status
Simulation time 72610257 ps
CPU time 0.93 seconds
Started May 21 12:35:35 PM PDT 24
Finished May 21 12:36:07 PM PDT 24
Peak memory 199740 kb
Host smart-1a4c226b-57d8-489e-ab1c-5b9e1f3f45d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461122959 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3461122959
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1969525598
Short name T1210
Test name
Test status
Simulation time 168379894 ps
CPU time 0.61 seconds
Started May 21 12:35:36 PM PDT 24
Finished May 21 12:36:07 PM PDT 24
Peak memory 195512 kb
Host smart-41d989a5-59ad-472c-b02f-9f5fb124d451
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969525598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1969525598
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.701340755
Short name T1301
Test name
Test status
Simulation time 47423200 ps
CPU time 0.55 seconds
Started May 21 12:35:34 PM PDT 24
Finished May 21 12:36:06 PM PDT 24
Peak memory 194252 kb
Host smart-e5707d37-b060-48b3-a8aa-3f74ffd67604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701340755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.701340755
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.589550473
Short name T1234
Test name
Test status
Simulation time 135660102 ps
CPU time 0.71 seconds
Started May 21 12:35:42 PM PDT 24
Finished May 21 12:36:13 PM PDT 24
Peak memory 197520 kb
Host smart-511f5a62-4b19-4e89-a30e-0e659ccc26b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589550473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.589550473
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3149279836
Short name T1196
Test name
Test status
Simulation time 155014221 ps
CPU time 1.08 seconds
Started May 21 12:35:19 PM PDT 24
Finished May 21 12:35:50 PM PDT 24
Peak memory 199864 kb
Host smart-8e3bad67-2cba-4080-b419-19dd5ce38177
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149279836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3149279836
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.15651723
Short name T95
Test name
Test status
Simulation time 49659332 ps
CPU time 0.94 seconds
Started May 21 12:35:40 PM PDT 24
Finished May 21 12:36:13 PM PDT 24
Peak memory 198720 kb
Host smart-9222b182-67df-401d-896f-fe3e1610a4ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15651723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.15651723
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2291903509
Short name T1200
Test name
Test status
Simulation time 56529650 ps
CPU time 0.83 seconds
Started May 21 12:35:27 PM PDT 24
Finished May 21 12:35:59 PM PDT 24
Peak memory 199708 kb
Host smart-3f786505-a4da-4282-aa67-a8dc390928d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291903509 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2291903509
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2739477280
Short name T73
Test name
Test status
Simulation time 73128108 ps
CPU time 0.64 seconds
Started May 21 12:35:29 PM PDT 24
Finished May 21 12:36:00 PM PDT 24
Peak memory 195492 kb
Host smart-5c1a786d-8004-403c-b8bb-466fbdae4fa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739477280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2739477280
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2068889354
Short name T1315
Test name
Test status
Simulation time 16022387 ps
CPU time 0.56 seconds
Started May 21 12:35:41 PM PDT 24
Finished May 21 12:36:12 PM PDT 24
Peak memory 194236 kb
Host smart-3215402c-1ac6-4a21-949b-df416434c3ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068889354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2068889354
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1157219271
Short name T1294
Test name
Test status
Simulation time 22684683 ps
CPU time 0.68 seconds
Started May 21 12:35:32 PM PDT 24
Finished May 21 12:36:03 PM PDT 24
Peak memory 196680 kb
Host smart-03f996c2-eb29-4c8b-bcca-fd2d6c493a57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157219271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1157219271
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.4113000823
Short name T1285
Test name
Test status
Simulation time 40369858 ps
CPU time 2.06 seconds
Started May 21 12:35:30 PM PDT 24
Finished May 21 12:36:02 PM PDT 24
Peak memory 199952 kb
Host smart-92836e2c-7142-4e68-8d5d-be626eb13608
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113000823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.4113000823
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.72409442
Short name T1216
Test name
Test status
Simulation time 41108421 ps
CPU time 0.95 seconds
Started May 21 12:35:35 PM PDT 24
Finished May 21 12:36:06 PM PDT 24
Peak memory 198628 kb
Host smart-c4093524-0385-4459-8650-bbbb4ee72785
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72409442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.72409442
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4229671472
Short name T1311
Test name
Test status
Simulation time 230954433 ps
CPU time 0.86 seconds
Started May 21 12:35:39 PM PDT 24
Finished May 21 12:36:10 PM PDT 24
Peak memory 199716 kb
Host smart-406c6689-5a66-4167-a804-9058f34c95d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229671472 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.4229671472
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1112449612
Short name T1220
Test name
Test status
Simulation time 15105660 ps
CPU time 0.59 seconds
Started May 21 12:35:25 PM PDT 24
Finished May 21 12:35:56 PM PDT 24
Peak memory 195248 kb
Host smart-157236cb-6744-4339-9037-4ef708a507ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112449612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1112449612
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2195137650
Short name T1230
Test name
Test status
Simulation time 26352047 ps
CPU time 0.56 seconds
Started May 21 12:35:36 PM PDT 24
Finished May 21 12:36:07 PM PDT 24
Peak memory 194192 kb
Host smart-91028db9-864d-4d72-bc90-287d420e97f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195137650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2195137650
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4072763538
Short name T1269
Test name
Test status
Simulation time 20399103 ps
CPU time 0.63 seconds
Started May 21 12:35:26 PM PDT 24
Finished May 21 12:35:58 PM PDT 24
Peak memory 194716 kb
Host smart-0ca8b3c1-4405-490a-8b49-db0be71773e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072763538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.4072763538
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2714501661
Short name T1253
Test name
Test status
Simulation time 434031353 ps
CPU time 2.1 seconds
Started May 21 12:35:37 PM PDT 24
Finished May 21 12:36:09 PM PDT 24
Peak memory 199924 kb
Host smart-6d50e43b-214d-4a02-b27e-6c32dad97354
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714501661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2714501661
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.283254429
Short name T89
Test name
Test status
Simulation time 93287211 ps
CPU time 1.34 seconds
Started May 21 12:35:37 PM PDT 24
Finished May 21 12:36:08 PM PDT 24
Peak memory 199056 kb
Host smart-6e68f5f7-dd03-43b6-a16f-e7a399f8c790
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283254429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.283254429
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.4248542691
Short name T1305
Test name
Test status
Simulation time 18634638 ps
CPU time 0.86 seconds
Started May 21 12:35:41 PM PDT 24
Finished May 21 12:36:12 PM PDT 24
Peak memory 199576 kb
Host smart-b905c8f3-673d-410f-9a99-e961737260cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248542691 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.4248542691
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2375365255
Short name T75
Test name
Test status
Simulation time 44386023 ps
CPU time 0.61 seconds
Started May 21 12:35:29 PM PDT 24
Finished May 21 12:36:01 PM PDT 24
Peak memory 195452 kb
Host smart-6e9496f2-14bd-45bf-aa54-f3442f5ab7c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375365255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2375365255
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1164231201
Short name T1255
Test name
Test status
Simulation time 39031460 ps
CPU time 0.56 seconds
Started May 21 12:35:28 PM PDT 24
Finished May 21 12:35:59 PM PDT 24
Peak memory 194312 kb
Host smart-bb48680e-3189-4292-badb-e1add88b4c11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164231201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1164231201
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2363461551
Short name T83
Test name
Test status
Simulation time 46363174 ps
CPU time 0.71 seconds
Started May 21 12:35:42 PM PDT 24
Finished May 21 12:36:12 PM PDT 24
Peak memory 196700 kb
Host smart-5bd34486-ed8a-43ad-97de-c48e7cae64a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363461551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2363461551
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.4075275590
Short name T1201
Test name
Test status
Simulation time 228266348 ps
CPU time 1.23 seconds
Started May 21 12:35:34 PM PDT 24
Finished May 21 12:36:06 PM PDT 24
Peak memory 199888 kb
Host smart-79a915f2-2615-4d8d-b8e5-491dfa716e20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075275590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.4075275590
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1124964271
Short name T123
Test name
Test status
Simulation time 322273150 ps
CPU time 1.26 seconds
Started May 21 12:35:29 PM PDT 24
Finished May 21 12:36:01 PM PDT 24
Peak memory 198984 kb
Host smart-c022dd3a-eb5f-4b62-acd7-3d621c392d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124964271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1124964271
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1610788796
Short name T1206
Test name
Test status
Simulation time 21174890 ps
CPU time 0.7 seconds
Started May 21 12:35:36 PM PDT 24
Finished May 21 12:36:08 PM PDT 24
Peak memory 198444 kb
Host smart-eb092903-fbf0-416c-b105-dd4a678528e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610788796 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1610788796
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3082515326
Short name T85
Test name
Test status
Simulation time 45607513 ps
CPU time 0.54 seconds
Started May 21 12:35:40 PM PDT 24
Finished May 21 12:36:11 PM PDT 24
Peak memory 195124 kb
Host smart-3e327c5e-9157-4e63-a5fe-cf6ebf30a77f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082515326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3082515326
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1668846598
Short name T1297
Test name
Test status
Simulation time 14446763 ps
CPU time 0.62 seconds
Started May 21 12:35:43 PM PDT 24
Finished May 21 12:36:13 PM PDT 24
Peak memory 194240 kb
Host smart-e9df5c5b-3542-4e62-9ec4-b1d7e1defb96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668846598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1668846598
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2339285709
Short name T1248
Test name
Test status
Simulation time 107752586 ps
CPU time 0.81 seconds
Started May 21 12:35:31 PM PDT 24
Finished May 21 12:36:02 PM PDT 24
Peak memory 196404 kb
Host smart-ee6f1aa5-9060-4c3b-abd7-038807bd1a02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339285709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2339285709
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.829902131
Short name T1195
Test name
Test status
Simulation time 92882371 ps
CPU time 1.19 seconds
Started May 21 12:35:30 PM PDT 24
Finished May 21 12:36:02 PM PDT 24
Peak memory 199916 kb
Host smart-e830543b-3a0b-4781-8019-9660708f48f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829902131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.829902131
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2487113439
Short name T87
Test name
Test status
Simulation time 49614887 ps
CPU time 0.96 seconds
Started May 21 12:35:37 PM PDT 24
Finished May 21 12:36:08 PM PDT 24
Peak memory 198776 kb
Host smart-cb949ecc-a20d-4b7c-acee-ef67b4133f0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487113439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2487113439
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.441043296
Short name T72
Test name
Test status
Simulation time 16779790 ps
CPU time 0.76 seconds
Started May 21 12:35:16 PM PDT 24
Finished May 21 12:35:45 PM PDT 24
Peak memory 196180 kb
Host smart-b7107da6-8679-4a7b-a185-26e10f188545
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441043296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.441043296
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1175144997
Short name T1228
Test name
Test status
Simulation time 676514097 ps
CPU time 1.62 seconds
Started May 21 12:35:15 PM PDT 24
Finished May 21 12:35:45 PM PDT 24
Peak memory 197568 kb
Host smart-05c1f2c5-ab33-4965-b004-94da2f238ef9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175144997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1175144997
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2587966962
Short name T1283
Test name
Test status
Simulation time 22329739 ps
CPU time 0.58 seconds
Started May 21 12:35:15 PM PDT 24
Finished May 21 12:35:43 PM PDT 24
Peak memory 195268 kb
Host smart-f0e82ad1-ea4b-4134-9643-6c8161a0e8fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587966962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2587966962
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2919303701
Short name T1281
Test name
Test status
Simulation time 86414487 ps
CPU time 1.21 seconds
Started May 21 12:35:19 PM PDT 24
Finished May 21 12:35:50 PM PDT 24
Peak memory 199904 kb
Host smart-03a7c747-e5ce-4b61-b10e-437af0a6312b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919303701 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2919303701
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3196857197
Short name T1247
Test name
Test status
Simulation time 56014927 ps
CPU time 0.59 seconds
Started May 21 12:35:19 PM PDT 24
Finished May 21 12:35:49 PM PDT 24
Peak memory 195344 kb
Host smart-25c7ae15-19df-4483-ae2b-22c7f64a42d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196857197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3196857197
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3059326685
Short name T1214
Test name
Test status
Simulation time 12418793 ps
CPU time 0.55 seconds
Started May 21 12:35:25 PM PDT 24
Finished May 21 12:35:57 PM PDT 24
Peak memory 194196 kb
Host smart-9d98d919-c3d3-46e6-a9af-b5943854a8ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059326685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3059326685
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.868176782
Short name T77
Test name
Test status
Simulation time 15764680 ps
CPU time 0.7 seconds
Started May 21 12:35:16 PM PDT 24
Finished May 21 12:35:46 PM PDT 24
Peak memory 196736 kb
Host smart-1a5b6986-d992-4fa8-bd58-ac377ed6f978
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868176782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.868176782
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.426831895
Short name T1231
Test name
Test status
Simulation time 116296896 ps
CPU time 2.21 seconds
Started May 21 12:35:25 PM PDT 24
Finished May 21 12:35:58 PM PDT 24
Peak memory 199832 kb
Host smart-00b697f9-8818-44c1-a836-0bdc1b4efee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426831895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.426831895
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.748395098
Short name T86
Test name
Test status
Simulation time 54699316 ps
CPU time 0.95 seconds
Started May 21 12:35:15 PM PDT 24
Finished May 21 12:35:43 PM PDT 24
Peak memory 198816 kb
Host smart-fef9f39d-f3ef-4f5f-b626-f65a19c4d8cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748395098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.748395098
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.885052609
Short name T1191
Test name
Test status
Simulation time 34686637 ps
CPU time 0.55 seconds
Started May 21 12:35:42 PM PDT 24
Finished May 21 12:36:12 PM PDT 24
Peak memory 194136 kb
Host smart-d3872385-3d6c-4905-a798-05e5d944dfbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885052609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.885052609
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2943711284
Short name T1188
Test name
Test status
Simulation time 15322903 ps
CPU time 0.57 seconds
Started May 21 12:35:29 PM PDT 24
Finished May 21 12:36:00 PM PDT 24
Peak memory 194240 kb
Host smart-9ebffd84-4df6-46f5-a295-f53cb1a422a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943711284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2943711284
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1432316490
Short name T1262
Test name
Test status
Simulation time 38476161 ps
CPU time 0.62 seconds
Started May 21 12:35:31 PM PDT 24
Finished May 21 12:36:02 PM PDT 24
Peak memory 194248 kb
Host smart-809160af-1730-45a1-8181-57040016adea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432316490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1432316490
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.677744047
Short name T1208
Test name
Test status
Simulation time 12846350 ps
CPU time 0.57 seconds
Started May 21 12:35:45 PM PDT 24
Finished May 21 12:36:15 PM PDT 24
Peak memory 194140 kb
Host smart-e00afde9-4047-4cdc-a7df-98969fb12c1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677744047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.677744047
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2432629272
Short name T1288
Test name
Test status
Simulation time 42794767 ps
CPU time 0.54 seconds
Started May 21 12:35:34 PM PDT 24
Finished May 21 12:36:05 PM PDT 24
Peak memory 194140 kb
Host smart-787da32b-fd3a-42b9-bb30-7b706acf17b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432629272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2432629272
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2375316865
Short name T1204
Test name
Test status
Simulation time 155317219 ps
CPU time 0.59 seconds
Started May 21 12:35:39 PM PDT 24
Finished May 21 12:36:10 PM PDT 24
Peak memory 194224 kb
Host smart-dc0577d9-14bd-48df-8706-ca24edde7079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375316865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2375316865
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1151906833
Short name T1192
Test name
Test status
Simulation time 14091195 ps
CPU time 0.57 seconds
Started May 21 12:35:48 PM PDT 24
Finished May 21 12:36:19 PM PDT 24
Peak memory 194456 kb
Host smart-288ad89c-8dbc-4ffe-aa9a-1f5fbaa5cdea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151906833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1151906833
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.4070620223
Short name T1215
Test name
Test status
Simulation time 15561378 ps
CPU time 0.57 seconds
Started May 21 12:35:34 PM PDT 24
Finished May 21 12:36:05 PM PDT 24
Peak memory 194452 kb
Host smart-21be108d-9f96-4a1c-8593-02a514594b4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070620223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.4070620223
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2150822873
Short name T1240
Test name
Test status
Simulation time 14702457 ps
CPU time 0.57 seconds
Started May 21 12:35:45 PM PDT 24
Finished May 21 12:36:15 PM PDT 24
Peak memory 194144 kb
Host smart-9a6d204d-6817-47bf-8294-21aaa2088182
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150822873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2150822873
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.612445844
Short name T1287
Test name
Test status
Simulation time 16854901 ps
CPU time 0.57 seconds
Started May 21 12:35:29 PM PDT 24
Finished May 21 12:36:00 PM PDT 24
Peak memory 194192 kb
Host smart-5a5b1493-212d-4ede-b05d-31c3140eacb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612445844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.612445844
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.284596173
Short name T1239
Test name
Test status
Simulation time 63395790 ps
CPU time 0.77 seconds
Started May 21 12:35:18 PM PDT 24
Finished May 21 12:35:48 PM PDT 24
Peak memory 196100 kb
Host smart-99438cab-5f6d-469e-b639-cf02994af570
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284596173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.284596173
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.260922463
Short name T1276
Test name
Test status
Simulation time 136306823 ps
CPU time 1.4 seconds
Started May 21 12:35:16 PM PDT 24
Finished May 21 12:35:46 PM PDT 24
Peak memory 197060 kb
Host smart-77f5683a-350f-4648-862e-8f484f00b376
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260922463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.260922463
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.150502228
Short name T1309
Test name
Test status
Simulation time 16730022 ps
CPU time 0.56 seconds
Started May 21 12:35:20 PM PDT 24
Finished May 21 12:35:52 PM PDT 24
Peak memory 195244 kb
Host smart-08c05af0-8adf-4663-a740-2b478d32de1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150502228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.150502228
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3008886411
Short name T1316
Test name
Test status
Simulation time 100472212 ps
CPU time 0.87 seconds
Started May 21 12:35:17 PM PDT 24
Finished May 21 12:35:47 PM PDT 24
Peak memory 199676 kb
Host smart-1ad181c2-480d-477d-ab1b-09bcb1649f87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008886411 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3008886411
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3057978918
Short name T1271
Test name
Test status
Simulation time 16933147 ps
CPU time 0.56 seconds
Started May 21 12:35:19 PM PDT 24
Finished May 21 12:35:49 PM PDT 24
Peak memory 195172 kb
Host smart-eb229424-3a92-41ef-9109-71d2c0e6abb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057978918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3057978918
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1110131809
Short name T1252
Test name
Test status
Simulation time 89270404 ps
CPU time 0.62 seconds
Started May 21 12:35:15 PM PDT 24
Finished May 21 12:35:43 PM PDT 24
Peak memory 194172 kb
Host smart-4664cbd8-4532-4202-a6cc-0df168a15bff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110131809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1110131809
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2822687257
Short name T81
Test name
Test status
Simulation time 12646372 ps
CPU time 0.65 seconds
Started May 21 12:35:21 PM PDT 24
Finished May 21 12:35:52 PM PDT 24
Peak memory 196508 kb
Host smart-6c4c8262-9e84-47f4-bec5-9cc55c5f2f72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822687257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2822687257
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3595978657
Short name T1319
Test name
Test status
Simulation time 179620452 ps
CPU time 1.15 seconds
Started May 21 12:35:15 PM PDT 24
Finished May 21 12:35:45 PM PDT 24
Peak memory 199840 kb
Host smart-4734ac30-9666-4387-a7fa-9977190d7b19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595978657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3595978657
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.4231472047
Short name T1299
Test name
Test status
Simulation time 227160624 ps
CPU time 0.91 seconds
Started May 21 12:35:24 PM PDT 24
Finished May 21 12:35:56 PM PDT 24
Peak memory 198992 kb
Host smart-26f79cd9-cd98-42e4-9ba5-81fcd6922507
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231472047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.4231472047
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2293048878
Short name T1320
Test name
Test status
Simulation time 12383412 ps
CPU time 0.62 seconds
Started May 21 12:35:36 PM PDT 24
Finished May 21 12:36:07 PM PDT 24
Peak memory 194248 kb
Host smart-22e08acb-93c5-4670-976a-fa3c6118fbd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293048878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2293048878
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2171265167
Short name T1277
Test name
Test status
Simulation time 63976044 ps
CPU time 0.55 seconds
Started May 21 12:35:38 PM PDT 24
Finished May 21 12:36:09 PM PDT 24
Peak memory 194228 kb
Host smart-451a7fbd-689f-4cdb-bc03-193ab07e1215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171265167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2171265167
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.855803492
Short name T1318
Test name
Test status
Simulation time 75400323 ps
CPU time 0.57 seconds
Started May 21 12:35:36 PM PDT 24
Finished May 21 12:36:09 PM PDT 24
Peak memory 194244 kb
Host smart-ab899fc9-5f2f-4d43-ab01-d69d3ebd40db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855803492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.855803492
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1111821701
Short name T1317
Test name
Test status
Simulation time 42366075 ps
CPU time 0.56 seconds
Started May 21 12:35:35 PM PDT 24
Finished May 21 12:36:06 PM PDT 24
Peak memory 194152 kb
Host smart-cd6a4991-c5b4-4b9c-9fbe-1d8f912cfd1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111821701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1111821701
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2729518764
Short name T1292
Test name
Test status
Simulation time 14204879 ps
CPU time 0.58 seconds
Started May 21 12:35:47 PM PDT 24
Finished May 21 12:36:19 PM PDT 24
Peak memory 194160 kb
Host smart-ee63f976-204b-4e38-9ff7-e8859bf28ca1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729518764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2729518764
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3934317080
Short name T1245
Test name
Test status
Simulation time 54058627 ps
CPU time 0.57 seconds
Started May 21 12:35:36 PM PDT 24
Finished May 21 12:36:07 PM PDT 24
Peak memory 194248 kb
Host smart-63398e7a-229b-4573-b219-3b06b5d6c99f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934317080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3934317080
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1983218447
Short name T1194
Test name
Test status
Simulation time 26861789 ps
CPU time 0.55 seconds
Started May 21 12:35:39 PM PDT 24
Finished May 21 12:36:10 PM PDT 24
Peak memory 194196 kb
Host smart-7f81badb-d99d-4ae2-8ddd-549e3206858c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983218447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1983218447
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.321216807
Short name T1275
Test name
Test status
Simulation time 15713713 ps
CPU time 0.56 seconds
Started May 21 12:35:35 PM PDT 24
Finished May 21 12:36:07 PM PDT 24
Peak memory 194152 kb
Host smart-5e130871-a8f5-49df-b098-cabd0c0dee97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321216807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.321216807
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.34035876
Short name T1225
Test name
Test status
Simulation time 15502076 ps
CPU time 0.55 seconds
Started May 21 12:35:46 PM PDT 24
Finished May 21 12:36:16 PM PDT 24
Peak memory 194224 kb
Host smart-0e4d3263-dbcc-4722-be91-bd17dfa5c2b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34035876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.34035876
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3951921579
Short name T1223
Test name
Test status
Simulation time 32380426 ps
CPU time 0.57 seconds
Started May 21 12:35:47 PM PDT 24
Finished May 21 12:36:19 PM PDT 24
Peak memory 194160 kb
Host smart-6d398b94-cf18-4520-b7f6-ebe23115916e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951921579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3951921579
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.62561320
Short name T1202
Test name
Test status
Simulation time 29914871 ps
CPU time 0.77 seconds
Started May 21 12:35:16 PM PDT 24
Finished May 21 12:35:45 PM PDT 24
Peak memory 196108 kb
Host smart-992cc3dd-da0c-4c81-a423-5c0f2b1ed6de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62561320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.62561320
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3110343654
Short name T1278
Test name
Test status
Simulation time 68870648 ps
CPU time 1.41 seconds
Started May 21 12:35:18 PM PDT 24
Finished May 21 12:35:48 PM PDT 24
Peak memory 197688 kb
Host smart-b8bcc279-d6a0-4c7a-b383-ead5a64d3cab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110343654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3110343654
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.4236329250
Short name T71
Test name
Test status
Simulation time 16160294 ps
CPU time 0.63 seconds
Started May 21 12:35:21 PM PDT 24
Finished May 21 12:35:52 PM PDT 24
Peak memory 195232 kb
Host smart-99f22e37-6266-4e6e-ad93-af56448732ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236329250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.4236329250
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4136435052
Short name T1244
Test name
Test status
Simulation time 15479709 ps
CPU time 0.65 seconds
Started May 21 12:35:21 PM PDT 24
Finished May 21 12:35:52 PM PDT 24
Peak memory 197604 kb
Host smart-5ce67e4e-29de-4a1c-b53b-1a2c71996fcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136435052 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.4136435052
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2087447056
Short name T1184
Test name
Test status
Simulation time 14218635 ps
CPU time 0.55 seconds
Started May 21 12:35:20 PM PDT 24
Finished May 21 12:35:51 PM PDT 24
Peak memory 195232 kb
Host smart-a56a28df-0121-4466-b2bd-2a0cbee048d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087447056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2087447056
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1840605055
Short name T1219
Test name
Test status
Simulation time 144868127 ps
CPU time 0.57 seconds
Started May 21 12:35:23 PM PDT 24
Finished May 21 12:35:55 PM PDT 24
Peak memory 194260 kb
Host smart-e0902b35-b566-4ba7-b55c-029b6da210ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840605055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1840605055
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1032076930
Short name T1304
Test name
Test status
Simulation time 301276182 ps
CPU time 0.78 seconds
Started May 21 12:35:20 PM PDT 24
Finished May 21 12:35:52 PM PDT 24
Peak memory 196104 kb
Host smart-82d6d6a4-6815-4deb-93d7-6fdf4105182b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032076930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1032076930
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.998844374
Short name T1256
Test name
Test status
Simulation time 125118744 ps
CPU time 2.04 seconds
Started May 21 12:35:17 PM PDT 24
Finished May 21 12:35:48 PM PDT 24
Peak memory 199884 kb
Host smart-4ba9b673-232a-437f-b460-03b88692288f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998844374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.998844374
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1070317769
Short name T1306
Test name
Test status
Simulation time 45371044 ps
CPU time 0.95 seconds
Started May 21 12:35:18 PM PDT 24
Finished May 21 12:35:49 PM PDT 24
Peak memory 198848 kb
Host smart-812a0fcf-e627-4af6-a281-1feb0104db45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070317769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1070317769
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2314498632
Short name T1295
Test name
Test status
Simulation time 14047812 ps
CPU time 0.57 seconds
Started May 21 12:35:39 PM PDT 24
Finished May 21 12:36:10 PM PDT 24
Peak memory 194172 kb
Host smart-a24ae748-14cc-4c71-96cb-c5df120accbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314498632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2314498632
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2316925857
Short name T1242
Test name
Test status
Simulation time 23525477 ps
CPU time 0.61 seconds
Started May 21 12:35:40 PM PDT 24
Finished May 21 12:36:11 PM PDT 24
Peak memory 194220 kb
Host smart-c6d7549b-c157-4e70-bbdd-cbbfdbdeda6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316925857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2316925857
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.4173606191
Short name T1226
Test name
Test status
Simulation time 13311581 ps
CPU time 0.57 seconds
Started May 21 12:35:42 PM PDT 24
Finished May 21 12:36:12 PM PDT 24
Peak memory 194180 kb
Host smart-a5a8a3e5-cf7c-47e3-9c36-b6398cf44ad6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173606191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.4173606191
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3071413598
Short name T1243
Test name
Test status
Simulation time 27734198 ps
CPU time 0.55 seconds
Started May 21 12:35:45 PM PDT 24
Finished May 21 12:36:15 PM PDT 24
Peak memory 194224 kb
Host smart-00e97d73-ac07-4396-b0c3-569c263846a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071413598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3071413598
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3400621601
Short name T1254
Test name
Test status
Simulation time 22654897 ps
CPU time 0.55 seconds
Started May 21 12:35:51 PM PDT 24
Finished May 21 12:36:22 PM PDT 24
Peak memory 193960 kb
Host smart-9562d606-a0ba-4385-a6d6-1ca37f738471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400621601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3400621601
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2596523962
Short name T1257
Test name
Test status
Simulation time 41802078 ps
CPU time 0.54 seconds
Started May 21 12:35:49 PM PDT 24
Finished May 21 12:36:20 PM PDT 24
Peak memory 193960 kb
Host smart-2f663b1b-16ac-44bd-baf3-d2931a4e3507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596523962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2596523962
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2895940988
Short name T1185
Test name
Test status
Simulation time 70193469 ps
CPU time 0.58 seconds
Started May 21 12:35:38 PM PDT 24
Finished May 21 12:36:08 PM PDT 24
Peak memory 194516 kb
Host smart-481c37f2-2a33-4921-9055-3399411e05f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895940988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2895940988
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1045226028
Short name T1229
Test name
Test status
Simulation time 35166756 ps
CPU time 0.56 seconds
Started May 21 12:35:50 PM PDT 24
Finished May 21 12:36:20 PM PDT 24
Peak memory 194156 kb
Host smart-d6cc80b2-b3d5-4694-b045-7d05891b7233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045226028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1045226028
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1618381300
Short name T1310
Test name
Test status
Simulation time 15096178 ps
CPU time 0.56 seconds
Started May 21 12:35:42 PM PDT 24
Finished May 21 12:36:13 PM PDT 24
Peak memory 194312 kb
Host smart-0d3372d6-bf0c-40de-8adf-e0f7c23b7bd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618381300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1618381300
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.434824439
Short name T1293
Test name
Test status
Simulation time 14888599 ps
CPU time 0.54 seconds
Started May 21 12:35:42 PM PDT 24
Finished May 21 12:36:12 PM PDT 24
Peak memory 194144 kb
Host smart-52ba54c6-fa62-49a4-921f-ebc103e4cadd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434824439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.434824439
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1220645772
Short name T1249
Test name
Test status
Simulation time 130928599 ps
CPU time 0.67 seconds
Started May 21 12:35:18 PM PDT 24
Finished May 21 12:35:48 PM PDT 24
Peak memory 197664 kb
Host smart-a4432f50-56d6-44ca-9971-0b8a91e5393f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220645772 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1220645772
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.883346408
Short name T79
Test name
Test status
Simulation time 36021705 ps
CPU time 0.58 seconds
Started May 21 12:35:22 PM PDT 24
Finished May 21 12:35:54 PM PDT 24
Peak memory 195212 kb
Host smart-e4a36e45-e58a-4810-a294-24fe7d5225e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883346408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.883346408
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.4248262397
Short name T1221
Test name
Test status
Simulation time 26457010 ps
CPU time 0.62 seconds
Started May 21 12:35:17 PM PDT 24
Finished May 21 12:35:46 PM PDT 24
Peak memory 194168 kb
Host smart-70bdc6f3-5d32-4ae0-af6e-c26e7c052129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248262397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.4248262397
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3563137077
Short name T84
Test name
Test status
Simulation time 34237818 ps
CPU time 0.73 seconds
Started May 21 12:35:15 PM PDT 24
Finished May 21 12:35:43 PM PDT 24
Peak memory 196936 kb
Host smart-eb597094-1178-4799-a414-7124aabb537d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563137077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3563137077
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1737871974
Short name T1284
Test name
Test status
Simulation time 189964580 ps
CPU time 1.82 seconds
Started May 21 12:35:26 PM PDT 24
Finished May 21 12:35:59 PM PDT 24
Peak memory 199836 kb
Host smart-75fbd66a-04f6-4a88-a12d-8661433416da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737871974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1737871974
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3395742836
Short name T1279
Test name
Test status
Simulation time 92192004 ps
CPU time 0.91 seconds
Started May 21 12:35:20 PM PDT 24
Finished May 21 12:35:51 PM PDT 24
Peak memory 198832 kb
Host smart-84f65652-6c38-4ded-990a-d48419987973
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395742836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3395742836
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3871731156
Short name T1291
Test name
Test status
Simulation time 24070504 ps
CPU time 0.78 seconds
Started May 21 12:35:16 PM PDT 24
Finished May 21 12:35:46 PM PDT 24
Peak memory 198828 kb
Host smart-88db0274-7558-4f5d-a688-686a199c3ad1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871731156 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3871731156
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3587151402
Short name T82
Test name
Test status
Simulation time 42214328 ps
CPU time 0.6 seconds
Started May 21 12:35:14 PM PDT 24
Finished May 21 12:35:41 PM PDT 24
Peak memory 195284 kb
Host smart-a0baacc7-487e-4254-a1fc-b968c9b4f7da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587151402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3587151402
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2941268048
Short name T1224
Test name
Test status
Simulation time 17670041 ps
CPU time 0.54 seconds
Started May 21 12:35:17 PM PDT 24
Finished May 21 12:35:47 PM PDT 24
Peak memory 194140 kb
Host smart-dc63fc73-4403-491f-a290-d6244d79da29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941268048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2941268048
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.781928276
Short name T1265
Test name
Test status
Simulation time 32221113 ps
CPU time 0.64 seconds
Started May 21 12:35:17 PM PDT 24
Finished May 21 12:35:46 PM PDT 24
Peak memory 195572 kb
Host smart-1bdb838e-7909-47a4-be9a-7fcc861a5159
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781928276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.781928276
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2413392564
Short name T1205
Test name
Test status
Simulation time 123716493 ps
CPU time 1.45 seconds
Started May 21 12:35:12 PM PDT 24
Finished May 21 12:35:40 PM PDT 24
Peak memory 199872 kb
Host smart-225ebbaf-970d-43bd-b13c-1bbcbc1794b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413392564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2413392564
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2058836175
Short name T1264
Test name
Test status
Simulation time 313830784 ps
CPU time 0.91 seconds
Started May 21 12:35:14 PM PDT 24
Finished May 21 12:35:42 PM PDT 24
Peak memory 198716 kb
Host smart-a92bd38e-71b3-42fe-8a68-323a44b514db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058836175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2058836175
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3713883776
Short name T1274
Test name
Test status
Simulation time 29820763 ps
CPU time 0.71 seconds
Started May 21 12:35:20 PM PDT 24
Finished May 21 12:35:51 PM PDT 24
Peak memory 198212 kb
Host smart-d70bfcb4-1576-40de-a600-373d72a29e58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713883776 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3713883776
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.4197900265
Short name T1198
Test name
Test status
Simulation time 39037792 ps
CPU time 0.55 seconds
Started May 21 12:35:20 PM PDT 24
Finished May 21 12:35:52 PM PDT 24
Peak memory 195232 kb
Host smart-4bd63df3-fda7-4e75-8283-3d044daac00a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197900265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4197900265
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1666871812
Short name T1251
Test name
Test status
Simulation time 51667286 ps
CPU time 0.58 seconds
Started May 21 12:35:23 PM PDT 24
Finished May 21 12:35:55 PM PDT 24
Peak memory 194196 kb
Host smart-e4418d32-fc22-482a-9876-c72a5a8d495e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666871812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1666871812
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1040497032
Short name T1312
Test name
Test status
Simulation time 51329092 ps
CPU time 0.73 seconds
Started May 21 12:35:21 PM PDT 24
Finished May 21 12:35:52 PM PDT 24
Peak memory 195828 kb
Host smart-645ee679-dc5b-49a8-a400-a8444e448729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040497032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1040497032
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2825202400
Short name T1193
Test name
Test status
Simulation time 1477180447 ps
CPU time 2.74 seconds
Started May 21 12:35:20 PM PDT 24
Finished May 21 12:35:54 PM PDT 24
Peak memory 199896 kb
Host smart-37ad14f4-d38e-4abf-8d2d-16db484dfaeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825202400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2825202400
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2865489032
Short name T94
Test name
Test status
Simulation time 67406783 ps
CPU time 1.24 seconds
Started May 21 12:35:27 PM PDT 24
Finished May 21 12:35:59 PM PDT 24
Peak memory 199096 kb
Host smart-12bd1be3-996c-4daa-859e-432768b48c08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865489032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2865489032
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3125468907
Short name T1203
Test name
Test status
Simulation time 87113265 ps
CPU time 0.76 seconds
Started May 21 12:35:39 PM PDT 24
Finished May 21 12:36:10 PM PDT 24
Peak memory 199596 kb
Host smart-370b10fe-64c6-47c4-a090-e96083d082b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125468907 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3125468907
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1911065656
Short name T1236
Test name
Test status
Simulation time 56074320 ps
CPU time 0.64 seconds
Started May 21 12:35:22 PM PDT 24
Finished May 21 12:35:54 PM PDT 24
Peak memory 195532 kb
Host smart-80311efa-b59b-47b0-9098-0b879e599347
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911065656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1911065656
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3468904126
Short name T1296
Test name
Test status
Simulation time 48959665 ps
CPU time 0.55 seconds
Started May 21 12:35:25 PM PDT 24
Finished May 21 12:35:57 PM PDT 24
Peak memory 194140 kb
Host smart-8d93a33d-bdca-4f6f-a693-436f8f40708e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468904126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3468904126
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.739833803
Short name T1314
Test name
Test status
Simulation time 77516871 ps
CPU time 0.64 seconds
Started May 21 12:35:36 PM PDT 24
Finished May 21 12:36:08 PM PDT 24
Peak memory 195508 kb
Host smart-657fe7a1-a7af-4ef3-8ac7-374622a867dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739833803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.739833803
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2475593474
Short name T1308
Test name
Test status
Simulation time 248587129 ps
CPU time 2.27 seconds
Started May 21 12:35:29 PM PDT 24
Finished May 21 12:36:02 PM PDT 24
Peak memory 199884 kb
Host smart-db84dcb6-19b3-4844-bce2-91232ab476d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475593474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2475593474
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3301989974
Short name T1266
Test name
Test status
Simulation time 149279974 ps
CPU time 0.91 seconds
Started May 21 12:35:27 PM PDT 24
Finished May 21 12:35:59 PM PDT 24
Peak memory 198864 kb
Host smart-1f4a7c87-9951-4d1b-a455-116b29b39623
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301989974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3301989974
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3884560804
Short name T1207
Test name
Test status
Simulation time 69494384 ps
CPU time 0.72 seconds
Started May 21 12:35:19 PM PDT 24
Finished May 21 12:35:50 PM PDT 24
Peak memory 198344 kb
Host smart-4a8adbff-1d38-470f-9833-459547fedee7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884560804 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3884560804
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1875323884
Short name T1250
Test name
Test status
Simulation time 20687753 ps
CPU time 0.59 seconds
Started May 21 12:35:30 PM PDT 24
Finished May 21 12:36:01 PM PDT 24
Peak memory 195180 kb
Host smart-dddc568c-fc79-452a-b03a-d597d5499810
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875323884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1875323884
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1994371557
Short name T1218
Test name
Test status
Simulation time 21899002 ps
CPU time 0.56 seconds
Started May 21 12:35:39 PM PDT 24
Finished May 21 12:36:10 PM PDT 24
Peak memory 194180 kb
Host smart-50bc4a41-8a1f-4341-98dc-b4a2ca3c8064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994371557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1994371557
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.174457397
Short name T1260
Test name
Test status
Simulation time 65975161 ps
CPU time 0.75 seconds
Started May 21 12:35:33 PM PDT 24
Finished May 21 12:36:04 PM PDT 24
Peak memory 196976 kb
Host smart-cafe70da-3c72-4a13-94d0-2740c625150d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174457397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.174457397
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.4252409270
Short name T1227
Test name
Test status
Simulation time 547650783 ps
CPU time 1.36 seconds
Started May 21 12:35:31 PM PDT 24
Finished May 21 12:36:06 PM PDT 24
Peak memory 199884 kb
Host smart-65cb3056-3fe3-4238-a3a7-61a5016d143d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252409270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.4252409270
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/default/0.uart_alert_test.158586417
Short name T1137
Test name
Test status
Simulation time 14151029 ps
CPU time 0.56 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:39:22 PM PDT 24
Peak memory 195836 kb
Host smart-2e423946-a7a7-42bf-bf59-b51b4324341a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158586417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.158586417
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.35585986
Short name T399
Test name
Test status
Simulation time 34358322416 ps
CPU time 78.63 seconds
Started May 21 12:39:15 PM PDT 24
Finished May 21 12:40:44 PM PDT 24
Peak memory 200432 kb
Host smart-7ea1b0a8-5c71-4d55-a6ee-cd1aa90d5bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35585986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.35585986
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.605510147
Short name T448
Test name
Test status
Simulation time 169917907663 ps
CPU time 50.13 seconds
Started May 21 12:39:16 PM PDT 24
Finished May 21 12:40:17 PM PDT 24
Peak memory 200540 kb
Host smart-22b056ac-36b7-4327-bea7-c84845f1a3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605510147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.605510147
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1623136048
Short name T777
Test name
Test status
Simulation time 7229976012 ps
CPU time 11.59 seconds
Started May 21 12:39:05 PM PDT 24
Finished May 21 12:39:27 PM PDT 24
Peak memory 199356 kb
Host smart-8798ac84-ddc8-4e92-ac9c-ee6a04a6e78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623136048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1623136048
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2884087683
Short name T381
Test name
Test status
Simulation time 35806039024 ps
CPU time 11.61 seconds
Started May 21 12:39:19 PM PDT 24
Finished May 21 12:39:41 PM PDT 24
Peak memory 200504 kb
Host smart-730cdf73-8678-4105-919b-8fe628cde8ef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884087683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2884087683
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.4230195081
Short name T1043
Test name
Test status
Simulation time 143940717970 ps
CPU time 219.85 seconds
Started May 21 12:39:31 PM PDT 24
Finished May 21 12:43:20 PM PDT 24
Peak memory 200448 kb
Host smart-4f60f7b9-96db-4c64-80b8-93aa58ff664b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4230195081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.4230195081
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1524922713
Short name T540
Test name
Test status
Simulation time 7133174369 ps
CPU time 7.13 seconds
Started May 21 12:39:20 PM PDT 24
Finished May 21 12:39:38 PM PDT 24
Peak memory 199716 kb
Host smart-2e285ae0-9c24-4d72-872a-ac4ada3401fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524922713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1524922713
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.4047651052
Short name T396
Test name
Test status
Simulation time 11590392434 ps
CPU time 4.8 seconds
Started May 21 12:39:18 PM PDT 24
Finished May 21 12:39:34 PM PDT 24
Peak memory 195100 kb
Host smart-95d1ed32-e180-4ad3-987a-c62a0fb9b9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047651052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.4047651052
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2499417737
Short name T1028
Test name
Test status
Simulation time 26039896816 ps
CPU time 634.24 seconds
Started May 21 12:39:25 PM PDT 24
Finished May 21 12:50:09 PM PDT 24
Peak memory 200388 kb
Host smart-302ba38a-6f39-4724-b9c4-565ee411136f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499417737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2499417737
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1122748965
Short name T633
Test name
Test status
Simulation time 2097289173 ps
CPU time 8.24 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:39:30 PM PDT 24
Peak memory 198496 kb
Host smart-936c201b-bcfe-4306-a00f-021fe0be4f8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1122748965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1122748965
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.706882740
Short name T112
Test name
Test status
Simulation time 67397595461 ps
CPU time 33.47 seconds
Started May 21 12:39:13 PM PDT 24
Finished May 21 12:39:57 PM PDT 24
Peak memory 200396 kb
Host smart-d0ea24f8-7949-42cb-9233-a6973666874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706882740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.706882740
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.4161572215
Short name T1161
Test name
Test status
Simulation time 37641426579 ps
CPU time 16.91 seconds
Started May 21 12:39:09 PM PDT 24
Finished May 21 12:39:36 PM PDT 24
Peak memory 196388 kb
Host smart-351f3480-dd2c-4c13-a5a4-c2c2c225b7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161572215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.4161572215
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.2385670055
Short name T831
Test name
Test status
Simulation time 714021915 ps
CPU time 2.69 seconds
Started May 21 12:38:59 PM PDT 24
Finished May 21 12:39:13 PM PDT 24
Peak memory 199304 kb
Host smart-c3b3828e-6547-4ec9-9187-cc4454ec0cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385670055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2385670055
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.240335779
Short name T693
Test name
Test status
Simulation time 234003714011 ps
CPU time 48.38 seconds
Started May 21 12:39:34 PM PDT 24
Finished May 21 12:40:31 PM PDT 24
Peak memory 200416 kb
Host smart-2b137812-e475-4d39-ab8a-461327462b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240335779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.240335779
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1960838307
Short name T859
Test name
Test status
Simulation time 128995136331 ps
CPU time 585.82 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:49:08 PM PDT 24
Peak memory 225300 kb
Host smart-812b0705-9dd3-44bd-ae2f-ace00a2df241
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960838307 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1960838307
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.4080915188
Short name T1009
Test name
Test status
Simulation time 8107828476 ps
CPU time 9.64 seconds
Started May 21 12:39:05 PM PDT 24
Finished May 21 12:39:24 PM PDT 24
Peak memory 200144 kb
Host smart-820f5474-ca54-4219-9e3c-15e0a74b4b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080915188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.4080915188
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.860527504
Short name T521
Test name
Test status
Simulation time 66020242487 ps
CPU time 146.04 seconds
Started May 21 12:39:17 PM PDT 24
Finished May 21 12:41:54 PM PDT 24
Peak memory 200428 kb
Host smart-e195e309-b112-40a9-90f2-287feccbb9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860527504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.860527504
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3025559997
Short name T707
Test name
Test status
Simulation time 143206794 ps
CPU time 0.55 seconds
Started May 21 12:39:14 PM PDT 24
Finished May 21 12:39:25 PM PDT 24
Peak memory 195848 kb
Host smart-68c9c96e-6904-4088-ab99-6f75dbd02c02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025559997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3025559997
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3301257831
Short name T850
Test name
Test status
Simulation time 67297448980 ps
CPU time 39.94 seconds
Started May 21 12:39:21 PM PDT 24
Finished May 21 12:40:12 PM PDT 24
Peak memory 200512 kb
Host smart-6a3adf18-6b1d-40ac-af5f-350d1fadf0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301257831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3301257831
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2114330715
Short name T992
Test name
Test status
Simulation time 71282848916 ps
CPU time 47.74 seconds
Started May 21 12:39:11 PM PDT 24
Finished May 21 12:40:10 PM PDT 24
Peak memory 200504 kb
Host smart-9ed3d281-fc39-42e0-a487-5ad125b95735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114330715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2114330715
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1329548653
Short name T623
Test name
Test status
Simulation time 156391406283 ps
CPU time 72.79 seconds
Started May 21 12:39:26 PM PDT 24
Finished May 21 12:40:48 PM PDT 24
Peak memory 200444 kb
Host smart-6137f4d6-480e-4fa0-985e-0340a23c9596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329548653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1329548653
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.2729652725
Short name T997
Test name
Test status
Simulation time 7093886753 ps
CPU time 3.84 seconds
Started May 21 12:39:02 PM PDT 24
Finished May 21 12:39:15 PM PDT 24
Peak memory 197336 kb
Host smart-6f21f96e-d2d7-4468-b02b-7ae59132d247
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729652725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2729652725
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2263401564
Short name T934
Test name
Test status
Simulation time 64031359604 ps
CPU time 205.06 seconds
Started May 21 12:39:13 PM PDT 24
Finished May 21 12:42:49 PM PDT 24
Peak memory 200424 kb
Host smart-9c75ceb6-3b8a-41bc-819e-23f5b12a66bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263401564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2263401564
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.860069509
Short name T564
Test name
Test status
Simulation time 5840352699 ps
CPU time 11.89 seconds
Started May 21 12:39:26 PM PDT 24
Finished May 21 12:39:47 PM PDT 24
Peak memory 199824 kb
Host smart-b757546a-b04e-4fde-8f3c-0aa65170ef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860069509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.860069509
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.464039146
Short name T1139
Test name
Test status
Simulation time 77936563058 ps
CPU time 62.53 seconds
Started May 21 12:39:07 PM PDT 24
Finished May 21 12:40:18 PM PDT 24
Peak memory 200700 kb
Host smart-6dc88a9a-7d83-4825-8789-258a9ed4fea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464039146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.464039146
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1493168815
Short name T259
Test name
Test status
Simulation time 11488065948 ps
CPU time 148.91 seconds
Started May 21 12:39:11 PM PDT 24
Finished May 21 12:41:49 PM PDT 24
Peak memory 200452 kb
Host smart-5b8ba1f7-1b8f-42b5-96e6-9619f829141f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1493168815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1493168815
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3279273253
Short name T950
Test name
Test status
Simulation time 5701175487 ps
CPU time 53.12 seconds
Started May 21 12:39:04 PM PDT 24
Finished May 21 12:40:06 PM PDT 24
Peak memory 199664 kb
Host smart-7afd835b-364f-4646-b33a-dc109ff90798
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3279273253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3279273253
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1967142823
Short name T880
Test name
Test status
Simulation time 224037253759 ps
CPU time 224.93 seconds
Started May 21 12:39:02 PM PDT 24
Finished May 21 12:42:57 PM PDT 24
Peak memory 200496 kb
Host smart-6d07b736-dd71-4f23-8a03-e4b7d0653f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967142823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1967142823
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3717639661
Short name T364
Test name
Test status
Simulation time 51093018839 ps
CPU time 6.59 seconds
Started May 21 12:39:03 PM PDT 24
Finished May 21 12:39:19 PM PDT 24
Peak memory 196516 kb
Host smart-b722c886-0a78-4a89-80d1-c66d2ac134a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717639661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3717639661
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.4067471884
Short name T30
Test name
Test status
Simulation time 251886808 ps
CPU time 0.76 seconds
Started May 21 12:39:22 PM PDT 24
Finished May 21 12:39:33 PM PDT 24
Peak memory 219008 kb
Host smart-b63ec68c-549c-40d5-9ba7-590c99d2295c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067471884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.4067471884
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.672754586
Short name T825
Test name
Test status
Simulation time 510630240 ps
CPU time 2.49 seconds
Started May 21 12:39:27 PM PDT 24
Finished May 21 12:39:38 PM PDT 24
Peak memory 199996 kb
Host smart-f45b821c-38d2-4cc2-bd3c-b37f2837dde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672754586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.672754586
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1174559471
Short name T493
Test name
Test status
Simulation time 7839049709 ps
CPU time 17.18 seconds
Started May 21 12:39:06 PM PDT 24
Finished May 21 12:39:33 PM PDT 24
Peak memory 200484 kb
Host smart-dfd7dc44-2462-4cfe-b5b4-322c1c859e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174559471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1174559471
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2845743251
Short name T469
Test name
Test status
Simulation time 81411441510 ps
CPU time 72.79 seconds
Started May 21 12:39:14 PM PDT 24
Finished May 21 12:40:38 PM PDT 24
Peak memory 200480 kb
Host smart-c10d7484-55d4-4ccb-9fc9-00fd7fb013bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845743251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2845743251
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.4255563215
Short name T1117
Test name
Test status
Simulation time 11422549 ps
CPU time 0.56 seconds
Started May 21 12:39:41 PM PDT 24
Finished May 21 12:39:51 PM PDT 24
Peak memory 195852 kb
Host smart-eb6eb89c-f820-4fba-8d75-2fb003d2f36d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255563215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.4255563215
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3726044940
Short name T479
Test name
Test status
Simulation time 91669587807 ps
CPU time 45.26 seconds
Started May 21 12:39:38 PM PDT 24
Finished May 21 12:40:33 PM PDT 24
Peak memory 200524 kb
Host smart-b369198a-b123-4df8-9ad5-df73dac40ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726044940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3726044940
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1365395989
Short name T770
Test name
Test status
Simulation time 93649909064 ps
CPU time 39.09 seconds
Started May 21 12:39:38 PM PDT 24
Finished May 21 12:40:26 PM PDT 24
Peak memory 200444 kb
Host smart-d9c6f460-3cbf-43d9-bf73-d4400aae2125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365395989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1365395989
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2217857181
Short name T793
Test name
Test status
Simulation time 95616854567 ps
CPU time 84.47 seconds
Started May 21 12:39:44 PM PDT 24
Finished May 21 12:41:19 PM PDT 24
Peak memory 200352 kb
Host smart-faa65a71-5834-4983-82fd-e8a770a815be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217857181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2217857181
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1121634429
Short name T680
Test name
Test status
Simulation time 34314768298 ps
CPU time 48.32 seconds
Started May 21 12:39:43 PM PDT 24
Finished May 21 12:40:41 PM PDT 24
Peak memory 200480 kb
Host smart-ee02d2ff-e6c5-4462-ae3c-e1fe1751896c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121634429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1121634429
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_loopback.1119535379
Short name T355
Test name
Test status
Simulation time 6190187851 ps
CPU time 3.63 seconds
Started May 21 12:39:27 PM PDT 24
Finished May 21 12:39:39 PM PDT 24
Peak memory 199016 kb
Host smart-3c874bf1-4fab-4a01-9101-586ac5d0f2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119535379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1119535379
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2056629022
Short name T788
Test name
Test status
Simulation time 195386957669 ps
CPU time 101.79 seconds
Started May 21 12:39:34 PM PDT 24
Finished May 21 12:41:24 PM PDT 24
Peak memory 216176 kb
Host smart-974fd531-51e4-46ff-967a-384d013475e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056629022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2056629022
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2975788694
Short name T1123
Test name
Test status
Simulation time 16703406693 ps
CPU time 853.05 seconds
Started May 21 12:39:42 PM PDT 24
Finished May 21 12:54:05 PM PDT 24
Peak memory 200500 kb
Host smart-d6eef033-242b-4104-98bd-138a528c8f34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975788694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2975788694
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2312878257
Short name T672
Test name
Test status
Simulation time 6572991013 ps
CPU time 8.76 seconds
Started May 21 12:39:41 PM PDT 24
Finished May 21 12:40:00 PM PDT 24
Peak memory 199204 kb
Host smart-53da21e7-3fef-4741-85d6-f6032e850061
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2312878257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2312878257
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2004041945
Short name T785
Test name
Test status
Simulation time 116177819092 ps
CPU time 205.8 seconds
Started May 21 12:39:44 PM PDT 24
Finished May 21 12:43:20 PM PDT 24
Peak memory 200404 kb
Host smart-8b86d186-b05d-463d-a35c-89e2534e9a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004041945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2004041945
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1231511190
Short name T470
Test name
Test status
Simulation time 46144156665 ps
CPU time 83.46 seconds
Started May 21 12:39:28 PM PDT 24
Finished May 21 12:41:00 PM PDT 24
Peak memory 196380 kb
Host smart-dd096e92-9db3-4580-9df1-b6280fe0edf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231511190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1231511190
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3033602488
Short name T744
Test name
Test status
Simulation time 5649677121 ps
CPU time 3.11 seconds
Started May 21 12:39:43 PM PDT 24
Finished May 21 12:39:56 PM PDT 24
Peak memory 200148 kb
Host smart-7eafe842-40b8-43a3-aa63-1cba9195f455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033602488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3033602488
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.4127885165
Short name T114
Test name
Test status
Simulation time 54731376025 ps
CPU time 283.57 seconds
Started May 21 12:39:43 PM PDT 24
Finished May 21 12:44:37 PM PDT 24
Peak memory 200432 kb
Host smart-6b7d8b31-0c8d-4355-b9e2-8b3917df4bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127885165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.4127885165
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.402390897
Short name T276
Test name
Test status
Simulation time 11635263698 ps
CPU time 148.28 seconds
Started May 21 12:39:51 PM PDT 24
Finished May 21 12:42:30 PM PDT 24
Peak memory 216960 kb
Host smart-0cfa3e87-c90d-410a-8425-ea97c22743e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402390897 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.402390897
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3948217776
Short name T270
Test name
Test status
Simulation time 882224277 ps
CPU time 1.62 seconds
Started May 21 12:39:28 PM PDT 24
Finished May 21 12:39:39 PM PDT 24
Peak memory 200288 kb
Host smart-0c62ae2f-fc29-4fae-9dcd-a2d503f2c73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948217776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3948217776
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2542898747
Short name T1039
Test name
Test status
Simulation time 6861132246 ps
CPU time 13.97 seconds
Started May 21 12:39:19 PM PDT 24
Finished May 21 12:39:44 PM PDT 24
Peak memory 200404 kb
Host smart-ed82bbb6-5e7b-45f0-ad7c-2ae32e3d3369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542898747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2542898747
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3680064929
Short name T615
Test name
Test status
Simulation time 24490640075 ps
CPU time 51.1 seconds
Started May 21 12:42:12 PM PDT 24
Finished May 21 12:43:08 PM PDT 24
Peak memory 200468 kb
Host smart-091df1c7-08d0-4626-ae9d-b76d8272a1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680064929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3680064929
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.750539416
Short name T835
Test name
Test status
Simulation time 14000716693 ps
CPU time 13.28 seconds
Started May 21 12:42:09 PM PDT 24
Finished May 21 12:42:26 PM PDT 24
Peak memory 200500 kb
Host smart-7a41deac-51e5-46f6-85d6-2dde84eb615b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750539416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.750539416
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2843553106
Short name T45
Test name
Test status
Simulation time 24251441897 ps
CPU time 29.91 seconds
Started May 21 12:42:12 PM PDT 24
Finished May 21 12:42:47 PM PDT 24
Peak memory 200496 kb
Host smart-b9b3232c-8bdd-47f2-b958-f7302713cc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843553106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2843553106
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3870498742
Short name T368
Test name
Test status
Simulation time 48636895451 ps
CPU time 27.69 seconds
Started May 21 12:42:10 PM PDT 24
Finished May 21 12:42:43 PM PDT 24
Peak memory 200456 kb
Host smart-6d1c4e78-1fce-4f93-9294-9e30735d3fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870498742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3870498742
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1389941397
Short name T197
Test name
Test status
Simulation time 41559739002 ps
CPU time 35.13 seconds
Started May 21 12:42:12 PM PDT 24
Finished May 21 12:42:53 PM PDT 24
Peak memory 200512 kb
Host smart-35a0c7cc-72cf-4b52-9d7e-981113d573b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389941397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1389941397
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.349862500
Short name T977
Test name
Test status
Simulation time 35791537438 ps
CPU time 51.05 seconds
Started May 21 12:42:12 PM PDT 24
Finished May 21 12:43:09 PM PDT 24
Peak memory 200472 kb
Host smart-36de3a07-215b-42ea-a8b3-8596d2814d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349862500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.349862500
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1860837890
Short name T1108
Test name
Test status
Simulation time 41645317793 ps
CPU time 36.71 seconds
Started May 21 12:42:13 PM PDT 24
Finished May 21 12:42:55 PM PDT 24
Peak memory 200424 kb
Host smart-ef8becea-015e-46b0-8588-fc07070a9051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860837890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1860837890
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3839503516
Short name T647
Test name
Test status
Simulation time 50623641976 ps
CPU time 13.84 seconds
Started May 21 12:42:15 PM PDT 24
Finished May 21 12:42:33 PM PDT 24
Peak memory 200728 kb
Host smart-7c8b5b1b-6a60-4940-9112-42f48a04d285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839503516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3839503516
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2237925441
Short name T384
Test name
Test status
Simulation time 10894538 ps
CPU time 0.53 seconds
Started May 21 12:39:36 PM PDT 24
Finished May 21 12:39:47 PM PDT 24
Peak memory 194852 kb
Host smart-3f056ec8-2430-4c1c-a4e2-2da4b2f348c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237925441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2237925441
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1300059261
Short name T929
Test name
Test status
Simulation time 45503532055 ps
CPU time 65.02 seconds
Started May 21 12:39:38 PM PDT 24
Finished May 21 12:40:53 PM PDT 24
Peak memory 200672 kb
Host smart-990ffbb4-1de8-4fd1-8085-2ada0ed15ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300059261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1300059261
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.4221619424
Short name T153
Test name
Test status
Simulation time 117868096859 ps
CPU time 50.76 seconds
Started May 21 12:39:47 PM PDT 24
Finished May 21 12:40:48 PM PDT 24
Peak memory 200448 kb
Host smart-07ad9f03-f31d-4a7d-895b-1c851947b4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221619424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.4221619424
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.4179391102
Short name T1083
Test name
Test status
Simulation time 84598928502 ps
CPU time 33.97 seconds
Started May 21 12:39:47 PM PDT 24
Finished May 21 12:40:31 PM PDT 24
Peak memory 200300 kb
Host smart-2a804e96-c980-4b4e-9472-f9125e369d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179391102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.4179391102
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3446309057
Short name T374
Test name
Test status
Simulation time 5183957079 ps
CPU time 4.84 seconds
Started May 21 12:39:37 PM PDT 24
Finished May 21 12:39:52 PM PDT 24
Peak memory 200024 kb
Host smart-d02e6c0a-c1b6-4dcd-8a4d-1c7a624ebe1f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446309057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3446309057
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2676508157
Short name T682
Test name
Test status
Simulation time 218242508945 ps
CPU time 197.15 seconds
Started May 21 12:39:42 PM PDT 24
Finished May 21 12:43:09 PM PDT 24
Peak memory 200432 kb
Host smart-c6ecf3b9-4c70-4a84-8a82-1eadd100b7ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676508157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2676508157
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1576005602
Short name T3
Test name
Test status
Simulation time 3484755401 ps
CPU time 2.78 seconds
Started May 21 12:39:40 PM PDT 24
Finished May 21 12:39:52 PM PDT 24
Peak memory 200396 kb
Host smart-c226cb01-646f-41e8-be87-ddc68b88b96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576005602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1576005602
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.456819456
Short name T982
Test name
Test status
Simulation time 108132411997 ps
CPU time 187.66 seconds
Started May 21 12:39:44 PM PDT 24
Finished May 21 12:43:02 PM PDT 24
Peak memory 200544 kb
Host smart-159235c6-254d-4c14-adfe-0055b8f1afda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456819456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.456819456
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3606836041
Short name T471
Test name
Test status
Simulation time 14543886807 ps
CPU time 420.21 seconds
Started May 21 12:39:40 PM PDT 24
Finished May 21 12:46:50 PM PDT 24
Peak memory 200360 kb
Host smart-c76a17d7-c394-4bd8-b845-bd00200c7e65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3606836041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3606836041
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2994540078
Short name T674
Test name
Test status
Simulation time 7735232489 ps
CPU time 67.21 seconds
Started May 21 12:39:32 PM PDT 24
Finished May 21 12:40:48 PM PDT 24
Peak memory 200516 kb
Host smart-12c3779d-3b5d-4411-b1e8-b97283dcf9dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994540078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2994540078
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1252909801
Short name T583
Test name
Test status
Simulation time 39535623720 ps
CPU time 14.2 seconds
Started May 21 12:39:37 PM PDT 24
Finished May 21 12:40:01 PM PDT 24
Peak memory 200028 kb
Host smart-33b22f4c-1d80-47ca-ab7f-9d244f3b33d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252909801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1252909801
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1135881228
Short name T455
Test name
Test status
Simulation time 36837664454 ps
CPU time 14.75 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:39:59 PM PDT 24
Peak memory 196260 kb
Host smart-642f2d8c-7735-4dda-a411-00ff1a403fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135881228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1135881228
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3021960516
Short name T628
Test name
Test status
Simulation time 780724575 ps
CPU time 1.11 seconds
Started May 21 12:39:45 PM PDT 24
Finished May 21 12:39:56 PM PDT 24
Peak memory 198948 kb
Host smart-b2817662-af3b-488f-ab0d-cd6301b7ce00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021960516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3021960516
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.867099676
Short name T620
Test name
Test status
Simulation time 162078839732 ps
CPU time 542.92 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:48:48 PM PDT 24
Peak memory 209024 kb
Host smart-d2cfc252-806b-4135-ac5b-b31e564e5c5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867099676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.867099676
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3058894675
Short name T494
Test name
Test status
Simulation time 5676094948 ps
CPU time 68.62 seconds
Started May 21 12:39:37 PM PDT 24
Finished May 21 12:40:55 PM PDT 24
Peak memory 216808 kb
Host smart-e6cf49c4-ab6e-4cfa-97db-b02420d425ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058894675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3058894675
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2898578855
Short name T412
Test name
Test status
Simulation time 6521918179 ps
CPU time 25.91 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:40:10 PM PDT 24
Peak memory 199892 kb
Host smart-9e27e2a4-e966-453e-96d7-366ae740f90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898578855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2898578855
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2150709452
Short name T691
Test name
Test status
Simulation time 35328710104 ps
CPU time 26.12 seconds
Started May 21 12:39:28 PM PDT 24
Finished May 21 12:40:04 PM PDT 24
Peak memory 200420 kb
Host smart-75d22fc9-a2cc-4743-adf5-7c355aaf7da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150709452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2150709452
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1982606771
Short name T386
Test name
Test status
Simulation time 160749015833 ps
CPU time 272.26 seconds
Started May 21 12:42:25 PM PDT 24
Finished May 21 12:47:00 PM PDT 24
Peak memory 200400 kb
Host smart-58d447da-101b-448c-acea-f1d75155bfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982606771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1982606771
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1481729652
Short name T630
Test name
Test status
Simulation time 95735664418 ps
CPU time 37.08 seconds
Started May 21 12:42:14 PM PDT 24
Finished May 21 12:42:55 PM PDT 24
Peak memory 200392 kb
Host smart-03f689f4-b46b-41fd-8537-3779921f8c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481729652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1481729652
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.4059140295
Short name T1148
Test name
Test status
Simulation time 46741955406 ps
CPU time 61.9 seconds
Started May 21 12:42:25 PM PDT 24
Finished May 21 12:43:30 PM PDT 24
Peak memory 200400 kb
Host smart-cb72e2c7-aa22-4a9b-914d-ced7ccefc3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059140295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.4059140295
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2772271672
Short name T1015
Test name
Test status
Simulation time 147561294132 ps
CPU time 119.97 seconds
Started May 21 12:42:15 PM PDT 24
Finished May 21 12:44:20 PM PDT 24
Peak memory 200192 kb
Host smart-ef6ad023-53d1-4c58-85b6-648d3ff3f7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772271672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2772271672
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2749745762
Short name T652
Test name
Test status
Simulation time 96399965750 ps
CPU time 163.4 seconds
Started May 21 12:42:17 PM PDT 24
Finished May 21 12:45:04 PM PDT 24
Peak memory 200460 kb
Host smart-bcbb11e3-cafa-46a4-ad44-26c016828ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749745762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2749745762
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.4247354556
Short name T591
Test name
Test status
Simulation time 94648992874 ps
CPU time 112.38 seconds
Started May 21 12:42:15 PM PDT 24
Finished May 21 12:44:12 PM PDT 24
Peak memory 200604 kb
Host smart-1f78f1de-6f3b-42bb-b64d-e41db4b73ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247354556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.4247354556
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.628005060
Short name T1165
Test name
Test status
Simulation time 145318776142 ps
CPU time 35.5 seconds
Started May 21 12:42:25 PM PDT 24
Finished May 21 12:43:04 PM PDT 24
Peak memory 200432 kb
Host smart-56229b88-25af-48af-811a-29c918da56bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628005060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.628005060
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1184523036
Short name T464
Test name
Test status
Simulation time 68754773622 ps
CPU time 51.86 seconds
Started May 21 12:42:20 PM PDT 24
Finished May 21 12:43:15 PM PDT 24
Peak memory 200484 kb
Host smart-3fd62051-01b4-40c2-a0a0-1d810da12ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184523036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1184523036
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2044542652
Short name T538
Test name
Test status
Simulation time 41531278 ps
CPU time 0.56 seconds
Started May 21 12:39:44 PM PDT 24
Finished May 21 12:39:56 PM PDT 24
Peak memory 195876 kb
Host smart-a3b7f6f0-9f17-4163-81e3-9ee0e401423c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044542652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2044542652
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3310109377
Short name T136
Test name
Test status
Simulation time 352813993080 ps
CPU time 335.52 seconds
Started May 21 12:39:34 PM PDT 24
Finished May 21 12:45:20 PM PDT 24
Peak memory 200388 kb
Host smart-776287fc-56e5-44d7-ad4b-a98eab90108b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310109377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3310109377
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2357206636
Short name T852
Test name
Test status
Simulation time 81921441408 ps
CPU time 141.87 seconds
Started May 21 12:39:42 PM PDT 24
Finished May 21 12:42:14 PM PDT 24
Peak memory 200564 kb
Host smart-3ca5753e-0611-40c3-bdf1-2e86b3939663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357206636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2357206636
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1127403935
Short name T848
Test name
Test status
Simulation time 57626196832 ps
CPU time 84.46 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:41:09 PM PDT 24
Peak memory 200448 kb
Host smart-843ef42e-ba55-49d0-9874-33556b9efbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127403935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1127403935
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.922082736
Short name T1132
Test name
Test status
Simulation time 37282706801 ps
CPU time 72.48 seconds
Started May 21 12:39:44 PM PDT 24
Finished May 21 12:41:07 PM PDT 24
Peak memory 200508 kb
Host smart-c5d74681-3dd7-44eb-8e65-15229dcc89de
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922082736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.922082736
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.993576693
Short name T926
Test name
Test status
Simulation time 296785692613 ps
CPU time 176.85 seconds
Started May 21 12:39:42 PM PDT 24
Finished May 21 12:42:49 PM PDT 24
Peak memory 200520 kb
Host smart-f4e39200-32e6-4be2-aa44-f1c7ade31136
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=993576693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.993576693
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1813754861
Short name T352
Test name
Test status
Simulation time 7979863784 ps
CPU time 8.46 seconds
Started May 21 12:39:40 PM PDT 24
Finished May 21 12:39:58 PM PDT 24
Peak memory 199588 kb
Host smart-872aaeb2-c832-4fc3-98ff-66398ccd9c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813754861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1813754861
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3789214467
Short name T485
Test name
Test status
Simulation time 55872242528 ps
CPU time 100.65 seconds
Started May 21 12:39:41 PM PDT 24
Finished May 21 12:41:31 PM PDT 24
Peak memory 200824 kb
Host smart-33f550ea-5347-4bfd-a91f-24285cb3b063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789214467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3789214467
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2226775714
Short name T451
Test name
Test status
Simulation time 18113600988 ps
CPU time 107.9 seconds
Started May 21 12:39:44 PM PDT 24
Finished May 21 12:41:42 PM PDT 24
Peak memory 200400 kb
Host smart-51dc3f47-cccc-4a28-aa06-831901c7fd63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2226775714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2226775714
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3658689862
Short name T945
Test name
Test status
Simulation time 1904904821 ps
CPU time 4.93 seconds
Started May 21 12:39:40 PM PDT 24
Finished May 21 12:39:54 PM PDT 24
Peak memory 198784 kb
Host smart-ac625ef1-57f3-4c46-afd5-c853ece720a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3658689862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3658689862
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2176277715
Short name T243
Test name
Test status
Simulation time 142310507358 ps
CPU time 102.8 seconds
Started May 21 12:39:39 PM PDT 24
Finished May 21 12:41:32 PM PDT 24
Peak memory 200356 kb
Host smart-4f1163af-1556-4fe4-a2e9-5783902a3e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176277715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2176277715
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2041337304
Short name T474
Test name
Test status
Simulation time 4775141091 ps
CPU time 8.1 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:39:53 PM PDT 24
Peak memory 196376 kb
Host smart-fa5e4021-6388-4852-a2a0-1b4ce0c09496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041337304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2041337304
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1471006343
Short name T1173
Test name
Test status
Simulation time 101609109 ps
CPU time 0.89 seconds
Started May 21 12:39:44 PM PDT 24
Finished May 21 12:39:56 PM PDT 24
Peak memory 197584 kb
Host smart-c864c5b0-537d-4b09-818c-515151b1efc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471006343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1471006343
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.4243076981
Short name T1063
Test name
Test status
Simulation time 66728418380 ps
CPU time 122.71 seconds
Started May 21 12:39:47 PM PDT 24
Finished May 21 12:42:00 PM PDT 24
Peak memory 200540 kb
Host smart-535bc9f3-131f-4565-9bf8-635dc9ed7691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243076981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.4243076981
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1864563476
Short name T165
Test name
Test status
Simulation time 32059660926 ps
CPU time 297.94 seconds
Started May 21 12:39:42 PM PDT 24
Finished May 21 12:44:49 PM PDT 24
Peak memory 215396 kb
Host smart-2ae1624d-5c78-4a1c-8176-29996c366416
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864563476 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1864563476
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2603413156
Short name T1121
Test name
Test status
Simulation time 9701607385 ps
CPU time 8.7 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:39:53 PM PDT 24
Peak memory 199852 kb
Host smart-50a0e6aa-a35d-4582-b1c2-765b4694a683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603413156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2603413156
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1197764796
Short name T863
Test name
Test status
Simulation time 64468804500 ps
CPU time 36.47 seconds
Started May 21 12:39:40 PM PDT 24
Finished May 21 12:40:26 PM PDT 24
Peak memory 200372 kb
Host smart-1416674a-ebc7-4bed-b6a0-d967f62b77cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197764796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1197764796
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3970812533
Short name T892
Test name
Test status
Simulation time 277063638100 ps
CPU time 26.21 seconds
Started May 21 12:42:20 PM PDT 24
Finished May 21 12:42:49 PM PDT 24
Peak memory 200520 kb
Host smart-d4434cc6-6933-4942-bd80-9e87903e3187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970812533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3970812533
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2314062939
Short name T380
Test name
Test status
Simulation time 370273440516 ps
CPU time 68.17 seconds
Started May 21 12:42:16 PM PDT 24
Finished May 21 12:43:28 PM PDT 24
Peak memory 200452 kb
Host smart-ac097ac4-8c89-4ca4-909b-7b60f86a2595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314062939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2314062939
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3141299439
Short name T429
Test name
Test status
Simulation time 11023265293 ps
CPU time 10.03 seconds
Started May 21 12:42:18 PM PDT 24
Finished May 21 12:42:31 PM PDT 24
Peak memory 200320 kb
Host smart-62bd59e0-f2e2-471f-9ef4-12a0736b902c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141299439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3141299439
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.44847487
Short name T611
Test name
Test status
Simulation time 35612371394 ps
CPU time 58.37 seconds
Started May 21 12:42:17 PM PDT 24
Finished May 21 12:43:19 PM PDT 24
Peak memory 200500 kb
Host smart-052727e5-a957-46b1-a228-d01743ff5942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44847487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.44847487
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.591578812
Short name T537
Test name
Test status
Simulation time 45256232247 ps
CPU time 150.11 seconds
Started May 21 12:42:25 PM PDT 24
Finished May 21 12:44:58 PM PDT 24
Peak memory 200432 kb
Host smart-f9ccfebb-bb41-4efc-a3b1-256293c70497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591578812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.591578812
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1932147846
Short name T594
Test name
Test status
Simulation time 97721399782 ps
CPU time 58.9 seconds
Started May 21 12:42:16 PM PDT 24
Finished May 21 12:43:19 PM PDT 24
Peak memory 200428 kb
Host smart-39acda21-29b9-4474-a303-dde158b1b0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932147846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1932147846
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3811218015
Short name T1172
Test name
Test status
Simulation time 116799112956 ps
CPU time 133.78 seconds
Started May 21 12:42:20 PM PDT 24
Finished May 21 12:44:37 PM PDT 24
Peak memory 200520 kb
Host smart-5245562f-9c72-499c-9c7e-be7a64d6afba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811218015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3811218015
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3896191373
Short name T988
Test name
Test status
Simulation time 71917697916 ps
CPU time 30.41 seconds
Started May 21 12:42:20 PM PDT 24
Finished May 21 12:42:53 PM PDT 24
Peak memory 200356 kb
Host smart-ba929ce4-411d-446a-8cc5-235786b78a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896191373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3896191373
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.722912619
Short name T569
Test name
Test status
Simulation time 33021536082 ps
CPU time 63.58 seconds
Started May 21 12:42:25 PM PDT 24
Finished May 21 12:43:32 PM PDT 24
Peak memory 200436 kb
Host smart-453796d3-1d9d-492e-a716-66e9dd501945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722912619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.722912619
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2304269214
Short name T972
Test name
Test status
Simulation time 13290751 ps
CPU time 0.58 seconds
Started May 21 12:39:51 PM PDT 24
Finished May 21 12:40:02 PM PDT 24
Peak memory 195884 kb
Host smart-628ec0e3-4bbd-4c3c-bc0a-8f1ca56701bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304269214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2304269214
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.4219092524
Short name T1119
Test name
Test status
Simulation time 70187537805 ps
CPU time 86.59 seconds
Started May 21 12:39:47 PM PDT 24
Finished May 21 12:41:24 PM PDT 24
Peak memory 200528 kb
Host smart-f1630d6b-e2dc-4d7a-b7f5-84773666ef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219092524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.4219092524
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3052715917
Short name T300
Test name
Test status
Simulation time 132868048312 ps
CPU time 52.37 seconds
Started May 21 12:39:46 PM PDT 24
Finished May 21 12:40:49 PM PDT 24
Peak memory 200392 kb
Host smart-a7b7f3dd-85e8-402b-9a41-430481185c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052715917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3052715917
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3818837489
Short name T811
Test name
Test status
Simulation time 112250171400 ps
CPU time 47.54 seconds
Started May 21 12:39:45 PM PDT 24
Finished May 21 12:40:42 PM PDT 24
Peak memory 200416 kb
Host smart-8e392e7c-2cb7-44e1-bdc2-cf2d30e50003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818837489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3818837489
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2779724625
Short name T322
Test name
Test status
Simulation time 51952492760 ps
CPU time 21.04 seconds
Started May 21 12:39:49 PM PDT 24
Finished May 21 12:40:21 PM PDT 24
Peak memory 200392 kb
Host smart-7094c2f9-189a-4ff4-9d31-f72bb5b4ce57
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779724625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2779724625
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.231387459
Short name T299
Test name
Test status
Simulation time 157936417624 ps
CPU time 403.33 seconds
Started May 21 12:39:50 PM PDT 24
Finished May 21 12:46:45 PM PDT 24
Peak memory 200520 kb
Host smart-fbd2a8d7-4675-4c41-a09f-2db7cd13045a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231387459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.231387459
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1321693452
Short name T11
Test name
Test status
Simulation time 4577054811 ps
CPU time 9.21 seconds
Started May 21 12:39:53 PM PDT 24
Finished May 21 12:40:12 PM PDT 24
Peak memory 199260 kb
Host smart-da6af2ac-edbd-45cc-ab1c-6beca793f234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321693452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1321693452
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.339696586
Short name T621
Test name
Test status
Simulation time 203514909104 ps
CPU time 96.18 seconds
Started May 21 12:39:41 PM PDT 24
Finished May 21 12:41:26 PM PDT 24
Peak memory 208600 kb
Host smart-84fef545-c516-488b-b816-2ad504ea0e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339696586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.339696586
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2393491672
Short name T509
Test name
Test status
Simulation time 21386750558 ps
CPU time 313.47 seconds
Started May 21 12:39:48 PM PDT 24
Finished May 21 12:45:13 PM PDT 24
Peak memory 200424 kb
Host smart-be60be3a-be45-4fb0-a364-b19b5e9b0945
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2393491672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2393491672
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2188676625
Short name T105
Test name
Test status
Simulation time 7189797094 ps
CPU time 8.24 seconds
Started May 21 12:39:50 PM PDT 24
Finished May 21 12:40:09 PM PDT 24
Peak memory 199224 kb
Host smart-f940a13a-41f2-4932-9f61-d609bb223446
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2188676625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2188676625
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3656345602
Short name T143
Test name
Test status
Simulation time 78053422970 ps
CPU time 30.56 seconds
Started May 21 12:39:43 PM PDT 24
Finished May 21 12:40:24 PM PDT 24
Peak memory 200364 kb
Host smart-cf564b4c-ca39-4f91-a89c-07c14aa764c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656345602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3656345602
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.407958330
Short name T808
Test name
Test status
Simulation time 40401241181 ps
CPU time 72.13 seconds
Started May 21 12:39:41 PM PDT 24
Finished May 21 12:41:03 PM PDT 24
Peak memory 196496 kb
Host smart-76081209-bac4-4b42-bce7-e674e16d3abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407958330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.407958330
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3484536804
Short name T366
Test name
Test status
Simulation time 531336298 ps
CPU time 1.4 seconds
Started May 21 12:39:46 PM PDT 24
Finished May 21 12:39:58 PM PDT 24
Peak memory 198760 kb
Host smart-f256eaaf-208f-43cd-a62f-8c91ebb46ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484536804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3484536804
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2676360037
Short name T822
Test name
Test status
Simulation time 536399500344 ps
CPU time 174.59 seconds
Started May 21 12:39:50 PM PDT 24
Finished May 21 12:42:55 PM PDT 24
Peak memory 208852 kb
Host smart-0685cc76-1075-4f00-9764-7fe24ec13d16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676360037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2676360037
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.4261440491
Short name T819
Test name
Test status
Simulation time 84363374723 ps
CPU time 1457.73 seconds
Started May 21 12:39:48 PM PDT 24
Finished May 21 01:04:16 PM PDT 24
Peak memory 216936 kb
Host smart-2ab8c8e8-cf37-4694-9ed6-6b2b74898eca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261440491 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.4261440491
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2356908869
Short name T579
Test name
Test status
Simulation time 7610851904 ps
CPU time 9.12 seconds
Started May 21 12:39:50 PM PDT 24
Finished May 21 12:40:10 PM PDT 24
Peak memory 199804 kb
Host smart-d49193f0-e73b-4dd2-860f-db09ef84bfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356908869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2356908869
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.4123742164
Short name T789
Test name
Test status
Simulation time 89273714231 ps
CPU time 35.09 seconds
Started May 21 12:39:42 PM PDT 24
Finished May 21 12:40:28 PM PDT 24
Peak memory 200684 kb
Host smart-959a5d12-eba1-49d0-bdf3-94efbcb69c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123742164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.4123742164
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3402277314
Short name T1176
Test name
Test status
Simulation time 11465942294 ps
CPU time 23.79 seconds
Started May 21 12:42:17 PM PDT 24
Finished May 21 12:42:45 PM PDT 24
Peak memory 200480 kb
Host smart-3f36be84-2d33-4f73-a009-b563ce2bf24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402277314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3402277314
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.14854620
Short name T991
Test name
Test status
Simulation time 98008107841 ps
CPU time 84.85 seconds
Started May 21 12:42:18 PM PDT 24
Finished May 21 12:43:47 PM PDT 24
Peak memory 200484 kb
Host smart-6ba27585-dcb8-401a-9b0e-c879e9511c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14854620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.14854620
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.114833188
Short name T183
Test name
Test status
Simulation time 44729962120 ps
CPU time 38.25 seconds
Started May 21 12:42:19 PM PDT 24
Finished May 21 12:43:00 PM PDT 24
Peak memory 200332 kb
Host smart-e4b9fdb6-0d9a-46df-a730-b52327aee0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114833188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.114833188
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3096725548
Short name T1033
Test name
Test status
Simulation time 176290834700 ps
CPU time 67.88 seconds
Started May 21 12:42:22 PM PDT 24
Finished May 21 12:43:33 PM PDT 24
Peak memory 200460 kb
Host smart-c109f352-68c5-4886-83e7-534bfda03a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096725548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3096725548
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2740579635
Short name T1004
Test name
Test status
Simulation time 116539803483 ps
CPU time 208.51 seconds
Started May 21 12:42:24 PM PDT 24
Finished May 21 12:45:55 PM PDT 24
Peak memory 200336 kb
Host smart-ba16cf1e-a2ea-4581-8e17-0728f5740915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740579635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2740579635
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1561464549
Short name T1169
Test name
Test status
Simulation time 25469384337 ps
CPU time 12.25 seconds
Started May 21 12:42:26 PM PDT 24
Finished May 21 12:42:41 PM PDT 24
Peak memory 200488 kb
Host smart-1251dd02-6597-4ebb-9b86-da9f08d3c3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561464549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1561464549
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3747175968
Short name T104
Test name
Test status
Simulation time 35753700945 ps
CPU time 19.9 seconds
Started May 21 12:42:23 PM PDT 24
Finished May 21 12:42:46 PM PDT 24
Peak memory 200424 kb
Host smart-3bf9c4b8-4634-412c-b547-d678ab8ddc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747175968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3747175968
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2794100684
Short name T782
Test name
Test status
Simulation time 54177728420 ps
CPU time 29.46 seconds
Started May 21 12:42:23 PM PDT 24
Finished May 21 12:42:55 PM PDT 24
Peak memory 200492 kb
Host smart-09728787-0d18-418b-bd4f-faba28775e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794100684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2794100684
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.306553089
Short name T575
Test name
Test status
Simulation time 27271573 ps
CPU time 0.57 seconds
Started May 21 12:39:57 PM PDT 24
Finished May 21 12:40:06 PM PDT 24
Peak memory 195864 kb
Host smart-7aecd414-2421-4d74-8206-92f928da1cba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306553089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.306553089
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2272544581
Short name T1024
Test name
Test status
Simulation time 121717793475 ps
CPU time 176.63 seconds
Started May 21 12:39:51 PM PDT 24
Finished May 21 12:42:58 PM PDT 24
Peak memory 200380 kb
Host smart-e3778518-6a58-44b8-9a40-ba693068bad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272544581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2272544581
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.4238300141
Short name T585
Test name
Test status
Simulation time 120752571048 ps
CPU time 51.89 seconds
Started May 21 12:39:48 PM PDT 24
Finished May 21 12:40:51 PM PDT 24
Peak memory 200488 kb
Host smart-4dc8ca2f-bb71-457e-8a35-9a43f9ac667c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238300141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.4238300141
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.285997412
Short name T171
Test name
Test status
Simulation time 28354976468 ps
CPU time 28.91 seconds
Started May 21 12:39:48 PM PDT 24
Finished May 21 12:40:28 PM PDT 24
Peak memory 200428 kb
Host smart-89c24505-703e-4287-9afc-22f96519d744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285997412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.285997412
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2332132730
Short name T844
Test name
Test status
Simulation time 22279101835 ps
CPU time 12.48 seconds
Started May 21 12:39:48 PM PDT 24
Finished May 21 12:40:12 PM PDT 24
Peak memory 200444 kb
Host smart-06a3f6da-53ba-424b-b236-28745fca182c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332132730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2332132730
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2810279475
Short name T747
Test name
Test status
Simulation time 196893391901 ps
CPU time 373.58 seconds
Started May 21 12:39:53 PM PDT 24
Finished May 21 12:46:16 PM PDT 24
Peak memory 200460 kb
Host smart-def259f8-6617-49a7-916a-a0bb4fbf2b31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2810279475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2810279475
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2633854832
Short name T641
Test name
Test status
Simulation time 7487748647 ps
CPU time 13.03 seconds
Started May 21 12:39:49 PM PDT 24
Finished May 21 12:40:13 PM PDT 24
Peak memory 198476 kb
Host smart-5c6ebdbc-99f8-46b0-bfee-3f37dd83d88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633854832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2633854832
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.4148361242
Short name T514
Test name
Test status
Simulation time 17803950149 ps
CPU time 26.02 seconds
Started May 21 12:39:48 PM PDT 24
Finished May 21 12:40:24 PM PDT 24
Peak memory 200640 kb
Host smart-2b30f1b2-c56b-4a44-8ee5-4b1b6baaee75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148361242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.4148361242
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.960748184
Short name T247
Test name
Test status
Simulation time 10729959178 ps
CPU time 603.59 seconds
Started May 21 12:39:48 PM PDT 24
Finished May 21 12:50:02 PM PDT 24
Peak memory 200364 kb
Host smart-a522f561-bcfc-437e-bd48-e4aa72acd78b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960748184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.960748184
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1091904832
Short name T812
Test name
Test status
Simulation time 2781969034 ps
CPU time 4.94 seconds
Started May 21 12:39:48 PM PDT 24
Finished May 21 12:40:04 PM PDT 24
Peak memory 198980 kb
Host smart-64125a15-ddd3-41c2-a0fe-db1bf6375556
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091904832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1091904832
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1536040537
Short name T739
Test name
Test status
Simulation time 139889760045 ps
CPU time 93.46 seconds
Started May 21 12:39:49 PM PDT 24
Finished May 21 12:41:33 PM PDT 24
Peak memory 200456 kb
Host smart-c5224e69-7ee1-4f34-89a6-b897a9e272a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536040537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1536040537
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1980216890
Short name T529
Test name
Test status
Simulation time 32472151466 ps
CPU time 23.21 seconds
Started May 21 12:39:49 PM PDT 24
Finished May 21 12:40:23 PM PDT 24
Peak memory 196476 kb
Host smart-b64993b7-5c09-4114-a647-603097724085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980216890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1980216890
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3418984176
Short name T503
Test name
Test status
Simulation time 491817680 ps
CPU time 1.19 seconds
Started May 21 12:39:48 PM PDT 24
Finished May 21 12:40:00 PM PDT 24
Peak memory 200436 kb
Host smart-1bcb6120-629b-4d58-b99b-458b91ffd3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418984176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3418984176
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.689687929
Short name T893
Test name
Test status
Simulation time 260508721843 ps
CPU time 328.38 seconds
Started May 21 12:39:53 PM PDT 24
Finished May 21 12:45:31 PM PDT 24
Peak memory 200448 kb
Host smart-6d012994-12eb-4aa6-be9f-784c8a276dc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689687929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.689687929
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2904503409
Short name T645
Test name
Test status
Simulation time 221646756087 ps
CPU time 437.5 seconds
Started May 21 12:39:50 PM PDT 24
Finished May 21 12:47:18 PM PDT 24
Peak memory 225468 kb
Host smart-e0cc8e03-bb53-4856-9f57-0e22fa6b2f62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904503409 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2904503409
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1200886778
Short name T980
Test name
Test status
Simulation time 783610928 ps
CPU time 1.08 seconds
Started May 21 12:39:47 PM PDT 24
Finished May 21 12:39:59 PM PDT 24
Peak memory 197352 kb
Host smart-caa65801-50ef-4893-ad00-b5e27bd356c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200886778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1200886778
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2018091900
Short name T640
Test name
Test status
Simulation time 79973233215 ps
CPU time 83.16 seconds
Started May 21 12:39:56 PM PDT 24
Finished May 21 12:41:28 PM PDT 24
Peak memory 200440 kb
Host smart-8f89ec73-a0d9-4d87-8a19-f2c2d9a6e7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018091900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2018091900
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1961933488
Short name T595
Test name
Test status
Simulation time 44600656341 ps
CPU time 24.61 seconds
Started May 21 12:42:22 PM PDT 24
Finished May 21 12:42:50 PM PDT 24
Peak memory 200512 kb
Host smart-dbe1aada-ada8-4cc3-b8b0-03b6b00e8244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961933488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1961933488
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1212017924
Short name T170
Test name
Test status
Simulation time 12038301295 ps
CPU time 24.03 seconds
Started May 21 12:42:24 PM PDT 24
Finished May 21 12:42:51 PM PDT 24
Peak memory 200480 kb
Host smart-a2939f69-e525-4212-aa1d-9af4077206c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212017924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1212017924
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1336455338
Short name T517
Test name
Test status
Simulation time 108760022496 ps
CPU time 153.79 seconds
Started May 21 12:42:25 PM PDT 24
Finished May 21 12:45:02 PM PDT 24
Peak memory 200444 kb
Host smart-95387d01-0d68-42f7-8c3a-aa3117d77b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336455338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1336455338
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1114635136
Short name T663
Test name
Test status
Simulation time 155880209427 ps
CPU time 333.71 seconds
Started May 21 12:42:23 PM PDT 24
Finished May 21 12:48:01 PM PDT 24
Peak memory 200388 kb
Host smart-a7a024c6-8397-4c8b-af94-a4c1d428be76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114635136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1114635136
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.4116708280
Short name T607
Test name
Test status
Simulation time 33687729933 ps
CPU time 32.54 seconds
Started May 21 12:42:21 PM PDT 24
Finished May 21 12:42:57 PM PDT 24
Peak memory 200520 kb
Host smart-8628e195-b211-40ee-84fd-db118d3c5434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116708280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.4116708280
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1087793189
Short name T624
Test name
Test status
Simulation time 21408669036 ps
CPU time 37.97 seconds
Started May 21 12:42:22 PM PDT 24
Finished May 21 12:43:03 PM PDT 24
Peak memory 200448 kb
Host smart-2d4318d2-7b7f-4cb4-9169-066970634359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087793189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1087793189
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2065226553
Short name T810
Test name
Test status
Simulation time 130924131290 ps
CPU time 74.66 seconds
Started May 21 12:42:22 PM PDT 24
Finished May 21 12:43:40 PM PDT 24
Peak memory 200432 kb
Host smart-a0e22735-6e8a-4167-b79c-f2f685f573c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065226553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2065226553
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3059069409
Short name T1096
Test name
Test status
Simulation time 82210950094 ps
CPU time 77.28 seconds
Started May 21 12:42:22 PM PDT 24
Finished May 21 12:43:43 PM PDT 24
Peak memory 200504 kb
Host smart-2f431f06-ebe0-41fd-8aac-7b8d7e491b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059069409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3059069409
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.771955986
Short name T1071
Test name
Test status
Simulation time 411881610960 ps
CPU time 40.48 seconds
Started May 21 12:42:23 PM PDT 24
Finished May 21 12:43:07 PM PDT 24
Peak memory 200472 kb
Host smart-308f8fde-2a34-41c6-b271-7d8c1ddc00a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771955986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.771955986
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3230573220
Short name T313
Test name
Test status
Simulation time 79303986134 ps
CPU time 146.99 seconds
Started May 21 12:42:21 PM PDT 24
Finished May 21 12:44:51 PM PDT 24
Peak memory 200536 kb
Host smart-bf7f7ef8-899a-4065-886d-d4cfa579c75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230573220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3230573220
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.4126069994
Short name T392
Test name
Test status
Simulation time 156900302013 ps
CPU time 271.67 seconds
Started May 21 12:40:00 PM PDT 24
Finished May 21 12:44:38 PM PDT 24
Peak memory 200376 kb
Host smart-3efbc52c-666c-4e2e-b535-d8134dddfc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126069994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.4126069994
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.711587506
Short name T391
Test name
Test status
Simulation time 101990003639 ps
CPU time 160.47 seconds
Started May 21 12:39:55 PM PDT 24
Finished May 21 12:42:44 PM PDT 24
Peak memory 200408 kb
Host smart-43834086-7ea5-4d19-9894-a1725aa87d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711587506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.711587506
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1708001568
Short name T1181
Test name
Test status
Simulation time 77892551168 ps
CPU time 121.27 seconds
Started May 21 12:39:57 PM PDT 24
Finished May 21 12:42:06 PM PDT 24
Peak memory 200416 kb
Host smart-db0fbf27-cbf1-4ee7-b9c3-4a3aed54b544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708001568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1708001568
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.548544337
Short name T875
Test name
Test status
Simulation time 19575936908 ps
CPU time 23.64 seconds
Started May 21 12:39:54 PM PDT 24
Finished May 21 12:40:27 PM PDT 24
Peak memory 200484 kb
Host smart-2e499568-94fd-488a-a472-cc76a31fc46b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548544337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.548544337
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2062598690
Short name T570
Test name
Test status
Simulation time 86497297414 ps
CPU time 261.31 seconds
Started May 21 12:39:59 PM PDT 24
Finished May 21 12:44:28 PM PDT 24
Peak memory 200528 kb
Host smart-ad75b631-669f-4c01-9198-5ead3cef97dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2062598690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2062598690
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1034236903
Short name T1149
Test name
Test status
Simulation time 1559131301 ps
CPU time 0.85 seconds
Started May 21 12:39:56 PM PDT 24
Finished May 21 12:40:05 PM PDT 24
Peak memory 196628 kb
Host smart-94594988-fd77-450d-b813-686b945d2cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034236903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1034236903
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.4029013802
Short name T312
Test name
Test status
Simulation time 244157998161 ps
CPU time 107.47 seconds
Started May 21 12:39:56 PM PDT 24
Finished May 21 12:41:52 PM PDT 24
Peak memory 200672 kb
Host smart-ca9f4d7d-c0e0-4254-a99f-c5ac95215089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029013802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.4029013802
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3663436003
Short name T296
Test name
Test status
Simulation time 17044796059 ps
CPU time 973.1 seconds
Started May 21 12:39:53 PM PDT 24
Finished May 21 12:56:16 PM PDT 24
Peak memory 200424 kb
Host smart-0281a98a-74c2-461e-8748-810f193077a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663436003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3663436003
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1782084344
Short name T855
Test name
Test status
Simulation time 1529468582 ps
CPU time 1.25 seconds
Started May 21 12:39:57 PM PDT 24
Finished May 21 12:40:06 PM PDT 24
Peak memory 198264 kb
Host smart-71fade32-e6e6-4e42-b957-30e269989ac3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1782084344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1782084344
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.688251685
Short name T745
Test name
Test status
Simulation time 259030368613 ps
CPU time 142.92 seconds
Started May 21 12:39:55 PM PDT 24
Finished May 21 12:42:27 PM PDT 24
Peak memory 200392 kb
Host smart-dad8563b-5b95-4391-90c4-388c304ee2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688251685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.688251685
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1831409435
Short name T385
Test name
Test status
Simulation time 4794431167 ps
CPU time 1.51 seconds
Started May 21 12:39:59 PM PDT 24
Finished May 21 12:40:08 PM PDT 24
Peak memory 196816 kb
Host smart-e5ef818c-9783-4798-b919-fda7f164af15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831409435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1831409435
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1137950526
Short name T685
Test name
Test status
Simulation time 6215781877 ps
CPU time 25.98 seconds
Started May 21 12:39:56 PM PDT 24
Finished May 21 12:40:30 PM PDT 24
Peak memory 200324 kb
Host smart-2aa7a6ff-0afd-4c66-87b4-ac1dc94d08a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137950526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1137950526
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2161536153
Short name T902
Test name
Test status
Simulation time 6303808868 ps
CPU time 16.97 seconds
Started May 21 12:39:55 PM PDT 24
Finished May 21 12:40:21 PM PDT 24
Peak memory 200016 kb
Host smart-7556536a-f2e4-42d9-8ea5-0a91960253b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161536153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2161536153
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.243240168
Short name T244
Test name
Test status
Simulation time 60519995317 ps
CPU time 61.23 seconds
Started May 21 12:39:54 PM PDT 24
Finished May 21 12:41:05 PM PDT 24
Peak memory 200444 kb
Host smart-5f426dc5-296e-43ed-b98e-bf54f34dcf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243240168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.243240168
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.955712421
Short name T179
Test name
Test status
Simulation time 263230943087 ps
CPU time 78.72 seconds
Started May 21 12:42:24 PM PDT 24
Finished May 21 12:43:46 PM PDT 24
Peak memory 200440 kb
Host smart-59e74eb3-7c24-4a46-817e-a33eb039f67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955712421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.955712421
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3055449990
Short name T325
Test name
Test status
Simulation time 16596009616 ps
CPU time 19.12 seconds
Started May 21 12:42:26 PM PDT 24
Finished May 21 12:42:47 PM PDT 24
Peak memory 200448 kb
Host smart-cc23dc0d-6372-47f7-aa72-748ae1643bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055449990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3055449990
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1689243946
Short name T191
Test name
Test status
Simulation time 20622250781 ps
CPU time 35.43 seconds
Started May 21 12:42:24 PM PDT 24
Finished May 21 12:43:03 PM PDT 24
Peak memory 200412 kb
Host smart-d3a5a5c3-8fd5-4088-be0f-91e22fef6d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689243946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1689243946
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3358358466
Short name T697
Test name
Test status
Simulation time 231611026797 ps
CPU time 19.54 seconds
Started May 21 12:42:25 PM PDT 24
Finished May 21 12:42:47 PM PDT 24
Peak memory 200492 kb
Host smart-d50d86fb-8b38-46b2-ab72-0877a653ae99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358358466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3358358466
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.4199073957
Short name T536
Test name
Test status
Simulation time 72794240582 ps
CPU time 62.38 seconds
Started May 21 12:42:22 PM PDT 24
Finished May 21 12:43:27 PM PDT 24
Peak memory 200472 kb
Host smart-de20cd23-ad05-49c8-90ae-0e9d9ffd55f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199073957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.4199073957
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3315618739
Short name T1045
Test name
Test status
Simulation time 16198291957 ps
CPU time 36.02 seconds
Started May 21 12:42:23 PM PDT 24
Finished May 21 12:43:03 PM PDT 24
Peak memory 200436 kb
Host smart-365195c8-f8d1-4812-b919-2b9a96ef462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315618739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3315618739
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3966731923
Short name T436
Test name
Test status
Simulation time 132046623570 ps
CPU time 68.4 seconds
Started May 21 12:42:23 PM PDT 24
Finished May 21 12:43:35 PM PDT 24
Peak memory 200496 kb
Host smart-53b510b9-ad2c-4db4-a41e-3dc61859b2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966731923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3966731923
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2941844316
Short name T605
Test name
Test status
Simulation time 94375976792 ps
CPU time 243.22 seconds
Started May 21 12:42:23 PM PDT 24
Finished May 21 12:46:30 PM PDT 24
Peak memory 200476 kb
Host smart-9f1963ab-0e17-4355-bdf3-e079493c86cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941844316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2941844316
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1784876829
Short name T923
Test name
Test status
Simulation time 180582653749 ps
CPU time 78.84 seconds
Started May 21 12:42:22 PM PDT 24
Finished May 21 12:43:44 PM PDT 24
Peak memory 200732 kb
Host smart-7bfbb859-8aa4-4876-a5c4-c262394688f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784876829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1784876829
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.4177277820
Short name T353
Test name
Test status
Simulation time 33653165 ps
CPU time 0.53 seconds
Started May 21 12:40:05 PM PDT 24
Finished May 21 12:40:09 PM PDT 24
Peak memory 194860 kb
Host smart-5ea7307b-1298-4d98-ab44-d26029d18eef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177277820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.4177277820
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1230091009
Short name T864
Test name
Test status
Simulation time 155413953997 ps
CPU time 29.37 seconds
Started May 21 12:39:59 PM PDT 24
Finished May 21 12:40:35 PM PDT 24
Peak memory 200464 kb
Host smart-f94ecfcc-706b-4077-b733-198ca796721b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230091009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1230091009
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3297244340
Short name T7
Test name
Test status
Simulation time 24066089096 ps
CPU time 36.44 seconds
Started May 21 12:39:57 PM PDT 24
Finished May 21 12:40:41 PM PDT 24
Peak memory 200312 kb
Host smart-7fc359ed-d828-4f25-884a-ee06c3823bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297244340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3297244340
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.4255126370
Short name T173
Test name
Test status
Simulation time 24821002306 ps
CPU time 42.34 seconds
Started May 21 12:39:54 PM PDT 24
Finished May 21 12:40:45 PM PDT 24
Peak memory 200392 kb
Host smart-3fba4949-e887-4b8f-b60d-9e2ea3fc0ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255126370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.4255126370
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3253439202
Short name T912
Test name
Test status
Simulation time 11409538220 ps
CPU time 21.69 seconds
Started May 21 12:39:58 PM PDT 24
Finished May 21 12:40:27 PM PDT 24
Peak memory 200412 kb
Host smart-8a6e1dbb-05f3-41b0-ae4c-2a7b83cdd445
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253439202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3253439202
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1013448481
Short name T705
Test name
Test status
Simulation time 157443750534 ps
CPU time 934.36 seconds
Started May 21 12:40:02 PM PDT 24
Finished May 21 12:55:42 PM PDT 24
Peak memory 200504 kb
Host smart-7e97459e-bac0-4c65-8f63-2d0e3b1baa4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1013448481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1013448481
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.4250706984
Short name T1115
Test name
Test status
Simulation time 2703209698 ps
CPU time 2.21 seconds
Started May 21 12:40:12 PM PDT 24
Finished May 21 12:40:18 PM PDT 24
Peak memory 199116 kb
Host smart-1a6d6e09-b568-4f53-9f7b-1f1032743c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250706984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.4250706984
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1318189408
Short name T638
Test name
Test status
Simulation time 28258833202 ps
CPU time 25.21 seconds
Started May 21 12:39:59 PM PDT 24
Finished May 21 12:40:31 PM PDT 24
Peak memory 200724 kb
Host smart-b5747228-7d8d-42b0-b7e2-1a2e814254e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318189408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1318189408
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2819192570
Short name T1138
Test name
Test status
Simulation time 3788023332 ps
CPU time 57.71 seconds
Started May 21 12:40:03 PM PDT 24
Finished May 21 12:41:06 PM PDT 24
Peak memory 200508 kb
Host smart-a863d5b7-717d-4ead-a3e4-216b5f064574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2819192570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2819192570
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3112397035
Short name T402
Test name
Test status
Simulation time 5034969221 ps
CPU time 10.99 seconds
Started May 21 12:39:55 PM PDT 24
Finished May 21 12:40:15 PM PDT 24
Peak memory 199612 kb
Host smart-71703957-9ba1-467f-beed-d08811b23086
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3112397035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3112397035
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3914847348
Short name T434
Test name
Test status
Simulation time 85138299081 ps
CPU time 33.18 seconds
Started May 21 12:39:57 PM PDT 24
Finished May 21 12:40:38 PM PDT 24
Peak memory 200452 kb
Host smart-d23b8d85-4cc8-4c04-a224-dfacfb676493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914847348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3914847348
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2814349237
Short name T373
Test name
Test status
Simulation time 3270261198 ps
CPU time 6.24 seconds
Started May 21 12:39:56 PM PDT 24
Finished May 21 12:40:10 PM PDT 24
Peak memory 196448 kb
Host smart-3125d6a3-af70-4b3c-b96e-f8933896266d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814349237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2814349237
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2062233920
Short name T978
Test name
Test status
Simulation time 276127033 ps
CPU time 1.15 seconds
Started May 21 12:39:58 PM PDT 24
Finished May 21 12:40:07 PM PDT 24
Peak memory 200376 kb
Host smart-f2b00216-d8b7-4528-81ff-b8d4cbb7e53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062233920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2062233920
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.957316823
Short name T834
Test name
Test status
Simulation time 35730832411 ps
CPU time 757.75 seconds
Started May 21 12:40:06 PM PDT 24
Finished May 21 12:52:47 PM PDT 24
Peak memory 215856 kb
Host smart-760a158e-bff0-4046-9f45-e4c33595339f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957316823 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.957316823
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3490629462
Short name T18
Test name
Test status
Simulation time 3574147420 ps
CPU time 1.56 seconds
Started May 21 12:39:57 PM PDT 24
Finished May 21 12:40:07 PM PDT 24
Peak memory 198916 kb
Host smart-69f4ffe2-2b25-4532-8c5a-8d911f65cd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490629462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3490629462
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1368437649
Short name T754
Test name
Test status
Simulation time 18750708883 ps
CPU time 17.16 seconds
Started May 21 12:40:06 PM PDT 24
Finished May 21 12:40:26 PM PDT 24
Peak memory 198140 kb
Host smart-12863cee-df2d-48c3-a62f-aa4b76063ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368437649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1368437649
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3947336655
Short name T644
Test name
Test status
Simulation time 23576589163 ps
CPU time 36.45 seconds
Started May 21 12:42:25 PM PDT 24
Finished May 21 12:43:04 PM PDT 24
Peak memory 200444 kb
Host smart-95387d24-ee34-4370-9224-f24a4011a6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947336655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3947336655
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2996483103
Short name T13
Test name
Test status
Simulation time 149548373140 ps
CPU time 22.99 seconds
Started May 21 12:42:28 PM PDT 24
Finished May 21 12:42:52 PM PDT 24
Peak memory 200312 kb
Host smart-db9cbd6e-4522-4062-b7e1-d87d3f96b068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996483103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2996483103
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2327519784
Short name T1177
Test name
Test status
Simulation time 20828044982 ps
CPU time 20.36 seconds
Started May 21 12:42:31 PM PDT 24
Finished May 21 12:42:53 PM PDT 24
Peak memory 200488 kb
Host smart-0fb5c7d8-24eb-4170-b802-6296818e3237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327519784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2327519784
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3675223302
Short name T219
Test name
Test status
Simulation time 157352917789 ps
CPU time 84.96 seconds
Started May 21 12:42:28 PM PDT 24
Finished May 21 12:43:54 PM PDT 24
Peak memory 200488 kb
Host smart-b459b36f-95d4-4237-a7df-77e490c8b68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675223302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3675223302
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3344477975
Short name T181
Test name
Test status
Simulation time 38122349683 ps
CPU time 38.01 seconds
Started May 21 12:42:30 PM PDT 24
Finished May 21 12:43:09 PM PDT 24
Peak memory 200440 kb
Host smart-fe0f07d0-75b9-48ec-8a26-2e6a649ed4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344477975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3344477975
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3599994981
Short name T1084
Test name
Test status
Simulation time 10261805210 ps
CPU time 18.16 seconds
Started May 21 12:42:29 PM PDT 24
Finished May 21 12:42:48 PM PDT 24
Peak memory 200344 kb
Host smart-948ef65f-9431-4098-bfc0-bb750d12c361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599994981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3599994981
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1084818321
Short name T180
Test name
Test status
Simulation time 22000842796 ps
CPU time 40.02 seconds
Started May 21 12:42:29 PM PDT 24
Finished May 21 12:43:11 PM PDT 24
Peak memory 200460 kb
Host smart-f3aea233-48b4-4d37-8cb3-25e85841d73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084818321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1084818321
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.874973649
Short name T613
Test name
Test status
Simulation time 47847271 ps
CPU time 0.56 seconds
Started May 21 12:40:03 PM PDT 24
Finished May 21 12:40:09 PM PDT 24
Peak memory 195848 kb
Host smart-7515c606-6817-42c8-86a0-c0b359cfbcdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874973649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.874973649
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2116765967
Short name T511
Test name
Test status
Simulation time 273385460041 ps
CPU time 148.51 seconds
Started May 21 12:40:11 PM PDT 24
Finished May 21 12:42:43 PM PDT 24
Peak memory 200528 kb
Host smart-e50314e7-f8e4-4bb5-9e2b-0e07150449c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116765967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2116765967
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2840905854
Short name T973
Test name
Test status
Simulation time 47651123651 ps
CPU time 21.21 seconds
Started May 21 12:40:06 PM PDT 24
Finished May 21 12:40:31 PM PDT 24
Peak memory 200224 kb
Host smart-5abe2e71-a0bf-48e2-a692-8888d6065ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840905854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2840905854
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.660800112
Short name T723
Test name
Test status
Simulation time 83864721388 ps
CPU time 140.89 seconds
Started May 21 12:40:02 PM PDT 24
Finished May 21 12:42:28 PM PDT 24
Peak memory 200504 kb
Host smart-bc0b7b6b-c766-4c61-8d5b-15a6580f377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660800112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.660800112
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2823481057
Short name T1116
Test name
Test status
Simulation time 62314364999 ps
CPU time 104.02 seconds
Started May 21 12:40:01 PM PDT 24
Finished May 21 12:41:51 PM PDT 24
Peak memory 200532 kb
Host smart-899e63aa-c187-4efc-b8b2-3b27e730a0ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823481057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2823481057
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.657174357
Short name T468
Test name
Test status
Simulation time 153784107171 ps
CPU time 335.19 seconds
Started May 21 12:40:02 PM PDT 24
Finished May 21 12:45:43 PM PDT 24
Peak memory 200500 kb
Host smart-725bd595-45d6-4605-a7a2-b31c754839c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=657174357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.657174357
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.518110282
Short name T963
Test name
Test status
Simulation time 206617794 ps
CPU time 0.78 seconds
Started May 21 12:40:07 PM PDT 24
Finished May 21 12:40:11 PM PDT 24
Peak memory 196288 kb
Host smart-b8ee1dc5-76fa-461a-b13f-2ae09c628b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518110282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.518110282
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.4071489524
Short name T642
Test name
Test status
Simulation time 66974294224 ps
CPU time 32.87 seconds
Started May 21 12:40:09 PM PDT 24
Finished May 21 12:40:45 PM PDT 24
Peak memory 200512 kb
Host smart-54fbb72d-3040-4129-bb16-f6f628100491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071489524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.4071489524
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.581326700
Short name T255
Test name
Test status
Simulation time 33231890255 ps
CPU time 1717.14 seconds
Started May 21 12:40:07 PM PDT 24
Finished May 21 01:08:48 PM PDT 24
Peak memory 200380 kb
Host smart-86201d34-25b3-4b18-8e9f-f7193c0307c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=581326700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.581326700
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3248423515
Short name T1160
Test name
Test status
Simulation time 5400487496 ps
CPU time 45.65 seconds
Started May 21 12:40:04 PM PDT 24
Finished May 21 12:40:54 PM PDT 24
Peak memory 199924 kb
Host smart-8367adf8-1051-44f6-899a-a50eb94fdde3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3248423515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3248423515
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1010469837
Short name T162
Test name
Test status
Simulation time 94387678657 ps
CPU time 92.97 seconds
Started May 21 12:40:05 PM PDT 24
Finished May 21 12:41:42 PM PDT 24
Peak memory 200436 kb
Host smart-4b84c921-6e0f-40d0-b929-50c53b6d5909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010469837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1010469837
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.469689284
Short name T734
Test name
Test status
Simulation time 3406847247 ps
CPU time 1 seconds
Started May 21 12:40:02 PM PDT 24
Finished May 21 12:40:09 PM PDT 24
Peak memory 196532 kb
Host smart-7fad7727-cf2e-4f9a-90ff-0bdd5029b9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469689284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.469689284
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2036077323
Short name T99
Test name
Test status
Simulation time 536104342 ps
CPU time 2.28 seconds
Started May 21 12:40:03 PM PDT 24
Finished May 21 12:40:11 PM PDT 24
Peak memory 198660 kb
Host smart-47473da4-1c1d-40f3-9989-bd6ff99e3d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036077323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2036077323
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1586687182
Short name T522
Test name
Test status
Simulation time 412841969332 ps
CPU time 925.41 seconds
Started May 21 12:40:02 PM PDT 24
Finished May 21 12:55:33 PM PDT 24
Peak memory 217092 kb
Host smart-902d2da9-18ae-42d2-9e22-9c2aa67bdc70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586687182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1586687182
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1465261060
Short name T69
Test name
Test status
Simulation time 111767098862 ps
CPU time 1456.35 seconds
Started May 21 12:40:05 PM PDT 24
Finished May 21 01:04:26 PM PDT 24
Peak memory 218904 kb
Host smart-fc79a48a-6131-4b50-8f77-ebaf1298065b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465261060 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1465261060
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.4026457585
Short name T297
Test name
Test status
Simulation time 1342330693 ps
CPU time 1.98 seconds
Started May 21 12:40:11 PM PDT 24
Finished May 21 12:40:17 PM PDT 24
Peak memory 200088 kb
Host smart-7df6d602-b05a-4875-a6d8-b6ede67a7c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026457585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.4026457585
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1826459898
Short name T726
Test name
Test status
Simulation time 54275970384 ps
CPU time 43.79 seconds
Started May 21 12:40:01 PM PDT 24
Finished May 21 12:40:51 PM PDT 24
Peak memory 200440 kb
Host smart-9eabc7f7-e6e5-4871-8105-7858d6aff820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826459898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1826459898
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2480912504
Short name T234
Test name
Test status
Simulation time 21384572611 ps
CPU time 43.31 seconds
Started May 21 12:42:30 PM PDT 24
Finished May 21 12:43:15 PM PDT 24
Peak memory 200516 kb
Host smart-f64f4ea4-e01c-43c1-a6ab-e65d8140c401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480912504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2480912504
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.625875578
Short name T727
Test name
Test status
Simulation time 193339899881 ps
CPU time 27.1 seconds
Started May 21 12:42:27 PM PDT 24
Finished May 21 12:42:56 PM PDT 24
Peak memory 200476 kb
Host smart-dcdc2452-e4a0-4a01-a56d-eeb9469bf1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625875578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.625875578
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3933239730
Short name T370
Test name
Test status
Simulation time 82879461816 ps
CPU time 22.61 seconds
Started May 21 12:42:29 PM PDT 24
Finished May 21 12:42:53 PM PDT 24
Peak memory 200736 kb
Host smart-e945419d-a28f-4e16-abfa-14f824624d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933239730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3933239730
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2514640711
Short name T332
Test name
Test status
Simulation time 78563589816 ps
CPU time 43.62 seconds
Started May 21 12:42:29 PM PDT 24
Finished May 21 12:43:14 PM PDT 24
Peak memory 200508 kb
Host smart-949668b3-5846-4c5e-9862-32974e71306a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514640711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2514640711
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2665315074
Short name T1027
Test name
Test status
Simulation time 79825880910 ps
CPU time 69.15 seconds
Started May 21 12:42:31 PM PDT 24
Finished May 21 12:43:42 PM PDT 24
Peak memory 200480 kb
Host smart-4b339c6d-1d0b-4921-843c-579a8fcb4dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665315074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2665315074
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.2840294782
Short name T818
Test name
Test status
Simulation time 59065245651 ps
CPU time 93.02 seconds
Started May 21 12:42:33 PM PDT 24
Finished May 21 12:44:07 PM PDT 24
Peak memory 200484 kb
Host smart-0e70ff41-d0b8-44de-b711-943abe9dcef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840294782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2840294782
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2111348661
Short name T209
Test name
Test status
Simulation time 39167168411 ps
CPU time 35.89 seconds
Started May 21 12:42:33 PM PDT 24
Finished May 21 12:43:10 PM PDT 24
Peak memory 200492 kb
Host smart-296ff5e4-90db-4239-9d9a-208594ae5fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111348661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2111348661
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3879299204
Short name T971
Test name
Test status
Simulation time 118085545899 ps
CPU time 26.65 seconds
Started May 21 12:42:29 PM PDT 24
Finished May 21 12:42:58 PM PDT 24
Peak memory 200512 kb
Host smart-d764e0a6-5895-4030-82dd-395ec5f317b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879299204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3879299204
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3635416535
Short name T635
Test name
Test status
Simulation time 98504318842 ps
CPU time 17.69 seconds
Started May 21 12:42:31 PM PDT 24
Finished May 21 12:42:50 PM PDT 24
Peak memory 200516 kb
Host smart-dcb73940-2ba4-4aab-b08e-42505357e1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635416535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3635416535
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1694977043
Short name T1011
Test name
Test status
Simulation time 18846745 ps
CPU time 0.55 seconds
Started May 21 12:40:17 PM PDT 24
Finished May 21 12:40:22 PM PDT 24
Peak memory 195868 kb
Host smart-9217a302-86de-42e6-a269-b501ef67df72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694977043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1694977043
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2514623719
Short name T1153
Test name
Test status
Simulation time 190476316691 ps
CPU time 31.61 seconds
Started May 21 12:40:02 PM PDT 24
Finished May 21 12:40:39 PM PDT 24
Peak memory 200464 kb
Host smart-bde95770-4df0-4ae5-a7eb-2e7978a0714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514623719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2514623719
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1440120070
Short name T56
Test name
Test status
Simulation time 149221702317 ps
CPU time 66.05 seconds
Started May 21 12:40:03 PM PDT 24
Finished May 21 12:41:14 PM PDT 24
Peak memory 200448 kb
Host smart-dc2acd70-c341-4149-9b62-dfeec471ae3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440120070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1440120070
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1065224486
Short name T526
Test name
Test status
Simulation time 113310985061 ps
CPU time 226.7 seconds
Started May 21 12:40:01 PM PDT 24
Finished May 21 12:43:54 PM PDT 24
Peak memory 200432 kb
Host smart-870c1180-b695-4f98-b085-0202e1d4f3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065224486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1065224486
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.4018728827
Short name T265
Test name
Test status
Simulation time 28530735899 ps
CPU time 16.24 seconds
Started May 21 12:40:02 PM PDT 24
Finished May 21 12:40:24 PM PDT 24
Peak memory 200508 kb
Host smart-b1bffb4a-e787-4a21-9130-678d9824e766
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018728827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.4018728827
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1070165154
Short name T1044
Test name
Test status
Simulation time 33088955337 ps
CPU time 29.17 seconds
Started May 21 12:40:13 PM PDT 24
Finished May 21 12:40:47 PM PDT 24
Peak memory 200588 kb
Host smart-cd2a0c6b-a71d-48e4-9028-b13e19c43e8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1070165154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1070165154
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.415362943
Short name T1097
Test name
Test status
Simulation time 1539900966 ps
CPU time 3.1 seconds
Started May 21 12:40:08 PM PDT 24
Finished May 21 12:40:14 PM PDT 24
Peak memory 196596 kb
Host smart-689f94b5-e21f-47db-ba1a-2487f8e4a08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415362943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.415362943
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3592568568
Short name T551
Test name
Test status
Simulation time 140440710286 ps
CPU time 59.81 seconds
Started May 21 12:40:02 PM PDT 24
Finished May 21 12:41:07 PM PDT 24
Peak memory 208796 kb
Host smart-500fc5c6-7c8b-4656-8330-adfdf57e2baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592568568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3592568568
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2633637090
Short name T683
Test name
Test status
Simulation time 20644347185 ps
CPU time 1136.05 seconds
Started May 21 12:40:15 PM PDT 24
Finished May 21 12:59:15 PM PDT 24
Peak memory 199540 kb
Host smart-6262540d-878b-4f2e-bc82-f0f8287c5ccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633637090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2633637090
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.952358038
Short name T800
Test name
Test status
Simulation time 6226042162 ps
CPU time 54.64 seconds
Started May 21 12:40:01 PM PDT 24
Finished May 21 12:41:02 PM PDT 24
Peak memory 200452 kb
Host smart-60b91184-ab01-4546-bb15-7db78899d3ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=952358038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.952358038
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3985748951
Short name T587
Test name
Test status
Simulation time 77237997775 ps
CPU time 108.01 seconds
Started May 21 12:40:14 PM PDT 24
Finished May 21 12:42:06 PM PDT 24
Peak memory 200016 kb
Host smart-fcd5754f-d4c6-42c2-bf62-db8cfb98aba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985748951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3985748951
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.4053202594
Short name T740
Test name
Test status
Simulation time 67160919319 ps
CPU time 105.52 seconds
Started May 21 12:40:04 PM PDT 24
Finished May 21 12:41:54 PM PDT 24
Peak memory 196532 kb
Host smart-df699bad-c599-4e29-8db9-4c23d4cbc58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053202594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.4053202594
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.349563084
Short name T618
Test name
Test status
Simulation time 765597155 ps
CPU time 1.43 seconds
Started May 21 12:40:05 PM PDT 24
Finished May 21 12:40:10 PM PDT 24
Peak memory 199232 kb
Host smart-83fc8ac4-af31-4a7a-8d17-37cd3a0c68bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349563084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.349563084
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2007966895
Short name T1124
Test name
Test status
Simulation time 56996497961 ps
CPU time 508 seconds
Started May 21 12:40:14 PM PDT 24
Finished May 21 12:48:46 PM PDT 24
Peak memory 216948 kb
Host smart-ce7153a5-33d2-45a9-8e31-89e935f72832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007966895 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2007966895
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3120916225
Short name T660
Test name
Test status
Simulation time 6880799704 ps
CPU time 8.96 seconds
Started May 21 12:40:09 PM PDT 24
Finished May 21 12:40:21 PM PDT 24
Peak memory 200064 kb
Host smart-11f17ca4-fab8-4a70-bc9a-8b21e4532455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120916225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3120916225
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1170780157
Short name T706
Test name
Test status
Simulation time 85905373153 ps
CPU time 109.95 seconds
Started May 21 12:40:04 PM PDT 24
Finished May 21 12:41:58 PM PDT 24
Peak memory 200504 kb
Host smart-5835f3a2-4534-44f0-8081-ad9cc0e3425e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170780157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1170780157
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3348465223
Short name T1156
Test name
Test status
Simulation time 21274782145 ps
CPU time 14.33 seconds
Started May 21 12:42:30 PM PDT 24
Finished May 21 12:42:46 PM PDT 24
Peak memory 200524 kb
Host smart-99ed84e8-92de-4033-ac03-58219186fc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348465223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3348465223
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.670873895
Short name T709
Test name
Test status
Simulation time 62281992837 ps
CPU time 31.63 seconds
Started May 21 12:42:30 PM PDT 24
Finished May 21 12:43:03 PM PDT 24
Peak memory 200480 kb
Host smart-059974b9-5e78-4aa2-b90a-dddf8013e4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670873895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.670873895
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2849765309
Short name T1150
Test name
Test status
Simulation time 25675228497 ps
CPU time 43.1 seconds
Started May 21 12:42:30 PM PDT 24
Finished May 21 12:43:14 PM PDT 24
Peak memory 200460 kb
Host smart-12c85e9a-d769-458c-963f-3f8b6c09f984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849765309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2849765309
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.4166202664
Short name T438
Test name
Test status
Simulation time 225698402529 ps
CPU time 91.02 seconds
Started May 21 12:42:30 PM PDT 24
Finished May 21 12:44:03 PM PDT 24
Peak memory 200424 kb
Host smart-c28798b6-db12-414e-a044-ce750dc74746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166202664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.4166202664
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1643992979
Short name T1077
Test name
Test status
Simulation time 12526294432 ps
CPU time 9.89 seconds
Started May 21 12:42:31 PM PDT 24
Finished May 21 12:42:43 PM PDT 24
Peak memory 199132 kb
Host smart-4df25c3e-bdbd-457a-9c13-4c38c7e63700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643992979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1643992979
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3539345253
Short name T190
Test name
Test status
Simulation time 50727698957 ps
CPU time 83.98 seconds
Started May 21 12:42:29 PM PDT 24
Finished May 21 12:43:55 PM PDT 24
Peak memory 200532 kb
Host smart-236b9335-a73d-47cb-a672-0a6a29cff6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539345253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3539345253
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1248528841
Short name T103
Test name
Test status
Simulation time 59395922556 ps
CPU time 101.42 seconds
Started May 21 12:42:30 PM PDT 24
Finished May 21 12:44:13 PM PDT 24
Peak memory 200440 kb
Host smart-08ef26fa-2b99-422b-abdb-ee91ba18e7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248528841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1248528841
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.19930769
Short name T324
Test name
Test status
Simulation time 73307975236 ps
CPU time 159.32 seconds
Started May 21 12:42:31 PM PDT 24
Finished May 21 12:45:12 PM PDT 24
Peak memory 200444 kb
Host smart-bb4d7e93-6b85-464d-bd89-4e779429b3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19930769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.19930769
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3427652087
Short name T350
Test name
Test status
Simulation time 13032165 ps
CPU time 0.6 seconds
Started May 21 12:40:12 PM PDT 24
Finished May 21 12:40:16 PM PDT 24
Peak memory 195884 kb
Host smart-f7b19a2e-12e2-4086-a38c-f2d8040e630b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427652087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3427652087
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2917842186
Short name T976
Test name
Test status
Simulation time 161681328307 ps
CPU time 263.08 seconds
Started May 21 12:40:10 PM PDT 24
Finished May 21 12:44:37 PM PDT 24
Peak memory 200452 kb
Host smart-0ca1b96b-d491-4f2e-8842-a606051aad86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917842186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2917842186
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.374280059
Short name T1101
Test name
Test status
Simulation time 138867271418 ps
CPU time 84.45 seconds
Started May 21 12:40:14 PM PDT 24
Finished May 21 12:41:43 PM PDT 24
Peak memory 200760 kb
Host smart-93298e75-9820-4b6a-ac9c-1144da68731c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374280059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.374280059
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2984034482
Short name T675
Test name
Test status
Simulation time 69389265296 ps
CPU time 34.16 seconds
Started May 21 12:40:11 PM PDT 24
Finished May 21 12:40:48 PM PDT 24
Peak memory 200432 kb
Host smart-40fb237d-c370-42b0-89c2-bf71a2497d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984034482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2984034482
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.971579882
Short name T1029
Test name
Test status
Simulation time 12225865344 ps
CPU time 21.23 seconds
Started May 21 12:40:18 PM PDT 24
Finished May 21 12:40:44 PM PDT 24
Peak memory 198120 kb
Host smart-a069d457-8c1c-4e0a-8c76-5233dfbb1e8f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971579882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.971579882
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2266358146
Short name T986
Test name
Test status
Simulation time 56248609084 ps
CPU time 323.63 seconds
Started May 21 12:40:10 PM PDT 24
Finished May 21 12:45:37 PM PDT 24
Peak memory 200488 kb
Host smart-9c5d5e85-7daf-4351-856b-6d4620176655
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266358146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2266358146
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1886977192
Short name T759
Test name
Test status
Simulation time 1745114417 ps
CPU time 2.06 seconds
Started May 21 12:40:10 PM PDT 24
Finished May 21 12:40:16 PM PDT 24
Peak memory 196460 kb
Host smart-082d323b-67a3-42c2-af4d-319010e17cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886977192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1886977192
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.4179635517
Short name T760
Test name
Test status
Simulation time 503274114180 ps
CPU time 62.41 seconds
Started May 21 12:40:12 PM PDT 24
Finished May 21 12:41:18 PM PDT 24
Peak memory 200532 kb
Host smart-4316e06e-76d0-487e-a08c-7801a19e2c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179635517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.4179635517
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3856405418
Short name T278
Test name
Test status
Simulation time 8329266148 ps
CPU time 165.48 seconds
Started May 21 12:40:12 PM PDT 24
Finished May 21 12:43:01 PM PDT 24
Peak memory 200536 kb
Host smart-ae0b0633-5446-4745-a469-b27b5158d9d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856405418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3856405418
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3316445530
Short name T106
Test name
Test status
Simulation time 5989358845 ps
CPU time 13.66 seconds
Started May 21 12:40:10 PM PDT 24
Finished May 21 12:40:28 PM PDT 24
Peak memory 198448 kb
Host smart-c9cd91ed-5138-4fd7-be26-a39fd0279f2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316445530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3316445530
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.86987827
Short name T157
Test name
Test status
Simulation time 94398106087 ps
CPU time 217.7 seconds
Started May 21 12:40:13 PM PDT 24
Finished May 21 12:43:55 PM PDT 24
Peak memory 200436 kb
Host smart-342e5c36-146b-4094-b4a3-5236e1dac09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86987827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.86987827
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.4134805205
Short name T459
Test name
Test status
Simulation time 3078757994 ps
CPU time 2.02 seconds
Started May 21 12:40:16 PM PDT 24
Finished May 21 12:40:23 PM PDT 24
Peak memory 196508 kb
Host smart-9222632b-aaf4-4a90-8bc8-2cd216ac40e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134805205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.4134805205
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2282648806
Short name T1134
Test name
Test status
Simulation time 624035419 ps
CPU time 4.17 seconds
Started May 21 12:40:12 PM PDT 24
Finished May 21 12:40:20 PM PDT 24
Peak memory 198648 kb
Host smart-e1aa4d05-2320-4e0b-87db-2b579e193db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282648806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2282648806
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2493287322
Short name T377
Test name
Test status
Simulation time 156755175671 ps
CPU time 298.39 seconds
Started May 21 12:40:15 PM PDT 24
Finished May 21 12:45:17 PM PDT 24
Peak memory 208104 kb
Host smart-e7faa6c3-2aef-4ed2-bfb0-a016fef2114c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493287322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2493287322
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.658151653
Short name T938
Test name
Test status
Simulation time 40955605064 ps
CPU time 976.36 seconds
Started May 21 12:40:20 PM PDT 24
Finished May 21 12:56:43 PM PDT 24
Peak memory 217232 kb
Host smart-915df020-3fc3-47d0-9b4b-bf2bc2935ab0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658151653 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.658151653
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3519728936
Short name T425
Test name
Test status
Simulation time 6318316641 ps
CPU time 16.79 seconds
Started May 21 12:40:14 PM PDT 24
Finished May 21 12:40:35 PM PDT 24
Peak memory 200348 kb
Host smart-8a0df648-1175-4e9b-901d-0bc821d5fab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519728936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3519728936
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.227987610
Short name T281
Test name
Test status
Simulation time 143327958283 ps
CPU time 28.39 seconds
Started May 21 12:40:10 PM PDT 24
Finished May 21 12:40:42 PM PDT 24
Peak memory 200432 kb
Host smart-65e06671-6b69-4592-8b26-65134b9c613d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227987610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.227987610
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.4246897431
Short name T152
Test name
Test status
Simulation time 76499793500 ps
CPU time 111.38 seconds
Started May 21 12:42:31 PM PDT 24
Finished May 21 12:44:24 PM PDT 24
Peak memory 200416 kb
Host smart-fb9c51b7-a93a-428a-8f46-8487479bebd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246897431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.4246897431
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3792758282
Short name T1021
Test name
Test status
Simulation time 89523675366 ps
CPU time 35.3 seconds
Started May 21 12:42:31 PM PDT 24
Finished May 21 12:43:08 PM PDT 24
Peak memory 199928 kb
Host smart-ce57add5-7286-426b-bd21-6e9c26f41838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792758282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3792758282
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.4034090709
Short name T198
Test name
Test status
Simulation time 95293883840 ps
CPU time 162.12 seconds
Started May 21 12:42:30 PM PDT 24
Finished May 21 12:45:14 PM PDT 24
Peak memory 200428 kb
Host smart-d9e166f3-64d1-4d3c-86d9-46376b5d93ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034090709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.4034090709
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2827912333
Short name T1018
Test name
Test status
Simulation time 41811598167 ps
CPU time 128.7 seconds
Started May 21 12:42:34 PM PDT 24
Finished May 21 12:44:43 PM PDT 24
Peak memory 200392 kb
Host smart-9771db99-7a85-4790-b942-6dde9f3bf36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827912333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2827912333
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2949638011
Short name T881
Test name
Test status
Simulation time 28542832683 ps
CPU time 11.94 seconds
Started May 21 12:42:37 PM PDT 24
Finished May 21 12:42:50 PM PDT 24
Peak memory 200348 kb
Host smart-a1b51762-a3f7-44c5-8bb2-e2c0b8897313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949638011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2949638011
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1942359925
Short name T301
Test name
Test status
Simulation time 85444013829 ps
CPU time 25.5 seconds
Started May 21 12:42:37 PM PDT 24
Finished May 21 12:43:04 PM PDT 24
Peak memory 200304 kb
Host smart-41f7fb73-abc3-4783-927e-96b39d10e6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942359925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1942359925
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2214550259
Short name T207
Test name
Test status
Simulation time 122466411584 ps
CPU time 172.99 seconds
Started May 21 12:42:37 PM PDT 24
Finished May 21 12:45:31 PM PDT 24
Peak memory 200480 kb
Host smart-e5510825-5ca4-45b3-91b1-4e772a46664e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214550259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2214550259
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.4137433228
Short name T1026
Test name
Test status
Simulation time 65640118593 ps
CPU time 124.16 seconds
Started May 21 12:42:39 PM PDT 24
Finished May 21 12:44:44 PM PDT 24
Peak memory 200500 kb
Host smart-3d175478-bfd7-47ce-8466-954d72be77cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137433228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.4137433228
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3598364713
Short name T496
Test name
Test status
Simulation time 15013853 ps
CPU time 0.59 seconds
Started May 21 12:39:19 PM PDT 24
Finished May 21 12:39:30 PM PDT 24
Peak memory 195768 kb
Host smart-68e85d28-825f-4f52-bf08-d2aa188bd681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598364713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3598364713
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3274179108
Short name T1022
Test name
Test status
Simulation time 99400893483 ps
CPU time 116.95 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:41:20 PM PDT 24
Peak memory 200380 kb
Host smart-c35c8749-020d-4e6e-9100-97c5b5563dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274179108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3274179108
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2108647947
Short name T420
Test name
Test status
Simulation time 12963356891 ps
CPU time 17.27 seconds
Started May 21 12:39:23 PM PDT 24
Finished May 21 12:39:50 PM PDT 24
Peak memory 200472 kb
Host smart-4de1f32f-0f1d-4190-a8c3-72751b4e1df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108647947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2108647947
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.741779447
Short name T166
Test name
Test status
Simulation time 71560023454 ps
CPU time 34.79 seconds
Started May 21 12:39:24 PM PDT 24
Finished May 21 12:40:09 PM PDT 24
Peak memory 200436 kb
Host smart-10abdd77-88a4-481b-be26-7360a1395799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741779447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.741779447
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3232205290
Short name T1112
Test name
Test status
Simulation time 53757493152 ps
CPU time 87.5 seconds
Started May 21 12:39:18 PM PDT 24
Finished May 21 12:40:56 PM PDT 24
Peak memory 199900 kb
Host smart-aed2d154-079e-4c25-bfa0-a309835553f2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232205290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3232205290
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1283150951
Short name T1110
Test name
Test status
Simulation time 202826964110 ps
CPU time 95.65 seconds
Started May 21 12:39:29 PM PDT 24
Finished May 21 12:41:14 PM PDT 24
Peak memory 200540 kb
Host smart-afcbd412-5f49-4ce9-bc94-9656e846b9a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1283150951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1283150951
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2906289994
Short name T342
Test name
Test status
Simulation time 1641639353 ps
CPU time 4.33 seconds
Started May 21 12:39:31 PM PDT 24
Finished May 21 12:39:44 PM PDT 24
Peak memory 199404 kb
Host smart-29c0836a-6c8b-41c9-b5e3-f6e99027755e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906289994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2906289994
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2872188602
Short name T999
Test name
Test status
Simulation time 91161717305 ps
CPU time 145.45 seconds
Started May 21 12:39:11 PM PDT 24
Finished May 21 12:41:45 PM PDT 24
Peak memory 208932 kb
Host smart-528750d4-2c71-4ad6-804e-277fa578ae10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872188602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2872188602
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2301811806
Short name T845
Test name
Test status
Simulation time 8413507915 ps
CPU time 298.67 seconds
Started May 21 12:39:24 PM PDT 24
Finished May 21 12:44:33 PM PDT 24
Peak memory 200504 kb
Host smart-11c6ef99-0919-433b-ba5d-86b4ebc44e39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2301811806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2301811806
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.4047919083
Short name T316
Test name
Test status
Simulation time 3614873290 ps
CPU time 14.06 seconds
Started May 21 12:39:25 PM PDT 24
Finished May 21 12:39:48 PM PDT 24
Peak memory 198784 kb
Host smart-0ef80ee7-0a7c-45fb-b4d5-6e6033be62fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047919083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.4047919083
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3117690177
Short name T1070
Test name
Test status
Simulation time 87617314479 ps
CPU time 65.62 seconds
Started May 21 12:39:11 PM PDT 24
Finished May 21 12:40:27 PM PDT 24
Peak memory 200476 kb
Host smart-f8ea1aec-de4f-4b1b-91a1-a888e61aaf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117690177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3117690177
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1129978417
Short name T692
Test name
Test status
Simulation time 3829283975 ps
CPU time 6.19 seconds
Started May 21 12:39:20 PM PDT 24
Finished May 21 12:39:37 PM PDT 24
Peak memory 196496 kb
Host smart-633dc353-7748-47f3-9e84-ab22582ca578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129978417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1129978417
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.510666592
Short name T32
Test name
Test status
Simulation time 344361281 ps
CPU time 0.92 seconds
Started May 21 12:39:32 PM PDT 24
Finished May 21 12:39:42 PM PDT 24
Peak memory 219068 kb
Host smart-f3532a77-e226-4cf7-9050-8ae93c6f5777
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510666592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.510666592
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2948857754
Short name T772
Test name
Test status
Simulation time 908568291 ps
CPU time 1.7 seconds
Started May 21 12:39:19 PM PDT 24
Finished May 21 12:39:31 PM PDT 24
Peak memory 200344 kb
Host smart-f3f368fb-c0fa-40b3-8903-2c52d39b8785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948857754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2948857754
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3272447598
Short name T1107
Test name
Test status
Simulation time 231570227048 ps
CPU time 1070.02 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:57:35 PM PDT 24
Peak memory 209008 kb
Host smart-4d87de6a-38bc-4295-be35-0e1e655fa6a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272447598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3272447598
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1688022258
Short name T561
Test name
Test status
Simulation time 16753168407 ps
CPU time 224.94 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:43:07 PM PDT 24
Peak memory 210872 kb
Host smart-b5c1f28d-bf7e-428f-868a-816fc48afb72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688022258 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1688022258
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1782699508
Short name T649
Test name
Test status
Simulation time 7619497720 ps
CPU time 8.96 seconds
Started May 21 12:39:10 PM PDT 24
Finished May 21 12:39:28 PM PDT 24
Peak memory 200416 kb
Host smart-a69cbe44-1a82-4295-977b-58a4e468869f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782699508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1782699508
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3618726625
Short name T417
Test name
Test status
Simulation time 7153789054 ps
CPU time 10.42 seconds
Started May 21 12:39:14 PM PDT 24
Finished May 21 12:39:35 PM PDT 24
Peak memory 199972 kb
Host smart-36f07da2-ecfc-4236-bc8b-ca9d7008216e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618726625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3618726625
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1194535198
Short name T388
Test name
Test status
Simulation time 21733582 ps
CPU time 0.57 seconds
Started May 21 12:40:15 PM PDT 24
Finished May 21 12:40:20 PM PDT 24
Peak memory 195896 kb
Host smart-cb2f60f3-f511-4937-b3f8-4c28f4c27cba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194535198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1194535198
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.83211758
Short name T768
Test name
Test status
Simulation time 59112532410 ps
CPU time 86.38 seconds
Started May 21 12:40:13 PM PDT 24
Finished May 21 12:41:44 PM PDT 24
Peak memory 200488 kb
Host smart-653923a1-8b6f-435a-87d4-17190dc2123d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83211758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.83211758
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1796141482
Short name T266
Test name
Test status
Simulation time 169685875859 ps
CPU time 296.78 seconds
Started May 21 12:40:14 PM PDT 24
Finished May 21 12:45:16 PM PDT 24
Peak memory 200412 kb
Host smart-47d9dac3-a7e5-4e17-afcf-e2ffebb15f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796141482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1796141482
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3819794376
Short name T202
Test name
Test status
Simulation time 144373009916 ps
CPU time 218.24 seconds
Started May 21 12:40:18 PM PDT 24
Finished May 21 12:44:02 PM PDT 24
Peak memory 200376 kb
Host smart-e869245a-4961-46de-b001-a63880283c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819794376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3819794376
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1198782909
Short name T1054
Test name
Test status
Simulation time 372687018632 ps
CPU time 114.1 seconds
Started May 21 12:40:16 PM PDT 24
Finished May 21 12:42:15 PM PDT 24
Peak memory 199612 kb
Host smart-ead4b513-9b26-4b92-b3f3-29d64b784e15
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198782909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1198782909
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.48092276
Short name T584
Test name
Test status
Simulation time 70653935214 ps
CPU time 676.17 seconds
Started May 21 12:40:13 PM PDT 24
Finished May 21 12:51:33 PM PDT 24
Peak memory 200508 kb
Host smart-24f5973a-fc3b-4a6e-b5c9-7e67fd7b0291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48092276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.48092276
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1651982911
Short name T622
Test name
Test status
Simulation time 8705266657 ps
CPU time 8.79 seconds
Started May 21 12:40:18 PM PDT 24
Finished May 21 12:40:32 PM PDT 24
Peak memory 198300 kb
Host smart-0423d5a5-eb75-4fb9-b67f-5d7dca73c9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651982911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1651982911
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.4054646596
Short name T1079
Test name
Test status
Simulation time 42513626198 ps
CPU time 73.16 seconds
Started May 21 12:40:16 PM PDT 24
Finished May 21 12:41:34 PM PDT 24
Peak memory 208920 kb
Host smart-b5b63afe-31e1-491f-ad63-7ba78a867da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054646596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.4054646596
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.119329906
Short name T542
Test name
Test status
Simulation time 12401959075 ps
CPU time 206.87 seconds
Started May 21 12:40:13 PM PDT 24
Finished May 21 12:43:44 PM PDT 24
Peak memory 200404 kb
Host smart-8f1cc289-b30b-48e4-9fbc-ce8b88cc3c16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119329906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.119329906
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1487443539
Short name T631
Test name
Test status
Simulation time 6078286588 ps
CPU time 38.54 seconds
Started May 21 12:40:13 PM PDT 24
Finished May 21 12:40:56 PM PDT 24
Peak memory 200504 kb
Host smart-4c4de4df-cb2f-4bd3-864b-fdc5c96487db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1487443539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1487443539
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3000782523
Short name T987
Test name
Test status
Simulation time 125547297998 ps
CPU time 132.3 seconds
Started May 21 12:40:11 PM PDT 24
Finished May 21 12:42:28 PM PDT 24
Peak memory 200484 kb
Host smart-65ccb2cc-4f89-4ce2-b97b-9ae2c3b2bb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000782523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3000782523
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1137761780
Short name T967
Test name
Test status
Simulation time 4839038478 ps
CPU time 1.82 seconds
Started May 21 12:40:12 PM PDT 24
Finished May 21 12:40:18 PM PDT 24
Peak memory 196528 kb
Host smart-a1d857bc-1885-46b5-ac06-dcf9d4f945b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137761780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1137761780
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3121680934
Short name T1086
Test name
Test status
Simulation time 442430891 ps
CPU time 1.78 seconds
Started May 21 12:40:12 PM PDT 24
Finished May 21 12:40:18 PM PDT 24
Peak memory 199064 kb
Host smart-f48dbc30-7434-451f-8bb1-b30de7085ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121680934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3121680934
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2492487193
Short name T634
Test name
Test status
Simulation time 34513040021 ps
CPU time 657.5 seconds
Started May 21 12:40:12 PM PDT 24
Finished May 21 12:51:14 PM PDT 24
Peak memory 216948 kb
Host smart-0da102a5-ca8f-4e06-99c6-52370c06e9b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492487193 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2492487193
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1916767449
Short name T1007
Test name
Test status
Simulation time 1118772321 ps
CPU time 2.66 seconds
Started May 21 12:40:09 PM PDT 24
Finished May 21 12:40:16 PM PDT 24
Peak memory 198972 kb
Host smart-f0b65e22-2b6c-4ccd-9f32-777b60a4f13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916767449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1916767449
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3769908670
Short name T951
Test name
Test status
Simulation time 9498260732 ps
CPU time 19.16 seconds
Started May 21 12:40:10 PM PDT 24
Finished May 21 12:40:33 PM PDT 24
Peak memory 200404 kb
Host smart-bedb6cca-bbbc-4b7d-90bf-4827084662cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769908670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3769908670
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3637111754
Short name T188
Test name
Test status
Simulation time 12422084526 ps
CPU time 19.04 seconds
Started May 21 12:42:39 PM PDT 24
Finished May 21 12:42:59 PM PDT 24
Peak memory 200240 kb
Host smart-30e39ada-9c27-401b-8b91-f431b93d1130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637111754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3637111754
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.689815462
Short name T192
Test name
Test status
Simulation time 33160840868 ps
CPU time 57.33 seconds
Started May 21 12:42:35 PM PDT 24
Finished May 21 12:43:33 PM PDT 24
Peak memory 200452 kb
Host smart-3f75f887-b714-4400-9725-376571d01dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689815462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.689815462
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2493956938
Short name T664
Test name
Test status
Simulation time 52709047883 ps
CPU time 94.19 seconds
Started May 21 12:42:34 PM PDT 24
Finished May 21 12:44:10 PM PDT 24
Peak memory 200524 kb
Host smart-36b32763-572c-4f41-8bc4-c030df13d346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493956938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2493956938
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.4106068117
Short name T1025
Test name
Test status
Simulation time 110078232969 ps
CPU time 157.73 seconds
Started May 21 12:42:35 PM PDT 24
Finished May 21 12:45:14 PM PDT 24
Peak memory 200552 kb
Host smart-d6ab573e-c777-4980-91b6-517596cd2edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106068117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.4106068117
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.259597702
Short name T1102
Test name
Test status
Simulation time 229084281483 ps
CPU time 32.91 seconds
Started May 21 12:42:34 PM PDT 24
Finished May 21 12:43:08 PM PDT 24
Peak memory 200400 kb
Host smart-031cca93-35f0-4cc1-a1d4-8a50f451ae22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259597702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.259597702
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1785788299
Short name T328
Test name
Test status
Simulation time 116243597875 ps
CPU time 59.45 seconds
Started May 21 12:42:48 PM PDT 24
Finished May 21 12:43:49 PM PDT 24
Peak memory 200436 kb
Host smart-acdf87f8-0c0c-4d6f-94be-ef7c4f955148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785788299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1785788299
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1408190462
Short name T1048
Test name
Test status
Simulation time 98244999034 ps
CPU time 52.32 seconds
Started May 21 12:42:49 PM PDT 24
Finished May 21 12:43:45 PM PDT 24
Peak memory 200532 kb
Host smart-d7706a72-c399-4e22-85d3-325f8adf9cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408190462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1408190462
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3833729444
Short name T28
Test name
Test status
Simulation time 32564941 ps
CPU time 0.54 seconds
Started May 21 12:40:25 PM PDT 24
Finished May 21 12:40:34 PM PDT 24
Peak memory 195256 kb
Host smart-211cf4e5-006e-42b2-9fdc-35a7c6b2bd81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833729444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3833729444
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2196373846
Short name T646
Test name
Test status
Simulation time 80997510529 ps
CPU time 132.82 seconds
Started May 21 12:40:22 PM PDT 24
Finished May 21 12:42:43 PM PDT 24
Peak memory 200436 kb
Host smart-a38e8145-bea6-45a2-9d75-77e34e331161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196373846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2196373846
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2510661410
Short name T900
Test name
Test status
Simulation time 59967545570 ps
CPU time 28.13 seconds
Started May 21 12:40:18 PM PDT 24
Finished May 21 12:40:51 PM PDT 24
Peak memory 200460 kb
Host smart-2c1fed09-f1dc-4e0e-af60-07dd46686880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510661410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2510661410
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2176337754
Short name T1035
Test name
Test status
Simulation time 107072638679 ps
CPU time 80.23 seconds
Started May 21 12:40:26 PM PDT 24
Finished May 21 12:41:55 PM PDT 24
Peak memory 200504 kb
Host smart-f4d9202f-0e7a-4b9d-8432-528b3384aa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176337754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2176337754
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1904963085
Short name T40
Test name
Test status
Simulation time 122073081104 ps
CPU time 130.5 seconds
Started May 21 12:40:25 PM PDT 24
Finished May 21 12:42:44 PM PDT 24
Peak memory 200420 kb
Host smart-c5462493-0992-4816-977a-bdd9478d3512
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904963085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1904963085
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2286505954
Short name T1131
Test name
Test status
Simulation time 113799409814 ps
CPU time 187.04 seconds
Started May 21 12:40:22 PM PDT 24
Finished May 21 12:43:37 PM PDT 24
Peak memory 200480 kb
Host smart-fa1d08cf-a9f1-4fb1-9fdb-32decdacc69f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286505954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2286505954
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2613298703
Short name T317
Test name
Test status
Simulation time 7333375284 ps
CPU time 16.45 seconds
Started May 21 12:40:16 PM PDT 24
Finished May 21 12:40:37 PM PDT 24
Peak memory 200500 kb
Host smart-d8100fd4-c424-4497-92f4-fa26db940052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613298703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2613298703
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.848231890
Short name T1093
Test name
Test status
Simulation time 26219403045 ps
CPU time 48 seconds
Started May 21 12:40:24 PM PDT 24
Finished May 21 12:41:20 PM PDT 24
Peak memory 200760 kb
Host smart-53209a9f-b95b-4215-8f57-564087d90b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848231890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.848231890
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3558201455
Short name T952
Test name
Test status
Simulation time 14821069365 ps
CPU time 706.36 seconds
Started May 21 12:40:18 PM PDT 24
Finished May 21 12:52:10 PM PDT 24
Peak memory 200416 kb
Host smart-8671b033-7504-4899-945c-323faae7bf1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3558201455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3558201455
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1456270128
Short name T41
Test name
Test status
Simulation time 3583273161 ps
CPU time 5 seconds
Started May 21 12:40:18 PM PDT 24
Finished May 21 12:40:29 PM PDT 24
Peak memory 198768 kb
Host smart-07bd701d-5232-430f-8212-8a490906ba64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1456270128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1456270128
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2875923223
Short name T832
Test name
Test status
Simulation time 32245123256 ps
CPU time 24.49 seconds
Started May 21 12:40:18 PM PDT 24
Finished May 21 12:40:47 PM PDT 24
Peak memory 200304 kb
Host smart-a4aad233-945d-4fff-ae59-f15d7f524289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875923223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2875923223
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1389019827
Short name T922
Test name
Test status
Simulation time 41106238554 ps
CPU time 68.59 seconds
Started May 21 12:40:19 PM PDT 24
Finished May 21 12:41:33 PM PDT 24
Peak memory 196380 kb
Host smart-738e6a1e-7892-4a7a-9eb8-fef1d7b8aa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389019827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1389019827
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3349350672
Short name T508
Test name
Test status
Simulation time 5645272637 ps
CPU time 25.09 seconds
Started May 21 12:40:16 PM PDT 24
Finished May 21 12:40:45 PM PDT 24
Peak memory 200224 kb
Host smart-30594f08-05ab-4918-b91b-294f5dec190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349350672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3349350672
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1989291999
Short name T410
Test name
Test status
Simulation time 10410055032 ps
CPU time 122.05 seconds
Started May 21 12:40:23 PM PDT 24
Finished May 21 12:42:33 PM PDT 24
Peak memory 217264 kb
Host smart-b4c2a2a9-80dd-4a92-8b75-837d2b6f9959
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989291999 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1989291999
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3426135141
Short name T886
Test name
Test status
Simulation time 1899422937 ps
CPU time 1.73 seconds
Started May 21 12:40:19 PM PDT 24
Finished May 21 12:40:27 PM PDT 24
Peak memory 198764 kb
Host smart-1d1167eb-b383-40b3-afd7-538a73bff48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426135141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3426135141
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.616026307
Short name T51
Test name
Test status
Simulation time 21090578918 ps
CPU time 35.42 seconds
Started May 21 12:40:21 PM PDT 24
Finished May 21 12:41:04 PM PDT 24
Peak memory 200488 kb
Host smart-917a9c4a-0b4c-467c-ad75-7cd68c2cdad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616026307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.616026307
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1666283387
Short name T167
Test name
Test status
Simulation time 139032409505 ps
CPU time 74.39 seconds
Started May 21 12:42:42 PM PDT 24
Finished May 21 12:43:59 PM PDT 24
Peak memory 200232 kb
Host smart-0984d723-39cd-451a-9f0e-0c31ded55abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666283387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1666283387
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2949404354
Short name T803
Test name
Test status
Simulation time 116720635279 ps
CPU time 137.31 seconds
Started May 21 12:42:45 PM PDT 24
Finished May 21 12:45:04 PM PDT 24
Peak memory 200452 kb
Host smart-698c150e-19ab-42b7-9a89-8adc1972c547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949404354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2949404354
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3286930347
Short name T914
Test name
Test status
Simulation time 81474498908 ps
CPU time 160.02 seconds
Started May 21 12:42:43 PM PDT 24
Finished May 21 12:45:25 PM PDT 24
Peak memory 200456 kb
Host smart-85250d86-7955-4aa3-b9ba-e2c906ca5b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286930347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3286930347
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3850420828
Short name T891
Test name
Test status
Simulation time 19585622708 ps
CPU time 30.3 seconds
Started May 21 12:42:49 PM PDT 24
Finished May 21 12:43:22 PM PDT 24
Peak memory 200352 kb
Host smart-e75cfff2-868c-40fd-ba17-89f4a3415e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850420828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3850420828
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2520880567
Short name T957
Test name
Test status
Simulation time 59083696769 ps
CPU time 54.33 seconds
Started May 21 12:42:44 PM PDT 24
Finished May 21 12:43:40 PM PDT 24
Peak memory 200504 kb
Host smart-4313cba7-5f77-4500-bbca-14143f04ac58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520880567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2520880567
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2766835670
Short name T666
Test name
Test status
Simulation time 22363485010 ps
CPU time 33.04 seconds
Started May 21 12:42:45 PM PDT 24
Finished May 21 12:43:20 PM PDT 24
Peak memory 200416 kb
Host smart-8833fbca-366a-4f5f-bc7c-b7a698791a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766835670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2766835670
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3373306077
Short name T898
Test name
Test status
Simulation time 84618546441 ps
CPU time 18.74 seconds
Started May 21 12:42:44 PM PDT 24
Finished May 21 12:43:05 PM PDT 24
Peak memory 200540 kb
Host smart-57d1e1ca-2cf6-4315-b67b-52544aebe52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373306077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3373306077
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1819023974
Short name T1080
Test name
Test status
Simulation time 120440274762 ps
CPU time 54.47 seconds
Started May 21 12:42:42 PM PDT 24
Finished May 21 12:43:39 PM PDT 24
Peak memory 200396 kb
Host smart-63e853f2-36e3-43f1-bf5a-8a2831ec7970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819023974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1819023974
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2526823277
Short name T145
Test name
Test status
Simulation time 91198150547 ps
CPU time 42.65 seconds
Started May 21 12:42:42 PM PDT 24
Finished May 21 12:43:27 PM PDT 24
Peak memory 200452 kb
Host smart-f50849db-9b7a-4707-b37d-2d9fdb34415b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526823277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2526823277
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2135990109
Short name T678
Test name
Test status
Simulation time 26298652 ps
CPU time 0.58 seconds
Started May 21 12:40:17 PM PDT 24
Finished May 21 12:40:23 PM PDT 24
Peak memory 195272 kb
Host smart-8f70a5e0-2b82-4af7-bb97-72177d373fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135990109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2135990109
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3925657009
Short name T671
Test name
Test status
Simulation time 59441851834 ps
CPU time 23.93 seconds
Started May 21 12:40:20 PM PDT 24
Finished May 21 12:40:49 PM PDT 24
Peak memory 200440 kb
Host smart-c951da4d-2897-4efb-9fa4-48f141319b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925657009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3925657009
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2799550158
Short name T267
Test name
Test status
Simulation time 56318439450 ps
CPU time 48.96 seconds
Started May 21 12:40:17 PM PDT 24
Finished May 21 12:41:11 PM PDT 24
Peak memory 200352 kb
Host smart-7f879748-1a4d-48e0-8489-e8b88b666fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799550158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2799550158
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2519089319
Short name T439
Test name
Test status
Simulation time 131476661737 ps
CPU time 51.26 seconds
Started May 21 12:40:16 PM PDT 24
Finished May 21 12:41:12 PM PDT 24
Peak memory 200540 kb
Host smart-3ca6955d-5384-4d79-a7c7-22e269191900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519089319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2519089319
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2968018803
Short name T484
Test name
Test status
Simulation time 126123689391 ps
CPU time 105.07 seconds
Started May 21 12:40:16 PM PDT 24
Finished May 21 12:42:05 PM PDT 24
Peak memory 200512 kb
Host smart-9d246fb9-556b-4c35-9973-379d8a89589c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968018803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2968018803
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1627124574
Short name T510
Test name
Test status
Simulation time 146105257887 ps
CPU time 629.32 seconds
Started May 21 12:40:20 PM PDT 24
Finished May 21 12:50:56 PM PDT 24
Peak memory 200440 kb
Host smart-908956b3-11b5-4b99-a50f-32282ca2d92f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627124574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1627124574
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.4137365027
Short name T506
Test name
Test status
Simulation time 7187920447 ps
CPU time 4.89 seconds
Started May 21 12:40:22 PM PDT 24
Finished May 21 12:40:35 PM PDT 24
Peak memory 199572 kb
Host smart-eacfe42b-d470-4031-a4b1-f558c37f41b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137365027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.4137365027
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2004050104
Short name T578
Test name
Test status
Simulation time 91868845356 ps
CPU time 39.08 seconds
Started May 21 12:40:15 PM PDT 24
Finished May 21 12:40:59 PM PDT 24
Peak memory 200704 kb
Host smart-e69477ac-2834-4a16-a9c7-339ce4fce85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004050104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2004050104
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2891766817
Short name T282
Test name
Test status
Simulation time 6186169925 ps
CPU time 340.36 seconds
Started May 21 12:40:22 PM PDT 24
Finished May 21 12:46:10 PM PDT 24
Peak memory 200432 kb
Host smart-3110045a-c2d2-423d-9923-dd6f5fdcfe53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2891766817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2891766817
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2652676099
Short name T854
Test name
Test status
Simulation time 4750976668 ps
CPU time 21.47 seconds
Started May 21 12:40:18 PM PDT 24
Finished May 21 12:40:45 PM PDT 24
Peak memory 199560 kb
Host smart-5e804902-f27e-44aa-87b8-b4fb686618af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652676099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2652676099
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1282996221
Short name T404
Test name
Test status
Simulation time 40122023677 ps
CPU time 25.12 seconds
Started May 21 12:40:19 PM PDT 24
Finished May 21 12:40:50 PM PDT 24
Peak memory 200392 kb
Host smart-ede3dce8-8a3f-48ce-be3f-affa767d10ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282996221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1282996221
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.220620671
Short name T713
Test name
Test status
Simulation time 3051915536 ps
CPU time 3 seconds
Started May 21 12:40:17 PM PDT 24
Finished May 21 12:40:25 PM PDT 24
Peak memory 196336 kb
Host smart-77a714d4-de05-4f6b-82c8-2d6e4aac52ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220620671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.220620671
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1176565158
Short name T689
Test name
Test status
Simulation time 6067222010 ps
CPU time 19.66 seconds
Started May 21 12:40:22 PM PDT 24
Finished May 21 12:40:49 PM PDT 24
Peak memory 200344 kb
Host smart-7c667e0c-3b1f-4e9f-a9ec-8ac176676fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176565158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1176565158
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3677872228
Short name T216
Test name
Test status
Simulation time 492731053901 ps
CPU time 373.45 seconds
Started May 21 12:40:24 PM PDT 24
Finished May 21 12:46:46 PM PDT 24
Peak memory 200508 kb
Host smart-e8794054-3ba1-4bd5-8ef7-3bfc804115b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677872228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3677872228
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3796700065
Short name T60
Test name
Test status
Simulation time 245058368574 ps
CPU time 641.26 seconds
Started May 21 12:40:18 PM PDT 24
Finished May 21 12:51:05 PM PDT 24
Peak memory 216916 kb
Host smart-83eeb875-6c67-4932-9a28-086de4f636dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796700065 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3796700065
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3727327298
Short name T941
Test name
Test status
Simulation time 1012505685 ps
CPU time 3.97 seconds
Started May 21 12:40:20 PM PDT 24
Finished May 21 12:40:30 PM PDT 24
Peak memory 199324 kb
Host smart-53d143d8-61d7-412c-87f7-6466759df95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727327298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3727327298
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.4098212285
Short name T699
Test name
Test status
Simulation time 307643254993 ps
CPU time 74.48 seconds
Started May 21 12:40:20 PM PDT 24
Finished May 21 12:41:40 PM PDT 24
Peak memory 200480 kb
Host smart-93897c9a-6a00-40f7-b044-13232e55e067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098212285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.4098212285
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.595485190
Short name T887
Test name
Test status
Simulation time 47714986943 ps
CPU time 26.01 seconds
Started May 21 12:42:42 PM PDT 24
Finished May 21 12:43:09 PM PDT 24
Peak memory 200428 kb
Host smart-971df059-71d9-4c13-a9ce-aa664f9a1f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595485190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.595485190
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.4276829818
Short name T756
Test name
Test status
Simulation time 105786732573 ps
CPU time 170.98 seconds
Started May 21 12:42:41 PM PDT 24
Finished May 21 12:45:34 PM PDT 24
Peak memory 200548 kb
Host smart-741da141-570d-4775-8297-0cfc0802f3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276829818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4276829818
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3028712772
Short name T657
Test name
Test status
Simulation time 16688827302 ps
CPU time 32.07 seconds
Started May 21 12:42:43 PM PDT 24
Finished May 21 12:43:17 PM PDT 24
Peak memory 200372 kb
Host smart-8f9e9ae3-e942-45e3-8a6e-ca2511712005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028712772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3028712772
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.877838274
Short name T194
Test name
Test status
Simulation time 31740638243 ps
CPU time 52.05 seconds
Started May 21 12:42:44 PM PDT 24
Finished May 21 12:43:38 PM PDT 24
Peak memory 200516 kb
Host smart-8bad5541-8cf2-4b98-b8fc-f3cf6dd8645f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877838274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.877838274
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2807241868
Short name T1111
Test name
Test status
Simulation time 10240309434 ps
CPU time 18.47 seconds
Started May 21 12:42:43 PM PDT 24
Finished May 21 12:43:04 PM PDT 24
Peak memory 200280 kb
Host smart-6e09efc6-5fb2-4c88-a21f-ebd234a7de78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807241868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2807241868
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2968158328
Short name T1073
Test name
Test status
Simulation time 18535050597 ps
CPU time 8.69 seconds
Started May 21 12:42:51 PM PDT 24
Finished May 21 12:43:04 PM PDT 24
Peak memory 200424 kb
Host smart-ca2450ca-b90f-4186-885f-731d841092fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968158328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2968158328
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2148718273
Short name T228
Test name
Test status
Simulation time 52651655828 ps
CPU time 40.91 seconds
Started May 21 12:42:52 PM PDT 24
Finished May 21 12:43:37 PM PDT 24
Peak memory 200396 kb
Host smart-65a6dac4-98d8-4e95-bfd3-456b33be9bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148718273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2148718273
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2202994348
Short name T212
Test name
Test status
Simulation time 102643734452 ps
CPU time 79.79 seconds
Started May 21 12:42:50 PM PDT 24
Finished May 21 12:44:14 PM PDT 24
Peak memory 200392 kb
Host smart-d94af16e-c442-40ff-be9c-c08dfa5e4c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202994348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2202994348
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2309676106
Short name T838
Test name
Test status
Simulation time 40987787 ps
CPU time 0.54 seconds
Started May 21 12:40:28 PM PDT 24
Finished May 21 12:40:36 PM PDT 24
Peak memory 195756 kb
Host smart-95d58473-f758-4531-825c-da65249e9500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309676106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2309676106
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2243888008
Short name T608
Test name
Test status
Simulation time 129367974803 ps
CPU time 54.53 seconds
Started May 21 12:40:21 PM PDT 24
Finished May 21 12:41:22 PM PDT 24
Peak memory 200496 kb
Host smart-f03f3d63-1d46-41cc-8f8f-72d5f4fca74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243888008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2243888008
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3724017557
Short name T650
Test name
Test status
Simulation time 23345676007 ps
CPU time 35.88 seconds
Started May 21 12:40:19 PM PDT 24
Finished May 21 12:41:01 PM PDT 24
Peak memory 200288 kb
Host smart-c99b4536-f9d3-4f02-9281-0b0c6a7555f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724017557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3724017557
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3317770831
Short name T720
Test name
Test status
Simulation time 42521896706 ps
CPU time 30.14 seconds
Started May 21 12:40:20 PM PDT 24
Finished May 21 12:40:56 PM PDT 24
Peak memory 200476 kb
Host smart-744c5320-f0a5-4c6f-b1f0-2383c978ffab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317770831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3317770831
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2742816465
Short name T387
Test name
Test status
Simulation time 85552798727 ps
CPU time 52.97 seconds
Started May 21 12:40:19 PM PDT 24
Finished May 21 12:41:17 PM PDT 24
Peak memory 196512 kb
Host smart-166ff80f-bbee-4ad7-97d4-032b36f5db53
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742816465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2742816465
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2878078398
Short name T251
Test name
Test status
Simulation time 82689579104 ps
CPU time 174.09 seconds
Started May 21 12:40:23 PM PDT 24
Finished May 21 12:43:25 PM PDT 24
Peak memory 200328 kb
Host smart-1e26db91-37ef-45d7-927d-b53dce2abd87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2878078398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2878078398
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1384288085
Short name T477
Test name
Test status
Simulation time 8238514593 ps
CPU time 7.1 seconds
Started May 21 12:40:18 PM PDT 24
Finished May 21 12:40:30 PM PDT 24
Peak memory 199848 kb
Host smart-d85a753e-470f-4c29-8712-f74213d32797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384288085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1384288085
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3743810487
Short name T1051
Test name
Test status
Simulation time 84817864136 ps
CPU time 142.52 seconds
Started May 21 12:40:22 PM PDT 24
Finished May 21 12:42:51 PM PDT 24
Peak memory 200520 kb
Host smart-afed3503-2d2c-477f-9055-f83101f26a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743810487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3743810487
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2833971346
Short name T495
Test name
Test status
Simulation time 8284447465 ps
CPU time 105.83 seconds
Started May 21 12:40:22 PM PDT 24
Finished May 21 12:42:16 PM PDT 24
Peak memory 200360 kb
Host smart-76179c68-8c0b-489f-94cf-ecdd7de14f96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2833971346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2833971346
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3268228747
Short name T696
Test name
Test status
Simulation time 6561203807 ps
CPU time 27.49 seconds
Started May 21 12:40:21 PM PDT 24
Finished May 21 12:40:56 PM PDT 24
Peak memory 199672 kb
Host smart-c91d1dfa-6ea6-479c-a613-124bee6b306d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268228747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3268228747
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.579829272
Short name T820
Test name
Test status
Simulation time 55547755892 ps
CPU time 22.22 seconds
Started May 21 12:40:17 PM PDT 24
Finished May 21 12:40:44 PM PDT 24
Peak memory 200416 kb
Host smart-ee4b38be-f29c-4269-83c9-4518e8892fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579829272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.579829272
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2102324866
Short name T959
Test name
Test status
Simulation time 41443227826 ps
CPU time 16.02 seconds
Started May 21 12:40:18 PM PDT 24
Finished May 21 12:40:39 PM PDT 24
Peak memory 196092 kb
Host smart-4dc7d661-d83b-45e3-b50c-fb6b60819b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102324866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2102324866
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2077814254
Short name T57
Test name
Test status
Simulation time 726709636 ps
CPU time 1.83 seconds
Started May 21 12:40:17 PM PDT 24
Finished May 21 12:40:23 PM PDT 24
Peak memory 200100 kb
Host smart-45ac4be6-2c8e-45cc-b415-8b4c087f2543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077814254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2077814254
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1581283006
Short name T1069
Test name
Test status
Simulation time 1040688664 ps
CPU time 1.29 seconds
Started May 21 12:40:24 PM PDT 24
Finished May 21 12:40:33 PM PDT 24
Peak memory 198844 kb
Host smart-cd5fa5aa-641d-4d91-978e-f47772f4783b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581283006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1581283006
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.4061107767
Short name T68
Test name
Test status
Simulation time 91543138263 ps
CPU time 549.23 seconds
Started May 21 12:40:27 PM PDT 24
Finished May 21 12:49:44 PM PDT 24
Peak memory 217160 kb
Host smart-8b760af7-a157-4a4d-927a-950a3be968f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061107767 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.4061107767
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2558332815
Short name T698
Test name
Test status
Simulation time 2885225894 ps
CPU time 2.87 seconds
Started May 21 12:40:22 PM PDT 24
Finished May 21 12:40:32 PM PDT 24
Peak memory 199244 kb
Host smart-e4e0db53-2153-407b-ac8e-69670f581ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558332815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2558332815
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3707894248
Short name T286
Test name
Test status
Simulation time 53853000518 ps
CPU time 66.86 seconds
Started May 21 12:40:21 PM PDT 24
Finished May 21 12:41:35 PM PDT 24
Peak memory 200508 kb
Host smart-b0f6b3fa-c406-41e3-9a3f-d1e9030d5fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707894248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3707894248
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3378729312
Short name T1126
Test name
Test status
Simulation time 25765868501 ps
CPU time 48.84 seconds
Started May 21 12:42:52 PM PDT 24
Finished May 21 12:43:45 PM PDT 24
Peak memory 200452 kb
Host smart-82bc2494-a03b-453e-adbe-f340665e970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378729312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3378729312
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1764156220
Short name T969
Test name
Test status
Simulation time 76699291002 ps
CPU time 49.24 seconds
Started May 21 12:42:50 PM PDT 24
Finished May 21 12:43:43 PM PDT 24
Peak memory 200400 kb
Host smart-0021dfa2-adec-459e-b9f7-808ea5782dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764156220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1764156220
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2539494726
Short name T535
Test name
Test status
Simulation time 208869151054 ps
CPU time 192.28 seconds
Started May 21 12:42:50 PM PDT 24
Finished May 21 12:46:06 PM PDT 24
Peak memory 200432 kb
Host smart-ba36e204-d2cb-4ab6-9d16-13ebd9891c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539494726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2539494726
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2413374930
Short name T593
Test name
Test status
Simulation time 41706780245 ps
CPU time 37.78 seconds
Started May 21 12:42:49 PM PDT 24
Finished May 21 12:43:31 PM PDT 24
Peak memory 200480 kb
Host smart-8ec41428-da14-4915-b1ca-1d1f001912cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413374930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2413374930
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2634253708
Short name T158
Test name
Test status
Simulation time 75164361322 ps
CPU time 162.8 seconds
Started May 21 12:42:49 PM PDT 24
Finished May 21 12:45:35 PM PDT 24
Peak memory 200492 kb
Host smart-6ffc4c4f-f8c8-4c28-9726-b7bed7b9c4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634253708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2634253708
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.897837225
Short name T441
Test name
Test status
Simulation time 35295997118 ps
CPU time 23.84 seconds
Started May 21 12:42:50 PM PDT 24
Finished May 21 12:43:18 PM PDT 24
Peak memory 200412 kb
Host smart-02ac2da3-2d32-4d3e-b6f4-34db2e77d13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897837225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.897837225
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.4138569377
Short name T327
Test name
Test status
Simulation time 179596091870 ps
CPU time 72.36 seconds
Started May 21 12:42:50 PM PDT 24
Finished May 21 12:44:06 PM PDT 24
Peak memory 200492 kb
Host smart-b36599c9-2e59-4bce-a9c4-e9b36df5d64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138569377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.4138569377
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3667750537
Short name T208
Test name
Test status
Simulation time 17547451773 ps
CPU time 23.65 seconds
Started May 21 12:42:51 PM PDT 24
Finished May 21 12:43:18 PM PDT 24
Peak memory 200508 kb
Host smart-4d41dfe7-c5ab-4cc8-b476-e86a309ed0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667750537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3667750537
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2746302542
Short name T333
Test name
Test status
Simulation time 16555743889 ps
CPU time 28.54 seconds
Started May 21 12:42:52 PM PDT 24
Finished May 21 12:43:24 PM PDT 24
Peak memory 200448 kb
Host smart-1bc2260b-65f0-4d98-acc8-5f98c5c14315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746302542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2746302542
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3304707784
Short name T371
Test name
Test status
Simulation time 14998041915 ps
CPU time 23.73 seconds
Started May 21 12:42:49 PM PDT 24
Finished May 21 12:43:17 PM PDT 24
Peak memory 199424 kb
Host smart-6c2fdccf-7ef6-4778-8bda-55045ac65f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304707784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3304707784
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1715877255
Short name T668
Test name
Test status
Simulation time 37529146 ps
CPU time 0.6 seconds
Started May 21 12:40:23 PM PDT 24
Finished May 21 12:40:31 PM PDT 24
Peak memory 195896 kb
Host smart-a27ef9ab-762d-4be3-9294-9bb741c2362f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715877255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1715877255
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1897718630
Short name T532
Test name
Test status
Simulation time 47838968965 ps
CPU time 74.36 seconds
Started May 21 12:40:24 PM PDT 24
Finished May 21 12:41:46 PM PDT 24
Peak memory 200444 kb
Host smart-4ed544e8-6037-4362-a7ae-050798d9d9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897718630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1897718630
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2895467180
Short name T445
Test name
Test status
Simulation time 234189458349 ps
CPU time 436.27 seconds
Started May 21 12:40:27 PM PDT 24
Finished May 21 12:47:51 PM PDT 24
Peak memory 200592 kb
Host smart-2da00b72-025f-48d3-a614-16e84879a07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895467180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2895467180
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2681691599
Short name T59
Test name
Test status
Simulation time 19152345753 ps
CPU time 29.22 seconds
Started May 21 12:40:23 PM PDT 24
Finished May 21 12:41:00 PM PDT 24
Peak memory 200504 kb
Host smart-04dcc4bd-71e4-4352-a78c-187211747367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681691599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2681691599
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.77041194
Short name T1122
Test name
Test status
Simulation time 12357732962 ps
CPU time 2.14 seconds
Started May 21 12:40:23 PM PDT 24
Finished May 21 12:40:33 PM PDT 24
Peak memory 197692 kb
Host smart-cbbb6a36-1c5b-4b4f-a652-796398ae4896
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77041194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.77041194
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2457372725
Short name T356
Test name
Test status
Simulation time 129771627204 ps
CPU time 224.21 seconds
Started May 21 12:40:28 PM PDT 24
Finished May 21 12:44:20 PM PDT 24
Peak memory 200388 kb
Host smart-4adaba5e-e814-41a1-ba7a-c7e19621a606
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457372725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2457372725
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3522507522
Short name T868
Test name
Test status
Simulation time 1809455494 ps
CPU time 2.17 seconds
Started May 21 12:40:26 PM PDT 24
Finished May 21 12:40:37 PM PDT 24
Peak memory 197664 kb
Host smart-28301834-b84a-4370-8951-935c7757c83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522507522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3522507522
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.502116475
Short name T1000
Test name
Test status
Simulation time 20348954025 ps
CPU time 17.68 seconds
Started May 21 12:40:23 PM PDT 24
Finished May 21 12:40:49 PM PDT 24
Peak memory 198824 kb
Host smart-128be605-10cf-42dd-899a-70137d575d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502116475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.502116475
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3534496837
Short name T572
Test name
Test status
Simulation time 25969691768 ps
CPU time 319.01 seconds
Started May 21 12:40:24 PM PDT 24
Finished May 21 12:45:52 PM PDT 24
Peak memory 200508 kb
Host smart-c187233f-3ef4-4ad9-a13c-5b8efccd0aa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3534496837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3534496837
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3014780418
Short name T592
Test name
Test status
Simulation time 3070311997 ps
CPU time 3.95 seconds
Started May 21 12:40:26 PM PDT 24
Finished May 21 12:40:38 PM PDT 24
Peak memory 199712 kb
Host smart-ac39496b-a0e2-48ab-b906-0182888efeff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3014780418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3014780418
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1780967458
Short name T249
Test name
Test status
Simulation time 160425234473 ps
CPU time 168.76 seconds
Started May 21 12:40:26 PM PDT 24
Finished May 21 12:43:23 PM PDT 24
Peak memory 200520 kb
Host smart-aad58513-293b-4948-a901-b48d4e242ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780967458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1780967458
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2728053390
Short name T792
Test name
Test status
Simulation time 3915293960 ps
CPU time 6.41 seconds
Started May 21 12:40:24 PM PDT 24
Finished May 21 12:40:39 PM PDT 24
Peak memory 196424 kb
Host smart-257c865c-3ae3-4156-b587-41985e0b918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728053390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2728053390
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3543512364
Short name T516
Test name
Test status
Simulation time 708552668 ps
CPU time 1.41 seconds
Started May 21 12:40:24 PM PDT 24
Finished May 21 12:40:33 PM PDT 24
Peak memory 199204 kb
Host smart-bdb82be7-728c-4a53-a3ef-ed30abd50438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543512364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3543512364
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3049314078
Short name T915
Test name
Test status
Simulation time 120608621385 ps
CPU time 221.81 seconds
Started May 21 12:40:24 PM PDT 24
Finished May 21 12:44:14 PM PDT 24
Peak memory 200724 kb
Host smart-149861c3-bcf7-4cbb-9458-1a2f30c15092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049314078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3049314078
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1766290559
Short name T616
Test name
Test status
Simulation time 215858483707 ps
CPU time 526.66 seconds
Started May 21 12:40:24 PM PDT 24
Finished May 21 12:49:20 PM PDT 24
Peak memory 225368 kb
Host smart-6bae6c74-568c-48f7-9b71-0ae93ff9cb51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766290559 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1766290559
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2509419461
Short name T531
Test name
Test status
Simulation time 6744683628 ps
CPU time 22.64 seconds
Started May 21 12:40:28 PM PDT 24
Finished May 21 12:40:58 PM PDT 24
Peak memory 200448 kb
Host smart-3d0e0b4d-379d-43a6-836d-2baa59572aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509419461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2509419461
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.4240780944
Short name T853
Test name
Test status
Simulation time 58066406428 ps
CPU time 47.42 seconds
Started May 21 12:40:26 PM PDT 24
Finished May 21 12:41:22 PM PDT 24
Peak memory 200496 kb
Host smart-e919e2d6-82ce-4f15-8c46-0fd0bf4eb06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240780944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.4240780944
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2260041416
Short name T168
Test name
Test status
Simulation time 38381748298 ps
CPU time 54.73 seconds
Started May 21 12:42:49 PM PDT 24
Finished May 21 12:43:46 PM PDT 24
Peak memory 200496 kb
Host smart-2db305ba-0055-46a7-b679-c5527b3dbd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260041416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2260041416
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2161558375
Short name T714
Test name
Test status
Simulation time 57872379989 ps
CPU time 107.89 seconds
Started May 21 12:42:51 PM PDT 24
Finished May 21 12:44:42 PM PDT 24
Peak memory 200456 kb
Host smart-33bbb6f1-4409-4a86-8270-7080936be9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161558375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2161558375
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2156577248
Short name T1060
Test name
Test status
Simulation time 17872066349 ps
CPU time 27.73 seconds
Started May 21 12:42:53 PM PDT 24
Finished May 21 12:43:24 PM PDT 24
Peak memory 200552 kb
Host smart-ba35e18f-0fdf-46ac-a8f6-465128359edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156577248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2156577248
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.281298624
Short name T130
Test name
Test status
Simulation time 39577400355 ps
CPU time 32.82 seconds
Started May 21 12:42:51 PM PDT 24
Finished May 21 12:43:28 PM PDT 24
Peak memory 200568 kb
Host smart-d276d102-e194-46e5-881a-b2aa4e479a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281298624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.281298624
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3402261215
Short name T201
Test name
Test status
Simulation time 106541284225 ps
CPU time 55.73 seconds
Started May 21 12:42:50 PM PDT 24
Finished May 21 12:43:49 PM PDT 24
Peak memory 200460 kb
Host smart-41ad1e37-9f65-4405-8a73-4f47336e2804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402261215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3402261215
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.48587478
Short name T937
Test name
Test status
Simulation time 6320524916 ps
CPU time 24.02 seconds
Started May 21 12:42:51 PM PDT 24
Finished May 21 12:43:19 PM PDT 24
Peak memory 200528 kb
Host smart-e4c34309-cdfa-458d-8a98-0e8ffd80ac96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48587478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.48587478
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2952547232
Short name T329
Test name
Test status
Simulation time 57659219452 ps
CPU time 61.22 seconds
Started May 21 12:42:50 PM PDT 24
Finished May 21 12:43:55 PM PDT 24
Peak memory 200472 kb
Host smart-ee548eca-498c-4a2b-bb26-dd0187e4e5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952547232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2952547232
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3576785985
Short name T195
Test name
Test status
Simulation time 270295049660 ps
CPU time 64 seconds
Started May 21 12:42:49 PM PDT 24
Finished May 21 12:43:56 PM PDT 24
Peak memory 200504 kb
Host smart-af8d17d5-ad45-475c-b777-025ce6ad8d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576785985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3576785985
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3874078869
Short name T1136
Test name
Test status
Simulation time 13424071 ps
CPU time 0.55 seconds
Started May 21 12:40:29 PM PDT 24
Finished May 21 12:40:37 PM PDT 24
Peak memory 195272 kb
Host smart-a53cc2f4-e649-4fa1-8995-1de6539474da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874078869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3874078869
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1694520143
Short name T769
Test name
Test status
Simulation time 106187096023 ps
CPU time 57.13 seconds
Started May 21 12:40:27 PM PDT 24
Finished May 21 12:41:32 PM PDT 24
Peak memory 200432 kb
Host smart-7e7c8a15-b3f8-4a49-8cae-d42b79d763b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694520143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1694520143
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3923779325
Short name T1038
Test name
Test status
Simulation time 38668142402 ps
CPU time 72.43 seconds
Started May 21 12:40:24 PM PDT 24
Finished May 21 12:41:45 PM PDT 24
Peak memory 200436 kb
Host smart-3e093811-26ea-4be0-837c-f0aedf6599f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923779325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3923779325
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1508973323
Short name T932
Test name
Test status
Simulation time 99133713472 ps
CPU time 144.97 seconds
Started May 21 12:40:24 PM PDT 24
Finished May 21 12:42:57 PM PDT 24
Peak memory 200540 kb
Host smart-26370fc9-d463-4946-9df0-57e0d0b562c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508973323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1508973323
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2282794997
Short name T701
Test name
Test status
Simulation time 189727891038 ps
CPU time 325.44 seconds
Started May 21 12:40:25 PM PDT 24
Finished May 21 12:45:58 PM PDT 24
Peak memory 198396 kb
Host smart-e0a36a18-e4f1-4936-b937-0ca9d23900ac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282794997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2282794997
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.904984177
Short name T679
Test name
Test status
Simulation time 106531455802 ps
CPU time 847.02 seconds
Started May 21 12:40:25 PM PDT 24
Finished May 21 12:54:41 PM PDT 24
Peak memory 200488 kb
Host smart-5f112099-6b1b-42ab-978b-7043fd7928ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=904984177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.904984177
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2911439677
Short name T397
Test name
Test status
Simulation time 10517006808 ps
CPU time 21.31 seconds
Started May 21 12:40:23 PM PDT 24
Finished May 21 12:40:52 PM PDT 24
Peak memory 200496 kb
Host smart-982576bf-b927-41bc-b41c-f0f8f89e451f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911439677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2911439677
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3864459106
Short name T794
Test name
Test status
Simulation time 108882957912 ps
CPU time 43.31 seconds
Started May 21 12:40:25 PM PDT 24
Finished May 21 12:41:16 PM PDT 24
Peak memory 200524 kb
Host smart-2af8e804-8356-4328-b44f-64bdb330e742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864459106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3864459106
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.559611661
Short name T360
Test name
Test status
Simulation time 8053353602 ps
CPU time 486.44 seconds
Started May 21 12:40:29 PM PDT 24
Finished May 21 12:48:43 PM PDT 24
Peak memory 200472 kb
Host smart-68ff755c-351c-4920-9d9a-2750cf882948
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559611661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.559611661
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2676107831
Short name T1099
Test name
Test status
Simulation time 1827415336 ps
CPU time 3.29 seconds
Started May 21 12:40:25 PM PDT 24
Finished May 21 12:40:36 PM PDT 24
Peak memory 198284 kb
Host smart-aeefb204-a310-4f9b-9038-c05f5a4cde94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676107831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2676107831
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2735388260
Short name T164
Test name
Test status
Simulation time 110526152531 ps
CPU time 69.69 seconds
Started May 21 12:40:27 PM PDT 24
Finished May 21 12:41:45 PM PDT 24
Peak memory 200272 kb
Host smart-efe733fb-13fd-419e-a148-99377daa0954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735388260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2735388260
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.398624105
Short name T722
Test name
Test status
Simulation time 2381082854 ps
CPU time 4.3 seconds
Started May 21 12:40:24 PM PDT 24
Finished May 21 12:40:37 PM PDT 24
Peak memory 196524 kb
Host smart-1007fbef-51b0-41fe-a9d1-5e3cbdfa7f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398624105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.398624105
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3043356809
Short name T847
Test name
Test status
Simulation time 501210627 ps
CPU time 1.26 seconds
Started May 21 12:40:25 PM PDT 24
Finished May 21 12:40:35 PM PDT 24
Peak memory 198712 kb
Host smart-33284dfb-e658-41b8-a4f7-bedeef7d9dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043356809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3043356809
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2476489905
Short name T20
Test name
Test status
Simulation time 46097530550 ps
CPU time 239.66 seconds
Started May 21 12:40:29 PM PDT 24
Finished May 21 12:44:36 PM PDT 24
Peak memory 200388 kb
Host smart-d0283c76-8d1a-49c7-aebb-f364ffcd1d34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476489905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2476489905
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.290282584
Short name T879
Test name
Test status
Simulation time 73017022548 ps
CPU time 178.64 seconds
Started May 21 12:40:27 PM PDT 24
Finished May 21 12:43:34 PM PDT 24
Peak memory 216532 kb
Host smart-96e352d1-ac31-4d2e-9946-cf679b22602f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290282584 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.290282584
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1559299745
Short name T588
Test name
Test status
Simulation time 6254643518 ps
CPU time 17.55 seconds
Started May 21 12:40:26 PM PDT 24
Finished May 21 12:40:52 PM PDT 24
Peak memory 200336 kb
Host smart-afc90e0a-65d3-449e-98aa-da628fdd40f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559299745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1559299745
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3065642815
Short name T400
Test name
Test status
Simulation time 318138875969 ps
CPU time 28.97 seconds
Started May 21 12:40:24 PM PDT 24
Finished May 21 12:41:02 PM PDT 24
Peak memory 200248 kb
Host smart-413b49c4-6d0e-4d6a-8163-fbd065fad51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065642815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3065642815
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1585833059
Short name T231
Test name
Test status
Simulation time 18149209770 ps
CPU time 29.26 seconds
Started May 21 12:42:50 PM PDT 24
Finished May 21 12:43:23 PM PDT 24
Peak memory 200416 kb
Host smart-7b81fec6-64fd-4cd9-ae67-afe94ebefc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585833059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1585833059
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3951638390
Short name T499
Test name
Test status
Simulation time 78170055394 ps
CPU time 124.83 seconds
Started May 21 12:42:58 PM PDT 24
Finished May 21 12:45:05 PM PDT 24
Peak memory 200476 kb
Host smart-49e590cd-acf8-4980-b5a5-67d500a3ebfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951638390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3951638390
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2258601999
Short name T111
Test name
Test status
Simulation time 112914042017 ps
CPU time 178.04 seconds
Started May 21 12:42:57 PM PDT 24
Finished May 21 12:45:57 PM PDT 24
Peak memory 200532 kb
Host smart-eda2d028-44ba-4e60-94ff-add9a712e061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258601999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2258601999
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.4016988514
Short name T252
Test name
Test status
Simulation time 77066596362 ps
CPU time 29.74 seconds
Started May 21 12:42:57 PM PDT 24
Finished May 21 12:43:29 PM PDT 24
Peak memory 200536 kb
Host smart-8ad735be-e94b-4055-a022-a186cef062a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016988514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.4016988514
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3752601234
Short name T1062
Test name
Test status
Simulation time 75225874830 ps
CPU time 30.64 seconds
Started May 21 12:43:01 PM PDT 24
Finished May 21 12:43:33 PM PDT 24
Peak memory 200296 kb
Host smart-5e9d53ab-8849-45c4-ab39-9c7d9b5fcd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752601234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3752601234
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.133594175
Short name T39
Test name
Test status
Simulation time 88356706452 ps
CPU time 166.21 seconds
Started May 21 12:42:57 PM PDT 24
Finished May 21 12:45:45 PM PDT 24
Peak memory 200520 kb
Host smart-1323d763-4337-422c-9d91-2da310361f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133594175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.133594175
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3650417774
Short name T1003
Test name
Test status
Simulation time 27809312983 ps
CPU time 14.64 seconds
Started May 21 12:42:57 PM PDT 24
Finished May 21 12:43:14 PM PDT 24
Peak memory 200384 kb
Host smart-9b3e1798-a1f2-4fad-aed0-74e9b9f0ce79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650417774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3650417774
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.937741986
Short name T866
Test name
Test status
Simulation time 116130170036 ps
CPU time 44.6 seconds
Started May 21 12:42:59 PM PDT 24
Finished May 21 12:43:45 PM PDT 24
Peak memory 200576 kb
Host smart-c4a41371-cede-4874-8f9b-c3021b767697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937741986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.937741986
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3163662176
Short name T1100
Test name
Test status
Simulation time 12982087 ps
CPU time 0.55 seconds
Started May 21 12:40:38 PM PDT 24
Finished May 21 12:40:48 PM PDT 24
Peak memory 195548 kb
Host smart-738379a9-54af-4d43-b28e-d8f1b433c711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163662176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3163662176
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.396801509
Short name T294
Test name
Test status
Simulation time 145375253179 ps
CPU time 313.34 seconds
Started May 21 12:40:32 PM PDT 24
Finished May 21 12:45:53 PM PDT 24
Peak memory 200432 kb
Host smart-2beb38cc-6eb8-45a4-a4ef-2e70f6f6385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396801509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.396801509
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2815725890
Short name T462
Test name
Test status
Simulation time 198238889856 ps
CPU time 58.17 seconds
Started May 21 12:40:29 PM PDT 24
Finished May 21 12:41:34 PM PDT 24
Peak memory 200568 kb
Host smart-41fce196-6070-4795-8aee-515bf45110d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815725890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2815725890
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_intr.1912740827
Short name T1067
Test name
Test status
Simulation time 4452581310 ps
CPU time 1.98 seconds
Started May 21 12:40:40 PM PDT 24
Finished May 21 12:40:52 PM PDT 24
Peak memory 199780 kb
Host smart-b5e53a84-797e-44a6-acb8-4f940431cf24
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912740827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1912740827
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3527523652
Short name T858
Test name
Test status
Simulation time 130763793028 ps
CPU time 615.22 seconds
Started May 21 12:40:34 PM PDT 24
Finished May 21 12:50:56 PM PDT 24
Peak memory 200444 kb
Host smart-ad0c6e49-9dd4-4d87-89ba-c15633aae208
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3527523652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3527523652
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3625410633
Short name T411
Test name
Test status
Simulation time 7540830150 ps
CPU time 5.56 seconds
Started May 21 12:40:39 PM PDT 24
Finished May 21 12:40:53 PM PDT 24
Peak memory 200068 kb
Host smart-c3df1a2d-a1a1-4d03-943a-88fe7a3cc0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625410633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3625410633
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3937462555
Short name T711
Test name
Test status
Simulation time 64916941628 ps
CPU time 57.9 seconds
Started May 21 12:40:31 PM PDT 24
Finished May 21 12:41:36 PM PDT 24
Peak memory 199680 kb
Host smart-13b38a80-830c-489b-81d6-cd0cd98fceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937462555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3937462555
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.201478158
Short name T813
Test name
Test status
Simulation time 8192302917 ps
CPU time 183.34 seconds
Started May 21 12:40:31 PM PDT 24
Finished May 21 12:43:42 PM PDT 24
Peak memory 200448 kb
Host smart-6aabf769-1cb9-40f5-a72e-f3aa02ac4e41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201478158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.201478158
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4008410745
Short name T791
Test name
Test status
Simulation time 2219776589 ps
CPU time 3.93 seconds
Started May 21 12:40:32 PM PDT 24
Finished May 21 12:40:43 PM PDT 24
Peak memory 198552 kb
Host smart-ece83ee2-13d4-4f3a-b780-ab0d4827df2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4008410745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4008410745
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3237834152
Short name T958
Test name
Test status
Simulation time 105485366181 ps
CPU time 46.8 seconds
Started May 21 12:40:39 PM PDT 24
Finished May 21 12:41:35 PM PDT 24
Peak memory 200500 kb
Host smart-5f1eca5e-7477-417a-ba4c-39a89133e83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237834152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3237834152
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.4205637525
Short name T869
Test name
Test status
Simulation time 3766339603 ps
CPU time 7.06 seconds
Started May 21 12:40:37 PM PDT 24
Finished May 21 12:40:52 PM PDT 24
Peak memory 196732 kb
Host smart-57930f48-e1aa-4045-8dae-84de14d4514d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205637525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.4205637525
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.607189132
Short name T763
Test name
Test status
Simulation time 281882856 ps
CPU time 1.39 seconds
Started May 21 12:40:30 PM PDT 24
Finished May 21 12:40:38 PM PDT 24
Peak memory 198772 kb
Host smart-2a295154-da0c-4758-bb33-6de4338d2992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607189132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.607189132
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.4185322454
Short name T889
Test name
Test status
Simulation time 9788522174 ps
CPU time 116.61 seconds
Started May 21 12:40:32 PM PDT 24
Finished May 21 12:42:35 PM PDT 24
Peak memory 217248 kb
Host smart-6c554d54-cafe-4934-8df3-e8a7d5861f47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185322454 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.4185322454
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1685691719
Short name T661
Test name
Test status
Simulation time 1525654749 ps
CPU time 2.09 seconds
Started May 21 12:40:36 PM PDT 24
Finished May 21 12:40:46 PM PDT 24
Peak memory 198764 kb
Host smart-6227849c-3a44-479d-b3b2-aa6f86adb5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685691719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1685691719
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2854398719
Short name T1103
Test name
Test status
Simulation time 9850826190 ps
CPU time 14.39 seconds
Started May 21 12:40:25 PM PDT 24
Finished May 21 12:40:48 PM PDT 24
Peak memory 198084 kb
Host smart-9d74a310-08c3-4a3d-b97b-3486108692d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854398719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2854398719
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3319622942
Short name T290
Test name
Test status
Simulation time 100147582034 ps
CPU time 86.66 seconds
Started May 21 12:43:00 PM PDT 24
Finished May 21 12:44:29 PM PDT 24
Peak memory 200544 kb
Host smart-f5f45fc6-f78b-4f30-a9ab-bba82bf70788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319622942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3319622942
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1443471836
Short name T184
Test name
Test status
Simulation time 88464651870 ps
CPU time 41.86 seconds
Started May 21 12:42:57 PM PDT 24
Finished May 21 12:43:41 PM PDT 24
Peak memory 200488 kb
Host smart-f148096f-245a-4a29-945c-b1ffad77229d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443471836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1443471836
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2893423802
Short name T1128
Test name
Test status
Simulation time 42637882335 ps
CPU time 15.91 seconds
Started May 21 12:42:58 PM PDT 24
Finished May 21 12:43:16 PM PDT 24
Peak memory 200036 kb
Host smart-7b141f82-890c-4724-bd81-d4a2ea5ff5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893423802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2893423802
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.104535499
Short name T491
Test name
Test status
Simulation time 98960778200 ps
CPU time 51.67 seconds
Started May 21 12:42:58 PM PDT 24
Finished May 21 12:43:52 PM PDT 24
Peak memory 200428 kb
Host smart-c9503c64-c4ed-4dfd-8ed3-7a705f04ab09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104535499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.104535499
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2084401390
Short name T550
Test name
Test status
Simulation time 65779424760 ps
CPU time 51.88 seconds
Started May 21 12:43:04 PM PDT 24
Finished May 21 12:44:02 PM PDT 24
Peak memory 200476 kb
Host smart-33ff04b3-1690-4ed0-811e-7e856766f25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084401390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2084401390
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2191397635
Short name T126
Test name
Test status
Simulation time 15655048847 ps
CPU time 28.87 seconds
Started May 21 12:43:03 PM PDT 24
Finished May 21 12:43:37 PM PDT 24
Peak memory 200424 kb
Host smart-7e499e73-3f3c-475b-a4d7-3482d762c44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191397635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2191397635
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3671885982
Short name T598
Test name
Test status
Simulation time 139833029448 ps
CPU time 64.93 seconds
Started May 21 12:43:09 PM PDT 24
Finished May 21 12:44:18 PM PDT 24
Peak memory 200488 kb
Host smart-cd98fcf2-4dfe-4bb4-b324-bcd6750cc95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671885982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3671885982
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.4181511421
Short name T372
Test name
Test status
Simulation time 26664541093 ps
CPU time 41.51 seconds
Started May 21 12:43:03 PM PDT 24
Finished May 21 12:43:50 PM PDT 24
Peak memory 200432 kb
Host smart-ec5f85c0-0431-461f-89d1-35a433d00474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181511421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.4181511421
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3772637819
Short name T186
Test name
Test status
Simulation time 103276323637 ps
CPU time 51.51 seconds
Started May 21 12:43:06 PM PDT 24
Finished May 21 12:44:02 PM PDT 24
Peak memory 200428 kb
Host smart-5c7b3385-e6cf-49fd-9b55-d1cb8b3e934e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772637819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3772637819
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3912469641
Short name T731
Test name
Test status
Simulation time 98627735668 ps
CPU time 268.56 seconds
Started May 21 12:43:09 PM PDT 24
Finished May 21 12:47:42 PM PDT 24
Peak memory 200376 kb
Host smart-e4958876-5fb3-4999-b8da-bcf6ee3facc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912469641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3912469641
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3464624370
Short name T940
Test name
Test status
Simulation time 12689637 ps
CPU time 0.55 seconds
Started May 21 12:40:30 PM PDT 24
Finished May 21 12:40:38 PM PDT 24
Peak memory 195328 kb
Host smart-3f4ad56e-09b4-4957-a386-674c3688c58a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464624370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3464624370
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2988798852
Short name T401
Test name
Test status
Simulation time 377618643665 ps
CPU time 382.88 seconds
Started May 21 12:40:40 PM PDT 24
Finished May 21 12:47:12 PM PDT 24
Peak memory 200524 kb
Host smart-e3e55500-a4e7-4ae6-904c-852189f6a616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988798852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2988798852
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3754526414
Short name T885
Test name
Test status
Simulation time 44769183784 ps
CPU time 11.88 seconds
Started May 21 12:40:40 PM PDT 24
Finished May 21 12:41:00 PM PDT 24
Peak memory 200036 kb
Host smart-c9f13e5b-7b1c-44f6-9514-f27a379bff62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754526414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3754526414
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3362757481
Short name T160
Test name
Test status
Simulation time 106050989900 ps
CPU time 42.87 seconds
Started May 21 12:40:33 PM PDT 24
Finished May 21 12:41:23 PM PDT 24
Peak memory 200428 kb
Host smart-326c6832-289a-4d0a-998f-392589914058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362757481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3362757481
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1445586764
Short name T555
Test name
Test status
Simulation time 386637803703 ps
CPU time 648.46 seconds
Started May 21 12:40:37 PM PDT 24
Finished May 21 12:51:34 PM PDT 24
Peak memory 200436 kb
Host smart-f08e8e4e-e29e-436a-a56c-aa8b1eddb8df
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445586764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1445586764
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3665351222
Short name T548
Test name
Test status
Simulation time 121230689886 ps
CPU time 707.3 seconds
Started May 21 12:40:40 PM PDT 24
Finished May 21 12:52:36 PM PDT 24
Peak memory 200492 kb
Host smart-9a7de080-a811-4642-aa4a-b242c6942d9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3665351222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3665351222
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.350597046
Short name T335
Test name
Test status
Simulation time 3708699185 ps
CPU time 6.89 seconds
Started May 21 12:40:40 PM PDT 24
Finished May 21 12:40:57 PM PDT 24
Peak memory 200192 kb
Host smart-6048b91f-5c10-4d79-bb70-25d801f82bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350597046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.350597046
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1987356161
Short name T954
Test name
Test status
Simulation time 56038619515 ps
CPU time 47.25 seconds
Started May 21 12:40:39 PM PDT 24
Finished May 21 12:41:35 PM PDT 24
Peak memory 200696 kb
Host smart-e9422edf-2981-45ec-81da-f531578d0f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987356161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1987356161
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1129274330
Short name T599
Test name
Test status
Simulation time 10869504597 ps
CPU time 312.36 seconds
Started May 21 12:40:38 PM PDT 24
Finished May 21 12:45:59 PM PDT 24
Peak memory 200508 kb
Host smart-d754a71c-541c-4b8b-a413-d01b5a7e6dca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129274330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1129274330
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3572219214
Short name T956
Test name
Test status
Simulation time 5701214374 ps
CPU time 49.52 seconds
Started May 21 12:40:32 PM PDT 24
Finished May 21 12:41:29 PM PDT 24
Peak memory 200508 kb
Host smart-a2fac872-d6a4-4524-837c-5fcec8c7b748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572219214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3572219214
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2714101900
Short name T708
Test name
Test status
Simulation time 24618389778 ps
CPU time 33.99 seconds
Started May 21 12:40:36 PM PDT 24
Finished May 21 12:41:19 PM PDT 24
Peak memory 200528 kb
Host smart-f17cec9d-1e28-4b7d-91dc-a2b523e9b321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714101900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2714101900
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2426571700
Short name T1129
Test name
Test status
Simulation time 6206731749 ps
CPU time 10.55 seconds
Started May 21 12:40:32 PM PDT 24
Finished May 21 12:40:49 PM PDT 24
Peak memory 196396 kb
Host smart-2141eb93-03ac-4b6b-ae98-8798d31d8d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426571700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2426571700
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.4243658108
Short name T272
Test name
Test status
Simulation time 519655586 ps
CPU time 1.23 seconds
Started May 21 12:40:40 PM PDT 24
Finished May 21 12:40:50 PM PDT 24
Peak memory 198860 kb
Host smart-2c47fa23-990a-4c0c-940f-1b3863d65f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243658108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.4243658108
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.2293899666
Short name T653
Test name
Test status
Simulation time 47713128886 ps
CPU time 90.19 seconds
Started May 21 12:40:39 PM PDT 24
Finished May 21 12:42:18 PM PDT 24
Peak memory 200428 kb
Host smart-eab9291c-1280-4bf5-9e77-7478f84a426a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293899666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2293899666
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.725796443
Short name T814
Test name
Test status
Simulation time 127538225474 ps
CPU time 1276.36 seconds
Started May 21 12:40:30 PM PDT 24
Finished May 21 01:01:54 PM PDT 24
Peak memory 225460 kb
Host smart-125a4a34-772b-4964-92e4-b83661de525b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725796443 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.725796443
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1130766467
Short name T361
Test name
Test status
Simulation time 1199419006 ps
CPU time 3.12 seconds
Started May 21 12:40:30 PM PDT 24
Finished May 21 12:40:40 PM PDT 24
Peak memory 199440 kb
Host smart-a578fd3c-895c-4fb1-abe7-52319607409b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130766467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1130766467
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3587631494
Short name T393
Test name
Test status
Simulation time 18456944854 ps
CPU time 17.51 seconds
Started May 21 12:40:35 PM PDT 24
Finished May 21 12:41:00 PM PDT 24
Peak memory 200196 kb
Host smart-05aa5262-a5f8-455c-a86b-7ec9c6b6926d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587631494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3587631494
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.306053283
Short name T904
Test name
Test status
Simulation time 35975677329 ps
CPU time 48.66 seconds
Started May 21 12:43:02 PM PDT 24
Finished May 21 12:43:52 PM PDT 24
Peak memory 200512 kb
Host smart-ee504a73-44c1-496b-9848-3ae44677e8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306053283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.306053283
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.834266366
Short name T223
Test name
Test status
Simulation time 91587443508 ps
CPU time 73.59 seconds
Started May 21 12:43:02 PM PDT 24
Finished May 21 12:44:18 PM PDT 24
Peak memory 200368 kb
Host smart-b9e40325-81f8-475e-ba65-aae0d2186c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834266366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.834266366
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3310957415
Short name T1036
Test name
Test status
Simulation time 51788825772 ps
CPU time 44.95 seconds
Started May 21 12:43:04 PM PDT 24
Finished May 21 12:43:54 PM PDT 24
Peak memory 200348 kb
Host smart-fe546e0a-7b0f-460c-8ee6-9cae6ee19fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310957415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3310957415
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.64023003
Short name T648
Test name
Test status
Simulation time 16809132501 ps
CPU time 26.52 seconds
Started May 21 12:43:03 PM PDT 24
Finished May 21 12:43:33 PM PDT 24
Peak memory 200452 kb
Host smart-8fc4da2b-2897-46fe-9919-a019d98c7e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64023003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.64023003
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.274795143
Short name T185
Test name
Test status
Simulation time 19637190611 ps
CPU time 31.31 seconds
Started May 21 12:43:05 PM PDT 24
Finished May 21 12:43:41 PM PDT 24
Peak memory 200428 kb
Host smart-6bb5d154-ab8d-44b2-ac58-01675c1d173f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274795143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.274795143
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2505038142
Short name T700
Test name
Test status
Simulation time 108677642656 ps
CPU time 102.39 seconds
Started May 21 12:43:09 PM PDT 24
Finished May 21 12:44:56 PM PDT 24
Peak memory 200304 kb
Host smart-f31fade8-9746-4270-ae44-6d08424d8208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505038142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2505038142
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2223819083
Short name T189
Test name
Test status
Simulation time 29112898522 ps
CPU time 22.23 seconds
Started May 21 12:43:08 PM PDT 24
Finished May 21 12:43:34 PM PDT 24
Peak memory 200428 kb
Host smart-8b6ed47f-d665-48c2-95c2-8f095b780bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223819083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2223819083
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3513023837
Short name T996
Test name
Test status
Simulation time 25776094677 ps
CPU time 15.25 seconds
Started May 21 12:43:04 PM PDT 24
Finished May 21 12:43:24 PM PDT 24
Peak memory 200492 kb
Host smart-a2799382-25fc-47d0-885c-7f1e4ee661b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513023837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3513023837
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.330076048
Short name T733
Test name
Test status
Simulation time 91549644809 ps
CPU time 352.32 seconds
Started May 21 12:43:05 PM PDT 24
Finished May 21 12:49:03 PM PDT 24
Peak memory 200492 kb
Host smart-0174ab10-840d-4bf7-ac96-b2434167eb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330076048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.330076048
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.473352265
Short name T919
Test name
Test status
Simulation time 34527441 ps
CPU time 0.53 seconds
Started May 21 12:40:35 PM PDT 24
Finished May 21 12:40:44 PM PDT 24
Peak memory 195820 kb
Host smart-e7bd0309-adec-4695-b1a0-13f18deafb39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473352265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.473352265
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1315518789
Short name T1046
Test name
Test status
Simulation time 335318724452 ps
CPU time 119.81 seconds
Started May 21 12:40:31 PM PDT 24
Finished May 21 12:42:38 PM PDT 24
Peak memory 200468 kb
Host smart-003fae9d-f412-49b6-8c2d-c30d42578056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315518789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1315518789
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.4267228458
Short name T132
Test name
Test status
Simulation time 59178462766 ps
CPU time 13.79 seconds
Started May 21 12:40:34 PM PDT 24
Finished May 21 12:40:55 PM PDT 24
Peak memory 200512 kb
Host smart-88a3e017-47e8-4987-ab29-2d1e6e026e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267228458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.4267228458
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1762866187
Short name T580
Test name
Test status
Simulation time 94521501587 ps
CPU time 287.14 seconds
Started May 21 12:40:41 PM PDT 24
Finished May 21 12:45:38 PM PDT 24
Peak memory 200504 kb
Host smart-8a5717fd-4b83-4056-a6dd-785d092eaf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762866187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1762866187
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.425290017
Short name T804
Test name
Test status
Simulation time 16157214958 ps
CPU time 26.93 seconds
Started May 21 12:40:35 PM PDT 24
Finished May 21 12:41:10 PM PDT 24
Peak memory 200512 kb
Host smart-48d162cf-b178-4b23-aba9-d170052afcca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425290017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.425290017
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1608250900
Short name T415
Test name
Test status
Simulation time 66930638634 ps
CPU time 155.56 seconds
Started May 21 12:40:32 PM PDT 24
Finished May 21 12:43:14 PM PDT 24
Peak memory 200456 kb
Host smart-567d477a-44f7-4973-9f1e-74ff2366498f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608250900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1608250900
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1973811434
Short name T340
Test name
Test status
Simulation time 4317601186 ps
CPU time 5.86 seconds
Started May 21 12:40:39 PM PDT 24
Finished May 21 12:40:53 PM PDT 24
Peak memory 199260 kb
Host smart-2258b3cd-d587-4ca0-a4d4-b24f224efee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973811434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1973811434
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1831153805
Short name T695
Test name
Test status
Simulation time 48382796792 ps
CPU time 16.99 seconds
Started May 21 12:40:39 PM PDT 24
Finished May 21 12:41:05 PM PDT 24
Peak memory 200728 kb
Host smart-f90cc6bc-2294-4cab-bdfe-ce5891b67649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831153805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1831153805
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.165012177
Short name T245
Test name
Test status
Simulation time 26346891964 ps
CPU time 144.62 seconds
Started May 21 12:40:34 PM PDT 24
Finished May 21 12:43:05 PM PDT 24
Peak memory 200444 kb
Host smart-9f587d2c-3e57-4739-a6d9-790c75144b8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=165012177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.165012177
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.226474808
Short name T560
Test name
Test status
Simulation time 6183065917 ps
CPU time 3.32 seconds
Started May 21 12:40:33 PM PDT 24
Finished May 21 12:40:43 PM PDT 24
Peak memory 199056 kb
Host smart-cad8a42c-6857-4815-b27b-26d7b642a26f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=226474808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.226474808
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2149458653
Short name T571
Test name
Test status
Simulation time 30106509643 ps
CPU time 11.42 seconds
Started May 21 12:40:35 PM PDT 24
Finished May 21 12:40:54 PM PDT 24
Peak memory 200404 kb
Host smart-3a6c9474-6be0-4dc4-a63c-957ea169f00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149458653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2149458653
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2495047324
Short name T964
Test name
Test status
Simulation time 2967041488 ps
CPU time 5.48 seconds
Started May 21 12:40:33 PM PDT 24
Finished May 21 12:40:45 PM PDT 24
Peak memory 196256 kb
Host smart-cf874f43-2ba7-4a24-a404-c3c71775fb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495047324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2495047324
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1864103124
Short name T291
Test name
Test status
Simulation time 498653958 ps
CPU time 2.04 seconds
Started May 21 12:40:36 PM PDT 24
Finished May 21 12:40:47 PM PDT 24
Peak memory 198880 kb
Host smart-3e0673d8-a506-47f2-a996-c86329722cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864103124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1864103124
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3609699071
Short name T1066
Test name
Test status
Simulation time 181196523655 ps
CPU time 613.59 seconds
Started May 21 12:40:32 PM PDT 24
Finished May 21 12:50:53 PM PDT 24
Peak memory 216948 kb
Host smart-66119d58-29d2-47ac-943b-1e6810d4de49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609699071 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3609699071
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.233749039
Short name T306
Test name
Test status
Simulation time 6982792391 ps
CPU time 25.12 seconds
Started May 21 12:40:34 PM PDT 24
Finished May 21 12:41:07 PM PDT 24
Peak memory 200144 kb
Host smart-9efd839f-b2ae-4b10-9938-1afeb7ef31e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233749039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.233749039
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.4244032215
Short name T732
Test name
Test status
Simulation time 80597639847 ps
CPU time 35.5 seconds
Started May 21 12:40:36 PM PDT 24
Finished May 21 12:41:20 PM PDT 24
Peak memory 200508 kb
Host smart-8f67a77b-1733-4664-ac06-6d5e362e937e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244032215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.4244032215
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1664497401
Short name T895
Test name
Test status
Simulation time 10489585674 ps
CPU time 18.41 seconds
Started May 21 12:43:09 PM PDT 24
Finished May 21 12:43:32 PM PDT 24
Peak memory 200284 kb
Host smart-591dcf7a-8dcd-410b-a1db-434b8017bd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664497401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1664497401
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3043087172
Short name T636
Test name
Test status
Simulation time 154315090246 ps
CPU time 83.99 seconds
Started May 21 12:43:08 PM PDT 24
Finished May 21 12:44:36 PM PDT 24
Peak memory 200320 kb
Host smart-367553c8-d76a-4653-886b-964f0094e227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043087172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3043087172
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3397862472
Short name T1055
Test name
Test status
Simulation time 64435204495 ps
CPU time 25.8 seconds
Started May 21 12:43:11 PM PDT 24
Finished May 21 12:43:41 PM PDT 24
Peak memory 200460 kb
Host smart-7ad0f471-4380-4bb0-8211-3d85ddf4cc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397862472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3397862472
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2280476561
Short name T512
Test name
Test status
Simulation time 66755043004 ps
CPU time 102.1 seconds
Started May 21 12:43:10 PM PDT 24
Finished May 21 12:44:56 PM PDT 24
Peak memory 200744 kb
Host smart-3493059e-6eb1-4348-a861-8bd511a146a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280476561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2280476561
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.576035272
Short name T1163
Test name
Test status
Simulation time 226267974477 ps
CPU time 375.4 seconds
Started May 21 12:43:12 PM PDT 24
Finished May 21 12:49:31 PM PDT 24
Peak memory 200196 kb
Host smart-6f01e6d2-35c1-4108-93c2-8950dcd73b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576035272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.576035272
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2593421332
Short name T589
Test name
Test status
Simulation time 77863715700 ps
CPU time 38.21 seconds
Started May 21 12:43:10 PM PDT 24
Finished May 21 12:43:52 PM PDT 24
Peak memory 200384 kb
Host smart-beedbfee-5238-4923-91bb-437da2065cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593421332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2593421332
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3827820729
Short name T203
Test name
Test status
Simulation time 9268593601 ps
CPU time 16.69 seconds
Started May 21 12:43:10 PM PDT 24
Finished May 21 12:43:31 PM PDT 24
Peak memory 200448 kb
Host smart-24236a1e-e0b9-48c9-badd-648ef99ad056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827820729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3827820729
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2319377077
Short name T568
Test name
Test status
Simulation time 32896771831 ps
CPU time 24.59 seconds
Started May 21 12:43:11 PM PDT 24
Finished May 21 12:43:40 PM PDT 24
Peak memory 200432 kb
Host smart-237c33f8-a459-4f19-9219-abb61fa1bf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319377077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2319377077
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1587808727
Short name T543
Test name
Test status
Simulation time 8675986831 ps
CPU time 15.61 seconds
Started May 21 12:43:09 PM PDT 24
Finished May 21 12:43:28 PM PDT 24
Peak memory 200340 kb
Host smart-dd0133c5-3801-49e4-8407-d1eb070ac614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587808727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1587808727
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.146046263
Short name T156
Test name
Test status
Simulation time 34328927160 ps
CPU time 30.67 seconds
Started May 21 12:43:10 PM PDT 24
Finished May 21 12:43:44 PM PDT 24
Peak memory 200500 kb
Host smart-a134be8c-ad1b-4364-9a09-f893186b0582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146046263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.146046263
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1340011689
Short name T984
Test name
Test status
Simulation time 14517255 ps
CPU time 0.55 seconds
Started May 21 12:40:39 PM PDT 24
Finished May 21 12:40:48 PM PDT 24
Peak memory 195828 kb
Host smart-4656f67e-cf64-471b-9f85-d57ef829469e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340011689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1340011689
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1260423504
Short name T1013
Test name
Test status
Simulation time 151838536288 ps
CPU time 330.01 seconds
Started May 21 12:40:35 PM PDT 24
Finished May 21 12:46:12 PM PDT 24
Peak memory 200456 kb
Host smart-f3187f49-befb-439f-8f68-1350f6ff66d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260423504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1260423504
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.4057855049
Short name T659
Test name
Test status
Simulation time 20193209474 ps
CPU time 34.86 seconds
Started May 21 12:40:38 PM PDT 24
Finished May 21 12:41:22 PM PDT 24
Peak memory 200496 kb
Host smart-a16726db-ea7c-4869-9e78-d43bbd601031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057855049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.4057855049
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1051144779
Short name T703
Test name
Test status
Simulation time 35180042628 ps
CPU time 57.75 seconds
Started May 21 12:40:39 PM PDT 24
Finished May 21 12:41:46 PM PDT 24
Peak memory 200436 kb
Host smart-10831388-d4b1-4275-8f2e-979bc3fd88c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051144779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1051144779
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.170518827
Short name T478
Test name
Test status
Simulation time 56646035188 ps
CPU time 44.77 seconds
Started May 21 12:40:38 PM PDT 24
Finished May 21 12:41:32 PM PDT 24
Peak memory 200556 kb
Host smart-b0366e82-fff7-449a-8d08-93566ebe9195
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170518827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.170518827
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2558336073
Short name T367
Test name
Test status
Simulation time 74809551234 ps
CPU time 170.4 seconds
Started May 21 12:40:42 PM PDT 24
Finished May 21 12:43:43 PM PDT 24
Peak memory 200544 kb
Host smart-c2cde602-59ca-4bba-a416-685f1b04181b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2558336073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2558336073
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3909318439
Short name T545
Test name
Test status
Simulation time 6066027751 ps
CPU time 6.78 seconds
Started May 21 12:40:41 PM PDT 24
Finished May 21 12:40:58 PM PDT 24
Peak memory 199036 kb
Host smart-cd61bdb6-630a-40f0-8e6b-eeb6883d25d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909318439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3909318439
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2337965300
Short name T528
Test name
Test status
Simulation time 154774496354 ps
CPU time 68.82 seconds
Started May 21 12:40:37 PM PDT 24
Finished May 21 12:41:55 PM PDT 24
Peak memory 208940 kb
Host smart-89903e92-a6ce-4621-b0b7-1a66f59d16a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337965300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2337965300
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2186804931
Short name T1109
Test name
Test status
Simulation time 4635381914 ps
CPU time 50.51 seconds
Started May 21 12:40:40 PM PDT 24
Finished May 21 12:41:41 PM PDT 24
Peak memory 200472 kb
Host smart-ad479b70-1351-4089-90ec-27cb74849d48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2186804931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2186804931
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1815313345
Short name T453
Test name
Test status
Simulation time 6131107684 ps
CPU time 10.65 seconds
Started May 21 12:40:40 PM PDT 24
Finished May 21 12:41:00 PM PDT 24
Peak memory 199324 kb
Host smart-daadbdf5-b263-4409-81ca-08fefe1f517e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815313345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1815313345
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2597629352
Short name T643
Test name
Test status
Simulation time 43982545344 ps
CPU time 38.83 seconds
Started May 21 12:40:42 PM PDT 24
Finished May 21 12:41:31 PM PDT 24
Peak memory 200316 kb
Host smart-15375d55-876a-4583-b0b6-16fa6b8bd46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597629352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2597629352
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3161086182
Short name T1052
Test name
Test status
Simulation time 4620355853 ps
CPU time 7.13 seconds
Started May 21 12:40:39 PM PDT 24
Finished May 21 12:40:55 PM PDT 24
Peak memory 196488 kb
Host smart-1f43be8c-63f5-49b9-aeee-7d69aa1e2fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161086182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3161086182
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.294327782
Short name T1140
Test name
Test status
Simulation time 734431986 ps
CPU time 1.4 seconds
Started May 21 12:40:40 PM PDT 24
Finished May 21 12:40:50 PM PDT 24
Peak memory 198764 kb
Host smart-45c59648-2038-4004-88ec-804cf4c8ad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294327782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.294327782
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1205957497
Short name T931
Test name
Test status
Simulation time 283068971064 ps
CPU time 843.9 seconds
Started May 21 12:40:40 PM PDT 24
Finished May 21 12:54:54 PM PDT 24
Peak memory 225460 kb
Host smart-e6a9a9fc-5632-49c0-ac96-1b538b674cb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205957497 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1205957497
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1663727428
Short name T1040
Test name
Test status
Simulation time 7557130601 ps
CPU time 9.19 seconds
Started May 21 12:40:41 PM PDT 24
Finished May 21 12:41:00 PM PDT 24
Peak memory 200144 kb
Host smart-f2914270-62a3-4461-8c47-eec20893403d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663727428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1663727428
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2309178276
Short name T275
Test name
Test status
Simulation time 12276978247 ps
CPU time 10.17 seconds
Started May 21 12:40:36 PM PDT 24
Finished May 21 12:40:54 PM PDT 24
Peak memory 200228 kb
Host smart-9f1a1c72-eec9-4cd3-bbcc-013119b8ed4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309178276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2309178276
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1504508866
Short name T240
Test name
Test status
Simulation time 73749786443 ps
CPU time 23.35 seconds
Started May 21 12:43:11 PM PDT 24
Finished May 21 12:43:38 PM PDT 24
Peak memory 200536 kb
Host smart-d2d0a905-d063-4c6f-b170-922bdfd9f7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504508866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1504508866
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3084662603
Short name T125
Test name
Test status
Simulation time 29135049173 ps
CPU time 43.56 seconds
Started May 21 12:43:10 PM PDT 24
Finished May 21 12:43:57 PM PDT 24
Peak memory 200512 kb
Host smart-3643519c-0332-4e91-96db-57bdf585ee80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084662603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3084662603
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1143054523
Short name T1056
Test name
Test status
Simulation time 157824016833 ps
CPU time 259.37 seconds
Started May 21 12:43:13 PM PDT 24
Finished May 21 12:47:35 PM PDT 24
Peak memory 200512 kb
Host smart-ebfaf359-760a-47dc-b2fe-fc6ec2a0b4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143054523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1143054523
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3335801920
Short name T224
Test name
Test status
Simulation time 22320531575 ps
CPU time 39.68 seconds
Started May 21 12:43:10 PM PDT 24
Finished May 21 12:43:54 PM PDT 24
Peak memory 200428 kb
Host smart-15379144-f011-437b-9b57-75c18aa661b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335801920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3335801920
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3096725208
Short name T1076
Test name
Test status
Simulation time 83949103207 ps
CPU time 69.5 seconds
Started May 21 12:43:12 PM PDT 24
Finished May 21 12:44:25 PM PDT 24
Peak memory 200488 kb
Host smart-e74c36d3-5b10-4607-a20f-3a2b098f17ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096725208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3096725208
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1311974082
Short name T1094
Test name
Test status
Simulation time 27430250785 ps
CPU time 25.44 seconds
Started May 21 12:43:11 PM PDT 24
Finished May 21 12:43:41 PM PDT 24
Peak memory 200084 kb
Host smart-711661de-e7c3-49bc-b9b7-a2c463672e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311974082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1311974082
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.999240794
Short name T204
Test name
Test status
Simulation time 61205134422 ps
CPU time 31.67 seconds
Started May 21 12:43:17 PM PDT 24
Finished May 21 12:43:52 PM PDT 24
Peak memory 200496 kb
Host smart-4df82e93-784a-44d3-9a1f-1212f5a340ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999240794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.999240794
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3909305255
Short name T447
Test name
Test status
Simulation time 19572955520 ps
CPU time 33.07 seconds
Started May 21 12:43:16 PM PDT 24
Finished May 21 12:43:52 PM PDT 24
Peak memory 200460 kb
Host smart-b8ab2a08-813d-4b3d-bc2c-f8d939bbc426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909305255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3909305255
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2527705876
Short name T1158
Test name
Test status
Simulation time 88250825356 ps
CPU time 257.81 seconds
Started May 21 12:43:16 PM PDT 24
Finished May 21 12:47:37 PM PDT 24
Peak memory 200368 kb
Host smart-ac6078f7-5036-40c6-a723-4a2d935cb6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527705876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2527705876
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2842316243
Short name T323
Test name
Test status
Simulation time 32895484319 ps
CPU time 87.41 seconds
Started May 21 12:43:15 PM PDT 24
Finished May 21 12:44:45 PM PDT 24
Peak memory 200448 kb
Host smart-dc72ba99-88a1-4978-9fb2-0c837f4413d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842316243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2842316243
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2298054159
Short name T816
Test name
Test status
Simulation time 13063191 ps
CPU time 0.54 seconds
Started May 21 12:39:13 PM PDT 24
Finished May 21 12:39:24 PM PDT 24
Peak memory 195860 kb
Host smart-e39ed96a-b675-4268-a81e-90ea6fb3aa81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298054159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2298054159
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.4229537139
Short name T319
Test name
Test status
Simulation time 32322501795 ps
CPU time 38.36 seconds
Started May 21 12:39:31 PM PDT 24
Finished May 21 12:40:19 PM PDT 24
Peak memory 200512 kb
Host smart-f2d2e924-0120-42c7-b55e-32a4110e34c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229537139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.4229537139
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3654636314
Short name T116
Test name
Test status
Simulation time 230391441026 ps
CPU time 379.63 seconds
Started May 21 12:39:14 PM PDT 24
Finished May 21 12:45:44 PM PDT 24
Peak memory 200392 kb
Host smart-5c4ac6a6-6455-4aa3-b72d-cbbb063e4a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654636314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3654636314
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1703402995
Short name T127
Test name
Test status
Simulation time 27838357541 ps
CPU time 51.32 seconds
Started May 21 12:39:14 PM PDT 24
Finished May 21 12:40:16 PM PDT 24
Peak memory 200460 kb
Host smart-3348df0a-8d2a-43c5-a5df-a3b254d837d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703402995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1703402995
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.353962662
Short name T383
Test name
Test status
Simulation time 264675594726 ps
CPU time 142.11 seconds
Started May 21 12:39:26 PM PDT 24
Finished May 21 12:41:57 PM PDT 24
Peak memory 199908 kb
Host smart-01a18c78-a91a-4b20-b943-66a348a2cc9d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353962662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.353962662
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.4122753164
Short name T1095
Test name
Test status
Simulation time 214439570533 ps
CPU time 334.77 seconds
Started May 21 12:39:14 PM PDT 24
Finished May 21 12:45:00 PM PDT 24
Peak memory 200452 kb
Host smart-5e729720-8cda-4890-bbd1-daa729014374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122753164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.4122753164
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1836227713
Short name T1170
Test name
Test status
Simulation time 8545958444 ps
CPU time 8.03 seconds
Started May 21 12:39:19 PM PDT 24
Finished May 21 12:39:37 PM PDT 24
Peak memory 200444 kb
Host smart-9ec02221-6808-4a1f-99a0-fb6c00b5600e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836227713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1836227713
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.102532527
Short name T1049
Test name
Test status
Simulation time 18768330009 ps
CPU time 9.73 seconds
Started May 21 12:39:26 PM PDT 24
Finished May 21 12:39:45 PM PDT 24
Peak memory 195220 kb
Host smart-dbf63ca9-e08e-4fcc-ac8f-71049271d480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102532527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.102532527
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3024340408
Short name T849
Test name
Test status
Simulation time 9304481302 ps
CPU time 135.05 seconds
Started May 21 12:39:29 PM PDT 24
Finished May 21 12:41:53 PM PDT 24
Peak memory 200404 kb
Host smart-0ca705ce-f95a-4b67-86be-d5b069d1d391
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024340408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3024340408
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3032596020
Short name T828
Test name
Test status
Simulation time 3575625525 ps
CPU time 14.98 seconds
Started May 21 12:39:11 PM PDT 24
Finished May 21 12:39:35 PM PDT 24
Peak memory 199464 kb
Host smart-5ee2da56-c149-4716-a39b-3d8818456264
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3032596020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3032596020
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2648149474
Short name T320
Test name
Test status
Simulation time 28300617433 ps
CPU time 20.24 seconds
Started May 21 12:39:30 PM PDT 24
Finished May 21 12:40:00 PM PDT 24
Peak memory 199940 kb
Host smart-dc1dfd10-dadd-4936-bd6a-4b569be88057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648149474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2648149474
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3743993494
Short name T562
Test name
Test status
Simulation time 53808215677 ps
CPU time 15.99 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:40:01 PM PDT 24
Peak memory 196452 kb
Host smart-dc547b29-fbf5-42f6-95d5-879949fe4901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743993494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3743993494
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.4190075378
Short name T96
Test name
Test status
Simulation time 136040470 ps
CPU time 0.76 seconds
Started May 21 12:39:33 PM PDT 24
Finished May 21 12:39:43 PM PDT 24
Peak memory 218924 kb
Host smart-591e6dac-c761-4a7e-b72b-62b39d62ab90
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190075378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.4190075378
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3331252490
Short name T962
Test name
Test status
Simulation time 934042320 ps
CPU time 4.14 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:39:27 PM PDT 24
Peak memory 200380 kb
Host smart-525621b6-f14d-4b76-a9e3-8a9cf2ff64b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331252490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3331252490
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2178268021
Short name T826
Test name
Test status
Simulation time 207401938072 ps
CPU time 585.95 seconds
Started May 21 12:39:33 PM PDT 24
Finished May 21 12:49:28 PM PDT 24
Peak memory 200452 kb
Host smart-532b5ba2-5d7f-4f28-ac5d-1cfc96779614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178268021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2178268021
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.102093417
Short name T1065
Test name
Test status
Simulation time 141877516877 ps
CPU time 1457.1 seconds
Started May 21 12:39:13 PM PDT 24
Finished May 21 01:03:41 PM PDT 24
Peak memory 226764 kb
Host smart-bb3a7c27-f62d-47b2-a205-7351cc907c08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102093417 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.102093417
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3187254196
Short name T970
Test name
Test status
Simulation time 1978239500 ps
CPU time 4.71 seconds
Started May 21 12:39:14 PM PDT 24
Finished May 21 12:39:30 PM PDT 24
Peak memory 200120 kb
Host smart-e83292c1-56d4-412c-bd35-7e45a29b6da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187254196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3187254196
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1972544082
Short name T303
Test name
Test status
Simulation time 21343742257 ps
CPU time 40.68 seconds
Started May 21 12:39:14 PM PDT 24
Finished May 21 12:40:05 PM PDT 24
Peak memory 200440 kb
Host smart-ab2fc958-0a05-49be-acd1-2fefddce8e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972544082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1972544082
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.851121001
Short name T981
Test name
Test status
Simulation time 55395657 ps
CPU time 0.56 seconds
Started May 21 12:40:38 PM PDT 24
Finished May 21 12:40:47 PM PDT 24
Peak memory 195884 kb
Host smart-71ffb7ed-c02c-42e1-84b5-625675654787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851121001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.851121001
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.398315264
Short name T304
Test name
Test status
Simulation time 95758591277 ps
CPU time 164.76 seconds
Started May 21 12:40:38 PM PDT 24
Finished May 21 12:43:31 PM PDT 24
Peak memory 200540 kb
Host smart-d3a735eb-2be8-4b38-b236-b5c0417bcb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398315264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.398315264
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2174673777
Short name T554
Test name
Test status
Simulation time 128687148570 ps
CPU time 111.08 seconds
Started May 21 12:40:37 PM PDT 24
Finished May 21 12:42:36 PM PDT 24
Peak memory 200404 kb
Host smart-695dc6e7-7788-40d4-b285-d95fd7a445b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174673777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2174673777
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3143659993
Short name T1113
Test name
Test status
Simulation time 193534237319 ps
CPU time 363.49 seconds
Started May 21 12:40:40 PM PDT 24
Finished May 21 12:46:52 PM PDT 24
Peak memory 200680 kb
Host smart-02dab37f-885d-4b5c-88bb-a6370e958c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143659993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3143659993
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.60961112
Short name T1068
Test name
Test status
Simulation time 285128685472 ps
CPU time 72.02 seconds
Started May 21 12:40:38 PM PDT 24
Finished May 21 12:41:58 PM PDT 24
Peak memory 198628 kb
Host smart-67d727a9-f0d1-49e8-9272-318c557dee32
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60961112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.60961112
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.663643346
Short name T590
Test name
Test status
Simulation time 177207654077 ps
CPU time 1057.19 seconds
Started May 21 12:40:41 PM PDT 24
Finished May 21 12:58:28 PM PDT 24
Peak memory 200208 kb
Host smart-76f25583-b1e9-481f-b44a-7b73f8c860ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=663643346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.663643346
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3994495838
Short name T920
Test name
Test status
Simulation time 2071914832 ps
CPU time 3.53 seconds
Started May 21 12:40:39 PM PDT 24
Finished May 21 12:40:51 PM PDT 24
Peak memory 195912 kb
Host smart-a7d0d6a1-75d5-446e-94c0-64cab0e6f513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994495838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3994495838
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.2190472682
Short name T910
Test name
Test status
Simulation time 22193605286 ps
CPU time 516.91 seconds
Started May 21 12:40:38 PM PDT 24
Finished May 21 12:49:23 PM PDT 24
Peak memory 200424 kb
Host smart-ccc535c7-6a83-40f2-8b67-55bdd12e7278
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190472682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2190472682
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3779060562
Short name T839
Test name
Test status
Simulation time 6645141612 ps
CPU time 3.38 seconds
Started May 21 12:40:39 PM PDT 24
Finished May 21 12:40:51 PM PDT 24
Peak memory 199152 kb
Host smart-ed553219-b27c-41b7-90b3-74bcb7ab3a04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3779060562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3779060562
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.285505503
Short name T870
Test name
Test status
Simulation time 95586723196 ps
CPU time 42.5 seconds
Started May 21 12:40:37 PM PDT 24
Finished May 21 12:41:28 PM PDT 24
Peak memory 200392 kb
Host smart-06460fd1-3fc4-4cc3-b26c-7d48bf2b571b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285505503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.285505503
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2079958289
Short name T302
Test name
Test status
Simulation time 4827245492 ps
CPU time 4.63 seconds
Started May 21 12:40:39 PM PDT 24
Finished May 21 12:40:52 PM PDT 24
Peak memory 196424 kb
Host smart-7b14e320-2d45-44ec-918e-95e72f8c1270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079958289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2079958289
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2181961278
Short name T563
Test name
Test status
Simulation time 290905458 ps
CPU time 1.11 seconds
Started May 21 12:40:41 PM PDT 24
Finished May 21 12:40:52 PM PDT 24
Peak memory 199336 kb
Host smart-db2399d1-6c2a-4b6a-8dab-d1406f4a91fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181961278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2181961278
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3614449988
Short name T567
Test name
Test status
Simulation time 85148655668 ps
CPU time 415 seconds
Started May 21 12:40:39 PM PDT 24
Finished May 21 12:47:43 PM PDT 24
Peak memory 217236 kb
Host smart-4fb42c69-f3b3-47af-906d-84f1faf75719
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614449988 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3614449988
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.209274961
Short name T724
Test name
Test status
Simulation time 7534241965 ps
CPU time 16.93 seconds
Started May 21 12:40:38 PM PDT 24
Finished May 21 12:41:03 PM PDT 24
Peak memory 200444 kb
Host smart-a7ea8348-7fe7-4ab4-ac0d-31b0164febe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209274961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.209274961
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.4077546475
Short name T261
Test name
Test status
Simulation time 108506550742 ps
CPU time 223.52 seconds
Started May 21 12:40:38 PM PDT 24
Finished May 21 12:44:29 PM PDT 24
Peak memory 200480 kb
Host smart-11934d32-be33-424e-89fa-9befde87746c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077546475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.4077546475
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3736274690
Short name T1105
Test name
Test status
Simulation time 34277718 ps
CPU time 0.56 seconds
Started May 21 12:40:49 PM PDT 24
Finished May 21 12:41:00 PM PDT 24
Peak memory 195884 kb
Host smart-d6180b52-45c3-4d8f-b15f-9532166db0aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736274690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3736274690
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.57275016
Short name T946
Test name
Test status
Simulation time 44484523072 ps
CPU time 78.84 seconds
Started May 21 12:40:46 PM PDT 24
Finished May 21 12:42:15 PM PDT 24
Peak memory 200480 kb
Host smart-4cad318d-981c-48e5-8e69-a974dc2f8c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57275016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.57275016
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2092458096
Short name T284
Test name
Test status
Simulation time 124777962947 ps
CPU time 76.04 seconds
Started May 21 12:40:45 PM PDT 24
Finished May 21 12:42:10 PM PDT 24
Peak memory 200536 kb
Host smart-181f03cd-ca35-4eaf-8295-c4e9f7ca094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092458096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2092458096
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2460981549
Short name T924
Test name
Test status
Simulation time 13527577793 ps
CPU time 21.34 seconds
Started May 21 12:40:49 PM PDT 24
Finished May 21 12:41:20 PM PDT 24
Peak memory 200180 kb
Host smart-5093e1df-eef6-422c-8bc9-df57544ddfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460981549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2460981549
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.365894493
Short name T427
Test name
Test status
Simulation time 216916459163 ps
CPU time 76.25 seconds
Started May 21 12:40:47 PM PDT 24
Finished May 21 12:42:13 PM PDT 24
Peak memory 197336 kb
Host smart-ba9b15a1-9c1a-4873-9b11-902de3faab58
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365894493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.365894493
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.60604085
Short name T473
Test name
Test status
Simulation time 147189276370 ps
CPU time 959.11 seconds
Started May 21 12:40:49 PM PDT 24
Finished May 21 12:57:00 PM PDT 24
Peak memory 200464 kb
Host smart-44902c13-b6f9-4e52-b695-35e979af6033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60604085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.60604085
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3411348514
Short name T533
Test name
Test status
Simulation time 5612824132 ps
CPU time 11 seconds
Started May 21 12:40:48 PM PDT 24
Finished May 21 12:41:09 PM PDT 24
Peak memory 199212 kb
Host smart-d43c1379-cfd4-4c4e-b9ed-1a3f35cb6d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411348514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3411348514
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3959879694
Short name T670
Test name
Test status
Simulation time 73669852482 ps
CPU time 192.8 seconds
Started May 21 12:40:46 PM PDT 24
Finished May 21 12:44:09 PM PDT 24
Peak memory 200720 kb
Host smart-316669b2-bc0f-42cf-a6e9-76cfd24c48c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959879694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3959879694
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.4195279111
Short name T1089
Test name
Test status
Simulation time 13165248616 ps
CPU time 402.41 seconds
Started May 21 12:40:50 PM PDT 24
Finished May 21 12:47:43 PM PDT 24
Peak memory 200508 kb
Host smart-e4a42f30-4a1f-4940-b518-b442386c0c16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4195279111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.4195279111
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2379058518
Short name T339
Test name
Test status
Simulation time 5307560752 ps
CPU time 43.59 seconds
Started May 21 12:40:45 PM PDT 24
Finished May 21 12:41:38 PM PDT 24
Peak memory 198460 kb
Host smart-5713e5e1-b437-4efc-8153-0df4103bcd9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2379058518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2379058518
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3714312018
Short name T806
Test name
Test status
Simulation time 144986064085 ps
CPU time 320.78 seconds
Started May 21 12:40:49 PM PDT 24
Finished May 21 12:46:21 PM PDT 24
Peak memory 200328 kb
Host smart-6458e52a-d58e-46bb-9031-196f0a0ce7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714312018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3714312018
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2594998312
Short name T428
Test name
Test status
Simulation time 4908390623 ps
CPU time 2.86 seconds
Started May 21 12:40:46 PM PDT 24
Finished May 21 12:40:59 PM PDT 24
Peak memory 196536 kb
Host smart-b8e8a4f4-1263-4675-a1ab-bfa23d3717f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594998312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2594998312
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.957246149
Short name T389
Test name
Test status
Simulation time 617737393 ps
CPU time 2.95 seconds
Started May 21 12:40:39 PM PDT 24
Finished May 21 12:40:50 PM PDT 24
Peak memory 198796 kb
Host smart-fd3c2898-effe-453e-aab4-086dc628fee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957246149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.957246149
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1688668857
Short name T721
Test name
Test status
Simulation time 173798896506 ps
CPU time 1059.41 seconds
Started May 21 12:40:46 PM PDT 24
Finished May 21 12:58:36 PM PDT 24
Peak memory 200464 kb
Host smart-66391eb1-de1e-4708-bac1-229d0820eb8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688668857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1688668857
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3754727454
Short name T748
Test name
Test status
Simulation time 1499423951 ps
CPU time 1.9 seconds
Started May 21 12:40:48 PM PDT 24
Finished May 21 12:41:00 PM PDT 24
Peak memory 199088 kb
Host smart-289f5e00-b737-437f-8295-1d119f1d7193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754727454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3754727454
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3011655137
Short name T637
Test name
Test status
Simulation time 36424448179 ps
CPU time 65.46 seconds
Started May 21 12:40:45 PM PDT 24
Finished May 21 12:42:00 PM PDT 24
Peak memory 200416 kb
Host smart-bd29014f-a1f4-44b5-aa25-afedc1312fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011655137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3011655137
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2354975005
Short name T757
Test name
Test status
Simulation time 27621279 ps
CPU time 0.57 seconds
Started May 21 12:40:49 PM PDT 24
Finished May 21 12:41:00 PM PDT 24
Peak memory 195880 kb
Host smart-232628d0-543c-48da-b7b7-b584e4c2b15e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354975005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2354975005
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.486253025
Short name T423
Test name
Test status
Simulation time 48543496327 ps
CPU time 44.02 seconds
Started May 21 12:40:48 PM PDT 24
Finished May 21 12:41:43 PM PDT 24
Peak memory 200440 kb
Host smart-b5e7f694-e4ba-44d7-91ae-a866d037f38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486253025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.486253025
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3682555097
Short name T686
Test name
Test status
Simulation time 64939010222 ps
CPU time 75.4 seconds
Started May 21 12:40:47 PM PDT 24
Finished May 21 12:42:13 PM PDT 24
Peak memory 200416 kb
Host smart-af3ca5a4-0bf9-4dbc-b36a-e5a2a4147b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682555097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3682555097
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3849698073
Short name T1088
Test name
Test status
Simulation time 48531195318 ps
CPU time 16.44 seconds
Started May 21 12:40:50 PM PDT 24
Finished May 21 12:41:17 PM PDT 24
Peak memory 200448 kb
Host smart-3563720b-2082-4ea5-90ab-7b9b4d830a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849698073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3849698073
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1013006639
Short name T911
Test name
Test status
Simulation time 32897791919 ps
CPU time 28.81 seconds
Started May 21 12:40:48 PM PDT 24
Finished May 21 12:41:27 PM PDT 24
Peak memory 199344 kb
Host smart-6de237ed-84ff-4156-a9b7-6fbf1fb6af5b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013006639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1013006639
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2332744513
Short name T586
Test name
Test status
Simulation time 54103822182 ps
CPU time 283.09 seconds
Started May 21 12:40:49 PM PDT 24
Finished May 21 12:45:42 PM PDT 24
Peak memory 200504 kb
Host smart-32dccab1-705e-4450-8d08-90f51a023829
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332744513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2332744513
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2403704815
Short name T421
Test name
Test status
Simulation time 1111116241 ps
CPU time 0.97 seconds
Started May 21 12:40:48 PM PDT 24
Finished May 21 12:40:59 PM PDT 24
Peak memory 196124 kb
Host smart-f4a95dd1-b0a1-4e5f-9f92-c04148af372b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403704815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2403704815
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1815167801
Short name T824
Test name
Test status
Simulation time 26782565642 ps
CPU time 21.36 seconds
Started May 21 12:40:46 PM PDT 24
Finished May 21 12:41:18 PM PDT 24
Peak memory 200764 kb
Host smart-e6d99678-ec11-4552-9a94-4d5b780ea5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815167801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1815167801
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2695523664
Short name T363
Test name
Test status
Simulation time 10251465567 ps
CPU time 111.41 seconds
Started May 21 12:40:46 PM PDT 24
Finished May 21 12:42:48 PM PDT 24
Peak memory 200532 kb
Host smart-29b977ec-dc93-4f10-9d66-4c93b0958e21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2695523664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2695523664
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2518661701
Short name T658
Test name
Test status
Simulation time 4949159124 ps
CPU time 13 seconds
Started May 21 12:40:48 PM PDT 24
Finished May 21 12:41:11 PM PDT 24
Peak memory 199368 kb
Host smart-58039a1c-6ffe-498f-a56e-bedff88e8270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2518661701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2518661701
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1383548127
Short name T933
Test name
Test status
Simulation time 8572561269 ps
CPU time 14.6 seconds
Started May 21 12:40:50 PM PDT 24
Finished May 21 12:41:15 PM PDT 24
Peak memory 200472 kb
Host smart-36571117-727b-45ef-8548-1fc2a9f59770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383548127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1383548127
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1860270111
Short name T750
Test name
Test status
Simulation time 36842495568 ps
CPU time 57.79 seconds
Started May 21 12:40:46 PM PDT 24
Finished May 21 12:41:54 PM PDT 24
Peak memory 196208 kb
Host smart-a664a831-7233-49a0-a569-b9072366922a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860270111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1860270111
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3005512646
Short name T1167
Test name
Test status
Simulation time 495208426 ps
CPU time 2.09 seconds
Started May 21 12:40:48 PM PDT 24
Finished May 21 12:41:01 PM PDT 24
Peak memory 199556 kb
Host smart-a077e71a-059a-4697-9555-37acb7f61e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005512646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3005512646
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3609808523
Short name T737
Test name
Test status
Simulation time 361334769106 ps
CPU time 993.39 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:57:39 PM PDT 24
Peak memory 200436 kb
Host smart-cdc07f61-5838-4705-be87-b810715d403e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609808523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3609808523
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1813741356
Short name T742
Test name
Test status
Simulation time 1351972733 ps
CPU time 2.39 seconds
Started May 21 12:40:47 PM PDT 24
Finished May 21 12:40:59 PM PDT 24
Peak memory 199064 kb
Host smart-deefbbd5-74e9-4291-aa3d-636c9e400dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813741356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1813741356
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2495082068
Short name T878
Test name
Test status
Simulation time 51626208341 ps
CPU time 84.84 seconds
Started May 21 12:40:50 PM PDT 24
Finished May 21 12:42:26 PM PDT 24
Peak memory 200384 kb
Host smart-5258719c-9e1e-4389-878f-d9724d9da33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495082068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2495082068
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3234948613
Short name T29
Test name
Test status
Simulation time 37595624 ps
CPU time 0.55 seconds
Started May 21 12:41:04 PM PDT 24
Finished May 21 12:41:12 PM PDT 24
Peak memory 195848 kb
Host smart-3a94c8ea-3db4-48fa-be09-0358b628cae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234948613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3234948613
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2228773080
Short name T651
Test name
Test status
Simulation time 121479613946 ps
CPU time 190.43 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:44:16 PM PDT 24
Peak memory 200480 kb
Host smart-75741207-bd18-4219-a5f9-689660a94f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228773080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2228773080
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2188483994
Short name T1047
Test name
Test status
Simulation time 48023180125 ps
CPU time 21.68 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:41:27 PM PDT 24
Peak memory 200536 kb
Host smart-4a5d2d8a-f1fc-4071-ad6e-ba8f961a7728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188483994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2188483994
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2674073955
Short name T600
Test name
Test status
Simulation time 104924840336 ps
CPU time 203.48 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:44:28 PM PDT 24
Peak memory 200316 kb
Host smart-13cb91e7-86ca-4fbf-884d-eb76d2cad785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674073955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2674073955
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2693060963
Short name T865
Test name
Test status
Simulation time 82538726152 ps
CPU time 34.19 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:41:40 PM PDT 24
Peak memory 196480 kb
Host smart-14e348cc-8610-41d6-8e88-0b8f6fba8149
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693060963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2693060963
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2110218901
Short name T480
Test name
Test status
Simulation time 209917552293 ps
CPU time 256.57 seconds
Started May 21 12:40:54 PM PDT 24
Finished May 21 12:45:20 PM PDT 24
Peak memory 200520 kb
Host smart-4037ba9a-485b-4060-82f0-6af9a7b9f3cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2110218901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2110218901
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2648542664
Short name T341
Test name
Test status
Simulation time 2168091881 ps
CPU time 1.09 seconds
Started May 21 12:41:00 PM PDT 24
Finished May 21 12:41:09 PM PDT 24
Peak memory 196592 kb
Host smart-14066cbf-4395-4b2c-b697-9d2a06605241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648542664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2648542664
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1928912337
Short name T656
Test name
Test status
Simulation time 41826321528 ps
CPU time 63.99 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:42:09 PM PDT 24
Peak memory 200236 kb
Host smart-91f06ce3-b6d0-4e3b-9ccb-a673bfd20c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928912337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1928912337
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3306963541
Short name T944
Test name
Test status
Simulation time 11511137711 ps
CPU time 39.85 seconds
Started May 21 12:41:03 PM PDT 24
Finished May 21 12:41:50 PM PDT 24
Peak memory 200480 kb
Host smart-60fd295f-0f7c-4e1f-902c-9b2d16b4b4b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306963541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3306963541
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2670014063
Short name T617
Test name
Test status
Simulation time 1723504248 ps
CPU time 2.02 seconds
Started May 21 12:40:56 PM PDT 24
Finished May 21 12:41:08 PM PDT 24
Peak memory 198544 kb
Host smart-1aea0104-0417-45b0-ab92-192a1ac9de4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2670014063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2670014063
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2096391427
Short name T771
Test name
Test status
Simulation time 27638711667 ps
CPU time 44.68 seconds
Started May 21 12:40:52 PM PDT 24
Finished May 21 12:41:46 PM PDT 24
Peak memory 200496 kb
Host smart-06cc6c6a-6a2b-40ba-9aed-7ec09e2f431b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096391427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2096391427
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1187815907
Short name T916
Test name
Test status
Simulation time 6271894474 ps
CPU time 5.64 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:41:11 PM PDT 24
Peak memory 196484 kb
Host smart-a9209851-ea44-4734-91b2-22b8ee9d95c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187815907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1187815907
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2427415495
Short name T295
Test name
Test status
Simulation time 450842217 ps
CPU time 1.67 seconds
Started May 21 12:40:48 PM PDT 24
Finished May 21 12:41:01 PM PDT 24
Peak memory 198728 kb
Host smart-23e483c9-62f1-4501-9866-6c50eb40b9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427415495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2427415495
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3365981219
Short name T867
Test name
Test status
Simulation time 8132644815 ps
CPU time 96.94 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:42:43 PM PDT 24
Peak memory 200676 kb
Host smart-9c5fbdf7-04fa-4bbb-a295-b54ed2aa5b17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365981219 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3365981219
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3653266527
Short name T307
Test name
Test status
Simulation time 7268701654 ps
CPU time 8.38 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:41:13 PM PDT 24
Peak memory 200324 kb
Host smart-a0fa9fc8-cd90-430d-8e51-fd91bce2987a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653266527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3653266527
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2616037973
Short name T431
Test name
Test status
Simulation time 136855512590 ps
CPU time 55.22 seconds
Started May 21 12:40:48 PM PDT 24
Finished May 21 12:41:54 PM PDT 24
Peak memory 200344 kb
Host smart-8b6241b2-4096-4afc-9653-dbc5decf6fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616037973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2616037973
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.4006397144
Short name T337
Test name
Test status
Simulation time 43143190 ps
CPU time 0.6 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:41:06 PM PDT 24
Peak memory 195840 kb
Host smart-c53835e5-27b9-4abe-9141-1d6d92513471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006397144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.4006397144
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1842191736
Short name T502
Test name
Test status
Simulation time 139465165299 ps
CPU time 23.11 seconds
Started May 21 12:40:54 PM PDT 24
Finished May 21 12:41:27 PM PDT 24
Peak memory 200452 kb
Host smart-574817f5-254e-4154-8b06-bc8b27f45ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842191736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1842191736
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.141427755
Short name T242
Test name
Test status
Simulation time 80709545877 ps
CPU time 150.95 seconds
Started May 21 12:41:01 PM PDT 24
Finished May 21 12:43:40 PM PDT 24
Peak memory 200424 kb
Host smart-ad449100-42c2-40bc-aeb8-fb7c03505226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141427755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.141427755
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1786675996
Short name T856
Test name
Test status
Simulation time 14121233043 ps
CPU time 23.6 seconds
Started May 21 12:40:53 PM PDT 24
Finished May 21 12:41:25 PM PDT 24
Peak memory 200308 kb
Host smart-f0c2d768-1552-40bf-9233-427b00c76d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786675996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1786675996
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2159244399
Short name T762
Test name
Test status
Simulation time 22327593203 ps
CPU time 9.69 seconds
Started May 21 12:41:02 PM PDT 24
Finished May 21 12:41:20 PM PDT 24
Peak memory 200468 kb
Host smart-787ce2ea-3534-4711-ad1f-b5dc043bf0f1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159244399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2159244399
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2541718246
Short name T460
Test name
Test status
Simulation time 112471552919 ps
CPU time 657.32 seconds
Started May 21 12:40:56 PM PDT 24
Finished May 21 12:52:03 PM PDT 24
Peak memory 200752 kb
Host smart-9d6f074a-d74c-416e-b65e-57dae6c9a971
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2541718246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2541718246
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1604959675
Short name T974
Test name
Test status
Simulation time 7510731636 ps
CPU time 4.72 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:41:10 PM PDT 24
Peak memory 199916 kb
Host smart-0a80a625-40d5-484a-b998-c06b46c904f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604959675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1604959675
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.202561771
Short name T559
Test name
Test status
Simulation time 144147965053 ps
CPU time 229.79 seconds
Started May 21 12:40:54 PM PDT 24
Finished May 21 12:44:53 PM PDT 24
Peak memory 200700 kb
Host smart-e89c2558-f304-4f28-9585-1b9a8b65a7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202561771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.202561771
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1515807103
Short name T472
Test name
Test status
Simulation time 4942779643 ps
CPU time 277.22 seconds
Started May 21 12:40:56 PM PDT 24
Finished May 21 12:45:43 PM PDT 24
Peak memory 200532 kb
Host smart-beb69ba1-278f-458e-a1a0-e90c34cc1b3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515807103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1515807103
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1879039742
Short name T799
Test name
Test status
Simulation time 5180570350 ps
CPU time 7.83 seconds
Started May 21 12:41:02 PM PDT 24
Finished May 21 12:41:18 PM PDT 24
Peak memory 198628 kb
Host smart-1c4f416e-4468-462f-9caf-973460bc2a23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879039742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1879039742
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.365245517
Short name T566
Test name
Test status
Simulation time 245433383922 ps
CPU time 137.21 seconds
Started May 21 12:41:01 PM PDT 24
Finished May 21 12:43:26 PM PDT 24
Peak memory 200312 kb
Host smart-e595f489-8a25-4b1e-ab56-b499a101047f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365245517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.365245517
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1342481612
Short name T2
Test name
Test status
Simulation time 3455712609 ps
CPU time 1.84 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:41:07 PM PDT 24
Peak memory 196804 kb
Host smart-55881f35-d4ea-4194-9240-b891cc738943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342481612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1342481612
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.344019347
Short name T1120
Test name
Test status
Simulation time 734743970 ps
CPU time 3.06 seconds
Started May 21 12:40:56 PM PDT 24
Finished May 21 12:41:09 PM PDT 24
Peak memory 199128 kb
Host smart-3e789911-d8ee-4efb-8890-e58818be669a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344019347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.344019347
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2773975865
Short name T836
Test name
Test status
Simulation time 399451897776 ps
CPU time 478.1 seconds
Started May 21 12:40:56 PM PDT 24
Finished May 21 12:49:04 PM PDT 24
Peak memory 200456 kb
Host smart-52d450c4-6339-4bc7-ac43-ab4b1b844358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773975865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2773975865
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.670797731
Short name T985
Test name
Test status
Simulation time 279507563653 ps
CPU time 1037.19 seconds
Started May 21 12:41:01 PM PDT 24
Finished May 21 12:58:26 PM PDT 24
Peak memory 225400 kb
Host smart-5fc08d61-f630-4c2c-bb0c-4233c19a2023
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670797731 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.670797731
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3602707895
Short name T1118
Test name
Test status
Simulation time 6068038358 ps
CPU time 34.06 seconds
Started May 21 12:40:53 PM PDT 24
Finished May 21 12:41:37 PM PDT 24
Peak memory 200324 kb
Host smart-428f8c5a-62e5-4933-92f2-fd5cde486b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602707895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3602707895
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3559680847
Short name T930
Test name
Test status
Simulation time 10074059661 ps
CPU time 18.66 seconds
Started May 21 12:40:57 PM PDT 24
Finished May 21 12:41:25 PM PDT 24
Peak memory 200404 kb
Host smart-8dd76181-3fe8-4359-b1de-03478b913ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559680847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3559680847
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3761240107
Short name T382
Test name
Test status
Simulation time 18900914 ps
CPU time 0.55 seconds
Started May 21 12:41:01 PM PDT 24
Finished May 21 12:41:10 PM PDT 24
Peak memory 195864 kb
Host smart-80f2ef71-aab8-4285-8477-1c151fc0235a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761240107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3761240107
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.584287739
Short name T901
Test name
Test status
Simulation time 170372623941 ps
CPU time 102.14 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:42:48 PM PDT 24
Peak memory 200404 kb
Host smart-a37a050a-56f3-4247-9aa7-14fff3d36e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584287739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.584287739
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1165224413
Short name T667
Test name
Test status
Simulation time 94527446545 ps
CPU time 35.38 seconds
Started May 21 12:40:57 PM PDT 24
Finished May 21 12:41:42 PM PDT 24
Peak memory 200524 kb
Host smart-9ed495ef-8832-42a1-b2ed-d7eee9208517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165224413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1165224413
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3679306891
Short name T606
Test name
Test status
Simulation time 98654722233 ps
CPU time 38.87 seconds
Started May 21 12:40:57 PM PDT 24
Finished May 21 12:41:45 PM PDT 24
Peak memory 200408 kb
Host smart-fdf1e40e-826a-42fb-a35b-c45e9cfd69a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679306891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3679306891
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.891463390
Short name T1142
Test name
Test status
Simulation time 14007164490 ps
CPU time 11.8 seconds
Started May 21 12:41:01 PM PDT 24
Finished May 21 12:41:20 PM PDT 24
Peak memory 198256 kb
Host smart-518dd4b1-9186-4e05-8a7c-e76f239e68f1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891463390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.891463390
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3171527369
Short name T433
Test name
Test status
Simulation time 116034487616 ps
CPU time 593.13 seconds
Started May 21 12:41:01 PM PDT 24
Finished May 21 12:51:02 PM PDT 24
Peak memory 200460 kb
Host smart-07853296-9031-4592-acee-71202e40f3a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3171527369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3171527369
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2818460368
Short name T408
Test name
Test status
Simulation time 5313415563 ps
CPU time 4.25 seconds
Started May 21 12:41:02 PM PDT 24
Finished May 21 12:41:14 PM PDT 24
Peak memory 199420 kb
Host smart-acb59516-38b8-4343-8a86-6e94f02e0ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818460368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2818460368
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1919900103
Short name T547
Test name
Test status
Simulation time 5328814383 ps
CPU time 9 seconds
Started May 21 12:40:56 PM PDT 24
Finished May 21 12:41:15 PM PDT 24
Peak memory 200556 kb
Host smart-a05e88d0-75df-4982-abd1-ac2e29acff3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919900103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1919900103
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3536427208
Short name T894
Test name
Test status
Simulation time 13704677961 ps
CPU time 170.44 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:43:56 PM PDT 24
Peak memory 200304 kb
Host smart-5d5a70d8-e3fa-4936-b9b3-dc23b4d60efe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3536427208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3536427208
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1770007458
Short name T596
Test name
Test status
Simulation time 2688737975 ps
CPU time 16.91 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:41:22 PM PDT 24
Peak memory 198308 kb
Host smart-151caf03-df00-4590-843d-a8ca9fd9aaee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1770007458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1770007458
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1205053798
Short name T1087
Test name
Test status
Simulation time 344366763292 ps
CPU time 64.44 seconds
Started May 21 12:40:54 PM PDT 24
Finished May 21 12:42:08 PM PDT 24
Peak memory 200504 kb
Host smart-e7839b2a-5e64-49bb-989f-e33e7640001e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205053798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1205053798
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2675068056
Short name T821
Test name
Test status
Simulation time 44965537979 ps
CPU time 20.01 seconds
Started May 21 12:41:02 PM PDT 24
Finished May 21 12:41:30 PM PDT 24
Peak memory 196460 kb
Host smart-31acddaf-aed6-4fe5-a161-a415d09d42d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675068056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2675068056
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.510010602
Short name T101
Test name
Test status
Simulation time 5885388269 ps
CPU time 19.93 seconds
Started May 21 12:40:56 PM PDT 24
Finished May 21 12:41:26 PM PDT 24
Peak memory 200528 kb
Host smart-177dee10-afe2-4935-b885-c0092c32e8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510010602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.510010602
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2710950104
Short name T298
Test name
Test status
Simulation time 402988934824 ps
CPU time 200.46 seconds
Started May 21 12:41:00 PM PDT 24
Finished May 21 12:44:28 PM PDT 24
Peak memory 200524 kb
Host smart-e01e9226-ec74-47c6-bfef-18ff9dfd0791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710950104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2710950104
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3449465694
Short name T419
Test name
Test status
Simulation time 35177539354 ps
CPU time 447.69 seconds
Started May 21 12:40:54 PM PDT 24
Finished May 21 12:48:31 PM PDT 24
Peak memory 208696 kb
Host smart-b650b734-cbdb-4d6d-9367-9182e7deb453
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449465694 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3449465694
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.448602204
Short name T1141
Test name
Test status
Simulation time 1157994171 ps
CPU time 2.63 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:41:08 PM PDT 24
Peak memory 199628 kb
Host smart-3f823d1b-a5cd-4e30-ba69-fcef16ae9214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448602204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.448602204
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.695984151
Short name T1098
Test name
Test status
Simulation time 65309977524 ps
CPU time 49.78 seconds
Started May 21 12:40:55 PM PDT 24
Finished May 21 12:41:55 PM PDT 24
Peak memory 200520 kb
Host smart-c4c17651-642b-47c6-acf1-46888d109ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695984151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.695984151
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2559374297
Short name T837
Test name
Test status
Simulation time 14540394 ps
CPU time 0.57 seconds
Started May 21 12:41:01 PM PDT 24
Finished May 21 12:41:09 PM PDT 24
Peak memory 195844 kb
Host smart-e446a9f3-e88b-41b4-94bf-3b65ae0630af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559374297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2559374297
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3934219364
Short name T877
Test name
Test status
Simulation time 28896458937 ps
CPU time 11.46 seconds
Started May 21 12:40:59 PM PDT 24
Finished May 21 12:41:19 PM PDT 24
Peak memory 199512 kb
Host smart-688243c5-1a1e-407c-933b-7c023654c6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934219364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3934219364
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1005950178
Short name T466
Test name
Test status
Simulation time 24445120358 ps
CPU time 36.84 seconds
Started May 21 12:41:02 PM PDT 24
Finished May 21 12:41:47 PM PDT 24
Peak memory 200388 kb
Host smart-1f9b8369-958f-4a68-8046-70aa9b722555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005950178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1005950178
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3679867255
Short name T293
Test name
Test status
Simulation time 69629607053 ps
CPU time 22.21 seconds
Started May 21 12:41:01 PM PDT 24
Finished May 21 12:41:31 PM PDT 24
Peak memory 200512 kb
Host smart-3c867da5-e7f6-4249-a0b5-e90675cbb55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679867255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3679867255
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.343165878
Short name T765
Test name
Test status
Simulation time 293355609830 ps
CPU time 240.12 seconds
Started May 21 12:41:00 PM PDT 24
Finished May 21 12:45:08 PM PDT 24
Peak memory 197824 kb
Host smart-0d2fa006-fc2c-45ef-b401-342370c19cb8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343165878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.343165878
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1177093735
Short name T1175
Test name
Test status
Simulation time 137757506075 ps
CPU time 237.54 seconds
Started May 21 12:41:06 PM PDT 24
Finished May 21 12:45:10 PM PDT 24
Peak memory 200416 kb
Host smart-db710211-186e-42fc-9dc7-7a1a4c501ff5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1177093735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1177093735
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2115048626
Short name T953
Test name
Test status
Simulation time 3057512106 ps
CPU time 2.18 seconds
Started May 21 12:41:03 PM PDT 24
Finished May 21 12:41:12 PM PDT 24
Peak memory 198852 kb
Host smart-c7b008d3-f0f5-451e-94da-d4578a33098a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115048626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2115048626
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1423191697
Short name T256
Test name
Test status
Simulation time 287416450344 ps
CPU time 101.25 seconds
Started May 21 12:40:59 PM PDT 24
Finished May 21 12:42:49 PM PDT 24
Peak memory 200728 kb
Host smart-56102995-3507-44d9-9e2d-9e8e7c040b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423191697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1423191697
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1134002165
Short name T524
Test name
Test status
Simulation time 3158927207 ps
CPU time 85.51 seconds
Started May 21 12:41:02 PM PDT 24
Finished May 21 12:42:35 PM PDT 24
Peak memory 200468 kb
Host smart-4b8a26fd-df0d-4b46-92a6-3d32c9b5d56b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1134002165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1134002165
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1927067032
Short name T983
Test name
Test status
Simulation time 1482225850 ps
CPU time 5.99 seconds
Started May 21 12:41:00 PM PDT 24
Finished May 21 12:41:14 PM PDT 24
Peak memory 199756 kb
Host smart-91740b63-95f8-4b00-bfbc-61426d966cfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1927067032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1927067032
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.600967300
Short name T625
Test name
Test status
Simulation time 64735834592 ps
CPU time 115.47 seconds
Started May 21 12:41:01 PM PDT 24
Finished May 21 12:43:04 PM PDT 24
Peak memory 200420 kb
Host smart-b2526128-a9b7-4ce0-90c1-fb6779a777c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600967300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.600967300
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.4243800373
Short name T10
Test name
Test status
Simulation time 43020450174 ps
CPU time 20.28 seconds
Started May 21 12:41:09 PM PDT 24
Finished May 21 12:41:36 PM PDT 24
Peak memory 196444 kb
Host smart-b02ba6cd-2d24-46b3-975f-989a1a70be48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243800373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.4243800373
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2793632232
Short name T741
Test name
Test status
Simulation time 692422536 ps
CPU time 1.55 seconds
Started May 21 12:41:01 PM PDT 24
Finished May 21 12:41:10 PM PDT 24
Peak memory 198792 kb
Host smart-03870dc7-dcbb-4678-90c3-e94609a9fbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793632232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2793632232
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3383490468
Short name T49
Test name
Test status
Simulation time 61223654617 ps
CPU time 94.78 seconds
Started May 21 12:41:03 PM PDT 24
Finished May 21 12:42:45 PM PDT 24
Peak memory 200420 kb
Host smart-3b2a6f68-7dc8-45bc-8ec0-df2fbf350abd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383490468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3383490468
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1141399457
Short name T108
Test name
Test status
Simulation time 55334692181 ps
CPU time 526.23 seconds
Started May 21 12:41:00 PM PDT 24
Finished May 21 12:49:54 PM PDT 24
Peak memory 225472 kb
Host smart-2607f607-8234-474d-98d6-f9acdb5ef1be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141399457 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1141399457
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3516081425
Short name T488
Test name
Test status
Simulation time 2156734463 ps
CPU time 2.05 seconds
Started May 21 12:41:03 PM PDT 24
Finished May 21 12:41:12 PM PDT 24
Peak memory 198960 kb
Host smart-7dc48cea-0e1d-494b-8681-02fb164c7c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516081425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3516081425
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3969554884
Short name T330
Test name
Test status
Simulation time 103523460127 ps
CPU time 271.69 seconds
Started May 21 12:41:01 PM PDT 24
Finished May 21 12:45:40 PM PDT 24
Peak memory 200512 kb
Host smart-e59d0962-8959-43af-9c20-d37df8970f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969554884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3969554884
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3600868318
Short name T1144
Test name
Test status
Simulation time 12124864 ps
CPU time 0.55 seconds
Started May 21 12:41:09 PM PDT 24
Finished May 21 12:41:16 PM PDT 24
Peak memory 195812 kb
Host smart-f71c2591-b4ee-4cb0-9359-0c9e64149c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600868318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3600868318
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.4045521866
Short name T908
Test name
Test status
Simulation time 71725917742 ps
CPU time 11.09 seconds
Started May 21 12:40:59 PM PDT 24
Finished May 21 12:41:18 PM PDT 24
Peak memory 200456 kb
Host smart-8f1b7057-d139-4869-8475-8d5d016d74ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045521866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.4045521866
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1974471451
Short name T1019
Test name
Test status
Simulation time 46197406437 ps
CPU time 32.32 seconds
Started May 21 12:41:04 PM PDT 24
Finished May 21 12:41:44 PM PDT 24
Peak memory 200392 kb
Host smart-45a70823-e1a9-4645-a64e-edb9a2f9efba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974471451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1974471451
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_intr.3282700894
Short name T704
Test name
Test status
Simulation time 3741586587 ps
CPU time 3.78 seconds
Started May 21 12:41:00 PM PDT 24
Finished May 21 12:41:12 PM PDT 24
Peak memory 196544 kb
Host smart-44f0bb93-5dab-462e-9d13-4a19003dc841
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282700894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3282700894
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3265153221
Short name T26
Test name
Test status
Simulation time 114551165305 ps
CPU time 197.39 seconds
Started May 21 12:41:10 PM PDT 24
Finished May 21 12:44:34 PM PDT 24
Peak memory 200448 kb
Host smart-55490922-a3fe-40a6-9064-949b210d334d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265153221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3265153221
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.4218738758
Short name T527
Test name
Test status
Simulation time 405331640 ps
CPU time 0.84 seconds
Started May 21 12:41:07 PM PDT 24
Finished May 21 12:41:15 PM PDT 24
Peak memory 196812 kb
Host smart-30f71445-59da-4c9e-bb5c-aa0ef2948b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218738758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.4218738758
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.454550025
Short name T305
Test name
Test status
Simulation time 28053555709 ps
CPU time 21.42 seconds
Started May 21 12:41:06 PM PDT 24
Finished May 21 12:41:35 PM PDT 24
Peak memory 199680 kb
Host smart-4c8fb568-95a5-40de-ae79-c005f7b29013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454550025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.454550025
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.769695368
Short name T311
Test name
Test status
Simulation time 24297229014 ps
CPU time 267.71 seconds
Started May 21 12:41:05 PM PDT 24
Finished May 21 12:45:40 PM PDT 24
Peak memory 200412 kb
Host smart-39a0d3ea-c88b-49bb-9890-7f14acbbd827
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=769695368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.769695368
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.4133230914
Short name T414
Test name
Test status
Simulation time 6419428705 ps
CPU time 25.99 seconds
Started May 21 12:41:00 PM PDT 24
Finished May 21 12:41:34 PM PDT 24
Peak memory 199568 kb
Host smart-cf0a9e11-108e-4a7c-a461-4e65f64bef45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4133230914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.4133230914
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1920228212
Short name T829
Test name
Test status
Simulation time 66861767919 ps
CPU time 115.84 seconds
Started May 21 12:41:06 PM PDT 24
Finished May 21 12:43:09 PM PDT 24
Peak memory 200400 kb
Host smart-edbc0057-de26-4cce-b9c0-73fbfbe73b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920228212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1920228212
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1010680304
Short name T273
Test name
Test status
Simulation time 5053338870 ps
CPU time 2.75 seconds
Started May 21 12:41:05 PM PDT 24
Finished May 21 12:41:15 PM PDT 24
Peak memory 196776 kb
Host smart-e1793a7a-608b-40bd-b04f-3fb00deb0e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010680304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1010680304
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3282913050
Short name T351
Test name
Test status
Simulation time 576443057 ps
CPU time 2.42 seconds
Started May 21 12:41:00 PM PDT 24
Finished May 21 12:41:11 PM PDT 24
Peak memory 200248 kb
Host smart-05726479-34db-4b94-a45d-7cbdd6d8cc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282913050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3282913050
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1062505323
Short name T539
Test name
Test status
Simulation time 233512932464 ps
CPU time 202.77 seconds
Started May 21 12:41:06 PM PDT 24
Finished May 21 12:44:35 PM PDT 24
Peak memory 216676 kb
Host smart-f852f310-8bad-4407-b326-5e8ca930f553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062505323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1062505323
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.509364100
Short name T113
Test name
Test status
Simulation time 3713170227 ps
CPU time 2.58 seconds
Started May 21 12:41:09 PM PDT 24
Finished May 21 12:41:18 PM PDT 24
Peak memory 199132 kb
Host smart-4badd5a3-17c1-4e27-88dc-5557a33f69f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509364100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.509364100
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.530897419
Short name T310
Test name
Test status
Simulation time 227761132747 ps
CPU time 94.46 seconds
Started May 21 12:41:02 PM PDT 24
Finished May 21 12:42:44 PM PDT 24
Peak memory 200540 kb
Host smart-f32daf77-6f18-46e8-b16a-ab745954e831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530897419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.530897419
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2363357068
Short name T444
Test name
Test status
Simulation time 21517706 ps
CPU time 0.57 seconds
Started May 21 12:41:05 PM PDT 24
Finished May 21 12:41:13 PM PDT 24
Peak memory 195828 kb
Host smart-a566d93e-5e1b-4431-874c-668d96a298f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363357068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2363357068
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3413995958
Short name T736
Test name
Test status
Simulation time 139375952373 ps
CPU time 170.55 seconds
Started May 21 12:41:08 PM PDT 24
Finished May 21 12:44:06 PM PDT 24
Peak memory 200416 kb
Host smart-44f97282-841f-43c9-b4cb-8c6be90b9285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413995958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3413995958
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2461744399
Short name T903
Test name
Test status
Simulation time 131116604882 ps
CPU time 93.56 seconds
Started May 21 12:41:05 PM PDT 24
Finished May 21 12:42:46 PM PDT 24
Peak memory 200504 kb
Host smart-bca959ec-55c9-426e-9531-15118137658c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461744399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2461744399
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1217873952
Short name T331
Test name
Test status
Simulation time 68907769979 ps
CPU time 23.03 seconds
Started May 21 12:41:06 PM PDT 24
Finished May 21 12:41:36 PM PDT 24
Peak memory 200372 kb
Host smart-eb995a9a-ae48-4728-bcee-4b45b36ef3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217873952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1217873952
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3069419045
Short name T717
Test name
Test status
Simulation time 160756300260 ps
CPU time 194.06 seconds
Started May 21 12:41:05 PM PDT 24
Finished May 21 12:44:26 PM PDT 24
Peak memory 200296 kb
Host smart-50d5010f-7c42-4aac-a2be-dab82ac3e597
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069419045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3069419045
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.245212477
Short name T884
Test name
Test status
Simulation time 125585342219 ps
CPU time 471.25 seconds
Started May 21 12:41:09 PM PDT 24
Finished May 21 12:49:07 PM PDT 24
Peak memory 200536 kb
Host smart-05fe233d-5330-4be2-a5b0-6b15ce521120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245212477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.245212477
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2546776250
Short name T778
Test name
Test status
Simulation time 3552868933 ps
CPU time 3.6 seconds
Started May 21 12:41:09 PM PDT 24
Finished May 21 12:41:19 PM PDT 24
Peak memory 196280 kb
Host smart-911e4022-489e-4534-9ebe-c239b942d4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546776250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2546776250
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.563305050
Short name T690
Test name
Test status
Simulation time 123016615844 ps
CPU time 76.24 seconds
Started May 21 12:41:05 PM PDT 24
Finished May 21 12:42:28 PM PDT 24
Peak memory 200852 kb
Host smart-0fc45f0c-0844-4ac2-8433-5272edea04ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563305050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.563305050
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.423264153
Short name T968
Test name
Test status
Simulation time 19008876266 ps
CPU time 216.58 seconds
Started May 21 12:41:09 PM PDT 24
Finished May 21 12:44:53 PM PDT 24
Peak memory 200528 kb
Host smart-d38c03f1-73db-4e40-a1d0-9f6702d8f95d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=423264153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.423264153
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3360654120
Short name T673
Test name
Test status
Simulation time 3200250310 ps
CPU time 7.89 seconds
Started May 21 12:41:07 PM PDT 24
Finished May 21 12:41:22 PM PDT 24
Peak memory 199152 kb
Host smart-cb4cc2b6-aabc-4cf0-a867-d12a4fe33ea1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360654120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3360654120
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3786021454
Short name T446
Test name
Test status
Simulation time 109403188918 ps
CPU time 115.88 seconds
Started May 21 12:41:08 PM PDT 24
Finished May 21 12:43:11 PM PDT 24
Peak memory 200368 kb
Host smart-794ecfe3-a666-4ee6-9bd7-9dfff442c19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786021454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3786021454
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.4226849854
Short name T1053
Test name
Test status
Simulation time 697941943 ps
CPU time 0.9 seconds
Started May 21 12:41:09 PM PDT 24
Finished May 21 12:41:17 PM PDT 24
Peak memory 196148 kb
Host smart-e30975b1-f778-436d-8ec7-1cb83394d0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226849854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.4226849854
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.261630846
Short name T1032
Test name
Test status
Simulation time 299116562 ps
CPU time 0.98 seconds
Started May 21 12:41:05 PM PDT 24
Finished May 21 12:41:13 PM PDT 24
Peak memory 198896 kb
Host smart-0a67d258-15a4-49a6-9a0b-cd27d12dc539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261630846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.261630846
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.250793544
Short name T321
Test name
Test status
Simulation time 113507088614 ps
CPU time 225.01 seconds
Started May 21 12:41:07 PM PDT 24
Finished May 21 12:45:00 PM PDT 24
Peak memory 216924 kb
Host smart-784e6de9-9ccc-46d5-8597-c966ae9fbb24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250793544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.250793544
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1297597816
Short name T795
Test name
Test status
Simulation time 54109790250 ps
CPU time 604.44 seconds
Started May 21 12:41:08 PM PDT 24
Finished May 21 12:51:20 PM PDT 24
Peak memory 225364 kb
Host smart-3f33b35d-1cc6-47d2-b35e-ab42acfe3b3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297597816 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1297597816
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2818527445
Short name T552
Test name
Test status
Simulation time 948775055 ps
CPU time 4.1 seconds
Started May 21 12:41:07 PM PDT 24
Finished May 21 12:41:19 PM PDT 24
Peak memory 200032 kb
Host smart-66ea2ff5-a764-4692-bd8b-13d65aca15ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818527445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2818527445
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2058949337
Short name T817
Test name
Test status
Simulation time 6842336772 ps
CPU time 10.05 seconds
Started May 21 12:41:06 PM PDT 24
Finished May 21 12:41:23 PM PDT 24
Peak memory 198160 kb
Host smart-dc64a7f8-563b-4a7e-ad74-a27a4c18abf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058949337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2058949337
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2209994869
Short name T612
Test name
Test status
Simulation time 10480527 ps
CPU time 0.53 seconds
Started May 21 12:41:15 PM PDT 24
Finished May 21 12:41:21 PM PDT 24
Peak memory 195784 kb
Host smart-43fabfd1-4e39-49f4-832a-bd7a0b44e3aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209994869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2209994869
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1587159788
Short name T876
Test name
Test status
Simulation time 69015638670 ps
CPU time 101.28 seconds
Started May 21 12:41:07 PM PDT 24
Finished May 21 12:42:55 PM PDT 24
Peak memory 200496 kb
Host smart-52ced099-9fdc-448d-a7f6-50009b5a5d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587159788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1587159788
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.481062150
Short name T1091
Test name
Test status
Simulation time 124341750139 ps
CPU time 69.22 seconds
Started May 21 12:41:14 PM PDT 24
Finished May 21 12:42:29 PM PDT 24
Peak memory 200268 kb
Host smart-e552260e-cc79-4ceb-8ae0-075939d7c0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481062150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.481062150
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2036376351
Short name T334
Test name
Test status
Simulation time 23761718424 ps
CPU time 17.7 seconds
Started May 21 12:41:07 PM PDT 24
Finished May 21 12:41:32 PM PDT 24
Peak memory 200420 kb
Host smart-a320abd3-f241-4621-ab2a-23e7c02d4859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036376351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2036376351
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1168816815
Short name T716
Test name
Test status
Simulation time 21969614661 ps
CPU time 9.96 seconds
Started May 21 12:41:07 PM PDT 24
Finished May 21 12:41:24 PM PDT 24
Peak memory 198160 kb
Host smart-a8fd7830-5823-4ef0-bf91-c5e47c091c0f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168816815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1168816815
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2722948330
Short name T1106
Test name
Test status
Simulation time 91742455567 ps
CPU time 259.48 seconds
Started May 21 12:41:15 PM PDT 24
Finished May 21 12:45:39 PM PDT 24
Peak memory 200420 kb
Host smart-7f5c5185-06f0-4de5-9cef-bc457de5fcf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722948330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2722948330
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1276442119
Short name T574
Test name
Test status
Simulation time 1187845311 ps
CPU time 0.98 seconds
Started May 21 12:41:11 PM PDT 24
Finished May 21 12:41:18 PM PDT 24
Peak memory 195872 kb
Host smart-d80a4410-2886-4919-97e1-c714dbf90d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276442119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1276442119
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1451414563
Short name T513
Test name
Test status
Simulation time 136397910915 ps
CPU time 283.05 seconds
Started May 21 12:41:06 PM PDT 24
Finished May 21 12:45:56 PM PDT 24
Peak memory 200176 kb
Host smart-cac25687-a6ab-45a2-9e49-7c1ff57c337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451414563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1451414563
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3767655048
Short name T504
Test name
Test status
Simulation time 5505358104 ps
CPU time 102.28 seconds
Started May 21 12:41:15 PM PDT 24
Finished May 21 12:43:02 PM PDT 24
Peak memory 200468 kb
Host smart-bdbcbdeb-153b-4e83-86d0-95323c464029
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3767655048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3767655048
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2507162590
Short name T481
Test name
Test status
Simulation time 2429762933 ps
CPU time 3.7 seconds
Started May 21 12:41:09 PM PDT 24
Finished May 21 12:41:20 PM PDT 24
Peak memory 199076 kb
Host smart-f1b9f2e2-a411-4a83-8029-05cdf01ada1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2507162590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2507162590
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2276001692
Short name T461
Test name
Test status
Simulation time 18230147250 ps
CPU time 16.71 seconds
Started May 21 12:41:08 PM PDT 24
Finished May 21 12:41:32 PM PDT 24
Peak memory 198996 kb
Host smart-2065d89f-ee3d-4c10-a450-be3abb7098a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276001692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2276001692
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3084974139
Short name T629
Test name
Test status
Simulation time 720060795 ps
CPU time 1 seconds
Started May 21 12:41:14 PM PDT 24
Finished May 21 12:41:21 PM PDT 24
Peak memory 195808 kb
Host smart-205f20d7-9115-4293-950b-e456a5db6521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084974139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3084974139
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.4191094712
Short name T549
Test name
Test status
Simulation time 316908448 ps
CPU time 1.2 seconds
Started May 21 12:41:06 PM PDT 24
Finished May 21 12:41:15 PM PDT 24
Peak memory 198820 kb
Host smart-1fe876ee-7f9b-4b78-85ae-5f5290a67b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191094712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.4191094712
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2540886769
Short name T1006
Test name
Test status
Simulation time 132892542689 ps
CPU time 195.9 seconds
Started May 21 12:41:11 PM PDT 24
Finished May 21 12:44:34 PM PDT 24
Peak memory 200484 kb
Host smart-4e26e762-6360-417a-981d-ba42e7c9a722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540886769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2540886769
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2197733313
Short name T61
Test name
Test status
Simulation time 35477120970 ps
CPU time 470.9 seconds
Started May 21 12:41:12 PM PDT 24
Finished May 21 12:49:09 PM PDT 24
Peak memory 216900 kb
Host smart-10b083e6-6a6f-4b0f-891c-34d4ca1612a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197733313 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2197733313
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3641571179
Short name T406
Test name
Test status
Simulation time 2767381363 ps
CPU time 2.62 seconds
Started May 21 12:41:06 PM PDT 24
Finished May 21 12:41:15 PM PDT 24
Peak memory 199248 kb
Host smart-c9d40420-5168-48da-b891-14e0bb970455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641571179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3641571179
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2620871711
Short name T1016
Test name
Test status
Simulation time 92972589374 ps
CPU time 14.81 seconds
Started May 21 12:41:15 PM PDT 24
Finished May 21 12:41:35 PM PDT 24
Peak memory 200464 kb
Host smart-b267d17a-fd3b-4690-9223-282063821ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620871711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2620871711
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2011921929
Short name T797
Test name
Test status
Simulation time 14055003 ps
CPU time 0.55 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:39:23 PM PDT 24
Peak memory 195900 kb
Host smart-8b008fef-2a33-444c-a283-5624010895b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011921929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2011921929
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3860939898
Short name T995
Test name
Test status
Simulation time 82729483048 ps
CPU time 25.78 seconds
Started May 21 12:39:14 PM PDT 24
Finished May 21 12:39:51 PM PDT 24
Peak memory 200456 kb
Host smart-204ed0d1-8713-4193-a10d-b0c06d171b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860939898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3860939898
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.660145858
Short name T975
Test name
Test status
Simulation time 190416536586 ps
CPU time 83.71 seconds
Started May 21 12:39:40 PM PDT 24
Finished May 21 12:41:13 PM PDT 24
Peak memory 200416 kb
Host smart-8026f9ca-d4bd-489d-af1b-11c87a1d0580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660145858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.660145858
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3438244658
Short name T1057
Test name
Test status
Simulation time 46491566807 ps
CPU time 77.52 seconds
Started May 21 12:39:31 PM PDT 24
Finished May 21 12:40:58 PM PDT 24
Peak memory 200448 kb
Host smart-decdbbbe-7ee8-4e9d-84b1-e4c495ccaa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438244658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3438244658
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.806256691
Short name T827
Test name
Test status
Simulation time 76420825932 ps
CPU time 140.55 seconds
Started May 21 12:39:33 PM PDT 24
Finished May 21 12:42:03 PM PDT 24
Peak memory 200216 kb
Host smart-60b48a58-ecba-46d5-9104-9b3814805eaf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806256691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.806256691
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.613261190
Short name T749
Test name
Test status
Simulation time 131438950340 ps
CPU time 697.25 seconds
Started May 21 12:39:16 PM PDT 24
Finished May 21 12:51:03 PM PDT 24
Peak memory 200316 kb
Host smart-5671298e-b661-4f8f-a524-dfeb02bb70c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=613261190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.613261190
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3802986305
Short name T338
Test name
Test status
Simulation time 1780572037 ps
CPU time 3.28 seconds
Started May 21 12:39:24 PM PDT 24
Finished May 21 12:39:37 PM PDT 24
Peak memory 196424 kb
Host smart-082a4d5e-791e-4088-ba25-97dd2950fb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802986305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3802986305
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2104380839
Short name T871
Test name
Test status
Simulation time 106123072254 ps
CPU time 42.36 seconds
Started May 21 12:39:19 PM PDT 24
Finished May 21 12:40:12 PM PDT 24
Peak memory 200732 kb
Host smart-a92ea72c-19f5-4fac-b958-eed8dbeff9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104380839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2104380839
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3424066727
Short name T840
Test name
Test status
Simulation time 26243804309 ps
CPU time 278.95 seconds
Started May 21 12:39:19 PM PDT 24
Finished May 21 12:44:08 PM PDT 24
Peak memory 200448 kb
Host smart-4b5db684-1b6c-4572-b30a-ff60798fa854
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3424066727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3424066727
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2921946099
Short name T614
Test name
Test status
Simulation time 3999780146 ps
CPU time 4.62 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:39:27 PM PDT 24
Peak memory 198400 kb
Host smart-c8a893b4-31c6-450b-917b-de2c67fdc42f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2921946099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2921946099
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1108020003
Short name T258
Test name
Test status
Simulation time 378338807517 ps
CPU time 41.59 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:40:04 PM PDT 24
Peak memory 200516 kb
Host smart-44935e91-fb89-4077-a8f7-e544a45eaac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108020003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1108020003
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1122373530
Short name T285
Test name
Test status
Simulation time 2679568747 ps
CPU time 2.91 seconds
Started May 21 12:39:28 PM PDT 24
Finished May 21 12:39:40 PM PDT 24
Peak memory 196244 kb
Host smart-9cf64225-4305-4550-9bbb-3241e5c8d5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122373530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1122373530
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.413466404
Short name T31
Test name
Test status
Simulation time 207409190 ps
CPU time 0.8 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:39:46 PM PDT 24
Peak memory 219008 kb
Host smart-8e276ff1-37b0-4678-9a7a-6823ec096488
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413466404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.413466404
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2080431411
Short name T907
Test name
Test status
Simulation time 643614142 ps
CPU time 1.64 seconds
Started May 21 12:39:27 PM PDT 24
Finished May 21 12:39:38 PM PDT 24
Peak memory 198592 kb
Host smart-245f61fc-5aaf-4e06-9e34-76cf022f2b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080431411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2080431411
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2982337874
Short name T1061
Test name
Test status
Simulation time 226838485097 ps
CPU time 1096.92 seconds
Started May 21 12:39:32 PM PDT 24
Finished May 21 12:57:58 PM PDT 24
Peak memory 200452 kb
Host smart-b37e61d0-26ef-40e5-bb3d-dc27bf62cf11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982337874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2982337874
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3425604440
Short name T565
Test name
Test status
Simulation time 167313099442 ps
CPU time 1640.68 seconds
Started May 21 12:39:37 PM PDT 24
Finished May 21 01:07:07 PM PDT 24
Peak memory 229652 kb
Host smart-295520a5-0220-45c0-ab32-fd7bacac094b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425604440 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3425604440
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.4152797841
Short name T489
Test name
Test status
Simulation time 2071260301 ps
CPU time 2.2 seconds
Started May 21 12:39:14 PM PDT 24
Finished May 21 12:39:27 PM PDT 24
Peak memory 199520 kb
Host smart-9fde6fd5-0a8a-4000-ae08-746d323f73a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152797841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.4152797841
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.183919099
Short name T665
Test name
Test status
Simulation time 101962610910 ps
CPU time 89.25 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:41:15 PM PDT 24
Peak memory 200476 kb
Host smart-a04da120-40e8-40db-9d55-fd16e7c76001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183919099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.183919099
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.117039973
Short name T413
Test name
Test status
Simulation time 15008494 ps
CPU time 0.56 seconds
Started May 21 12:41:13 PM PDT 24
Finished May 21 12:41:19 PM PDT 24
Peak memory 195768 kb
Host smart-b9d53f17-7094-4540-bb35-6baa9219bb6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117039973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.117039973
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.835378870
Short name T694
Test name
Test status
Simulation time 147371985273 ps
CPU time 134.38 seconds
Started May 21 12:41:11 PM PDT 24
Finished May 21 12:43:32 PM PDT 24
Peak memory 200444 kb
Host smart-62889a82-a35e-4682-94ed-d8992d3d7b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835378870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.835378870
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1766239707
Short name T218
Test name
Test status
Simulation time 39488567607 ps
CPU time 45.5 seconds
Started May 21 12:41:14 PM PDT 24
Finished May 21 12:42:05 PM PDT 24
Peak memory 200476 kb
Host smart-2c5e9201-653a-4194-a05c-693b27abe5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766239707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1766239707
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.93161196
Short name T906
Test name
Test status
Simulation time 49069164574 ps
CPU time 11.25 seconds
Started May 21 12:41:11 PM PDT 24
Finished May 21 12:41:29 PM PDT 24
Peak memory 200444 kb
Host smart-9790c9a4-bdad-4de3-88c0-4eb5c08ab246
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93161196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.93161196
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.89499106
Short name T476
Test name
Test status
Simulation time 58490719243 ps
CPU time 200 seconds
Started May 21 12:41:12 PM PDT 24
Finished May 21 12:44:39 PM PDT 24
Peak memory 200456 kb
Host smart-5fe35ef5-2fd0-471a-af00-37cf3f1aa0aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89499106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.89499106
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2983264191
Short name T743
Test name
Test status
Simulation time 3302587124 ps
CPU time 7.63 seconds
Started May 21 12:41:10 PM PDT 24
Finished May 21 12:41:25 PM PDT 24
Peak memory 199380 kb
Host smart-315375d2-140b-467f-b32b-d59e4a7a990a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983264191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2983264191
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2389418187
Short name T1078
Test name
Test status
Simulation time 96449141404 ps
CPU time 38.41 seconds
Started May 21 12:41:13 PM PDT 24
Finished May 21 12:41:57 PM PDT 24
Peak memory 200700 kb
Host smart-83216fc4-8bab-4be5-b7a2-658ce5470236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389418187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2389418187
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.482721288
Short name T1151
Test name
Test status
Simulation time 13966886224 ps
CPU time 349.42 seconds
Started May 21 12:41:11 PM PDT 24
Finished May 21 12:47:07 PM PDT 24
Peak memory 200364 kb
Host smart-a2001b8e-e5e8-4f8b-995f-6902364bce30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482721288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.482721288
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2391847943
Short name T422
Test name
Test status
Simulation time 6214030854 ps
CPU time 6.76 seconds
Started May 21 12:41:15 PM PDT 24
Finished May 21 12:41:27 PM PDT 24
Peak memory 199680 kb
Host smart-04661367-e2b7-4e2e-8a02-4ad888bfe4e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391847943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2391847943
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.127825258
Short name T44
Test name
Test status
Simulation time 68426152117 ps
CPU time 26.94 seconds
Started May 21 12:41:15 PM PDT 24
Finished May 21 12:41:47 PM PDT 24
Peak memory 200400 kb
Host smart-3e938c04-d9e1-41b6-adc6-db3fded40af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127825258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.127825258
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3405176148
Short name T1017
Test name
Test status
Simulation time 3898411561 ps
CPU time 6.99 seconds
Started May 21 12:41:16 PM PDT 24
Finished May 21 12:41:28 PM PDT 24
Peak memory 196444 kb
Host smart-8b464af2-0f58-418d-bf33-59412a06f14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405176148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3405176148
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1358944197
Short name T943
Test name
Test status
Simulation time 5722063493 ps
CPU time 16.75 seconds
Started May 21 12:41:12 PM PDT 24
Finished May 21 12:41:35 PM PDT 24
Peak memory 200188 kb
Host smart-e3ef8b84-b8a4-4e22-b48b-eaf5b8bac4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358944197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1358944197
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3051295251
Short name T558
Test name
Test status
Simulation time 863873369 ps
CPU time 2.38 seconds
Started May 21 12:41:15 PM PDT 24
Finished May 21 12:41:22 PM PDT 24
Peak memory 199728 kb
Host smart-41f1b6ce-ff18-4efd-a1c7-ebd792edbc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051295251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3051295251
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1053107624
Short name T702
Test name
Test status
Simulation time 43413696300 ps
CPU time 78.51 seconds
Started May 21 12:41:12 PM PDT 24
Finished May 21 12:42:37 PM PDT 24
Peak memory 200516 kb
Host smart-fd135d8a-7eec-4583-927e-8d9d1ad98524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053107624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1053107624
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.663293864
Short name T928
Test name
Test status
Simulation time 13722222 ps
CPU time 0.57 seconds
Started May 21 12:41:20 PM PDT 24
Finished May 21 12:41:24 PM PDT 24
Peak memory 196092 kb
Host smart-f67b0cc9-8bb7-4fee-9330-3e2ef5735987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663293864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.663293864
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1201665566
Short name T1030
Test name
Test status
Simulation time 105618788529 ps
CPU time 70.19 seconds
Started May 21 12:41:22 PM PDT 24
Finished May 21 12:42:35 PM PDT 24
Peak memory 200444 kb
Host smart-c9aac3e8-addf-49c1-92da-5a168f8b0e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201665566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1201665566
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2173353660
Short name T857
Test name
Test status
Simulation time 140859749965 ps
CPU time 49.28 seconds
Started May 21 12:41:20 PM PDT 24
Finished May 21 12:42:13 PM PDT 24
Peak memory 200464 kb
Host smart-cc874abb-cb1a-4b57-aaa4-56d8807febc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173353660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2173353660
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2099617272
Short name T751
Test name
Test status
Simulation time 51198662418 ps
CPU time 25.54 seconds
Started May 21 12:41:19 PM PDT 24
Finished May 21 12:41:49 PM PDT 24
Peak memory 200476 kb
Host smart-14b78149-08b5-4cbe-beed-aab64f9e8546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099617272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2099617272
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.4220706766
Short name T289
Test name
Test status
Simulation time 26599469490 ps
CPU time 13.18 seconds
Started May 21 12:41:19 PM PDT 24
Finished May 21 12:41:36 PM PDT 24
Peak memory 200404 kb
Host smart-1b81351d-bf1d-460b-a1ad-1f0d7d4c5a17
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220706766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.4220706766
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.416067842
Short name T764
Test name
Test status
Simulation time 58638071412 ps
CPU time 82.23 seconds
Started May 21 12:41:20 PM PDT 24
Finished May 21 12:42:46 PM PDT 24
Peak memory 200432 kb
Host smart-eb931d1d-bef1-4f5e-aec7-df26ca96e5d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=416067842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.416067842
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3869125399
Short name T407
Test name
Test status
Simulation time 9977723354 ps
CPU time 17.98 seconds
Started May 21 12:41:22 PM PDT 24
Finished May 21 12:41:43 PM PDT 24
Peak memory 200336 kb
Host smart-7c74ec79-3323-4f47-8179-4826257e7431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869125399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3869125399
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.793249104
Short name T862
Test name
Test status
Simulation time 140135962785 ps
CPU time 135.5 seconds
Started May 21 12:41:19 PM PDT 24
Finished May 21 12:43:38 PM PDT 24
Peak memory 216212 kb
Host smart-80683616-8ad7-44dc-94bb-ed1b56fe6b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793249104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.793249104
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3346361924
Short name T604
Test name
Test status
Simulation time 9944562422 ps
CPU time 399.13 seconds
Started May 21 12:41:18 PM PDT 24
Finished May 21 12:48:01 PM PDT 24
Peak memory 200348 kb
Host smart-a413673d-f652-400a-bfda-99a89a4db98e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3346361924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3346361924
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.912475072
Short name T805
Test name
Test status
Simulation time 4729153468 ps
CPU time 11.66 seconds
Started May 21 12:41:20 PM PDT 24
Finished May 21 12:41:35 PM PDT 24
Peak memory 198988 kb
Host smart-8c1f2a1b-9ca3-4cff-b494-086b72f507e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912475072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.912475072
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.546718014
Short name T23
Test name
Test status
Simulation time 32969150205 ps
CPU time 18.02 seconds
Started May 21 12:41:21 PM PDT 24
Finished May 21 12:41:42 PM PDT 24
Peak memory 200416 kb
Host smart-fa64b62b-47fb-42b5-94bf-f4291b38e03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546718014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.546718014
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3926738616
Short name T883
Test name
Test status
Simulation time 2705355223 ps
CPU time 1.68 seconds
Started May 21 12:41:20 PM PDT 24
Finished May 21 12:41:25 PM PDT 24
Peak memory 196916 kb
Host smart-f9f0ff57-936e-4646-8e1b-88f5698c17ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926738616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3926738616
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2502381246
Short name T947
Test name
Test status
Simulation time 521979838 ps
CPU time 1.44 seconds
Started May 21 12:41:15 PM PDT 24
Finished May 21 12:41:21 PM PDT 24
Peak memory 199132 kb
Host smart-637dab4f-44f6-4f9f-bdf0-26c20347ae8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502381246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2502381246
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.499540869
Short name T215
Test name
Test status
Simulation time 314756366024 ps
CPU time 432.77 seconds
Started May 21 12:41:18 PM PDT 24
Finished May 21 12:48:35 PM PDT 24
Peak memory 208932 kb
Host smart-d72129f9-6960-4cdc-b749-6c4551caa091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499540869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.499540869
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3914962106
Short name T66
Test name
Test status
Simulation time 75600866811 ps
CPU time 483.37 seconds
Started May 21 12:41:22 PM PDT 24
Finished May 21 12:49:28 PM PDT 24
Peak memory 217396 kb
Host smart-a45b1f77-30a3-417f-b407-7a5c37a154e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914962106 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3914962106
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.607471664
Short name T1127
Test name
Test status
Simulation time 312671273 ps
CPU time 1.23 seconds
Started May 21 12:41:19 PM PDT 24
Finished May 21 12:41:24 PM PDT 24
Peak memory 197928 kb
Host smart-fb4f3090-e10c-4e05-a28d-05923abaf032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607471664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.607471664
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1322186028
Short name T326
Test name
Test status
Simulation time 35941098741 ps
CPU time 56.09 seconds
Started May 21 12:42:20 PM PDT 24
Finished May 21 12:43:19 PM PDT 24
Peak memory 200496 kb
Host smart-f99abc7c-70c2-4639-a6f0-ce2ccaf07e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322186028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1322186028
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2592183868
Short name T336
Test name
Test status
Simulation time 11938850 ps
CPU time 0.56 seconds
Started May 21 12:41:26 PM PDT 24
Finished May 21 12:41:31 PM PDT 24
Peak memory 195876 kb
Host smart-6de92882-1d7c-496c-bd57-8c44dfae7a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592183868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2592183868
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.456624657
Short name T507
Test name
Test status
Simulation time 165162528512 ps
CPU time 246.63 seconds
Started May 21 12:41:19 PM PDT 24
Finished May 21 12:45:29 PM PDT 24
Peak memory 200448 kb
Host smart-11f4b59b-ebda-4abb-8cb1-e1a6497b5aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456624657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.456624657
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.2943049915
Short name T939
Test name
Test status
Simulation time 192783073333 ps
CPU time 87.23 seconds
Started May 21 12:41:18 PM PDT 24
Finished May 21 12:42:50 PM PDT 24
Peak memory 200300 kb
Host smart-4915ef06-18f4-4a41-9c01-03878078c51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943049915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2943049915
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_intr.15612694
Short name T541
Test name
Test status
Simulation time 50179179247 ps
CPU time 20.22 seconds
Started May 21 12:41:25 PM PDT 24
Finished May 21 12:41:51 PM PDT 24
Peak memory 200452 kb
Host smart-6e585d11-a87e-475d-a365-7e6ebef72c9d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15612694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.15612694
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.4155025923
Short name T1
Test name
Test status
Simulation time 95524721912 ps
CPU time 223.72 seconds
Started May 21 12:41:23 PM PDT 24
Finished May 21 12:45:10 PM PDT 24
Peak memory 200424 kb
Host smart-8db5837e-6c5c-4a7e-afe6-1f5e1c190417
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4155025923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4155025923
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3868793142
Short name T1162
Test name
Test status
Simulation time 11758659734 ps
CPU time 11.92 seconds
Started May 21 12:41:25 PM PDT 24
Finished May 21 12:41:42 PM PDT 24
Peak memory 200336 kb
Host smart-74f2dd14-165c-40f5-bcf5-9e3d5a80acaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868793142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3868793142
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2790579115
Short name T17
Test name
Test status
Simulation time 11494526976 ps
CPU time 22.28 seconds
Started May 21 12:41:27 PM PDT 24
Finished May 21 12:41:54 PM PDT 24
Peak memory 199572 kb
Host smart-fcaac541-43f9-4633-a33f-4bf75ab22fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790579115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2790579115
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1411431471
Short name T409
Test name
Test status
Simulation time 12142068811 ps
CPU time 747.17 seconds
Started May 21 12:41:27 PM PDT 24
Finished May 21 12:54:00 PM PDT 24
Peak memory 200388 kb
Host smart-dad1825a-53a4-4ba6-8f99-f13c4cd36300
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411431471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1411431471
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3890580240
Short name T450
Test name
Test status
Simulation time 6047984057 ps
CPU time 14.57 seconds
Started May 21 12:41:24 PM PDT 24
Finished May 21 12:41:43 PM PDT 24
Peak memory 198600 kb
Host smart-e1c9d7d5-c527-40f5-98cb-dadc20de2249
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3890580240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3890580240
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3733859734
Short name T581
Test name
Test status
Simulation time 246620466714 ps
CPU time 88.99 seconds
Started May 21 12:41:29 PM PDT 24
Finished May 21 12:43:04 PM PDT 24
Peak memory 200420 kb
Host smart-c503bc9e-aace-4848-8caf-b39057e34f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733859734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3733859734
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.16277711
Short name T909
Test name
Test status
Simulation time 30407562672 ps
CPU time 13.59 seconds
Started May 21 12:41:26 PM PDT 24
Finished May 21 12:41:44 PM PDT 24
Peak memory 196436 kb
Host smart-486f0cac-02ac-4157-9737-dcace67f654c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16277711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.16277711
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3004864059
Short name T43
Test name
Test status
Simulation time 5786050794 ps
CPU time 6.21 seconds
Started May 21 12:41:19 PM PDT 24
Finished May 21 12:41:29 PM PDT 24
Peak memory 199736 kb
Host smart-ed164702-1038-4df9-9ba5-ec389d7613f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004864059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3004864059
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.4218570418
Short name T603
Test name
Test status
Simulation time 238253760875 ps
CPU time 579.83 seconds
Started May 21 12:41:29 PM PDT 24
Finished May 21 12:51:14 PM PDT 24
Peak memory 216960 kb
Host smart-479295e9-decf-4101-a187-b9d433a29cee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218570418 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.4218570418
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3661675414
Short name T639
Test name
Test status
Simulation time 6598093445 ps
CPU time 21.35 seconds
Started May 21 12:41:25 PM PDT 24
Finished May 21 12:41:51 PM PDT 24
Peak memory 199916 kb
Host smart-cd50e717-b54f-4037-a0fd-bf077f6e82c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661675414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3661675414
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.340701787
Short name T544
Test name
Test status
Simulation time 163321718790 ps
CPU time 72.74 seconds
Started May 21 12:41:22 PM PDT 24
Finished May 21 12:42:38 PM PDT 24
Peak memory 200444 kb
Host smart-c8bf11d2-52d8-4fe6-84f5-c3832764ddd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340701787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.340701787
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3460154345
Short name T1135
Test name
Test status
Simulation time 42083494 ps
CPU time 0.51 seconds
Started May 21 12:41:28 PM PDT 24
Finished May 21 12:41:34 PM PDT 24
Peak memory 194860 kb
Host smart-b6e4d8b6-601f-474b-bc90-dafc3a0b76b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460154345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3460154345
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2593568545
Short name T758
Test name
Test status
Simulation time 46670894895 ps
CPU time 22.45 seconds
Started May 21 12:41:25 PM PDT 24
Finished May 21 12:41:53 PM PDT 24
Peak memory 200472 kb
Host smart-e80d4d50-5c60-4a54-a727-32ab79a3cd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593568545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2593568545
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2796359364
Short name T117
Test name
Test status
Simulation time 186024532557 ps
CPU time 46.74 seconds
Started May 21 12:41:24 PM PDT 24
Finished May 21 12:42:14 PM PDT 24
Peak memory 200484 kb
Host smart-21aa9b3b-5d63-4c4c-93e7-cd525a547b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796359364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2796359364
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.196771408
Short name T211
Test name
Test status
Simulation time 22561625431 ps
CPU time 21.77 seconds
Started May 21 12:41:26 PM PDT 24
Finished May 21 12:41:53 PM PDT 24
Peak memory 200336 kb
Host smart-2434a1a1-35f2-478b-8738-d231d07e1ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196771408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.196771408
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2046842735
Short name T809
Test name
Test status
Simulation time 24394387330 ps
CPU time 37.88 seconds
Started May 21 12:41:25 PM PDT 24
Finished May 21 12:42:07 PM PDT 24
Peak memory 200016 kb
Host smart-765b3d7c-324a-403f-8c3c-ae3268232a01
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046842735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2046842735
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.2185872907
Short name T979
Test name
Test status
Simulation time 259265260810 ps
CPU time 112 seconds
Started May 21 12:41:28 PM PDT 24
Finished May 21 12:43:25 PM PDT 24
Peak memory 200444 kb
Host smart-df9c4782-731f-49db-94b5-5a92b3283570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2185872907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2185872907
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2658898861
Short name T500
Test name
Test status
Simulation time 1732886489 ps
CPU time 2.33 seconds
Started May 21 12:41:29 PM PDT 24
Finished May 21 12:41:37 PM PDT 24
Peak memory 197836 kb
Host smart-ebe7bc90-046b-44f1-9f05-7339bb2c62aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658898861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2658898861
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.992472426
Short name T917
Test name
Test status
Simulation time 108700934119 ps
CPU time 129.88 seconds
Started May 21 12:41:27 PM PDT 24
Finished May 21 12:43:42 PM PDT 24
Peak memory 199920 kb
Host smart-67570b2d-33e7-4cb3-942d-ceed5a5a2c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992472426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.992472426
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.753888340
Short name T773
Test name
Test status
Simulation time 19334109863 ps
CPU time 1043.91 seconds
Started May 21 12:41:25 PM PDT 24
Finished May 21 12:58:54 PM PDT 24
Peak memory 200480 kb
Host smart-01938f09-8ad3-4557-9a81-c48d52890d5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=753888340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.753888340
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.744096747
Short name T465
Test name
Test status
Simulation time 5211174445 ps
CPU time 22.04 seconds
Started May 21 12:41:26 PM PDT 24
Finished May 21 12:41:53 PM PDT 24
Peak memory 199360 kb
Host smart-75625784-d2c8-4af8-a698-0321fca65542
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744096747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.744096747
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3586373927
Short name T1072
Test name
Test status
Simulation time 73860078677 ps
CPU time 27.49 seconds
Started May 21 12:41:23 PM PDT 24
Finished May 21 12:41:54 PM PDT 24
Peak memory 200420 kb
Host smart-a5f162d3-c5f5-4bd3-83c4-6efd70c8293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586373927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3586373927
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3185569422
Short name T1182
Test name
Test status
Simulation time 1271569975 ps
CPU time 2.69 seconds
Started May 21 12:41:29 PM PDT 24
Finished May 21 12:41:37 PM PDT 24
Peak memory 196100 kb
Host smart-1d957af2-1a02-4b43-b682-d90d69f72988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185569422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3185569422
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3708866327
Short name T344
Test name
Test status
Simulation time 308827901 ps
CPU time 1.35 seconds
Started May 21 12:41:27 PM PDT 24
Finished May 21 12:41:33 PM PDT 24
Peak memory 200244 kb
Host smart-831640f0-0e18-4048-a93d-64a9a24c0f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708866327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3708866327
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3191038868
Short name T206
Test name
Test status
Simulation time 534523439010 ps
CPU time 1248.39 seconds
Started May 21 12:41:25 PM PDT 24
Finished May 21 01:02:19 PM PDT 24
Peak memory 230236 kb
Host smart-8eb4f168-5de9-4f8c-bd52-7af607d44882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191038868 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3191038868
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1942791764
Short name T288
Test name
Test status
Simulation time 2421576923 ps
CPU time 2.25 seconds
Started May 21 12:41:27 PM PDT 24
Finished May 21 12:41:34 PM PDT 24
Peak memory 200420 kb
Host smart-b91fd63c-db69-4619-b9e5-b3cdd2d9f035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942791764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1942791764
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.99110398
Short name T1081
Test name
Test status
Simulation time 65953335111 ps
CPU time 106.04 seconds
Started May 21 12:41:25 PM PDT 24
Finished May 21 12:43:15 PM PDT 24
Peak memory 200484 kb
Host smart-97be6384-1fd4-4bc5-b82e-3ce312c40902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99110398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.99110398
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1875201253
Short name T369
Test name
Test status
Simulation time 12729334 ps
CPU time 0.56 seconds
Started May 21 12:41:30 PM PDT 24
Finished May 21 12:41:36 PM PDT 24
Peak memory 196096 kb
Host smart-85115f37-f050-4bcf-b359-6b44281fb647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875201253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1875201253
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1616666850
Short name T619
Test name
Test status
Simulation time 30622264732 ps
CPU time 50.88 seconds
Started May 21 12:41:25 PM PDT 24
Finished May 21 12:42:21 PM PDT 24
Peak memory 200560 kb
Host smart-b93994d5-ebdc-4518-992f-df7c0b5dff55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616666850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1616666850
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3285987136
Short name T802
Test name
Test status
Simulation time 75574336665 ps
CPU time 32.3 seconds
Started May 21 12:41:27 PM PDT 24
Finished May 21 12:42:05 PM PDT 24
Peak memory 200364 kb
Host smart-90de524d-d32b-4cd8-8b0a-a790de088c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285987136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3285987136
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2303404377
Short name T1031
Test name
Test status
Simulation time 17209969025 ps
CPU time 7.25 seconds
Started May 21 12:41:24 PM PDT 24
Finished May 21 12:41:36 PM PDT 24
Peak memory 200508 kb
Host smart-1ea39ba5-7ded-4045-b2ed-9b4ea5860fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303404377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2303404377
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1822289011
Short name T712
Test name
Test status
Simulation time 33289771748 ps
CPU time 14.81 seconds
Started May 21 12:41:31 PM PDT 24
Finished May 21 12:41:51 PM PDT 24
Peak memory 200452 kb
Host smart-1dba60d7-2508-4430-b7e9-cf1f2c0a3c2c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822289011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1822289011
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3426156157
Short name T365
Test name
Test status
Simulation time 251731375198 ps
CPU time 234.28 seconds
Started May 21 12:41:30 PM PDT 24
Finished May 21 12:45:30 PM PDT 24
Peak memory 200408 kb
Host smart-0b316a02-ee4f-42ea-b13f-94e5455dca00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426156157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3426156157
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3590506647
Short name T1152
Test name
Test status
Simulation time 6748858713 ps
CPU time 3.77 seconds
Started May 21 12:41:31 PM PDT 24
Finished May 21 12:41:40 PM PDT 24
Peak memory 200256 kb
Host smart-43d10625-ae9e-4624-85f8-33ebc20fcca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590506647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3590506647
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3810236688
Short name T989
Test name
Test status
Simulation time 41879160354 ps
CPU time 34.22 seconds
Started May 21 12:41:32 PM PDT 24
Finished May 21 12:42:11 PM PDT 24
Peak memory 198860 kb
Host smart-f09c86cd-5b73-40be-8f59-ac10ab7c8cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810236688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3810236688
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3592381175
Short name T927
Test name
Test status
Simulation time 8919653142 ps
CPU time 518.77 seconds
Started May 21 12:41:32 PM PDT 24
Finished May 21 12:50:16 PM PDT 24
Peak memory 200476 kb
Host smart-108313fe-e029-4620-bf70-74d5a1351602
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3592381175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3592381175
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1935392576
Short name T405
Test name
Test status
Simulation time 7133558383 ps
CPU time 11.82 seconds
Started May 21 12:41:33 PM PDT 24
Finished May 21 12:41:50 PM PDT 24
Peak memory 199764 kb
Host smart-f157e168-ccf3-4cd2-99bc-2881cb38e994
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1935392576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1935392576
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2724636620
Short name T1171
Test name
Test status
Simulation time 22380340893 ps
CPU time 42.2 seconds
Started May 21 12:41:34 PM PDT 24
Finished May 21 12:42:20 PM PDT 24
Peak memory 200452 kb
Host smart-65f76a22-5208-497d-8bac-03ac9aed3859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724636620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2724636620
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1793095
Short name T1104
Test name
Test status
Simulation time 743575494 ps
CPU time 0.96 seconds
Started May 21 12:41:32 PM PDT 24
Finished May 21 12:41:38 PM PDT 24
Peak memory 195888 kb
Host smart-17d46431-709f-4cf1-b34e-38c16b598a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1793095
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.757195210
Short name T1183
Test name
Test status
Simulation time 481703475 ps
CPU time 2.11 seconds
Started May 21 12:41:28 PM PDT 24
Finished May 21 12:41:35 PM PDT 24
Peak memory 200388 kb
Host smart-4d1cdf11-731f-432c-8dde-1c4e97e7e0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757195210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.757195210
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.12412226
Short name T483
Test name
Test status
Simulation time 85175176024 ps
CPU time 38.41 seconds
Started May 21 12:41:31 PM PDT 24
Finished May 21 12:42:15 PM PDT 24
Peak memory 200360 kb
Host smart-18597663-0440-41bd-ba64-a21063ad6ee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12412226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.12412226
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3869880817
Short name T62
Test name
Test status
Simulation time 63343198285 ps
CPU time 610.99 seconds
Started May 21 12:41:31 PM PDT 24
Finished May 21 12:51:47 PM PDT 24
Peak memory 216860 kb
Host smart-e115061b-d430-41fe-9470-0ce66adde24e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869880817 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3869880817
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.309400054
Short name T274
Test name
Test status
Simulation time 7105898978 ps
CPU time 5.65 seconds
Started May 21 12:41:30 PM PDT 24
Finished May 21 12:41:41 PM PDT 24
Peak memory 200412 kb
Host smart-d86f7349-c8a6-4f7e-89b6-8c2383302451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309400054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.309400054
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3493207958
Short name T546
Test name
Test status
Simulation time 115159846656 ps
CPU time 14.29 seconds
Started May 21 12:41:29 PM PDT 24
Finished May 21 12:41:48 PM PDT 24
Peak memory 197376 kb
Host smart-e922ce38-d71e-4c87-a49c-a1beeed62ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493207958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3493207958
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.646294993
Short name T787
Test name
Test status
Simulation time 14098308 ps
CPU time 0.55 seconds
Started May 21 12:41:40 PM PDT 24
Finished May 21 12:41:43 PM PDT 24
Peak memory 195320 kb
Host smart-d9fc65e5-9f69-4258-a5c0-4c34472b8632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646294993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.646294993
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2681257602
Short name T452
Test name
Test status
Simulation time 30864725443 ps
CPU time 13.21 seconds
Started May 21 12:41:33 PM PDT 24
Finished May 21 12:41:51 PM PDT 24
Peak memory 200516 kb
Host smart-86a42a36-6265-4bb2-b113-77ccc1e5d91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681257602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2681257602
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.33504187
Short name T897
Test name
Test status
Simulation time 67998959876 ps
CPU time 58.96 seconds
Started May 21 12:41:33 PM PDT 24
Finished May 21 12:42:37 PM PDT 24
Peak memory 200680 kb
Host smart-cd35d2ce-454c-4fc1-81a0-29a7357d1317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33504187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.33504187
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.4123362613
Short name T110
Test name
Test status
Simulation time 105264984807 ps
CPU time 85.94 seconds
Started May 21 12:41:32 PM PDT 24
Finished May 21 12:43:03 PM PDT 24
Peak memory 200420 kb
Host smart-925f1772-f5a2-42a5-8c53-8938d4dff453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123362613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.4123362613
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.997321983
Short name T602
Test name
Test status
Simulation time 222555605536 ps
CPU time 102.43 seconds
Started May 21 12:41:33 PM PDT 24
Finished May 21 12:43:20 PM PDT 24
Peak memory 200448 kb
Host smart-5a4f4c6b-d05c-40e1-ab62-696e9d6eb91f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997321983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.997321983
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3942019254
Short name T669
Test name
Test status
Simulation time 86392583229 ps
CPU time 500.46 seconds
Started May 21 12:41:30 PM PDT 24
Finished May 21 12:49:56 PM PDT 24
Peak memory 200508 kb
Host smart-89c4cf21-fa65-4d75-9b93-aa028128e9db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3942019254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3942019254
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1359331504
Short name T347
Test name
Test status
Simulation time 4959954791 ps
CPU time 9.61 seconds
Started May 21 12:41:30 PM PDT 24
Finished May 21 12:41:44 PM PDT 24
Peak memory 196888 kb
Host smart-cccbce8f-169a-4191-ad7c-3f9bfb2caa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359331504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1359331504
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3949290292
Short name T277
Test name
Test status
Simulation time 112692092023 ps
CPU time 133.61 seconds
Started May 21 12:41:33 PM PDT 24
Finished May 21 12:43:51 PM PDT 24
Peak memory 200476 kb
Host smart-15a1f140-5760-4d85-8b19-93c97fa9f750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949290292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3949290292
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1981453463
Short name T47
Test name
Test status
Simulation time 11199460468 ps
CPU time 343.16 seconds
Started May 21 12:41:31 PM PDT 24
Finished May 21 12:47:19 PM PDT 24
Peak memory 200480 kb
Host smart-068551e7-b11f-4a5f-afda-b4c4f717bd81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1981453463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1981453463
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3212254749
Short name T766
Test name
Test status
Simulation time 6501620954 ps
CPU time 16.01 seconds
Started May 21 12:41:33 PM PDT 24
Finished May 21 12:41:54 PM PDT 24
Peak memory 198592 kb
Host smart-7d8346c8-233b-4ae4-9569-4d89863b2cf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3212254749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3212254749
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.891924732
Short name T681
Test name
Test status
Simulation time 153301964007 ps
CPU time 223.05 seconds
Started May 21 12:41:32 PM PDT 24
Finished May 21 12:45:20 PM PDT 24
Peak memory 200488 kb
Host smart-76671ee1-6698-4d40-b48e-2ddeae674736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891924732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.891924732
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3356296106
Short name T1050
Test name
Test status
Simulation time 26727498759 ps
CPU time 13.52 seconds
Started May 21 12:41:31 PM PDT 24
Finished May 21 12:41:50 PM PDT 24
Peak memory 196164 kb
Host smart-cfc734ce-8c08-4966-96ef-07932100306e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356296106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3356296106
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.346928004
Short name T815
Test name
Test status
Simulation time 646576681 ps
CPU time 2.5 seconds
Started May 21 12:41:34 PM PDT 24
Finished May 21 12:41:41 PM PDT 24
Peak memory 200388 kb
Host smart-5e2df003-88d3-448c-94bc-d390f8518000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346928004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.346928004
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2022107768
Short name T98
Test name
Test status
Simulation time 166079065363 ps
CPU time 135.05 seconds
Started May 21 12:41:31 PM PDT 24
Finished May 21 12:43:51 PM PDT 24
Peak memory 200496 kb
Host smart-f7937757-f67a-4c7e-a3ac-a5b1cff0f62e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022107768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2022107768
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.662996154
Short name T1179
Test name
Test status
Simulation time 118728491184 ps
CPU time 564.66 seconds
Started May 21 12:41:30 PM PDT 24
Finished May 21 12:51:00 PM PDT 24
Peak memory 228048 kb
Host smart-fe3da239-5fb9-4e38-a362-ead530e1670b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662996154 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.662996154
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3813388442
Short name T582
Test name
Test status
Simulation time 1296145775 ps
CPU time 3.84 seconds
Started May 21 12:41:30 PM PDT 24
Finished May 21 12:41:39 PM PDT 24
Peak memory 199188 kb
Host smart-1719263d-1b68-4b75-b316-a071909ac5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813388442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3813388442
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3916178091
Short name T454
Test name
Test status
Simulation time 18388561718 ps
CPU time 36.34 seconds
Started May 21 12:41:34 PM PDT 24
Finished May 21 12:42:15 PM PDT 24
Peak memory 200504 kb
Host smart-27317387-da36-4f12-9b36-f809afecb4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916178091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3916178091
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.600419072
Short name T443
Test name
Test status
Simulation time 22935817 ps
CPU time 0.53 seconds
Started May 21 12:41:38 PM PDT 24
Finished May 21 12:41:41 PM PDT 24
Peak memory 195876 kb
Host smart-21b4f4fa-3759-4d4b-a8c6-48467ded453a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600419072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.600419072
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.567940361
Short name T725
Test name
Test status
Simulation time 76162008294 ps
CPU time 31.37 seconds
Started May 21 12:41:37 PM PDT 24
Finished May 21 12:42:11 PM PDT 24
Peak memory 200500 kb
Host smart-e7aa2792-3af4-41cc-8cf3-b8566b7a6367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567940361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.567940361
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1027191323
Short name T515
Test name
Test status
Simulation time 50802680227 ps
CPU time 51.44 seconds
Started May 21 12:41:39 PM PDT 24
Finished May 21 12:42:32 PM PDT 24
Peak memory 200432 kb
Host smart-78774fa6-c7c5-47bf-96e4-d9e8e40e31f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027191323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1027191323
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_intr.1180171918
Short name T684
Test name
Test status
Simulation time 254298551651 ps
CPU time 349.09 seconds
Started May 21 12:41:39 PM PDT 24
Finished May 21 12:47:31 PM PDT 24
Peak memory 200436 kb
Host smart-e0085ceb-08c8-4f26-ab9e-eb98857fb51e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180171918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1180171918
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3446510851
Short name T357
Test name
Test status
Simulation time 52110913425 ps
CPU time 109.65 seconds
Started May 21 12:41:38 PM PDT 24
Finished May 21 12:43:30 PM PDT 24
Peak memory 200360 kb
Host smart-13cb1dfe-66ee-4b55-bb20-95fddcc6b555
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3446510851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3446510851
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.294107469
Short name T345
Test name
Test status
Simulation time 7640036359 ps
CPU time 9.3 seconds
Started May 21 12:41:40 PM PDT 24
Finished May 21 12:41:52 PM PDT 24
Peak memory 199324 kb
Host smart-4fcd74f6-7f15-48d6-a4b3-36659c6dd65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294107469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.294107469
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2973874565
Short name T913
Test name
Test status
Simulation time 112307105674 ps
CPU time 81.35 seconds
Started May 21 12:41:38 PM PDT 24
Finished May 21 12:43:02 PM PDT 24
Peak memory 200688 kb
Host smart-e23adbe6-6ea9-44da-ba68-013d88a41361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973874565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2973874565
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1954532891
Short name T486
Test name
Test status
Simulation time 7577013366 ps
CPU time 438.92 seconds
Started May 21 12:41:40 PM PDT 24
Finished May 21 12:49:02 PM PDT 24
Peak memory 200528 kb
Host smart-748f1bf5-4d54-44a4-91eb-abf6530dedfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954532891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1954532891
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1655571005
Short name T994
Test name
Test status
Simulation time 7221685436 ps
CPU time 59.07 seconds
Started May 21 12:41:37 PM PDT 24
Finished May 21 12:42:39 PM PDT 24
Peak memory 200392 kb
Host smart-7e3e4e29-869c-4dec-8743-3cf6fd0fb324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655571005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1655571005
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1586505905
Short name T553
Test name
Test status
Simulation time 38175483914 ps
CPU time 27.98 seconds
Started May 21 12:41:39 PM PDT 24
Finished May 21 12:42:09 PM PDT 24
Peak memory 200436 kb
Host smart-cab8b44d-5373-4dd4-a944-69f43286b302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586505905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1586505905
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3289368679
Short name T775
Test name
Test status
Simulation time 6663641952 ps
CPU time 11.86 seconds
Started May 21 12:41:39 PM PDT 24
Finished May 21 12:41:54 PM PDT 24
Peak memory 196820 kb
Host smart-05bdcda9-23d6-40a1-bdda-5e7e1c75832b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289368679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3289368679
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2073678972
Short name T283
Test name
Test status
Simulation time 5467180346 ps
CPU time 17.53 seconds
Started May 21 12:41:39 PM PDT 24
Finished May 21 12:42:00 PM PDT 24
Peak memory 200052 kb
Host smart-980c773d-a25b-433e-826d-98d2fae1ee1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073678972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2073678972
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2673425874
Short name T1166
Test name
Test status
Simulation time 206524458523 ps
CPU time 81.13 seconds
Started May 21 12:41:41 PM PDT 24
Finished May 21 12:43:04 PM PDT 24
Peak memory 200788 kb
Host smart-41489142-f317-4165-af90-8ad0d3c73dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673425874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2673425874
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3641033689
Short name T67
Test name
Test status
Simulation time 145545983904 ps
CPU time 415.91 seconds
Started May 21 12:41:37 PM PDT 24
Finished May 21 12:48:35 PM PDT 24
Peak memory 217148 kb
Host smart-fe9e69bf-2af4-4cc9-8fa7-f3c7c89b42f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641033689 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3641033689
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3621428886
Short name T1074
Test name
Test status
Simulation time 1266442683 ps
CPU time 1.49 seconds
Started May 21 12:41:39 PM PDT 24
Finished May 21 12:41:44 PM PDT 24
Peak memory 199080 kb
Host smart-46b35e65-70d2-4239-9a8a-fae829ca972b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621428886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3621428886
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1988269606
Short name T1002
Test name
Test status
Simulation time 33172524792 ps
CPU time 70.96 seconds
Started May 21 12:41:38 PM PDT 24
Finished May 21 12:42:51 PM PDT 24
Peak memory 200392 kb
Host smart-c576c24c-5e56-4233-8f47-48eaf4308bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988269606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1988269606
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.662665083
Short name T27
Test name
Test status
Simulation time 10532628 ps
CPU time 0.55 seconds
Started May 21 12:41:45 PM PDT 24
Finished May 21 12:41:49 PM PDT 24
Peak memory 195348 kb
Host smart-63b63d2e-4b50-4d6a-967b-71ccabff372a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662665083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.662665083
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1388899042
Short name T899
Test name
Test status
Simulation time 23903061615 ps
CPU time 41.83 seconds
Started May 21 12:41:40 PM PDT 24
Finished May 21 12:42:25 PM PDT 24
Peak memory 200540 kb
Host smart-d99f5758-f781-4144-a903-cc65e78c9cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388899042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1388899042
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.18028841
Short name T262
Test name
Test status
Simulation time 119187804730 ps
CPU time 29.36 seconds
Started May 21 12:41:40 PM PDT 24
Finished May 21 12:42:12 PM PDT 24
Peak memory 200384 kb
Host smart-e572145f-433b-46b1-8fea-05c6e5656622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18028841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.18028841
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1460994145
Short name T139
Test name
Test status
Simulation time 61080147875 ps
CPU time 70.31 seconds
Started May 21 12:41:39 PM PDT 24
Finished May 21 12:42:53 PM PDT 24
Peak memory 200456 kb
Host smart-ace4d5ca-462a-4aac-94f2-c24cdddefd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460994145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1460994145
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.875187636
Short name T530
Test name
Test status
Simulation time 282315075399 ps
CPU time 395.74 seconds
Started May 21 12:41:38 PM PDT 24
Finished May 21 12:48:16 PM PDT 24
Peak memory 198620 kb
Host smart-ef2dd09a-8613-4738-8627-b0f1d3b2a470
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875187636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.875187636
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3149125615
Short name T783
Test name
Test status
Simulation time 259965726000 ps
CPU time 120.98 seconds
Started May 21 12:41:45 PM PDT 24
Finished May 21 12:43:49 PM PDT 24
Peak memory 200456 kb
Host smart-df273694-1c90-40dd-be71-b6e86ad00c83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3149125615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3149125615
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2793574836
Short name T490
Test name
Test status
Simulation time 4187571933 ps
CPU time 10.23 seconds
Started May 21 12:41:43 PM PDT 24
Finished May 21 12:41:55 PM PDT 24
Peak memory 199188 kb
Host smart-6c55d24c-edb7-47ef-9adc-aee817ce1f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793574836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2793574836
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1198013776
Short name T966
Test name
Test status
Simulation time 4198191884 ps
CPU time 8.38 seconds
Started May 21 12:41:39 PM PDT 24
Finished May 21 12:41:50 PM PDT 24
Peak memory 200692 kb
Host smart-36208302-8d62-4edd-921b-b09ae93c03f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198013776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1198013776
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.397310197
Short name T519
Test name
Test status
Simulation time 19386748028 ps
CPU time 979.14 seconds
Started May 21 12:41:46 PM PDT 24
Finished May 21 12:58:08 PM PDT 24
Peak memory 200452 kb
Host smart-f1b60d5a-d779-487f-81b6-591c49d5f2ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=397310197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.397310197
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2837824968
Short name T442
Test name
Test status
Simulation time 4953858946 ps
CPU time 41.34 seconds
Started May 21 12:41:39 PM PDT 24
Finished May 21 12:42:24 PM PDT 24
Peak memory 198940 kb
Host smart-d5007e5b-9937-4037-bc93-630c041e1048
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2837824968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2837824968
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3322816091
Short name T1147
Test name
Test status
Simulation time 201024574528 ps
CPU time 52.93 seconds
Started May 21 12:41:48 PM PDT 24
Finished May 21 12:42:43 PM PDT 24
Peak memory 200476 kb
Host smart-e3452af9-5dfb-430c-a818-677f68d4b09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322816091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3322816091
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3404169202
Short name T390
Test name
Test status
Simulation time 1587346073 ps
CPU time 3.19 seconds
Started May 21 12:41:38 PM PDT 24
Finished May 21 12:41:43 PM PDT 24
Peak memory 195840 kb
Host smart-7682d4ac-7e78-46b2-8267-0ce52747966d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404169202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3404169202
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3481834319
Short name T767
Test name
Test status
Simulation time 747115453 ps
CPU time 1.21 seconds
Started May 21 12:41:37 PM PDT 24
Finished May 21 12:41:41 PM PDT 24
Peak memory 199796 kb
Host smart-1acd3b1b-81c2-412c-8d8d-c9b731b542ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481834319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3481834319
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3328656525
Short name T1064
Test name
Test status
Simulation time 160708713579 ps
CPU time 823.7 seconds
Started May 21 12:41:42 PM PDT 24
Finished May 21 12:55:27 PM PDT 24
Peak memory 200392 kb
Host smart-afec3038-bc83-4014-ac12-0d449c020ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328656525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3328656525
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3263977716
Short name T843
Test name
Test status
Simulation time 409753448892 ps
CPU time 1636.53 seconds
Started May 21 12:41:43 PM PDT 24
Finished May 21 01:09:02 PM PDT 24
Peak memory 233512 kb
Host smart-9a56c00f-94b1-47d6-933b-2f323bdd9ba5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263977716 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3263977716
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.586658844
Short name T801
Test name
Test status
Simulation time 1232778248 ps
CPU time 2.17 seconds
Started May 21 12:41:44 PM PDT 24
Finished May 21 12:41:49 PM PDT 24
Peak memory 198656 kb
Host smart-a89cd170-11b0-488c-89ab-f0a681b655e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586658844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.586658844
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.4235486600
Short name T253
Test name
Test status
Simulation time 85677934033 ps
CPU time 36.16 seconds
Started May 21 12:41:40 PM PDT 24
Finished May 21 12:42:19 PM PDT 24
Peak memory 200456 kb
Host smart-7f02ee04-5ba7-4676-846b-1e31c7ec2f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235486600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.4235486600
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1060058433
Short name T418
Test name
Test status
Simulation time 34559657 ps
CPU time 0.59 seconds
Started May 21 12:41:45 PM PDT 24
Finished May 21 12:41:49 PM PDT 24
Peak memory 195848 kb
Host smart-edf65749-cfae-4314-bd25-f70ff19409bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060058433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1060058433
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.4059679282
Short name T449
Test name
Test status
Simulation time 138302023025 ps
CPU time 125.32 seconds
Started May 21 12:41:42 PM PDT 24
Finished May 21 12:43:50 PM PDT 24
Peak memory 200424 kb
Host smart-36e80907-3d6d-4b7f-a900-851961fa0684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059679282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.4059679282
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2930718183
Short name T1085
Test name
Test status
Simulation time 78260237207 ps
CPU time 172.97 seconds
Started May 21 12:41:44 PM PDT 24
Finished May 21 12:44:40 PM PDT 24
Peak memory 200380 kb
Host smart-8d4cc5ad-0075-4bba-bfb3-d93883005cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930718183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2930718183
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2719673100
Short name T1146
Test name
Test status
Simulation time 62580830480 ps
CPU time 154.41 seconds
Started May 21 12:41:43 PM PDT 24
Finished May 21 12:44:20 PM PDT 24
Peak memory 200504 kb
Host smart-014fe02d-1461-4be4-8204-d78f8005c4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719673100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2719673100
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.744870159
Short name T1014
Test name
Test status
Simulation time 102171276620 ps
CPU time 19.66 seconds
Started May 21 12:41:45 PM PDT 24
Finished May 21 12:42:07 PM PDT 24
Peak memory 200092 kb
Host smart-60b8334d-cbfe-4cbe-bbe0-6c76703c5365
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744870159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.744870159
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2515694246
Short name T246
Test name
Test status
Simulation time 100187617219 ps
CPU time 296.17 seconds
Started May 21 12:41:46 PM PDT 24
Finished May 21 12:46:45 PM PDT 24
Peak memory 200456 kb
Host smart-f554abb1-efda-49d4-97ac-c47ef9ba0376
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515694246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2515694246
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3099770858
Short name T761
Test name
Test status
Simulation time 7885484785 ps
CPU time 23.94 seconds
Started May 21 12:41:46 PM PDT 24
Finished May 21 12:42:13 PM PDT 24
Peak memory 198820 kb
Host smart-ca242e2f-88b3-4330-a850-dd8748ee1a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099770858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3099770858
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2718337245
Short name T263
Test name
Test status
Simulation time 30429757233 ps
CPU time 50.87 seconds
Started May 21 12:41:44 PM PDT 24
Finished May 21 12:42:38 PM PDT 24
Peak memory 199420 kb
Host smart-215d15dc-f754-480b-9382-e1a027660d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718337245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2718337245
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.4165161176
Short name T318
Test name
Test status
Simulation time 9762408966 ps
CPU time 268.86 seconds
Started May 21 12:41:48 PM PDT 24
Finished May 21 12:46:19 PM PDT 24
Peak memory 200476 kb
Host smart-c31df8d2-76a9-4fb2-b32f-4e78c61f6308
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4165161176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.4165161176
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2436335427
Short name T627
Test name
Test status
Simulation time 5257705713 ps
CPU time 43.93 seconds
Started May 21 12:41:44 PM PDT 24
Finished May 21 12:42:31 PM PDT 24
Peak memory 198596 kb
Host smart-a89db0d1-e375-4657-be2a-dbd2a0d0c6cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2436335427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2436335427
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1982822213
Short name T1125
Test name
Test status
Simulation time 24458388782 ps
CPU time 49.45 seconds
Started May 21 12:41:43 PM PDT 24
Finished May 21 12:42:35 PM PDT 24
Peak memory 200400 kb
Host smart-820f9cdc-93f5-4bc7-a934-220bfc1b27a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982822213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1982822213
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3387686234
Short name T6
Test name
Test status
Simulation time 1510013139 ps
CPU time 1.8 seconds
Started May 21 12:41:47 PM PDT 24
Finished May 21 12:41:51 PM PDT 24
Peak memory 196112 kb
Host smart-e3d2143d-6531-4503-89b8-47f96f5bb83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387686234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3387686234
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3274743635
Short name T935
Test name
Test status
Simulation time 469102712 ps
CPU time 1.64 seconds
Started May 21 12:41:45 PM PDT 24
Finished May 21 12:41:49 PM PDT 24
Peak memory 199132 kb
Host smart-a238bab8-5eb0-482b-ae59-469c45c42a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274743635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3274743635
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1052652706
Short name T1143
Test name
Test status
Simulation time 75860632296 ps
CPU time 22.54 seconds
Started May 21 12:41:44 PM PDT 24
Finished May 21 12:42:10 PM PDT 24
Peak memory 200508 kb
Host smart-ddc8d724-551c-45cb-96a2-7f84efe1ce35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052652706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1052652706
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.4003366742
Short name T35
Test name
Test status
Simulation time 64898294591 ps
CPU time 148.64 seconds
Started May 21 12:41:45 PM PDT 24
Finished May 21 12:44:16 PM PDT 24
Peak memory 217160 kb
Host smart-5cbaf38f-ba98-4052-9759-91b0a144f657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003366742 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.4003366742
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.255201662
Short name T100
Test name
Test status
Simulation time 2223324492 ps
CPU time 2.33 seconds
Started May 21 12:41:44 PM PDT 24
Finished May 21 12:41:48 PM PDT 24
Peak memory 199256 kb
Host smart-ba78e8e9-c28d-4bcc-aa2f-19b91d2c8cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255201662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.255201662
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.4178516682
Short name T379
Test name
Test status
Simulation time 15671689290 ps
CPU time 23.56 seconds
Started May 21 12:41:45 PM PDT 24
Finished May 21 12:42:11 PM PDT 24
Peak memory 199576 kb
Host smart-435a9f29-48a1-4ef7-aefe-43cd38fa643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178516682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.4178516682
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.4072621993
Short name T534
Test name
Test status
Simulation time 64040858 ps
CPU time 0.54 seconds
Started May 21 12:41:53 PM PDT 24
Finished May 21 12:41:55 PM PDT 24
Peak memory 194852 kb
Host smart-72b3d0cf-60d3-46bd-9149-7622cabaa08b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072621993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.4072621993
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1154208127
Short name T492
Test name
Test status
Simulation time 54261381432 ps
CPU time 25.45 seconds
Started May 21 12:41:51 PM PDT 24
Finished May 21 12:42:19 PM PDT 24
Peak memory 200472 kb
Host smart-e0531374-5798-4e11-bbe0-c46c0055e515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154208127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1154208127
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1459382233
Short name T174
Test name
Test status
Simulation time 32372524598 ps
CPU time 50.18 seconds
Started May 21 12:41:54 PM PDT 24
Finished May 21 12:42:46 PM PDT 24
Peak memory 200504 kb
Host smart-7e4506f4-8a85-49b5-82b3-5fd53039b49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459382233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1459382233
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1424948518
Short name T830
Test name
Test status
Simulation time 4881129486 ps
CPU time 8.91 seconds
Started May 21 12:41:52 PM PDT 24
Finished May 21 12:42:03 PM PDT 24
Peak memory 197624 kb
Host smart-e092c9ca-4774-488a-ba6f-424dea3fd181
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424948518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1424948518
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3436790023
Short name T1092
Test name
Test status
Simulation time 107573590242 ps
CPU time 793.26 seconds
Started May 21 12:41:56 PM PDT 24
Finished May 21 12:55:11 PM PDT 24
Peak memory 200436 kb
Host smart-65b4ad73-0576-4873-919b-5dd2b56e273b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436790023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3436790023
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2389871852
Short name T738
Test name
Test status
Simulation time 5199020721 ps
CPU time 4.31 seconds
Started May 21 12:41:53 PM PDT 24
Finished May 21 12:41:59 PM PDT 24
Peak memory 198568 kb
Host smart-54c59496-33af-4b26-9b0c-6ef767304651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389871852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2389871852
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3637945337
Short name T662
Test name
Test status
Simulation time 106075416689 ps
CPU time 380.23 seconds
Started May 21 12:41:50 PM PDT 24
Finished May 21 12:48:13 PM PDT 24
Peak memory 200764 kb
Host smart-e06634c3-99ce-494c-aa4c-c27ebd602712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637945337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3637945337
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1706099102
Short name T58
Test name
Test status
Simulation time 7274655130 ps
CPU time 151.81 seconds
Started May 21 12:41:54 PM PDT 24
Finished May 21 12:44:28 PM PDT 24
Peak memory 200508 kb
Host smart-808b3f81-fd25-445b-b9f8-54a240aabff3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1706099102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1706099102
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3148913760
Short name T22
Test name
Test status
Simulation time 6316097568 ps
CPU time 20.02 seconds
Started May 21 12:41:58 PM PDT 24
Finished May 21 12:42:19 PM PDT 24
Peak memory 198648 kb
Host smart-997a13c1-51d5-41f1-bc5a-78d62301da82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148913760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3148913760
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1074734334
Short name T151
Test name
Test status
Simulation time 32024297600 ps
CPU time 14.09 seconds
Started May 21 12:41:53 PM PDT 24
Finished May 21 12:42:09 PM PDT 24
Peak memory 200384 kb
Host smart-1a2f52b1-1aeb-4c29-bd9a-407d564a2303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074734334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1074734334
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.126636660
Short name T398
Test name
Test status
Simulation time 35193761666 ps
CPU time 10.8 seconds
Started May 21 12:42:01 PM PDT 24
Finished May 21 12:42:15 PM PDT 24
Peak memory 196140 kb
Host smart-98877983-5c11-4eff-9464-9fd4b5296328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126636660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.126636660
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2542075547
Short name T505
Test name
Test status
Simulation time 696880654 ps
CPU time 1.51 seconds
Started May 21 12:41:51 PM PDT 24
Finished May 21 12:41:55 PM PDT 24
Peak memory 200004 kb
Host smart-2ba08063-75c2-4b35-be83-3459f425761f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542075547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2542075547
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1642763775
Short name T155
Test name
Test status
Simulation time 61321088224 ps
CPU time 138.82 seconds
Started May 21 12:41:50 PM PDT 24
Finished May 21 12:44:11 PM PDT 24
Peak memory 200452 kb
Host smart-22e53b04-fd26-43c3-a138-b52fa2e47a99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642763775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1642763775
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1307724263
Short name T199
Test name
Test status
Simulation time 113603428082 ps
CPU time 1064.68 seconds
Started May 21 12:41:49 PM PDT 24
Finished May 21 12:59:36 PM PDT 24
Peak memory 225108 kb
Host smart-77da84ee-3c58-44b4-b88f-735c4faeaaaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307724263 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1307724263
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1031772011
Short name T416
Test name
Test status
Simulation time 1732748661 ps
CPU time 2.22 seconds
Started May 21 12:42:00 PM PDT 24
Finished May 21 12:42:06 PM PDT 24
Peak memory 199276 kb
Host smart-238402db-d841-44b4-ae22-e024e7bc2950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031772011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1031772011
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1305278775
Short name T990
Test name
Test status
Simulation time 354975156530 ps
CPU time 49.19 seconds
Started May 21 12:41:50 PM PDT 24
Finished May 21 12:42:42 PM PDT 24
Peak memory 200428 kb
Host smart-7d81683a-d0c8-47b5-b540-3a146e7f5640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305278775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1305278775
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2963860747
Short name T1114
Test name
Test status
Simulation time 109695128 ps
CPU time 0.54 seconds
Started May 21 12:39:16 PM PDT 24
Finished May 21 12:39:27 PM PDT 24
Peak memory 195820 kb
Host smart-a928defb-bd64-47ca-bf2d-5bea6558c406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963860747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2963860747
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2139269969
Short name T774
Test name
Test status
Simulation time 166361292514 ps
CPU time 16.7 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:40:01 PM PDT 24
Peak memory 200424 kb
Host smart-e91ac75d-b687-4842-89bd-6d137a2affc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139269969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2139269969
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2551212968
Short name T475
Test name
Test status
Simulation time 128322872435 ps
CPU time 101.93 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:41:05 PM PDT 24
Peak memory 200360 kb
Host smart-cbcd7ead-1a48-450a-b055-07e1682d2d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551212968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2551212968
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1897038628
Short name T520
Test name
Test status
Simulation time 20235507297 ps
CPU time 33.72 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:39:56 PM PDT 24
Peak memory 200452 kb
Host smart-4ea256a2-7bf8-4a21-ae7c-6860da785a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897038628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1897038628
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.911463400
Short name T556
Test name
Test status
Simulation time 26131928598 ps
CPU time 3.64 seconds
Started May 21 12:39:26 PM PDT 24
Finished May 21 12:39:39 PM PDT 24
Peak memory 199332 kb
Host smart-96684f85-0d2d-426e-9840-2ac177d50ebe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911463400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.911463400
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2746044513
Short name T403
Test name
Test status
Simulation time 203565268763 ps
CPU time 203.95 seconds
Started May 21 12:39:15 PM PDT 24
Finished May 21 12:42:50 PM PDT 24
Peak memory 200396 kb
Host smart-d094ce65-24d4-428a-8b3b-a00608c7ec0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746044513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2746044513
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1845094425
Short name T348
Test name
Test status
Simulation time 7995283146 ps
CPU time 5.98 seconds
Started May 21 12:39:28 PM PDT 24
Finished May 21 12:39:44 PM PDT 24
Peak memory 199288 kb
Host smart-4e3f9a03-ceff-44eb-821a-2debbeab0be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845094425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1845094425
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3302350362
Short name T676
Test name
Test status
Simulation time 284938790553 ps
CPU time 24.88 seconds
Started May 21 12:39:20 PM PDT 24
Finished May 21 12:39:55 PM PDT 24
Peak memory 216156 kb
Host smart-c256fa6a-f840-4f96-ba53-dbaf718b81d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302350362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3302350362
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.137846884
Short name T1059
Test name
Test status
Simulation time 16283554485 ps
CPU time 787.36 seconds
Started May 21 12:39:37 PM PDT 24
Finished May 21 12:52:55 PM PDT 24
Peak memory 200504 kb
Host smart-d1fc8edf-d7fd-4d0f-9b4f-1bff38a5da53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137846884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.137846884
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.406739415
Short name T961
Test name
Test status
Simulation time 1881154703 ps
CPU time 1.15 seconds
Started May 21 12:39:25 PM PDT 24
Finished May 21 12:39:36 PM PDT 24
Peak memory 198392 kb
Host smart-f1a99afa-b7b3-4df2-81fc-7fed7ed1b651
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=406739415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.406739415
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1137824606
Short name T1012
Test name
Test status
Simulation time 41187802669 ps
CPU time 20.17 seconds
Started May 21 12:39:38 PM PDT 24
Finished May 21 12:40:08 PM PDT 24
Peak memory 200352 kb
Host smart-e28a3cd8-156f-4718-a0e1-755fd9da8a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137824606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1137824606
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3479765522
Short name T1023
Test name
Test status
Simulation time 39396220639 ps
CPU time 63.01 seconds
Started May 21 12:39:13 PM PDT 24
Finished May 21 12:40:26 PM PDT 24
Peak memory 196208 kb
Host smart-7de1d5ad-bd67-45a5-aa5a-e2e99b3858e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479765522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3479765522
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2801618736
Short name T498
Test name
Test status
Simulation time 864662877 ps
CPU time 1.97 seconds
Started May 21 12:39:15 PM PDT 24
Finished May 21 12:39:27 PM PDT 24
Peak memory 200080 kb
Host smart-7c79dfe3-e70f-4e88-ae2e-255b17fb7d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801618736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2801618736
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3808985959
Short name T888
Test name
Test status
Simulation time 273446303752 ps
CPU time 311.39 seconds
Started May 21 12:39:28 PM PDT 24
Finished May 21 12:44:48 PM PDT 24
Peak memory 208952 kb
Host smart-eecdd7ac-525f-4d02-8610-b14a82b2d2d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808985959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3808985959
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3966075515
Short name T746
Test name
Test status
Simulation time 234915294186 ps
CPU time 614.87 seconds
Started May 21 12:39:28 PM PDT 24
Finished May 21 12:49:52 PM PDT 24
Peak memory 217188 kb
Host smart-85878224-f844-4d7e-97f9-d840b2974488
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966075515 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3966075515
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.4028041634
Short name T719
Test name
Test status
Simulation time 6457570639 ps
CPU time 21.34 seconds
Started May 21 12:39:14 PM PDT 24
Finished May 21 12:39:47 PM PDT 24
Peak memory 200216 kb
Host smart-f8700759-59cc-4d09-b2ac-937f0b76055d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028041634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.4028041634
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2587761157
Short name T576
Test name
Test status
Simulation time 182515348606 ps
CPU time 154.31 seconds
Started May 21 12:39:24 PM PDT 24
Finished May 21 12:42:08 PM PDT 24
Peak memory 200436 kb
Host smart-ddac6f8f-5af4-43be-8aff-872db3598e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587761157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2587761157
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.4277034689
Short name T753
Test name
Test status
Simulation time 19973732349 ps
CPU time 11.8 seconds
Started May 21 12:41:54 PM PDT 24
Finished May 21 12:42:07 PM PDT 24
Peak memory 200028 kb
Host smart-8da3b15c-a1be-49c2-8381-f1c5bbb01e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277034689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.4277034689
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.4019411300
Short name T1174
Test name
Test status
Simulation time 4996777822 ps
CPU time 73.22 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:43:18 PM PDT 24
Peak memory 216900 kb
Host smart-da7d122f-257b-4f28-a0bc-72419f897de4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019411300 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.4019411300
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3649183386
Short name T918
Test name
Test status
Simulation time 407153851959 ps
CPU time 1840.75 seconds
Started May 21 12:41:58 PM PDT 24
Finished May 21 01:12:40 PM PDT 24
Peak memory 225184 kb
Host smart-4cf867b7-8bbe-41cf-b522-ae1126886f1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649183386 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3649183386
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1967395588
Short name T1058
Test name
Test status
Simulation time 20055552085 ps
CPU time 19.14 seconds
Started May 21 12:41:52 PM PDT 24
Finished May 21 12:42:13 PM PDT 24
Peak memory 200596 kb
Host smart-3f43abe8-7466-4ce9-8110-2b9a6a9e51ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967395588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1967395588
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.209338532
Short name T780
Test name
Test status
Simulation time 121841355133 ps
CPU time 329.4 seconds
Started May 21 12:41:51 PM PDT 24
Finished May 21 12:47:23 PM PDT 24
Peak memory 217204 kb
Host smart-141bbbaf-443e-4092-b6f7-5094bc7da6d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209338532 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.209338532
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3300376501
Short name T860
Test name
Test status
Simulation time 14250436525 ps
CPU time 19.83 seconds
Started May 21 12:41:53 PM PDT 24
Finished May 21 12:42:15 PM PDT 24
Peak memory 200264 kb
Host smart-26e28c07-20f7-4eb8-9837-e4f3564c37b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300376501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3300376501
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3095391291
Short name T610
Test name
Test status
Simulation time 105824047799 ps
CPU time 486.48 seconds
Started May 21 12:41:50 PM PDT 24
Finished May 21 12:50:00 PM PDT 24
Peak memory 211920 kb
Host smart-e47aef96-c768-4512-a5c6-caf6d2b6e04a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095391291 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3095391291
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.726477256
Short name T955
Test name
Test status
Simulation time 33952053314 ps
CPU time 56.51 seconds
Started May 21 12:41:56 PM PDT 24
Finished May 21 12:42:54 PM PDT 24
Peak memory 200532 kb
Host smart-6e7002d1-de6e-4918-893c-177b9d82e13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726477256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.726477256
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3496743542
Short name T64
Test name
Test status
Simulation time 20254739576 ps
CPU time 362.94 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:48:08 PM PDT 24
Peak memory 216268 kb
Host smart-6871feb1-743e-4ab7-b692-84760380aa61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496743542 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3496743542
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3346990852
Short name T457
Test name
Test status
Simulation time 68476566437 ps
CPU time 29.73 seconds
Started May 21 12:41:51 PM PDT 24
Finished May 21 12:42:23 PM PDT 24
Peak memory 200484 kb
Host smart-7c40ccef-ccdd-437b-9145-8fc3c7a9c9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346990852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3346990852
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2732426713
Short name T993
Test name
Test status
Simulation time 65903445553 ps
CPU time 409.44 seconds
Started May 21 12:41:57 PM PDT 24
Finished May 21 12:48:48 PM PDT 24
Peak memory 217064 kb
Host smart-7f656075-2ebd-46a4-8ff3-449a3c1feac0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732426713 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2732426713
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1517200232
Short name T227
Test name
Test status
Simulation time 74162817738 ps
CPU time 72.61 seconds
Started May 21 12:41:50 PM PDT 24
Finished May 21 12:43:06 PM PDT 24
Peak memory 200412 kb
Host smart-19698966-05b3-47e6-b5ca-ab439fd323da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517200232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1517200232
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1633658504
Short name T34
Test name
Test status
Simulation time 150634105845 ps
CPU time 381.27 seconds
Started May 21 12:41:50 PM PDT 24
Finished May 21 12:48:14 PM PDT 24
Peak memory 228828 kb
Host smart-97d7564b-4d6d-439b-ad3f-3e99ba7f03c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633658504 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1633658504
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2974559280
Short name T786
Test name
Test status
Simulation time 56072727705 ps
CPU time 83.31 seconds
Started May 21 12:42:01 PM PDT 24
Finished May 21 12:43:28 PM PDT 24
Peak memory 200432 kb
Host smart-592907e1-ff58-466e-a02a-d0e7040bc8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974559280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2974559280
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.978959310
Short name T102
Test name
Test status
Simulation time 61195727573 ps
CPU time 94.83 seconds
Started May 21 12:41:56 PM PDT 24
Finished May 21 12:43:32 PM PDT 24
Peak memory 211352 kb
Host smart-08a3f0a8-6f30-4b81-89eb-7f990c5dd6fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978959310 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.978959310
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1379472728
Short name T239
Test name
Test status
Simulation time 27023107268 ps
CPU time 30.28 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:42:35 PM PDT 24
Peak memory 200484 kb
Host smart-a6cc0a92-e559-49fd-9328-48aca7c9adee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379472728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1379472728
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.50531780
Short name T577
Test name
Test status
Simulation time 131389868032 ps
CPU time 395 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:48:41 PM PDT 24
Peak memory 210856 kb
Host smart-a5b4cd3e-6e81-4514-8be1-71dfb6b12007
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50531780 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.50531780
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1239323001
Short name T175
Test name
Test status
Simulation time 142635113207 ps
CPU time 57.2 seconds
Started May 21 12:42:00 PM PDT 24
Finished May 21 12:43:00 PM PDT 24
Peak memory 200468 kb
Host smart-58f5ef82-3ec7-4e46-b957-e97bf8d90409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239323001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1239323001
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1059362688
Short name T315
Test name
Test status
Simulation time 126337635695 ps
CPU time 316.79 seconds
Started May 21 12:42:01 PM PDT 24
Finished May 21 12:47:22 PM PDT 24
Peak memory 210616 kb
Host smart-1801e3a6-c9a8-49d0-968d-3c4c5b08acb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059362688 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1059362688
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3726171206
Short name T779
Test name
Test status
Simulation time 22527827 ps
CPU time 0.54 seconds
Started May 21 12:39:22 PM PDT 24
Finished May 21 12:39:33 PM PDT 24
Peak memory 195904 kb
Host smart-a2a8cf0d-65f5-4db7-b42f-0c76afd6b561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726171206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3726171206
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1879113585
Short name T1034
Test name
Test status
Simulation time 248302168041 ps
CPU time 119.43 seconds
Started May 21 12:39:18 PM PDT 24
Finished May 21 12:41:28 PM PDT 24
Peak memory 200376 kb
Host smart-23f632f0-7f7b-438d-b9b6-ca16915bc89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879113585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1879113585
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1934522894
Short name T1041
Test name
Test status
Simulation time 15473951358 ps
CPU time 25.99 seconds
Started May 21 12:39:20 PM PDT 24
Finished May 21 12:39:57 PM PDT 24
Peak memory 198876 kb
Host smart-8740c992-8f77-41d5-8d2c-9dcb08603158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934522894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1934522894
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3334784299
Short name T238
Test name
Test status
Simulation time 43058794012 ps
CPU time 69.49 seconds
Started May 21 12:39:21 PM PDT 24
Finished May 21 12:40:41 PM PDT 24
Peak memory 200460 kb
Host smart-b918bd16-f4e4-43e5-bc8f-9cd956bb65ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334784299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3334784299
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3108159054
Short name T16
Test name
Test status
Simulation time 52365179547 ps
CPU time 13.68 seconds
Started May 21 12:39:23 PM PDT 24
Finished May 21 12:39:47 PM PDT 24
Peak memory 200708 kb
Host smart-2bbefa2d-d2e8-407a-8817-b70d8a57438b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108159054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3108159054
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.4257132003
Short name T254
Test name
Test status
Simulation time 47216683004 ps
CPU time 471.36 seconds
Started May 21 12:39:19 PM PDT 24
Finished May 21 12:47:21 PM PDT 24
Peak memory 200452 kb
Host smart-135ba711-d27e-4b82-bbc7-a27395ff840f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4257132003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.4257132003
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1598196424
Short name T781
Test name
Test status
Simulation time 6868683734 ps
CPU time 14.01 seconds
Started May 21 12:39:37 PM PDT 24
Finished May 21 12:40:01 PM PDT 24
Peak memory 198924 kb
Host smart-4b874964-a46a-4b13-9714-2233f24ccc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598196424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1598196424
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2311693908
Short name T257
Test name
Test status
Simulation time 31228181052 ps
CPU time 59.28 seconds
Started May 21 12:39:28 PM PDT 24
Finished May 21 12:40:36 PM PDT 24
Peak memory 199224 kb
Host smart-e6b4b347-f0bc-4e36-8129-cf64f297ab2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311693908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2311693908
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1600218598
Short name T394
Test name
Test status
Simulation time 20190215333 ps
CPU time 602.61 seconds
Started May 21 12:39:27 PM PDT 24
Finished May 21 12:49:39 PM PDT 24
Peak memory 200544 kb
Host smart-01e0abdc-b2d7-498c-89ff-af0eaa6d2507
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1600218598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1600218598
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3777635620
Short name T942
Test name
Test status
Simulation time 2118861937 ps
CPU time 3.39 seconds
Started May 21 12:39:31 PM PDT 24
Finished May 21 12:39:43 PM PDT 24
Peak memory 198588 kb
Host smart-47eece51-536f-4324-aba3-58aeb7b18224
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3777635620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3777635620
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1689132283
Short name T1075
Test name
Test status
Simulation time 135243967399 ps
CPU time 255.08 seconds
Started May 21 12:39:20 PM PDT 24
Finished May 21 12:43:46 PM PDT 24
Peak memory 200472 kb
Host smart-6f7df0f5-dc4b-417d-9459-5b217e407df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689132283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1689132283
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1442339255
Short name T861
Test name
Test status
Simulation time 50032048729 ps
CPU time 74.7 seconds
Started May 21 12:39:22 PM PDT 24
Finished May 21 12:40:47 PM PDT 24
Peak memory 196512 kb
Host smart-ff15fd1b-ca13-409d-a9b9-7605c167e745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442339255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1442339255
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3292326732
Short name T456
Test name
Test status
Simulation time 99387830 ps
CPU time 0.73 seconds
Started May 21 12:39:23 PM PDT 24
Finished May 21 12:39:34 PM PDT 24
Peak memory 197388 kb
Host smart-1ab206a2-54eb-489c-bce1-ede159b5ae5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292326732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3292326732
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.349021100
Short name T752
Test name
Test status
Simulation time 176017994084 ps
CPU time 1742.24 seconds
Started May 21 12:39:19 PM PDT 24
Finished May 21 01:08:33 PM PDT 24
Peak memory 200480 kb
Host smart-68dcaf19-2ff8-4d93-ae9e-e2277dce7829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349021100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.349021100
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2364115472
Short name T710
Test name
Test status
Simulation time 26463441226 ps
CPU time 303.57 seconds
Started May 21 12:39:23 PM PDT 24
Finished May 21 12:44:36 PM PDT 24
Peak memory 215964 kb
Host smart-53aafe42-720a-4ab1-a1c2-0f16817ffb57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364115472 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2364115472
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1052304851
Short name T395
Test name
Test status
Simulation time 826865406 ps
CPU time 1.86 seconds
Started May 21 12:39:42 PM PDT 24
Finished May 21 12:39:54 PM PDT 24
Peak memory 198924 kb
Host smart-b6ebefe6-c375-4322-beb7-73b6bfd08267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052304851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1052304851
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2494720092
Short name T882
Test name
Test status
Simulation time 89538788933 ps
CPU time 93.76 seconds
Started May 21 12:39:31 PM PDT 24
Finished May 21 12:41:13 PM PDT 24
Peak memory 200480 kb
Host smart-882c9664-f0c5-4a74-95ce-e92583fa0fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494720092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2494720092
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.280419103
Short name T921
Test name
Test status
Simulation time 117475594716 ps
CPU time 199.02 seconds
Started May 21 12:42:00 PM PDT 24
Finished May 21 12:45:23 PM PDT 24
Peak memory 200428 kb
Host smart-f09621de-5523-4e47-95c9-a3aa69b904d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280419103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.280419103
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2476651634
Short name T375
Test name
Test status
Simulation time 76685756934 ps
CPU time 226.25 seconds
Started May 21 12:41:59 PM PDT 24
Finished May 21 12:45:47 PM PDT 24
Peak memory 208828 kb
Host smart-949f9c73-3305-426d-89c9-37c44aa2c397
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476651634 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2476651634
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3555615035
Short name T655
Test name
Test status
Simulation time 234428885038 ps
CPU time 41.29 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:42:47 PM PDT 24
Peak memory 200400 kb
Host smart-24ec3710-7d11-4771-9cbe-bb40842763e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555615035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3555615035
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2895996146
Short name T65
Test name
Test status
Simulation time 145371412117 ps
CPU time 1964.33 seconds
Started May 21 12:41:59 PM PDT 24
Finished May 21 01:14:45 PM PDT 24
Peak memory 225460 kb
Host smart-ca270683-81d7-47cd-b231-2ba7195f6041
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895996146 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2895996146
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.965738924
Short name T841
Test name
Test status
Simulation time 153229268369 ps
CPU time 279.88 seconds
Started May 21 12:42:05 PM PDT 24
Finished May 21 12:46:47 PM PDT 24
Peak memory 200412 kb
Host smart-3a4dfa70-62b5-4954-96d7-1626e0560f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965738924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.965738924
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2667405490
Short name T1178
Test name
Test status
Simulation time 61333257013 ps
CPU time 339.07 seconds
Started May 21 12:42:03 PM PDT 24
Finished May 21 12:47:46 PM PDT 24
Peak memory 215528 kb
Host smart-825d198f-a12e-4285-a2d5-ce56de072343
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667405490 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2667405490
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3165822811
Short name T1005
Test name
Test status
Simulation time 62575300278 ps
CPU time 21.83 seconds
Started May 21 12:41:59 PM PDT 24
Finished May 21 12:42:23 PM PDT 24
Peak memory 200100 kb
Host smart-a95dbab0-3936-448f-82b5-99bbe7d98e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165822811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3165822811
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3484164248
Short name T573
Test name
Test status
Simulation time 126416064107 ps
CPU time 420.34 seconds
Started May 21 12:42:07 PM PDT 24
Finished May 21 12:49:10 PM PDT 24
Peak memory 226272 kb
Host smart-6dd06e7b-5984-4696-b720-c9cbd7f0fc1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484164248 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3484164248
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2083630293
Short name T784
Test name
Test status
Simulation time 80056087779 ps
CPU time 255.7 seconds
Started May 21 12:41:59 PM PDT 24
Finished May 21 12:46:16 PM PDT 24
Peak memory 200524 kb
Host smart-b18fccbc-62e7-44ff-824c-4386d3f2441a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083630293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2083630293
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2032108756
Short name T435
Test name
Test status
Simulation time 18926708573 ps
CPU time 245.48 seconds
Started May 21 12:42:00 PM PDT 24
Finished May 21 12:46:09 PM PDT 24
Peak memory 208648 kb
Host smart-8518f88e-0396-4f88-9dc9-28050e650bc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032108756 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2032108756
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.178658590
Short name T1020
Test name
Test status
Simulation time 12038325329 ps
CPU time 36.4 seconds
Started May 21 12:42:07 PM PDT 24
Finished May 21 12:42:46 PM PDT 24
Peak memory 200364 kb
Host smart-cd04f045-47a7-418f-beea-e4f3ce8e87f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178658590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.178658590
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2657669930
Short name T187
Test name
Test status
Simulation time 239092690348 ps
CPU time 798.37 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:55:25 PM PDT 24
Peak memory 225536 kb
Host smart-3045b769-34c8-45c2-840f-f0fc6ccbeacc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657669930 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2657669930
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3187844476
Short name T260
Test name
Test status
Simulation time 100765346801 ps
CPU time 83.05 seconds
Started May 21 12:42:01 PM PDT 24
Finished May 21 12:43:28 PM PDT 24
Peak memory 200544 kb
Host smart-8eef1618-9290-46cf-8277-f65c13333958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187844476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3187844476
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3239044160
Short name T557
Test name
Test status
Simulation time 91817118194 ps
CPU time 761.89 seconds
Started May 21 12:42:00 PM PDT 24
Finished May 21 12:54:46 PM PDT 24
Peak memory 212720 kb
Host smart-5d3995b7-2683-46ef-b001-3dfc6e26740e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239044160 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3239044160
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2698446929
Short name T1090
Test name
Test status
Simulation time 141667574656 ps
CPU time 644.29 seconds
Started May 21 12:42:00 PM PDT 24
Finished May 21 12:52:46 PM PDT 24
Peak memory 217104 kb
Host smart-1386c52d-c20f-44ab-8ec2-337adfb7734a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698446929 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2698446929
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.537197361
Short name T214
Test name
Test status
Simulation time 68042057413 ps
CPU time 63.14 seconds
Started May 21 12:42:01 PM PDT 24
Finished May 21 12:43:08 PM PDT 24
Peak memory 200444 kb
Host smart-27db8ea2-df22-40e2-95c9-41b51f6ee2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537197361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.537197361
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1930178217
Short name T755
Test name
Test status
Simulation time 140356766277 ps
CPU time 362.66 seconds
Started May 21 12:41:58 PM PDT 24
Finished May 21 12:48:02 PM PDT 24
Peak memory 226588 kb
Host smart-1f89c862-6eeb-4c63-b169-b95857e2412c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930178217 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1930178217
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1541650378
Short name T196
Test name
Test status
Simulation time 26643772144 ps
CPU time 12.62 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:42:18 PM PDT 24
Peak memory 200404 kb
Host smart-9c4562af-b7ae-46ca-b40e-5ce7d7f61c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541650378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1541650378
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3532853030
Short name T718
Test name
Test status
Simulation time 96559867288 ps
CPU time 580.38 seconds
Started May 21 12:42:00 PM PDT 24
Finished May 21 12:51:43 PM PDT 24
Peak memory 228380 kb
Host smart-dba98d24-5f2f-4645-abfd-d2b9e0f4115b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532853030 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3532853030
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.772865506
Short name T873
Test name
Test status
Simulation time 15536451 ps
CPU time 0.58 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:39:45 PM PDT 24
Peak memory 195896 kb
Host smart-35fa04fd-6394-4cd8-9f17-0720d5fa6955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772865506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.772865506
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.203748836
Short name T359
Test name
Test status
Simulation time 270359352877 ps
CPU time 1069.44 seconds
Started May 21 12:39:23 PM PDT 24
Finished May 21 12:57:23 PM PDT 24
Peak memory 200468 kb
Host smart-fdd524ea-8703-41d6-9687-8a85e2c900fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203748836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.203748836
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2307788601
Short name T129
Test name
Test status
Simulation time 17648772494 ps
CPU time 15.24 seconds
Started May 21 12:39:32 PM PDT 24
Finished May 21 12:39:56 PM PDT 24
Peak memory 199676 kb
Host smart-f7c96eb5-0d96-4bd9-88df-5d7c6c738472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307788601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2307788601
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1991753277
Short name T176
Test name
Test status
Simulation time 24500531032 ps
CPU time 44.02 seconds
Started May 21 12:39:18 PM PDT 24
Finished May 21 12:40:13 PM PDT 24
Peak memory 200388 kb
Host smart-2104f183-b681-499a-8917-f23fb490a364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991753277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1991753277
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1911485510
Short name T890
Test name
Test status
Simulation time 4104969299 ps
CPU time 9.26 seconds
Started May 21 12:39:22 PM PDT 24
Finished May 21 12:39:42 PM PDT 24
Peak memory 200368 kb
Host smart-cf29c38a-dd78-4444-9399-7700ac27d818
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911485510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1911485510
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2368646416
Short name T48
Test name
Test status
Simulation time 83840028392 ps
CPU time 797.64 seconds
Started May 21 12:39:38 PM PDT 24
Finished May 21 12:53:05 PM PDT 24
Peak memory 200680 kb
Host smart-20d2e772-f06b-48ac-aef8-cbbb32425e80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2368646416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2368646416
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1743974653
Short name T949
Test name
Test status
Simulation time 10091669175 ps
CPU time 19.91 seconds
Started May 21 12:39:22 PM PDT 24
Finished May 21 12:39:52 PM PDT 24
Peak memory 200188 kb
Host smart-7f0eef49-e0d8-4331-afaa-5baa88a9aa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743974653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1743974653
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.3020923107
Short name T54
Test name
Test status
Simulation time 101207466832 ps
CPU time 37.84 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:40:22 PM PDT 24
Peak memory 199364 kb
Host smart-f364061f-e020-4800-a480-bb162ebe8c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020923107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3020923107
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2938221070
Short name T1010
Test name
Test status
Simulation time 18046662070 ps
CPU time 66.08 seconds
Started May 21 12:39:31 PM PDT 24
Finished May 21 12:40:46 PM PDT 24
Peak memory 200524 kb
Host smart-15f4edae-d66a-49ac-bfeb-9fed503b9511
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2938221070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2938221070
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1088771737
Short name T846
Test name
Test status
Simulation time 6389358182 ps
CPU time 51.36 seconds
Started May 21 12:39:41 PM PDT 24
Finished May 21 12:40:42 PM PDT 24
Peak memory 198360 kb
Host smart-2807f218-44bf-4f0e-bb72-12f058120780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088771737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1088771737
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.4170204972
Short name T1164
Test name
Test status
Simulation time 73419579563 ps
CPU time 30.76 seconds
Started May 21 12:39:29 PM PDT 24
Finished May 21 12:40:09 PM PDT 24
Peak memory 200380 kb
Host smart-45a1b704-ff98-47d2-b644-8893d1477cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170204972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.4170204972
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.4269474877
Short name T1133
Test name
Test status
Simulation time 35580311042 ps
CPU time 27.84 seconds
Started May 21 12:39:42 PM PDT 24
Finished May 21 12:40:19 PM PDT 24
Peak memory 196816 kb
Host smart-3c70e655-c56d-459b-8ab7-2df34251df98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269474877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.4269474877
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3957896723
Short name T1145
Test name
Test status
Simulation time 285464859 ps
CPU time 1.53 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:39:46 PM PDT 24
Peak memory 199360 kb
Host smart-3fbd034f-aed4-46f6-b8df-e7c737affc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957896723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3957896723
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2648546479
Short name T314
Test name
Test status
Simulation time 33229123187 ps
CPU time 436.57 seconds
Started May 21 12:39:41 PM PDT 24
Finished May 21 12:47:07 PM PDT 24
Peak memory 216912 kb
Host smart-f56573c6-d110-447a-8eab-3e229d878472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648546479 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2648546479
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3186542951
Short name T376
Test name
Test status
Simulation time 1276089728 ps
CPU time 1.35 seconds
Started May 21 12:39:22 PM PDT 24
Finished May 21 12:39:33 PM PDT 24
Peak memory 197132 kb
Host smart-fc671dec-1cd1-4f72-bb81-c8367f3aa6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186542951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3186542951
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3367360338
Short name T1180
Test name
Test status
Simulation time 67404426610 ps
CPU time 109.71 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:41:34 PM PDT 24
Peak memory 200504 kb
Host smart-bf94855d-3b93-4071-bc42-7a35a79d4b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367360338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3367360338
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.608851257
Short name T482
Test name
Test status
Simulation time 54879068250 ps
CPU time 116.03 seconds
Started May 21 12:42:00 PM PDT 24
Finished May 21 12:43:59 PM PDT 24
Peak memory 200456 kb
Host smart-f94516f4-84e0-48fb-b8f9-ad6a70a2438e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608851257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.608851257
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2170513770
Short name T851
Test name
Test status
Simulation time 130518056493 ps
CPU time 597.29 seconds
Started May 21 12:42:01 PM PDT 24
Finished May 21 12:52:02 PM PDT 24
Peak memory 217224 kb
Host smart-a7c7cfbe-f155-4fe7-abc1-c712af6b0ddc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170513770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2170513770
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3953051941
Short name T965
Test name
Test status
Simulation time 13747800455 ps
CPU time 20.4 seconds
Started May 21 12:42:00 PM PDT 24
Finished May 21 12:42:23 PM PDT 24
Peak memory 200376 kb
Host smart-2358be3b-d153-42e2-92fc-bb92e4aff111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953051941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3953051941
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2904032307
Short name T960
Test name
Test status
Simulation time 44642492269 ps
CPU time 80.34 seconds
Started May 21 12:42:08 PM PDT 24
Finished May 21 12:43:31 PM PDT 24
Peak memory 200372 kb
Host smart-bf1cf45b-48a7-4e14-9085-b0c611c039e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904032307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2904032307
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.2069793707
Short name T1001
Test name
Test status
Simulation time 9236222851 ps
CPU time 55.61 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:43:01 PM PDT 24
Peak memory 208756 kb
Host smart-5d282d04-a35c-420b-935a-06aba5f0c650
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069793707 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2069793707
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1305089277
Short name T728
Test name
Test status
Simulation time 117758131361 ps
CPU time 31.14 seconds
Started May 21 12:42:03 PM PDT 24
Finished May 21 12:42:38 PM PDT 24
Peak memory 200428 kb
Host smart-676f5233-bcee-499c-9b05-6e3c0f13e90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305089277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1305089277
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2894109092
Short name T5
Test name
Test status
Simulation time 30103000573 ps
CPU time 28.09 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:42:34 PM PDT 24
Peak memory 199540 kb
Host smart-49f95e11-3b0f-4fd8-beb1-307c9176d23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894109092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2894109092
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3885704285
Short name T292
Test name
Test status
Simulation time 57132192054 ps
CPU time 1371.41 seconds
Started May 21 12:42:00 PM PDT 24
Finished May 21 01:04:55 PM PDT 24
Peak memory 216280 kb
Host smart-703d5f41-99d6-467a-bd39-3f4266891f38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885704285 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3885704285
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3186010498
Short name T874
Test name
Test status
Simulation time 178620729997 ps
CPU time 150.01 seconds
Started May 21 12:42:01 PM PDT 24
Finished May 21 12:44:35 PM PDT 24
Peak memory 200736 kb
Host smart-81756e52-2a64-4fa1-a20d-f6be74d8e169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186010498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3186010498
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.206079258
Short name T998
Test name
Test status
Simulation time 41867583213 ps
CPU time 158.4 seconds
Started May 21 12:41:59 PM PDT 24
Finished May 21 12:44:40 PM PDT 24
Peak memory 209044 kb
Host smart-6b028e86-4d93-4cb8-a93c-d915164dbd66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206079258 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.206079258
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2020956472
Short name T432
Test name
Test status
Simulation time 49562200753 ps
CPU time 22.01 seconds
Started May 21 12:42:01 PM PDT 24
Finished May 21 12:42:27 PM PDT 24
Peak memory 198656 kb
Host smart-c00e5be4-7d33-4df9-b7d3-9eda38bd863d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020956472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2020956472
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1740450761
Short name T687
Test name
Test status
Simulation time 68061866099 ps
CPU time 149.12 seconds
Started May 21 12:42:05 PM PDT 24
Finished May 21 12:44:36 PM PDT 24
Peak memory 216160 kb
Host smart-7777ef3a-abcd-4d80-b347-3d51c84527df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740450761 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1740450761
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.891201518
Short name T42
Test name
Test status
Simulation time 18189838667 ps
CPU time 31.55 seconds
Started May 21 12:42:04 PM PDT 24
Finished May 21 12:42:38 PM PDT 24
Peak memory 200488 kb
Host smart-e854a2df-68a2-41b0-9924-0cc6ac284853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891201518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.891201518
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.3417605656
Short name T925
Test name
Test status
Simulation time 87664737132 ps
CPU time 797.07 seconds
Started May 21 12:42:03 PM PDT 24
Finished May 21 12:55:24 PM PDT 24
Peak memory 225484 kb
Host smart-3fafea57-28af-4897-8257-e3379d1da915
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417605656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.3417605656
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.823898813
Short name T1008
Test name
Test status
Simulation time 18754724512 ps
CPU time 25.71 seconds
Started May 21 12:42:06 PM PDT 24
Finished May 21 12:42:34 PM PDT 24
Peak memory 200300 kb
Host smart-8e8028e6-2894-47ef-a96c-d29664224701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823898813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.823898813
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3942413097
Short name T121
Test name
Test status
Simulation time 89766344736 ps
CPU time 1366.4 seconds
Started May 21 12:42:05 PM PDT 24
Finished May 21 01:04:54 PM PDT 24
Peak memory 217244 kb
Host smart-7976360f-b8b5-438a-967f-3b87dfbd39eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942413097 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3942413097
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1445262861
Short name T688
Test name
Test status
Simulation time 15494646920 ps
CPU time 30.91 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:42:37 PM PDT 24
Peak memory 200452 kb
Host smart-a90755c3-6396-4be5-83e3-7fe9af13e314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445262861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1445262861
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2037021663
Short name T632
Test name
Test status
Simulation time 130933062622 ps
CPU time 676.52 seconds
Started May 21 12:42:07 PM PDT 24
Finished May 21 12:53:26 PM PDT 24
Peak memory 216856 kb
Host smart-4c1e4ae5-f976-4d5b-af70-cd06cfcbcdf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037021663 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2037021663
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3084230306
Short name T354
Test name
Test status
Simulation time 24965031 ps
CPU time 0.55 seconds
Started May 21 12:39:24 PM PDT 24
Finished May 21 12:39:34 PM PDT 24
Peak memory 195796 kb
Host smart-d51c81d2-0c7d-4b15-b7a5-f9e3f1b48ff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084230306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3084230306
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.419467325
Short name T807
Test name
Test status
Simulation time 223231664649 ps
CPU time 224.07 seconds
Started May 21 12:39:35 PM PDT 24
Finished May 21 12:43:29 PM PDT 24
Peak memory 200408 kb
Host smart-b35009a3-8244-4802-b1ac-8d4da2f7fba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419467325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.419467325
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1085471196
Short name T497
Test name
Test status
Simulation time 78911061363 ps
CPU time 120.83 seconds
Started May 21 12:39:24 PM PDT 24
Finished May 21 12:41:34 PM PDT 24
Peak memory 200624 kb
Host smart-17487065-833a-4827-a6c7-5ae14d53ae34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085471196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1085471196
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.4228145182
Short name T677
Test name
Test status
Simulation time 242066845161 ps
CPU time 26.28 seconds
Started May 21 12:39:38 PM PDT 24
Finished May 21 12:40:14 PM PDT 24
Peak memory 200052 kb
Host smart-0497839f-0ab8-4107-b012-058b24217b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228145182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.4228145182
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2009288801
Short name T487
Test name
Test status
Simulation time 7406774507 ps
CPU time 13.25 seconds
Started May 21 12:39:38 PM PDT 24
Finished May 21 12:40:01 PM PDT 24
Peak memory 197260 kb
Host smart-77e78e33-2bd6-4e1b-9682-a2b9374edd67
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009288801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2009288801
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3624256547
Short name T790
Test name
Test status
Simulation time 98657255755 ps
CPU time 790.74 seconds
Started May 21 12:39:26 PM PDT 24
Finished May 21 12:52:46 PM PDT 24
Peak memory 200480 kb
Host smart-cb9d03c7-33df-48ae-ae4d-6804a6f4a92b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624256547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3624256547
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3794199379
Short name T362
Test name
Test status
Simulation time 7019336117 ps
CPU time 4.96 seconds
Started May 21 12:39:39 PM PDT 24
Finished May 21 12:39:54 PM PDT 24
Peak memory 199272 kb
Host smart-a9ebb6a8-b3f0-4ec5-b079-fce6ddef4a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794199379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3794199379
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3402791556
Short name T269
Test name
Test status
Simulation time 71011626157 ps
CPU time 102.69 seconds
Started May 21 12:39:26 PM PDT 24
Finished May 21 12:41:18 PM PDT 24
Peak memory 200788 kb
Host smart-9efdade2-5328-4ee9-92e8-167cd5334510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402791556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3402791556
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1674560207
Short name T601
Test name
Test status
Simulation time 19779820366 ps
CPU time 67.07 seconds
Started May 21 12:39:23 PM PDT 24
Finished May 21 12:40:40 PM PDT 24
Peak memory 200436 kb
Host smart-4f0c7e7a-064a-4869-ba85-b292f0176d95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1674560207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1674560207
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.4240830045
Short name T349
Test name
Test status
Simulation time 1830823568 ps
CPU time 2.85 seconds
Started May 21 12:39:42 PM PDT 24
Finished May 21 12:39:55 PM PDT 24
Peak memory 198400 kb
Host smart-9b29c281-1261-4c2c-a8f5-2126d054c75f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4240830045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.4240830045
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.39333304
Short name T378
Test name
Test status
Simulation time 39026315232 ps
CPU time 16.78 seconds
Started May 21 12:39:22 PM PDT 24
Finished May 21 12:39:49 PM PDT 24
Peak memory 200172 kb
Host smart-e0a9b16a-e817-4715-920a-7ec726806e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39333304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.39333304
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2818860659
Short name T424
Test name
Test status
Simulation time 3040939297 ps
CPU time 1.85 seconds
Started May 21 12:39:43 PM PDT 24
Finished May 21 12:39:54 PM PDT 24
Peak memory 196532 kb
Host smart-641e949f-8fe1-47ea-8e72-09a41a64cf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818860659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2818860659
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1083934369
Short name T597
Test name
Test status
Simulation time 921206759 ps
CPU time 2.32 seconds
Started May 21 12:39:29 PM PDT 24
Finished May 21 12:39:40 PM PDT 24
Peak memory 199336 kb
Host smart-a13812bf-a749-487b-a347-eadea5530370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083934369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1083934369
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.4254892157
Short name T63
Test name
Test status
Simulation time 85042744781 ps
CPU time 603.46 seconds
Started May 21 12:39:44 PM PDT 24
Finished May 21 12:49:58 PM PDT 24
Peak memory 216968 kb
Host smart-9c84da74-be60-402e-b4c7-5ec532d1a066
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254892157 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.4254892157
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.755754814
Short name T426
Test name
Test status
Simulation time 915604947 ps
CPU time 1.51 seconds
Started May 21 12:39:19 PM PDT 24
Finished May 21 12:39:32 PM PDT 24
Peak memory 197216 kb
Host smart-70463e4c-03a6-4661-861a-83a3981497cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755754814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.755754814
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2677991688
Short name T523
Test name
Test status
Simulation time 80058333277 ps
CPU time 23.62 seconds
Started May 21 12:39:17 PM PDT 24
Finished May 21 12:39:52 PM PDT 24
Peak memory 200400 kb
Host smart-6c1e478b-bc87-4f0e-a92e-95086a7b5ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677991688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2677991688
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3460136528
Short name T833
Test name
Test status
Simulation time 25015355078 ps
CPU time 18.86 seconds
Started May 21 12:42:09 PM PDT 24
Finished May 21 12:42:33 PM PDT 24
Peak memory 200324 kb
Host smart-d162195e-1d56-4db7-9995-c22bc38b80d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460136528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3460136528
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2092245232
Short name T142
Test name
Test status
Simulation time 18253258648 ps
CPU time 30.77 seconds
Started May 21 12:42:06 PM PDT 24
Finished May 21 12:42:39 PM PDT 24
Peak memory 200224 kb
Host smart-60404e5c-0319-430d-8ae9-316a3f92b0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092245232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2092245232
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1623058855
Short name T1168
Test name
Test status
Simulation time 95011629607 ps
CPU time 125.58 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:44:11 PM PDT 24
Peak memory 200540 kb
Host smart-0a6305ca-ed49-4ead-9e27-8b43bd12ed36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623058855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1623058855
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.2841800955
Short name T124
Test name
Test status
Simulation time 66508464606 ps
CPU time 353.56 seconds
Started May 21 12:42:08 PM PDT 24
Finished May 21 12:48:04 PM PDT 24
Peak memory 216884 kb
Host smart-73398122-2557-4c89-a98e-14bcd83636c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841800955 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2841800955
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2356230928
Short name T626
Test name
Test status
Simulation time 125036118025 ps
CPU time 128.47 seconds
Started May 21 12:42:04 PM PDT 24
Finished May 21 12:44:16 PM PDT 24
Peak memory 200448 kb
Host smart-f93d0a77-ee32-47bd-bef6-042f39662561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356230928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2356230928
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3530866296
Short name T37
Test name
Test status
Simulation time 266836199564 ps
CPU time 995.43 seconds
Started May 21 12:42:05 PM PDT 24
Finished May 21 12:58:43 PM PDT 24
Peak memory 216988 kb
Host smart-c346bee7-2c3f-403a-859d-c857aa4d9781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530866296 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3530866296
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1507811533
Short name T842
Test name
Test status
Simulation time 115462249809 ps
CPU time 37.43 seconds
Started May 21 12:42:05 PM PDT 24
Finished May 21 12:42:45 PM PDT 24
Peak memory 200504 kb
Host smart-21cd4d6e-52c7-47af-b1c3-4d2f32131d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507811533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1507811533
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1813182199
Short name T654
Test name
Test status
Simulation time 204673622279 ps
CPU time 307.6 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:47:13 PM PDT 24
Peak memory 210256 kb
Host smart-48a68e07-150a-4981-bf8a-f55ff172c5f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813182199 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1813182199
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3449736437
Short name T776
Test name
Test status
Simulation time 16583240022 ps
CPU time 15.01 seconds
Started May 21 12:42:08 PM PDT 24
Finished May 21 12:42:26 PM PDT 24
Peak memory 198472 kb
Host smart-c0533c12-03be-432a-9a5c-98396de06882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449736437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3449736437
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2115422654
Short name T33
Test name
Test status
Simulation time 50769465380 ps
CPU time 861.02 seconds
Started May 21 12:42:03 PM PDT 24
Finished May 21 12:56:28 PM PDT 24
Peak memory 216984 kb
Host smart-4be0ae4f-ae54-40ba-ae5a-bb29abb3b3ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115422654 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2115422654
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2932193767
Short name T134
Test name
Test status
Simulation time 117429469587 ps
CPU time 192.35 seconds
Started May 21 12:42:03 PM PDT 24
Finished May 21 12:45:19 PM PDT 24
Peak memory 200440 kb
Host smart-20933ef7-931d-4cd1-a44d-6315ed22cf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932193767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2932193767
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1573398073
Short name T1155
Test name
Test status
Simulation time 201254011436 ps
CPU time 58.4 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:43:04 PM PDT 24
Peak memory 200480 kb
Host smart-f6919943-d1b7-4a4f-9ee9-70c97eb2ac41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573398073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1573398073
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.732826409
Short name T823
Test name
Test status
Simulation time 111564720169 ps
CPU time 354.23 seconds
Started May 21 12:42:08 PM PDT 24
Finished May 21 12:48:05 PM PDT 24
Peak memory 211956 kb
Host smart-718449bd-5306-4c99-9638-9b1441f3a41d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732826409 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.732826409
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2649463450
Short name T241
Test name
Test status
Simulation time 152936812500 ps
CPU time 259.75 seconds
Started May 21 12:42:04 PM PDT 24
Finished May 21 12:46:27 PM PDT 24
Peak memory 200500 kb
Host smart-ef851d83-dda1-448a-83a0-3c35bee5dc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649463450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2649463450
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3450051315
Short name T154
Test name
Test status
Simulation time 185468993424 ps
CPU time 462.85 seconds
Started May 21 12:42:05 PM PDT 24
Finished May 21 12:49:50 PM PDT 24
Peak memory 225748 kb
Host smart-5d20b9b8-b304-47e0-a329-24b87335366a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450051315 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3450051315
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.4222205801
Short name T525
Test name
Test status
Simulation time 126909987245 ps
CPU time 60.3 seconds
Started May 21 12:42:02 PM PDT 24
Finished May 21 12:43:06 PM PDT 24
Peak memory 200404 kb
Host smart-e6523dba-fde5-4450-9e58-b1ead2973525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222205801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.4222205801
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3759717464
Short name T287
Test name
Test status
Simulation time 209415265183 ps
CPU time 299.89 seconds
Started May 21 12:42:10 PM PDT 24
Finished May 21 12:47:15 PM PDT 24
Peak memory 216988 kb
Host smart-5b2b8b50-8c64-49b4-91ad-4a89aeea7171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759717464 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3759717464
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.934054723
Short name T796
Test name
Test status
Simulation time 11440482 ps
CPU time 0.55 seconds
Started May 21 12:39:34 PM PDT 24
Finished May 21 12:39:43 PM PDT 24
Peak memory 195776 kb
Host smart-edad94d8-ebbd-4554-90ad-cfad3aa7ba8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934054723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.934054723
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.314372650
Short name T128
Test name
Test status
Simulation time 115259002434 ps
CPU time 181.21 seconds
Started May 21 12:39:37 PM PDT 24
Finished May 21 12:42:48 PM PDT 24
Peak memory 200440 kb
Host smart-2ad29380-e5ba-4a71-9b6d-07f00fc41916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314372650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.314372650
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2540599992
Short name T715
Test name
Test status
Simulation time 145805814994 ps
CPU time 66.55 seconds
Started May 21 12:39:33 PM PDT 24
Finished May 21 12:40:48 PM PDT 24
Peak memory 200472 kb
Host smart-3f1ff365-1a97-409c-ab54-6d6e51f98ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540599992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2540599992
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1797605300
Short name T735
Test name
Test status
Simulation time 66279011777 ps
CPU time 55.25 seconds
Started May 21 12:39:39 PM PDT 24
Finished May 21 12:40:43 PM PDT 24
Peak memory 200556 kb
Host smart-b15d9d95-009f-4bb0-b81c-de2920a940de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797605300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1797605300
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.316334768
Short name T1042
Test name
Test status
Simulation time 14357089060 ps
CPU time 7.03 seconds
Started May 21 12:39:22 PM PDT 24
Finished May 21 12:39:39 PM PDT 24
Peak memory 198596 kb
Host smart-a98b6a5c-bb55-474e-a778-19f3774f2e37
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316334768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.316334768
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1577778068
Short name T467
Test name
Test status
Simulation time 96818026557 ps
CPU time 776.99 seconds
Started May 21 12:39:29 PM PDT 24
Finished May 21 12:52:35 PM PDT 24
Peak memory 200452 kb
Host smart-4d98258c-f86e-4d23-baa9-05ff8c823e6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1577778068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1577778068
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1052759592
Short name T948
Test name
Test status
Simulation time 1027176170 ps
CPU time 1.35 seconds
Started May 21 12:39:43 PM PDT 24
Finished May 21 12:39:54 PM PDT 24
Peak memory 199016 kb
Host smart-c43729b9-f785-4404-aaed-5e7ad337818c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052759592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1052759592
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3081852729
Short name T463
Test name
Test status
Simulation time 18691784068 ps
CPU time 16.65 seconds
Started May 21 12:39:32 PM PDT 24
Finished May 21 12:39:58 PM PDT 24
Peak memory 198612 kb
Host smart-3ca67c33-84f5-404f-ab6f-129f7a5593bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081852729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3081852729
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.318896726
Short name T518
Test name
Test status
Simulation time 21275310585 ps
CPU time 351.77 seconds
Started May 21 12:39:26 PM PDT 24
Finished May 21 12:45:27 PM PDT 24
Peak memory 200424 kb
Host smart-818177ad-dbce-4cf2-9fa1-753226021865
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=318896726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.318896726
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.301409709
Short name T346
Test name
Test status
Simulation time 4622360228 ps
CPU time 46.63 seconds
Started May 21 12:39:27 PM PDT 24
Finished May 21 12:40:22 PM PDT 24
Peak memory 199568 kb
Host smart-68abb836-676d-499a-9295-62b4b8eb152b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=301409709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.301409709
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.635626223
Short name T430
Test name
Test status
Simulation time 21305903191 ps
CPU time 19.12 seconds
Started May 21 12:39:38 PM PDT 24
Finished May 21 12:40:06 PM PDT 24
Peak memory 198692 kb
Host smart-be2a0302-468f-42e2-bbac-de363fecd9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635626223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.635626223
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.627571781
Short name T271
Test name
Test status
Simulation time 29841160384 ps
CPU time 11.08 seconds
Started May 21 12:39:37 PM PDT 24
Finished May 21 12:39:58 PM PDT 24
Peak memory 196496 kb
Host smart-f85966b6-6fa5-43ba-82b7-e3f20c1f792f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627571781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.627571781
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.22583413
Short name T798
Test name
Test status
Simulation time 5866477088 ps
CPU time 17.56 seconds
Started May 21 12:39:24 PM PDT 24
Finished May 21 12:39:51 PM PDT 24
Peak memory 199688 kb
Host smart-24528ce4-1489-490b-9922-4a6599e2ec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22583413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.22583413
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.2480463542
Short name T308
Test name
Test status
Simulation time 286636277288 ps
CPU time 162.55 seconds
Started May 21 12:39:34 PM PDT 24
Finished May 21 12:42:25 PM PDT 24
Peak memory 200712 kb
Host smart-5d69d27d-bcfc-444f-837f-bb70587f8fbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480463542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2480463542
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2842738526
Short name T1154
Test name
Test status
Simulation time 281569702484 ps
CPU time 845.35 seconds
Started May 21 12:39:28 PM PDT 24
Finished May 21 12:53:42 PM PDT 24
Peak memory 225472 kb
Host smart-4a429378-c876-4eea-ab83-a2e4b901afdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842738526 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2842738526
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3665473032
Short name T730
Test name
Test status
Simulation time 1115586322 ps
CPU time 3.22 seconds
Started May 21 12:39:39 PM PDT 24
Finished May 21 12:39:52 PM PDT 24
Peak memory 200316 kb
Host smart-38613bfa-2b7f-43e5-8040-b08a05ffece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665473032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3665473032
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1677362311
Short name T1037
Test name
Test status
Simulation time 5889776681 ps
CPU time 2.73 seconds
Started May 21 12:39:32 PM PDT 24
Finished May 21 12:39:43 PM PDT 24
Peak memory 200220 kb
Host smart-398eb686-b662-438c-b1b2-f15dc9fd1140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677362311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1677362311
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.144410890
Short name T1157
Test name
Test status
Simulation time 133408502456 ps
CPU time 21.66 seconds
Started May 21 12:42:15 PM PDT 24
Finished May 21 12:42:41 PM PDT 24
Peak memory 200364 kb
Host smart-148857a0-6d10-4afb-ba65-9f6319685f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144410890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.144410890
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2508041671
Short name T501
Test name
Test status
Simulation time 50196051927 ps
CPU time 1506.23 seconds
Started May 21 12:42:11 PM PDT 24
Finished May 21 01:07:23 PM PDT 24
Peak memory 216968 kb
Host smart-020e9f25-9672-4a4e-b008-c2c8c2aa7cbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508041671 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2508041671
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3015853339
Short name T440
Test name
Test status
Simulation time 151648728464 ps
CPU time 67.49 seconds
Started May 21 12:42:10 PM PDT 24
Finished May 21 12:43:23 PM PDT 24
Peak memory 200512 kb
Host smart-0e078fbf-f1a0-4b71-b202-9eb19da7d0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015853339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3015853339
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3656496227
Short name T896
Test name
Test status
Simulation time 14339098629 ps
CPU time 170.02 seconds
Started May 21 12:42:08 PM PDT 24
Finished May 21 12:45:02 PM PDT 24
Peak memory 209048 kb
Host smart-4d227033-2317-4c92-9d8f-f7adc66109b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656496227 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3656496227
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3879319914
Short name T729
Test name
Test status
Simulation time 141298811497 ps
CPU time 132.67 seconds
Started May 21 12:42:08 PM PDT 24
Finished May 21 12:44:25 PM PDT 24
Peak memory 200448 kb
Host smart-2d1fa912-0d31-447a-ba19-950be45d76e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879319914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3879319914
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3239934867
Short name T609
Test name
Test status
Simulation time 60539270574 ps
CPU time 443.71 seconds
Started May 21 12:42:11 PM PDT 24
Finished May 21 12:49:40 PM PDT 24
Peak memory 216432 kb
Host smart-29c69cf6-106e-494d-afef-849d7340487f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239934867 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3239934867
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1684293195
Short name T458
Test name
Test status
Simulation time 175010188010 ps
CPU time 91.2 seconds
Started May 21 12:42:08 PM PDT 24
Finished May 21 12:43:43 PM PDT 24
Peak memory 200512 kb
Host smart-3ec277d3-752b-4737-9cbe-453274e1a5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684293195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1684293195
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3507507835
Short name T178
Test name
Test status
Simulation time 11854778318 ps
CPU time 10.77 seconds
Started May 21 12:42:11 PM PDT 24
Finished May 21 12:42:27 PM PDT 24
Peak memory 200468 kb
Host smart-1926ef03-9ce7-42ff-b7ef-a8a12457c7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507507835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3507507835
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.169833226
Short name T233
Test name
Test status
Simulation time 17185152820 ps
CPU time 31.23 seconds
Started May 21 12:42:10 PM PDT 24
Finished May 21 12:42:45 PM PDT 24
Peak memory 200420 kb
Host smart-7374d509-2632-47ae-a72b-0e0b1f2b5bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169833226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.169833226
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3981580857
Short name T1130
Test name
Test status
Simulation time 173541789448 ps
CPU time 508.3 seconds
Started May 21 12:42:09 PM PDT 24
Finished May 21 12:50:40 PM PDT 24
Peak memory 216948 kb
Host smart-2c79d386-4df8-4569-b086-f4ed89256c4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981580857 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3981580857
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1564397925
Short name T872
Test name
Test status
Simulation time 196237699384 ps
CPU time 408.36 seconds
Started May 21 12:42:10 PM PDT 24
Finished May 21 12:49:02 PM PDT 24
Peak memory 200384 kb
Host smart-fae55c7a-1300-49b8-907b-9dcde2ac3769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564397925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1564397925
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1139687731
Short name T268
Test name
Test status
Simulation time 17822004379 ps
CPU time 266.7 seconds
Started May 21 12:42:09 PM PDT 24
Finished May 21 12:46:40 PM PDT 24
Peak memory 216856 kb
Host smart-7abd574c-0a51-421f-bff6-b1a7fe155bd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139687731 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1139687731
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.4287791886
Short name T936
Test name
Test status
Simulation time 40860434723 ps
CPU time 18.2 seconds
Started May 21 12:42:11 PM PDT 24
Finished May 21 12:42:35 PM PDT 24
Peak memory 200484 kb
Host smart-dd448f4c-7159-4eb5-a384-45b72e55d38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287791886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.4287791886
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.853343603
Short name T1159
Test name
Test status
Simulation time 914868893211 ps
CPU time 1183.36 seconds
Started May 21 12:42:09 PM PDT 24
Finished May 21 01:01:57 PM PDT 24
Peak memory 233552 kb
Host smart-c1655d86-e7a4-44dc-be4b-c0288d4e1d3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853343603 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.853343603
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%