Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	118244	1			T1	2		T2	45		T3	1
all_values[1]	118244	1			T1	2		T2	45		T3	1
all_values[2]	118244	1			T1	2		T2	45		T3	1
all_values[3]	118244	1			T1	2		T2	45		T3	1
all_values[4]	118244	1			T1	2		T2	45		T3	1
all_values[5]	118244	1			T1	2		T2	45		T3	1
all_values[6]	118244	1			T1	2		T2	45		T3	1
all_values[7]	118244	1			T1	2		T2	45		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

479408

1

T1

16

T2

194

T3

4

auto[1]

466544

1

T2

166

T3

4

T4

44

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

885965

1

T1

13

T2

309

T3

7

auto[1]

59987

1

T1

3

T2

51

T3

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	35760	1			T2	19		T5	5		T8	18
all_values[0]	auto[0]	auto[1]	22551	1			T1	2		T2	7		T3	1
all_values[0]	auto[1]	auto[0]	34023	1			T2	4		T4	3		T5	14
all_values[0]	auto[1]	auto[1]	25910	1			T2	15		T4	3		T5	25
all_values[1]	auto[0]	auto[0]	58337	1			T1	2		T2	24		T4	14
all_values[1]	auto[0]	auto[1]	1607	1			T2	1		T4	1		T7	6
all_values[1]	auto[1]	auto[0]	56616	1			T2	17		T3	1		T5	49
all_values[1]	auto[1]	auto[1]	1684	1			T2	3		T11	1		T13	23
all_values[2]	auto[0]	auto[0]	57057	1			T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	2813	1			T1	1		T2	1		T4	2
all_values[2]	auto[1]	auto[0]	55819	1			T2	35		T5	24		T8	31
all_values[2]	auto[1]	auto[1]	2555	1			T2	7		T5	8		T8	1
all_values[3]	auto[0]	auto[0]	62454	1			T1	2		T2	27		T4	9
all_values[3]	auto[0]	auto[1]	285	1			T2	1		T14	1		T16	1
all_values[3]	auto[1]	auto[0]	55173	1			T2	13		T3	1		T4	6
all_values[3]	auto[1]	auto[1]	332	1			T2	4		T13	2		T17	3
all_values[4]	auto[0]	auto[0]	59383	1			T1	2		T2	11		T3	1
all_values[4]	auto[0]	auto[1]	504	1			T16	3		T17	3		T31	1
all_values[4]	auto[1]	auto[0]	57986	1			T2	34		T4	10		T5	35
all_values[4]	auto[1]	auto[1]	371	1			T16	1		T17	5		T21	5
all_values[5]	auto[0]	auto[0]	56924	1			T1	2		T2	40		T4	4
all_values[5]	auto[0]	auto[1]	170	1			T16	1		T17	6		T31	2
all_values[5]	auto[1]	auto[0]	60959	1			T2	3		T3	1		T4	11
all_values[5]	auto[1]	auto[1]	191	1			T2	2		T16	2		T17	2
all_values[6]	auto[0]	auto[0]	61278	1			T1	2		T2	14		T4	10
all_values[6]	auto[0]	auto[1]	206	1			T2	5		T17	3		T125	2
all_values[6]	auto[1]	auto[0]	56599	1			T2	26		T3	1		T4	5
all_values[6]	auto[1]	auto[1]	161	1			T17	2		T31	1		T33	1
all_values[7]	auto[0]	auto[0]	59746	1			T1	2		T2	39		T3	1
all_values[7]	auto[0]	auto[1]	333	1			T2	3		T11	6		T18	3
all_values[7]	auto[1]	auto[0]	57851	1			T2	1		T4	6		T5	19
all_values[7]	auto[1]	auto[1]	314	1			T2	2		T16	3		T17	6