Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2584

1

T1

1

T2

2

T3

1

auto[UartRx]

2584

1

T1

1

T2

2

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4550	1			T1	2		T2	4		T3	2
values[1]	49	1			T8	1		T30	2		T31	2
values[2]	55	1			T4	1		T12	1		T17	1
values[3]	57	1			T24	1		T30	2		T32	1
values[4]	63	1			T16	1		T30	1		T32	1
values[5]	47	1			T16	1		T30	1		T17	3
values[6]	49	1			T4	1		T12	1		T16	3
values[7]	71	1			T4	1		T12	1		T24	1
values[8]	77	1			T24	2		T16	1		T30	1
values[9]	51	1			T16	1		T30	1		T17	1
values[10]	68	1			T8	1		T30	2		T17	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2373	1			T1	1		T2	2		T3	1
auto[UartTx]	values[1]	17	1			T30	1		T31	1		T32	1
auto[UartTx]	values[2]	22	1			T4	1		T17	1		T125	1
auto[UartTx]	values[3]	22	1			T30	1		T125	1		T111	1
auto[UartTx]	values[4]	21	1			T32	1		T51	1		T336	1
auto[UartTx]	values[5]	15	1			T30	1		T17	2		T109	1
auto[UartTx]	values[6]	14	1			T108	1		T293	1		T169	1
auto[UartTx]	values[7]	22	1			T4	1		T12	1		T31	1
auto[UartTx]	values[8]	31	1			T24	2		T17	1		T129	2
auto[UartTx]	values[9]	17	1			T17	1		T32	1		T129	1
auto[UartTx]	values[10]	22	1			T17	1		T125	1		T323	1
auto[UartRx]	values[0]	2177	1			T1	1		T2	2		T3	1
auto[UartRx]	values[1]	32	1			T8	1		T30	1		T31	1
auto[UartRx]	values[2]	33	1			T12	1		T125	1		T162	1
auto[UartRx]	values[3]	35	1			T24	1		T30	1		T32	1
auto[UartRx]	values[4]	42	1			T16	1		T30	1		T109	1
auto[UartRx]	values[5]	32	1			T16	1		T17	1		T31	1
auto[UartRx]	values[6]	35	1			T4	1		T12	1		T16	3
auto[UartRx]	values[7]	49	1			T24	1		T16	1		T31	1
auto[UartRx]	values[8]	46	1			T16	1		T30	1		T17	1
auto[UartRx]	values[9]	34	1			T16	1		T30	1		T32	1
auto[UartRx]	values[10]	46	1			T8	1		T30	2		T33	1