Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2456	1			T3	13		T4	1		T5	5
auto[BaudRate115200]	1921	1			T5	2		T7	2		T8	12
auto[BaudRate230400]	1949	1			T4	2		T5	3		T7	1
auto[BaudRate128Kbps]	1947	1			T1	1		T4	2		T5	1
auto[BaudRate256Kbps]	2089	1			T4	3		T5	3		T7	1
auto[BaudRate1Mbps]	1823	1			T2	3		T4	1		T5	1
auto[BaudRate1p5Mbps]	1339	1			T1	1		T2	4		T4	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1259	1			T3	13		T8	100		T34	2
freqs[25]	1181	1			T285	2		T41	9		T22	4
freqs[48]	615	1			T44	17		T295	2		T337	19
freqs[50]	599	1			T13	10		T19	2		T200	7
freqs[100]	1150	1			T9	8		T126	9		T37	8

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	238	1			T3	13		T8	9		T34	1
auto[BaudRate9600]	freqs[25]	201	1			T41	3		T23	1		T338	3
auto[BaudRate9600]	freqs[48]	120	1			T44	2		T337	19		T210	2
auto[BaudRate9600]	freqs[50]	74	1			T13	2		T200	1		T339	1
auto[BaudRate9600]	freqs[100]	172	1			T9	1		T126	3		T37	2
auto[BaudRate115200]	freqs[24]	157	1			T8	12		T125	18		T318	1
auto[BaudRate115200]	freqs[25]	174	1			T41	1		T22	2		T306	1
auto[BaudRate115200]	freqs[48]	55	1			T44	2		T134	1		T156	1
auto[BaudRate115200]	freqs[50]	96	1			T200	1		T145	1		T339	1
auto[BaudRate115200]	freqs[100]	143	1			T9	3		T37	1		T16	3
auto[BaudRate230400]	freqs[24]	180	1			T8	19		T15	1		T258	2
auto[BaudRate230400]	freqs[25]	166	1			T41	2		T306	1		T23	1
auto[BaudRate230400]	freqs[48]	82	1			T44	1		T295	1		T155	4
auto[BaudRate230400]	freqs[50]	90	1			T13	2		T200	3		T145	4
auto[BaudRate230400]	freqs[100]	174	1			T126	2		T37	1		T16	9
auto[BaudRate128Kbps]	freqs[24]	202	1			T8	19		T15	1		T258	1
auto[BaudRate128Kbps]	freqs[25]	178	1			T41	2		T22	2		T306	2
auto[BaudRate128Kbps]	freqs[48]	75	1			T44	1		T134	3		T210	1
auto[BaudRate128Kbps]	freqs[50]	83	1			T200	2		T145	1		T339	1
auto[BaudRate128Kbps]	freqs[100]	167	1			T126	2		T37	1		T16	1
auto[BaudRate256Kbps]	freqs[24]	189	1			T8	17		T15	2		T125	28
auto[BaudRate256Kbps]	freqs[25]	184	1			T285	1		T41	1		T272	3
auto[BaudRate256Kbps]	freqs[48]	98	1			T44	2		T134	2		T155	3
auto[BaudRate256Kbps]	freqs[50]	101	1			T19	1		T145	3		T339	4
auto[BaudRate256Kbps]	freqs[100]	186	1			T9	2		T37	1		T16	2
auto[BaudRate1Mbps]	freqs[24]	185	1			T8	16		T34	1		T15	1
auto[BaudRate1Mbps]	freqs[25]	189	1			T272	2		T306	3		T296	1
auto[BaudRate1Mbps]	freqs[48]	105	1			T44	5		T295	1		T134	1
auto[BaudRate1Mbps]	freqs[50]	89	1			T13	4		T19	1		T339	4
auto[BaudRate1Mbps]	freqs[100]	151	1			T9	1		T126	1		T37	2
auto[BaudRate1p5Mbps]	freqs[25]	89	1			T285	1		T272	2		T306	1
auto[BaudRate1p5Mbps]	freqs[48]	80	1			T44	4		T134	1		T156	1
auto[BaudRate1p5Mbps]	freqs[50]	66	1			T13	2		T339	2		T340	2
auto[BaudRate1p5Mbps]	freqs[100]	157	1			T9	1		T126	1		T16	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded