Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.46	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	5	125	96.15

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	5	125	96.15	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	34434624	1			T2	68181		T3	1		T4	20
all_levels[1]	187108	1			T2	1695		T5	87		T7	3
all_levels[2]	2612	1			T5	8		T8	17		T9	4
all_levels[3]	1055	1			T5	2		T8	1		T9	4
all_levels[4]	752	1			T5	1		T8	4		T9	1
all_levels[5]	550	1			T8	1		T9	2		T35	1
all_levels[6]	415	1			T8	1		T9	2		T36	1
all_levels[7]	339	1			T7	1		T9	4		T11	2
all_levels[8]	301	1			T9	1		T36	1		T126	1
all_levels[9]	261	1			T8	1		T36	1		T127	1
all_levels[10]	199	1			T11	2		T13	1		T18	3
all_levels[11]	184	1			T5	1		T11	1		T35	1
all_levels[12]	157	1			T5	1		T13	1		T35	1
all_levels[13]	170	1			T126	1		T37	1		T127	1
all_levels[14]	105	1			T127	1		T16	1		T17	1
all_levels[15]	106	1			T37	3		T16	1		T128	3
all_levels[16]	107	1			T11	1		T125	1		T109	1
all_levels[17]	89	1			T7	1		T18	1		T35	1
all_levels[18]	100	1			T37	1		T15	1		T21	1
all_levels[19]	104	1			T7	1		T8	1		T35	1
all_levels[20]	82	1			T128	1		T109	2		T129	1
all_levels[21]	87	1			T45	1		T21	1		T117	2
all_levels[22]	62	1			T35	1		T130	1		T128	1
all_levels[23]	60	1			T35	2		T125	1		T131	1
all_levels[24]	59	1			T13	3		T131	1		T132	1
all_levels[25]	45	1			T18	1		T129	2		T133	1
all_levels[26]	64	1			T14	4		T125	4		T129	1
all_levels[27]	50	1			T14	1		T37	1		T116	1
all_levels[28]	38	1			T18	1		T116	1		T134	1
all_levels[29]	34	1			T135	1		T136	1		T137	1
all_levels[30]	55	1			T11	1		T132	1		T138	2
all_levels[31]	40	1			T17	1		T108	1		T132	1
all_levels[32]	36	1			T14	1		T139	1		T129	1
all_levels[33]	29	1			T129	2		T140	2		T141	1
all_levels[34]	24	1			T11	1		T140	1		T142	1
all_levels[35]	28	1			T129	1		T143	1		T144	1
all_levels[36]	20	1			T129	1		T110	1		T145	1
all_levels[37]	26	1			T128	2		T146	1		T145	1
all_levels[38]	21	1			T13	1		T147	1		T148	1
all_levels[39]	20	1			T14	1		T149	3		T150	1
all_levels[40]	15	1			T151	1		T152	1		T51	1
all_levels[41]	19	1			T147	2		T143	1		T51	1
all_levels[42]	19	1			T47	1		T117	2		T147	1
all_levels[43]	17	1			T129	1		T153	1		T154	1
all_levels[44]	18	1			T42	1		T155	1		T156	3
all_levels[45]	16	1			T145	1		T148	1		T157	5
all_levels[46]	18	1			T35	1		T158	1		T119	3
all_levels[47]	19	1			T33	1		T132	1		T141	1
all_levels[48]	17	1			T42	3		T138	1		T146	1
all_levels[49]	13	1			T140	1		T159	1		T160	2
all_levels[50]	11	1			T161	1		T146	1		T150	3
all_levels[51]	20	1			T162	2		T153	1		T155	1
all_levels[52]	9	1			T146	1		T163	1		T164	1
all_levels[53]	16	1			T147	1		T148	1		T165	1
all_levels[54]	12	1			T166	5		T139	1		T167	1
all_levels[55]	8	1			T167	1		T163	1		T168	1
all_levels[56]	12	1			T32	1		T131	2		T150	1
all_levels[57]	12	1			T14	2		T118	2		T169	1
all_levels[58]	7	1			T170	1		T171	2		T172	1
all_levels[59]	17	1			T159	1		T173	1		T167	1
all_levels[60]	9	1			T159	1		T168	1		T174	1
all_levels[61]	14	1			T138	2		T175	1		T176	1
all_levels[62]	8	1			T177	1		T178	1		T179	1
all_levels[63]	12	1			T42	1		T159	1		T180	3
all_levels[64]	113	1			T13	1		T14	1		T15	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34626079

1

T2

69876

T4

18

T5

656

auto[1]

4590

1

T3

1

T4

2

T7

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	5	125	96.15	5

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[36]]	[auto[1]]	0	1	1
[all_levels[52] , all_levels[53]]	[auto[1]]	--	--	2
[all_levels[55]]	[auto[1]]	0	1	1
[all_levels[60]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	34430535	1			T2	68181		T4	18		T5	556
all_levels[0]	auto[1]	4089	1			T3	1		T4	2		T7	3
all_levels[1]	auto[0]	187022	1			T2	1695		T5	87		T7	1
all_levels[1]	auto[1]	86	1			T7	2		T126	1		T37	2
all_levels[2]	auto[0]	2587	1			T5	8		T8	17		T9	4
all_levels[2]	auto[1]	25	1			T15	1		T134	1		T181	1
all_levels[3]	auto[0]	1043	1			T5	2		T8	1		T9	4
all_levels[3]	auto[1]	12	1			T21	1		T155	2		T182	2
all_levels[4]	auto[0]	723	1			T5	1		T8	4		T9	1
all_levels[4]	auto[1]	29	1			T183	1		T184	4		T133	1
all_levels[5]	auto[0]	526	1			T8	1		T9	2		T35	1
all_levels[5]	auto[1]	24	1			T116	3		T131	2		T185	1
all_levels[6]	auto[0]	410	1			T8	1		T9	2		T36	1
all_levels[6]	auto[1]	5	1			T134	1		T186	1		T187	1
all_levels[7]	auto[0]	317	1			T7	1		T9	4		T11	2
all_levels[7]	auto[1]	22	1			T161	3		T188	1		T189	2
all_levels[8]	auto[0]	289	1			T9	1		T36	1		T126	1
all_levels[8]	auto[1]	12	1			T190	1		T191	2		T192	1
all_levels[9]	auto[0]	235	1			T8	1		T36	1		T127	1
all_levels[9]	auto[1]	26	1			T193	2		T194	1		T175	1
all_levels[10]	auto[0]	186	1			T11	2		T13	1		T18	3
all_levels[10]	auto[1]	13	1			T37	1		T149	1		T105	1
all_levels[11]	auto[0]	174	1			T5	1		T11	1		T35	1
all_levels[11]	auto[1]	10	1			T195	1		T196	3		T197	2
all_levels[12]	auto[0]	148	1			T5	1		T13	1		T35	1
all_levels[12]	auto[1]	9	1			T116	1		T198	1		T66	1
all_levels[13]	auto[0]	154	1			T126	1		T37	1		T127	1
all_levels[13]	auto[1]	16	1			T134	1		T199	1		T186	2
all_levels[14]	auto[0]	96	1			T127	1		T16	1		T17	1
all_levels[14]	auto[1]	9	1			T200	1		T201	1		T202	3
all_levels[15]	auto[0]	101	1			T37	2		T16	1		T128	3
all_levels[15]	auto[1]	5	1			T37	1		T203	1		T204	1
all_levels[16]	auto[0]	100	1			T11	1		T125	1		T109	1
all_levels[16]	auto[1]	7	1			T205	1		T180	1		T203	1
all_levels[17]	auto[0]	85	1			T7	1		T18	1		T35	1
all_levels[17]	auto[1]	4	1			T180	2		T206	2		-	-
all_levels[18]	auto[0]	95	1			T37	1		T15	1		T21	1
all_levels[18]	auto[1]	5	1			T207	1		T208	2		T209	1
all_levels[19]	auto[0]	92	1			T7	1		T8	1		T35	1
all_levels[19]	auto[1]	12	1			T210	1		T211	1		T136	1
all_levels[20]	auto[0]	67	1			T128	1		T109	1		T129	1
all_levels[20]	auto[1]	15	1			T109	1		T212	1		T213	2
all_levels[21]	auto[0]	78	1			T45	1		T21	1		T117	1
all_levels[21]	auto[1]	9	1			T117	1		T134	1		T214	3
all_levels[22]	auto[0]	61	1			T35	1		T130	1		T128	1
all_levels[22]	auto[1]	1	1			T215	1		-	-		-	-
all_levels[23]	auto[0]	51	1			T35	1		T125	1		T131	1
all_levels[23]	auto[1]	9	1			T35	1		T147	1		T216	1
all_levels[24]	auto[0]	53	1			T13	1		T131	1		T132	1
all_levels[24]	auto[1]	6	1			T13	2		T201	1		T217	1
all_levels[25]	auto[0]	41	1			T18	1		T129	2		T133	1
all_levels[25]	auto[1]	4	1			T218	1		T219	1		T220	2
all_levels[26]	auto[0]	52	1			T14	1		T125	2		T129	1
all_levels[26]	auto[1]	12	1			T14	3		T125	2		T221	2
all_levels[27]	auto[0]	42	1			T14	1		T37	1		T116	1
all_levels[27]	auto[1]	8	1			T222	1		T177	1		T223	3
all_levels[28]	auto[0]	33	1			T18	1		T116	1		T134	1
all_levels[28]	auto[1]	5	1			T224	4		T168	1		-	-
all_levels[29]	auto[0]	30	1			T135	1		T136	1		T137	1
all_levels[29]	auto[1]	4	1			T225	1		T226	1		T227	2
all_levels[30]	auto[0]	47	1			T11	1		T132	1		T138	1
all_levels[30]	auto[1]	8	1			T138	1		T205	1		T228	3
all_levels[31]	auto[0]	34	1			T17	1		T108	1		T132	1
all_levels[31]	auto[1]	6	1			T229	2		T230	1		T231	2
all_levels[32]	auto[0]	33	1			T14	1		T139	1		T129	1
all_levels[32]	auto[1]	3	1			T232	1		T233	1		T234	1
all_levels[33]	auto[0]	28	1			T129	2		T140	1		T141	1
all_levels[33]	auto[1]	1	1			T140	1		-	-		-	-
all_levels[34]	auto[0]	23	1			T11	1		T140	1		T142	1
all_levels[34]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[35]	auto[0]	23	1			T129	1		T143	1		T144	1
all_levels[35]	auto[1]	5	1			T236	3		T237	1		T238	1
all_levels[36]	auto[0]	20	1			T129	1		T110	1		T145	1
all_levels[37]	auto[0]	23	1			T128	1		T146	1		T145	1
all_levels[37]	auto[1]	3	1			T128	1		T239	1		T240	1
all_levels[38]	auto[0]	18	1			T13	1		T147	1		T148	1
all_levels[38]	auto[1]	3	1			T241	1		T242	1		T243	1
all_levels[39]	auto[0]	18	1			T14	1		T149	2		T150	1
all_levels[39]	auto[1]	2	1			T149	1		T244	1		-	-
all_levels[40]	auto[0]	14	1			T151	1		T152	1		T51	1
all_levels[40]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[41]	auto[0]	16	1			T147	2		T143	1		T51	1
all_levels[41]	auto[1]	3	1			T68	2		T246	1		-	-
all_levels[42]	auto[0]	15	1			T47	1		T117	1		T147	1
all_levels[42]	auto[1]	4	1			T117	1		T247	1		T248	2
all_levels[43]	auto[0]	15	1			T129	1		T153	1		T154	1
all_levels[43]	auto[1]	2	1			T249	2		-	-		-	-
all_levels[44]	auto[0]	16	1			T42	1		T155	1		T156	1
all_levels[44]	auto[1]	2	1			T156	2		-	-		-	-
all_levels[45]	auto[0]	13	1			T145	1		T148	1		T157	2
all_levels[45]	auto[1]	3	1			T157	3		-	-		-	-
all_levels[46]	auto[0]	14	1			T35	1		T158	1		T119	1
all_levels[46]	auto[1]	4	1			T119	2		T250	2		-	-
all_levels[47]	auto[0]	16	1			T33	1		T132	1		T141	1
all_levels[47]	auto[1]	3	1			T68	2		T177	1		-	-
all_levels[48]	auto[0]	16	1			T42	2		T138	1		T146	1
all_levels[48]	auto[1]	1	1			T42	1		-	-		-	-
all_levels[49]	auto[0]	12	1			T140	1		T159	1		T160	1
all_levels[49]	auto[1]	1	1			T160	1		-	-		-	-
all_levels[50]	auto[0]	9	1			T161	1		T146	1		T150	1
all_levels[50]	auto[1]	2	1			T150	2		-	-		-	-
all_levels[51]	auto[0]	16	1			T162	1		T153	1		T155	1
all_levels[51]	auto[1]	4	1			T162	1		T232	2		T251	1
all_levels[52]	auto[0]	9	1			T146	1		T163	1		T164	1
all_levels[53]	auto[0]	16	1			T147	1		T148	1		T165	1
all_levels[54]	auto[0]	8	1			T166	1		T139	1		T167	1
all_levels[54]	auto[1]	4	1			T166	4		-	-		-	-
all_levels[55]	auto[0]	8	1			T167	1		T163	1		T168	1
all_levels[56]	auto[0]	11	1			T32	1		T131	1		T150	1
all_levels[56]	auto[1]	1	1			T131	1		-	-		-	-
all_levels[57]	auto[0]	9	1			T14	1		T118	1		T169	1
all_levels[57]	auto[1]	3	1			T14	1		T118	1		T252	1
all_levels[58]	auto[0]	6	1			T170	1		T171	1		T172	1
all_levels[58]	auto[1]	1	1			T171	1		-	-		-	-
all_levels[59]	auto[0]	16	1			T159	1		T173	1		T167	1
all_levels[59]	auto[1]	1	1			T253	1		-	-		-	-
all_levels[60]	auto[0]	9	1			T159	1		T168	1		T174	1
all_levels[61]	auto[0]	11	1			T138	1		T175	1		T176	1
all_levels[61]	auto[1]	3	1			T138	1		T254	1		T255	1
all_levels[62]	auto[0]	7	1			T177	1		T178	1		T179	1
all_levels[62]	auto[1]	1	1			T256	1		-	-		-	-
all_levels[63]	auto[0]	10	1			T42	1		T159	1		T180	1
all_levels[63]	auto[1]	2	1			T180	2		-	-		-	-
all_levels[64]	auto[0]	94	1			T13	1		T14	1		T15	1
all_levels[64]	auto[1]	19	1			T15	1		T257	1		T207	3