Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	118244	1			T1	2		T2	45		T3	1
all_pins[1]	118244	1			T1	2		T2	45		T3	1
all_pins[2]	118244	1			T1	2		T2	45		T3	1
all_pins[3]	118244	1			T1	2		T2	45		T3	1
all_pins[4]	118244	1			T1	2		T2	45		T3	1
all_pins[5]	118244	1			T1	2		T2	45		T3	1
all_pins[6]	118244	1			T1	2		T2	45		T3	1
all_pins[7]	118244	1			T1	2		T2	45		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	913555	1			T1	16		T2	327		T3	8
values[0x1]	32397	1			T2	33		T4	3		T5	33
transitions[0x0=>0x1]	31218	1			T2	28		T4	3		T5	33
transitions[0x1=>0x0]	30784	1			T2	27		T4	3		T5	33

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	92266	1			T1	2		T2	30		T3	1
all_pins[0]	values[0x1]	25978	1			T2	15		T4	3		T5	25
all_pins[0]	transitions[0x0=>0x1]	25339	1			T2	13		T4	3		T5	25
all_pins[0]	transitions[0x1=>0x0]	1042	1			T2	1		T11	1		T14	3
all_pins[1]	values[0x0]	116563	1			T1	2		T2	42		T3	1
all_pins[1]	values[0x1]	1681	1			T2	3		T11	1		T13	23
all_pins[1]	transitions[0x0=>0x1]	1545	1			T2	2		T13	23		T14	2
all_pins[1]	transitions[0x1=>0x0]	2462	1			T2	6		T5	8		T8	1
all_pins[2]	values[0x0]	115646	1			T1	2		T2	38		T3	1
all_pins[2]	values[0x1]	2598	1			T2	7		T5	8		T8	1
all_pins[2]	transitions[0x0=>0x1]	2531	1			T2	6		T5	8		T8	1
all_pins[2]	transitions[0x1=>0x0]	265	1			T2	3		T17	3		T258	2
all_pins[3]	values[0x0]	117912	1			T1	2		T2	41		T3	1
all_pins[3]	values[0x1]	332	1			T2	4		T13	2		T17	3
all_pins[3]	transitions[0x0=>0x1]	293	1			T2	4		T13	2		T17	2
all_pins[3]	transitions[0x1=>0x0]	332	1			T16	1		T17	4		T21	5
all_pins[4]	values[0x0]	117873	1			T1	2		T2	45		T3	1
all_pins[4]	values[0x1]	371	1			T16	1		T17	5		T21	5
all_pins[4]	transitions[0x0=>0x1]	311	1			T16	1		T17	3		T21	4
all_pins[4]	transitions[0x1=>0x0]	181	1			T2	2		T16	2		T31	1
all_pins[5]	values[0x0]	118003	1			T1	2		T2	43		T3	1
all_pins[5]	values[0x1]	241	1			T2	2		T16	2		T17	2
all_pins[5]	transitions[0x0=>0x1]	194	1			T2	2		T16	2		T17	2
all_pins[5]	transitions[0x1=>0x0]	835	1			T7	2		T8	3		T13	3
all_pins[6]	values[0x0]	117362	1			T1	2		T2	45		T3	1
all_pins[6]	values[0x1]	882	1			T7	2		T8	3		T13	3
all_pins[6]	transitions[0x0=>0x1]	837	1			T7	2		T8	3		T13	3
all_pins[6]	transitions[0x1=>0x0]	269	1			T2	2		T16	3		T17	4
all_pins[7]	values[0x0]	117930	1			T1	2		T2	43		T3	1
all_pins[7]	values[0x1]	314	1			T2	2		T16	3		T17	6
all_pins[7]	transitions[0x0=>0x1]	168	1			T2	1		T16	2		T17	3
all_pins[7]	transitions[0x1=>0x0]	25398	1			T2	13		T4	3		T5	25