Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8933413	1			T2	12879		T4	8		T5	265
all_levels[1]	2111175	1			T2	66		T4	4		T5	23
all_levels[2]	530157	1			T2	55		T4	4		T5	22
all_levels[3]	375971	1			T2	59		T4	1		T5	29
all_levels[4]	264885	1			T2	68		T5	19		T8	31
all_levels[5]	301770	1			T2	68		T5	109		T8	29
all_levels[6]	345924	1			T2	56		T5	95		T8	31
all_levels[7]	289749	1			T2	59		T5	7		T8	24
all_levels[8]	345859	1			T2	70		T5	2		T8	35
all_levels[9]	221929	1			T2	55		T5	6		T8	28
all_levels[10]	408701	1			T2	64		T5	10		T8	18
all_levels[11]	309897	1			T2	50		T5	2		T8	19
all_levels[12]	215074	1			T2	64		T4	3		T8	18
all_levels[13]	290159	1			T2	57		T5	1		T8	17
all_levels[14]	221023	1			T2	56		T8	20		T9	1
all_levels[15]	258500	1			T2	60		T8	21		T9	226
all_levels[16]	280971	1			T2	52		T5	56		T8	30
all_levels[17]	525555	1			T2	68		T8	28		T9	19
all_levels[18]	209352	1			T2	56		T5	11		T8	23
all_levels[19]	246504	1			T2	55		T8	26		T9	2
all_levels[20]	208864	1			T2	47		T8	30		T10	495
all_levels[21]	322308	1			T2	63		T8	26		T10	495
all_levels[22]	233786	1			T2	66		T8	23		T10	493
all_levels[23]	213184	1			T2	66		T8	28		T9	1
all_levels[24]	256753	1			T2	63		T8	21		T10	495
all_levels[25]	253487	1			T2	51		T8	33		T9	1
all_levels[26]	248836	1			T2	69		T8	20		T10	479
all_levels[27]	225396	1			T2	74		T7	5		T8	23
all_levels[28]	198548	1			T2	45		T8	23		T9	2
all_levels[29]	315373	1			T2	55		T7	3		T8	19
all_levels[30]	216227	1			T2	58		T8	28		T10	493
all_levels[31]	609922	1			T2	2923		T8	361		T9	2
all_levels[32]	14641078	1			T2	52280		T7	5		T8	8669

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34626079

1

T2

69876

T4

18

T5

656

auto[1]

4251

1

T2

1

T4

2

T5

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8931213	1			T2	12879		T4	8		T5	265
all_levels[0]	auto[1]	2200	1			T13	6		T14	4		T35	5
all_levels[1]	auto[0]	2110722	1			T2	66		T4	4		T5	23
all_levels[1]	auto[1]	453	1			T13	1		T14	2		T37	3
all_levels[2]	auto[0]	530104	1			T2	55		T4	4		T5	22
all_levels[2]	auto[1]	53	1			T47	2		T184	6		T147	1
all_levels[3]	auto[0]	375776	1			T2	59		T4	1		T5	29
all_levels[3]	auto[1]	195	1			T108	21		T23	4		T286	1
all_levels[4]	auto[0]	264854	1			T2	68		T5	19		T8	31
all_levels[4]	auto[1]	31	1			T134	1		T158	1		T147	1
all_levels[5]	auto[0]	301735	1			T2	68		T5	109		T8	29
all_levels[5]	auto[1]	35	1			T37	1		T166	1		T128	1
all_levels[6]	auto[0]	345896	1			T2	56		T5	95		T8	31
all_levels[6]	auto[1]	28	1			T126	1		T284	1		T344	1
all_levels[7]	auto[0]	289641	1			T2	59		T5	7		T8	24
all_levels[7]	auto[1]	108	1			T139	1		T211	5		T189	1
all_levels[8]	auto[0]	345830	1			T2	70		T5	2		T8	35
all_levels[8]	auto[1]	29	1			T207	1		T150	1		T334	1
all_levels[9]	auto[0]	221897	1			T2	55		T5	6		T8	28
all_levels[9]	auto[1]	32	1			T45	1		T21	2		T140	2
all_levels[10]	auto[0]	408669	1			T2	64		T5	10		T8	18
all_levels[10]	auto[1]	32	1			T166	1		T289	2		T191	2
all_levels[11]	auto[0]	309875	1			T2	50		T5	2		T8	19
all_levels[11]	auto[1]	22	1			T9	1		T39	1		T257	2
all_levels[12]	auto[0]	215040	1			T2	64		T4	1		T8	18
all_levels[12]	auto[1]	34	1			T4	2		T116	3		T128	1
all_levels[13]	auto[0]	290139	1			T2	57		T5	1		T8	17
all_levels[13]	auto[1]	20	1			T45	1		T322	1		T299	1
all_levels[14]	auto[0]	221003	1			T2	56		T8	20		T9	1
all_levels[14]	auto[1]	20	1			T158	1		T200	1		T274	1
all_levels[15]	auto[0]	258372	1			T2	60		T8	21		T9	226
all_levels[15]	auto[1]	128	1			T126	1		T316	8		T115	1
all_levels[16]	auto[0]	280950	1			T2	52		T5	56		T8	30
all_levels[16]	auto[1]	21	1			T134	2		T147	1		T303	1
all_levels[17]	auto[0]	525527	1			T2	68		T8	28		T9	19
all_levels[17]	auto[1]	28	1			T10	1		T13	1		T126	1
all_levels[18]	auto[0]	209333	1			T2	56		T5	10		T8	23
all_levels[18]	auto[1]	19	1			T5	1		T13	1		T127	1
all_levels[19]	auto[0]	246479	1			T2	55		T8	26		T9	2
all_levels[19]	auto[1]	25	1			T345	4		T186	2		T185	2
all_levels[20]	auto[0]	208846	1			T2	47		T8	30		T10	495
all_levels[20]	auto[1]	18	1			T35	1		T127	1		T130	1
all_levels[21]	auto[0]	322288	1			T2	63		T8	26		T10	495
all_levels[21]	auto[1]	20	1			T326	1		T142	2		T346	1
all_levels[22]	auto[0]	233761	1			T2	66		T8	23		T10	493
all_levels[22]	auto[1]	25	1			T35	1		T41	1		T131	2
all_levels[23]	auto[0]	213163	1			T2	66		T8	28		T9	1
all_levels[23]	auto[1]	21	1			T138	1		T180	1		T347	3
all_levels[24]	auto[0]	256737	1			T2	63		T8	21		T10	495
all_levels[24]	auto[1]	16	1			T31	1		T162	1		T348	1
all_levels[25]	auto[0]	253480	1			T2	51		T8	33		T9	1
all_levels[25]	auto[1]	7	1			T116	2		T349	2		T350	1
all_levels[26]	auto[0]	248817	1			T2	69		T8	20		T10	479
all_levels[26]	auto[1]	19	1			T117	1		T351	1		T293	1
all_levels[27]	auto[0]	225373	1			T2	74		T7	5		T8	23
all_levels[27]	auto[1]	23	1			T129	1		T138	1		T133	2
all_levels[28]	auto[0]	198536	1			T2	45		T8	23		T9	2
all_levels[28]	auto[1]	12	1			T138	2		T265	1		T247	2
all_levels[29]	auto[0]	315353	1			T2	55		T7	1		T8	19
all_levels[29]	auto[1]	20	1			T7	2		T109	1		T181	1
all_levels[30]	auto[0]	216212	1			T2	58		T8	28		T10	493
all_levels[30]	auto[1]	15	1			T17	2		T339	1		T176	1
all_levels[31]	auto[0]	609912	1			T2	2923		T8	361		T9	2
all_levels[31]	auto[1]	10	1			T128	3		T158	1		T193	2
all_levels[32]	auto[0]	14640546	1			T2	52279		T7	3		T8	8669
all_levels[32]	auto[1]	532	1			T2	1		T7	2		T11	1