Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	758	1			T2	7		T16	7		T17	15
all_values[1]	758	1			T2	7		T16	7		T17	15
all_values[2]	758	1			T2	7		T16	7		T17	15
all_values[3]	758	1			T2	7		T16	7		T17	15
all_values[4]	758	1			T2	7		T16	7		T17	15
all_values[5]	758	1			T2	7		T16	7		T17	15
all_values[6]	758	1			T2	7		T16	7		T17	15
all_values[7]	758	1			T2	7		T16	7		T17	15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3319

1

T2

26

T16

29

T17

57

auto[1]

2745

1

T2

30

T16

27

T17

63

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2220

1

T2

23

T16

18

T17

42

auto[1]

3844

1

T2

33

T16

38

T17

78

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3581

1

T2

38

T16

30

T17

69

auto[1]

2483

1

T2

18

T16

26

T17

51

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	242	1			T2	1		T16	5		T17	5
all_values[0]	auto[0]	auto[1]	auto[1]	204	1			T2	5		T17	3		T31	2
all_values[0]	auto[1]	auto[0]	auto[1]	163	1			T2	1		T16	1		T17	2
all_values[0]	auto[1]	auto[1]	auto[1]	149	1			T16	1		T17	5		T109	2
all_values[1]	auto[0]	auto[0]	auto[0]	216	1			T17	2		T31	4		T33	4
all_values[1]	auto[0]	auto[1]	auto[0]	209	1			T2	3		T16	2		T17	4
all_values[1]	auto[1]	auto[0]	auto[1]	194	1			T2	2		T16	2		T17	6
all_values[1]	auto[1]	auto[1]	auto[1]	139	1			T2	2		T16	3		T17	3
all_values[2]	auto[0]	auto[0]	auto[0]	154	1			T2	2		T16	1		T17	4
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T16	1		T17	1		T31	1
all_values[2]	auto[0]	auto[1]	auto[0]	150	1			T2	3		T17	3		T31	1
all_values[2]	auto[0]	auto[1]	auto[1]	76	1			T16	1		T17	2		T31	1
all_values[2]	auto[1]	auto[0]	auto[1]	159	1			T16	1		T17	2		T31	1
all_values[2]	auto[1]	auto[1]	auto[1]	149	1			T2	2		T16	3		T17	3
all_values[3]	auto[0]	auto[0]	auto[0]	186	1			T2	1		T17	2		T31	2
all_values[3]	auto[0]	auto[0]	auto[1]	68	1			T16	1		T17	1		T125	1
all_values[3]	auto[0]	auto[1]	auto[0]	122	1			T16	4		T17	3		T33	3
all_values[3]	auto[0]	auto[1]	auto[1]	78	1			T2	2		T17	2		T33	1
all_values[3]	auto[1]	auto[0]	auto[1]	164	1			T2	2		T16	2		T17	5
all_values[3]	auto[1]	auto[1]	auto[1]	140	1			T2	2		T17	2		T31	1
all_values[4]	auto[0]	auto[0]	auto[0]	181	1			T2	4		T16	2		T17	1
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T31	1		T33	1		T108	1
all_values[4]	auto[0]	auto[1]	auto[0]	112	1			T2	2		T16	1		T17	5
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T16	1		T17	3		T31	1
all_values[4]	auto[1]	auto[0]	auto[1]	187	1			T16	2		T17	2		T31	1
all_values[4]	auto[1]	auto[1]	auto[1]	116	1			T2	1		T16	1		T17	4
all_values[5]	auto[0]	auto[0]	auto[0]	160	1			T2	3		T16	1		T17	3
all_values[5]	auto[0]	auto[0]	auto[1]	61	1			T17	2		T33	1		T109	1
all_values[5]	auto[0]	auto[1]	auto[0]	133	1			T2	1		T16	2		T17	2
all_values[5]	auto[0]	auto[1]	auto[1]	91	1			T2	1		T16	2		T17	1
all_values[5]	auto[1]	auto[0]	auto[1]	170	1			T16	2		T17	5		T31	3
all_values[5]	auto[1]	auto[1]	auto[1]	143	1			T2	2		T17	2		T33	1
all_values[6]	auto[0]	auto[0]	auto[0]	181	1			T2	1		T16	3		T17	3
all_values[6]	auto[0]	auto[0]	auto[1]	91	1			T2	3		T17	2		T108	2
all_values[6]	auto[0]	auto[1]	auto[0]	115	1			T2	1		T16	2		T17	6
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T17	1		T125	2		T109	1
all_values[6]	auto[1]	auto[0]	auto[1]	167	1			T2	2		T16	2		T17	1
all_values[6]	auto[1]	auto[1]	auto[1]	129	1			T17	2		T31	1		T33	1
all_values[7]	auto[0]	auto[0]	auto[0]	164	1			T2	2		T17	4		T125	1
all_values[7]	auto[0]	auto[0]	auto[1]	74	1			T2	1		T16	1		T17	2
all_values[7]	auto[0]	auto[1]	auto[0]	137	1			T31	2		T125	1		T108	1
all_values[7]	auto[0]	auto[1]	auto[1]	69	1			T2	2		T17	2		T31	1
all_values[7]	auto[1]	auto[0]	auto[1]	183	1			T2	1		T16	2		T17	2
all_values[7]	auto[1]	auto[1]	auto[1]	131	1			T2	1		T16	4		T17	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal