Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.29 99.27 97.95 100.00 98.80 100.00 99.71


Total test records in report: 1319
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T1258 /workspace/coverage/cover_reg_top/20.uart_intr_test.1586456708 May 23 12:32:24 PM PDT 24 May 23 12:32:28 PM PDT 24 22382476 ps
T1259 /workspace/coverage/cover_reg_top/18.uart_intr_test.4207784361 May 23 12:32:24 PM PDT 24 May 23 12:32:28 PM PDT 24 15126167 ps
T1260 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.347015548 May 23 12:32:04 PM PDT 24 May 23 12:32:06 PM PDT 24 14504353 ps
T1261 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2430185326 May 23 12:31:51 PM PDT 24 May 23 12:31:54 PM PDT 24 75078461 ps
T1262 /workspace/coverage/cover_reg_top/13.uart_csr_rw.984049327 May 23 12:32:08 PM PDT 24 May 23 12:32:11 PM PDT 24 14911354 ps
T1263 /workspace/coverage/cover_reg_top/7.uart_tl_errors.1642250141 May 23 12:32:07 PM PDT 24 May 23 12:32:11 PM PDT 24 137119224 ps
T91 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1362623948 May 23 12:32:07 PM PDT 24 May 23 12:32:11 PM PDT 24 83692547 ps
T1264 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.693525432 May 23 12:31:50 PM PDT 24 May 23 12:31:51 PM PDT 24 15738122 ps
T1265 /workspace/coverage/cover_reg_top/29.uart_intr_test.266779553 May 23 12:32:22 PM PDT 24 May 23 12:32:26 PM PDT 24 16949905 ps
T77 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2250903025 May 23 12:31:51 PM PDT 24 May 23 12:31:53 PM PDT 24 34010400 ps
T1266 /workspace/coverage/cover_reg_top/41.uart_intr_test.3991542066 May 23 12:32:23 PM PDT 24 May 23 12:32:28 PM PDT 24 19954238 ps
T64 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3059119853 May 23 12:32:07 PM PDT 24 May 23 12:32:09 PM PDT 24 15907853 ps
T1267 /workspace/coverage/cover_reg_top/27.uart_intr_test.1606914604 May 23 12:32:21 PM PDT 24 May 23 12:32:23 PM PDT 24 63396902 ps
T1268 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3042876757 May 23 12:31:39 PM PDT 24 May 23 12:31:41 PM PDT 24 112144753 ps
T123 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1456117543 May 23 12:32:08 PM PDT 24 May 23 12:32:12 PM PDT 24 61065518 ps
T1269 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1470372597 May 23 12:32:07 PM PDT 24 May 23 12:32:09 PM PDT 24 117913436 ps
T1270 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.826459731 May 23 12:31:42 PM PDT 24 May 23 12:31:44 PM PDT 24 100145800 ps
T1271 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1070302439 May 23 12:32:24 PM PDT 24 May 23 12:32:28 PM PDT 24 25880637 ps
T1272 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.652145895 May 23 12:31:50 PM PDT 24 May 23 12:31:51 PM PDT 24 18074302 ps
T122 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.326279080 May 23 12:32:06 PM PDT 24 May 23 12:32:09 PM PDT 24 318638582 ps
T1273 /workspace/coverage/cover_reg_top/13.uart_tl_errors.2075723932 May 23 12:32:10 PM PDT 24 May 23 12:32:13 PM PDT 24 228646887 ps
T1274 /workspace/coverage/cover_reg_top/43.uart_intr_test.2769008810 May 23 12:32:23 PM PDT 24 May 23 12:32:28 PM PDT 24 45247084 ps
T1275 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1994370818 May 23 12:31:45 PM PDT 24 May 23 12:31:48 PM PDT 24 259548005 ps
T1276 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1102610579 May 23 12:32:10 PM PDT 24 May 23 12:32:13 PM PDT 24 178088148 ps
T1277 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1049833721 May 23 12:32:04 PM PDT 24 May 23 12:32:06 PM PDT 24 21546769 ps
T1278 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1403271976 May 23 12:31:46 PM PDT 24 May 23 12:31:49 PM PDT 24 94169096 ps
T1279 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2622794283 May 23 12:32:20 PM PDT 24 May 23 12:32:23 PM PDT 24 16762984 ps
T1280 /workspace/coverage/cover_reg_top/0.uart_intr_test.1144140486 May 23 12:31:45 PM PDT 24 May 23 12:31:47 PM PDT 24 37380093 ps
T1281 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1693828758 May 23 12:32:04 PM PDT 24 May 23 12:32:07 PM PDT 24 53782946 ps
T1282 /workspace/coverage/cover_reg_top/3.uart_csr_rw.1727402662 May 23 12:31:51 PM PDT 24 May 23 12:31:53 PM PDT 24 36421181 ps
T1283 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.39703298 May 23 12:31:40 PM PDT 24 May 23 12:31:42 PM PDT 24 48531886 ps
T1284 /workspace/coverage/cover_reg_top/35.uart_intr_test.369932351 May 23 12:32:22 PM PDT 24 May 23 12:32:27 PM PDT 24 29629423 ps
T1285 /workspace/coverage/cover_reg_top/32.uart_intr_test.2867065235 May 23 12:32:21 PM PDT 24 May 23 12:32:24 PM PDT 24 11740527 ps
T124 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.904059613 May 23 12:31:52 PM PDT 24 May 23 12:31:55 PM PDT 24 261423444 ps
T1286 /workspace/coverage/cover_reg_top/14.uart_intr_test.2216883699 May 23 12:32:10 PM PDT 24 May 23 12:32:12 PM PDT 24 15872481 ps
T1287 /workspace/coverage/cover_reg_top/13.uart_intr_test.3073859018 May 23 12:32:12 PM PDT 24 May 23 12:32:14 PM PDT 24 57718935 ps
T1288 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1852137103 May 23 12:32:20 PM PDT 24 May 23 12:32:22 PM PDT 24 183567188 ps
T1289 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1371033458 May 23 12:32:19 PM PDT 24 May 23 12:32:21 PM PDT 24 31565522 ps
T1290 /workspace/coverage/cover_reg_top/12.uart_tl_errors.749253861 May 23 12:32:08 PM PDT 24 May 23 12:32:11 PM PDT 24 280123714 ps
T1291 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1869046762 May 23 12:31:51 PM PDT 24 May 23 12:31:53 PM PDT 24 48117666 ps
T1292 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.142181937 May 23 12:31:45 PM PDT 24 May 23 12:31:47 PM PDT 24 31324245 ps
T1293 /workspace/coverage/cover_reg_top/2.uart_tl_errors.588212399 May 23 12:31:39 PM PDT 24 May 23 12:31:42 PM PDT 24 19821741 ps
T1294 /workspace/coverage/cover_reg_top/9.uart_tl_errors.727281293 May 23 12:32:08 PM PDT 24 May 23 12:32:13 PM PDT 24 112998112 ps
T1295 /workspace/coverage/cover_reg_top/11.uart_intr_test.1822337235 May 23 12:32:09 PM PDT 24 May 23 12:32:11 PM PDT 24 17097955 ps
T1296 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3232699821 May 23 12:31:50 PM PDT 24 May 23 12:31:52 PM PDT 24 24054611 ps
T1297 /workspace/coverage/cover_reg_top/16.uart_intr_test.55792525 May 23 12:32:22 PM PDT 24 May 23 12:32:25 PM PDT 24 17238745 ps
T1298 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.515236953 May 23 12:32:06 PM PDT 24 May 23 12:32:08 PM PDT 24 135025516 ps
T65 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3367574274 May 23 12:32:21 PM PDT 24 May 23 12:32:24 PM PDT 24 23435519 ps
T1299 /workspace/coverage/cover_reg_top/31.uart_intr_test.3268017530 May 23 12:32:23 PM PDT 24 May 23 12:32:28 PM PDT 24 64008347 ps
T1300 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3268513082 May 23 12:31:51 PM PDT 24 May 23 12:31:54 PM PDT 24 369231028 ps
T1301 /workspace/coverage/cover_reg_top/44.uart_intr_test.347453337 May 23 12:32:38 PM PDT 24 May 23 12:32:41 PM PDT 24 19628160 ps
T1302 /workspace/coverage/cover_reg_top/48.uart_intr_test.3640806428 May 23 12:32:32 PM PDT 24 May 23 12:32:34 PM PDT 24 53235917 ps
T1303 /workspace/coverage/cover_reg_top/36.uart_intr_test.1147071520 May 23 12:32:24 PM PDT 24 May 23 12:32:28 PM PDT 24 17904928 ps
T1304 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3686452261 May 23 12:32:08 PM PDT 24 May 23 12:32:11 PM PDT 24 21384638 ps
T1305 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3494643633 May 23 12:31:50 PM PDT 24 May 23 12:31:53 PM PDT 24 31600844 ps
T1306 /workspace/coverage/cover_reg_top/5.uart_intr_test.1804551881 May 23 12:31:50 PM PDT 24 May 23 12:31:52 PM PDT 24 12767012 ps
T1307 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4095248998 May 23 12:32:05 PM PDT 24 May 23 12:32:07 PM PDT 24 31954651 ps
T1308 /workspace/coverage/cover_reg_top/18.uart_tl_errors.3553825688 May 23 12:32:23 PM PDT 24 May 23 12:32:28 PM PDT 24 818225310 ps
T1309 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.978759730 May 23 12:31:52 PM PDT 24 May 23 12:31:55 PM PDT 24 28916386 ps
T1310 /workspace/coverage/cover_reg_top/6.uart_intr_test.2986154360 May 23 12:32:05 PM PDT 24 May 23 12:32:07 PM PDT 24 11450408 ps
T1311 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.932526110 May 23 12:31:52 PM PDT 24 May 23 12:31:56 PM PDT 24 393248970 ps
T1312 /workspace/coverage/cover_reg_top/10.uart_intr_test.4220704722 May 23 12:32:07 PM PDT 24 May 23 12:32:10 PM PDT 24 43584176 ps
T1313 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.373144595 May 23 12:32:08 PM PDT 24 May 23 12:32:11 PM PDT 24 73956088 ps
T1314 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1670398297 May 23 12:31:38 PM PDT 24 May 23 12:31:39 PM PDT 24 55233188 ps
T1315 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3704894419 May 23 12:32:20 PM PDT 24 May 23 12:32:22 PM PDT 24 77662198 ps
T1316 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3964460451 May 23 12:32:22 PM PDT 24 May 23 12:32:25 PM PDT 24 23026800 ps
T1317 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.150589986 May 23 12:31:50 PM PDT 24 May 23 12:31:53 PM PDT 24 93438946 ps
T1318 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1338898463 May 23 12:32:25 PM PDT 24 May 23 12:32:29 PM PDT 24 14230015 ps
T1319 /workspace/coverage/cover_reg_top/26.uart_intr_test.1217806415 May 23 12:32:21 PM PDT 24 May 23 12:32:23 PM PDT 24 11890790 ps

Test location /workspace/coverage/default/47.uart_stress_all.2497118428
Short name T2
Test name
Test status
Simulation time 41576539128 ps
CPU time 342.17 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 12:52:20 PM PDT 24
Peak memory 200332 kb
Host smart-d6caa716-b197-4e18-aeb3-86548bcb639b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497118428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2497118428
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2335982481
Short name T17
Test name
Test status
Simulation time 108675611939 ps
CPU time 2214.1 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 01:23:32 PM PDT 24
Peak memory 216916 kb
Host smart-d919f6e4-dfe2-44fa-a850-799757318e88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335982481 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2335982481
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3720426019
Short name T147
Test name
Test status
Simulation time 850300670757 ps
CPU time 611.6 seconds
Started May 23 12:46:53 PM PDT 24
Finished May 23 12:57:06 PM PDT 24
Peak memory 225380 kb
Host smart-7e69e0b2-e833-4627-a854-3a44d65fb462
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720426019 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3720426019
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3969976874
Short name T8
Test name
Test status
Simulation time 204579625594 ps
CPU time 612.24 seconds
Started May 23 12:47:01 PM PDT 24
Finished May 23 12:57:14 PM PDT 24
Peak memory 225300 kb
Host smart-a2303346-0e1d-4eb9-997f-b8e7bf11ba32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969976874 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3969976874
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all.4610918
Short name T21
Test name
Test status
Simulation time 233905930553 ps
CPU time 354.01 seconds
Started May 23 12:43:57 PM PDT 24
Finished May 23 12:49:53 PM PDT 24
Peak memory 200368 kb
Host smart-25cfca82-198d-4167-a440-24efa1815178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4610918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.4610918
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.273259569
Short name T129
Test name
Test status
Simulation time 93988147708 ps
CPU time 761.51 seconds
Started May 23 12:46:49 PM PDT 24
Finished May 23 12:59:33 PM PDT 24
Peak memory 216852 kb
Host smart-ce3c5e29-20cf-49d1-a3c7-98cd6cfcedc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273259569 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.273259569
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1756110157
Short name T307
Test name
Test status
Simulation time 132809462486 ps
CPU time 922.72 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 01:01:48 PM PDT 24
Peak memory 200348 kb
Host smart-09260ba2-d7e7-4dc9-9a9e-6b38b81ef9e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1756110157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1756110157
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.188275328
Short name T108
Test name
Test status
Simulation time 257226677971 ps
CPU time 306.99 seconds
Started May 23 12:46:34 PM PDT 24
Finished May 23 12:51:43 PM PDT 24
Peak memory 217152 kb
Host smart-05888de9-0783-48ef-903c-62e769f35a82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188275328 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.188275328
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2056974193
Short name T153
Test name
Test status
Simulation time 278203748297 ps
CPU time 772.06 seconds
Started May 23 12:44:52 PM PDT 24
Finished May 23 12:57:46 PM PDT 24
Peak memory 216736 kb
Host smart-26a983d8-1bbd-401f-ad01-bdcb75b32dfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056974193 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2056974193
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1137601619
Short name T13
Test name
Test status
Simulation time 175253156057 ps
CPU time 141.13 seconds
Started May 23 12:47:08 PM PDT 24
Finished May 23 12:49:30 PM PDT 24
Peak memory 200488 kb
Host smart-9d26d303-c519-4a7a-b426-101c20ed7b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137601619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1137601619
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3246117440
Short name T99
Test name
Test status
Simulation time 281176984 ps
CPU time 0.92 seconds
Started May 23 12:43:45 PM PDT 24
Finished May 23 12:43:47 PM PDT 24
Peak memory 218884 kb
Host smart-434b41e9-9c0f-46ee-a469-55362e5bd896
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246117440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3246117440
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/10.uart_alert_test.716060603
Short name T363
Test name
Test status
Simulation time 13589314 ps
CPU time 0.61 seconds
Started May 23 12:44:20 PM PDT 24
Finished May 23 12:44:21 PM PDT 24
Peak memory 195768 kb
Host smart-93b57af0-7137-4ee5-b825-63aa52db0448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716060603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.716060603
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_stress_all.1033000754
Short name T265
Test name
Test status
Simulation time 962629674797 ps
CPU time 147.9 seconds
Started May 23 12:45:14 PM PDT 24
Finished May 23 12:47:43 PM PDT 24
Peak memory 216108 kb
Host smart-502daea8-2bd9-4d83-a0a0-b3629bed9ab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033000754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1033000754
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_fifo_full.4167217450
Short name T135
Test name
Test status
Simulation time 263805849501 ps
CPU time 386.94 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 12:53:05 PM PDT 24
Peak memory 200424 kb
Host smart-2f0107b7-dbe7-4a13-9305-37abfc891143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167217450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.4167217450
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2930331857
Short name T125
Test name
Test status
Simulation time 173391447325 ps
CPU time 719.15 seconds
Started May 23 12:44:14 PM PDT 24
Finished May 23 12:56:15 PM PDT 24
Peak memory 217168 kb
Host smart-48887ce5-3f36-4e2e-98ae-3529630a61e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930331857 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2930331857
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1094187853
Short name T62
Test name
Test status
Simulation time 20284064 ps
CPU time 0.61 seconds
Started May 23 12:31:39 PM PDT 24
Finished May 23 12:31:41 PM PDT 24
Peak memory 195268 kb
Host smart-2faf9096-4d69-4939-9f29-6edb7b260a51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094187853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1094187853
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3293059692
Short name T286
Test name
Test status
Simulation time 146019011825 ps
CPU time 113.46 seconds
Started May 23 12:47:44 PM PDT 24
Finished May 23 12:49:39 PM PDT 24
Peak memory 200396 kb
Host smart-f4be8048-2605-4f51-9ee0-6566e0dca734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293059692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3293059692
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.330378911
Short name T94
Test name
Test status
Simulation time 160568478 ps
CPU time 1.28 seconds
Started May 23 12:32:03 PM PDT 24
Finished May 23 12:32:05 PM PDT 24
Peak memory 198940 kb
Host smart-730046fd-345f-43e1-b5be-5eb14fb3f788
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330378911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.330378911
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.292291638
Short name T138
Test name
Test status
Simulation time 199807917887 ps
CPU time 72.28 seconds
Started May 23 12:47:19 PM PDT 24
Finished May 23 12:48:33 PM PDT 24
Peak memory 200376 kb
Host smart-a9512ed9-9630-4bc0-b57f-dbeda63f9ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292291638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.292291638
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3309611019
Short name T116
Test name
Test status
Simulation time 204957142493 ps
CPU time 356.99 seconds
Started May 23 12:47:44 PM PDT 24
Finished May 23 12:53:43 PM PDT 24
Peak memory 200376 kb
Host smart-49f85291-9c65-4af4-9c9e-0b46e720a95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309611019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3309611019
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all.1977046361
Short name T294
Test name
Test status
Simulation time 371297708531 ps
CPU time 733.7 seconds
Started May 23 12:45:04 PM PDT 24
Finished May 23 12:57:19 PM PDT 24
Peak memory 200248 kb
Host smart-b437d51f-0ef7-4b46-aa18-7b8c4798965c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977046361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1977046361
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1043969715
Short name T134
Test name
Test status
Simulation time 46858537718 ps
CPU time 40.56 seconds
Started May 23 12:48:15 PM PDT 24
Finished May 23 12:48:57 PM PDT 24
Peak memory 200240 kb
Host smart-3e1574a9-4bc5-4f47-89ba-8513c8a40943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043969715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1043969715
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all.3101331816
Short name T143
Test name
Test status
Simulation time 739460577146 ps
CPU time 424.07 seconds
Started May 23 12:44:11 PM PDT 24
Finished May 23 12:51:17 PM PDT 24
Peak memory 208824 kb
Host smart-dc87ac83-883b-4477-a74f-508a31033568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101331816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3101331816
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2254604535
Short name T168
Test name
Test status
Simulation time 1448966957410 ps
CPU time 959.14 seconds
Started May 23 12:46:37 PM PDT 24
Finished May 23 01:02:38 PM PDT 24
Peak memory 225336 kb
Host smart-2d439a6c-5716-40c0-90e9-5f76922c7fab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254604535 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2254604535
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.131189675
Short name T82
Test name
Test status
Simulation time 28125430 ps
CPU time 0.67 seconds
Started May 23 12:32:07 PM PDT 24
Finished May 23 12:32:10 PM PDT 24
Peak memory 195200 kb
Host smart-393d685a-b7b2-4aa6-918b-bcd0da183b0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131189675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.131189675
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.4143334578
Short name T111
Test name
Test status
Simulation time 246167814134 ps
CPU time 660.92 seconds
Started May 23 12:44:52 PM PDT 24
Finished May 23 12:55:54 PM PDT 24
Peak memory 225240 kb
Host smart-47e239ac-1422-4472-9bd8-dc2364670612
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143334578 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.4143334578
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2008624812
Short name T90
Test name
Test status
Simulation time 83524964 ps
CPU time 1.24 seconds
Started May 23 12:32:07 PM PDT 24
Finished May 23 12:32:10 PM PDT 24
Peak memory 198944 kb
Host smart-f08584cf-3a74-4789-a515-32a5e51918ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008624812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2008624812
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3166195679
Short name T207
Test name
Test status
Simulation time 63638498876 ps
CPU time 29.45 seconds
Started May 23 12:47:33 PM PDT 24
Finished May 23 12:48:05 PM PDT 24
Peak memory 200420 kb
Host smart-f91735c7-fc98-43f3-8f0f-a8db0b6d202d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166195679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3166195679
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1714486535
Short name T41
Test name
Test status
Simulation time 126292662450 ps
CPU time 59.8 seconds
Started May 23 12:45:06 PM PDT 24
Finished May 23 12:46:07 PM PDT 24
Peak memory 200168 kb
Host smart-4d966ee6-5ba5-4e17-ae53-92760b40fb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714486535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1714486535
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2988335480
Short name T37
Test name
Test status
Simulation time 186777069244 ps
CPU time 355.75 seconds
Started May 23 12:47:22 PM PDT 24
Finished May 23 12:53:19 PM PDT 24
Peak memory 200132 kb
Host smart-f7a245e8-91d5-4e41-90b5-4253c2197253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988335480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2988335480
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2553694788
Short name T180
Test name
Test status
Simulation time 17429978834 ps
CPU time 49.83 seconds
Started May 23 12:43:56 PM PDT 24
Finished May 23 12:44:47 PM PDT 24
Peak memory 200312 kb
Host smart-aae469c8-d324-4a6e-a033-97fb14a39ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553694788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2553694788
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1359838401
Short name T14
Test name
Test status
Simulation time 150669562670 ps
CPU time 47.05 seconds
Started May 23 12:47:46 PM PDT 24
Finished May 23 12:48:34 PM PDT 24
Peak memory 200336 kb
Host smart-90f3556c-cb94-4910-8881-0d3607cb6142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359838401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1359838401
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1102085971
Short name T184
Test name
Test status
Simulation time 143211673873 ps
CPU time 103.63 seconds
Started May 23 12:47:56 PM PDT 24
Finished May 23 12:49:41 PM PDT 24
Peak memory 200296 kb
Host smart-0984793c-ddbd-4099-9713-97005f5299ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102085971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1102085971
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.269184642
Short name T50
Test name
Test status
Simulation time 62352937629 ps
CPU time 282.07 seconds
Started May 23 12:44:20 PM PDT 24
Finished May 23 12:49:03 PM PDT 24
Peak memory 216716 kb
Host smart-af134849-1d38-4808-bd18-be8963db25c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269184642 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.269184642
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2111228084
Short name T1054
Test name
Test status
Simulation time 470314826629 ps
CPU time 1787.89 seconds
Started May 23 12:44:51 PM PDT 24
Finished May 23 01:14:41 PM PDT 24
Peak memory 233536 kb
Host smart-b412b191-c954-4eab-ba54-cdcd301ba6e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111228084 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2111228084
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3651139862
Short name T444
Test name
Test status
Simulation time 196581333300 ps
CPU time 78.15 seconds
Started May 23 12:46:37 PM PDT 24
Finished May 23 12:47:57 PM PDT 24
Peak memory 200508 kb
Host smart-8b1b988a-9065-4c62-9873-bff67cc26622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651139862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3651139862
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.796450315
Short name T109
Test name
Test status
Simulation time 53722914868 ps
CPU time 452.64 seconds
Started May 23 12:47:03 PM PDT 24
Finished May 23 12:54:37 PM PDT 24
Peak memory 216064 kb
Host smart-fde4dd55-cb72-4b55-8800-07dc3019d080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796450315 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.796450315
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3387341694
Short name T156
Test name
Test status
Simulation time 120607816161 ps
CPU time 128.31 seconds
Started May 23 12:47:55 PM PDT 24
Finished May 23 12:50:04 PM PDT 24
Peak memory 200452 kb
Host smart-790a619c-ff99-4957-b9d5-b633336749f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387341694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3387341694
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all.3388025949
Short name T245
Test name
Test status
Simulation time 202655712569 ps
CPU time 925.7 seconds
Started May 23 12:43:52 PM PDT 24
Finished May 23 12:59:19 PM PDT 24
Peak memory 200216 kb
Host smart-c6194470-df23-4755-a729-efdf96bddc15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388025949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3388025949
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_fifo_full.4046065517
Short name T146
Test name
Test status
Simulation time 85688901841 ps
CPU time 16.09 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:44:42 PM PDT 24
Peak memory 200376 kb
Host smart-4d1ef8a3-c9fd-4e7c-bcfd-57072e885707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046065517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.4046065517
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_full.715337524
Short name T298
Test name
Test status
Simulation time 187409439874 ps
CPU time 390.49 seconds
Started May 23 12:44:38 PM PDT 24
Finished May 23 12:51:13 PM PDT 24
Peak memory 200400 kb
Host smart-71603b49-be0c-48a3-97b9-4875d8773f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715337524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.715337524
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3176475790
Short name T177
Test name
Test status
Simulation time 202236164821 ps
CPU time 113.54 seconds
Started May 23 12:45:28 PM PDT 24
Finished May 23 12:47:23 PM PDT 24
Peak memory 200440 kb
Host smart-e2d7ce7f-690b-4ee2-949b-e1720d19925c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176475790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3176475790
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1875163638
Short name T171
Test name
Test status
Simulation time 167680849319 ps
CPU time 77.88 seconds
Started May 23 12:47:22 PM PDT 24
Finished May 23 12:48:41 PM PDT 24
Peak memory 200308 kb
Host smart-aca198d4-30f0-4be8-b0dc-3fa977dc8ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875163638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1875163638
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.616037846
Short name T191
Test name
Test status
Simulation time 75070039804 ps
CPU time 34.16 seconds
Started May 23 12:47:44 PM PDT 24
Finished May 23 12:48:20 PM PDT 24
Peak memory 200212 kb
Host smart-3b165bb4-7248-4060-9990-cda46e2fb77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616037846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.616037846
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2381571348
Short name T232
Test name
Test status
Simulation time 117114009215 ps
CPU time 40.75 seconds
Started May 23 12:47:58 PM PDT 24
Finished May 23 12:48:40 PM PDT 24
Peak memory 200480 kb
Host smart-0b5ca40a-1d44-4390-b8c3-ebcca7e989b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381571348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2381571348
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.4121744422
Short name T45
Test name
Test status
Simulation time 23495728164 ps
CPU time 35.33 seconds
Started May 23 12:47:04 PM PDT 24
Finished May 23 12:47:41 PM PDT 24
Peak memory 200420 kb
Host smart-521cdbfe-a328-448d-8f39-c31465017667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121744422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.4121744422
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1951327371
Short name T247
Test name
Test status
Simulation time 59570036028 ps
CPU time 136.12 seconds
Started May 23 12:47:26 PM PDT 24
Finished May 23 12:49:43 PM PDT 24
Peak memory 200296 kb
Host smart-2043ef66-628f-4dc7-9f47-a9376468145e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951327371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1951327371
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3700660287
Short name T243
Test name
Test status
Simulation time 52109694139 ps
CPU time 54.31 seconds
Started May 23 12:47:32 PM PDT 24
Finished May 23 12:48:29 PM PDT 24
Peak memory 200380 kb
Host smart-f34edf88-1049-4562-8330-688909e4b92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700660287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3700660287
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all.2138783977
Short name T197
Test name
Test status
Simulation time 202095093505 ps
CPU time 169.7 seconds
Started May 23 12:44:51 PM PDT 24
Finished May 23 12:47:43 PM PDT 24
Peak memory 200432 kb
Host smart-7fae8cc4-a9f8-4b80-a6ec-7c5bdd8c2903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138783977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2138783977
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1988999332
Short name T193
Test name
Test status
Simulation time 159887140890 ps
CPU time 54 seconds
Started May 23 12:47:44 PM PDT 24
Finished May 23 12:48:40 PM PDT 24
Peak memory 200300 kb
Host smart-d9b3cd2b-7d0a-408c-9308-ba7bf82f6fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988999332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1988999332
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1776025586
Short name T557
Test name
Test status
Simulation time 387500004487 ps
CPU time 165.58 seconds
Started May 23 12:45:16 PM PDT 24
Finished May 23 12:48:03 PM PDT 24
Peak memory 215832 kb
Host smart-840d7af6-2a3f-466c-a0a4-bafbfcdf0a39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776025586 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1776025586
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.788722686
Short name T68
Test name
Test status
Simulation time 86761352697 ps
CPU time 256.13 seconds
Started May 23 12:47:06 PM PDT 24
Finished May 23 12:51:23 PM PDT 24
Peak memory 216484 kb
Host smart-8eee9a2e-d4a1-49b2-80a9-de10036c32c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788722686 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.788722686
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3073866273
Short name T479
Test name
Test status
Simulation time 87143060731 ps
CPU time 92.84 seconds
Started May 23 12:47:01 PM PDT 24
Finished May 23 12:48:35 PM PDT 24
Peak memory 200408 kb
Host smart-092b57d6-a8fa-4be7-850d-1095a71bce53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073866273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3073866273
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1456117543
Short name T123
Test name
Test status
Simulation time 61065518 ps
CPU time 1.01 seconds
Started May 23 12:32:08 PM PDT 24
Finished May 23 12:32:12 PM PDT 24
Peak memory 198800 kb
Host smart-d1863e2b-1421-4129-875c-0a7edda0947f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456117543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1456117543
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1754557231
Short name T97
Test name
Test status
Simulation time 164790659 ps
CPU time 0.88 seconds
Started May 23 12:31:45 PM PDT 24
Finished May 23 12:31:47 PM PDT 24
Peak memory 198572 kb
Host smart-7192b34f-5129-4bcc-85cd-f3a1de0f2350
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754557231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1754557231
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1336511284
Short name T225
Test name
Test status
Simulation time 25359015441 ps
CPU time 47.9 seconds
Started May 23 12:47:18 PM PDT 24
Finished May 23 12:48:07 PM PDT 24
Peak memory 200444 kb
Host smart-c7dba52c-3492-464d-8c3d-19ca4d098d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336511284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1336511284
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.855342353
Short name T244
Test name
Test status
Simulation time 90437554132 ps
CPU time 36.14 seconds
Started May 23 12:47:19 PM PDT 24
Finished May 23 12:47:57 PM PDT 24
Peak memory 200488 kb
Host smart-04391b7d-6fe8-45ff-b39e-ace0a8607728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855342353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.855342353
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3587777924
Short name T1091
Test name
Test status
Simulation time 90432253747 ps
CPU time 39.99 seconds
Started May 23 12:44:21 PM PDT 24
Finished May 23 12:45:02 PM PDT 24
Peak memory 200724 kb
Host smart-bb686ad7-e841-4c2d-9e99-a6a0d50fd1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587777924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3587777924
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_stress_all.1403016077
Short name T160
Test name
Test status
Simulation time 190140362647 ps
CPU time 95.81 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:46:03 PM PDT 24
Peak memory 216676 kb
Host smart-42db4d59-3072-4539-881b-d96cf965b891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403016077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1403016077
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.4279656367
Short name T239
Test name
Test status
Simulation time 206598447262 ps
CPU time 469.07 seconds
Started May 23 12:47:22 PM PDT 24
Finished May 23 12:55:13 PM PDT 24
Peak memory 200480 kb
Host smart-66e17072-d55a-4cd2-b93d-e7d23789a591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279656367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.4279656367
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.2976039890
Short name T238
Test name
Test status
Simulation time 111685639717 ps
CPU time 215.41 seconds
Started May 23 12:44:29 PM PDT 24
Finished May 23 12:48:06 PM PDT 24
Peak memory 200500 kb
Host smart-d1d14b46-9a20-4796-a54c-56f7dde8efc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976039890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2976039890
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1972615098
Short name T218
Test name
Test status
Simulation time 154872152109 ps
CPU time 94.71 seconds
Started May 23 12:47:25 PM PDT 24
Finished May 23 12:49:00 PM PDT 24
Peak memory 200280 kb
Host smart-8cca39ea-2d89-4629-aeaa-6fe0d5589022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972615098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1972615098
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.224672561
Short name T256
Test name
Test status
Simulation time 44823843321 ps
CPU time 21.62 seconds
Started May 23 12:47:24 PM PDT 24
Finished May 23 12:47:47 PM PDT 24
Peak memory 200388 kb
Host smart-462da447-08e7-4593-8ade-c613f86c4669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224672561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.224672561
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1971413391
Short name T42
Test name
Test status
Simulation time 97250208830 ps
CPU time 20.16 seconds
Started May 23 12:47:25 PM PDT 24
Finished May 23 12:47:46 PM PDT 24
Peak memory 200308 kb
Host smart-3df08590-5b5c-4354-b124-35568cff5527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971413391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1971413391
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3893672602
Short name T157
Test name
Test status
Simulation time 47585931307 ps
CPU time 24.46 seconds
Started May 23 12:44:34 PM PDT 24
Finished May 23 12:45:00 PM PDT 24
Peak memory 200332 kb
Host smart-89bd6b14-f287-40d2-9a07-ec3e77876362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893672602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3893672602
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1124886926
Short name T593
Test name
Test status
Simulation time 67135372010 ps
CPU time 32.76 seconds
Started May 23 12:47:26 PM PDT 24
Finished May 23 12:48:00 PM PDT 24
Peak memory 200376 kb
Host smart-2454fc5b-f426-49e5-b67d-3807b68d52d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124886926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1124886926
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1894825143
Short name T119
Test name
Test status
Simulation time 59490406021 ps
CPU time 43.84 seconds
Started May 23 12:47:32 PM PDT 24
Finished May 23 12:48:18 PM PDT 24
Peak memory 200380 kb
Host smart-efb6b488-13c3-4b1f-8616-80d031555fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894825143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1894825143
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2012913873
Short name T131
Test name
Test status
Simulation time 55308199961 ps
CPU time 127.85 seconds
Started May 23 12:47:34 PM PDT 24
Finished May 23 12:49:44 PM PDT 24
Peak memory 200308 kb
Host smart-46fca2d7-cb59-4062-a37b-fb8e97c1aa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012913873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2012913873
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.4183369425
Short name T166
Test name
Test status
Simulation time 47356819240 ps
CPU time 13.86 seconds
Started May 23 12:47:34 PM PDT 24
Finished May 23 12:47:50 PM PDT 24
Peak memory 200320 kb
Host smart-bfd1fd0c-5348-47dc-8d1d-f32186201509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183369425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.4183369425
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.4036027128
Short name T140
Test name
Test status
Simulation time 81023360050 ps
CPU time 141.57 seconds
Started May 23 12:45:07 PM PDT 24
Finished May 23 12:47:30 PM PDT 24
Peak memory 200292 kb
Host smart-d4f781d4-2387-4294-962c-e53253d15fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036027128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.4036027128
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1075583195
Short name T215
Test name
Test status
Simulation time 115647903576 ps
CPU time 204.71 seconds
Started May 23 12:47:58 PM PDT 24
Finished May 23 12:51:24 PM PDT 24
Peak memory 200404 kb
Host smart-7d784a2a-4c29-43be-afdf-740312514718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075583195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1075583195
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_stress_all.1707932341
Short name T249
Test name
Test status
Simulation time 251618811388 ps
CPU time 234.25 seconds
Started May 23 12:45:46 PM PDT 24
Finished May 23 12:49:41 PM PDT 24
Peak memory 200408 kb
Host smart-93f65547-749b-4564-849e-7b90ad3821ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707932341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1707932341
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1495188362
Short name T235
Test name
Test status
Simulation time 51519786631 ps
CPU time 22.44 seconds
Started May 23 12:46:40 PM PDT 24
Finished May 23 12:47:04 PM PDT 24
Peak memory 200492 kb
Host smart-3e8f83e1-1c4f-4df9-a892-6f1f555858b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495188362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1495188362
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1990966092
Short name T253
Test name
Test status
Simulation time 109301093593 ps
CPU time 38 seconds
Started May 23 12:46:47 PM PDT 24
Finished May 23 12:47:27 PM PDT 24
Peak memory 200408 kb
Host smart-fa4de8d0-0a20-4077-a4db-65e5c9bbeb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990966092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1990966092
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2069064314
Short name T150
Test name
Test status
Simulation time 53106042475 ps
CPU time 29.14 seconds
Started May 23 12:44:10 PM PDT 24
Finished May 23 12:44:41 PM PDT 24
Peak memory 200400 kb
Host smart-439b7338-16f4-463d-8db2-2aee670f997c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069064314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2069064314
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.87918800
Short name T76
Test name
Test status
Simulation time 71339097 ps
CPU time 0.66 seconds
Started May 23 12:31:45 PM PDT 24
Finished May 23 12:31:47 PM PDT 24
Peak memory 194672 kb
Host smart-d8777607-6c27-4e48-b1ab-54e2149c80f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87918800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.87918800
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1994370818
Short name T1275
Test name
Test status
Simulation time 259548005 ps
CPU time 1.49 seconds
Started May 23 12:31:45 PM PDT 24
Finished May 23 12:31:48 PM PDT 24
Peak memory 197260 kb
Host smart-7d09a3b6-6fe0-4358-a411-d684200b231c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994370818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1994370818
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4180683106
Short name T1249
Test name
Test status
Simulation time 16493436 ps
CPU time 0.61 seconds
Started May 23 12:31:39 PM PDT 24
Finished May 23 12:31:42 PM PDT 24
Peak memory 195068 kb
Host smart-218b269e-ce05-43d4-8dc6-ec445b37566a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180683106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4180683106
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.826459731
Short name T1270
Test name
Test status
Simulation time 100145800 ps
CPU time 1.14 seconds
Started May 23 12:31:42 PM PDT 24
Finished May 23 12:31:44 PM PDT 24
Peak memory 199696 kb
Host smart-669ddc51-a044-42f4-835d-a5bbf9f84802
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826459731 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.826459731
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3175003678
Short name T1255
Test name
Test status
Simulation time 55876889 ps
CPU time 0.61 seconds
Started May 23 12:31:46 PM PDT 24
Finished May 23 12:31:48 PM PDT 24
Peak memory 195068 kb
Host smart-678832fe-8de5-4bfb-8138-63a8020b384c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175003678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3175003678
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1144140486
Short name T1280
Test name
Test status
Simulation time 37380093 ps
CPU time 0.54 seconds
Started May 23 12:31:45 PM PDT 24
Finished May 23 12:31:47 PM PDT 24
Peak memory 194020 kb
Host smart-55722627-a71f-4cdc-ab3a-fa567a6e8524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144140486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1144140486
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1670398297
Short name T1314
Test name
Test status
Simulation time 55233188 ps
CPU time 0.72 seconds
Started May 23 12:31:38 PM PDT 24
Finished May 23 12:31:39 PM PDT 24
Peak memory 196820 kb
Host smart-350d9c66-3fd7-4446-a3cc-db5739235ad8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670398297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1670398297
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2637621361
Short name T1235
Test name
Test status
Simulation time 112728930 ps
CPU time 2.3 seconds
Started May 23 12:31:40 PM PDT 24
Finished May 23 12:31:44 PM PDT 24
Peak memory 199672 kb
Host smart-2dc681eb-3a8e-4465-aaa5-a23a161a3003
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637621361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2637621361
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2191341611
Short name T92
Test name
Test status
Simulation time 309531071 ps
CPU time 1.22 seconds
Started May 23 12:31:47 PM PDT 24
Finished May 23 12:31:49 PM PDT 24
Peak memory 198868 kb
Host smart-1d380b24-7486-410f-9c38-7d7d1c8e1527
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191341611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2191341611
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.142181937
Short name T1292
Test name
Test status
Simulation time 31324245 ps
CPU time 0.79 seconds
Started May 23 12:31:45 PM PDT 24
Finished May 23 12:31:47 PM PDT 24
Peak memory 195940 kb
Host smart-fc51d8b8-a118-4265-9347-0b4ca2efbd35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142181937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.142181937
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1403271976
Short name T1278
Test name
Test status
Simulation time 94169096 ps
CPU time 1.59 seconds
Started May 23 12:31:46 PM PDT 24
Finished May 23 12:31:49 PM PDT 24
Peak memory 197364 kb
Host smart-c30bd47f-2d4d-4922-8516-1f6742fc2c04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403271976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1403271976
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2534972624
Short name T63
Test name
Test status
Simulation time 55451771 ps
CPU time 0.65 seconds
Started May 23 12:31:44 PM PDT 24
Finished May 23 12:31:46 PM PDT 24
Peak memory 195068 kb
Host smart-eab56eaf-3c89-4454-bc96-4cb9596f6463
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534972624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2534972624
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3042876757
Short name T1268
Test name
Test status
Simulation time 112144753 ps
CPU time 1.36 seconds
Started May 23 12:31:39 PM PDT 24
Finished May 23 12:31:41 PM PDT 24
Peak memory 199740 kb
Host smart-85ba173c-8f60-4f03-9a1a-ac14496a5f4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042876757 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3042876757
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.4144654877
Short name T1191
Test name
Test status
Simulation time 13373978 ps
CPU time 0.57 seconds
Started May 23 12:31:42 PM PDT 24
Finished May 23 12:31:44 PM PDT 24
Peak memory 193700 kb
Host smart-9e6fcc64-92d6-44b3-a69b-d8ee0f5866d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144654877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.4144654877
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2073051177
Short name T1248
Test name
Test status
Simulation time 40209200 ps
CPU time 0.61 seconds
Started May 23 12:31:42 PM PDT 24
Finished May 23 12:31:44 PM PDT 24
Peak memory 195004 kb
Host smart-2cd3aca6-beba-4b58-ab63-2c695f2e53a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073051177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2073051177
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2044898665
Short name T1198
Test name
Test status
Simulation time 307897009 ps
CPU time 1.49 seconds
Started May 23 12:31:38 PM PDT 24
Finished May 23 12:31:40 PM PDT 24
Peak memory 199628 kb
Host smart-efd4fea6-4138-4a49-a44c-d68bfdfa01cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044898665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2044898665
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1211596882
Short name T1236
Test name
Test status
Simulation time 85570852 ps
CPU time 1.42 seconds
Started May 23 12:31:40 PM PDT 24
Finished May 23 12:31:43 PM PDT 24
Peak memory 199212 kb
Host smart-e13fdcfa-482a-4fcb-84bf-1ef129f0afee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211596882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1211596882
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3686452261
Short name T1304
Test name
Test status
Simulation time 21384638 ps
CPU time 0.71 seconds
Started May 23 12:32:08 PM PDT 24
Finished May 23 12:32:11 PM PDT 24
Peak memory 197956 kb
Host smart-946e7aef-099d-42d8-8266-ed75d0e7dd98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686452261 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3686452261
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.4220704722
Short name T1312
Test name
Test status
Simulation time 43584176 ps
CPU time 0.56 seconds
Started May 23 12:32:07 PM PDT 24
Finished May 23 12:32:10 PM PDT 24
Peak memory 194092 kb
Host smart-dbce8d6e-f35b-42e3-a124-f43874b5eaa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220704722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.4220704722
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.4101321381
Short name T1246
Test name
Test status
Simulation time 53894434 ps
CPU time 0.59 seconds
Started May 23 12:32:07 PM PDT 24
Finished May 23 12:32:10 PM PDT 24
Peak memory 195136 kb
Host smart-164ebb52-7fda-402e-a142-4a0fb25c9390
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101321381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.4101321381
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1399292089
Short name T1193
Test name
Test status
Simulation time 185222755 ps
CPU time 1.05 seconds
Started May 23 12:32:07 PM PDT 24
Finished May 23 12:32:10 PM PDT 24
Peak memory 199728 kb
Host smart-3a47eb38-0e5a-4a3b-94c3-e1fb46e1c7e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399292089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1399292089
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1362623948
Short name T91
Test name
Test status
Simulation time 83692547 ps
CPU time 1.37 seconds
Started May 23 12:32:07 PM PDT 24
Finished May 23 12:32:11 PM PDT 24
Peak memory 199052 kb
Host smart-0aa7cf8e-fee5-435d-b324-d7c95ceffa3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362623948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1362623948
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3155997839
Short name T1207
Test name
Test status
Simulation time 46998202 ps
CPU time 0.82 seconds
Started May 23 12:32:10 PM PDT 24
Finished May 23 12:32:13 PM PDT 24
Peak memory 199584 kb
Host smart-54080297-f69b-49ca-8d6a-d2240002e340
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155997839 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3155997839
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2578097657
Short name T78
Test name
Test status
Simulation time 79108765 ps
CPU time 0.6 seconds
Started May 23 12:32:11 PM PDT 24
Finished May 23 12:32:13 PM PDT 24
Peak memory 195104 kb
Host smart-7373dcfc-9993-4249-b5a8-fe5b2da9cb9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578097657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2578097657
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1822337235
Short name T1295
Test name
Test status
Simulation time 17097955 ps
CPU time 0.56 seconds
Started May 23 12:32:09 PM PDT 24
Finished May 23 12:32:11 PM PDT 24
Peak memory 194048 kb
Host smart-cd7590fd-5b95-43a8-bb29-c1ef537f2308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822337235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1822337235
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.947493857
Short name T1252
Test name
Test status
Simulation time 54115249 ps
CPU time 0.75 seconds
Started May 23 12:32:09 PM PDT 24
Finished May 23 12:32:12 PM PDT 24
Peak memory 196608 kb
Host smart-ab169eec-4445-46af-b3c9-4653f31a56d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947493857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.947493857
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1398649702
Short name T1244
Test name
Test status
Simulation time 83708461 ps
CPU time 1.03 seconds
Started May 23 12:32:06 PM PDT 24
Finished May 23 12:32:09 PM PDT 24
Peak memory 199700 kb
Host smart-493912b6-9c9b-4ffb-98a0-5183cde89859
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398649702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1398649702
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1197259793
Short name T1232
Test name
Test status
Simulation time 33565659 ps
CPU time 0.88 seconds
Started May 23 12:32:09 PM PDT 24
Finished May 23 12:32:12 PM PDT 24
Peak memory 199600 kb
Host smart-d1bddef2-b5d1-4eea-98dc-aa80435943c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197259793 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1197259793
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2063148243
Short name T81
Test name
Test status
Simulation time 12623420 ps
CPU time 0.6 seconds
Started May 23 12:32:09 PM PDT 24
Finished May 23 12:32:12 PM PDT 24
Peak memory 195160 kb
Host smart-3ef3c097-e5b2-49af-97f3-ed45331705e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063148243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2063148243
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.4175720061
Short name T1202
Test name
Test status
Simulation time 11534996 ps
CPU time 0.56 seconds
Started May 23 12:32:09 PM PDT 24
Finished May 23 12:32:12 PM PDT 24
Peak memory 194080 kb
Host smart-71f679a9-0ea7-4799-bf26-3b41b2c15e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175720061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.4175720061
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1131889840
Short name T1242
Test name
Test status
Simulation time 50295163 ps
CPU time 0.77 seconds
Started May 23 12:32:10 PM PDT 24
Finished May 23 12:32:12 PM PDT 24
Peak memory 196840 kb
Host smart-f38d8818-5346-4128-aebf-abab46e5fce1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131889840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1131889840
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.749253861
Short name T1290
Test name
Test status
Simulation time 280123714 ps
CPU time 1.37 seconds
Started May 23 12:32:08 PM PDT 24
Finished May 23 12:32:11 PM PDT 24
Peak memory 199736 kb
Host smart-c14bd300-5fca-4082-8577-ad02cb20f869
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749253861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.749253861
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3999555574
Short name T89
Test name
Test status
Simulation time 43055957 ps
CPU time 0.9 seconds
Started May 23 12:32:11 PM PDT 24
Finished May 23 12:32:13 PM PDT 24
Peak memory 198240 kb
Host smart-6ec94660-8484-412a-8c88-cb695e014482
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999555574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3999555574
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1470372597
Short name T1269
Test name
Test status
Simulation time 117913436 ps
CPU time 0.97 seconds
Started May 23 12:32:07 PM PDT 24
Finished May 23 12:32:09 PM PDT 24
Peak memory 199564 kb
Host smart-69c44aec-0c3e-465f-ac9a-242151daf742
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470372597 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1470372597
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.984049327
Short name T1262
Test name
Test status
Simulation time 14911354 ps
CPU time 0.64 seconds
Started May 23 12:32:08 PM PDT 24
Finished May 23 12:32:11 PM PDT 24
Peak memory 195060 kb
Host smart-25d8e31a-375e-4a6e-a839-013ce21aaee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984049327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.984049327
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3073859018
Short name T1287
Test name
Test status
Simulation time 57718935 ps
CPU time 0.61 seconds
Started May 23 12:32:12 PM PDT 24
Finished May 23 12:32:14 PM PDT 24
Peak memory 194124 kb
Host smart-51f7614f-b860-4834-8e85-667efd93e2f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073859018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3073859018
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.484967947
Short name T80
Test name
Test status
Simulation time 109888014 ps
CPU time 0.66 seconds
Started May 23 12:32:09 PM PDT 24
Finished May 23 12:32:12 PM PDT 24
Peak memory 195100 kb
Host smart-2350b79b-107b-4b47-9b59-951055e379f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484967947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.484967947
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2075723932
Short name T1273
Test name
Test status
Simulation time 228646887 ps
CPU time 1.48 seconds
Started May 23 12:32:10 PM PDT 24
Finished May 23 12:32:13 PM PDT 24
Peak memory 199688 kb
Host smart-287e64a0-20ba-4a1e-b7d0-3a9d992720b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075723932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2075723932
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.90816331
Short name T1225
Test name
Test status
Simulation time 75954958 ps
CPU time 1.02 seconds
Started May 23 12:32:05 PM PDT 24
Finished May 23 12:32:07 PM PDT 24
Peak memory 199696 kb
Host smart-442dca97-ebaa-439e-b0fa-6c0815660bf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90816331 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.90816331
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.477929982
Short name T60
Test name
Test status
Simulation time 60375282 ps
CPU time 0.6 seconds
Started May 23 12:32:06 PM PDT 24
Finished May 23 12:32:08 PM PDT 24
Peak memory 195152 kb
Host smart-be9948b1-3d62-4357-a719-ab96349385b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477929982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.477929982
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2216883699
Short name T1286
Test name
Test status
Simulation time 15872481 ps
CPU time 0.56 seconds
Started May 23 12:32:10 PM PDT 24
Finished May 23 12:32:12 PM PDT 24
Peak memory 194036 kb
Host smart-71fb8e3b-7846-4123-a9d6-01190921408a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216883699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2216883699
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4095248998
Short name T1307
Test name
Test status
Simulation time 31954651 ps
CPU time 0.79 seconds
Started May 23 12:32:05 PM PDT 24
Finished May 23 12:32:07 PM PDT 24
Peak memory 196864 kb
Host smart-eeec70c0-656c-4389-9730-bbeb74a04d1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095248998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.4095248998
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.4253385460
Short name T1224
Test name
Test status
Simulation time 86841255 ps
CPU time 2.19 seconds
Started May 23 12:32:08 PM PDT 24
Finished May 23 12:32:13 PM PDT 24
Peak memory 199708 kb
Host smart-d22fb3c2-7e5e-4d09-9334-209cae3d7ecd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253385460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.4253385460
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1102610579
Short name T1276
Test name
Test status
Simulation time 178088148 ps
CPU time 0.9 seconds
Started May 23 12:32:10 PM PDT 24
Finished May 23 12:32:13 PM PDT 24
Peak memory 198748 kb
Host smart-268b82d4-3617-4d09-99bd-12885b2576b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102610579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1102610579
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.646027474
Short name T1220
Test name
Test status
Simulation time 29052212 ps
CPU time 0.65 seconds
Started May 23 12:32:22 PM PDT 24
Finished May 23 12:32:26 PM PDT 24
Peak memory 197416 kb
Host smart-7a551613-2899-4e69-8704-ee8cd9f05e7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646027474 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.646027474
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1665924125
Short name T84
Test name
Test status
Simulation time 40108968 ps
CPU time 0.58 seconds
Started May 23 12:32:22 PM PDT 24
Finished May 23 12:32:25 PM PDT 24
Peak memory 195068 kb
Host smart-0b0bea21-193c-4aa3-ac82-d3c144a92f5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665924125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1665924125
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.4072410271
Short name T1213
Test name
Test status
Simulation time 15740910 ps
CPU time 0.55 seconds
Started May 23 12:32:19 PM PDT 24
Finished May 23 12:32:20 PM PDT 24
Peak memory 194040 kb
Host smart-f9741077-5515-4b6b-9f23-afaa98a104a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072410271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.4072410271
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3704894419
Short name T1315
Test name
Test status
Simulation time 77662198 ps
CPU time 0.65 seconds
Started May 23 12:32:20 PM PDT 24
Finished May 23 12:32:22 PM PDT 24
Peak memory 195364 kb
Host smart-9b6a4629-517d-41bf-8491-d8aa032c6d60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704894419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3704894419
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3612619919
Short name T1192
Test name
Test status
Simulation time 42418752 ps
CPU time 2.22 seconds
Started May 23 12:32:06 PM PDT 24
Finished May 23 12:32:09 PM PDT 24
Peak memory 199692 kb
Host smart-6349c785-fbbe-472d-bebf-9ffa16fd13c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612619919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3612619919
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1556878525
Short name T87
Test name
Test status
Simulation time 1003251901 ps
CPU time 1.23 seconds
Started May 23 12:32:04 PM PDT 24
Finished May 23 12:32:07 PM PDT 24
Peak memory 198972 kb
Host smart-e160e07a-c3ed-4839-8d47-2e5ff7d9a123
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556878525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1556878525
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1302135534
Short name T1226
Test name
Test status
Simulation time 44354876 ps
CPU time 0.95 seconds
Started May 23 12:32:22 PM PDT 24
Finished May 23 12:32:25 PM PDT 24
Peak memory 199580 kb
Host smart-a68f0116-5b36-4092-bac5-4e189ab9d595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302135534 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1302135534
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1070302439
Short name T1271
Test name
Test status
Simulation time 25880637 ps
CPU time 0.6 seconds
Started May 23 12:32:24 PM PDT 24
Finished May 23 12:32:28 PM PDT 24
Peak memory 195136 kb
Host smart-3672291e-9e66-480f-b970-c3cfa3835f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070302439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1070302439
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.55792525
Short name T1297
Test name
Test status
Simulation time 17238745 ps
CPU time 0.56 seconds
Started May 23 12:32:22 PM PDT 24
Finished May 23 12:32:25 PM PDT 24
Peak memory 194036 kb
Host smart-c0253ffb-756c-4023-878e-f47e83ec6ba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55792525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.55792525
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3370839348
Short name T85
Test name
Test status
Simulation time 13287400 ps
CPU time 0.63 seconds
Started May 23 12:32:22 PM PDT 24
Finished May 23 12:32:25 PM PDT 24
Peak memory 194304 kb
Host smart-20407fa7-c769-4b91-a75d-635459347852
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370839348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3370839348
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3131232894
Short name T1209
Test name
Test status
Simulation time 60213946 ps
CPU time 1.57 seconds
Started May 23 12:32:23 PM PDT 24
Finished May 23 12:32:28 PM PDT 24
Peak memory 199772 kb
Host smart-6d8c14f1-7495-49bc-9842-a0e2293c1ae9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131232894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3131232894
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.864503542
Short name T93
Test name
Test status
Simulation time 181183419 ps
CPU time 0.92 seconds
Started May 23 12:32:22 PM PDT 24
Finished May 23 12:32:27 PM PDT 24
Peak memory 198576 kb
Host smart-378c82f4-cfe2-4d3e-b3c5-bfb068787578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864503542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.864503542
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2622794283
Short name T1279
Test name
Test status
Simulation time 16762984 ps
CPU time 0.81 seconds
Started May 23 12:32:20 PM PDT 24
Finished May 23 12:32:23 PM PDT 24
Peak memory 199536 kb
Host smart-741cdb3a-f9ee-4bea-be28-a34139aec29b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622794283 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2622794283
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3650779277
Short name T1245
Test name
Test status
Simulation time 24839485 ps
CPU time 0.61 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:25 PM PDT 24
Peak memory 195108 kb
Host smart-520a2eb3-4160-4b23-a724-986ac4fd4306
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650779277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3650779277
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3061704493
Short name T1197
Test name
Test status
Simulation time 38371571 ps
CPU time 0.55 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:25 PM PDT 24
Peak memory 194072 kb
Host smart-4920ee03-7b6f-4aa3-898d-e6e03fbbffb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061704493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3061704493
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1338898463
Short name T1318
Test name
Test status
Simulation time 14230015 ps
CPU time 0.61 seconds
Started May 23 12:32:25 PM PDT 24
Finished May 23 12:32:29 PM PDT 24
Peak memory 195220 kb
Host smart-3454d0af-fcb9-4764-abee-f9c8ab05c7d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338898463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1338898463
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1371033458
Short name T1289
Test name
Test status
Simulation time 31565522 ps
CPU time 1.53 seconds
Started May 23 12:32:19 PM PDT 24
Finished May 23 12:32:21 PM PDT 24
Peak memory 199708 kb
Host smart-a6e18826-648b-4cfd-9d06-2af0c2ec9319
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371033458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1371033458
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2151706100
Short name T95
Test name
Test status
Simulation time 251634838 ps
CPU time 1.29 seconds
Started May 23 12:32:20 PM PDT 24
Finished May 23 12:32:22 PM PDT 24
Peak memory 199120 kb
Host smart-ead80fbb-b533-4818-8945-4648e2c24174
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151706100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2151706100
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3445145171
Short name T1222
Test name
Test status
Simulation time 99356534 ps
CPU time 1.23 seconds
Started May 23 12:32:25 PM PDT 24
Finished May 23 12:32:30 PM PDT 24
Peak memory 199788 kb
Host smart-74ae7bd9-dac9-4a6b-8869-080ee1d911d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445145171 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3445145171
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3367574274
Short name T65
Test name
Test status
Simulation time 23435519 ps
CPU time 0.58 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:24 PM PDT 24
Peak memory 195120 kb
Host smart-04027cdf-aea1-4077-9cb2-c41ebe591856
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367574274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3367574274
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.4207784361
Short name T1259
Test name
Test status
Simulation time 15126167 ps
CPU time 0.55 seconds
Started May 23 12:32:24 PM PDT 24
Finished May 23 12:32:28 PM PDT 24
Peak memory 194044 kb
Host smart-9463c11a-1206-4885-aaa5-307b9730510d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207784361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.4207784361
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3964460451
Short name T1316
Test name
Test status
Simulation time 23026800 ps
CPU time 0.66 seconds
Started May 23 12:32:22 PM PDT 24
Finished May 23 12:32:25 PM PDT 24
Peak memory 195276 kb
Host smart-b72f05d6-0a40-4ba4-80ba-60927fa6b237
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964460451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3964460451
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3553825688
Short name T1308
Test name
Test status
Simulation time 818225310 ps
CPU time 1.56 seconds
Started May 23 12:32:23 PM PDT 24
Finished May 23 12:32:28 PM PDT 24
Peak memory 199740 kb
Host smart-f982d774-3cce-4d6e-9cf7-ebe85f179d0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553825688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3553825688
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1852137103
Short name T1288
Test name
Test status
Simulation time 183567188 ps
CPU time 0.94 seconds
Started May 23 12:32:20 PM PDT 24
Finished May 23 12:32:22 PM PDT 24
Peak memory 198572 kb
Host smart-d19c2cbf-225c-41e8-8780-e7716fb49355
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852137103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1852137103
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.136128203
Short name T1223
Test name
Test status
Simulation time 117710672 ps
CPU time 1.5 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:25 PM PDT 24
Peak memory 199680 kb
Host smart-3c70d0f2-8bb8-4323-b5d2-2e60c9735461
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136128203 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.136128203
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2571334810
Short name T79
Test name
Test status
Simulation time 13492523 ps
CPU time 0.63 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:23 PM PDT 24
Peak memory 195248 kb
Host smart-ab0741bc-ac1c-4ff8-80de-6a98aeb8f870
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571334810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2571334810
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3230171337
Short name T1201
Test name
Test status
Simulation time 51234037 ps
CPU time 0.57 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:24 PM PDT 24
Peak memory 194008 kb
Host smart-29fb19fc-219d-4579-a8ba-a849ce163c81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230171337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3230171337
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1062440823
Short name T1219
Test name
Test status
Simulation time 31751387 ps
CPU time 0.59 seconds
Started May 23 12:32:24 PM PDT 24
Finished May 23 12:32:28 PM PDT 24
Peak memory 195188 kb
Host smart-abc4d95a-c0bd-40aa-a8f4-2d7b790397dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062440823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1062440823
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1628437618
Short name T1188
Test name
Test status
Simulation time 559588587 ps
CPU time 2.32 seconds
Started May 23 12:32:23 PM PDT 24
Finished May 23 12:32:29 PM PDT 24
Peak memory 199756 kb
Host smart-7195ca06-a4c5-45eb-96ca-a5211719af3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628437618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1628437618
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2264577621
Short name T88
Test name
Test status
Simulation time 200344721 ps
CPU time 0.96 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:24 PM PDT 24
Peak memory 198448 kb
Host smart-29dd98c7-afa2-49c0-bfdc-19b5759059dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264577621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2264577621
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3719715751
Short name T1234
Test name
Test status
Simulation time 33876292 ps
CPU time 0.81 seconds
Started May 23 12:31:51 PM PDT 24
Finished May 23 12:31:53 PM PDT 24
Peak memory 196028 kb
Host smart-13575ecd-525a-44e4-9415-f3c92a8a2ec3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719715751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3719715751
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1381678
Short name T1237
Test name
Test status
Simulation time 463535866 ps
CPU time 2.64 seconds
Started May 23 12:31:50 PM PDT 24
Finished May 23 12:31:54 PM PDT 24
Peak memory 197396 kb
Host smart-00f0611b-6c9d-4e38-8f66-ca81e712fe7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1381678
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.39703298
Short name T1283
Test name
Test status
Simulation time 48531886 ps
CPU time 0.63 seconds
Started May 23 12:31:40 PM PDT 24
Finished May 23 12:31:42 PM PDT 24
Peak memory 195040 kb
Host smart-8749106e-57a6-4cc8-aff1-8b29aa38cd82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39703298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.39703298
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1522780523
Short name T1186
Test name
Test status
Simulation time 117594072 ps
CPU time 0.88 seconds
Started May 23 12:31:52 PM PDT 24
Finished May 23 12:31:55 PM PDT 24
Peak memory 198780 kb
Host smart-c064df1f-fb03-449e-93e5-eb0fed883d19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522780523 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1522780523
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2310582271
Short name T1233
Test name
Test status
Simulation time 12398592 ps
CPU time 0.56 seconds
Started May 23 12:31:53 PM PDT 24
Finished May 23 12:31:55 PM PDT 24
Peak memory 194764 kb
Host smart-9843233b-d64e-4751-b758-f07503ea7ef7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310582271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2310582271
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3545853492
Short name T1228
Test name
Test status
Simulation time 71527594 ps
CPU time 0.55 seconds
Started May 23 12:31:39 PM PDT 24
Finished May 23 12:31:41 PM PDT 24
Peak memory 194232 kb
Host smart-02419263-3431-4631-a74e-3e50909315d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545853492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3545853492
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.978759730
Short name T1309
Test name
Test status
Simulation time 28916386 ps
CPU time 0.73 seconds
Started May 23 12:31:52 PM PDT 24
Finished May 23 12:31:55 PM PDT 24
Peak memory 196504 kb
Host smart-f2619705-798c-4e78-b7ae-29763d7998d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978759730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.978759730
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.588212399
Short name T1293
Test name
Test status
Simulation time 19821741 ps
CPU time 1.08 seconds
Started May 23 12:31:39 PM PDT 24
Finished May 23 12:31:42 PM PDT 24
Peak memory 199540 kb
Host smart-28d60963-7f50-4513-8bf2-4869141da174
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588212399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.588212399
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1586456708
Short name T1258
Test name
Test status
Simulation time 22382476 ps
CPU time 0.57 seconds
Started May 23 12:32:24 PM PDT 24
Finished May 23 12:32:28 PM PDT 24
Peak memory 194092 kb
Host smart-56cddb0c-f4b8-4b43-9b54-fc7e2649f919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586456708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1586456708
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.499661503
Short name T1238
Test name
Test status
Simulation time 14338747 ps
CPU time 0.55 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:23 PM PDT 24
Peak memory 193988 kb
Host smart-174d7623-2dee-4245-b87c-95f32bbd7baf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499661503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.499661503
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3291450396
Short name T1231
Test name
Test status
Simulation time 64020667 ps
CPU time 0.57 seconds
Started May 23 12:32:23 PM PDT 24
Finished May 23 12:32:27 PM PDT 24
Peak memory 194064 kb
Host smart-e3b6799f-e270-4a70-9d73-ba7b72dff599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291450396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3291450396
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.342660724
Short name T1199
Test name
Test status
Simulation time 30643626 ps
CPU time 0.56 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:25 PM PDT 24
Peak memory 194000 kb
Host smart-992a8726-cf77-4cc8-bbfe-46020a97b63f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342660724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.342660724
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3466053639
Short name T1204
Test name
Test status
Simulation time 95028511 ps
CPU time 0.55 seconds
Started May 23 12:32:25 PM PDT 24
Finished May 23 12:32:29 PM PDT 24
Peak memory 194012 kb
Host smart-c4cbeed2-47a7-4538-8724-dc10b9255d3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466053639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3466053639
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3373021631
Short name T1227
Test name
Test status
Simulation time 52508625 ps
CPU time 0.6 seconds
Started May 23 12:32:22 PM PDT 24
Finished May 23 12:32:26 PM PDT 24
Peak memory 194108 kb
Host smart-7e65e07f-cf68-4dce-a785-14d7f76f4c9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373021631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3373021631
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1217806415
Short name T1319
Test name
Test status
Simulation time 11890790 ps
CPU time 0.59 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:23 PM PDT 24
Peak memory 194256 kb
Host smart-9c25e963-db1a-4c3b-b46b-0c98a9ab18ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217806415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1217806415
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1606914604
Short name T1267
Test name
Test status
Simulation time 63396902 ps
CPU time 0.64 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:23 PM PDT 24
Peak memory 194244 kb
Host smart-1ba5bffb-6674-44bb-9a65-b03031b0d8b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606914604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1606914604
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1910459530
Short name T1257
Test name
Test status
Simulation time 40956139 ps
CPU time 0.55 seconds
Started May 23 12:32:20 PM PDT 24
Finished May 23 12:32:22 PM PDT 24
Peak memory 194052 kb
Host smart-f6035dbe-1843-438a-a1ce-26fbfbff0dd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910459530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1910459530
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.266779553
Short name T1265
Test name
Test status
Simulation time 16949905 ps
CPU time 0.6 seconds
Started May 23 12:32:22 PM PDT 24
Finished May 23 12:32:26 PM PDT 24
Peak memory 194036 kb
Host smart-22e1eccf-88e7-4cb0-b8e3-eb2f34d40127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266779553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.266779553
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.221235738
Short name T1230
Test name
Test status
Simulation time 75237601 ps
CPU time 0.66 seconds
Started May 23 12:31:51 PM PDT 24
Finished May 23 12:31:53 PM PDT 24
Peak memory 195076 kb
Host smart-d080c3da-1adf-4431-98a6-2e030ec4db47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221235738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.221235738
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.932526110
Short name T1311
Test name
Test status
Simulation time 393248970 ps
CPU time 1.47 seconds
Started May 23 12:31:52 PM PDT 24
Finished May 23 12:31:56 PM PDT 24
Peak memory 197120 kb
Host smart-be98c4fe-9d67-49cf-a962-3dd84a1f5fce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932526110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.932526110
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2543089860
Short name T1205
Test name
Test status
Simulation time 167425316 ps
CPU time 0.6 seconds
Started May 23 12:31:50 PM PDT 24
Finished May 23 12:31:52 PM PDT 24
Peak memory 195204 kb
Host smart-eaa1747d-1564-4da0-9b13-e590404e3acd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543089860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2543089860
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4051675381
Short name T1196
Test name
Test status
Simulation time 34148732 ps
CPU time 0.68 seconds
Started May 23 12:31:51 PM PDT 24
Finished May 23 12:31:54 PM PDT 24
Peak memory 197408 kb
Host smart-ad668cf5-d851-4019-9db7-0df4f9647e16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051675381 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.4051675381
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1727402662
Short name T1282
Test name
Test status
Simulation time 36421181 ps
CPU time 0.6 seconds
Started May 23 12:31:51 PM PDT 24
Finished May 23 12:31:53 PM PDT 24
Peak memory 195268 kb
Host smart-d4bd1cd5-3b9f-47a8-a918-6054ed71bbd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727402662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1727402662
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.457606111
Short name T1210
Test name
Test status
Simulation time 49823909 ps
CPU time 0.6 seconds
Started May 23 12:31:51 PM PDT 24
Finished May 23 12:31:54 PM PDT 24
Peak memory 194048 kb
Host smart-aeb5d7a6-5419-4733-86b4-38547b8fcee7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457606111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.457606111
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.652145895
Short name T1272
Test name
Test status
Simulation time 18074302 ps
CPU time 0.67 seconds
Started May 23 12:31:50 PM PDT 24
Finished May 23 12:31:51 PM PDT 24
Peak memory 197200 kb
Host smart-144efd91-2cbc-4ca9-817d-15535763bf70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652145895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.652145895
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3828079046
Short name T1206
Test name
Test status
Simulation time 253801534 ps
CPU time 1.45 seconds
Started May 23 12:31:53 PM PDT 24
Finished May 23 12:31:56 PM PDT 24
Peak memory 199708 kb
Host smart-6069bcd2-6c69-4c1d-982b-06c52ebe7bbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828079046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3828079046
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3416036934
Short name T96
Test name
Test status
Simulation time 278515681 ps
CPU time 0.93 seconds
Started May 23 12:31:51 PM PDT 24
Finished May 23 12:31:53 PM PDT 24
Peak memory 198740 kb
Host smart-6104e9f0-2121-4965-b081-5d9687e97eb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416036934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3416036934
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1742620353
Short name T1208
Test name
Test status
Simulation time 42967186 ps
CPU time 0.54 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:25 PM PDT 24
Peak memory 194040 kb
Host smart-a31c55c9-383c-4d48-a8c0-4bfb954a870d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742620353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1742620353
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3268017530
Short name T1299
Test name
Test status
Simulation time 64008347 ps
CPU time 0.57 seconds
Started May 23 12:32:23 PM PDT 24
Finished May 23 12:32:28 PM PDT 24
Peak memory 194144 kb
Host smart-a6cbcdae-2fb7-4d20-9ac2-78df70986f05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268017530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3268017530
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2867065235
Short name T1285
Test name
Test status
Simulation time 11740527 ps
CPU time 0.56 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:24 PM PDT 24
Peak memory 194100 kb
Host smart-e15857cf-6e90-4603-b932-33af2f2ec767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867065235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2867065235
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.349691210
Short name T1200
Test name
Test status
Simulation time 22953735 ps
CPU time 0.61 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:25 PM PDT 24
Peak memory 194064 kb
Host smart-33a45fae-c42e-4f83-968a-68c33488bce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349691210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.349691210
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1872744882
Short name T1212
Test name
Test status
Simulation time 33245887 ps
CPU time 0.57 seconds
Started May 23 12:32:22 PM PDT 24
Finished May 23 12:32:26 PM PDT 24
Peak memory 194048 kb
Host smart-fbadbe7f-1df3-4dcc-99ac-6cdc0fca61b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872744882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1872744882
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.369932351
Short name T1284
Test name
Test status
Simulation time 29629423 ps
CPU time 0.58 seconds
Started May 23 12:32:22 PM PDT 24
Finished May 23 12:32:27 PM PDT 24
Peak memory 194140 kb
Host smart-2c05666e-326d-40c7-a1da-42bf0b948efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369932351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.369932351
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1147071520
Short name T1303
Test name
Test status
Simulation time 17904928 ps
CPU time 0.6 seconds
Started May 23 12:32:24 PM PDT 24
Finished May 23 12:32:28 PM PDT 24
Peak memory 194160 kb
Host smart-0093fc69-c459-463d-a251-eb46df34d94a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147071520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1147071520
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.791828683
Short name T1247
Test name
Test status
Simulation time 89504183 ps
CPU time 0.56 seconds
Started May 23 12:32:25 PM PDT 24
Finished May 23 12:32:29 PM PDT 24
Peak memory 194036 kb
Host smart-8928425d-8c8f-426d-ad87-510238703345
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791828683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.791828683
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1241875682
Short name T1239
Test name
Test status
Simulation time 38893557 ps
CPU time 0.58 seconds
Started May 23 12:32:23 PM PDT 24
Finished May 23 12:32:28 PM PDT 24
Peak memory 194152 kb
Host smart-76223c9a-906a-4d65-ab47-59b7621c142c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241875682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1241875682
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.760956236
Short name T1189
Test name
Test status
Simulation time 22920073 ps
CPU time 0.61 seconds
Started May 23 12:32:23 PM PDT 24
Finished May 23 12:32:28 PM PDT 24
Peak memory 194088 kb
Host smart-a3ad0299-680c-4cce-92cd-a1e5da0ca2bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760956236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.760956236
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2430185326
Short name T1261
Test name
Test status
Simulation time 75078461 ps
CPU time 0.67 seconds
Started May 23 12:31:51 PM PDT 24
Finished May 23 12:31:54 PM PDT 24
Peak memory 194592 kb
Host smart-3a24a74a-e457-4949-a098-7271d903ec10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430185326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2430185326
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.150589986
Short name T1317
Test name
Test status
Simulation time 93438946 ps
CPU time 1.48 seconds
Started May 23 12:31:50 PM PDT 24
Finished May 23 12:31:53 PM PDT 24
Peak memory 197332 kb
Host smart-07f9544a-144c-4575-8054-70609cf5fe7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150589986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.150589986
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.693525432
Short name T1264
Test name
Test status
Simulation time 15738122 ps
CPU time 0.63 seconds
Started May 23 12:31:50 PM PDT 24
Finished May 23 12:31:51 PM PDT 24
Peak memory 195028 kb
Host smart-eba976ab-3515-43dd-87bf-1201710d138b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693525432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.693525432
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.662027854
Short name T1250
Test name
Test status
Simulation time 65451000 ps
CPU time 0.88 seconds
Started May 23 12:31:52 PM PDT 24
Finished May 23 12:31:55 PM PDT 24
Peak memory 199516 kb
Host smart-c402c152-7a29-400a-96fa-2a1bb844e589
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662027854 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.662027854
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2250903025
Short name T77
Test name
Test status
Simulation time 34010400 ps
CPU time 0.6 seconds
Started May 23 12:31:51 PM PDT 24
Finished May 23 12:31:53 PM PDT 24
Peak memory 195072 kb
Host smart-3be961bc-5d7a-400d-a26c-688f6ccbe1ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250903025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2250903025
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1230072564
Short name T1194
Test name
Test status
Simulation time 12786290 ps
CPU time 0.55 seconds
Started May 23 12:31:51 PM PDT 24
Finished May 23 12:31:54 PM PDT 24
Peak memory 194028 kb
Host smart-ddf26622-6bdd-4ce5-9356-78d6ea08553f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230072564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1230072564
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1695760181
Short name T1256
Test name
Test status
Simulation time 70199326 ps
CPU time 0.68 seconds
Started May 23 12:31:53 PM PDT 24
Finished May 23 12:31:55 PM PDT 24
Peak memory 195640 kb
Host smart-4d93d1ba-b856-44ba-ae67-d0b72ae6ed0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695760181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1695760181
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2212441755
Short name T1221
Test name
Test status
Simulation time 35099666 ps
CPU time 1.68 seconds
Started May 23 12:31:50 PM PDT 24
Finished May 23 12:31:52 PM PDT 24
Peak memory 199736 kb
Host smart-439d240c-48a2-4d61-8cd3-f44aa7666677
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212441755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2212441755
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.904059613
Short name T124
Test name
Test status
Simulation time 261423444 ps
CPU time 1.24 seconds
Started May 23 12:31:52 PM PDT 24
Finished May 23 12:31:55 PM PDT 24
Peak memory 199016 kb
Host smart-22942c2b-1e2a-4554-9ce7-50c6cfbb34e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904059613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.904059613
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2140038933
Short name T1214
Test name
Test status
Simulation time 19834706 ps
CPU time 0.59 seconds
Started May 23 12:32:22 PM PDT 24
Finished May 23 12:32:26 PM PDT 24
Peak memory 194044 kb
Host smart-5a5e5442-aa55-4261-b4a3-4334cac3173a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140038933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2140038933
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3991542066
Short name T1266
Test name
Test status
Simulation time 19954238 ps
CPU time 0.56 seconds
Started May 23 12:32:23 PM PDT 24
Finished May 23 12:32:28 PM PDT 24
Peak memory 194108 kb
Host smart-4ea8c21c-e0cf-4a63-b151-e76d3b9d2c17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991542066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3991542066
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3094775855
Short name T1240
Test name
Test status
Simulation time 37084444 ps
CPU time 0.57 seconds
Started May 23 12:32:21 PM PDT 24
Finished May 23 12:32:25 PM PDT 24
Peak memory 194056 kb
Host smart-a4e48830-32d1-4f65-a808-8ebf387cf0c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094775855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3094775855
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2769008810
Short name T1274
Test name
Test status
Simulation time 45247084 ps
CPU time 0.56 seconds
Started May 23 12:32:23 PM PDT 24
Finished May 23 12:32:28 PM PDT 24
Peak memory 194076 kb
Host smart-9f1c3a31-9492-469c-a567-23a3d702c686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769008810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2769008810
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.347453337
Short name T1301
Test name
Test status
Simulation time 19628160 ps
CPU time 0.55 seconds
Started May 23 12:32:38 PM PDT 24
Finished May 23 12:32:41 PM PDT 24
Peak memory 193976 kb
Host smart-9ac8565e-a83c-48b0-871b-ddfeee1fc25d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347453337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.347453337
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2912373060
Short name T1218
Test name
Test status
Simulation time 33733757 ps
CPU time 0.55 seconds
Started May 23 12:32:40 PM PDT 24
Finished May 23 12:32:42 PM PDT 24
Peak memory 194116 kb
Host smart-227184b4-722e-437b-9942-8fa2f9d024d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912373060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2912373060
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3091667885
Short name T1251
Test name
Test status
Simulation time 13631860 ps
CPU time 0.59 seconds
Started May 23 12:32:33 PM PDT 24
Finished May 23 12:32:36 PM PDT 24
Peak memory 194120 kb
Host smart-fd26cec1-1de9-4c5c-bddc-1eb5b90a257a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091667885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3091667885
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1807229295
Short name T1243
Test name
Test status
Simulation time 22225097 ps
CPU time 0.59 seconds
Started May 23 12:32:32 PM PDT 24
Finished May 23 12:32:34 PM PDT 24
Peak memory 194188 kb
Host smart-f47aac1f-ce36-4fdd-a10a-1b5ad35dec32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807229295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1807229295
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3640806428
Short name T1302
Test name
Test status
Simulation time 53235917 ps
CPU time 0.57 seconds
Started May 23 12:32:32 PM PDT 24
Finished May 23 12:32:34 PM PDT 24
Peak memory 194056 kb
Host smart-ca7e9c6b-ee16-4ab9-8c5b-7d571463abb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640806428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3640806428
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3560148506
Short name T1211
Test name
Test status
Simulation time 20157765 ps
CPU time 0.62 seconds
Started May 23 12:32:34 PM PDT 24
Finished May 23 12:32:36 PM PDT 24
Peak memory 194044 kb
Host smart-a4975171-eaac-484a-843a-ed1189a891b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560148506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3560148506
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3494643633
Short name T1305
Test name
Test status
Simulation time 31600844 ps
CPU time 1.49 seconds
Started May 23 12:31:50 PM PDT 24
Finished May 23 12:31:53 PM PDT 24
Peak memory 199752 kb
Host smart-1eae5956-7c7a-4182-99f7-129fdd7b2604
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494643633 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3494643633
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1869046762
Short name T1291
Test name
Test status
Simulation time 48117666 ps
CPU time 0.61 seconds
Started May 23 12:31:51 PM PDT 24
Finished May 23 12:31:53 PM PDT 24
Peak memory 195256 kb
Host smart-d498ea9f-1502-4d71-932c-29dd7338f8f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869046762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1869046762
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1804551881
Short name T1306
Test name
Test status
Simulation time 12767012 ps
CPU time 0.56 seconds
Started May 23 12:31:50 PM PDT 24
Finished May 23 12:31:52 PM PDT 24
Peak memory 194064 kb
Host smart-baff4f37-0f55-49a3-b562-1f28eba50249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804551881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1804551881
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1741173626
Short name T1229
Test name
Test status
Simulation time 97771824 ps
CPU time 0.73 seconds
Started May 23 12:31:52 PM PDT 24
Finished May 23 12:31:55 PM PDT 24
Peak memory 196464 kb
Host smart-6299828b-b642-42be-8f52-23fc05b22eda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741173626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1741173626
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3348298331
Short name T1187
Test name
Test status
Simulation time 97422252 ps
CPU time 2.24 seconds
Started May 23 12:31:50 PM PDT 24
Finished May 23 12:31:53 PM PDT 24
Peak memory 199716 kb
Host smart-33e16b06-ebbd-4426-b85d-99cebb49d50e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348298331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3348298331
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3268513082
Short name T1300
Test name
Test status
Simulation time 369231028 ps
CPU time 1.34 seconds
Started May 23 12:31:51 PM PDT 24
Finished May 23 12:31:54 PM PDT 24
Peak memory 199032 kb
Host smart-edeb12d1-0899-4e8b-a8df-5c6739342858
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268513082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3268513082
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1693828758
Short name T1281
Test name
Test status
Simulation time 53782946 ps
CPU time 1.27 seconds
Started May 23 12:32:04 PM PDT 24
Finished May 23 12:32:07 PM PDT 24
Peak memory 199708 kb
Host smart-10ef8dd3-f1d3-4426-a8c6-e99d8b4296a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693828758 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1693828758
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3054917026
Short name T1217
Test name
Test status
Simulation time 24400317 ps
CPU time 0.58 seconds
Started May 23 12:32:07 PM PDT 24
Finished May 23 12:32:09 PM PDT 24
Peak memory 195048 kb
Host smart-18f5abdd-9031-4c4f-9652-8418635773b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054917026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3054917026
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2986154360
Short name T1310
Test name
Test status
Simulation time 11450408 ps
CPU time 0.56 seconds
Started May 23 12:32:05 PM PDT 24
Finished May 23 12:32:07 PM PDT 24
Peak memory 194160 kb
Host smart-c2cfacac-f1e8-43a2-896a-5d556d08e487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986154360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2986154360
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.347015548
Short name T1260
Test name
Test status
Simulation time 14504353 ps
CPU time 0.64 seconds
Started May 23 12:32:04 PM PDT 24
Finished May 23 12:32:06 PM PDT 24
Peak memory 194432 kb
Host smart-74627dd3-ad7f-4065-b4f7-b7e76773182a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347015548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.347015548
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3232699821
Short name T1296
Test name
Test status
Simulation time 24054611 ps
CPU time 1.17 seconds
Started May 23 12:31:50 PM PDT 24
Finished May 23 12:31:52 PM PDT 24
Peak memory 199756 kb
Host smart-90964bd8-42bd-4c0b-9428-2dc402fd0ef0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232699821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3232699821
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1819376948
Short name T1203
Test name
Test status
Simulation time 91851812 ps
CPU time 0.74 seconds
Started May 23 12:32:09 PM PDT 24
Finished May 23 12:32:12 PM PDT 24
Peak memory 198804 kb
Host smart-c29cb58c-d839-4354-84c6-de4ba8e84c03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819376948 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1819376948
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3867639105
Short name T83
Test name
Test status
Simulation time 14917372 ps
CPU time 0.57 seconds
Started May 23 12:32:05 PM PDT 24
Finished May 23 12:32:06 PM PDT 24
Peak memory 195048 kb
Host smart-d3beea00-77fb-4478-b9a2-7426aedc5c4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867639105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3867639105
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1451730736
Short name T1215
Test name
Test status
Simulation time 64207159 ps
CPU time 0.58 seconds
Started May 23 12:32:05 PM PDT 24
Finished May 23 12:32:07 PM PDT 24
Peak memory 194008 kb
Host smart-84f276a1-273a-4534-9db4-47d34356d873
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451730736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1451730736
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1049833721
Short name T1277
Test name
Test status
Simulation time 21546769 ps
CPU time 0.72 seconds
Started May 23 12:32:04 PM PDT 24
Finished May 23 12:32:06 PM PDT 24
Peak memory 195600 kb
Host smart-423cc7e7-3f3a-4df7-8797-ebb9fa95a472
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049833721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1049833721
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1642250141
Short name T1263
Test name
Test status
Simulation time 137119224 ps
CPU time 1.93 seconds
Started May 23 12:32:07 PM PDT 24
Finished May 23 12:32:11 PM PDT 24
Peak memory 199736 kb
Host smart-46240b5a-317d-4079-a3c7-241ec8faff31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642250141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1642250141
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3899462436
Short name T1216
Test name
Test status
Simulation time 570445036 ps
CPU time 0.97 seconds
Started May 23 12:32:06 PM PDT 24
Finished May 23 12:32:08 PM PDT 24
Peak memory 198612 kb
Host smart-166752a8-1cff-4af5-8f58-80bf272b12bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899462436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3899462436
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2557399089
Short name T1253
Test name
Test status
Simulation time 89341618 ps
CPU time 0.72 seconds
Started May 23 12:32:06 PM PDT 24
Finished May 23 12:32:09 PM PDT 24
Peak memory 198272 kb
Host smart-fcb93ea7-d507-4aee-acb6-6bffc3530310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557399089 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2557399089
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3059119853
Short name T64
Test name
Test status
Simulation time 15907853 ps
CPU time 0.66 seconds
Started May 23 12:32:07 PM PDT 24
Finished May 23 12:32:09 PM PDT 24
Peak memory 195104 kb
Host smart-8c871d45-1546-44f6-89f0-d0f4944ab93b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059119853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3059119853
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.903553148
Short name T1195
Test name
Test status
Simulation time 28584583 ps
CPU time 0.58 seconds
Started May 23 12:32:05 PM PDT 24
Finished May 23 12:32:06 PM PDT 24
Peak memory 194104 kb
Host smart-78f54529-99d0-40ec-9e5e-9723dcbc294d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903553148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.903553148
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1622753591
Short name T1241
Test name
Test status
Simulation time 20101662 ps
CPU time 0.74 seconds
Started May 23 12:32:09 PM PDT 24
Finished May 23 12:32:12 PM PDT 24
Peak memory 197480 kb
Host smart-0677efdc-4c16-426f-9eec-e1db257f6562
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622753591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1622753591
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.4147519269
Short name T1190
Test name
Test status
Simulation time 40604904 ps
CPU time 1.5 seconds
Started May 23 12:32:07 PM PDT 24
Finished May 23 12:32:10 PM PDT 24
Peak memory 199712 kb
Host smart-37683ea5-99cb-4499-bfd2-ca7c18b986c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147519269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.4147519269
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.326279080
Short name T122
Test name
Test status
Simulation time 318638582 ps
CPU time 1.31 seconds
Started May 23 12:32:06 PM PDT 24
Finished May 23 12:32:09 PM PDT 24
Peak memory 199044 kb
Host smart-ce92c94c-32d0-43d5-b5ff-b9173fc368b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326279080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.326279080
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.515236953
Short name T1298
Test name
Test status
Simulation time 135025516 ps
CPU time 0.89 seconds
Started May 23 12:32:06 PM PDT 24
Finished May 23 12:32:08 PM PDT 24
Peak memory 199556 kb
Host smart-dcf944f5-ca4d-404b-b8fa-56423bd21415
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515236953 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.515236953
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2323685949
Short name T61
Test name
Test status
Simulation time 47658318 ps
CPU time 0.62 seconds
Started May 23 12:32:05 PM PDT 24
Finished May 23 12:32:08 PM PDT 24
Peak memory 195144 kb
Host smart-6e2861e2-4e83-4650-951a-3b46ef5d1f12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323685949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2323685949
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3481054424
Short name T1254
Test name
Test status
Simulation time 40867167 ps
CPU time 0.58 seconds
Started May 23 12:32:08 PM PDT 24
Finished May 23 12:32:10 PM PDT 24
Peak memory 194040 kb
Host smart-02db2538-70d7-423a-9c17-0231e629039a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481054424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3481054424
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.373144595
Short name T1313
Test name
Test status
Simulation time 73956088 ps
CPU time 0.68 seconds
Started May 23 12:32:08 PM PDT 24
Finished May 23 12:32:11 PM PDT 24
Peak memory 196512 kb
Host smart-199f9859-867b-41d0-969f-24141c731fb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373144595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.373144595
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.727281293
Short name T1294
Test name
Test status
Simulation time 112998112 ps
CPU time 2.18 seconds
Started May 23 12:32:08 PM PDT 24
Finished May 23 12:32:13 PM PDT 24
Peak memory 199700 kb
Host smart-11c6efad-e5c9-4fc4-9b4f-8a88deeaa1ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727281293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.727281293
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2719030417
Short name T86
Test name
Test status
Simulation time 160538787 ps
CPU time 0.99 seconds
Started May 23 12:32:07 PM PDT 24
Finished May 23 12:32:10 PM PDT 24
Peak memory 198556 kb
Host smart-a0dedf1e-132b-4812-b068-9b8ccb093f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719030417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2719030417
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2459345535
Short name T780
Test name
Test status
Simulation time 138650384 ps
CPU time 0.56 seconds
Started May 23 12:43:56 PM PDT 24
Finished May 23 12:43:58 PM PDT 24
Peak memory 195740 kb
Host smart-6242e9c7-64ea-4669-8ed4-83f316a67b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459345535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2459345535
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.4111872036
Short name T428
Test name
Test status
Simulation time 68782619700 ps
CPU time 105.74 seconds
Started May 23 12:43:52 PM PDT 24
Finished May 23 12:45:39 PM PDT 24
Peak memory 200156 kb
Host smart-a4f6f50f-99df-4877-ba84-78b5de071463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111872036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.4111872036
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1035124615
Short name T1027
Test name
Test status
Simulation time 30324409970 ps
CPU time 51.67 seconds
Started May 23 12:43:40 PM PDT 24
Finished May 23 12:44:33 PM PDT 24
Peak memory 200280 kb
Host smart-a98f76c6-b42a-44ee-8d5e-1e81934dee54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035124615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1035124615
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1849833031
Short name T835
Test name
Test status
Simulation time 131257457313 ps
CPU time 118.2 seconds
Started May 23 12:43:53 PM PDT 24
Finished May 23 12:45:52 PM PDT 24
Peak memory 200380 kb
Host smart-8ad313f6-8142-4f8c-b8c8-474705eb6b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849833031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1849833031
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.592888504
Short name T419
Test name
Test status
Simulation time 129528442823 ps
CPU time 46.56 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:44:34 PM PDT 24
Peak memory 199264 kb
Host smart-91c5fe24-2096-438e-af66-03d7a7066a98
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592888504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.592888504
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1843104185
Short name T825
Test name
Test status
Simulation time 81104237552 ps
CPU time 362.08 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:49:51 PM PDT 24
Peak memory 200380 kb
Host smart-d67f1b7a-f44f-44e9-a38f-81cde49983d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1843104185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1843104185
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3550000901
Short name T1127
Test name
Test status
Simulation time 9983949944 ps
CPU time 12.63 seconds
Started May 23 12:43:51 PM PDT 24
Finished May 23 12:44:05 PM PDT 24
Peak memory 198756 kb
Host smart-b6893ae6-8c8d-47c5-a149-321ca99417be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550000901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3550000901
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3383425468
Short name T74
Test name
Test status
Simulation time 2875761404 ps
CPU time 4.85 seconds
Started May 23 12:43:49 PM PDT 24
Finished May 23 12:43:56 PM PDT 24
Peak memory 200404 kb
Host smart-576e8e4e-df14-4e81-ac24-2032af1336db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383425468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3383425468
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3058214608
Short name T306
Test name
Test status
Simulation time 5799020732 ps
CPU time 68.25 seconds
Started May 23 12:43:50 PM PDT 24
Finished May 23 12:45:00 PM PDT 24
Peak memory 200344 kb
Host smart-2e0696ef-e356-451f-8d6b-7f1328461ad5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3058214608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3058214608
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1384051119
Short name T936
Test name
Test status
Simulation time 3127515376 ps
CPU time 12.66 seconds
Started May 23 12:43:50 PM PDT 24
Finished May 23 12:44:04 PM PDT 24
Peak memory 199456 kb
Host smart-08fadde2-c1eb-41cd-b674-4fcca94e87b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384051119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1384051119
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2207579479
Short name T487
Test name
Test status
Simulation time 161645775202 ps
CPU time 117.69 seconds
Started May 23 12:43:50 PM PDT 24
Finished May 23 12:45:50 PM PDT 24
Peak memory 200236 kb
Host smart-30769a6b-af3f-4222-84b0-31d993b14070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207579479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2207579479
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.666028964
Short name T738
Test name
Test status
Simulation time 3072166850 ps
CPU time 2.04 seconds
Started May 23 12:43:43 PM PDT 24
Finished May 23 12:43:46 PM PDT 24
Peak memory 196384 kb
Host smart-537c61e7-771a-40d1-82f4-3d4fdc6eb107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666028964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.666028964
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3367242052
Short name T672
Test name
Test status
Simulation time 306774574 ps
CPU time 2.44 seconds
Started May 23 12:43:53 PM PDT 24
Finished May 23 12:43:56 PM PDT 24
Peak memory 199928 kb
Host smart-20052a0f-7c4d-4ace-9e69-bbe588d5665c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367242052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3367242052
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1812933556
Short name T1154
Test name
Test status
Simulation time 27374395688 ps
CPU time 495.61 seconds
Started May 23 12:43:47 PM PDT 24
Finished May 23 12:52:05 PM PDT 24
Peak memory 216844 kb
Host smart-978fb7bb-0e45-45f8-870d-17bf28f37563
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812933556 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1812933556
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1502169401
Short name T562
Test name
Test status
Simulation time 8275484901 ps
CPU time 7.69 seconds
Started May 23 12:43:50 PM PDT 24
Finished May 23 12:44:00 PM PDT 24
Peak memory 200112 kb
Host smart-6929a4f2-4bdb-4efb-8a62-9aaec04120eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502169401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1502169401
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1892048812
Short name T511
Test name
Test status
Simulation time 43143949560 ps
CPU time 62.6 seconds
Started May 23 12:43:46 PM PDT 24
Finished May 23 12:44:51 PM PDT 24
Peak memory 200348 kb
Host smart-d8757e6e-b6f5-4a9f-af30-30cdd4fb5012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892048812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1892048812
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.412363374
Short name T674
Test name
Test status
Simulation time 197701157 ps
CPU time 0.57 seconds
Started May 23 12:43:47 PM PDT 24
Finished May 23 12:43:50 PM PDT 24
Peak memory 195644 kb
Host smart-66d8d7ff-7437-43c2-97bf-4b5990689304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412363374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.412363374
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3722170638
Short name T523
Test name
Test status
Simulation time 302065265768 ps
CPU time 349.82 seconds
Started May 23 12:43:45 PM PDT 24
Finished May 23 12:49:37 PM PDT 24
Peak memory 200312 kb
Host smart-7b67da31-e23a-405a-9689-d03f06c4304e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722170638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3722170638
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3492702838
Short name T73
Test name
Test status
Simulation time 62110416242 ps
CPU time 30.33 seconds
Started May 23 12:43:45 PM PDT 24
Finished May 23 12:44:17 PM PDT 24
Peak memory 200292 kb
Host smart-c14f7755-9f27-44b3-81eb-c718cc1faefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492702838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3492702838
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.4086441373
Short name T700
Test name
Test status
Simulation time 71267242633 ps
CPU time 60.76 seconds
Started May 23 12:43:55 PM PDT 24
Finished May 23 12:44:57 PM PDT 24
Peak memory 200260 kb
Host smart-7cfbdee1-45ef-4810-811f-76ef43068309
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086441373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.4086441373
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3844587766
Short name T669
Test name
Test status
Simulation time 85821931600 ps
CPU time 499.63 seconds
Started May 23 12:43:52 PM PDT 24
Finished May 23 12:52:13 PM PDT 24
Peak memory 200356 kb
Host smart-9d52193d-a15a-4efc-b2a3-d41001dbbd58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3844587766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3844587766
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1175663384
Short name T46
Test name
Test status
Simulation time 4346026345 ps
CPU time 4.06 seconds
Started May 23 12:43:52 PM PDT 24
Finished May 23 12:43:57 PM PDT 24
Peak memory 198612 kb
Host smart-5ddacbc4-e8ea-4259-9d9f-5d128f708a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175663384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1175663384
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.348893626
Short name T874
Test name
Test status
Simulation time 105174232696 ps
CPU time 209.37 seconds
Started May 23 12:43:48 PM PDT 24
Finished May 23 12:47:20 PM PDT 24
Peak memory 208576 kb
Host smart-4ef37205-fa23-436d-be24-538087e6b426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348893626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.348893626
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3179857549
Short name T1147
Test name
Test status
Simulation time 20255157826 ps
CPU time 432.87 seconds
Started May 23 12:43:47 PM PDT 24
Finished May 23 12:51:02 PM PDT 24
Peak memory 200356 kb
Host smart-76355eb2-0ff3-46fd-8a4b-128277d7111c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179857549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3179857549
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2624595245
Short name T580
Test name
Test status
Simulation time 4853953701 ps
CPU time 8.39 seconds
Started May 23 12:43:45 PM PDT 24
Finished May 23 12:43:55 PM PDT 24
Peak memory 199440 kb
Host smart-b39897f2-879b-4f9a-af7a-a3d6e61069b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2624595245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2624595245
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3256846658
Short name T889
Test name
Test status
Simulation time 227915175986 ps
CPU time 196.16 seconds
Started May 23 12:43:55 PM PDT 24
Finished May 23 12:47:12 PM PDT 24
Peak memory 200288 kb
Host smart-ef66c107-2dfc-42cd-b931-22466aa7a717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256846658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3256846658
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2090558334
Short name T388
Test name
Test status
Simulation time 38299574316 ps
CPU time 14.41 seconds
Started May 23 12:43:43 PM PDT 24
Finished May 23 12:43:59 PM PDT 24
Peak memory 196424 kb
Host smart-b2270413-6d61-4171-a53c-7021d78bd01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090558334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2090558334
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3560387892
Short name T98
Test name
Test status
Simulation time 128324472 ps
CPU time 0.81 seconds
Started May 23 12:43:47 PM PDT 24
Finished May 23 12:43:50 PM PDT 24
Peak memory 218752 kb
Host smart-53ea9c68-4b01-45f0-8b21-a9cfdbc3feef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560387892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3560387892
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2567794704
Short name T739
Test name
Test status
Simulation time 648427640 ps
CPU time 3.7 seconds
Started May 23 12:43:48 PM PDT 24
Finished May 23 12:43:54 PM PDT 24
Peak memory 199244 kb
Host smart-eb0c2af3-b727-435d-acad-67749727bcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567794704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2567794704
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1734179563
Short name T1040
Test name
Test status
Simulation time 163132762178 ps
CPU time 465.58 seconds
Started May 23 12:43:50 PM PDT 24
Finished May 23 12:51:38 PM PDT 24
Peak memory 200360 kb
Host smart-77378266-fef4-4cbb-b95a-3a37c24ca553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734179563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1734179563
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.165923756
Short name T847
Test name
Test status
Simulation time 218981403294 ps
CPU time 527.71 seconds
Started May 23 12:43:51 PM PDT 24
Finished May 23 12:52:40 PM PDT 24
Peak memory 225276 kb
Host smart-a456b792-f0f0-4dd1-be0c-8a5670aa84ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165923756 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.165923756
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2618534144
Short name T369
Test name
Test status
Simulation time 1027802526 ps
CPU time 2.16 seconds
Started May 23 12:43:57 PM PDT 24
Finished May 23 12:44:01 PM PDT 24
Peak memory 199968 kb
Host smart-944bcd3a-5311-4654-a845-0dccab4fe781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618534144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2618534144
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3661665674
Short name T324
Test name
Test status
Simulation time 16966560842 ps
CPU time 29.24 seconds
Started May 23 12:43:51 PM PDT 24
Finished May 23 12:44:22 PM PDT 24
Peak memory 200336 kb
Host smart-78304b12-6cc5-4e5c-a8a3-8e9198bc6021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661665674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3661665674
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3721919977
Short name T141
Test name
Test status
Simulation time 269086476547 ps
CPU time 127.89 seconds
Started May 23 12:44:14 PM PDT 24
Finished May 23 12:46:24 PM PDT 24
Peak memory 200384 kb
Host smart-88a33f6a-5099-46d2-b72c-76fb0e750b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721919977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3721919977
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3257002286
Short name T159
Test name
Test status
Simulation time 106880548345 ps
CPU time 44.28 seconds
Started May 23 12:44:20 PM PDT 24
Finished May 23 12:45:06 PM PDT 24
Peak memory 200296 kb
Host smart-9d905d12-7673-479c-9d17-a80b4da2b1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257002286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3257002286
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3821837710
Short name T693
Test name
Test status
Simulation time 102158567350 ps
CPU time 179.09 seconds
Started May 23 12:44:08 PM PDT 24
Finished May 23 12:47:09 PM PDT 24
Peak memory 200376 kb
Host smart-c7d065f8-e84e-4abf-9e54-0df89d11e177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821837710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3821837710
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3525721220
Short name T1121
Test name
Test status
Simulation time 56059217000 ps
CPU time 7.3 seconds
Started May 23 12:44:16 PM PDT 24
Finished May 23 12:44:25 PM PDT 24
Peak memory 200104 kb
Host smart-7547bbe8-7467-4407-b8a6-cc4cef8bb622
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525721220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3525721220
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.836988728
Short name T262
Test name
Test status
Simulation time 204173835494 ps
CPU time 1525.81 seconds
Started May 23 12:44:14 PM PDT 24
Finished May 23 01:09:41 PM PDT 24
Peak memory 200316 kb
Host smart-cb5d9cda-5040-49c3-ac56-2b6b4b88b780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836988728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.836988728
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.188597893
Short name T1166
Test name
Test status
Simulation time 2798958094 ps
CPU time 1.81 seconds
Started May 23 12:44:09 PM PDT 24
Finished May 23 12:44:13 PM PDT 24
Peak memory 198900 kb
Host smart-6ac9d55f-b586-4f28-8356-766d34cac3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188597893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.188597893
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3021354504
Short name T1094
Test name
Test status
Simulation time 69246484355 ps
CPU time 15.25 seconds
Started May 23 12:44:12 PM PDT 24
Finished May 23 12:44:29 PM PDT 24
Peak memory 195156 kb
Host smart-6e32bc69-fed9-4afc-b6ba-6f1775d1da52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021354504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3021354504
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2625840348
Short name T930
Test name
Test status
Simulation time 5442972385 ps
CPU time 147.87 seconds
Started May 23 12:44:11 PM PDT 24
Finished May 23 12:46:40 PM PDT 24
Peak memory 200284 kb
Host smart-21174d8c-21bd-4099-940d-cca08f5cd144
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625840348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2625840348
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.4098972120
Short name T944
Test name
Test status
Simulation time 2425404199 ps
CPU time 3.31 seconds
Started May 23 12:44:17 PM PDT 24
Finished May 23 12:44:21 PM PDT 24
Peak memory 198820 kb
Host smart-22262964-27eb-4507-b5f2-2d04a8b7329f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098972120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.4098972120
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.90667533
Short name T300
Test name
Test status
Simulation time 187426314464 ps
CPU time 412.53 seconds
Started May 23 12:44:12 PM PDT 24
Finished May 23 12:51:06 PM PDT 24
Peak memory 200416 kb
Host smart-f18a0b29-9a42-48a0-9a9a-ca240a0b186b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90667533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.90667533
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3947372944
Short name T1076
Test name
Test status
Simulation time 464312000 ps
CPU time 1.05 seconds
Started May 23 12:44:09 PM PDT 24
Finished May 23 12:44:12 PM PDT 24
Peak memory 196032 kb
Host smart-f272a785-8113-486e-9b68-d93d460d21f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947372944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3947372944
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2574997612
Short name T1026
Test name
Test status
Simulation time 520515489 ps
CPU time 1.66 seconds
Started May 23 12:44:08 PM PDT 24
Finished May 23 12:44:11 PM PDT 24
Peak memory 200192 kb
Host smart-d21e9aad-6ce9-4f30-be4b-6f509ae7c167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574997612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2574997612
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.710104235
Short name T735
Test name
Test status
Simulation time 176207422425 ps
CPU time 380.73 seconds
Started May 23 12:44:16 PM PDT 24
Finished May 23 12:50:38 PM PDT 24
Peak memory 200380 kb
Host smart-9f3b7eec-fe6f-4814-8222-a91d935aa005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710104235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.710104235
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.4115582025
Short name T100
Test name
Test status
Simulation time 328616236723 ps
CPU time 1315.65 seconds
Started May 23 12:44:10 PM PDT 24
Finished May 23 01:06:07 PM PDT 24
Peak memory 217184 kb
Host smart-9ef89f36-59a0-43fd-831e-f06ab5dcfad8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115582025 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.4115582025
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.449575703
Short name T457
Test name
Test status
Simulation time 6658989951 ps
CPU time 19.02 seconds
Started May 23 12:44:19 PM PDT 24
Finished May 23 12:44:39 PM PDT 24
Peak memory 200440 kb
Host smart-e2feb2f0-5182-4e6b-bb28-0231c21f5da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449575703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.449575703
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1502864977
Short name T514
Test name
Test status
Simulation time 183160753112 ps
CPU time 186.44 seconds
Started May 23 12:44:11 PM PDT 24
Finished May 23 12:47:20 PM PDT 24
Peak memory 200300 kb
Host smart-ac3d8d11-1155-444e-bef9-4725ab6f22cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502864977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1502864977
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1110025986
Short name T1101
Test name
Test status
Simulation time 74806711106 ps
CPU time 24.3 seconds
Started May 23 12:47:04 PM PDT 24
Finished May 23 12:47:29 PM PDT 24
Peak memory 200344 kb
Host smart-7c8cf6a8-db1d-4b48-b36d-e3d751a7af27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110025986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1110025986
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2902533456
Short name T1085
Test name
Test status
Simulation time 151406995154 ps
CPU time 50.15 seconds
Started May 23 12:47:04 PM PDT 24
Finished May 23 12:47:56 PM PDT 24
Peak memory 200324 kb
Host smart-df8fc8f8-14e2-49fe-8e13-eb5d81a80409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902533456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2902533456
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2399253277
Short name T127
Test name
Test status
Simulation time 49601293888 ps
CPU time 50.02 seconds
Started May 23 12:47:04 PM PDT 24
Finished May 23 12:47:56 PM PDT 24
Peak memory 200392 kb
Host smart-af5b8c95-6b25-4964-88dc-d693c89bec91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399253277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2399253277
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1422909813
Short name T213
Test name
Test status
Simulation time 61146604456 ps
CPU time 23.05 seconds
Started May 23 12:47:03 PM PDT 24
Finished May 23 12:47:28 PM PDT 24
Peak memory 200436 kb
Host smart-c304770c-d1cf-4647-9723-9e744052292d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422909813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1422909813
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.631816330
Short name T620
Test name
Test status
Simulation time 172205739154 ps
CPU time 132.64 seconds
Started May 23 12:47:04 PM PDT 24
Finished May 23 12:49:18 PM PDT 24
Peak memory 200336 kb
Host smart-b151f6bb-8b42-4e9c-805e-a39d802c820e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631816330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.631816330
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.359255056
Short name T1065
Test name
Test status
Simulation time 157968352287 ps
CPU time 24.11 seconds
Started May 23 12:47:05 PM PDT 24
Finished May 23 12:47:30 PM PDT 24
Peak memory 200412 kb
Host smart-164e86bd-81fc-4189-89d2-aed8ac7265d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359255056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.359255056
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3448344243
Short name T954
Test name
Test status
Simulation time 60195699544 ps
CPU time 170.53 seconds
Started May 23 12:47:06 PM PDT 24
Finished May 23 12:49:58 PM PDT 24
Peak memory 200436 kb
Host smart-50c1ddf5-08d1-4e29-8e42-6a0764bade9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448344243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3448344243
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1938822814
Short name T118
Test name
Test status
Simulation time 9708554451 ps
CPU time 15.98 seconds
Started May 23 12:47:05 PM PDT 24
Finished May 23 12:47:22 PM PDT 24
Peak memory 200296 kb
Host smart-debfe9d1-f8e7-42ee-a9fa-3c0685324a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938822814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1938822814
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2319191605
Short name T103
Test name
Test status
Simulation time 64086912 ps
CPU time 0.53 seconds
Started May 23 12:44:14 PM PDT 24
Finished May 23 12:44:16 PM PDT 24
Peak memory 195704 kb
Host smart-0aed89ee-f226-49b1-8d47-053bc7c0528c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319191605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2319191605
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1771373458
Short name T1001
Test name
Test status
Simulation time 39874020936 ps
CPU time 76.04 seconds
Started May 23 12:44:10 PM PDT 24
Finished May 23 12:45:28 PM PDT 24
Peak memory 200336 kb
Host smart-542de444-67a8-4329-a89b-b3266dc13529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771373458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1771373458
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1887665459
Short name T1011
Test name
Test status
Simulation time 16105020607 ps
CPU time 11.72 seconds
Started May 23 12:44:11 PM PDT 24
Finished May 23 12:44:24 PM PDT 24
Peak memory 200420 kb
Host smart-660f4dd7-f180-46d6-91f7-48d1ec0c07b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887665459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1887665459
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1909980360
Short name T804
Test name
Test status
Simulation time 94731904699 ps
CPU time 38.41 seconds
Started May 23 12:44:09 PM PDT 24
Finished May 23 12:44:49 PM PDT 24
Peak memory 200316 kb
Host smart-f79e8b8d-a624-4f24-9b9a-9c54ba9ec8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909980360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1909980360
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.560833585
Short name T926
Test name
Test status
Simulation time 8058997036 ps
CPU time 7.64 seconds
Started May 23 12:44:08 PM PDT 24
Finished May 23 12:44:18 PM PDT 24
Peak memory 197760 kb
Host smart-3f6ec7d7-4412-492f-b5ed-8b5b0cbfee77
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560833585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.560833585
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3500135439
Short name T860
Test name
Test status
Simulation time 53498538802 ps
CPU time 322.45 seconds
Started May 23 12:44:14 PM PDT 24
Finished May 23 12:49:38 PM PDT 24
Peak memory 200288 kb
Host smart-911ef77c-5a78-453d-923f-9f289e820f85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3500135439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3500135439
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1007337883
Short name T919
Test name
Test status
Simulation time 10292388051 ps
CPU time 6.56 seconds
Started May 23 12:44:12 PM PDT 24
Finished May 23 12:44:20 PM PDT 24
Peak memory 200384 kb
Host smart-4624c529-f530-4d2a-92c0-88235b0ebb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007337883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1007337883
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3679770175
Short name T1128
Test name
Test status
Simulation time 67830885001 ps
CPU time 29.36 seconds
Started May 23 12:44:12 PM PDT 24
Finished May 23 12:44:43 PM PDT 24
Peak memory 198248 kb
Host smart-6a634be6-8a20-4e00-bf85-701684ac4a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679770175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3679770175
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.874442996
Short name T916
Test name
Test status
Simulation time 21722863140 ps
CPU time 195.52 seconds
Started May 23 12:44:14 PM PDT 24
Finished May 23 12:47:31 PM PDT 24
Peak memory 200452 kb
Host smart-f31e817d-f5bf-4b4a-8ca8-280e66ce104e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874442996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.874442996
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.975742002
Short name T873
Test name
Test status
Simulation time 5105937488 ps
CPU time 44.67 seconds
Started May 23 12:44:17 PM PDT 24
Finished May 23 12:45:03 PM PDT 24
Peak memory 200424 kb
Host smart-072df1f6-2b25-40c6-a177-e19df9a4a9c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975742002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.975742002
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1358775141
Short name T1130
Test name
Test status
Simulation time 24432908159 ps
CPU time 43.92 seconds
Started May 23 12:44:13 PM PDT 24
Finished May 23 12:44:58 PM PDT 24
Peak memory 200028 kb
Host smart-adda1cef-f4ef-4c74-afd5-e16d1450dd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358775141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1358775141
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3052698483
Short name T302
Test name
Test status
Simulation time 39567783161 ps
CPU time 59.96 seconds
Started May 23 12:44:12 PM PDT 24
Finished May 23 12:45:14 PM PDT 24
Peak memory 196188 kb
Host smart-a508f6b1-1753-47d0-b215-2810dc2a40b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052698483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3052698483
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2906687852
Short name T876
Test name
Test status
Simulation time 11666426829 ps
CPU time 10.06 seconds
Started May 23 12:44:14 PM PDT 24
Finished May 23 12:44:26 PM PDT 24
Peak memory 200272 kb
Host smart-be1553dc-911c-426b-99d5-0c754b84be5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906687852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2906687852
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2510974801
Short name T19
Test name
Test status
Simulation time 1269766634 ps
CPU time 2.09 seconds
Started May 23 12:44:08 PM PDT 24
Finished May 23 12:44:12 PM PDT 24
Peak memory 198380 kb
Host smart-dd571252-2cd1-43f4-a887-bc3e085eb236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510974801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2510974801
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.628948096
Short name T904
Test name
Test status
Simulation time 8202604314 ps
CPU time 13.54 seconds
Started May 23 12:44:18 PM PDT 24
Finished May 23 12:44:32 PM PDT 24
Peak memory 200340 kb
Host smart-6cf9551c-cf94-4349-862c-bf734998d05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628948096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.628948096
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3399132073
Short name T344
Test name
Test status
Simulation time 24426727655 ps
CPU time 11.92 seconds
Started May 23 12:47:06 PM PDT 24
Finished May 23 12:47:19 PM PDT 24
Peak memory 200396 kb
Host smart-6ca041f0-0efc-4b82-b9b6-879ae43b7fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399132073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3399132073
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3830686121
Short name T105
Test name
Test status
Simulation time 53135594774 ps
CPU time 29.76 seconds
Started May 23 12:47:19 PM PDT 24
Finished May 23 12:47:50 PM PDT 24
Peak memory 200452 kb
Host smart-3898027f-8d8d-4d19-985c-15a0c9d6fc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830686121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3830686121
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.389827684
Short name T209
Test name
Test status
Simulation time 52612615358 ps
CPU time 293.98 seconds
Started May 23 12:47:19 PM PDT 24
Finished May 23 12:52:15 PM PDT 24
Peak memory 200456 kb
Host smart-4d3610dc-6d6b-45fc-bf43-9b71ee1b7fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389827684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.389827684
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1372745043
Short name T1102
Test name
Test status
Simulation time 20637484793 ps
CPU time 33.15 seconds
Started May 23 12:47:19 PM PDT 24
Finished May 23 12:47:54 PM PDT 24
Peak memory 200396 kb
Host smart-ae663dc9-0b8d-4375-b83e-ffd879ebfab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372745043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1372745043
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1144687332
Short name T195
Test name
Test status
Simulation time 98321608244 ps
CPU time 161.97 seconds
Started May 23 12:47:21 PM PDT 24
Finished May 23 12:50:04 PM PDT 24
Peak memory 200332 kb
Host smart-4059123e-b780-4a18-b1bc-e06b1d5a4ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144687332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1144687332
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1754646931
Short name T167
Test name
Test status
Simulation time 21635986446 ps
CPU time 33.22 seconds
Started May 23 12:47:19 PM PDT 24
Finished May 23 12:47:54 PM PDT 24
Peak memory 200292 kb
Host smart-9b2ec0f0-59a5-45ce-b649-627043a79991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754646931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1754646931
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2596251650
Short name T1183
Test name
Test status
Simulation time 51230977577 ps
CPU time 238.86 seconds
Started May 23 12:47:20 PM PDT 24
Finished May 23 12:51:20 PM PDT 24
Peak memory 200444 kb
Host smart-6d75aa6b-6ebb-4438-a71b-0358e7149a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596251650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2596251650
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3214381608
Short name T355
Test name
Test status
Simulation time 36616634 ps
CPU time 0.54 seconds
Started May 23 12:44:22 PM PDT 24
Finished May 23 12:44:24 PM PDT 24
Peak memory 195256 kb
Host smart-611a6874-a7f6-4497-bdcf-71397b78990f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214381608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3214381608
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2667015026
Short name T817
Test name
Test status
Simulation time 162289906326 ps
CPU time 288.29 seconds
Started May 23 12:44:17 PM PDT 24
Finished May 23 12:49:07 PM PDT 24
Peak memory 200464 kb
Host smart-9d661452-64ef-4834-bbc7-51c787cf0404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667015026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2667015026
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.468176092
Short name T377
Test name
Test status
Simulation time 19348673944 ps
CPU time 39.86 seconds
Started May 23 12:44:18 PM PDT 24
Finished May 23 12:45:05 PM PDT 24
Peak memory 200404 kb
Host smart-336cda07-5261-4ec1-b0bc-b2012780a158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468176092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.468176092
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.308414405
Short name T367
Test name
Test status
Simulation time 139314129679 ps
CPU time 59.89 seconds
Started May 23 12:44:12 PM PDT 24
Finished May 23 12:45:13 PM PDT 24
Peak memory 200324 kb
Host smart-9d7d6819-d1b4-494d-a494-47e3ce504883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308414405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.308414405
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.4148820052
Short name T1159
Test name
Test status
Simulation time 687638104648 ps
CPU time 1081.24 seconds
Started May 23 12:44:16 PM PDT 24
Finished May 23 01:02:19 PM PDT 24
Peak memory 200056 kb
Host smart-ca5c3895-b910-4391-a055-1feb24ce401c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148820052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.4148820052
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3884117151
Short name T610
Test name
Test status
Simulation time 143637093909 ps
CPU time 764.17 seconds
Started May 23 12:44:21 PM PDT 24
Finished May 23 12:57:07 PM PDT 24
Peak memory 199808 kb
Host smart-cd902a65-7bbb-4c39-9dd6-2957f1b870df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3884117151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3884117151
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3857917732
Short name T581
Test name
Test status
Simulation time 10164244143 ps
CPU time 18.34 seconds
Started May 23 12:44:22 PM PDT 24
Finished May 23 12:44:42 PM PDT 24
Peak memory 200408 kb
Host smart-dda912e3-38b7-4ab7-9293-775266370357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857917732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3857917732
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2880585453
Short name T531
Test name
Test status
Simulation time 55989786662 ps
CPU time 117.04 seconds
Started May 23 12:44:17 PM PDT 24
Finished May 23 12:46:16 PM PDT 24
Peak memory 200696 kb
Host smart-60eebc27-1f45-4c4e-8864-d645d159f2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880585453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2880585453
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1523694514
Short name T680
Test name
Test status
Simulation time 4626554481 ps
CPU time 232.57 seconds
Started May 23 12:44:19 PM PDT 24
Finished May 23 12:48:12 PM PDT 24
Peak memory 200196 kb
Host smart-ae7835bf-8838-4af4-a775-66154741f410
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523694514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1523694514
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2684890368
Short name T354
Test name
Test status
Simulation time 4127018158 ps
CPU time 8.62 seconds
Started May 23 12:44:09 PM PDT 24
Finished May 23 12:44:20 PM PDT 24
Peak memory 198492 kb
Host smart-d3d7eebb-cd0d-44ee-a951-74259616cb2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2684890368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2684890368
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1274598764
Short name T967
Test name
Test status
Simulation time 26846435946 ps
CPU time 11.21 seconds
Started May 23 12:44:23 PM PDT 24
Finished May 23 12:44:36 PM PDT 24
Peak memory 199468 kb
Host smart-448ddda5-baae-4596-a12b-1d8e1bbc4c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274598764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1274598764
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1664815967
Short name T1113
Test name
Test status
Simulation time 696936980 ps
CPU time 1.47 seconds
Started May 23 12:44:19 PM PDT 24
Finished May 23 12:44:22 PM PDT 24
Peak memory 195940 kb
Host smart-bf9bc8fa-1eb7-4f94-809c-cb3dc584a01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664815967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1664815967
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1412674938
Short name T588
Test name
Test status
Simulation time 264055602 ps
CPU time 1.55 seconds
Started May 23 12:44:13 PM PDT 24
Finished May 23 12:44:16 PM PDT 24
Peak memory 199136 kb
Host smart-50a8218a-adcc-4348-8fb3-11ed4fc522f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412674938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1412674938
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.2452765260
Short name T165
Test name
Test status
Simulation time 217349793608 ps
CPU time 574.21 seconds
Started May 23 12:44:18 PM PDT 24
Finished May 23 12:53:53 PM PDT 24
Peak memory 200916 kb
Host smart-31ec86e9-7baf-40db-8811-22aa6abdffa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452765260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2452765260
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.799879198
Short name T1095
Test name
Test status
Simulation time 102024929759 ps
CPU time 248.05 seconds
Started May 23 12:44:22 PM PDT 24
Finished May 23 12:48:32 PM PDT 24
Peak memory 217116 kb
Host smart-77642f2b-cf10-4703-9930-cb798ab81ffb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799879198 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.799879198
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.166097851
Short name T1028
Test name
Test status
Simulation time 6451158028 ps
CPU time 17.92 seconds
Started May 23 12:44:18 PM PDT 24
Finished May 23 12:44:37 PM PDT 24
Peak memory 200200 kb
Host smart-28960eaf-a9fe-4407-9484-0f983901adae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166097851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.166097851
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.282348226
Short name T815
Test name
Test status
Simulation time 121158304309 ps
CPU time 154.28 seconds
Started May 23 12:44:18 PM PDT 24
Finished May 23 12:46:54 PM PDT 24
Peak memory 200336 kb
Host smart-b98846c7-a3bd-4f9d-bf82-bc349afbd5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282348226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.282348226
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.649989942
Short name T777
Test name
Test status
Simulation time 114766741967 ps
CPU time 45.13 seconds
Started May 23 12:47:18 PM PDT 24
Finished May 23 12:48:05 PM PDT 24
Peak memory 200308 kb
Host smart-1a7007a1-e724-42b2-91fc-b66a199fadce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649989942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.649989942
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.4177295651
Short name T170
Test name
Test status
Simulation time 100615668066 ps
CPU time 85.18 seconds
Started May 23 12:47:18 PM PDT 24
Finished May 23 12:48:44 PM PDT 24
Peak memory 200428 kb
Host smart-0f1981ff-61c1-4459-a949-d947aa40671d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177295651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.4177295651
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2114149507
Short name T39
Test name
Test status
Simulation time 9539590031 ps
CPU time 20.73 seconds
Started May 23 12:47:17 PM PDT 24
Finished May 23 12:47:39 PM PDT 24
Peak memory 200320 kb
Host smart-69b4dc40-4383-4896-8c15-0feb9e42c2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114149507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2114149507
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2239737558
Short name T756
Test name
Test status
Simulation time 71475391839 ps
CPU time 78 seconds
Started May 23 12:47:18 PM PDT 24
Finished May 23 12:48:37 PM PDT 24
Peak memory 200432 kb
Host smart-c0fc8847-0e2e-4a82-99b8-3e5f85a80024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239737558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2239737558
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3356320616
Short name T699
Test name
Test status
Simulation time 25809205693 ps
CPU time 40.73 seconds
Started May 23 12:47:22 PM PDT 24
Finished May 23 12:48:04 PM PDT 24
Peak memory 200292 kb
Host smart-a39b5668-4278-43a1-a9ee-8dfa57b3d189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356320616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3356320616
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2790558287
Short name T604
Test name
Test status
Simulation time 143278751979 ps
CPU time 70.73 seconds
Started May 23 12:47:18 PM PDT 24
Finished May 23 12:48:30 PM PDT 24
Peak memory 200344 kb
Host smart-5e13bb7e-4ff2-49d1-b9ac-56508d268459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790558287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2790558287
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3635553515
Short name T585
Test name
Test status
Simulation time 114078511737 ps
CPU time 186.71 seconds
Started May 23 12:47:21 PM PDT 24
Finished May 23 12:50:29 PM PDT 24
Peak memory 200364 kb
Host smart-0fbe1564-4c58-4eba-9541-647be2e0cb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635553515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3635553515
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1388908359
Short name T410
Test name
Test status
Simulation time 59462942808 ps
CPU time 29.86 seconds
Started May 23 12:47:18 PM PDT 24
Finished May 23 12:47:49 PM PDT 24
Peak memory 200452 kb
Host smart-97ba3e13-4144-4bc8-a65e-cc328a182a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388908359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1388908359
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1998145339
Short name T189
Test name
Test status
Simulation time 147108019896 ps
CPU time 121.08 seconds
Started May 23 12:47:19 PM PDT 24
Finished May 23 12:49:22 PM PDT 24
Peak memory 200308 kb
Host smart-33ba9926-0b5e-4f05-8efd-6c459d5d118f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998145339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1998145339
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1904935540
Short name T582
Test name
Test status
Simulation time 14776595 ps
CPU time 0.62 seconds
Started May 23 12:44:18 PM PDT 24
Finished May 23 12:44:20 PM PDT 24
Peak memory 195216 kb
Host smart-536d487a-9847-421d-a66e-ad350d8ce072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904935540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1904935540
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1782932672
Short name T1056
Test name
Test status
Simulation time 17098136968 ps
CPU time 28.19 seconds
Started May 23 12:44:17 PM PDT 24
Finished May 23 12:44:47 PM PDT 24
Peak memory 200412 kb
Host smart-cae2c00e-4ec2-4f10-8904-6eb65dccbfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782932672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1782932672
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2188673884
Short name T305
Test name
Test status
Simulation time 100649172740 ps
CPU time 187.55 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:47:34 PM PDT 24
Peak memory 200264 kb
Host smart-dbeacb23-99be-4364-8a34-35055570bfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188673884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2188673884
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.473813079
Short name T640
Test name
Test status
Simulation time 151398848623 ps
CPU time 213.67 seconds
Started May 23 12:44:22 PM PDT 24
Finished May 23 12:47:57 PM PDT 24
Peak memory 200400 kb
Host smart-3fc4ea0f-b0e0-4c41-9f75-371116839f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473813079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.473813079
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1395770205
Short name T698
Test name
Test status
Simulation time 70182790953 ps
CPU time 30.78 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:44:57 PM PDT 24
Peak memory 200368 kb
Host smart-6189e047-47c8-4a5d-a625-8ea87f5e0e40
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395770205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1395770205
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3788653344
Short name T990
Test name
Test status
Simulation time 95261133142 ps
CPU time 495.7 seconds
Started May 23 12:44:20 PM PDT 24
Finished May 23 12:52:37 PM PDT 24
Peak memory 200352 kb
Host smart-aac05da5-bde2-4654-b6ce-8e75e3767629
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3788653344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3788653344
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2854381587
Short name T989
Test name
Test status
Simulation time 2355529853 ps
CPU time 1.7 seconds
Started May 23 12:44:23 PM PDT 24
Finished May 23 12:44:27 PM PDT 24
Peak memory 197912 kb
Host smart-4291a785-75bb-426d-bc6e-957ccdf0b44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854381587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2854381587
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.1858307667
Short name T268
Test name
Test status
Simulation time 5937197391 ps
CPU time 295.95 seconds
Started May 23 12:44:21 PM PDT 24
Finished May 23 12:49:19 PM PDT 24
Peak memory 200372 kb
Host smart-d9fba3c2-0416-4709-b926-2a970758fc78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1858307667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1858307667
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.128690455
Short name T789
Test name
Test status
Simulation time 5386989988 ps
CPU time 18.2 seconds
Started May 23 12:44:27 PM PDT 24
Finished May 23 12:44:47 PM PDT 24
Peak memory 198560 kb
Host smart-ca982f64-1864-4247-8d51-3862db91e538
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=128690455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.128690455
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3332496995
Short name T258
Test name
Test status
Simulation time 45876123600 ps
CPU time 20.27 seconds
Started May 23 12:44:20 PM PDT 24
Finished May 23 12:44:42 PM PDT 24
Peak memory 200308 kb
Host smart-20b4b181-d384-44e5-9bb9-39f2331e50cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332496995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3332496995
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3431374177
Short name T1062
Test name
Test status
Simulation time 3961559343 ps
CPU time 6.7 seconds
Started May 23 12:44:21 PM PDT 24
Finished May 23 12:44:30 PM PDT 24
Peak memory 196028 kb
Host smart-c1c90b52-3378-4714-bb64-854bab375894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431374177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3431374177
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2396294778
Short name T649
Test name
Test status
Simulation time 494292984 ps
CPU time 1.08 seconds
Started May 23 12:44:21 PM PDT 24
Finished May 23 12:44:23 PM PDT 24
Peak memory 198948 kb
Host smart-86c27b30-b5c7-46c9-8351-f634989c8db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396294778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2396294778
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.802554351
Short name T365
Test name
Test status
Simulation time 1143212557 ps
CPU time 4.26 seconds
Started May 23 12:44:20 PM PDT 24
Finished May 23 12:44:25 PM PDT 24
Peak memory 200168 kb
Host smart-19746f67-e782-4412-92dc-915e250ed7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802554351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.802554351
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1004653575
Short name T472
Test name
Test status
Simulation time 122793385873 ps
CPU time 237.38 seconds
Started May 23 12:44:20 PM PDT 24
Finished May 23 12:48:19 PM PDT 24
Peak memory 200420 kb
Host smart-489469f4-4e97-45f4-8b7d-cc1e00f77b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004653575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1004653575
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2616683043
Short name T175
Test name
Test status
Simulation time 118314229131 ps
CPU time 43.84 seconds
Started May 23 12:47:19 PM PDT 24
Finished May 23 12:48:05 PM PDT 24
Peak memory 200548 kb
Host smart-5a8b1294-706e-4c18-baa3-5c838646e905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616683043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2616683043
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2910944796
Short name T206
Test name
Test status
Simulation time 33592753786 ps
CPU time 30.97 seconds
Started May 23 12:47:22 PM PDT 24
Finished May 23 12:47:54 PM PDT 24
Peak memory 200472 kb
Host smart-c762ae23-bdb8-4ef0-9189-e4c8c473e213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910944796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2910944796
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.4201295013
Short name T924
Test name
Test status
Simulation time 81457411498 ps
CPU time 165.23 seconds
Started May 23 12:47:20 PM PDT 24
Finished May 23 12:50:07 PM PDT 24
Peak memory 200496 kb
Host smart-d8167659-d488-4606-afdd-457e74bc67aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201295013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.4201295013
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2542781169
Short name T183
Test name
Test status
Simulation time 131123281323 ps
CPU time 74.33 seconds
Started May 23 12:47:23 PM PDT 24
Finished May 23 12:48:39 PM PDT 24
Peak memory 200440 kb
Host smart-1658dfd4-b874-4a11-b8e4-38ecb2d0492e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542781169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2542781169
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1389648045
Short name T241
Test name
Test status
Simulation time 4472155119 ps
CPU time 8.79 seconds
Started May 23 12:47:20 PM PDT 24
Finished May 23 12:47:30 PM PDT 24
Peak memory 200308 kb
Host smart-983fbd6b-dddf-4694-92a3-2702340737f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389648045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1389648045
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.4068362688
Short name T205
Test name
Test status
Simulation time 67262139273 ps
CPU time 111.92 seconds
Started May 23 12:47:22 PM PDT 24
Finished May 23 12:49:16 PM PDT 24
Peak memory 200108 kb
Host smart-addfa7cd-53d8-4d15-a002-e4e816e86a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068362688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4068362688
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3202950436
Short name T443
Test name
Test status
Simulation time 19130579449 ps
CPU time 34.9 seconds
Started May 23 12:47:22 PM PDT 24
Finished May 23 12:47:58 PM PDT 24
Peak memory 200340 kb
Host smart-144feea4-b093-4442-99ec-cdb49a8dca70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202950436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3202950436
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1921678939
Short name T1110
Test name
Test status
Simulation time 152053123296 ps
CPU time 32.54 seconds
Started May 23 12:47:18 PM PDT 24
Finished May 23 12:47:52 PM PDT 24
Peak memory 200380 kb
Host smart-94a162f8-0685-4807-adaa-4ce14916d556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921678939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1921678939
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.462909445
Short name T612
Test name
Test status
Simulation time 34885502434 ps
CPU time 62.18 seconds
Started May 23 12:47:19 PM PDT 24
Finished May 23 12:48:22 PM PDT 24
Peak memory 200448 kb
Host smart-6a286cb4-17fb-42e4-8ec9-d10915e894e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462909445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.462909445
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.145339728
Short name T778
Test name
Test status
Simulation time 6446188934 ps
CPU time 18.78 seconds
Started May 23 12:47:21 PM PDT 24
Finished May 23 12:47:41 PM PDT 24
Peak memory 200316 kb
Host smart-e57efd0b-b15a-49ab-bdff-2ddc9c006618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145339728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.145339728
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.4003875239
Short name T840
Test name
Test status
Simulation time 12276162 ps
CPU time 0.54 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:44:27 PM PDT 24
Peak memory 194716 kb
Host smart-116efa6f-9482-4cab-a5cb-869e141f3a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003875239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.4003875239
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2405598933
Short name T1067
Test name
Test status
Simulation time 134542637680 ps
CPU time 135.21 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:46:41 PM PDT 24
Peak memory 200288 kb
Host smart-48d33e37-3125-4b4d-b8f2-bb097b57ab53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405598933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2405598933
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3161538686
Short name T227
Test name
Test status
Simulation time 44024651702 ps
CPU time 62.56 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:45:29 PM PDT 24
Peak memory 200332 kb
Host smart-cf6a0ec6-620b-41b1-a3bd-39d71780f19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161538686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3161538686
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1095624481
Short name T343
Test name
Test status
Simulation time 22446211266 ps
CPU time 34.05 seconds
Started May 23 12:44:22 PM PDT 24
Finished May 23 12:44:57 PM PDT 24
Peak memory 198948 kb
Host smart-a4ff8d1a-001b-45dc-944f-8302a57d6379
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095624481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1095624481
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.28054744
Short name T386
Test name
Test status
Simulation time 74349743992 ps
CPU time 367.48 seconds
Started May 23 12:44:26 PM PDT 24
Finished May 23 12:50:35 PM PDT 24
Peak memory 200464 kb
Host smart-f1c6a277-7099-41bf-b404-c5ec13e0ac0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28054744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.28054744
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.599905775
Short name T980
Test name
Test status
Simulation time 15806330564 ps
CPU time 12.36 seconds
Started May 23 12:44:23 PM PDT 24
Finished May 23 12:44:42 PM PDT 24
Peak memory 199156 kb
Host smart-d144d820-cc94-4343-9532-7e47c1670bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599905775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.599905775
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.125202888
Short name T489
Test name
Test status
Simulation time 106575727136 ps
CPU time 124.27 seconds
Started May 23 12:44:21 PM PDT 24
Finished May 23 12:46:27 PM PDT 24
Peak memory 200480 kb
Host smart-6ff100f7-865a-4c05-901f-cdbefc6062ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125202888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.125202888
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3846639066
Short name T427
Test name
Test status
Simulation time 10040709012 ps
CPU time 455.38 seconds
Started May 23 12:44:22 PM PDT 24
Finished May 23 12:51:59 PM PDT 24
Peak memory 200312 kb
Host smart-57f1a3cc-bb1a-45f7-9eab-4f8503bd1d7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3846639066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3846639066
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2064920535
Short name T382
Test name
Test status
Simulation time 4260999444 ps
CPU time 21.53 seconds
Started May 23 12:44:22 PM PDT 24
Finished May 23 12:44:46 PM PDT 24
Peak memory 199680 kb
Host smart-5ffd0dce-bb68-4478-b16a-74c57f5ab384
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064920535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2064920535
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1439844120
Short name T660
Test name
Test status
Simulation time 21177109608 ps
CPU time 32.31 seconds
Started May 23 12:44:25 PM PDT 24
Finished May 23 12:44:59 PM PDT 24
Peak memory 198736 kb
Host smart-0328e4ef-83cc-4163-ad89-0c1a1458bfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439844120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1439844120
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1973855046
Short name T623
Test name
Test status
Simulation time 4668632040 ps
CPU time 3.04 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:44:29 PM PDT 24
Peak memory 196648 kb
Host smart-189399f7-a8d8-4ce7-9bbd-996502c72bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973855046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1973855046
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3079672861
Short name T574
Test name
Test status
Simulation time 514500965 ps
CPU time 1.68 seconds
Started May 23 12:44:21 PM PDT 24
Finished May 23 12:44:24 PM PDT 24
Peak memory 199904 kb
Host smart-e4ffce65-00b6-45ec-98f5-d53b5cf44935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079672861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3079672861
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1861895388
Short name T1114
Test name
Test status
Simulation time 478129059118 ps
CPU time 442.12 seconds
Started May 23 12:44:23 PM PDT 24
Finished May 23 12:51:48 PM PDT 24
Peak memory 200356 kb
Host smart-45b31779-3afa-4959-a650-1d97f27d91b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861895388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1861895388
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3734692791
Short name T114
Test name
Test status
Simulation time 31732414038 ps
CPU time 211.45 seconds
Started May 23 12:44:23 PM PDT 24
Finished May 23 12:47:56 PM PDT 24
Peak memory 208572 kb
Host smart-d5889519-1c13-41c5-b8dc-09daf169110d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734692791 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3734692791
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.193313228
Short name T822
Test name
Test status
Simulation time 798318476 ps
CPU time 2.47 seconds
Started May 23 12:44:21 PM PDT 24
Finished May 23 12:44:25 PM PDT 24
Peak memory 200296 kb
Host smart-ab45e288-d342-43e3-b3f8-bbf8c652a2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193313228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.193313228
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.4181706251
Short name T898
Test name
Test status
Simulation time 6337022938 ps
CPU time 10.66 seconds
Started May 23 12:44:23 PM PDT 24
Finished May 23 12:44:36 PM PDT 24
Peak memory 199504 kb
Host smart-d6ae7415-2db3-4ca2-91e0-38020929bcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181706251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.4181706251
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3497486759
Short name T547
Test name
Test status
Simulation time 90465740884 ps
CPU time 108.62 seconds
Started May 23 12:47:19 PM PDT 24
Finished May 23 12:49:10 PM PDT 24
Peak memory 200356 kb
Host smart-3c875d61-5408-484d-b0b6-f8a1afd40ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497486759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3497486759
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3983958985
Short name T187
Test name
Test status
Simulation time 69615051103 ps
CPU time 201.96 seconds
Started May 23 12:47:22 PM PDT 24
Finished May 23 12:50:45 PM PDT 24
Peak memory 200400 kb
Host smart-a14f5bcf-1c25-47d8-9027-1c06bc3be2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983958985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3983958985
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3931443960
Short name T710
Test name
Test status
Simulation time 281258573322 ps
CPU time 135.08 seconds
Started May 23 12:47:22 PM PDT 24
Finished May 23 12:49:38 PM PDT 24
Peak memory 200308 kb
Host smart-3f71f354-8723-4ea0-89bc-d8217679f807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931443960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3931443960
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.674575028
Short name T1043
Test name
Test status
Simulation time 34873767762 ps
CPU time 16.45 seconds
Started May 23 12:47:26 PM PDT 24
Finished May 23 12:47:44 PM PDT 24
Peak memory 199992 kb
Host smart-544d3217-bed4-4a1a-aeca-0c325475c7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674575028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.674575028
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2086123901
Short name T66
Test name
Test status
Simulation time 92173189634 ps
CPU time 119.15 seconds
Started May 23 12:47:22 PM PDT 24
Finished May 23 12:49:22 PM PDT 24
Peak memory 200404 kb
Host smart-4dd8519b-f995-490b-ad42-43d303e64bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086123901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2086123901
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1609623599
Short name T395
Test name
Test status
Simulation time 17730569956 ps
CPU time 29.92 seconds
Started May 23 12:47:25 PM PDT 24
Finished May 23 12:47:56 PM PDT 24
Peak memory 200420 kb
Host smart-9d5a8980-de5d-406a-a644-a68714af3be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609623599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1609623599
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2718383170
Short name T1136
Test name
Test status
Simulation time 53709771124 ps
CPU time 30.05 seconds
Started May 23 12:47:23 PM PDT 24
Finished May 23 12:47:54 PM PDT 24
Peak memory 200480 kb
Host smart-e6b6a6b8-d91a-49fe-9f7e-38c2ea1e1449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718383170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2718383170
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3840519566
Short name T391
Test name
Test status
Simulation time 63448828 ps
CPU time 0.55 seconds
Started May 23 12:44:39 PM PDT 24
Finished May 23 12:44:43 PM PDT 24
Peak memory 195856 kb
Host smart-26d6d014-5a21-4c85-a9cc-5ee8a271168b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840519566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3840519566
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.4273551260
Short name T584
Test name
Test status
Simulation time 47303966505 ps
CPU time 21.25 seconds
Started May 23 12:44:25 PM PDT 24
Finished May 23 12:44:48 PM PDT 24
Peak memory 200392 kb
Host smart-f75ac746-0a4d-4df7-9c71-944352769800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273551260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.4273551260
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3640047352
Short name T597
Test name
Test status
Simulation time 28459676630 ps
CPU time 14.49 seconds
Started May 23 12:44:22 PM PDT 24
Finished May 23 12:44:39 PM PDT 24
Peak memory 200364 kb
Host smart-0bcc424b-1665-4931-8de5-15ecd9563561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640047352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3640047352
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1495209498
Short name T216
Test name
Test status
Simulation time 26109078335 ps
CPU time 15.24 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:44:42 PM PDT 24
Peak memory 200172 kb
Host smart-a792be14-0e1e-417a-bc9a-931af738d894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495209498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1495209498
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3642947439
Short name T826
Test name
Test status
Simulation time 46215970392 ps
CPU time 71.53 seconds
Started May 23 12:44:25 PM PDT 24
Finished May 23 12:45:39 PM PDT 24
Peak memory 200376 kb
Host smart-131f1c69-9c7c-4d9d-8ade-a89b4a8d8f60
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642947439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3642947439
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.450825280
Short name T782
Test name
Test status
Simulation time 63223894398 ps
CPU time 322.01 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:49:49 PM PDT 24
Peak memory 200396 kb
Host smart-dc013ec5-3dff-439b-a8ae-9044b82ace33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=450825280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.450825280
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3489019628
Short name T1041
Test name
Test status
Simulation time 7204142106 ps
CPU time 12.54 seconds
Started May 23 12:44:27 PM PDT 24
Finished May 23 12:44:41 PM PDT 24
Peak memory 199684 kb
Host smart-e37a1cae-6706-4aa8-84b5-8a6aa807cda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489019628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3489019628
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3881864087
Short name T277
Test name
Test status
Simulation time 14481238161 ps
CPU time 23.83 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:44:50 PM PDT 24
Peak memory 199264 kb
Host smart-92398145-76ff-4677-83c4-265539f91cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881864087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3881864087
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3672587203
Short name T10
Test name
Test status
Simulation time 28112235644 ps
CPU time 328.98 seconds
Started May 23 12:44:25 PM PDT 24
Finished May 23 12:49:56 PM PDT 24
Peak memory 200456 kb
Host smart-6f5902ff-cacd-4ad6-8eaf-6978ebc328d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672587203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3672587203
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.622998534
Short name T600
Test name
Test status
Simulation time 3048502993 ps
CPU time 5.03 seconds
Started May 23 12:44:20 PM PDT 24
Finished May 23 12:44:27 PM PDT 24
Peak memory 198232 kb
Host smart-88d4656f-bb5e-42d1-868c-0c22b710d88e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=622998534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.622998534
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2244452727
Short name T1107
Test name
Test status
Simulation time 27485633072 ps
CPU time 51.39 seconds
Started May 23 12:44:27 PM PDT 24
Finished May 23 12:45:20 PM PDT 24
Peak memory 200448 kb
Host smart-9b69e815-ce42-4bf5-b51b-8ccb5b048110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244452727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2244452727
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.318901576
Short name T933
Test name
Test status
Simulation time 4105236358 ps
CPU time 3.66 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:44:34 PM PDT 24
Peak memory 196440 kb
Host smart-5e64f8a0-760b-4221-90cc-32f2f02eb61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318901576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.318901576
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.308899860
Short name T507
Test name
Test status
Simulation time 288591193 ps
CPU time 1.27 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:44:28 PM PDT 24
Peak memory 198632 kb
Host smart-eca87065-4e99-4fa8-a1a1-9b325ac138a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308899860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.308899860
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2764226032
Short name T33
Test name
Test status
Simulation time 89741657909 ps
CPU time 702.95 seconds
Started May 23 12:44:28 PM PDT 24
Finished May 23 12:56:12 PM PDT 24
Peak memory 225300 kb
Host smart-66b48245-da28-43e9-a14d-0028e0d8e070
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764226032 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2764226032
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1016951178
Short name T690
Test name
Test status
Simulation time 6814128981 ps
CPU time 14.59 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:44:41 PM PDT 24
Peak memory 200360 kb
Host smart-c79bd578-8e82-4bdb-92c1-ec613badcca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016951178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1016951178
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2737016370
Short name T1020
Test name
Test status
Simulation time 114620808263 ps
CPU time 46.51 seconds
Started May 23 12:44:24 PM PDT 24
Finished May 23 12:45:12 PM PDT 24
Peak memory 200468 kb
Host smart-79066409-5178-4376-a475-5d56cd264e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737016370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2737016370
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.459234771
Short name T532
Test name
Test status
Simulation time 27091640217 ps
CPU time 8.43 seconds
Started May 23 12:47:23 PM PDT 24
Finished May 23 12:47:32 PM PDT 24
Peak memory 200360 kb
Host smart-15fc4610-5183-46c0-9a1c-809fa71b1787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459234771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.459234771
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1355928779
Short name T808
Test name
Test status
Simulation time 74529474279 ps
CPU time 57.11 seconds
Started May 23 12:47:22 PM PDT 24
Finished May 23 12:48:21 PM PDT 24
Peak memory 200212 kb
Host smart-cbf0efd9-7058-4ec1-bc90-507e0a6af65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355928779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1355928779
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.262772139
Short name T1079
Test name
Test status
Simulation time 139717235008 ps
CPU time 252.06 seconds
Started May 23 12:47:25 PM PDT 24
Finished May 23 12:51:38 PM PDT 24
Peak memory 200364 kb
Host smart-61e193ba-4cf8-4fc7-a0b0-281510ec4dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262772139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.262772139
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2908497421
Short name T470
Test name
Test status
Simulation time 35040944306 ps
CPU time 70.44 seconds
Started May 23 12:47:25 PM PDT 24
Finished May 23 12:48:37 PM PDT 24
Peak memory 200344 kb
Host smart-dfb5cdc3-fe07-4b44-92dc-153701ff2209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908497421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2908497421
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.826844148
Short name T15
Test name
Test status
Simulation time 38376982108 ps
CPU time 17.52 seconds
Started May 23 12:47:23 PM PDT 24
Finished May 23 12:47:42 PM PDT 24
Peak memory 200436 kb
Host smart-c4b68b1c-d59f-4e93-93b0-1b657c6e8f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826844148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.826844148
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2069823340
Short name T1124
Test name
Test status
Simulation time 13574916652 ps
CPU time 15.28 seconds
Started May 23 12:47:26 PM PDT 24
Finished May 23 12:47:43 PM PDT 24
Peak memory 200292 kb
Host smart-0cb9b0f8-0588-4aaa-bbcc-c083d767268c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069823340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2069823340
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3045880572
Short name T1149
Test name
Test status
Simulation time 46112352985 ps
CPU time 66.75 seconds
Started May 23 12:47:31 PM PDT 24
Finished May 23 12:48:39 PM PDT 24
Peak memory 200344 kb
Host smart-c1298db3-7cd6-4bb4-af46-f81af0f78bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045880572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3045880572
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.129359068
Short name T586
Test name
Test status
Simulation time 32408001 ps
CPU time 0.53 seconds
Started May 23 12:44:22 PM PDT 24
Finished May 23 12:44:24 PM PDT 24
Peak memory 195736 kb
Host smart-ddd50e3a-bcc9-446f-b770-da561a124bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129359068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.129359068
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2052661463
Short name T447
Test name
Test status
Simulation time 53766912394 ps
CPU time 57.85 seconds
Started May 23 12:44:38 PM PDT 24
Finished May 23 12:45:39 PM PDT 24
Peak memory 200440 kb
Host smart-8199a19c-3fcd-49f0-8ff0-f76ca16ddb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052661463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2052661463
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3105697579
Short name T897
Test name
Test status
Simulation time 77782622273 ps
CPU time 35.98 seconds
Started May 23 12:44:27 PM PDT 24
Finished May 23 12:45:04 PM PDT 24
Peak memory 200288 kb
Host smart-ebbc2b1d-328b-4bcb-bad3-7d44efc87f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105697579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3105697579
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2498120158
Short name T566
Test name
Test status
Simulation time 23210566451 ps
CPU time 29.54 seconds
Started May 23 12:44:27 PM PDT 24
Finished May 23 12:44:58 PM PDT 24
Peak memory 200364 kb
Host smart-5d3c712f-dca3-492e-af21-ee1687b7e553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498120158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2498120158
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1816502586
Short name T120
Test name
Test status
Simulation time 40915126896 ps
CPU time 68.79 seconds
Started May 23 12:44:27 PM PDT 24
Finished May 23 12:45:37 PM PDT 24
Peak memory 200328 kb
Host smart-1ad5e43d-0e3b-458f-9248-f86baa361f2d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816502586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1816502586
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.251086386
Short name T272
Test name
Test status
Simulation time 70940173820 ps
CPU time 99.37 seconds
Started May 23 12:44:37 PM PDT 24
Finished May 23 12:46:21 PM PDT 24
Peak memory 200448 kb
Host smart-8d93da7b-edf6-450f-83c4-e4caf58b381b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=251086386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.251086386
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.920797385
Short name T396
Test name
Test status
Simulation time 2487846428 ps
CPU time 3.59 seconds
Started May 23 12:44:37 PM PDT 24
Finished May 23 12:44:44 PM PDT 24
Peak memory 198356 kb
Host smart-e8c6bec3-a483-48c1-987a-c8168f988f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920797385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.920797385
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2502243765
Short name T820
Test name
Test status
Simulation time 77645724612 ps
CPU time 143.28 seconds
Started May 23 12:44:38 PM PDT 24
Finished May 23 12:47:05 PM PDT 24
Peak memory 199792 kb
Host smart-b69ca625-4880-4054-bcb1-af78a0dae7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502243765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2502243765
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1808316263
Short name T509
Test name
Test status
Simulation time 10838545107 ps
CPU time 131.42 seconds
Started May 23 12:44:23 PM PDT 24
Finished May 23 12:46:36 PM PDT 24
Peak memory 200308 kb
Host smart-327762c2-88ba-4b35-a329-776cdc8f01e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1808316263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1808316263
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1534557859
Short name T467
Test name
Test status
Simulation time 4023685294 ps
CPU time 12.18 seconds
Started May 23 12:44:27 PM PDT 24
Finished May 23 12:44:40 PM PDT 24
Peak memory 198508 kb
Host smart-05d7cb2b-df3f-4775-a825-37f22bf0be42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1534557859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1534557859
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.415023194
Short name T934
Test name
Test status
Simulation time 188771182853 ps
CPU time 37.65 seconds
Started May 23 12:44:39 PM PDT 24
Finished May 23 12:45:20 PM PDT 24
Peak memory 200292 kb
Host smart-e611b487-30b6-4982-86b2-df74c4e41ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415023194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.415023194
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2427063159
Short name T437
Test name
Test status
Simulation time 35022877888 ps
CPU time 55.86 seconds
Started May 23 12:44:43 PM PDT 24
Finished May 23 12:45:41 PM PDT 24
Peak memory 196220 kb
Host smart-56bf8398-1455-4dc3-8451-b16a3bd32a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427063159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2427063159
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3548442171
Short name T868
Test name
Test status
Simulation time 468632232 ps
CPU time 2.11 seconds
Started May 23 12:44:38 PM PDT 24
Finished May 23 12:44:44 PM PDT 24
Peak memory 199348 kb
Host smart-aa24442a-a245-4158-953e-c0ca9e6a92fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548442171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3548442171
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2173438669
Short name T1179
Test name
Test status
Simulation time 259192095434 ps
CPU time 627.48 seconds
Started May 23 12:44:21 PM PDT 24
Finished May 23 12:54:50 PM PDT 24
Peak memory 208908 kb
Host smart-b9cd71f7-dc85-45dc-bd8d-59e713d468be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173438669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2173438669
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.4168397246
Short name T960
Test name
Test status
Simulation time 79182265556 ps
CPU time 887.4 seconds
Started May 23 12:44:23 PM PDT 24
Finished May 23 12:59:13 PM PDT 24
Peak memory 215056 kb
Host smart-2c397a4e-c1f1-41da-b25e-81486c931add
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168397246 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.4168397246
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2777950991
Short name T688
Test name
Test status
Simulation time 1184360506 ps
CPU time 2.6 seconds
Started May 23 12:44:23 PM PDT 24
Finished May 23 12:44:27 PM PDT 24
Peak memory 199848 kb
Host smart-6b8a137c-eb15-4fa4-8dba-914385491f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777950991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2777950991
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3542841689
Short name T1088
Test name
Test status
Simulation time 79642380131 ps
CPU time 228.82 seconds
Started May 23 12:44:38 PM PDT 24
Finished May 23 12:48:31 PM PDT 24
Peak memory 200424 kb
Host smart-c4fc1933-a7ed-4e48-b9d3-aa48f9b56458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542841689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3542841689
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3739197068
Short name T608
Test name
Test status
Simulation time 29203868879 ps
CPU time 49.98 seconds
Started May 23 12:47:24 PM PDT 24
Finished May 23 12:48:15 PM PDT 24
Peak memory 200324 kb
Host smart-a0e607cc-93e9-4060-bc51-f02b9e450221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739197068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3739197068
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2273237334
Short name T214
Test name
Test status
Simulation time 68821746502 ps
CPU time 126.55 seconds
Started May 23 12:47:26 PM PDT 24
Finished May 23 12:49:34 PM PDT 24
Peak memory 200288 kb
Host smart-80361b23-c718-4a9e-b7e1-932cdbf00b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273237334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2273237334
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1407987017
Short name T442
Test name
Test status
Simulation time 94619656794 ps
CPU time 155.02 seconds
Started May 23 12:47:24 PM PDT 24
Finished May 23 12:50:00 PM PDT 24
Peak memory 200424 kb
Host smart-17796098-dae5-4675-8a17-817d9fbc7028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407987017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1407987017
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2123072246
Short name T819
Test name
Test status
Simulation time 107782260375 ps
CPU time 114.41 seconds
Started May 23 12:47:24 PM PDT 24
Finished May 23 12:49:20 PM PDT 24
Peak memory 200444 kb
Host smart-4ff70547-fd6c-466d-8c2e-b499b672f932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123072246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2123072246
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.755044080
Short name T340
Test name
Test status
Simulation time 31101319753 ps
CPU time 35.64 seconds
Started May 23 12:47:25 PM PDT 24
Finished May 23 12:48:02 PM PDT 24
Peak memory 200464 kb
Host smart-7fd4a6ad-4aed-4121-a5e7-9ca05276ebf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755044080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.755044080
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1578128551
Short name T178
Test name
Test status
Simulation time 139564460548 ps
CPU time 201.62 seconds
Started May 23 12:47:26 PM PDT 24
Finished May 23 12:50:49 PM PDT 24
Peak memory 200228 kb
Host smart-3f68f294-4158-4be2-8256-b0a81e7671b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578128551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1578128551
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3527933048
Short name T1039
Test name
Test status
Simulation time 18780953109 ps
CPU time 30.74 seconds
Started May 23 12:47:27 PM PDT 24
Finished May 23 12:47:59 PM PDT 24
Peak memory 200336 kb
Host smart-e9f9e22f-929c-4cd4-9547-3fc6f80bb280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527933048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3527933048
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1000442134
Short name T303
Test name
Test status
Simulation time 136252000300 ps
CPU time 226.52 seconds
Started May 23 12:47:26 PM PDT 24
Finished May 23 12:51:13 PM PDT 24
Peak memory 200404 kb
Host smart-8ce94695-6f7b-45f6-b75c-291cae4eadb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000442134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1000442134
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1114777103
Short name T418
Test name
Test status
Simulation time 15435250050 ps
CPU time 22.65 seconds
Started May 23 12:47:25 PM PDT 24
Finished May 23 12:47:49 PM PDT 24
Peak memory 200480 kb
Host smart-79daea21-345d-4719-9d10-ecf25f23b53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114777103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1114777103
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3624692032
Short name T771
Test name
Test status
Simulation time 37705150857 ps
CPU time 24.38 seconds
Started May 23 12:47:27 PM PDT 24
Finished May 23 12:47:53 PM PDT 24
Peak memory 200376 kb
Host smart-7b1a81b3-cc32-4a9e-af7a-5d59d83afd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624692032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3624692032
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1224269365
Short name T384
Test name
Test status
Simulation time 12955585 ps
CPU time 0.55 seconds
Started May 23 12:44:44 PM PDT 24
Finished May 23 12:44:46 PM PDT 24
Peak memory 195776 kb
Host smart-b842d067-4d0d-4d0b-9325-6adadd731abb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224269365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1224269365
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3330317694
Short name T1182
Test name
Test status
Simulation time 102853146278 ps
CPU time 29.43 seconds
Started May 23 12:44:23 PM PDT 24
Finished May 23 12:44:54 PM PDT 24
Peak memory 200300 kb
Host smart-d310e9bb-102d-4c50-84d7-57577ce1cce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330317694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3330317694
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2967687104
Short name T148
Test name
Test status
Simulation time 36345905809 ps
CPU time 22.08 seconds
Started May 23 12:44:25 PM PDT 24
Finished May 23 12:44:49 PM PDT 24
Peak memory 200044 kb
Host smart-5c48b265-c653-4771-a53f-07afe87e2703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967687104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2967687104
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_intr.689713754
Short name T23
Test name
Test status
Simulation time 318294670996 ps
CPU time 162.64 seconds
Started May 23 12:44:35 PM PDT 24
Finished May 23 12:47:20 PM PDT 24
Peak memory 200168 kb
Host smart-09fb4676-7869-41fd-8224-d74fa391aa85
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689713754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.689713754
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.4156921217
Short name T598
Test name
Test status
Simulation time 132117106069 ps
CPU time 788.84 seconds
Started May 23 12:44:39 PM PDT 24
Finished May 23 12:57:52 PM PDT 24
Peak memory 200096 kb
Host smart-93a51579-8c08-4578-9384-94a0c32b4bf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4156921217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.4156921217
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.928481421
Short name T434
Test name
Test status
Simulation time 4013364464 ps
CPU time 7.01 seconds
Started May 23 12:44:40 PM PDT 24
Finished May 23 12:44:50 PM PDT 24
Peak memory 197868 kb
Host smart-f45fe674-cad8-49e3-bff8-2deda718070a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928481421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.928481421
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3508129100
Short name T915
Test name
Test status
Simulation time 13033995025 ps
CPU time 11.86 seconds
Started May 23 12:44:50 PM PDT 24
Finished May 23 12:45:03 PM PDT 24
Peak memory 200408 kb
Host smart-47024780-62ba-4e6b-ac85-101e7a5a7844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508129100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3508129100
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.863688997
Short name T583
Test name
Test status
Simulation time 15083169066 ps
CPU time 652.45 seconds
Started May 23 12:44:39 PM PDT 24
Finished May 23 12:55:35 PM PDT 24
Peak memory 200380 kb
Host smart-8baeeedd-aaf4-4477-adb0-2eeb6ead7dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=863688997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.863688997
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3863809918
Short name T358
Test name
Test status
Simulation time 6974304995 ps
CPU time 63.84 seconds
Started May 23 12:44:33 PM PDT 24
Finished May 23 12:45:38 PM PDT 24
Peak memory 199216 kb
Host smart-4df498dc-b576-4326-8cbd-3fc2993aca9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3863809918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3863809918
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1338389183
Short name T834
Test name
Test status
Simulation time 12554409128 ps
CPU time 21.72 seconds
Started May 23 12:44:36 PM PDT 24
Finished May 23 12:45:01 PM PDT 24
Peak memory 200476 kb
Host smart-56317f0c-c0e6-4eba-8050-80f99b6348bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338389183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1338389183
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.4028856853
Short name T397
Test name
Test status
Simulation time 6616246298 ps
CPU time 5.86 seconds
Started May 23 12:44:46 PM PDT 24
Finished May 23 12:44:53 PM PDT 24
Peak memory 196440 kb
Host smart-ad7064ef-7308-4cf2-a0f9-c4fdd0bd564c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028856853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4028856853
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1164461674
Short name T633
Test name
Test status
Simulation time 5681867182 ps
CPU time 25.18 seconds
Started May 23 12:44:27 PM PDT 24
Finished May 23 12:44:54 PM PDT 24
Peak memory 200304 kb
Host smart-3f140602-d15e-4d07-8993-c55bb8350452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164461674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1164461674
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1467958307
Short name T115
Test name
Test status
Simulation time 99954023209 ps
CPU time 52.87 seconds
Started May 23 12:44:30 PM PDT 24
Finished May 23 12:45:24 PM PDT 24
Peak memory 200636 kb
Host smart-7fd188b7-32b9-4719-bf6d-158cad744ff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467958307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1467958307
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2327509287
Short name T31
Test name
Test status
Simulation time 47504499085 ps
CPU time 600.93 seconds
Started May 23 12:44:36 PM PDT 24
Finished May 23 12:54:40 PM PDT 24
Peak memory 216536 kb
Host smart-8ce9f074-ffb2-4712-a3cf-a79e0c37b771
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327509287 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2327509287
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.838714481
Short name T867
Test name
Test status
Simulation time 12943589248 ps
CPU time 29.69 seconds
Started May 23 12:44:46 PM PDT 24
Finished May 23 12:45:17 PM PDT 24
Peak memory 200212 kb
Host smart-f738f1fa-c41e-4646-b136-7a9944b69221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838714481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.838714481
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2103907487
Short name T642
Test name
Test status
Simulation time 43683895526 ps
CPU time 18.95 seconds
Started May 23 12:44:23 PM PDT 24
Finished May 23 12:44:45 PM PDT 24
Peak memory 200344 kb
Host smart-b8290de0-a190-4dbf-9db3-ca344787bc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103907487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2103907487
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.790595480
Short name T772
Test name
Test status
Simulation time 114505681064 ps
CPU time 214.83 seconds
Started May 23 12:47:27 PM PDT 24
Finished May 23 12:51:03 PM PDT 24
Peak memory 200456 kb
Host smart-d943c329-87ea-494a-ab34-bbed4440e9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790595480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.790595480
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3615739619
Short name T7
Test name
Test status
Simulation time 54259515967 ps
CPU time 157.42 seconds
Started May 23 12:47:25 PM PDT 24
Finished May 23 12:50:04 PM PDT 24
Peak memory 200448 kb
Host smart-8f3baadf-236f-4ddd-a95c-cef6ffa130f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615739619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3615739619
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1794354090
Short name T694
Test name
Test status
Simulation time 121864684660 ps
CPU time 188.31 seconds
Started May 23 12:47:30 PM PDT 24
Finished May 23 12:50:40 PM PDT 24
Peak memory 200308 kb
Host smart-2c40ac66-fa61-4a6d-b581-0954be04c1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794354090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1794354090
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1361763922
Short name T668
Test name
Test status
Simulation time 21293660074 ps
CPU time 10.4 seconds
Started May 23 12:47:40 PM PDT 24
Finished May 23 12:47:53 PM PDT 24
Peak memory 200164 kb
Host smart-f8dc2c2f-9422-4581-b5dc-c8462f534214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361763922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1361763922
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1148780794
Short name T152
Test name
Test status
Simulation time 22694702450 ps
CPU time 31.13 seconds
Started May 23 12:47:34 PM PDT 24
Finished May 23 12:48:08 PM PDT 24
Peak memory 200396 kb
Host smart-7dd0ee8b-0840-4280-8fd8-5036c989a976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148780794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1148780794
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.864450341
Short name T188
Test name
Test status
Simulation time 93281380889 ps
CPU time 294.24 seconds
Started May 23 12:47:37 PM PDT 24
Finished May 23 12:52:34 PM PDT 24
Peak memory 200492 kb
Host smart-86209ef5-c847-4511-9d57-6848672d960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864450341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.864450341
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3717250605
Short name T230
Test name
Test status
Simulation time 22813216017 ps
CPU time 57.04 seconds
Started May 23 12:47:32 PM PDT 24
Finished May 23 12:48:31 PM PDT 24
Peak memory 200428 kb
Host smart-7bd82a5f-170a-4f6f-b022-dbdd5adcb860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717250605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3717250605
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3938227566
Short name T322
Test name
Test status
Simulation time 28482785695 ps
CPU time 42.11 seconds
Started May 23 12:47:30 PM PDT 24
Finished May 23 12:48:14 PM PDT 24
Peak memory 200396 kb
Host smart-1b9918fc-6c86-4454-a772-bd53f10998e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938227566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3938227566
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1453637288
Short name T1155
Test name
Test status
Simulation time 40926072 ps
CPU time 0.62 seconds
Started May 23 12:44:37 PM PDT 24
Finished May 23 12:44:42 PM PDT 24
Peak memory 195760 kb
Host smart-2b696347-01cf-4009-b360-d7d954b0b412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453637288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1453637288
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2561252801
Short name T429
Test name
Test status
Simulation time 8544863667 ps
CPU time 11.19 seconds
Started May 23 12:44:42 PM PDT 24
Finished May 23 12:44:55 PM PDT 24
Peak memory 199796 kb
Host smart-e0ae514f-d637-4340-ad74-927a1ed51625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561252801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2561252801
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1047426461
Short name T663
Test name
Test status
Simulation time 75250012148 ps
CPU time 133.15 seconds
Started May 23 12:44:48 PM PDT 24
Finished May 23 12:47:02 PM PDT 24
Peak memory 200384 kb
Host smart-2a8c8329-3a13-4d0f-998e-0d9b8a5ce2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047426461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1047426461
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3790174852
Short name T573
Test name
Test status
Simulation time 63094546127 ps
CPU time 88.12 seconds
Started May 23 12:44:37 PM PDT 24
Finished May 23 12:46:09 PM PDT 24
Peak memory 200292 kb
Host smart-4f2dc480-df65-4712-8be7-1010bc09b8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790174852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3790174852
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.4158728284
Short name T1072
Test name
Test status
Simulation time 9177371803 ps
CPU time 3.93 seconds
Started May 23 12:44:36 PM PDT 24
Finished May 23 12:44:42 PM PDT 24
Peak memory 198132 kb
Host smart-15a0c4c2-f4b9-44d8-a726-6f59ad602c6a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158728284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.4158728284
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2727037709
Short name T920
Test name
Test status
Simulation time 88097934667 ps
CPU time 159.1 seconds
Started May 23 12:44:37 PM PDT 24
Finished May 23 12:47:20 PM PDT 24
Peak memory 200436 kb
Host smart-d9e9e80f-0d08-4d66-9bf0-e65b1123f1d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727037709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2727037709
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2675824049
Short name T1038
Test name
Test status
Simulation time 363795104 ps
CPU time 1.5 seconds
Started May 23 12:44:37 PM PDT 24
Finished May 23 12:44:42 PM PDT 24
Peak memory 200052 kb
Host smart-ed1090ba-06c6-4459-9263-4ec74b4343c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675824049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2675824049
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.468156779
Short name T595
Test name
Test status
Simulation time 154473008895 ps
CPU time 164.15 seconds
Started May 23 12:44:34 PM PDT 24
Finished May 23 12:47:20 PM PDT 24
Peak memory 200632 kb
Host smart-31f17000-d9ab-49a9-897c-47608aa92f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468156779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.468156779
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2630182041
Short name T403
Test name
Test status
Simulation time 23474098376 ps
CPU time 1365.46 seconds
Started May 23 12:44:35 PM PDT 24
Finished May 23 01:07:23 PM PDT 24
Peak memory 200376 kb
Host smart-cf1cd3a2-7209-456d-aa76-784b017a9758
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630182041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2630182041
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3769817902
Short name T800
Test name
Test status
Simulation time 6491398695 ps
CPU time 18 seconds
Started May 23 12:44:44 PM PDT 24
Finished May 23 12:45:04 PM PDT 24
Peak memory 199796 kb
Host smart-16bdf8dd-3b7f-4838-9bfc-98a2daaedff0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769817902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3769817902
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1406029745
Short name T18
Test name
Test status
Simulation time 236347910128 ps
CPU time 416.68 seconds
Started May 23 12:44:31 PM PDT 24
Finished May 23 12:51:28 PM PDT 24
Peak memory 200444 kb
Host smart-9db39908-cd47-469a-87b2-0fa8a0273a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406029745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1406029745
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.179597287
Short name T627
Test name
Test status
Simulation time 5757740955 ps
CPU time 10.21 seconds
Started May 23 12:44:33 PM PDT 24
Finished May 23 12:44:44 PM PDT 24
Peak memory 196408 kb
Host smart-79ac2888-28dc-47d4-b70a-5e6331e2d96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179597287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.179597287
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.390894934
Short name T102
Test name
Test status
Simulation time 5728461712 ps
CPU time 17.06 seconds
Started May 23 12:44:34 PM PDT 24
Finished May 23 12:44:54 PM PDT 24
Peak memory 200028 kb
Host smart-12570593-b547-4dc9-a994-fcc97e124bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390894934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.390894934
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.2594462584
Short name T910
Test name
Test status
Simulation time 275648172599 ps
CPU time 126.47 seconds
Started May 23 12:44:37 PM PDT 24
Finished May 23 12:46:46 PM PDT 24
Peak memory 209120 kb
Host smart-c7eaaf85-1138-4e6c-8240-2ff6a9b9565f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594462584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2594462584
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3722555666
Short name T469
Test name
Test status
Simulation time 930292950 ps
CPU time 1.95 seconds
Started May 23 12:44:45 PM PDT 24
Finished May 23 12:44:48 PM PDT 24
Peak memory 199224 kb
Host smart-a654d696-3d4a-4d68-915b-588e06f5be14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722555666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3722555666
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3232240165
Short name T296
Test name
Test status
Simulation time 87042001624 ps
CPU time 43.3 seconds
Started May 23 12:44:35 PM PDT 24
Finished May 23 12:45:21 PM PDT 24
Peak memory 200376 kb
Host smart-742dd909-c917-40bf-9339-4ff572eaf591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232240165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3232240165
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2711643993
Short name T1071
Test name
Test status
Simulation time 98917486714 ps
CPU time 104.73 seconds
Started May 23 12:47:34 PM PDT 24
Finished May 23 12:49:21 PM PDT 24
Peak memory 200480 kb
Host smart-756ff00b-3da8-4bc9-8279-81a0a87eda67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711643993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2711643993
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.798604677
Short name T544
Test name
Test status
Simulation time 121597264634 ps
CPU time 214.03 seconds
Started May 23 12:47:36 PM PDT 24
Finished May 23 12:51:13 PM PDT 24
Peak memory 200260 kb
Host smart-ffaf6f1e-83c9-4d37-b08b-a8a1910b15e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798604677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.798604677
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3871677086
Short name T852
Test name
Test status
Simulation time 105051341926 ps
CPU time 37.99 seconds
Started May 23 12:47:34 PM PDT 24
Finished May 23 12:48:15 PM PDT 24
Peak memory 200400 kb
Host smart-a93b1100-a78b-405f-9a7a-baf982c615c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871677086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3871677086
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3403095131
Short name T1156
Test name
Test status
Simulation time 9535842783 ps
CPU time 17.27 seconds
Started May 23 12:47:33 PM PDT 24
Finished May 23 12:47:53 PM PDT 24
Peak memory 200332 kb
Host smart-9e35fcca-3ddb-4bd0-848d-3d043a1dce9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403095131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3403095131
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3897962342
Short name T1057
Test name
Test status
Simulation time 64121181671 ps
CPU time 27.44 seconds
Started May 23 12:47:36 PM PDT 24
Finished May 23 12:48:06 PM PDT 24
Peak memory 200204 kb
Host smart-7f5b6218-7a9f-4c5e-ae71-aaf007f151d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897962342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3897962342
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2633982313
Short name T592
Test name
Test status
Simulation time 44114322851 ps
CPU time 29.37 seconds
Started May 23 12:47:35 PM PDT 24
Finished May 23 12:48:07 PM PDT 24
Peak memory 200372 kb
Host smart-1bdf9826-f128-40de-b647-cd3f8236b65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633982313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2633982313
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.690737673
Short name T722
Test name
Test status
Simulation time 44463982914 ps
CPU time 74.45 seconds
Started May 23 12:47:38 PM PDT 24
Finished May 23 12:48:55 PM PDT 24
Peak memory 200432 kb
Host smart-786fc599-9fc3-4ce9-af87-d35dfc1e077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690737673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.690737673
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2686100066
Short name T233
Test name
Test status
Simulation time 9450826296 ps
CPU time 16.04 seconds
Started May 23 12:47:38 PM PDT 24
Finished May 23 12:47:56 PM PDT 24
Peak memory 200472 kb
Host smart-e8ee9777-5eb5-4d04-b451-de6995e6165c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686100066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2686100066
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1743141015
Short name T872
Test name
Test status
Simulation time 66450484043 ps
CPU time 329.92 seconds
Started May 23 12:47:32 PM PDT 24
Finished May 23 12:53:04 PM PDT 24
Peak memory 200324 kb
Host smart-2a6570e6-3cf1-4dd7-9467-d274fb667613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743141015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1743141015
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2925516503
Short name T1022
Test name
Test status
Simulation time 16278501 ps
CPU time 0.55 seconds
Started May 23 12:44:37 PM PDT 24
Finished May 23 12:44:41 PM PDT 24
Peak memory 195728 kb
Host smart-e200cdd3-f064-4784-a1fe-c2df0d73d715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925516503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2925516503
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1447952406
Short name T741
Test name
Test status
Simulation time 29391199137 ps
CPU time 26.34 seconds
Started May 23 12:44:45 PM PDT 24
Finished May 23 12:45:13 PM PDT 24
Peak memory 200360 kb
Host smart-7dc54134-7019-4641-b251-a26cdac62c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447952406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1447952406
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2839260332
Short name T198
Test name
Test status
Simulation time 8234892984 ps
CPU time 15.15 seconds
Started May 23 12:44:37 PM PDT 24
Finished May 23 12:44:56 PM PDT 24
Peak memory 200188 kb
Host smart-bb376e6e-1e33-4491-a364-af644c878e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839260332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2839260332
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2792121404
Short name T459
Test name
Test status
Simulation time 54759477557 ps
CPU time 47.38 seconds
Started May 23 12:44:35 PM PDT 24
Finished May 23 12:45:24 PM PDT 24
Peak memory 200404 kb
Host smart-39c68663-d3bd-4a32-acd0-ddbb6aa0807e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792121404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2792121404
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1446045187
Short name T707
Test name
Test status
Simulation time 389154744890 ps
CPU time 179.91 seconds
Started May 23 12:44:41 PM PDT 24
Finished May 23 12:47:44 PM PDT 24
Peak memory 200300 kb
Host smart-8115176a-7b43-4cf3-93f9-4924389d6cfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446045187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1446045187
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.847577221
Short name T356
Test name
Test status
Simulation time 616400349 ps
CPU time 1.15 seconds
Started May 23 12:44:44 PM PDT 24
Finished May 23 12:44:47 PM PDT 24
Peak memory 197704 kb
Host smart-5f83972d-6288-484d-aa60-92d0866bbce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847577221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.847577221
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1841093076
Short name T601
Test name
Test status
Simulation time 43898081085 ps
CPU time 21.73 seconds
Started May 23 12:44:44 PM PDT 24
Finished May 23 12:45:07 PM PDT 24
Peak memory 200484 kb
Host smart-f015c192-6119-42eb-ade3-0b682d0f6ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841093076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1841093076
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1578970051
Short name T567
Test name
Test status
Simulation time 23781294377 ps
CPU time 323.19 seconds
Started May 23 12:44:28 PM PDT 24
Finished May 23 12:49:53 PM PDT 24
Peak memory 200384 kb
Host smart-51a6453c-9b40-4023-a449-93d650d0aa88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1578970051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1578970051
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1425439074
Short name T618
Test name
Test status
Simulation time 6280749452 ps
CPU time 10.29 seconds
Started May 23 12:44:33 PM PDT 24
Finished May 23 12:44:45 PM PDT 24
Peak memory 199540 kb
Host smart-be5febe5-782b-4a47-88c5-7aec07e6bc62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1425439074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1425439074
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.609354193
Short name T522
Test name
Test status
Simulation time 90002417154 ps
CPU time 146.37 seconds
Started May 23 12:44:37 PM PDT 24
Finished May 23 12:47:08 PM PDT 24
Peak memory 200280 kb
Host smart-52c15b05-1df3-40e1-b131-1aa285f00d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609354193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.609354193
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1427024412
Short name T563
Test name
Test status
Simulation time 2586188882 ps
CPU time 1.41 seconds
Started May 23 12:44:37 PM PDT 24
Finished May 23 12:44:41 PM PDT 24
Peak memory 196176 kb
Host smart-297efcbb-8346-458d-a77e-cb53ba4e0c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427024412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1427024412
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2940718595
Short name T957
Test name
Test status
Simulation time 859643541 ps
CPU time 1.02 seconds
Started May 23 12:44:37 PM PDT 24
Finished May 23 12:44:42 PM PDT 24
Peak memory 198824 kb
Host smart-60d7e160-962d-495c-9662-e8e513689b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940718595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2940718595
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.602793846
Short name T1008
Test name
Test status
Simulation time 147908670932 ps
CPU time 282.64 seconds
Started May 23 12:44:50 PM PDT 24
Finished May 23 12:49:34 PM PDT 24
Peak memory 200372 kb
Host smart-668fe1af-e187-4695-98e4-c9f9f8bf0690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602793846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.602793846
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2656937624
Short name T280
Test name
Test status
Simulation time 191096044673 ps
CPU time 498.22 seconds
Started May 23 12:44:34 PM PDT 24
Finished May 23 12:52:55 PM PDT 24
Peak memory 217184 kb
Host smart-d3d33d8e-7e5c-4eaa-b824-897d373d28ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656937624 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2656937624
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2440524683
Short name T1
Test name
Test status
Simulation time 584039589 ps
CPU time 2.15 seconds
Started May 23 12:44:34 PM PDT 24
Finished May 23 12:44:38 PM PDT 24
Peak memory 200360 kb
Host smart-43bd0369-b01c-465a-adcb-45582f5897aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440524683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2440524683
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1965971867
Short name T821
Test name
Test status
Simulation time 35102715610 ps
CPU time 53.34 seconds
Started May 23 12:44:34 PM PDT 24
Finished May 23 12:45:30 PM PDT 24
Peak memory 200400 kb
Host smart-509992c1-6e6d-46df-856d-eebebefe069d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965971867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1965971867
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1120668217
Short name T332
Test name
Test status
Simulation time 146100879838 ps
CPU time 99.29 seconds
Started May 23 12:47:38 PM PDT 24
Finished May 23 12:49:19 PM PDT 24
Peak memory 200412 kb
Host smart-f0cb5cd2-3b76-4440-9012-835fb06e8020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120668217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1120668217
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3750617855
Short name T911
Test name
Test status
Simulation time 123464045146 ps
CPU time 221.8 seconds
Started May 23 12:47:32 PM PDT 24
Finished May 23 12:51:16 PM PDT 24
Peak memory 200340 kb
Host smart-99adb59c-062b-479f-b4ab-65c1c9750f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750617855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3750617855
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3320341887
Short name T246
Test name
Test status
Simulation time 77999379357 ps
CPU time 20.72 seconds
Started May 23 12:47:36 PM PDT 24
Finished May 23 12:48:00 PM PDT 24
Peak memory 200324 kb
Host smart-3ca92bef-c90c-404a-b830-f9767c32cf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320341887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3320341887
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1573982026
Short name T250
Test name
Test status
Simulation time 111723326725 ps
CPU time 32.89 seconds
Started May 23 12:47:35 PM PDT 24
Finished May 23 12:48:11 PM PDT 24
Peak memory 200376 kb
Host smart-e75100cc-2fe7-487e-b23b-212bd6fd5e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573982026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1573982026
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3722011835
Short name T482
Test name
Test status
Simulation time 43408259399 ps
CPU time 67.49 seconds
Started May 23 12:47:40 PM PDT 24
Finished May 23 12:48:50 PM PDT 24
Peak memory 200408 kb
Host smart-1aa1ece4-57dc-4223-a513-2a3fc7146f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722011835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3722011835
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3332277378
Short name T677
Test name
Test status
Simulation time 14344760147 ps
CPU time 28.21 seconds
Started May 23 12:47:34 PM PDT 24
Finished May 23 12:48:05 PM PDT 24
Peak memory 200392 kb
Host smart-78b21176-486d-4c4e-93b1-7578744e447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332277378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3332277378
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1533392611
Short name T973
Test name
Test status
Simulation time 45420969183 ps
CPU time 12.41 seconds
Started May 23 12:47:35 PM PDT 24
Finished May 23 12:47:50 PM PDT 24
Peak memory 200348 kb
Host smart-dda56835-224e-48b8-83e9-f227fdae07db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533392611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1533392611
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3058965088
Short name T255
Test name
Test status
Simulation time 140235009015 ps
CPU time 57.22 seconds
Started May 23 12:47:36 PM PDT 24
Finished May 23 12:48:36 PM PDT 24
Peak memory 200352 kb
Host smart-01e6b428-be60-43fe-a53d-7fb17b380dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058965088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3058965088
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.649196613
Short name T875
Test name
Test status
Simulation time 14089458471 ps
CPU time 28.28 seconds
Started May 23 12:47:32 PM PDT 24
Finished May 23 12:48:02 PM PDT 24
Peak memory 200364 kb
Host smart-bf4e040c-4055-436e-a0f8-4ca4ce7ef43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649196613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.649196613
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3632064757
Short name T937
Test name
Test status
Simulation time 15076705 ps
CPU time 0.63 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 12:44:00 PM PDT 24
Peak memory 195820 kb
Host smart-19d00578-b4e0-4d5c-96c6-4355ab53e2b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632064757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3632064757
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2892258482
Short name T551
Test name
Test status
Simulation time 130679350515 ps
CPU time 357.62 seconds
Started May 23 12:43:48 PM PDT 24
Finished May 23 12:49:48 PM PDT 24
Peak memory 200260 kb
Host smart-acc5520f-9328-45f5-97cb-d922946707c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892258482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2892258482
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2374543548
Short name T877
Test name
Test status
Simulation time 33974712337 ps
CPU time 14.47 seconds
Started May 23 12:43:54 PM PDT 24
Finished May 23 12:44:10 PM PDT 24
Peak memory 200328 kb
Host smart-90e3a26d-eaaa-48ff-8722-b3ea84870d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374543548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2374543548
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.433234423
Short name T703
Test name
Test status
Simulation time 44857531321 ps
CPU time 71.12 seconds
Started May 23 12:43:49 PM PDT 24
Finished May 23 12:45:02 PM PDT 24
Peak memory 200384 kb
Host smart-158b73a5-a51b-4f22-a506-95530669b93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433234423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.433234423
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1258375786
Short name T1171
Test name
Test status
Simulation time 14438608121 ps
CPU time 7.14 seconds
Started May 23 12:43:53 PM PDT 24
Finished May 23 12:44:01 PM PDT 24
Peak memory 200068 kb
Host smart-72c7dd62-98ee-4899-ba12-8c9a22701ac4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258375786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1258375786
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.970109615
Short name T636
Test name
Test status
Simulation time 96445350217 ps
CPU time 395.35 seconds
Started May 23 12:43:59 PM PDT 24
Finished May 23 12:50:36 PM PDT 24
Peak memory 200480 kb
Host smart-822543b0-3b2f-4842-9975-e84d37b3c134
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=970109615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.970109615
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3815313292
Short name T645
Test name
Test status
Simulation time 8367881383 ps
CPU time 2.07 seconds
Started May 23 12:43:57 PM PDT 24
Finished May 23 12:44:01 PM PDT 24
Peak memory 199324 kb
Host smart-fe14242c-819f-4567-b4f8-939f4a5947e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815313292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3815313292
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3428156658
Short name T997
Test name
Test status
Simulation time 72548186247 ps
CPU time 31.12 seconds
Started May 23 12:44:04 PM PDT 24
Finished May 23 12:44:36 PM PDT 24
Peak memory 200596 kb
Host smart-7e8b8d7f-82e4-45c1-9b92-5b9f66ecc169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428156658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3428156658
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3283389640
Short name T643
Test name
Test status
Simulation time 7200521921 ps
CPU time 80.82 seconds
Started May 23 12:43:55 PM PDT 24
Finished May 23 12:45:17 PM PDT 24
Peak memory 200456 kb
Host smart-2c2ddc8c-6d09-495d-ac45-fb710dce4877
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3283389640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3283389640
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3885373565
Short name T543
Test name
Test status
Simulation time 3051029965 ps
CPU time 13.17 seconds
Started May 23 12:43:45 PM PDT 24
Finished May 23 12:44:00 PM PDT 24
Peak memory 199348 kb
Host smart-fac76086-9f77-41b8-93c8-3aecf8af7016
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3885373565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3885373565
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.457790700
Short name T552
Test name
Test status
Simulation time 44043914808 ps
CPU time 62.92 seconds
Started May 23 12:44:14 PM PDT 24
Finished May 23 12:45:19 PM PDT 24
Peak memory 199888 kb
Host smart-ed3847c9-e88f-4732-894e-627502d48f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457790700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.457790700
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3699479972
Short name T622
Test name
Test status
Simulation time 4905542294 ps
CPU time 2.89 seconds
Started May 23 12:43:57 PM PDT 24
Finished May 23 12:44:02 PM PDT 24
Peak memory 196368 kb
Host smart-241bb109-140d-4dba-9b9a-4c1ae7a36e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699479972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3699479972
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2967733447
Short name T27
Test name
Test status
Simulation time 136335010 ps
CPU time 0.94 seconds
Started May 23 12:43:59 PM PDT 24
Finished May 23 12:44:02 PM PDT 24
Peak memory 219100 kb
Host smart-6c0ae13e-dc6e-48a7-bc89-45a4632d3228
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967733447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2967733447
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3684598775
Short name T385
Test name
Test status
Simulation time 491759871 ps
CPU time 1.94 seconds
Started May 23 12:43:45 PM PDT 24
Finished May 23 12:43:48 PM PDT 24
Peak memory 200280 kb
Host smart-46d09690-b892-416a-bbcb-59de047be165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684598775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3684598775
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2379034333
Short name T172
Test name
Test status
Simulation time 104566647302 ps
CPU time 379.98 seconds
Started May 23 12:43:59 PM PDT 24
Finished May 23 12:50:21 PM PDT 24
Peak memory 200456 kb
Host smart-5235d1a1-61f3-4aba-be2f-3cc1b4802bf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379034333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2379034333
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.810310737
Short name T53
Test name
Test status
Simulation time 255166829832 ps
CPU time 1322.73 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 01:06:03 PM PDT 24
Peak memory 226536 kb
Host smart-5415a18d-e162-4570-af21-f461562a463f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810310737 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.810310737
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1659376327
Short name T287
Test name
Test status
Simulation time 6482931499 ps
CPU time 23.48 seconds
Started May 23 12:44:12 PM PDT 24
Finished May 23 12:44:38 PM PDT 24
Peak memory 200248 kb
Host smart-cbe97dac-f311-469d-9825-dbaf7bb14051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659376327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1659376327
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.516703555
Short name T478
Test name
Test status
Simulation time 68636109027 ps
CPU time 96.71 seconds
Started May 23 12:43:47 PM PDT 24
Finished May 23 12:45:26 PM PDT 24
Peak memory 200408 kb
Host smart-43fc6ce1-7875-4901-9863-a46823002ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516703555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.516703555
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.37648339
Short name T1115
Test name
Test status
Simulation time 36814407 ps
CPU time 0.55 seconds
Started May 23 12:44:55 PM PDT 24
Finished May 23 12:44:57 PM PDT 24
Peak memory 195492 kb
Host smart-b3e094fe-5338-49bb-be87-a24bd99b4aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37648339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.37648339
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3128609740
Short name T137
Test name
Test status
Simulation time 92285831729 ps
CPU time 56.73 seconds
Started May 23 12:44:38 PM PDT 24
Finished May 23 12:45:39 PM PDT 24
Peak memory 200332 kb
Host smart-ea6acdff-8326-4669-958d-e92073208545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128609740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3128609740
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.698446634
Short name T995
Test name
Test status
Simulation time 153680661799 ps
CPU time 126.54 seconds
Started May 23 12:44:35 PM PDT 24
Finished May 23 12:46:45 PM PDT 24
Peak memory 200356 kb
Host smart-762cccb8-7307-4fc4-b4eb-35254f60987c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698446634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.698446634
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.706779170
Short name T1058
Test name
Test status
Simulation time 115368504814 ps
CPU time 58.06 seconds
Started May 23 12:44:36 PM PDT 24
Finished May 23 12:45:37 PM PDT 24
Peak memory 200304 kb
Host smart-c735b49e-812b-4335-be62-97ead4d49d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706779170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.706779170
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.352517230
Short name T1017
Test name
Test status
Simulation time 24593497324 ps
CPU time 41.05 seconds
Started May 23 12:44:38 PM PDT 24
Finished May 23 12:45:23 PM PDT 24
Peak memory 199784 kb
Host smart-9521fff0-f91b-4d9e-b32d-23a89734f004
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352517230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.352517230
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1180895683
Short name T599
Test name
Test status
Simulation time 129504000598 ps
CPU time 523.25 seconds
Started May 23 12:44:51 PM PDT 24
Finished May 23 12:53:36 PM PDT 24
Peak memory 200280 kb
Host smart-3d56d5e8-6b57-42d3-bdef-8d90dade1090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180895683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1180895683
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2803455497
Short name T769
Test name
Test status
Simulation time 5111677955 ps
CPU time 3.31 seconds
Started May 23 12:44:55 PM PDT 24
Finished May 23 12:45:00 PM PDT 24
Peak memory 198272 kb
Host smart-b125b51a-b408-4038-a807-c24a5c41d4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803455497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2803455497
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.4048389491
Short name T1163
Test name
Test status
Simulation time 167884635916 ps
CPU time 147.7 seconds
Started May 23 12:44:40 PM PDT 24
Finished May 23 12:47:11 PM PDT 24
Peak memory 199688 kb
Host smart-33dfacce-a23b-420d-83f3-9f0a6e813f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048389491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.4048389491
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.2072576825
Short name T784
Test name
Test status
Simulation time 10735554399 ps
CPU time 516.72 seconds
Started May 23 12:44:51 PM PDT 24
Finished May 23 12:53:30 PM PDT 24
Peak memory 200376 kb
Host smart-9dfec93b-d0f6-487e-8062-94955320ae1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2072576825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2072576825
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3176107699
Short name T477
Test name
Test status
Simulation time 6319114423 ps
CPU time 56.94 seconds
Started May 23 12:44:45 PM PDT 24
Finished May 23 12:45:44 PM PDT 24
Peak memory 199564 kb
Host smart-ce5bfb35-3f9d-4644-92ee-faf4e12d649e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3176107699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3176107699
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1384522177
Short name T1049
Test name
Test status
Simulation time 96718387407 ps
CPU time 36.78 seconds
Started May 23 12:44:36 PM PDT 24
Finished May 23 12:45:16 PM PDT 24
Peak memory 200272 kb
Host smart-38049e32-9321-47ff-a8fa-93b521cee7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384522177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1384522177
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1351966991
Short name T871
Test name
Test status
Simulation time 2851483223 ps
CPU time 1.95 seconds
Started May 23 12:44:33 PM PDT 24
Finished May 23 12:44:36 PM PDT 24
Peak memory 196052 kb
Host smart-17ca2939-6e28-495f-b1d1-748de32865fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351966991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1351966991
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.496393049
Short name T812
Test name
Test status
Simulation time 705388810 ps
CPU time 2.3 seconds
Started May 23 12:44:44 PM PDT 24
Finished May 23 12:44:48 PM PDT 24
Peak memory 199276 kb
Host smart-737b50a9-5e44-4dea-86fc-8d5ac8218f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496393049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.496393049
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.579931387
Short name T413
Test name
Test status
Simulation time 146245783930 ps
CPU time 338.59 seconds
Started May 23 12:44:54 PM PDT 24
Finished May 23 12:50:34 PM PDT 24
Peak memory 200388 kb
Host smart-86438d54-ab5d-4d76-b9b3-b916768905df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579931387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.579931387
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.437680258
Short name T790
Test name
Test status
Simulation time 2142337704 ps
CPU time 1.21 seconds
Started May 23 12:44:39 PM PDT 24
Finished May 23 12:44:44 PM PDT 24
Peak memory 198756 kb
Host smart-344aefc1-fe13-4ded-a973-b551c0b1816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437680258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.437680258
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.587495992
Short name T414
Test name
Test status
Simulation time 72835040708 ps
CPU time 142.4 seconds
Started May 23 12:44:39 PM PDT 24
Finished May 23 12:47:05 PM PDT 24
Peak memory 200340 kb
Host smart-97f248b7-6814-4a59-bf8f-59f5975292b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587495992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.587495992
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1498607604
Short name T139
Test name
Test status
Simulation time 38002025054 ps
CPU time 36.98 seconds
Started May 23 12:47:31 PM PDT 24
Finished May 23 12:48:10 PM PDT 24
Peak memory 200448 kb
Host smart-ffcdb2cf-6f10-436b-bc64-838dc94afcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498607604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1498607604
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.551367803
Short name T1033
Test name
Test status
Simulation time 35121873760 ps
CPU time 27.63 seconds
Started May 23 12:47:32 PM PDT 24
Finished May 23 12:48:02 PM PDT 24
Peak memory 200272 kb
Host smart-4f15e7fd-d4b1-45d8-a048-4a415af2ad3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551367803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.551367803
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.9326717
Short name T1173
Test name
Test status
Simulation time 181361577529 ps
CPU time 110.17 seconds
Started May 23 12:47:35 PM PDT 24
Finished May 23 12:49:28 PM PDT 24
Peak memory 200400 kb
Host smart-d76a10c9-e166-42ff-b3c1-38d236aed4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9326717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.9326717
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3106556883
Short name T968
Test name
Test status
Simulation time 28056068814 ps
CPU time 53.05 seconds
Started May 23 12:47:33 PM PDT 24
Finished May 23 12:48:29 PM PDT 24
Peak memory 200372 kb
Host smart-54772f07-4065-46e8-a104-d5d5ba728aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106556883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3106556883
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3539880698
Short name T350
Test name
Test status
Simulation time 97180777183 ps
CPU time 142.34 seconds
Started May 23 12:47:35 PM PDT 24
Finished May 23 12:50:00 PM PDT 24
Peak memory 200400 kb
Host smart-d8ba9d40-47e1-45ab-8b36-9884f34f646e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539880698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3539880698
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1578908876
Short name T473
Test name
Test status
Simulation time 13422260750 ps
CPU time 26.57 seconds
Started May 23 12:47:30 PM PDT 24
Finished May 23 12:47:58 PM PDT 24
Peak memory 200436 kb
Host smart-86a390f7-d2a2-49ec-95eb-852c51f000da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578908876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1578908876
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2596238755
Short name T254
Test name
Test status
Simulation time 159411227872 ps
CPU time 64.96 seconds
Started May 23 12:47:38 PM PDT 24
Finished May 23 12:48:45 PM PDT 24
Peak memory 200388 kb
Host smart-a2212a55-c09a-4232-84be-36d3f1526ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596238755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2596238755
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2239613942
Short name T176
Test name
Test status
Simulation time 13104457497 ps
CPU time 24.66 seconds
Started May 23 12:47:36 PM PDT 24
Finished May 23 12:48:04 PM PDT 24
Peak memory 200212 kb
Host smart-8bfd36c8-41d8-4c4a-8451-04f4356632b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239613942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2239613942
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2602712989
Short name T1119
Test name
Test status
Simulation time 13278782 ps
CPU time 0.55 seconds
Started May 23 12:44:54 PM PDT 24
Finished May 23 12:44:56 PM PDT 24
Peak memory 195760 kb
Host smart-9f5f69f2-3ab4-4e7b-9f45-474b987e6716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602712989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2602712989
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2149436813
Short name T1007
Test name
Test status
Simulation time 42443270965 ps
CPU time 14.45 seconds
Started May 23 12:44:49 PM PDT 24
Finished May 23 12:45:04 PM PDT 24
Peak memory 200400 kb
Host smart-33b5f43a-bb7e-4339-a276-2b5c410d864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149436813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2149436813
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1516249578
Short name T104
Test name
Test status
Simulation time 55967110323 ps
CPU time 28.21 seconds
Started May 23 12:44:51 PM PDT 24
Finished May 23 12:45:21 PM PDT 24
Peak memory 200464 kb
Host smart-c8ebbb32-8170-4e1f-9139-081231489829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516249578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1516249578
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1936102836
Short name T495
Test name
Test status
Simulation time 21143994338 ps
CPU time 29.2 seconds
Started May 23 12:44:51 PM PDT 24
Finished May 23 12:45:21 PM PDT 24
Peak memory 200440 kb
Host smart-b5a9faf0-816c-43ed-9ea3-f8ad75512186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936102836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1936102836
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.296189699
Short name T918
Test name
Test status
Simulation time 33231848537 ps
CPU time 14.27 seconds
Started May 23 12:44:55 PM PDT 24
Finished May 23 12:45:11 PM PDT 24
Peak memory 199968 kb
Host smart-6943e638-82b1-4d8e-b360-12caf302f2b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296189699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.296189699
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.114616766
Short name T497
Test name
Test status
Simulation time 87721908451 ps
CPU time 312.48 seconds
Started May 23 12:44:50 PM PDT 24
Finished May 23 12:50:04 PM PDT 24
Peak memory 200308 kb
Host smart-22001884-56dc-49bb-879b-3390db02ac62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114616766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.114616766
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2294593537
Short name T714
Test name
Test status
Simulation time 4386702770 ps
CPU time 2.73 seconds
Started May 23 12:44:53 PM PDT 24
Finished May 23 12:44:58 PM PDT 24
Peak memory 198896 kb
Host smart-6ae5928b-9b45-4f3f-aaf5-89f1f3b1a8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294593537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2294593537
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.4171272565
Short name T259
Test name
Test status
Simulation time 111752431559 ps
CPU time 135.02 seconds
Started May 23 12:44:57 PM PDT 24
Finished May 23 12:47:13 PM PDT 24
Peak memory 200592 kb
Host smart-5d99c287-28e3-4a20-9cc5-684ae77db7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171272565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.4171272565
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2886591605
Short name T807
Test name
Test status
Simulation time 10442964152 ps
CPU time 145.94 seconds
Started May 23 12:44:51 PM PDT 24
Finished May 23 12:47:19 PM PDT 24
Peak memory 200416 kb
Host smart-2cecae32-4a3b-4997-a2ce-14ed9c52ff68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886591605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2886591605
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3186585925
Short name T768
Test name
Test status
Simulation time 4797163497 ps
CPU time 39.99 seconds
Started May 23 12:44:49 PM PDT 24
Finished May 23 12:45:31 PM PDT 24
Peak memory 199388 kb
Host smart-57ea4bff-672c-4215-a223-3470ae9b66fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186585925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3186585925
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2299627960
Short name T809
Test name
Test status
Simulation time 47756228005 ps
CPU time 50.04 seconds
Started May 23 12:44:50 PM PDT 24
Finished May 23 12:45:41 PM PDT 24
Peak memory 200360 kb
Host smart-cd7e49cc-c79d-4e51-861c-c0ae68e33228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299627960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2299627960
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3268318992
Short name T630
Test name
Test status
Simulation time 49783970940 ps
CPU time 13.56 seconds
Started May 23 12:44:51 PM PDT 24
Finished May 23 12:45:06 PM PDT 24
Peak memory 196464 kb
Host smart-34e8bcd5-8660-4642-8f51-4671aa848f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268318992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3268318992
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3665182118
Short name T420
Test name
Test status
Simulation time 268253220 ps
CPU time 1.26 seconds
Started May 23 12:44:57 PM PDT 24
Finished May 23 12:44:59 PM PDT 24
Peak memory 199316 kb
Host smart-c8b7611d-a1c9-4497-a687-08f97a69bbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665182118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3665182118
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3000122336
Short name T781
Test name
Test status
Simulation time 922601695 ps
CPU time 2.68 seconds
Started May 23 12:44:53 PM PDT 24
Finished May 23 12:44:57 PM PDT 24
Peak memory 199300 kb
Host smart-c5c2c22a-8ac3-447c-8169-e4ec81ebdd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000122336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3000122336
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1652007077
Short name T786
Test name
Test status
Simulation time 94467571003 ps
CPU time 13.37 seconds
Started May 23 12:44:52 PM PDT 24
Finished May 23 12:45:08 PM PDT 24
Peak memory 200308 kb
Host smart-f025bad8-0a09-4f65-8ab7-c62927ad1796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652007077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1652007077
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2980118858
Short name T1164
Test name
Test status
Simulation time 131060148107 ps
CPU time 189.18 seconds
Started May 23 12:47:36 PM PDT 24
Finished May 23 12:50:48 PM PDT 24
Peak memory 200340 kb
Host smart-4067c92d-fb84-4e08-b82d-3a281c454fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980118858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2980118858
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3131715594
Short name T179
Test name
Test status
Simulation time 246540126101 ps
CPU time 225.5 seconds
Started May 23 12:47:36 PM PDT 24
Finished May 23 12:51:24 PM PDT 24
Peak memory 200404 kb
Host smart-bf6506d4-eba7-4e6c-be29-42631b18702d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131715594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3131715594
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3842795421
Short name T1097
Test name
Test status
Simulation time 40599513472 ps
CPU time 30.28 seconds
Started May 23 12:47:35 PM PDT 24
Finished May 23 12:48:09 PM PDT 24
Peak memory 200240 kb
Host smart-3e9f1ef1-49de-45be-97f5-1e0d18d6cf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842795421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3842795421
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.3844374282
Short name T681
Test name
Test status
Simulation time 17593427685 ps
CPU time 29.92 seconds
Started May 23 12:47:35 PM PDT 24
Finished May 23 12:48:08 PM PDT 24
Peak memory 200408 kb
Host smart-47f5fe46-6269-436d-b015-60ec54308aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844374282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3844374282
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.921461314
Short name T831
Test name
Test status
Simulation time 86478692203 ps
CPU time 35.83 seconds
Started May 23 12:47:31 PM PDT 24
Finished May 23 12:48:09 PM PDT 24
Peak memory 200340 kb
Host smart-b6fea48e-488f-448c-9044-f08e26764c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921461314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.921461314
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1350802438
Short name T347
Test name
Test status
Simulation time 9220739577 ps
CPU time 15.63 seconds
Started May 23 12:47:34 PM PDT 24
Finished May 23 12:47:52 PM PDT 24
Peak memory 200416 kb
Host smart-de1a2962-a57d-401b-9ee9-fa3bec7c00ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350802438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1350802438
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3072877249
Short name T174
Test name
Test status
Simulation time 69828922955 ps
CPU time 31.78 seconds
Started May 23 12:47:44 PM PDT 24
Finished May 23 12:48:17 PM PDT 24
Peak memory 200384 kb
Host smart-0bca5a94-69ef-46ff-9d10-6b79c15c5ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072877249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3072877249
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.781129170
Short name T196
Test name
Test status
Simulation time 55282467564 ps
CPU time 24.47 seconds
Started May 23 12:47:44 PM PDT 24
Finished May 23 12:48:10 PM PDT 24
Peak memory 200320 kb
Host smart-e68f5a74-41cf-4c79-9a74-00c0c59d3940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781129170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.781129170
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3272661785
Short name T1099
Test name
Test status
Simulation time 147173960322 ps
CPU time 56.59 seconds
Started May 23 12:47:45 PM PDT 24
Finished May 23 12:48:43 PM PDT 24
Peak memory 200388 kb
Host smart-bd375604-0741-49cd-9a8d-702923c42199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272661785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3272661785
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.838568948
Short name T685
Test name
Test status
Simulation time 218893119359 ps
CPU time 118.55 seconds
Started May 23 12:47:44 PM PDT 24
Finished May 23 12:49:44 PM PDT 24
Peak memory 200288 kb
Host smart-46109705-2724-46c8-abb4-1b11a4077cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838568948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.838568948
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2558084838
Short name T25
Test name
Test status
Simulation time 47821804 ps
CPU time 0.56 seconds
Started May 23 12:44:54 PM PDT 24
Finished May 23 12:44:57 PM PDT 24
Peak memory 195748 kb
Host smart-476dbeef-0ded-4666-b0d9-689768379fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558084838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2558084838
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2470041684
Short name T525
Test name
Test status
Simulation time 22646070147 ps
CPU time 34.33 seconds
Started May 23 12:44:52 PM PDT 24
Finished May 23 12:45:28 PM PDT 24
Peak memory 200368 kb
Host smart-98dd188a-4bda-43ec-9983-78d978c39f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470041684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2470041684
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2035681542
Short name T1151
Test name
Test status
Simulation time 39547215144 ps
CPU time 16.81 seconds
Started May 23 12:44:52 PM PDT 24
Finished May 23 12:45:11 PM PDT 24
Peak memory 200448 kb
Host smart-d8c353cc-b4e7-499f-be65-d3b4dd0f4af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035681542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2035681542
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3468627114
Short name T838
Test name
Test status
Simulation time 31820219354 ps
CPU time 76.53 seconds
Started May 23 12:44:55 PM PDT 24
Finished May 23 12:46:13 PM PDT 24
Peak memory 200340 kb
Host smart-e99b1b87-c8b9-49a4-b26f-b35e2df0729a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468627114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3468627114
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1902092919
Short name T1010
Test name
Test status
Simulation time 61593792073 ps
CPU time 22.43 seconds
Started May 23 12:44:54 PM PDT 24
Finished May 23 12:45:18 PM PDT 24
Peak memory 199284 kb
Host smart-57c5326d-307b-415a-9969-7d2f31378031
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902092919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1902092919
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3463947346
Short name T798
Test name
Test status
Simulation time 197304167130 ps
CPU time 672.54 seconds
Started May 23 12:44:52 PM PDT 24
Finished May 23 12:56:07 PM PDT 24
Peak memory 200456 kb
Host smart-3171d1d1-b7b7-4608-afb8-5f7de87a4c39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3463947346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3463947346
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2176422973
Short name T1050
Test name
Test status
Simulation time 6674025244 ps
CPU time 3.12 seconds
Started May 23 12:44:50 PM PDT 24
Finished May 23 12:44:55 PM PDT 24
Peak memory 199024 kb
Host smart-2fb303eb-654c-4bd0-ba52-bf44b1a75111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176422973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2176422973
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.351870115
Short name T499
Test name
Test status
Simulation time 47664116121 ps
CPU time 84.43 seconds
Started May 23 12:44:53 PM PDT 24
Finished May 23 12:46:19 PM PDT 24
Peak memory 208640 kb
Host smart-85769a38-7eaf-4273-9963-2d8ea8aec069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351870115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.351870115
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.896522940
Short name T787
Test name
Test status
Simulation time 8469243765 ps
CPU time 238.67 seconds
Started May 23 12:44:48 PM PDT 24
Finished May 23 12:48:47 PM PDT 24
Peak memory 200316 kb
Host smart-63778d26-eb26-4f70-8aa9-26c493614592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896522940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.896522940
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1322004130
Short name T870
Test name
Test status
Simulation time 2533254909 ps
CPU time 21.79 seconds
Started May 23 12:44:52 PM PDT 24
Finished May 23 12:45:15 PM PDT 24
Peak memory 199488 kb
Host smart-d8002856-592b-4fa6-b343-efe20c751c1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1322004130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1322004130
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1379299795
Short name T659
Test name
Test status
Simulation time 74383815687 ps
CPU time 177.55 seconds
Started May 23 12:44:50 PM PDT 24
Finished May 23 12:47:49 PM PDT 24
Peak memory 200480 kb
Host smart-ba496d8e-9837-4a0f-85f3-3aa4c7829d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379299795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1379299795
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2906471912
Short name T902
Test name
Test status
Simulation time 3544724014 ps
CPU time 5.97 seconds
Started May 23 12:44:53 PM PDT 24
Finished May 23 12:45:01 PM PDT 24
Peak memory 196368 kb
Host smart-80506e11-53b0-41f0-97f8-73b3e9a191e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906471912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2906471912
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1730719040
Short name T34
Test name
Test status
Simulation time 5898481789 ps
CPU time 14.24 seconds
Started May 23 12:44:53 PM PDT 24
Finished May 23 12:45:10 PM PDT 24
Peak memory 200240 kb
Host smart-ec681be2-7078-4435-a65c-636c89cb3d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730719040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1730719040
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2333966637
Short name T626
Test name
Test status
Simulation time 103032511582 ps
CPU time 22.76 seconds
Started May 23 12:44:55 PM PDT 24
Finished May 23 12:45:19 PM PDT 24
Peak memory 200424 kb
Host smart-26a4c0f6-275e-4bb9-b070-978c30c34093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333966637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2333966637
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2183841304
Short name T878
Test name
Test status
Simulation time 1282407049 ps
CPU time 4.7 seconds
Started May 23 12:44:52 PM PDT 24
Finished May 23 12:44:58 PM PDT 24
Peak memory 199720 kb
Host smart-6daac6e1-01f0-42fd-8ff0-ffdd08cdd199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183841304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2183841304
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2859285047
Short name T1170
Test name
Test status
Simulation time 35021515470 ps
CPU time 58.4 seconds
Started May 23 12:44:51 PM PDT 24
Finished May 23 12:45:51 PM PDT 24
Peak memory 200348 kb
Host smart-398029b3-4451-42c6-8c5f-12840b6102f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859285047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2859285047
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3311985055
Short name T827
Test name
Test status
Simulation time 32349121399 ps
CPU time 17.57 seconds
Started May 23 12:47:44 PM PDT 24
Finished May 23 12:48:04 PM PDT 24
Peak memory 200468 kb
Host smart-65961c59-a4f5-4816-96f8-673190f6606c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311985055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3311985055
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.341102508
Short name T346
Test name
Test status
Simulation time 23901930801 ps
CPU time 15.72 seconds
Started May 23 12:47:46 PM PDT 24
Finished May 23 12:48:03 PM PDT 24
Peak memory 200388 kb
Host smart-b3c93980-5f5c-492f-8069-cf08a8f4141c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341102508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.341102508
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2793529064
Short name T1074
Test name
Test status
Simulation time 53254753540 ps
CPU time 91.78 seconds
Started May 23 12:47:44 PM PDT 24
Finished May 23 12:49:18 PM PDT 24
Peak memory 200288 kb
Host smart-e540ec66-64f2-43ee-a24a-fcc414227355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793529064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2793529064
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2948093444
Short name T792
Test name
Test status
Simulation time 102657441763 ps
CPU time 36.66 seconds
Started May 23 12:47:43 PM PDT 24
Finished May 23 12:48:22 PM PDT 24
Peak memory 200312 kb
Host smart-43173261-edf0-447e-b1c2-6f7f43237602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948093444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2948093444
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3656736833
Short name T1025
Test name
Test status
Simulation time 39625597803 ps
CPU time 18.99 seconds
Started May 23 12:47:44 PM PDT 24
Finished May 23 12:48:05 PM PDT 24
Peak memory 200352 kb
Host smart-69d559fb-90f9-4ad7-9011-8534c8ebf966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656736833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3656736833
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1218554700
Short name T975
Test name
Test status
Simulation time 9990239130 ps
CPU time 17.08 seconds
Started May 23 12:47:43 PM PDT 24
Finished May 23 12:48:02 PM PDT 24
Peak memory 199044 kb
Host smart-f02934c8-dc11-4d32-a939-ac13ccd2ad0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218554700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1218554700
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1000626736
Short name T181
Test name
Test status
Simulation time 177296564510 ps
CPU time 68.62 seconds
Started May 23 12:47:43 PM PDT 24
Finished May 23 12:48:54 PM PDT 24
Peak memory 200356 kb
Host smart-d2881465-ab65-42ff-817a-a78360310315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000626736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1000626736
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2479891753
Short name T978
Test name
Test status
Simulation time 22854630 ps
CPU time 0.56 seconds
Started May 23 12:45:04 PM PDT 24
Finished May 23 12:45:07 PM PDT 24
Peak memory 195720 kb
Host smart-c73e0a3f-6fe0-4d06-8214-f0e3ab9731f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479891753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2479891753
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2073296815
Short name T144
Test name
Test status
Simulation time 39499654296 ps
CPU time 35.71 seconds
Started May 23 12:44:57 PM PDT 24
Finished May 23 12:45:34 PM PDT 24
Peak memory 200396 kb
Host smart-bc639f9e-5e72-4797-8ebb-9782902815c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073296815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2073296815
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1822321327
Short name T755
Test name
Test status
Simulation time 97541715120 ps
CPU time 88.06 seconds
Started May 23 12:44:52 PM PDT 24
Finished May 23 12:46:22 PM PDT 24
Peak memory 200256 kb
Host smart-61e755ae-e3da-41cf-a12a-d7d21fa3ece8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822321327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1822321327
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3567109801
Short name T1082
Test name
Test status
Simulation time 41798467028 ps
CPU time 72.61 seconds
Started May 23 12:44:54 PM PDT 24
Finished May 23 12:46:08 PM PDT 24
Peak memory 200392 kb
Host smart-36cc5ad7-6d04-45d6-9794-b9c27e176e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567109801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3567109801
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1969415825
Short name T399
Test name
Test status
Simulation time 16060004959 ps
CPU time 50.01 seconds
Started May 23 12:44:53 PM PDT 24
Finished May 23 12:45:45 PM PDT 24
Peak memory 200292 kb
Host smart-37af3876-ff7b-465c-bb42-47bb547438fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969415825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1969415825
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1652758416
Short name T711
Test name
Test status
Simulation time 55429344726 ps
CPU time 396.68 seconds
Started May 23 12:44:54 PM PDT 24
Finished May 23 12:51:32 PM PDT 24
Peak memory 200464 kb
Host smart-fea4bd0e-f48a-4042-b59c-0069e8de7f4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652758416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1652758416
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.729905436
Short name T1034
Test name
Test status
Simulation time 7173470156 ps
CPU time 6.2 seconds
Started May 23 12:44:58 PM PDT 24
Finished May 23 12:45:05 PM PDT 24
Peak memory 199772 kb
Host smart-c078f55b-db12-4974-bf5a-32221e51ac0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729905436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.729905436
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.4938430
Short name T653
Test name
Test status
Simulation time 109099500894 ps
CPU time 88.98 seconds
Started May 23 12:44:53 PM PDT 24
Finished May 23 12:46:24 PM PDT 24
Peak memory 208836 kb
Host smart-e9821096-e4d3-4a27-864f-cc198d6d2ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4938430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.4938430
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1723072259
Short name T445
Test name
Test status
Simulation time 14727446764 ps
CPU time 116.94 seconds
Started May 23 12:44:51 PM PDT 24
Finished May 23 12:46:49 PM PDT 24
Peak memory 200300 kb
Host smart-90f5daa5-e8f6-4166-a165-47b18633a007
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1723072259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1723072259
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1775729917
Short name T894
Test name
Test status
Simulation time 3933662233 ps
CPU time 4.62 seconds
Started May 23 12:44:53 PM PDT 24
Finished May 23 12:44:59 PM PDT 24
Peak memory 199280 kb
Host smart-af825ccd-6a20-4460-b847-78655da86323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775729917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1775729917
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2693189750
Short name T496
Test name
Test status
Simulation time 21110841220 ps
CPU time 35.44 seconds
Started May 23 12:44:49 PM PDT 24
Finished May 23 12:45:26 PM PDT 24
Peak memory 200332 kb
Host smart-0091b1b0-606c-4ceb-8db1-e742ff3890a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693189750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2693189750
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3226520762
Short name T1112
Test name
Test status
Simulation time 1713513595 ps
CPU time 1.39 seconds
Started May 23 12:44:52 PM PDT 24
Finished May 23 12:44:55 PM PDT 24
Peak memory 195836 kb
Host smart-a1240503-927d-465b-9c64-be1e7fd80b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226520762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3226520762
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2575952338
Short name T1093
Test name
Test status
Simulation time 669831472 ps
CPU time 2.81 seconds
Started May 23 12:44:52 PM PDT 24
Finished May 23 12:44:57 PM PDT 24
Peak memory 198940 kb
Host smart-f0d0d84a-1227-417f-8a80-ba25fcdd7fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575952338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2575952338
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.691638356
Short name T951
Test name
Test status
Simulation time 176626480389 ps
CPU time 1016.22 seconds
Started May 23 12:45:05 PM PDT 24
Finished May 23 01:02:03 PM PDT 24
Peak memory 200296 kb
Host smart-baac4b85-c5ec-46a5-9e92-b308640129ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691638356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.691638356
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.667562915
Short name T953
Test name
Test status
Simulation time 129623316530 ps
CPU time 205.29 seconds
Started May 23 12:45:01 PM PDT 24
Finished May 23 12:48:28 PM PDT 24
Peak memory 216756 kb
Host smart-6a982ef3-2fdf-47f0-b67a-9977f633dbe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667562915 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.667562915
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2705234640
Short name T448
Test name
Test status
Simulation time 7156667277 ps
CPU time 1.55 seconds
Started May 23 12:44:53 PM PDT 24
Finished May 23 12:44:56 PM PDT 24
Peak memory 199668 kb
Host smart-47a48c39-ee00-47b9-9675-650342e451a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705234640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2705234640
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1111885687
Short name T424
Test name
Test status
Simulation time 21854877942 ps
CPU time 37.81 seconds
Started May 23 12:44:52 PM PDT 24
Finished May 23 12:45:32 PM PDT 24
Peak memory 200464 kb
Host smart-80b738f2-5acb-4557-a3cc-2759b902de4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111885687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1111885687
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.4201713249
Short name T202
Test name
Test status
Simulation time 62344738150 ps
CPU time 24.13 seconds
Started May 23 12:47:43 PM PDT 24
Finished May 23 12:48:09 PM PDT 24
Peak memory 200484 kb
Host smart-c4ee687a-1b13-4622-ab7f-437b6bbf00ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201713249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.4201713249
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3772286902
Short name T516
Test name
Test status
Simulation time 248477655016 ps
CPU time 211.85 seconds
Started May 23 12:47:43 PM PDT 24
Finished May 23 12:51:16 PM PDT 24
Peak memory 200460 kb
Host smart-726356fe-d69f-436c-8b3f-edee12b8f1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772286902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3772286902
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2957285722
Short name T578
Test name
Test status
Simulation time 152030010519 ps
CPU time 19.82 seconds
Started May 23 12:47:45 PM PDT 24
Finished May 23 12:48:06 PM PDT 24
Peak memory 200064 kb
Host smart-98e236f9-2e2d-4ec5-aa44-f413752cede1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957285722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2957285722
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.426154754
Short name T863
Test name
Test status
Simulation time 73698251024 ps
CPU time 58.76 seconds
Started May 23 12:47:47 PM PDT 24
Finished May 23 12:48:46 PM PDT 24
Peak memory 200448 kb
Host smart-7a764a2f-4f69-4b65-9398-de859685b97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426154754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.426154754
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3266086722
Short name T762
Test name
Test status
Simulation time 157832283259 ps
CPU time 39.91 seconds
Started May 23 12:47:46 PM PDT 24
Finished May 23 12:48:27 PM PDT 24
Peak memory 200372 kb
Host smart-58d394c6-3198-4308-b140-4970b96c4f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266086722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3266086722
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.221899851
Short name T194
Test name
Test status
Simulation time 11051343740 ps
CPU time 19.83 seconds
Started May 23 12:47:44 PM PDT 24
Finished May 23 12:48:06 PM PDT 24
Peak memory 200160 kb
Host smart-d0adef8b-1f76-43fa-8a97-4fd6d805b608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221899851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.221899851
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2203124392
Short name T231
Test name
Test status
Simulation time 82490086135 ps
CPU time 30.72 seconds
Started May 23 12:47:44 PM PDT 24
Finished May 23 12:48:17 PM PDT 24
Peak memory 200508 kb
Host smart-8fcc3785-ab7c-4d9c-8a56-73cb9010cd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203124392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2203124392
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2308797126
Short name T136
Test name
Test status
Simulation time 16555682438 ps
CPU time 29.93 seconds
Started May 23 12:47:43 PM PDT 24
Finished May 23 12:48:15 PM PDT 24
Peak memory 200408 kb
Host smart-80714c1e-cee9-4059-af1d-89850530f713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308797126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2308797126
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3269100176
Short name T130
Test name
Test status
Simulation time 136512676688 ps
CPU time 236.07 seconds
Started May 23 12:47:44 PM PDT 24
Finished May 23 12:51:42 PM PDT 24
Peak memory 200336 kb
Host smart-90bf9347-cae4-4e9a-956f-e61a8101e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269100176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3269100176
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.531935044
Short name T26
Test name
Test status
Simulation time 18338907 ps
CPU time 0.55 seconds
Started May 23 12:45:04 PM PDT 24
Finished May 23 12:45:06 PM PDT 24
Peak memory 195296 kb
Host smart-97cfcf2d-3449-464d-b42f-f8f7a10d16c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531935044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.531935044
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.565722954
Short name T471
Test name
Test status
Simulation time 44927541089 ps
CPU time 65.51 seconds
Started May 23 12:45:00 PM PDT 24
Finished May 23 12:46:07 PM PDT 24
Peak memory 200380 kb
Host smart-8c41a8fd-bd7b-4329-be52-68b927e773f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565722954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.565722954
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3270480034
Short name T775
Test name
Test status
Simulation time 7762461621 ps
CPU time 11.3 seconds
Started May 23 12:45:00 PM PDT 24
Finished May 23 12:45:13 PM PDT 24
Peak memory 199548 kb
Host smart-84f085ca-d12e-41ac-8d31-0547c2e99db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270480034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3270480034
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3359264623
Short name T155
Test name
Test status
Simulation time 148042718505 ps
CPU time 117.63 seconds
Started May 23 12:45:01 PM PDT 24
Finished May 23 12:47:01 PM PDT 24
Peak memory 200340 kb
Host smart-818a8e59-a8a8-47ef-ad80-4ec20412ef1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359264623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3359264623
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2592767137
Short name T342
Test name
Test status
Simulation time 47883736371 ps
CPU time 103.41 seconds
Started May 23 12:45:05 PM PDT 24
Finished May 23 12:46:50 PM PDT 24
Peak memory 200288 kb
Host smart-9cf51993-0ffd-4ba2-8eb8-e46edd91092f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592767137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2592767137
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1516713492
Short name T1116
Test name
Test status
Simulation time 96238105747 ps
CPU time 601.16 seconds
Started May 23 12:45:02 PM PDT 24
Finished May 23 12:55:05 PM PDT 24
Peak memory 200340 kb
Host smart-14d19f1b-b3fc-4e6e-9582-a2043055bdb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1516713492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1516713492
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3581526795
Short name T379
Test name
Test status
Simulation time 7138969434 ps
CPU time 20.1 seconds
Started May 23 12:45:00 PM PDT 24
Finished May 23 12:45:21 PM PDT 24
Peak memory 200316 kb
Host smart-84dd7f32-fdb9-4a08-a824-74fae1fb64c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581526795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3581526795
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3112814719
Short name T984
Test name
Test status
Simulation time 269271326683 ps
CPU time 34.26 seconds
Started May 23 12:45:02 PM PDT 24
Finished May 23 12:45:38 PM PDT 24
Peak memory 200876 kb
Host smart-6b768bcc-fed9-4e56-b91d-bac2ef9171ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112814719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3112814719
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2251551085
Short name T493
Test name
Test status
Simulation time 11841886703 ps
CPU time 273.59 seconds
Started May 23 12:45:02 PM PDT 24
Finished May 23 12:49:37 PM PDT 24
Peak memory 200340 kb
Host smart-4a9aee61-4d83-4862-915c-231d4ea19a0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251551085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2251551085
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1634106666
Short name T855
Test name
Test status
Simulation time 3063249676 ps
CPU time 11.82 seconds
Started May 23 12:45:01 PM PDT 24
Finished May 23 12:45:15 PM PDT 24
Peak memory 198800 kb
Host smart-fb835bb5-4136-445d-bfea-d6dc844e6d19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634106666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1634106666
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.559870084
Short name T173
Test name
Test status
Simulation time 208395901552 ps
CPU time 84.52 seconds
Started May 23 12:45:00 PM PDT 24
Finished May 23 12:46:26 PM PDT 24
Peak memory 200328 kb
Host smart-9db33350-3856-46cc-9db1-a76e5c290a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559870084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.559870084
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2603008265
Short name T534
Test name
Test status
Simulation time 33529902181 ps
CPU time 14 seconds
Started May 23 12:45:03 PM PDT 24
Finished May 23 12:45:19 PM PDT 24
Peak memory 196200 kb
Host smart-c313bb45-7df7-4043-bb9f-39e8efee072b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603008265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2603008265
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3828932677
Short name T309
Test name
Test status
Simulation time 5567687050 ps
CPU time 9 seconds
Started May 23 12:45:03 PM PDT 24
Finished May 23 12:45:13 PM PDT 24
Peak memory 199688 kb
Host smart-2f75bb9b-41c9-4d29-84d1-f7a91d2ee2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828932677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3828932677
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2416282476
Short name T59
Test name
Test status
Simulation time 12242042094 ps
CPU time 138.29 seconds
Started May 23 12:45:01 PM PDT 24
Finished May 23 12:47:20 PM PDT 24
Peak memory 217176 kb
Host smart-0b952ae4-76a3-4fec-9f4b-19ee632a950b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416282476 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2416282476
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2618085433
Short name T664
Test name
Test status
Simulation time 6191688237 ps
CPU time 13.88 seconds
Started May 23 12:45:02 PM PDT 24
Finished May 23 12:45:17 PM PDT 24
Peak memory 199704 kb
Host smart-e6f0546a-af3c-439c-b235-a18ee2e014c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618085433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2618085433
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1985517925
Short name T387
Test name
Test status
Simulation time 11601908144 ps
CPU time 11.08 seconds
Started May 23 12:45:03 PM PDT 24
Finished May 23 12:45:16 PM PDT 24
Peak memory 197352 kb
Host smart-d0539c8f-81da-4efe-8fb5-41a3f5024495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985517925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1985517925
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2481833765
Short name T648
Test name
Test status
Simulation time 162816269187 ps
CPU time 205.13 seconds
Started May 23 12:47:43 PM PDT 24
Finished May 23 12:51:11 PM PDT 24
Peak memory 200244 kb
Host smart-ed4fbebd-da59-45a8-9ba6-75d2fd5285b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481833765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2481833765
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1196680604
Short name T182
Test name
Test status
Simulation time 163326790551 ps
CPU time 291.57 seconds
Started May 23 12:47:43 PM PDT 24
Finished May 23 12:52:37 PM PDT 24
Peak memory 200384 kb
Host smart-a4a3e6ce-2f77-40e1-9088-4c49d3402679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196680604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1196680604
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1224532568
Short name T201
Test name
Test status
Simulation time 72249741102 ps
CPU time 68.86 seconds
Started May 23 12:47:45 PM PDT 24
Finished May 23 12:48:55 PM PDT 24
Peak memory 200288 kb
Host smart-79adca1c-4aa8-4695-bfc2-17c9c67092ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224532568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1224532568
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1904245985
Short name T1153
Test name
Test status
Simulation time 65950561548 ps
CPU time 129.45 seconds
Started May 23 12:47:47 PM PDT 24
Finished May 23 12:49:57 PM PDT 24
Peak memory 200444 kb
Host smart-82503e17-78c4-4bfb-9c77-73f9081a4697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904245985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1904245985
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1137010632
Short name T158
Test name
Test status
Simulation time 40164179226 ps
CPU time 72.53 seconds
Started May 23 12:47:43 PM PDT 24
Finished May 23 12:48:58 PM PDT 24
Peak memory 200300 kb
Host smart-3846809b-bc8e-4113-836a-5911b23f2ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137010632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1137010632
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2263456922
Short name T828
Test name
Test status
Simulation time 46306250094 ps
CPU time 39.62 seconds
Started May 23 12:47:43 PM PDT 24
Finished May 23 12:48:24 PM PDT 24
Peak memory 200412 kb
Host smart-97389fb9-bfe9-444f-ad08-0c6c08245512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263456922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2263456922
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1833733958
Short name T549
Test name
Test status
Simulation time 149937210870 ps
CPU time 221.82 seconds
Started May 23 12:47:43 PM PDT 24
Finished May 23 12:51:27 PM PDT 24
Peak memory 200400 kb
Host smart-672a64e7-0324-48c0-a274-1df92bb8a31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833733958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1833733958
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.4098858262
Short name T1135
Test name
Test status
Simulation time 122015757258 ps
CPU time 217.88 seconds
Started May 23 12:47:58 PM PDT 24
Finished May 23 12:51:37 PM PDT 24
Peak memory 200272 kb
Host smart-6a468d53-17da-4817-acfe-11ddd67fd04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098858262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.4098858262
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1478728225
Short name T900
Test name
Test status
Simulation time 269186354450 ps
CPU time 44.61 seconds
Started May 23 12:47:55 PM PDT 24
Finished May 23 12:48:41 PM PDT 24
Peak memory 200364 kb
Host smart-e81f40ac-c80d-4941-a9ce-a16b43f02ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478728225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1478728225
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2022927301
Short name T515
Test name
Test status
Simulation time 24070363 ps
CPU time 0.55 seconds
Started May 23 12:45:02 PM PDT 24
Finished May 23 12:45:04 PM PDT 24
Peak memory 194740 kb
Host smart-315b0a99-6d67-4daf-933b-23b37534f3bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022927301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2022927301
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1764415374
Short name T725
Test name
Test status
Simulation time 326282311767 ps
CPU time 99.14 seconds
Started May 23 12:45:02 PM PDT 24
Finished May 23 12:46:42 PM PDT 24
Peak memory 200396 kb
Host smart-f057b1a4-2ffd-4c5c-a5c6-80dd80b1c865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764415374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1764415374
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.583938278
Short name T793
Test name
Test status
Simulation time 23035044395 ps
CPU time 11.43 seconds
Started May 23 12:45:06 PM PDT 24
Finished May 23 12:45:18 PM PDT 24
Peak memory 200372 kb
Host smart-8acdbc91-cc27-4303-a338-04734301e8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583938278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.583938278
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.4111957825
Short name T163
Test name
Test status
Simulation time 28482556518 ps
CPU time 49.07 seconds
Started May 23 12:45:03 PM PDT 24
Finished May 23 12:45:53 PM PDT 24
Peak memory 200480 kb
Host smart-12eca63c-df8c-4823-944c-9f26561d562f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111957825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.4111957825
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3818113197
Short name T415
Test name
Test status
Simulation time 19680632114 ps
CPU time 30.48 seconds
Started May 23 12:45:04 PM PDT 24
Finished May 23 12:45:36 PM PDT 24
Peak memory 198180 kb
Host smart-0fe9649b-b235-496d-8f0e-a2a03d0193dc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818113197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3818113197
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.552954682
Short name T638
Test name
Test status
Simulation time 123912411180 ps
CPU time 887.89 seconds
Started May 23 12:45:02 PM PDT 24
Finished May 23 12:59:51 PM PDT 24
Peak memory 200444 kb
Host smart-0cc263b8-7158-4db7-a836-db8d1a44d04d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552954682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.552954682
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1120497886
Short name T1142
Test name
Test status
Simulation time 6342451888 ps
CPU time 6.85 seconds
Started May 23 12:45:02 PM PDT 24
Finished May 23 12:45:10 PM PDT 24
Peak memory 200392 kb
Host smart-48f1fd53-276c-485c-a9cc-5c344bfa96df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120497886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1120497886
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2865984569
Short name T1132
Test name
Test status
Simulation time 52423825622 ps
CPU time 54.94 seconds
Started May 23 12:45:03 PM PDT 24
Finished May 23 12:46:00 PM PDT 24
Peak memory 200264 kb
Host smart-1975f274-07e3-481c-aa9b-597e64645cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865984569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2865984569
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3387069728
Short name T541
Test name
Test status
Simulation time 26072648370 ps
CPU time 298.99 seconds
Started May 23 12:45:01 PM PDT 24
Finished May 23 12:50:01 PM PDT 24
Peak memory 200464 kb
Host smart-012916f9-8fe2-4d4a-bffc-cb19e1bfa18d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387069728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3387069728
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2782957768
Short name T370
Test name
Test status
Simulation time 6758014667 ps
CPU time 12.72 seconds
Started May 23 12:45:01 PM PDT 24
Finished May 23 12:45:15 PM PDT 24
Peak memory 199412 kb
Host smart-01591a74-0906-460a-8742-84f83f4950d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782957768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2782957768
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.384770192
Short name T279
Test name
Test status
Simulation time 64514780161 ps
CPU time 21.21 seconds
Started May 23 12:45:06 PM PDT 24
Finished May 23 12:45:28 PM PDT 24
Peak memory 199736 kb
Host smart-b18abab7-fa88-4ad1-a2b8-2d736df61fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384770192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.384770192
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2298814248
Short name T757
Test name
Test status
Simulation time 1558668510 ps
CPU time 1.39 seconds
Started May 23 12:44:59 PM PDT 24
Finished May 23 12:45:01 PM PDT 24
Peak memory 195888 kb
Host smart-94763994-29cb-440c-a27c-5ec68fdbcd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298814248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2298814248
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1689819490
Short name T773
Test name
Test status
Simulation time 463857733 ps
CPU time 2 seconds
Started May 23 12:45:00 PM PDT 24
Finished May 23 12:45:03 PM PDT 24
Peak memory 199212 kb
Host smart-42370e21-d92a-4215-b299-0011e5de800e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689819490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1689819490
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2527377186
Short name T291
Test name
Test status
Simulation time 2939915069 ps
CPU time 3.92 seconds
Started May 23 12:45:01 PM PDT 24
Finished May 23 12:45:06 PM PDT 24
Peak memory 200388 kb
Host smart-2e002116-29c4-435b-abde-8fa1fff7f97b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527377186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2527377186
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1639470374
Short name T866
Test name
Test status
Simulation time 26720809236 ps
CPU time 256.69 seconds
Started May 23 12:45:02 PM PDT 24
Finished May 23 12:49:20 PM PDT 24
Peak memory 217076 kb
Host smart-0ba9fb86-989c-4252-aa30-3258749fdd58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639470374 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1639470374
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1074421857
Short name T1084
Test name
Test status
Simulation time 7574567203 ps
CPU time 11.54 seconds
Started May 23 12:45:03 PM PDT 24
Finished May 23 12:45:16 PM PDT 24
Peak memory 199564 kb
Host smart-60ada709-86a3-4587-aae9-2e3027cf0da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074421857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1074421857
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.905479190
Short name T71
Test name
Test status
Simulation time 33726615272 ps
CPU time 60.45 seconds
Started May 23 12:45:01 PM PDT 24
Finished May 23 12:46:03 PM PDT 24
Peak memory 200340 kb
Host smart-b11b045a-e413-4e19-b929-c5ff057bab95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905479190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.905479190
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1444806812
Short name T1120
Test name
Test status
Simulation time 119060863358 ps
CPU time 400.05 seconds
Started May 23 12:47:57 PM PDT 24
Finished May 23 12:54:38 PM PDT 24
Peak memory 200528 kb
Host smart-06eadb4d-f0de-41a4-b8d0-767d3a9ae385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444806812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1444806812
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.351219572
Short name T151
Test name
Test status
Simulation time 21752099802 ps
CPU time 39.78 seconds
Started May 23 12:47:56 PM PDT 24
Finished May 23 12:48:36 PM PDT 24
Peak memory 200420 kb
Host smart-cda3eb2c-f727-44b1-9671-c6251a8c3cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351219572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.351219572
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2435452061
Short name T35
Test name
Test status
Simulation time 16593665990 ps
CPU time 28.39 seconds
Started May 23 12:47:55 PM PDT 24
Finished May 23 12:48:24 PM PDT 24
Peak memory 200376 kb
Host smart-b6d32480-d793-48cd-8d35-e761f7fec28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435452061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2435452061
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3315247486
Short name T752
Test name
Test status
Simulation time 176618518052 ps
CPU time 17.9 seconds
Started May 23 12:47:58 PM PDT 24
Finished May 23 12:48:17 PM PDT 24
Peak memory 200288 kb
Host smart-6271f1bc-8cee-4bd7-9e88-42a15a1487d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315247486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3315247486
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1747584182
Short name T349
Test name
Test status
Simulation time 114532552861 ps
CPU time 109.72 seconds
Started May 23 12:47:58 PM PDT 24
Finished May 23 12:49:49 PM PDT 24
Peak memory 200324 kb
Host smart-5e4db9fe-f1a3-43e4-9f99-7b7a04836116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747584182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1747584182
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3508703318
Short name T603
Test name
Test status
Simulation time 67979765826 ps
CPU time 20.05 seconds
Started May 23 12:47:58 PM PDT 24
Finished May 23 12:48:19 PM PDT 24
Peak memory 200332 kb
Host smart-4ac55f04-712e-40b8-92dd-49880b345fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508703318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3508703318
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2651986024
Short name T185
Test name
Test status
Simulation time 34675147064 ps
CPU time 64.18 seconds
Started May 23 12:47:57 PM PDT 24
Finished May 23 12:49:02 PM PDT 24
Peak memory 200380 kb
Host smart-4200ba46-1df4-4d1b-9675-416f162de733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651986024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2651986024
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1172213033
Short name T721
Test name
Test status
Simulation time 109215136425 ps
CPU time 73.68 seconds
Started May 23 12:47:56 PM PDT 24
Finished May 23 12:49:11 PM PDT 24
Peak memory 200400 kb
Host smart-3fa095d4-1782-4102-8e5c-578106e79eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172213033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1172213033
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2437864717
Short name T1143
Test name
Test status
Simulation time 25492060291 ps
CPU time 13.8 seconds
Started May 23 12:47:57 PM PDT 24
Finished May 23 12:48:12 PM PDT 24
Peak memory 200180 kb
Host smart-12aa83ee-97e8-4e34-9053-77b0aa91e16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437864717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2437864717
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1527412880
Short name T561
Test name
Test status
Simulation time 11751224 ps
CPU time 0.54 seconds
Started May 23 12:45:09 PM PDT 24
Finished May 23 12:45:10 PM PDT 24
Peak memory 195728 kb
Host smart-34862552-74c4-4ad9-9c27-1a037841a562
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527412880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1527412880
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.74218030
Short name T723
Test name
Test status
Simulation time 21563696638 ps
CPU time 38.17 seconds
Started May 23 12:45:02 PM PDT 24
Finished May 23 12:45:41 PM PDT 24
Peak memory 200400 kb
Host smart-e8423c08-12a7-4fb5-bfc7-a197ce43cb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74218030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.74218030
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.4081234807
Short name T795
Test name
Test status
Simulation time 21039106628 ps
CPU time 40.02 seconds
Started May 23 12:45:04 PM PDT 24
Finished May 23 12:45:46 PM PDT 24
Peak memory 200180 kb
Host smart-b45b844b-9bb6-46ae-be45-39453be08a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081234807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.4081234807
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3132901571
Short name T252
Test name
Test status
Simulation time 124287259164 ps
CPU time 177.11 seconds
Started May 23 12:45:03 PM PDT 24
Finished May 23 12:48:02 PM PDT 24
Peak memory 200440 kb
Host smart-651b3d19-3b18-41b3-b450-1bdf65a54bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132901571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3132901571
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2393456089
Short name T1080
Test name
Test status
Simulation time 71516293477 ps
CPU time 36.14 seconds
Started May 23 12:45:03 PM PDT 24
Finished May 23 12:45:41 PM PDT 24
Peak memory 200204 kb
Host smart-e5c06f77-9446-4d70-86d7-b9995716fecb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393456089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2393456089
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.907526585
Short name T38
Test name
Test status
Simulation time 75635426529 ps
CPU time 428.56 seconds
Started May 23 12:45:08 PM PDT 24
Finished May 23 12:52:18 PM PDT 24
Peak memory 200292 kb
Host smart-35cc0a10-7e77-47da-92f4-f545cdf3563a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=907526585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.907526585
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2737233623
Short name T394
Test name
Test status
Simulation time 6523192479 ps
CPU time 10.89 seconds
Started May 23 12:45:08 PM PDT 24
Finished May 23 12:45:20 PM PDT 24
Peak memory 199248 kb
Host smart-ad1196ce-8af3-4f9f-acbc-47530998c1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737233623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2737233623
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1634174924
Short name T512
Test name
Test status
Simulation time 123691458783 ps
CPU time 51.14 seconds
Started May 23 12:45:05 PM PDT 24
Finished May 23 12:45:57 PM PDT 24
Peak memory 200676 kb
Host smart-90c69e4e-8bfe-48c4-a95b-11166a94db47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634174924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1634174924
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1435837802
Short name T922
Test name
Test status
Simulation time 11081836524 ps
CPU time 624.93 seconds
Started May 23 12:45:08 PM PDT 24
Finished May 23 12:55:34 PM PDT 24
Peak memory 200260 kb
Host smart-9010dc95-ab5b-42da-a2a0-46ae3c31e76c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435837802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1435837802
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.94070619
Short name T378
Test name
Test status
Simulation time 7261526438 ps
CPU time 31.25 seconds
Started May 23 12:45:02 PM PDT 24
Finished May 23 12:45:35 PM PDT 24
Peak memory 198760 kb
Host smart-b654ee08-ac04-4b32-b311-77035bb5078c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94070619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.94070619
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2174031879
Short name T70
Test name
Test status
Simulation time 9084363793 ps
CPU time 4.54 seconds
Started May 23 12:45:03 PM PDT 24
Finished May 23 12:45:09 PM PDT 24
Peak memory 200100 kb
Host smart-1480a472-e1eb-4df8-8562-25e6e6cb7a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174031879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2174031879
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1806698595
Short name T845
Test name
Test status
Simulation time 2414503591 ps
CPU time 3.67 seconds
Started May 23 12:44:59 PM PDT 24
Finished May 23 12:45:03 PM PDT 24
Peak memory 196088 kb
Host smart-a97fce5b-f481-4780-b826-316bbf6d42d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806698595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1806698595
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3197796149
Short name T712
Test name
Test status
Simulation time 284638179 ps
CPU time 2.23 seconds
Started May 23 12:45:02 PM PDT 24
Finished May 23 12:45:06 PM PDT 24
Peak memory 198608 kb
Host smart-aa0ce513-9b96-4569-b669-694d775f4c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197796149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3197796149
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3639454714
Short name T701
Test name
Test status
Simulation time 222284382093 ps
CPU time 123.26 seconds
Started May 23 12:45:03 PM PDT 24
Finished May 23 12:47:08 PM PDT 24
Peak memory 200420 kb
Host smart-120bc717-d513-42e3-b20b-b94961d71613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639454714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3639454714
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.4062076681
Short name T57
Test name
Test status
Simulation time 32812711604 ps
CPU time 347.38 seconds
Started May 23 12:45:08 PM PDT 24
Finished May 23 12:50:57 PM PDT 24
Peak memory 210060 kb
Host smart-84c32663-cc0e-42dc-a61f-08640f613eb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062076681 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.4062076681
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3826919064
Short name T859
Test name
Test status
Simulation time 6371077303 ps
CPU time 30.63 seconds
Started May 23 12:45:09 PM PDT 24
Finished May 23 12:45:40 PM PDT 24
Peak memory 200024 kb
Host smart-8d95032f-1ae0-44d3-b2de-6a265782b0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826919064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3826919064
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.179626679
Short name T1078
Test name
Test status
Simulation time 65196489584 ps
CPU time 22.61 seconds
Started May 23 12:45:01 PM PDT 24
Finished May 23 12:45:25 PM PDT 24
Peak memory 200404 kb
Host smart-c713ba14-8588-41fc-8a30-19478071c361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179626679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.179626679
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1810230082
Short name T278
Test name
Test status
Simulation time 11836638818 ps
CPU time 36.08 seconds
Started May 23 12:47:56 PM PDT 24
Finished May 23 12:48:33 PM PDT 24
Peak memory 200376 kb
Host smart-30d459c1-2946-4cea-b788-4d3e903b38e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810230082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1810230082
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.322183379
Short name T715
Test name
Test status
Simulation time 155812128981 ps
CPU time 84.23 seconds
Started May 23 12:47:59 PM PDT 24
Finished May 23 12:49:24 PM PDT 24
Peak memory 200444 kb
Host smart-8ac0aa1d-e63e-435a-a520-ddce4f56a7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322183379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.322183379
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3377358708
Short name T927
Test name
Test status
Simulation time 269358937079 ps
CPU time 45.44 seconds
Started May 23 12:48:00 PM PDT 24
Finished May 23 12:48:46 PM PDT 24
Peak memory 200396 kb
Host smart-8264c1c9-60fb-41d5-a237-2b0b7567ea76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377358708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3377358708
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3995386618
Short name T333
Test name
Test status
Simulation time 39599072823 ps
CPU time 16.12 seconds
Started May 23 12:47:58 PM PDT 24
Finished May 23 12:48:16 PM PDT 24
Peak memory 200492 kb
Host smart-4c4332f9-c216-4ef3-b719-5ac74eae2965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995386618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3995386618
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2130000653
Short name T248
Test name
Test status
Simulation time 140436040066 ps
CPU time 26.94 seconds
Started May 23 12:47:57 PM PDT 24
Finished May 23 12:48:25 PM PDT 24
Peak memory 200380 kb
Host smart-11e3e989-5b77-4a05-ad9f-2a754acc42a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130000653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2130000653
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2901206884
Short name T535
Test name
Test status
Simulation time 62724545087 ps
CPU time 27.47 seconds
Started May 23 12:47:58 PM PDT 24
Finished May 23 12:48:26 PM PDT 24
Peak memory 200476 kb
Host smart-8fdc9cf9-742c-45d6-ae83-ef7a1390897b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901206884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2901206884
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2223100565
Short name T373
Test name
Test status
Simulation time 92203620934 ps
CPU time 111.24 seconds
Started May 23 12:48:02 PM PDT 24
Finished May 23 12:49:54 PM PDT 24
Peak memory 200476 kb
Host smart-39a449fd-cb43-47e0-927e-5aaf0316394c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223100565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2223100565
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.169247069
Short name T208
Test name
Test status
Simulation time 130574499233 ps
CPU time 106.75 seconds
Started May 23 12:47:56 PM PDT 24
Finished May 23 12:49:44 PM PDT 24
Peak memory 200484 kb
Host smart-893f2426-af4c-49d6-af55-63eb74af3c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169247069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.169247069
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.25994627
Short name T142
Test name
Test status
Simulation time 90571747694 ps
CPU time 146.55 seconds
Started May 23 12:47:56 PM PDT 24
Finished May 23 12:50:24 PM PDT 24
Peak memory 200336 kb
Host smart-159c1ec9-4fe5-409c-979d-6e328e7580ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25994627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.25994627
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3232344527
Short name T519
Test name
Test status
Simulation time 13247250 ps
CPU time 0.57 seconds
Started May 23 12:45:16 PM PDT 24
Finished May 23 12:45:18 PM PDT 24
Peak memory 195288 kb
Host smart-287f93d4-aafb-482c-94de-25c1694e6625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232344527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3232344527
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.4220088832
Short name T1060
Test name
Test status
Simulation time 33575621688 ps
CPU time 56.97 seconds
Started May 23 12:45:04 PM PDT 24
Finished May 23 12:46:03 PM PDT 24
Peak memory 200396 kb
Host smart-2bf4f5d1-f924-4049-a287-853c05770899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220088832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.4220088832
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.4035854412
Short name T1018
Test name
Test status
Simulation time 205340631995 ps
CPU time 508 seconds
Started May 23 12:45:07 PM PDT 24
Finished May 23 12:53:36 PM PDT 24
Peak memory 200292 kb
Host smart-9e841d46-8137-4db1-8729-32e1857ba89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035854412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.4035854412
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_intr.2174400844
Short name T22
Test name
Test status
Simulation time 65441973858 ps
CPU time 35.47 seconds
Started May 23 12:45:03 PM PDT 24
Finished May 23 12:45:41 PM PDT 24
Peak memory 200172 kb
Host smart-ef90ade7-efd7-4851-bf27-f8e59a67ed01
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174400844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2174400844
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.658419950
Short name T639
Test name
Test status
Simulation time 43982588604 ps
CPU time 210.35 seconds
Started May 23 12:45:17 PM PDT 24
Finished May 23 12:48:49 PM PDT 24
Peak memory 200388 kb
Host smart-200cd167-048f-4576-8745-fe05968904f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=658419950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.658419950
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3964836976
Short name T1184
Test name
Test status
Simulation time 8363781346 ps
CPU time 8.75 seconds
Started May 23 12:45:15 PM PDT 24
Finished May 23 12:45:25 PM PDT 24
Peak memory 200296 kb
Host smart-93907fbe-e0e5-4557-905e-bc1567bb279a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964836976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3964836976
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.3841862661
Short name T423
Test name
Test status
Simulation time 8136924839 ps
CPU time 192.66 seconds
Started May 23 12:45:15 PM PDT 24
Finished May 23 12:48:29 PM PDT 24
Peak memory 200368 kb
Host smart-745c48c2-733c-4855-b2dc-d880aaf55b75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3841862661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3841862661
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.787645191
Short name T451
Test name
Test status
Simulation time 4592607493 ps
CPU time 37.39 seconds
Started May 23 12:45:04 PM PDT 24
Finished May 23 12:45:43 PM PDT 24
Peak memory 200296 kb
Host smart-5bf48334-3641-4c66-93f1-6ea66517e5de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787645191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.787645191
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2945141294
Short name T500
Test name
Test status
Simulation time 124912674211 ps
CPU time 222.62 seconds
Started May 23 12:45:03 PM PDT 24
Finished May 23 12:48:47 PM PDT 24
Peak memory 200376 kb
Host smart-0c310015-e011-4a8a-bdef-fd8aba1a8790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945141294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2945141294
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3100005944
Short name T854
Test name
Test status
Simulation time 648644895 ps
CPU time 1.7 seconds
Started May 23 12:45:08 PM PDT 24
Finished May 23 12:45:10 PM PDT 24
Peak memory 195968 kb
Host smart-d1ca114c-9247-4e6c-bc40-fc816346ed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100005944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3100005944
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1935597390
Short name T785
Test name
Test status
Simulation time 6012484023 ps
CPU time 9.91 seconds
Started May 23 12:45:04 PM PDT 24
Finished May 23 12:45:16 PM PDT 24
Peak memory 199388 kb
Host smart-468ce2ee-c42b-4c1e-9bc8-567be41cb72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935597390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1935597390
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2830671156
Short name T1126
Test name
Test status
Simulation time 84375953251 ps
CPU time 1701.96 seconds
Started May 23 12:45:15 PM PDT 24
Finished May 23 01:13:39 PM PDT 24
Peak memory 216900 kb
Host smart-d2728b42-8558-4c40-966d-573be54790f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830671156 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2830671156
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2415059414
Short name T455
Test name
Test status
Simulation time 786299312 ps
CPU time 1.81 seconds
Started May 23 12:45:16 PM PDT 24
Finished May 23 12:45:20 PM PDT 24
Peak memory 200116 kb
Host smart-bb2b01e5-28c0-4888-8fc9-1db5a0f274d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415059414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2415059414
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.838611345
Short name T869
Test name
Test status
Simulation time 29906607650 ps
CPU time 49.98 seconds
Started May 23 12:45:09 PM PDT 24
Finished May 23 12:46:00 PM PDT 24
Peak memory 200384 kb
Host smart-59500010-c16c-4289-a77c-fa7d17feb6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838611345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.838611345
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1105108364
Short name T1169
Test name
Test status
Simulation time 54388770002 ps
CPU time 90.79 seconds
Started May 23 12:47:58 PM PDT 24
Finished May 23 12:49:30 PM PDT 24
Peak memory 200248 kb
Host smart-2d666ec4-f0d0-4271-b0e1-bc9bdbfe08e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105108364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1105108364
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.984697973
Short name T692
Test name
Test status
Simulation time 26100037879 ps
CPU time 12.12 seconds
Started May 23 12:47:59 PM PDT 24
Finished May 23 12:48:12 PM PDT 24
Peak memory 200452 kb
Host smart-5c39cff4-cfa3-4b8e-ba80-12277e5b0933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984697973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.984697973
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.4159824001
Short name T199
Test name
Test status
Simulation time 225401785369 ps
CPU time 88.22 seconds
Started May 23 12:47:57 PM PDT 24
Finished May 23 12:49:26 PM PDT 24
Peak memory 200336 kb
Host smart-ac5e9537-d37d-4066-a387-c092a7671622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159824001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.4159824001
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1971135825
Short name T843
Test name
Test status
Simulation time 131852205881 ps
CPU time 207.58 seconds
Started May 23 12:47:57 PM PDT 24
Finished May 23 12:51:26 PM PDT 24
Peak memory 200396 kb
Host smart-566a9e7a-9ea7-42a1-b711-c3a32098f80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971135825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1971135825
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1040083682
Short name T841
Test name
Test status
Simulation time 38438927092 ps
CPU time 29.87 seconds
Started May 23 12:48:00 PM PDT 24
Finished May 23 12:48:31 PM PDT 24
Peak memory 200404 kb
Host smart-81765897-bdc7-47d9-8675-4c4d056b4eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040083682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1040083682
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.929189787
Short name T326
Test name
Test status
Simulation time 27005785085 ps
CPU time 50.38 seconds
Started May 23 12:47:55 PM PDT 24
Finished May 23 12:48:47 PM PDT 24
Peak memory 200440 kb
Host smart-d20a25e0-37d0-4e74-9c4a-14f2af7a8a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929189787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.929189787
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3004343514
Short name T1053
Test name
Test status
Simulation time 125201970647 ps
CPU time 124.75 seconds
Started May 23 12:47:58 PM PDT 24
Finished May 23 12:50:04 PM PDT 24
Peak memory 200356 kb
Host smart-5e2cac21-a2a8-4771-afc4-57cef375415f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004343514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3004343514
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2801044136
Short name T833
Test name
Test status
Simulation time 20209927166 ps
CPU time 35.34 seconds
Started May 23 12:48:02 PM PDT 24
Finished May 23 12:48:38 PM PDT 24
Peak memory 200388 kb
Host smart-ff3fc2f5-e9b2-4e2e-b621-9fd1a079b14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801044136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2801044136
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3261137303
Short name T47
Test name
Test status
Simulation time 208179188807 ps
CPU time 39.34 seconds
Started May 23 12:47:59 PM PDT 24
Finished May 23 12:48:39 PM PDT 24
Peak memory 200388 kb
Host smart-a14711b6-5e25-40f4-bbfe-726d711b2c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261137303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3261137303
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3225979833
Short name T993
Test name
Test status
Simulation time 43875053 ps
CPU time 0.54 seconds
Started May 23 12:45:15 PM PDT 24
Finished May 23 12:45:17 PM PDT 24
Peak memory 195768 kb
Host smart-43ca314c-c74c-4296-9bb6-fc292ffa0b67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225979833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3225979833
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2588017496
Short name T964
Test name
Test status
Simulation time 35457700793 ps
CPU time 14.56 seconds
Started May 23 12:45:19 PM PDT 24
Finished May 23 12:45:34 PM PDT 24
Peak memory 200336 kb
Host smart-0b3e68d2-abbd-442a-bf66-48d89891577c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588017496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2588017496
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.423998832
Short name T555
Test name
Test status
Simulation time 17369011082 ps
CPU time 14.78 seconds
Started May 23 12:45:16 PM PDT 24
Finished May 23 12:45:33 PM PDT 24
Peak memory 198752 kb
Host smart-f44afb28-7292-4a48-a565-4e7a832018c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423998832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.423998832
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.516679937
Short name T149
Test name
Test status
Simulation time 21856036058 ps
CPU time 41.53 seconds
Started May 23 12:45:14 PM PDT 24
Finished May 23 12:45:56 PM PDT 24
Peak memory 200444 kb
Host smart-1d99db31-70f4-4a71-a20a-b466900d4cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516679937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.516679937
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.285856468
Short name T678
Test name
Test status
Simulation time 50337958565 ps
CPU time 82.56 seconds
Started May 23 12:45:16 PM PDT 24
Finished May 23 12:46:40 PM PDT 24
Peak memory 200376 kb
Host smart-7843f6f0-b08b-4c8f-8232-be4a0c9aa882
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285856468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.285856468
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.138750558
Short name T994
Test name
Test status
Simulation time 119811033933 ps
CPU time 335.24 seconds
Started May 23 12:45:14 PM PDT 24
Finished May 23 12:50:50 PM PDT 24
Peak memory 200388 kb
Host smart-a68ac3f1-7d38-4218-8eca-044f02fe418a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=138750558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.138750558
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1896064906
Short name T107
Test name
Test status
Simulation time 1271486220 ps
CPU time 2.62 seconds
Started May 23 12:45:15 PM PDT 24
Finished May 23 12:45:19 PM PDT 24
Peak memory 198332 kb
Host smart-781316c2-c3f7-483f-abb7-4186428a3ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896064906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1896064906
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3903322598
Short name T899
Test name
Test status
Simulation time 38115669614 ps
CPU time 65.95 seconds
Started May 23 12:45:15 PM PDT 24
Finished May 23 12:46:22 PM PDT 24
Peak memory 200204 kb
Host smart-19ae3f92-55b4-4e15-88d8-6640baa236da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903322598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3903322598
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.4093736470
Short name T650
Test name
Test status
Simulation time 27227824516 ps
CPU time 1364.12 seconds
Started May 23 12:45:15 PM PDT 24
Finished May 23 01:08:01 PM PDT 24
Peak memory 200360 kb
Host smart-88d31175-3199-4bfc-9ab8-456cef26cc28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4093736470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.4093736470
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3200480697
Short name T359
Test name
Test status
Simulation time 6516458186 ps
CPU time 63.58 seconds
Started May 23 12:45:18 PM PDT 24
Finished May 23 12:46:23 PM PDT 24
Peak memory 198520 kb
Host smart-c284908a-6995-44dc-98e0-ff11bd85868f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3200480697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3200480697
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3816956356
Short name T1013
Test name
Test status
Simulation time 270971736315 ps
CPU time 47.73 seconds
Started May 23 12:45:16 PM PDT 24
Finished May 23 12:46:05 PM PDT 24
Peak memory 200268 kb
Host smart-77d39678-f079-4aa9-988c-c6cd7b7ef451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816956356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3816956356
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1274316014
Short name T569
Test name
Test status
Simulation time 6543464967 ps
CPU time 6.21 seconds
Started May 23 12:45:14 PM PDT 24
Finished May 23 12:45:22 PM PDT 24
Peak memory 196280 kb
Host smart-1a1f9e45-1ef5-49f2-a463-7f0aa1ca5668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274316014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1274316014
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1580781271
Short name T591
Test name
Test status
Simulation time 845619156 ps
CPU time 4.74 seconds
Started May 23 12:45:15 PM PDT 24
Finished May 23 12:45:21 PM PDT 24
Peak memory 199220 kb
Host smart-6302a25e-68d7-4602-bad2-429fc229ae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580781271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1580781271
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3224535123
Short name T589
Test name
Test status
Simulation time 65145105455 ps
CPU time 53.72 seconds
Started May 23 12:45:19 PM PDT 24
Finished May 23 12:46:13 PM PDT 24
Peak memory 200512 kb
Host smart-6329151f-65e8-437e-993b-e18e7e971e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224535123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3224535123
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.203726352
Short name T851
Test name
Test status
Simulation time 80794840810 ps
CPU time 165.99 seconds
Started May 23 12:45:15 PM PDT 24
Finished May 23 12:48:03 PM PDT 24
Peak memory 216880 kb
Host smart-5430a104-5165-4eb2-9e60-25a9d7f93d59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203726352 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.203726352
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3803986986
Short name T713
Test name
Test status
Simulation time 1132729892 ps
CPU time 3.75 seconds
Started May 23 12:45:13 PM PDT 24
Finished May 23 12:45:17 PM PDT 24
Peak memory 199300 kb
Host smart-46d4f4bb-e8df-41bc-aab1-7d7a9e431a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803986986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3803986986
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1314501773
Short name T521
Test name
Test status
Simulation time 23715094337 ps
CPU time 12.32 seconds
Started May 23 12:45:14 PM PDT 24
Finished May 23 12:45:28 PM PDT 24
Peak memory 200384 kb
Host smart-3878f80b-7c81-43f6-9ef9-8403f974a022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314501773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1314501773
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1344869364
Short name T203
Test name
Test status
Simulation time 32151806369 ps
CPU time 34.56 seconds
Started May 23 12:47:55 PM PDT 24
Finished May 23 12:48:30 PM PDT 24
Peak memory 200444 kb
Host smart-2a53c9df-57a0-4f86-a8b9-326c1d3ddbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344869364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1344869364
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3433675686
Short name T744
Test name
Test status
Simulation time 163946295989 ps
CPU time 72.76 seconds
Started May 23 12:47:58 PM PDT 24
Finished May 23 12:49:12 PM PDT 24
Peak memory 200316 kb
Host smart-5f817f06-fd44-4f21-8dfc-0e4baae79c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433675686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3433675686
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2797976988
Short name T970
Test name
Test status
Simulation time 64730872955 ps
CPU time 43.16 seconds
Started May 23 12:47:54 PM PDT 24
Finished May 23 12:48:38 PM PDT 24
Peak memory 200460 kb
Host smart-00e2f9ec-f50e-40d6-81f8-a260ea3afb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797976988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2797976988
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.826979089
Short name T454
Test name
Test status
Simulation time 136704249646 ps
CPU time 47.32 seconds
Started May 23 12:47:55 PM PDT 24
Finished May 23 12:48:43 PM PDT 24
Peak memory 200468 kb
Host smart-2d0e84ca-f9f3-43a0-82db-c61ac126ee8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826979089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.826979089
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.166641633
Short name T348
Test name
Test status
Simulation time 23214010994 ps
CPU time 40.76 seconds
Started May 23 12:47:57 PM PDT 24
Finished May 23 12:48:39 PM PDT 24
Peak memory 200416 kb
Host smart-a2f5d8d8-a460-4b0f-aac0-3cf90819215f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166641633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.166641633
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.213268505
Short name T240
Test name
Test status
Simulation time 122290826401 ps
CPU time 31.18 seconds
Started May 23 12:47:59 PM PDT 24
Finished May 23 12:48:31 PM PDT 24
Peak memory 200408 kb
Host smart-4674ff77-3af6-428e-8130-aba7c827f802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213268505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.213268505
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2867421322
Short name T837
Test name
Test status
Simulation time 223315335837 ps
CPU time 204.82 seconds
Started May 23 12:47:55 PM PDT 24
Finished May 23 12:51:21 PM PDT 24
Peak memory 200388 kb
Host smart-6542a357-fbac-42aa-be79-07e7e30b429b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867421322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2867421322
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.719337417
Short name T596
Test name
Test status
Simulation time 28317281957 ps
CPU time 116.81 seconds
Started May 23 12:47:56 PM PDT 24
Finished May 23 12:49:54 PM PDT 24
Peak memory 200420 kb
Host smart-6c7ed472-6153-444d-9a43-d718fffd1fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719337417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.719337417
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3000307423
Short name T380
Test name
Test status
Simulation time 24296065 ps
CPU time 0.54 seconds
Started May 23 12:45:15 PM PDT 24
Finished May 23 12:45:17 PM PDT 24
Peak memory 195692 kb
Host smart-a9a665e7-031b-4b96-8e1e-7e19a9da44b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000307423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3000307423
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2183923520
Short name T928
Test name
Test status
Simulation time 17948931525 ps
CPU time 27.44 seconds
Started May 23 12:45:21 PM PDT 24
Finished May 23 12:45:49 PM PDT 24
Peak memory 200308 kb
Host smart-8fecfdae-4c31-4a27-8229-804a254455d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183923520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2183923520
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2671026929
Short name T982
Test name
Test status
Simulation time 100030173780 ps
CPU time 160.65 seconds
Started May 23 12:45:14 PM PDT 24
Finished May 23 12:47:56 PM PDT 24
Peak memory 200376 kb
Host smart-32bc810b-064d-42c2-8f1a-29ea9cfe2694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671026929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2671026929
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1465252211
Short name T200
Test name
Test status
Simulation time 75207556380 ps
CPU time 64.43 seconds
Started May 23 12:45:21 PM PDT 24
Finished May 23 12:46:26 PM PDT 24
Peak memory 200412 kb
Host smart-47600c68-926a-4b6c-9182-7f54494406db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465252211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1465252211
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2071135186
Short name T965
Test name
Test status
Simulation time 193289943203 ps
CPU time 338.63 seconds
Started May 23 12:45:21 PM PDT 24
Finished May 23 12:51:01 PM PDT 24
Peak memory 200344 kb
Host smart-7b375373-acfa-45d1-a82e-1692aa8957a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071135186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2071135186
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2571042471
Short name T404
Test name
Test status
Simulation time 128512322399 ps
CPU time 446.44 seconds
Started May 23 12:45:18 PM PDT 24
Finished May 23 12:52:45 PM PDT 24
Peak memory 200416 kb
Host smart-8f046f73-90a7-491f-b88f-fe9e0e38c5fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2571042471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2571042471
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2722077782
Short name T686
Test name
Test status
Simulation time 3918176121 ps
CPU time 1.85 seconds
Started May 23 12:45:17 PM PDT 24
Finished May 23 12:45:21 PM PDT 24
Peak memory 198072 kb
Host smart-7a111fde-8ce2-45f5-834a-be21f5dacd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722077782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2722077782
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3393744324
Short name T858
Test name
Test status
Simulation time 38813463208 ps
CPU time 13.8 seconds
Started May 23 12:45:17 PM PDT 24
Finished May 23 12:45:32 PM PDT 24
Peak memory 196364 kb
Host smart-dadce855-65cb-4227-903d-c9d03a49930c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393744324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3393744324
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3938768884
Short name T880
Test name
Test status
Simulation time 6721153163 ps
CPU time 410.27 seconds
Started May 23 12:45:21 PM PDT 24
Finished May 23 12:52:12 PM PDT 24
Peak memory 200340 kb
Host smart-92c70bed-d5b5-46e6-8f0a-a2ceb8da594e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938768884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3938768884
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.276821573
Short name T462
Test name
Test status
Simulation time 6084911618 ps
CPU time 11.97 seconds
Started May 23 12:45:19 PM PDT 24
Finished May 23 12:45:32 PM PDT 24
Peak memory 198448 kb
Host smart-a905c87d-a5e9-4405-a29f-56522b93291f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=276821573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.276821573
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.966573538
Short name T629
Test name
Test status
Simulation time 131189157947 ps
CPU time 46.57 seconds
Started May 23 12:45:17 PM PDT 24
Finished May 23 12:46:05 PM PDT 24
Peak memory 200380 kb
Host smart-a396f6f9-1b98-4727-a24d-0269d6710aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966573538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.966573538
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1227609128
Short name T879
Test name
Test status
Simulation time 2479013893 ps
CPU time 4.46 seconds
Started May 23 12:45:15 PM PDT 24
Finished May 23 12:45:21 PM PDT 24
Peak memory 196324 kb
Host smart-c2a87a11-d02f-4574-8231-155dffb3b6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227609128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1227609128
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2218557122
Short name T368
Test name
Test status
Simulation time 714245613 ps
CPU time 1.39 seconds
Started May 23 12:45:13 PM PDT 24
Finished May 23 12:45:15 PM PDT 24
Peak memory 200048 kb
Host smart-2ab24db3-124c-483c-a06e-29f08d320f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218557122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2218557122
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2957469517
Short name T760
Test name
Test status
Simulation time 322402979567 ps
CPU time 541.21 seconds
Started May 23 12:45:18 PM PDT 24
Finished May 23 12:54:21 PM PDT 24
Peak memory 200360 kb
Host smart-7b97e297-5ab6-4b6d-9e3d-acff6eeece30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957469517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2957469517
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3200062518
Short name T770
Test name
Test status
Simulation time 10175298756 ps
CPU time 6.1 seconds
Started May 23 12:45:14 PM PDT 24
Finished May 23 12:45:22 PM PDT 24
Peak memory 199964 kb
Host smart-aa36a2d4-0196-440d-bb42-0df8976451b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200062518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3200062518
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3877931682
Short name T751
Test name
Test status
Simulation time 132159253785 ps
CPU time 150.01 seconds
Started May 23 12:45:20 PM PDT 24
Finished May 23 12:47:50 PM PDT 24
Peak memory 200428 kb
Host smart-d0b5fe69-268e-43ef-a28f-4c8260ccff64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877931682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3877931682
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1755552896
Short name T117
Test name
Test status
Simulation time 218351548448 ps
CPU time 35.7 seconds
Started May 23 12:48:15 PM PDT 24
Finished May 23 12:48:51 PM PDT 24
Peak memory 200348 kb
Host smart-d02b9f53-0c82-45c3-9bf5-453ed9f64ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755552896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1755552896
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1078886419
Short name T810
Test name
Test status
Simulation time 110835375035 ps
CPU time 95.93 seconds
Started May 23 12:48:15 PM PDT 24
Finished May 23 12:49:52 PM PDT 24
Peak memory 200296 kb
Host smart-eeec8df2-b2b0-4e68-9ab1-cb3d07cea3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078886419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1078886419
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3527648708
Short name T1148
Test name
Test status
Simulation time 10518558359 ps
CPU time 18.22 seconds
Started May 23 12:48:11 PM PDT 24
Finished May 23 12:48:31 PM PDT 24
Peak memory 200364 kb
Host smart-7f1ad7a8-2461-4e45-9f26-b7c511dfcc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527648708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3527648708
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1234905710
Short name T576
Test name
Test status
Simulation time 53830801704 ps
CPU time 160.63 seconds
Started May 23 12:48:15 PM PDT 24
Finished May 23 12:50:57 PM PDT 24
Peak memory 200488 kb
Host smart-ba011961-6dbe-4cf0-a3fb-33d5b3b90667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234905710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1234905710
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.4137354348
Short name T217
Test name
Test status
Simulation time 95707329730 ps
CPU time 26.92 seconds
Started May 23 12:48:14 PM PDT 24
Finished May 23 12:48:42 PM PDT 24
Peak memory 200380 kb
Host smart-4d1207f7-dfd7-4758-a928-5701c1b12254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137354348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.4137354348
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2580023718
Short name T270
Test name
Test status
Simulation time 29109910999 ps
CPU time 41.32 seconds
Started May 23 12:48:13 PM PDT 24
Finished May 23 12:48:56 PM PDT 24
Peak memory 200252 kb
Host smart-0d3e0873-c533-47a2-8f5c-4d19429d7701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580023718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2580023718
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1661824642
Short name T991
Test name
Test status
Simulation time 66312647716 ps
CPU time 41.42 seconds
Started May 23 12:48:11 PM PDT 24
Finished May 23 12:48:53 PM PDT 24
Peak memory 200352 kb
Host smart-d274aa28-bfc7-4b01-84e3-0a165e63b92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661824642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1661824642
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1065052689
Short name T929
Test name
Test status
Simulation time 146639324984 ps
CPU time 223.79 seconds
Started May 23 12:48:10 PM PDT 24
Finished May 23 12:51:55 PM PDT 24
Peak memory 200464 kb
Host smart-b97a463b-98a4-49b6-9815-10113578632f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065052689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1065052689
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1231098856
Short name T212
Test name
Test status
Simulation time 12415058955 ps
CPU time 7.69 seconds
Started May 23 12:48:10 PM PDT 24
Finished May 23 12:48:19 PM PDT 24
Peak memory 200420 kb
Host smart-9af3cd87-6f54-48cc-ae82-4983e056fb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231098856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1231098856
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.236704516
Short name T1152
Test name
Test status
Simulation time 81850852432 ps
CPU time 34.42 seconds
Started May 23 12:48:12 PM PDT 24
Finished May 23 12:48:48 PM PDT 24
Peak memory 200428 kb
Host smart-62e80c75-6628-4d3f-bb30-901e230f0d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236704516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.236704516
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2350113781
Short name T376
Test name
Test status
Simulation time 23296342 ps
CPU time 0.59 seconds
Started May 23 12:43:53 PM PDT 24
Finished May 23 12:43:55 PM PDT 24
Peak memory 194684 kb
Host smart-875cb9f2-3e97-4516-b1b9-d11ee88f6aa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350113781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2350113781
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.727851713
Short name T398
Test name
Test status
Simulation time 163207124713 ps
CPU time 135.75 seconds
Started May 23 12:43:59 PM PDT 24
Finished May 23 12:46:17 PM PDT 24
Peak memory 200416 kb
Host smart-91991062-6487-4cb4-9099-01423bd039c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727851713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.727851713
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3522118467
Short name T474
Test name
Test status
Simulation time 27286128339 ps
CPU time 12.82 seconds
Started May 23 12:43:57 PM PDT 24
Finished May 23 12:44:11 PM PDT 24
Peak memory 200116 kb
Host smart-4e122163-1cc1-448b-b8a6-5dcab44f1724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522118467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3522118467
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1637416430
Short name T229
Test name
Test status
Simulation time 99635395239 ps
CPU time 41.39 seconds
Started May 23 12:43:56 PM PDT 24
Finished May 23 12:44:39 PM PDT 24
Peak memory 200240 kb
Host smart-b1b27bc3-e44f-40fc-a085-ce7111cf9754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637416430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1637416430
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2616724148
Short name T861
Test name
Test status
Simulation time 28269333380 ps
CPU time 8.11 seconds
Started May 23 12:43:59 PM PDT 24
Finished May 23 12:44:09 PM PDT 24
Peak memory 197324 kb
Host smart-2c7bc5bc-4e60-4808-8677-f38cf327dcc5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616724148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2616724148
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.773936933
Short name T476
Test name
Test status
Simulation time 101553079005 ps
CPU time 543.5 seconds
Started May 23 12:44:04 PM PDT 24
Finished May 23 12:53:08 PM PDT 24
Peak memory 200284 kb
Host smart-f6dc9ffe-fdef-4399-bfaf-3bd052be6472
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=773936933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.773936933
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.960950842
Short name T779
Test name
Test status
Simulation time 3285324259 ps
CPU time 2.74 seconds
Started May 23 12:44:03 PM PDT 24
Finished May 23 12:44:06 PM PDT 24
Peak memory 199108 kb
Host smart-640b5fd5-b14a-4ba2-9f38-ac90b9197514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960950842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.960950842
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3591319607
Short name T1118
Test name
Test status
Simulation time 48373084748 ps
CPU time 45.03 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 12:44:45 PM PDT 24
Peak memory 199928 kb
Host smart-3f8ab9e6-2e07-4979-af56-9134b205cf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591319607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3591319607
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2248426094
Short name T313
Test name
Test status
Simulation time 19197110441 ps
CPU time 1037.17 seconds
Started May 23 12:43:56 PM PDT 24
Finished May 23 01:01:15 PM PDT 24
Peak memory 200196 kb
Host smart-0fab640d-3da0-429a-a85f-ffdb750ffbd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2248426094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2248426094
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.209544504
Short name T371
Test name
Test status
Simulation time 3682053525 ps
CPU time 28 seconds
Started May 23 12:43:57 PM PDT 24
Finished May 23 12:44:27 PM PDT 24
Peak memory 198276 kb
Host smart-83656ff0-6cce-4334-a133-fc7f1bad6cca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209544504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.209544504
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2466156230
Short name T1133
Test name
Test status
Simulation time 136082582695 ps
CPU time 59.2 seconds
Started May 23 12:43:59 PM PDT 24
Finished May 23 12:45:00 PM PDT 24
Peak memory 200456 kb
Host smart-e8913628-d40b-4765-b20f-7dc0a9b03794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466156230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2466156230
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1334403754
Short name T881
Test name
Test status
Simulation time 4610956195 ps
CPU time 2.03 seconds
Started May 23 12:43:56 PM PDT 24
Finished May 23 12:43:59 PM PDT 24
Peak memory 196368 kb
Host smart-bda53702-5473-4bfd-820d-bc772a9d89ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334403754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1334403754
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1242814091
Short name T29
Test name
Test status
Simulation time 73515524 ps
CPU time 0.78 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 12:44:01 PM PDT 24
Peak memory 218584 kb
Host smart-226a0a3e-4e6c-4ecc-9c9a-b2affc939dbc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242814091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1242814091
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3555997449
Short name T560
Test name
Test status
Simulation time 705241443 ps
CPU time 1.26 seconds
Started May 23 12:43:56 PM PDT 24
Finished May 23 12:43:59 PM PDT 24
Peak memory 198904 kb
Host smart-546a9722-6183-4dbc-8f93-50e4d8e0ca52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555997449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3555997449
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3029989401
Short name T988
Test name
Test status
Simulation time 84902335090 ps
CPU time 278.45 seconds
Started May 23 12:43:59 PM PDT 24
Finished May 23 12:48:39 PM PDT 24
Peak memory 217096 kb
Host smart-a6d5334d-a8e7-498f-bac6-4a2e3b802213
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029989401 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3029989401
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1221622032
Short name T362
Test name
Test status
Simulation time 1108744633 ps
CPU time 1.43 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 12:44:01 PM PDT 24
Peak memory 198780 kb
Host smart-f583f4be-c8b3-4cf9-9f2f-ad9aa572f5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221622032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1221622032
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.783871401
Short name T981
Test name
Test status
Simulation time 23903939124 ps
CPU time 20.5 seconds
Started May 23 12:44:06 PM PDT 24
Finished May 23 12:44:27 PM PDT 24
Peak memory 200380 kb
Host smart-5b2fb3c2-fc8f-4351-a6ab-f55cfb8a393b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783871401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.783871401
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.552652184
Short name T857
Test name
Test status
Simulation time 20526439 ps
CPU time 0.55 seconds
Started May 23 12:45:27 PM PDT 24
Finished May 23 12:45:28 PM PDT 24
Peak memory 195744 kb
Host smart-ae455dc1-0407-4382-8820-05da890f0ef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552652184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.552652184
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.371656379
Short name T421
Test name
Test status
Simulation time 35945470974 ps
CPU time 16.14 seconds
Started May 23 12:45:21 PM PDT 24
Finished May 23 12:45:38 PM PDT 24
Peak memory 199920 kb
Host smart-84eeb814-75df-4f58-b089-9c3938211f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371656379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.371656379
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.458621342
Short name T527
Test name
Test status
Simulation time 10818152492 ps
CPU time 17.21 seconds
Started May 23 12:45:16 PM PDT 24
Finished May 23 12:45:34 PM PDT 24
Peak memory 199976 kb
Host smart-d8640aa2-20a4-459d-80ae-3a42ba5f6917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458621342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.458621342
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2580239177
Short name T655
Test name
Test status
Simulation time 10529731024 ps
CPU time 19.49 seconds
Started May 23 12:45:17 PM PDT 24
Finished May 23 12:45:38 PM PDT 24
Peak memory 200332 kb
Host smart-ab660bdd-4840-49e2-9ba1-b965c56c3f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580239177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2580239177
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3987869836
Short name T316
Test name
Test status
Simulation time 174013367384 ps
CPU time 280.11 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:50:11 PM PDT 24
Peak memory 200328 kb
Host smart-36b023ea-c7f2-4bbd-9fb8-5c5aede2c0c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987869836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3987869836
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.4035118937
Short name T530
Test name
Test status
Simulation time 109424930638 ps
CPU time 760.82 seconds
Started May 23 12:45:27 PM PDT 24
Finished May 23 12:58:09 PM PDT 24
Peak memory 200352 kb
Host smart-d4356524-166e-4769-9fb2-c2424a3c4888
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4035118937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.4035118937
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1536323686
Short name T1109
Test name
Test status
Simulation time 6032287534 ps
CPU time 10.38 seconds
Started May 23 12:45:27 PM PDT 24
Finished May 23 12:45:38 PM PDT 24
Peak memory 199416 kb
Host smart-a644e1b7-9c3e-4814-bb28-a15caba72ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536323686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1536323686
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1425218555
Short name T731
Test name
Test status
Simulation time 70534746267 ps
CPU time 29.35 seconds
Started May 23 12:45:28 PM PDT 24
Finished May 23 12:45:58 PM PDT 24
Peak memory 198484 kb
Host smart-2cb283d7-01cb-469e-b94f-638e0ffdb30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425218555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1425218555
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1299487249
Short name T1032
Test name
Test status
Simulation time 8756100020 ps
CPU time 501.95 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:53:53 PM PDT 24
Peak memory 200372 kb
Host smart-d8ad294c-da6d-492e-ad34-428163038db0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299487249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1299487249
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1046081708
Short name T796
Test name
Test status
Simulation time 3353944068 ps
CPU time 12.04 seconds
Started May 23 12:45:17 PM PDT 24
Finished May 23 12:45:31 PM PDT 24
Peak memory 198816 kb
Host smart-e5f7e89e-5885-4d12-b16f-864572c8754e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046081708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1046081708
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1522091218
Short name T666
Test name
Test status
Simulation time 165258672697 ps
CPU time 258.53 seconds
Started May 23 12:45:28 PM PDT 24
Finished May 23 12:49:48 PM PDT 24
Peak memory 200428 kb
Host smart-1bf736dc-4e41-4736-adf1-552a3f0d02d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522091218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1522091218
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3770878884
Short name T1064
Test name
Test status
Simulation time 1925026467 ps
CPU time 3.99 seconds
Started May 23 12:45:28 PM PDT 24
Finished May 23 12:45:33 PM PDT 24
Peak memory 195744 kb
Host smart-f5c04659-e4f3-41f0-9309-6102209a2046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770878884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3770878884
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3714550675
Short name T695
Test name
Test status
Simulation time 5347501549 ps
CPU time 12 seconds
Started May 23 12:45:16 PM PDT 24
Finished May 23 12:45:29 PM PDT 24
Peak memory 200240 kb
Host smart-cba59215-9878-48ba-bdf0-abfdd0a455e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714550675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3714550675
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3072513720
Short name T730
Test name
Test status
Simulation time 180758935230 ps
CPU time 681.71 seconds
Started May 23 12:45:28 PM PDT 24
Finished May 23 12:56:51 PM PDT 24
Peak memory 200348 kb
Host smart-6cb90fcf-9783-400e-baa5-5e2c25b71af8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072513720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3072513720
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.4018638995
Short name T112
Test name
Test status
Simulation time 143589372490 ps
CPU time 865.64 seconds
Started May 23 12:45:27 PM PDT 24
Finished May 23 12:59:54 PM PDT 24
Peak memory 217100 kb
Host smart-367cde5b-700f-4130-99ab-f7f8b0499adb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018638995 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.4018638995
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1081100346
Short name T329
Test name
Test status
Simulation time 6866067119 ps
CPU time 42.22 seconds
Started May 23 12:45:31 PM PDT 24
Finished May 23 12:46:15 PM PDT 24
Peak memory 200324 kb
Host smart-3f45791c-9114-4f9d-aeec-176b963a1818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081100346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1081100346
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1575526827
Short name T865
Test name
Test status
Simulation time 107857350261 ps
CPU time 10.83 seconds
Started May 23 12:45:17 PM PDT 24
Finished May 23 12:45:30 PM PDT 24
Peak memory 200332 kb
Host smart-132bec0f-43df-4987-817f-7198142e7463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575526827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1575526827
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3212656366
Short name T1098
Test name
Test status
Simulation time 12832833 ps
CPU time 0.55 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:45:31 PM PDT 24
Peak memory 195844 kb
Host smart-65808a6f-3cd7-47aa-b75d-8d45b9438689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212656366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3212656366
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2900121042
Short name T733
Test name
Test status
Simulation time 131462408056 ps
CPU time 275.49 seconds
Started May 23 12:45:32 PM PDT 24
Finished May 23 12:50:09 PM PDT 24
Peak memory 200444 kb
Host smart-c0149b02-aa2c-474e-a51d-973404f0349f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900121042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2900121042
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3377838159
Short name T299
Test name
Test status
Simulation time 203118252824 ps
CPU time 502.11 seconds
Started May 23 12:45:30 PM PDT 24
Finished May 23 12:53:54 PM PDT 24
Peak memory 200300 kb
Host smart-e19e183e-8fdb-42d0-b47c-8994af161355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377838159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3377838159
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_intr.1912674711
Short name T526
Test name
Test status
Simulation time 39456018441 ps
CPU time 11.98 seconds
Started May 23 12:45:30 PM PDT 24
Finished May 23 12:45:44 PM PDT 24
Peak memory 200024 kb
Host smart-9e52fbe4-bf87-403b-8a21-469ba2038319
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912674711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1912674711
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2727371758
Short name T945
Test name
Test status
Simulation time 262505823614 ps
CPU time 395.19 seconds
Started May 23 12:45:31 PM PDT 24
Finished May 23 12:52:08 PM PDT 24
Peak memory 200412 kb
Host smart-1d6b0c2a-e74d-484f-a382-867a3d8cbd41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727371758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2727371758
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1728596344
Short name T1160
Test name
Test status
Simulation time 12275076960 ps
CPU time 21.25 seconds
Started May 23 12:45:28 PM PDT 24
Finished May 23 12:45:51 PM PDT 24
Peak memory 198776 kb
Host smart-3298467b-c5ce-4353-9d61-3f60609e2c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728596344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1728596344
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.613636603
Short name T438
Test name
Test status
Simulation time 31850980475 ps
CPU time 27.37 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:45:57 PM PDT 24
Peak memory 200564 kb
Host smart-e3ce89f3-13b1-4f28-9170-67bb2ba4e5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613636603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.613636603
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2496382806
Short name T977
Test name
Test status
Simulation time 12867566696 ps
CPU time 146.45 seconds
Started May 23 12:45:28 PM PDT 24
Finished May 23 12:47:56 PM PDT 24
Peak memory 200348 kb
Host smart-da836ed6-6133-4eca-a5f1-2f25e32cd9d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496382806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2496382806
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1004911373
Short name T43
Test name
Test status
Simulation time 5879764660 ps
CPU time 14.24 seconds
Started May 23 12:45:31 PM PDT 24
Finished May 23 12:45:47 PM PDT 24
Peak memory 200408 kb
Host smart-2c062d51-f30f-43d5-8ed0-a4f3f4a5c132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004911373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1004911373
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3147407784
Short name T647
Test name
Test status
Simulation time 56958873724 ps
CPU time 31.96 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:46:02 PM PDT 24
Peak memory 200276 kb
Host smart-cf7279cf-7858-4777-b7d3-6f37e3bb7898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147407784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3147407784
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2381296341
Short name T492
Test name
Test status
Simulation time 50978590892 ps
CPU time 32.38 seconds
Started May 23 12:45:30 PM PDT 24
Finished May 23 12:46:04 PM PDT 24
Peak memory 196460 kb
Host smart-259def5d-a6aa-402b-818f-6850e39dae02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381296341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2381296341
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3874072365
Short name T709
Test name
Test status
Simulation time 270549465 ps
CPU time 1.04 seconds
Started May 23 12:45:27 PM PDT 24
Finished May 23 12:45:29 PM PDT 24
Peak memory 198656 kb
Host smart-663b282d-61c2-4b52-bf47-a01121a6a562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874072365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3874072365
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1387002146
Short name T315
Test name
Test status
Simulation time 80638803991 ps
CPU time 130.93 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:47:42 PM PDT 24
Peak memory 200524 kb
Host smart-ed7fab8f-18cc-4112-86d6-17c8710a40c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387002146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1387002146
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1476660585
Short name T747
Test name
Test status
Simulation time 196769597092 ps
CPU time 548.37 seconds
Started May 23 12:45:30 PM PDT 24
Finished May 23 12:54:40 PM PDT 24
Peak memory 217160 kb
Host smart-676030f2-a032-496a-b87f-82e910efaeca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476660585 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1476660585
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.316563673
Short name T1051
Test name
Test status
Simulation time 480674499 ps
CPU time 1.61 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:45:33 PM PDT 24
Peak memory 198796 kb
Host smart-d4a36e1d-0b83-4195-aae0-e3098786ef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316563673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.316563673
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.960427509
Short name T1180
Test name
Test status
Simulation time 86282241749 ps
CPU time 126.74 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:47:38 PM PDT 24
Peak memory 200284 kb
Host smart-1aeb17f6-bc00-47d9-af69-3edd69a29906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960427509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.960427509
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1053364808
Short name T579
Test name
Test status
Simulation time 69274421 ps
CPU time 0.54 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:45:31 PM PDT 24
Peak memory 194704 kb
Host smart-23a26bbc-25eb-4b21-903a-535d73b25668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053364808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1053364808
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1120570387
Short name T635
Test name
Test status
Simulation time 17960468812 ps
CPU time 7.42 seconds
Started May 23 12:45:30 PM PDT 24
Finished May 23 12:45:39 PM PDT 24
Peak memory 199020 kb
Host smart-96d48662-e540-410e-ac3d-b50da3b36a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120570387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1120570387
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1992922083
Short name T814
Test name
Test status
Simulation time 53737794342 ps
CPU time 24.18 seconds
Started May 23 12:45:30 PM PDT 24
Finished May 23 12:45:56 PM PDT 24
Peak memory 200444 kb
Host smart-b93bd957-8656-4053-bdae-a24edbc0fc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992922083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1992922083
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1746603455
Short name T126
Test name
Test status
Simulation time 207453920975 ps
CPU time 293.83 seconds
Started May 23 12:45:30 PM PDT 24
Finished May 23 12:50:25 PM PDT 24
Peak memory 200376 kb
Host smart-b6e5029a-1b95-4516-8ee7-b275d5b154ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746603455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1746603455
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.452675163
Short name T641
Test name
Test status
Simulation time 40969461903 ps
CPU time 12.82 seconds
Started May 23 12:45:31 PM PDT 24
Finished May 23 12:45:46 PM PDT 24
Peak memory 200168 kb
Host smart-66c207bb-5c40-42f3-9f36-8d361dc8900b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452675163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.452675163
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2475688012
Short name T702
Test name
Test status
Simulation time 112764653498 ps
CPU time 220.81 seconds
Started May 23 12:45:30 PM PDT 24
Finished May 23 12:49:13 PM PDT 24
Peak memory 200408 kb
Host smart-7f8c29bb-384d-4e15-a6d6-b6652c99c9ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2475688012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2475688012
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2485599971
Short name T360
Test name
Test status
Simulation time 8101588744 ps
CPU time 19.87 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:45:51 PM PDT 24
Peak memory 199748 kb
Host smart-b0543577-5f43-4337-a47f-300d8b6201f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485599971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2485599971
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1915253706
Short name T374
Test name
Test status
Simulation time 73148579408 ps
CPU time 35.23 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:46:06 PM PDT 24
Peak memory 200836 kb
Host smart-086af937-f515-4599-8300-0bac8d53c7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915253706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1915253706
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.425055716
Short name T799
Test name
Test status
Simulation time 10431704795 ps
CPU time 297.91 seconds
Started May 23 12:45:33 PM PDT 24
Finished May 23 12:50:32 PM PDT 24
Peak memory 200404 kb
Host smart-c92a0d79-fe7e-41ea-b44f-98862ebc1434
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=425055716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.425055716
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1914975389
Short name T1012
Test name
Test status
Simulation time 4753403171 ps
CPU time 10.61 seconds
Started May 23 12:45:30 PM PDT 24
Finished May 23 12:45:42 PM PDT 24
Peak memory 198364 kb
Host smart-d48d5296-bc24-421e-b0bb-9cfd7ebd7ffd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1914975389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1914975389
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.4052122265
Short name T269
Test name
Test status
Simulation time 110450241525 ps
CPU time 205.39 seconds
Started May 23 12:45:31 PM PDT 24
Finished May 23 12:48:58 PM PDT 24
Peak memory 200336 kb
Host smart-734ef711-9307-469c-b941-4e56ce2fa890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052122265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.4052122265
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.732981619
Short name T264
Test name
Test status
Simulation time 2728274775 ps
CPU time 5.32 seconds
Started May 23 12:45:31 PM PDT 24
Finished May 23 12:45:38 PM PDT 24
Peak memory 196124 kb
Host smart-53e194f6-f1c1-4d1b-bd4d-e35cfd58b075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732981619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.732981619
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.216725261
Short name T742
Test name
Test status
Simulation time 263135128 ps
CPU time 1.47 seconds
Started May 23 12:45:31 PM PDT 24
Finished May 23 12:45:34 PM PDT 24
Peak memory 198996 kb
Host smart-bd60797a-fd77-4b14-84a7-057ed026fa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216725261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.216725261
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.324820413
Short name T907
Test name
Test status
Simulation time 273269653170 ps
CPU time 112.55 seconds
Started May 23 12:45:33 PM PDT 24
Finished May 23 12:47:27 PM PDT 24
Peak memory 200352 kb
Host smart-7abe98a7-d4f1-462d-9499-b39320e3c134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324820413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.324820413
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3029224798
Short name T113
Test name
Test status
Simulation time 51125685130 ps
CPU time 217.66 seconds
Started May 23 12:45:32 PM PDT 24
Finished May 23 12:49:11 PM PDT 24
Peak memory 216080 kb
Host smart-07d610bf-bb3b-44e9-adbe-09ffa5537a45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029224798 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3029224798
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3964807258
Short name T836
Test name
Test status
Simulation time 7430812907 ps
CPU time 10.27 seconds
Started May 23 12:45:31 PM PDT 24
Finished May 23 12:45:43 PM PDT 24
Peak memory 200304 kb
Host smart-2a7382d5-eee4-42f4-870a-abf1cb379f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964807258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3964807258
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1420073426
Short name T727
Test name
Test status
Simulation time 20421791609 ps
CPU time 25.02 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:45:56 PM PDT 24
Peak memory 200548 kb
Host smart-6c372a24-8eb3-46a7-8e4f-79537bacd03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420073426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1420073426
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1791750584
Short name T697
Test name
Test status
Simulation time 31307442 ps
CPU time 0.63 seconds
Started May 23 12:45:30 PM PDT 24
Finished May 23 12:45:33 PM PDT 24
Peak memory 195820 kb
Host smart-c19b4abc-bb66-40d8-aa57-64820f3d622e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791750584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1791750584
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.633776081
Short name T883
Test name
Test status
Simulation time 71334341064 ps
CPU time 29.55 seconds
Started May 23 12:45:32 PM PDT 24
Finished May 23 12:46:03 PM PDT 24
Peak memory 200384 kb
Host smart-4d239547-7963-4dcd-b28b-28eb86b01f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633776081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.633776081
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.4076419278
Short name T764
Test name
Test status
Simulation time 35243986936 ps
CPU time 53.78 seconds
Started May 23 12:45:33 PM PDT 24
Finished May 23 12:46:28 PM PDT 24
Peak memory 200368 kb
Host smart-0b1260a6-427b-4b79-b1cd-8b6d01852d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076419278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4076419278
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3804583385
Short name T128
Test name
Test status
Simulation time 141085393267 ps
CPU time 20.55 seconds
Started May 23 12:45:32 PM PDT 24
Finished May 23 12:45:54 PM PDT 24
Peak memory 200220 kb
Host smart-d7d69ba4-c54c-4234-a942-14ba14a33142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804583385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3804583385
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2301856095
Short name T1055
Test name
Test status
Simulation time 45207008286 ps
CPU time 20.21 seconds
Started May 23 12:45:33 PM PDT 24
Finished May 23 12:45:54 PM PDT 24
Peak memory 200352 kb
Host smart-766154eb-98ff-481b-856b-fbea1012e426
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301856095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2301856095
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2632782253
Short name T261
Test name
Test status
Simulation time 56414758787 ps
CPU time 225.7 seconds
Started May 23 12:45:28 PM PDT 24
Finished May 23 12:49:15 PM PDT 24
Peak memory 200436 kb
Host smart-4c5c6cf8-a43f-4b73-8380-15be9d01a5dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2632782253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2632782253
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1003357023
Short name T352
Test name
Test status
Simulation time 6629548639 ps
CPU time 7.46 seconds
Started May 23 12:45:31 PM PDT 24
Finished May 23 12:45:41 PM PDT 24
Peak memory 199112 kb
Host smart-b8819b45-97cf-4c86-9cd3-87871f4cfc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003357023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1003357023
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2472275914
Short name T886
Test name
Test status
Simulation time 135787873261 ps
CPU time 89.78 seconds
Started May 23 12:45:37 PM PDT 24
Finished May 23 12:47:07 PM PDT 24
Peak memory 200724 kb
Host smart-e6e42a66-1704-4bca-8602-b64a09c3331b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472275914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2472275914
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2377435077
Short name T1145
Test name
Test status
Simulation time 10750550629 ps
CPU time 564.26 seconds
Started May 23 12:45:37 PM PDT 24
Finished May 23 12:55:02 PM PDT 24
Peak memory 200404 kb
Host smart-a10b928f-484b-4ee1-acfc-9eae0c4d707a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2377435077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2377435077
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2961576880
Short name T797
Test name
Test status
Simulation time 5452498968 ps
CPU time 21.75 seconds
Started May 23 12:45:37 PM PDT 24
Finished May 23 12:45:59 PM PDT 24
Peak memory 199736 kb
Host smart-03944aa6-1a1f-4526-90a2-112ebbfb3970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2961576880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2961576880
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2723981528
Short name T651
Test name
Test status
Simulation time 123163024404 ps
CPU time 92.37 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:47:04 PM PDT 24
Peak memory 200348 kb
Host smart-d80941bb-16cb-4cb5-a16a-ec4263ecbb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723981528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2723981528
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.4280015955
Short name T952
Test name
Test status
Simulation time 30896285410 ps
CPU time 10.74 seconds
Started May 23 12:45:31 PM PDT 24
Finished May 23 12:45:44 PM PDT 24
Peak memory 196464 kb
Host smart-750a40e3-d174-4b02-a89b-f50ef1cdea5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280015955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.4280015955
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3081972358
Short name T657
Test name
Test status
Simulation time 257037048 ps
CPU time 1.2 seconds
Started May 23 12:45:32 PM PDT 24
Finished May 23 12:45:35 PM PDT 24
Peak memory 199044 kb
Host smart-68c3d9f0-0642-4a60-a125-651a8c70d37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081972358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3081972358
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.1595194097
Short name T705
Test name
Test status
Simulation time 215413103135 ps
CPU time 1612.04 seconds
Started May 23 12:45:28 PM PDT 24
Finished May 23 01:12:22 PM PDT 24
Peak memory 216492 kb
Host smart-7b8c625d-9077-4a23-ac50-a3faf7b534fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595194097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1595194097
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1819061340
Short name T221
Test name
Test status
Simulation time 519360373873 ps
CPU time 826.46 seconds
Started May 23 12:45:31 PM PDT 24
Finished May 23 12:59:19 PM PDT 24
Peak memory 225284 kb
Host smart-e0412a64-96b3-4a92-85f3-dd96c5d0b37e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819061340 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1819061340
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.4239408869
Short name T1070
Test name
Test status
Simulation time 504374516 ps
CPU time 1.86 seconds
Started May 23 12:45:37 PM PDT 24
Finished May 23 12:45:40 PM PDT 24
Peak memory 199048 kb
Host smart-88e5888c-d6ca-44af-a934-395250558f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239408869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.4239408869
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.380711579
Short name T846
Test name
Test status
Simulation time 36858204446 ps
CPU time 17.71 seconds
Started May 23 12:45:32 PM PDT 24
Finished May 23 12:45:51 PM PDT 24
Peak memory 200276 kb
Host smart-606c4d82-17d8-4ed9-979c-383e3dc599d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380711579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.380711579
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.786186618
Short name T1045
Test name
Test status
Simulation time 54903774 ps
CPU time 0.56 seconds
Started May 23 12:45:42 PM PDT 24
Finished May 23 12:45:44 PM PDT 24
Peak memory 195780 kb
Host smart-52849787-8814-4f11-8069-561b8cf1b50c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786186618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.786186618
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3169925645
Short name T517
Test name
Test status
Simulation time 96287642471 ps
CPU time 156.72 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:48:07 PM PDT 24
Peak memory 200464 kb
Host smart-d73be77e-3c66-4afc-bc56-cfe8c9cceb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169925645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3169925645
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2368744627
Short name T164
Test name
Test status
Simulation time 15470031906 ps
CPU time 22.63 seconds
Started May 23 12:45:40 PM PDT 24
Finished May 23 12:46:04 PM PDT 24
Peak memory 200392 kb
Host smart-8aa2cd15-3a89-462c-a883-ac13f7afa1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368744627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2368744627
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.483060071
Short name T979
Test name
Test status
Simulation time 23234055526 ps
CPU time 81.26 seconds
Started May 23 12:45:40 PM PDT 24
Finished May 23 12:47:02 PM PDT 24
Peak memory 200404 kb
Host smart-fdb70b8a-3578-4186-9eef-99ebade23d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483060071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.483060071
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.133169002
Short name T1157
Test name
Test status
Simulation time 21180144264 ps
CPU time 18.27 seconds
Started May 23 12:45:43 PM PDT 24
Finished May 23 12:46:04 PM PDT 24
Peak memory 200452 kb
Host smart-0e021204-0330-4e3b-b703-d71fd50f596e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133169002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.133169002
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1472941387
Short name T613
Test name
Test status
Simulation time 119109496598 ps
CPU time 169.66 seconds
Started May 23 12:45:42 PM PDT 24
Finished May 23 12:48:33 PM PDT 24
Peak memory 200292 kb
Host smart-9f1827d3-80b6-42af-92f6-9f296edbaec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1472941387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1472941387
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.985735273
Short name T1125
Test name
Test status
Simulation time 12378189641 ps
CPU time 15.92 seconds
Started May 23 12:45:43 PM PDT 24
Finished May 23 12:46:00 PM PDT 24
Peak memory 200460 kb
Host smart-80ec2598-0adf-4e98-be82-4deb2af9395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985735273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.985735273
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1814295978
Short name T818
Test name
Test status
Simulation time 138650481799 ps
CPU time 132.31 seconds
Started May 23 12:45:43 PM PDT 24
Finished May 23 12:47:57 PM PDT 24
Peak memory 200112 kb
Host smart-8281bd3b-254e-4d61-b73c-c7b5f1f9cf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814295978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1814295978
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.2549136210
Short name T528
Test name
Test status
Simulation time 5897826021 ps
CPU time 319.66 seconds
Started May 23 12:45:40 PM PDT 24
Finished May 23 12:51:01 PM PDT 24
Peak memory 200396 kb
Host smart-0d40833d-c468-4293-94bc-e5e9fb064f81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2549136210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2549136210
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3570104948
Short name T1075
Test name
Test status
Simulation time 1493804051 ps
CPU time 1.78 seconds
Started May 23 12:45:40 PM PDT 24
Finished May 23 12:45:42 PM PDT 24
Peak memory 199400 kb
Host smart-88c79365-f0a9-4c38-bebe-add1ab4e5daf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3570104948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3570104948
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2119558970
Short name T740
Test name
Test status
Simulation time 19456636574 ps
CPU time 35.37 seconds
Started May 23 12:45:41 PM PDT 24
Finished May 23 12:46:17 PM PDT 24
Peak memory 200308 kb
Host smart-429a4042-d84f-4bdd-993c-fd2896cb8a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119558970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2119558970
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3037284659
Short name T271
Test name
Test status
Simulation time 37184910150 ps
CPU time 15.03 seconds
Started May 23 12:45:43 PM PDT 24
Finished May 23 12:46:00 PM PDT 24
Peak memory 196460 kb
Host smart-554a1192-7859-4b05-a5d6-b17ec3495284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037284659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3037284659
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1958123546
Short name T464
Test name
Test status
Simulation time 715814814 ps
CPU time 1.59 seconds
Started May 23 12:45:28 PM PDT 24
Finished May 23 12:45:32 PM PDT 24
Peak memory 198704 kb
Host smart-2f56480f-815f-45d5-8dbf-83b42214ece2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958123546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1958123546
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1352752279
Short name T955
Test name
Test status
Simulation time 110097086080 ps
CPU time 735.26 seconds
Started May 23 12:45:43 PM PDT 24
Finished May 23 12:58:01 PM PDT 24
Peak memory 200464 kb
Host smart-f32b7481-7baf-4d45-8056-04cac8cd6ba0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352752279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1352752279
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3318803997
Short name T293
Test name
Test status
Simulation time 147320202749 ps
CPU time 767.62 seconds
Started May 23 12:45:40 PM PDT 24
Finished May 23 12:58:29 PM PDT 24
Peak memory 225288 kb
Host smart-b0323594-1a60-4e2a-bf1d-82376b58fb0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318803997 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3318803997
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3393505846
Short name T48
Test name
Test status
Simulation time 1620966889 ps
CPU time 2.17 seconds
Started May 23 12:45:44 PM PDT 24
Finished May 23 12:45:48 PM PDT 24
Peak memory 199100 kb
Host smart-0b3ed48d-bccf-43b3-baed-2a89c85c1f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393505846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3393505846
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.778856039
Short name T490
Test name
Test status
Simulation time 31752374832 ps
CPU time 47.15 seconds
Started May 23 12:45:29 PM PDT 24
Finished May 23 12:46:18 PM PDT 24
Peak memory 200320 kb
Host smart-cecf01d8-898f-4536-8b73-0daffc1fc043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778856039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.778856039
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2478192936
Short name T985
Test name
Test status
Simulation time 13662740 ps
CPU time 0.59 seconds
Started May 23 12:45:43 PM PDT 24
Finished May 23 12:45:46 PM PDT 24
Peak memory 195800 kb
Host smart-e8828204-5b80-4d12-a765-00bd0d912dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478192936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2478192936
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3896807233
Short name T281
Test name
Test status
Simulation time 32397196751 ps
CPU time 59.88 seconds
Started May 23 12:45:41 PM PDT 24
Finished May 23 12:46:42 PM PDT 24
Peak memory 200452 kb
Host smart-9e66a6da-f7df-42e0-a735-16ee4e0914f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896807233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3896807233
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2966775726
Short name T644
Test name
Test status
Simulation time 66459447162 ps
CPU time 503.24 seconds
Started May 23 12:45:42 PM PDT 24
Finished May 23 12:54:06 PM PDT 24
Peak memory 200332 kb
Host smart-d53da88f-f62c-4822-81a2-dcbc3b765682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966775726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2966775726
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3316605315
Short name T1037
Test name
Test status
Simulation time 125684458343 ps
CPU time 99.52 seconds
Started May 23 12:45:41 PM PDT 24
Finished May 23 12:47:22 PM PDT 24
Peak memory 200308 kb
Host smart-3a4dedb0-2703-49b8-bdd8-55aa37abad29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316605315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3316605315
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3963854013
Short name T1181
Test name
Test status
Simulation time 10470385745 ps
CPU time 22.12 seconds
Started May 23 12:45:41 PM PDT 24
Finished May 23 12:46:04 PM PDT 24
Peak memory 200012 kb
Host smart-1010528c-fbd6-43d3-b5da-fe94bdd8787d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963854013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3963854013
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.404587379
Short name T708
Test name
Test status
Simulation time 162530695232 ps
CPU time 1340.43 seconds
Started May 23 12:45:43 PM PDT 24
Finished May 23 01:08:06 PM PDT 24
Peak memory 200388 kb
Host smart-9c16d6c6-1f3f-4987-b7ed-04e70530ab27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=404587379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.404587379
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2793975011
Short name T805
Test name
Test status
Simulation time 4057863978 ps
CPU time 5.42 seconds
Started May 23 12:45:42 PM PDT 24
Finished May 23 12:45:49 PM PDT 24
Peak memory 200136 kb
Host smart-ff94d458-5670-4197-be83-ede4fa1bd7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793975011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2793975011
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2487649567
Short name T667
Test name
Test status
Simulation time 50798415535 ps
CPU time 41.12 seconds
Started May 23 12:45:42 PM PDT 24
Finished May 23 12:46:25 PM PDT 24
Peak memory 200496 kb
Host smart-5be125fd-dde0-4578-8d9d-6c23bc4cdc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487649567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2487649567
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1416199418
Short name T1031
Test name
Test status
Simulation time 16170507595 ps
CPU time 919.23 seconds
Started May 23 12:45:42 PM PDT 24
Finished May 23 01:01:02 PM PDT 24
Peak memory 200380 kb
Host smart-ff2f88c4-6db1-4063-84d5-42519f66559e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416199418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1416199418
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2708007592
Short name T614
Test name
Test status
Simulation time 4520785503 ps
CPU time 34.84 seconds
Started May 23 12:45:43 PM PDT 24
Finished May 23 12:46:19 PM PDT 24
Peak memory 199252 kb
Host smart-aafa5e28-d223-4b93-b416-34563647ff87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2708007592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2708007592
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3285250720
Short name T484
Test name
Test status
Simulation time 91723770694 ps
CPU time 146.76 seconds
Started May 23 12:45:43 PM PDT 24
Finished May 23 12:48:12 PM PDT 24
Peak memory 200360 kb
Host smart-c82ac5a2-953a-421a-a5e6-d00eeb9d446f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285250720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3285250720
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3882264779
Short name T758
Test name
Test status
Simulation time 5609701657 ps
CPU time 2.74 seconds
Started May 23 12:45:41 PM PDT 24
Finished May 23 12:45:45 PM PDT 24
Peak memory 196404 kb
Host smart-098f8117-4009-4efd-8001-1a5a4fa602d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882264779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3882264779
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3859996475
Short name T914
Test name
Test status
Simulation time 5488904953 ps
CPU time 16.04 seconds
Started May 23 12:45:40 PM PDT 24
Finished May 23 12:45:57 PM PDT 24
Peak memory 199588 kb
Host smart-6fe145b7-55cb-4469-ab18-afe33aba97fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859996475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3859996475
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.411102163
Short name T887
Test name
Test status
Simulation time 219295860472 ps
CPU time 181.01 seconds
Started May 23 12:45:43 PM PDT 24
Finished May 23 12:48:46 PM PDT 24
Peak memory 208892 kb
Host smart-c25c4009-7eeb-4252-85e3-57f42209209c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411102163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.411102163
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3551988155
Short name T824
Test name
Test status
Simulation time 41294475188 ps
CPU time 523.74 seconds
Started May 23 12:45:42 PM PDT 24
Finished May 23 12:54:27 PM PDT 24
Peak memory 217156 kb
Host smart-34ddc8a3-50e1-4152-9fa2-3110e9309f50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551988155 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3551988155
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3838503195
Short name T962
Test name
Test status
Simulation time 1698091702 ps
CPU time 2.3 seconds
Started May 23 12:45:56 PM PDT 24
Finished May 23 12:46:00 PM PDT 24
Peak memory 199116 kb
Host smart-670ad6be-3dfc-4f80-bc71-01e99f8121e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838503195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3838503195
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2312889997
Short name T320
Test name
Test status
Simulation time 86692713677 ps
CPU time 155.42 seconds
Started May 23 12:45:44 PM PDT 24
Finished May 23 12:48:21 PM PDT 24
Peak memory 200348 kb
Host smart-8301cfe1-6d10-4b54-b282-04eccec3b27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312889997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2312889997
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.561341519
Short name T939
Test name
Test status
Simulation time 24035964 ps
CPU time 0.55 seconds
Started May 23 12:45:47 PM PDT 24
Finished May 23 12:45:49 PM PDT 24
Peak memory 195748 kb
Host smart-c34dbd05-0059-47fd-b790-eac9447376bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561341519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.561341519
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3370867771
Short name T906
Test name
Test status
Simulation time 151379368458 ps
CPU time 70 seconds
Started May 23 12:45:41 PM PDT 24
Finished May 23 12:46:52 PM PDT 24
Peak memory 200428 kb
Host smart-57eb8c47-aaa4-4e45-9a3e-5a309769faff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370867771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3370867771
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.637912754
Short name T559
Test name
Test status
Simulation time 73934244386 ps
CPU time 234 seconds
Started May 23 12:45:46 PM PDT 24
Finished May 23 12:49:41 PM PDT 24
Peak memory 200468 kb
Host smart-ad85f8d5-1e4c-43ef-b44c-558d893eab69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637912754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.637912754
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3255874435
Short name T211
Test name
Test status
Simulation time 32531155215 ps
CPU time 55.28 seconds
Started May 23 12:45:41 PM PDT 24
Finished May 23 12:46:38 PM PDT 24
Peak memory 200384 kb
Host smart-9fe726c0-20d3-4ba7-a1b2-51f64c2a2276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255874435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3255874435
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3873473769
Short name T632
Test name
Test status
Simulation time 39503067823 ps
CPU time 23.87 seconds
Started May 23 12:45:44 PM PDT 24
Finished May 23 12:46:10 PM PDT 24
Peak memory 200300 kb
Host smart-389e6d31-ac17-4963-a2be-c913eab53116
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873473769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3873473769
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1233922682
Short name T275
Test name
Test status
Simulation time 106175134835 ps
CPU time 204.36 seconds
Started May 23 12:45:43 PM PDT 24
Finished May 23 12:49:10 PM PDT 24
Peak memory 200444 kb
Host smart-7cace3fb-5a1f-4270-a48d-46220c250d3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1233922682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1233922682
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1413849502
Short name T468
Test name
Test status
Simulation time 7972814763 ps
CPU time 2.77 seconds
Started May 23 12:45:42 PM PDT 24
Finished May 23 12:45:47 PM PDT 24
Peak memory 198732 kb
Host smart-01483080-6709-4219-8bb7-e3126bb8870a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413849502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1413849502
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3973290755
Short name T5
Test name
Test status
Simulation time 345294400710 ps
CPU time 168.76 seconds
Started May 23 12:45:45 PM PDT 24
Finished May 23 12:48:35 PM PDT 24
Peak memory 208812 kb
Host smart-241c7c69-c451-40dc-9126-3464ccbada7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973290755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3973290755
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.4076060113
Short name T554
Test name
Test status
Simulation time 13064832496 ps
CPU time 160.76 seconds
Started May 23 12:45:48 PM PDT 24
Finished May 23 12:48:29 PM PDT 24
Peak memory 200352 kb
Host smart-966b6b57-cd35-44f5-b27f-af56f9ad75fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4076060113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.4076060113
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3643470751
Short name T440
Test name
Test status
Simulation time 1287773747 ps
CPU time 1.15 seconds
Started May 23 12:45:42 PM PDT 24
Finished May 23 12:45:44 PM PDT 24
Peak memory 195964 kb
Host smart-483f53bd-f98a-4460-890e-7731e32b1bb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3643470751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3643470751
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2793237426
Short name T311
Test name
Test status
Simulation time 372809971895 ps
CPU time 326.67 seconds
Started May 23 12:45:43 PM PDT 24
Finished May 23 12:51:12 PM PDT 24
Peak memory 200368 kb
Host smart-7f5ea4c1-8bb8-41d5-b82b-c2f1ab354ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793237426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2793237426
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2009703652
Short name T652
Test name
Test status
Simulation time 5867612199 ps
CPU time 2.24 seconds
Started May 23 12:45:44 PM PDT 24
Finished May 23 12:45:48 PM PDT 24
Peak memory 196436 kb
Host smart-8416c5fb-e8d5-47b8-a49c-10461aea29c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009703652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2009703652
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3398002423
Short name T717
Test name
Test status
Simulation time 471040216 ps
CPU time 1.21 seconds
Started May 23 12:45:43 PM PDT 24
Finished May 23 12:45:45 PM PDT 24
Peak memory 199956 kb
Host smart-940c5284-1415-4b1d-8f2b-a309592cc884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398002423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3398002423
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1250018047
Short name T853
Test name
Test status
Simulation time 23929547686 ps
CPU time 477.97 seconds
Started May 23 12:45:46 PM PDT 24
Finished May 23 12:53:45 PM PDT 24
Peak memory 216828 kb
Host smart-781c2fca-3b86-448f-9a39-5d386112d423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250018047 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1250018047
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1137930072
Short name T290
Test name
Test status
Simulation time 6965286460 ps
CPU time 26.48 seconds
Started May 23 12:45:47 PM PDT 24
Finished May 23 12:46:14 PM PDT 24
Peak memory 200416 kb
Host smart-5f38a9fd-3d70-484f-bf8d-10f5e973950c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137930072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1137930072
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2699307779
Short name T9
Test name
Test status
Simulation time 40951482037 ps
CPU time 74.56 seconds
Started May 23 12:45:47 PM PDT 24
Finished May 23 12:47:02 PM PDT 24
Peak memory 200480 kb
Host smart-48f5df59-9c3e-4eb6-94db-9a2b560cad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699307779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2699307779
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3260192552
Short name T357
Test name
Test status
Simulation time 46401970 ps
CPU time 0.56 seconds
Started May 23 12:45:52 PM PDT 24
Finished May 23 12:45:54 PM PDT 24
Peak memory 195844 kb
Host smart-2a664ead-6513-4e3f-8b5a-133bbf980ab2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260192552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3260192552
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2131077408
Short name T925
Test name
Test status
Simulation time 43896663085 ps
CPU time 66.38 seconds
Started May 23 12:45:42 PM PDT 24
Finished May 23 12:46:50 PM PDT 24
Peak memory 200268 kb
Host smart-c7941360-72b3-4826-8bdd-5220b783a315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131077408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2131077408
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.4064170175
Short name T504
Test name
Test status
Simulation time 117505962994 ps
CPU time 35.94 seconds
Started May 23 12:45:46 PM PDT 24
Finished May 23 12:46:23 PM PDT 24
Peak memory 200392 kb
Host smart-e49acb88-d495-4e45-b20b-7b2b995301c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064170175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.4064170175
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.84925208
Short name T486
Test name
Test status
Simulation time 50471833898 ps
CPU time 43.51 seconds
Started May 23 12:45:48 PM PDT 24
Finished May 23 12:46:32 PM PDT 24
Peak memory 200400 kb
Host smart-451e04a7-2d12-4043-958d-ce63dff5a763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84925208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.84925208
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1699796897
Short name T452
Test name
Test status
Simulation time 18346591170 ps
CPU time 27.32 seconds
Started May 23 12:45:42 PM PDT 24
Finished May 23 12:46:11 PM PDT 24
Peak memory 196376 kb
Host smart-2e5fa1e7-3471-450d-9d1e-c60538d7881c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699796897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1699796897
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3122996445
Short name T422
Test name
Test status
Simulation time 134467839941 ps
CPU time 1089.09 seconds
Started May 23 12:45:52 PM PDT 24
Finished May 23 01:04:02 PM PDT 24
Peak memory 200348 kb
Host smart-d26887bc-3f6c-4563-9829-d48e86a0b034
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3122996445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3122996445
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.23241768
Short name T338
Test name
Test status
Simulation time 5120326142 ps
CPU time 3.68 seconds
Started May 23 12:45:41 PM PDT 24
Finished May 23 12:45:45 PM PDT 24
Peak memory 198968 kb
Host smart-0758fc18-7050-4e0c-95fc-867be97b6b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23241768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.23241768
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2547594989
Short name T823
Test name
Test status
Simulation time 56828256823 ps
CPU time 31.9 seconds
Started May 23 12:45:48 PM PDT 24
Finished May 23 12:46:21 PM PDT 24
Peak memory 199608 kb
Host smart-de80fc25-972d-48d2-acc2-65bd99c1a27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547594989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2547594989
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1877629082
Short name T661
Test name
Test status
Simulation time 8576512217 ps
CPU time 489.11 seconds
Started May 23 12:45:53 PM PDT 24
Finished May 23 12:54:03 PM PDT 24
Peak memory 200400 kb
Host smart-448c2ae7-b781-4316-b3dd-727bafedb344
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1877629082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1877629082
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.667835785
Short name T811
Test name
Test status
Simulation time 6590480106 ps
CPU time 15.08 seconds
Started May 23 12:45:48 PM PDT 24
Finished May 23 12:46:04 PM PDT 24
Peak memory 200116 kb
Host smart-a8df329e-02e2-4131-b4d1-38363d031774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=667835785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.667835785
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2295917400
Short name T503
Test name
Test status
Simulation time 178716992751 ps
CPU time 53.92 seconds
Started May 23 12:45:43 PM PDT 24
Finished May 23 12:46:39 PM PDT 24
Peak memory 200264 kb
Host smart-373f5c2c-2198-45bf-808c-d464f386038a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295917400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2295917400
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3924897930
Short name T1019
Test name
Test status
Simulation time 71376529993 ps
CPU time 30.18 seconds
Started May 23 12:45:48 PM PDT 24
Finished May 23 12:46:19 PM PDT 24
Peak memory 196092 kb
Host smart-64922f92-d251-4459-b8f2-2f192fba57d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924897930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3924897930
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.357065336
Short name T893
Test name
Test status
Simulation time 683268783 ps
CPU time 2.15 seconds
Started May 23 12:45:46 PM PDT 24
Finished May 23 12:45:50 PM PDT 24
Peak memory 200048 kb
Host smart-ef802fb4-a209-4e75-b374-43a5a38b1b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357065336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.357065336
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3296663951
Short name T759
Test name
Test status
Simulation time 119240838959 ps
CPU time 200.8 seconds
Started May 23 12:45:55 PM PDT 24
Finished May 23 12:49:18 PM PDT 24
Peak memory 208760 kb
Host smart-f7b0d9c2-cfa0-4753-859a-c5d4284503a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296663951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3296663951
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3544712512
Short name T75
Test name
Test status
Simulation time 951067490759 ps
CPU time 699.17 seconds
Started May 23 12:45:52 PM PDT 24
Finished May 23 12:57:32 PM PDT 24
Peak memory 217108 kb
Host smart-2ab948ee-1706-43c5-b3fc-e2eff08e1379
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544712512 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3544712512
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2069957298
Short name T891
Test name
Test status
Simulation time 1555347112 ps
CPU time 3.32 seconds
Started May 23 12:45:40 PM PDT 24
Finished May 23 12:45:44 PM PDT 24
Peak memory 199176 kb
Host smart-2511285f-6864-4973-87ac-684c0596f4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069957298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2069957298
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3538832275
Short name T749
Test name
Test status
Simulation time 39241685490 ps
CPU time 67.59 seconds
Started May 23 12:45:47 PM PDT 24
Finished May 23 12:46:56 PM PDT 24
Peak memory 200408 kb
Host smart-50a58b49-6ead-4b23-af3d-0b6977e3a430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538832275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3538832275
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3332540676
Short name T542
Test name
Test status
Simulation time 42256491 ps
CPU time 0.57 seconds
Started May 23 12:45:52 PM PDT 24
Finished May 23 12:45:55 PM PDT 24
Peak memory 195824 kb
Host smart-276e796e-9650-4c8d-97ec-49c61e0efc81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332540676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3332540676
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3855698864
Short name T263
Test name
Test status
Simulation time 78074849641 ps
CPU time 125.55 seconds
Started May 23 12:45:53 PM PDT 24
Finished May 23 12:48:00 PM PDT 24
Peak memory 200420 kb
Host smart-388f25ba-e2b0-4496-9107-8e4b72e467d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855698864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3855698864
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1281996007
Short name T896
Test name
Test status
Simulation time 226350025847 ps
CPU time 33.59 seconds
Started May 23 12:45:54 PM PDT 24
Finished May 23 12:46:29 PM PDT 24
Peak memory 200380 kb
Host smart-14150b05-eb97-44a0-9784-9b4cce912f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281996007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1281996007
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3326565662
Short name T1123
Test name
Test status
Simulation time 76120803161 ps
CPU time 30.57 seconds
Started May 23 12:45:52 PM PDT 24
Finished May 23 12:46:24 PM PDT 24
Peak memory 200460 kb
Host smart-3f8abb5b-617f-46c7-9715-6aa42b78c753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326565662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3326565662
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.4196491506
Short name T594
Test name
Test status
Simulation time 4160193025 ps
CPU time 2.11 seconds
Started May 23 12:45:52 PM PDT 24
Finished May 23 12:45:56 PM PDT 24
Peak memory 196284 kb
Host smart-7901d11c-2aa2-4fb5-b229-924427c5c9a6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196491506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.4196491506
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.683801338
Short name T1015
Test name
Test status
Simulation time 118162145392 ps
CPU time 234.49 seconds
Started May 23 12:45:56 PM PDT 24
Finished May 23 12:49:52 PM PDT 24
Peak memory 200332 kb
Host smart-549acd46-c351-4bac-91f6-4375d61087a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=683801338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.683801338
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.4117484292
Short name T966
Test name
Test status
Simulation time 5393590257 ps
CPU time 10.25 seconds
Started May 23 12:45:54 PM PDT 24
Finished May 23 12:46:06 PM PDT 24
Peak memory 200268 kb
Host smart-1ce338a9-f3b7-4b11-a3f8-25922f65681c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117484292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.4117484292
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3131445736
Short name T1006
Test name
Test status
Simulation time 10450709541 ps
CPU time 18.99 seconds
Started May 23 12:45:54 PM PDT 24
Finished May 23 12:46:15 PM PDT 24
Peak memory 197540 kb
Host smart-fc710e8f-aa2a-46eb-ad0c-daffcdc2c0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131445736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3131445736
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1150124844
Short name T1096
Test name
Test status
Simulation time 8902975885 ps
CPU time 441.02 seconds
Started May 23 12:45:54 PM PDT 24
Finished May 23 12:53:17 PM PDT 24
Peak memory 200372 kb
Host smart-09717609-8e4a-4e2e-9cd5-9b17d00df931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150124844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1150124844
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3700543011
Short name T748
Test name
Test status
Simulation time 6091060051 ps
CPU time 13.33 seconds
Started May 23 12:45:57 PM PDT 24
Finished May 23 12:46:12 PM PDT 24
Peak memory 200136 kb
Host smart-27d63eb5-26f4-43be-bad5-24542cdb40a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3700543011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3700543011
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3298734953
Short name T1073
Test name
Test status
Simulation time 119965428586 ps
CPU time 138.2 seconds
Started May 23 12:45:56 PM PDT 24
Finished May 23 12:48:16 PM PDT 24
Peak memory 200188 kb
Host smart-345f11b0-c33d-4cd1-9220-f10fde93b0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298734953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3298734953
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.605754600
Short name T412
Test name
Test status
Simulation time 40262896132 ps
CPU time 68.06 seconds
Started May 23 12:45:54 PM PDT 24
Finished May 23 12:47:03 PM PDT 24
Peak memory 196348 kb
Host smart-ef316ea6-6985-4d1c-910a-e30e6f2c5fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605754600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.605754600
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3711856132
Short name T295
Test name
Test status
Simulation time 322311127 ps
CPU time 1.21 seconds
Started May 23 12:45:56 PM PDT 24
Finished May 23 12:45:59 PM PDT 24
Peak memory 198572 kb
Host smart-aed71038-a07a-43d9-b80b-814065d3c766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711856132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3711856132
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3437930035
Short name T339
Test name
Test status
Simulation time 162075980770 ps
CPU time 525.8 seconds
Started May 23 12:45:54 PM PDT 24
Finished May 23 12:54:41 PM PDT 24
Peak memory 200268 kb
Host smart-e54eb47f-ca1b-40ec-a865-25d10601dc88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437930035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3437930035
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.841871791
Short name T425
Test name
Test status
Simulation time 15389977483 ps
CPU time 198.39 seconds
Started May 23 12:45:53 PM PDT 24
Finished May 23 12:49:13 PM PDT 24
Peak memory 216012 kb
Host smart-22bfc6a7-2894-42da-869f-3172a583c17b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841871791 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.841871791
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1232283017
Short name T72
Test name
Test status
Simulation time 1657635262 ps
CPU time 3.04 seconds
Started May 23 12:45:53 PM PDT 24
Finished May 23 12:45:57 PM PDT 24
Peak memory 199204 kb
Host smart-ccab1a03-90dc-442b-b82b-e37dd2d7a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232283017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1232283017
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2377846799
Short name T803
Test name
Test status
Simulation time 37434853596 ps
CPU time 75.72 seconds
Started May 23 12:45:53 PM PDT 24
Finished May 23 12:47:10 PM PDT 24
Peak memory 200324 kb
Host smart-cfc5ce62-d608-4562-bc6f-f72d35577a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377846799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2377846799
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3697345124
Short name T619
Test name
Test status
Simulation time 41895710 ps
CPU time 0.55 seconds
Started May 23 12:45:58 PM PDT 24
Finished May 23 12:46:00 PM PDT 24
Peak memory 195848 kb
Host smart-f77407b1-f852-40ec-8b04-17765e05da05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697345124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3697345124
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.746342400
Short name T284
Test name
Test status
Simulation time 65039823905 ps
CPU time 119.19 seconds
Started May 23 12:45:54 PM PDT 24
Finished May 23 12:47:55 PM PDT 24
Peak memory 200228 kb
Host smart-edb36cb8-36b4-4380-9440-b39c93198768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746342400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.746342400
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1428257804
Short name T1081
Test name
Test status
Simulation time 123361751162 ps
CPU time 50.52 seconds
Started May 23 12:45:55 PM PDT 24
Finished May 23 12:46:47 PM PDT 24
Peak memory 200336 kb
Host smart-6ba44b3a-5484-4189-acf2-c05e6bc3ab48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428257804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1428257804
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2336918357
Short name T646
Test name
Test status
Simulation time 6870291621 ps
CPU time 12.22 seconds
Started May 23 12:45:55 PM PDT 24
Finished May 23 12:46:09 PM PDT 24
Peak memory 200412 kb
Host smart-4aab6b50-a3f6-4f44-a048-83460c744598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336918357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2336918357
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.242069373
Short name T689
Test name
Test status
Simulation time 45306725263 ps
CPU time 43.8 seconds
Started May 23 12:45:57 PM PDT 24
Finished May 23 12:46:42 PM PDT 24
Peak memory 200368 kb
Host smart-f47c3638-18fa-4cd5-be20-f3b6de73bac6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242069373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.242069373
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1878412633
Short name T402
Test name
Test status
Simulation time 94185558560 ps
CPU time 210.83 seconds
Started May 23 12:45:53 PM PDT 24
Finished May 23 12:49:25 PM PDT 24
Peak memory 200404 kb
Host smart-7981e4fa-a6c0-46ce-bbdc-bd2aeb220bd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878412633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1878412633
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2737719456
Short name T637
Test name
Test status
Simulation time 1765489853 ps
CPU time 3.79 seconds
Started May 23 12:45:54 PM PDT 24
Finished May 23 12:46:00 PM PDT 24
Peak memory 196280 kb
Host smart-79ca7a2a-3765-4764-b5a0-a862f9abcc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737719456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2737719456
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3293851202
Short name T736
Test name
Test status
Simulation time 141027044980 ps
CPU time 71.52 seconds
Started May 23 12:46:00 PM PDT 24
Finished May 23 12:47:13 PM PDT 24
Peak memory 199136 kb
Host smart-eab40a00-e3d4-4076-b12a-928b88597a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293851202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3293851202
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2554217555
Short name T895
Test name
Test status
Simulation time 10429023480 ps
CPU time 465.28 seconds
Started May 23 12:45:57 PM PDT 24
Finished May 23 12:53:44 PM PDT 24
Peak memory 200304 kb
Host smart-eac38eda-e5f6-4196-bffb-1446401237ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2554217555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2554217555
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3157206063
Short name T682
Test name
Test status
Simulation time 4014384336 ps
CPU time 3.42 seconds
Started May 23 12:45:58 PM PDT 24
Finished May 23 12:46:03 PM PDT 24
Peak memory 199420 kb
Host smart-333e82b7-a538-44fd-bf2c-3987e34afc4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157206063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3157206063
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1507336960
Short name T1024
Test name
Test status
Simulation time 55140086479 ps
CPU time 87.2 seconds
Started May 23 12:45:56 PM PDT 24
Finished May 23 12:47:25 PM PDT 24
Peak memory 200200 kb
Host smart-d07f1def-6713-49f7-8af1-b46a72fb42b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507336960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1507336960
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.11851967
Short name T400
Test name
Test status
Simulation time 2239815022 ps
CPU time 4.23 seconds
Started May 23 12:45:54 PM PDT 24
Finished May 23 12:46:00 PM PDT 24
Peak memory 195888 kb
Host smart-5c272ef1-e4a0-4d9b-a6ca-9b81323072ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11851967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.11851967
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1228680371
Short name T366
Test name
Test status
Simulation time 296132607 ps
CPU time 1.13 seconds
Started May 23 12:45:54 PM PDT 24
Finished May 23 12:45:57 PM PDT 24
Peak memory 198564 kb
Host smart-5c7d8be8-e416-408c-bb66-bf77d2d9e6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228680371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1228680371
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.249945455
Short name T1129
Test name
Test status
Simulation time 29361213189 ps
CPU time 26.75 seconds
Started May 23 12:45:58 PM PDT 24
Finished May 23 12:46:26 PM PDT 24
Peak memory 200428 kb
Host smart-6dd08c01-4ce6-419a-9ffc-00f2f3d07799
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249945455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.249945455
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1281230581
Short name T1087
Test name
Test status
Simulation time 247869508771 ps
CPU time 779.53 seconds
Started May 23 12:45:57 PM PDT 24
Finished May 23 12:58:59 PM PDT 24
Peak memory 217248 kb
Host smart-89cdd563-2a3a-4e0e-b874-1329d6196498
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281230581 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1281230581
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.598776366
Short name T1090
Test name
Test status
Simulation time 7927740499 ps
CPU time 16.33 seconds
Started May 23 12:45:54 PM PDT 24
Finished May 23 12:46:12 PM PDT 24
Peak memory 200128 kb
Host smart-83df326e-a1b3-4d0f-bdfd-6d0f7d0acb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598776366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.598776366
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2957137404
Short name T568
Test name
Test status
Simulation time 36605358187 ps
CPU time 24.61 seconds
Started May 23 12:45:54 PM PDT 24
Finished May 23 12:46:21 PM PDT 24
Peak memory 200448 kb
Host smart-b93307cb-a4da-45db-ba56-0cab52994172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957137404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2957137404
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2051522378
Short name T463
Test name
Test status
Simulation time 30079719 ps
CPU time 0.55 seconds
Started May 23 12:43:57 PM PDT 24
Finished May 23 12:43:59 PM PDT 24
Peak memory 195732 kb
Host smart-3e74a81c-ce24-496c-8268-aa50013f3b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051522378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2051522378
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1294450442
Short name T1069
Test name
Test status
Simulation time 146688333290 ps
CPU time 267.63 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 12:48:27 PM PDT 24
Peak memory 200460 kb
Host smart-d44411a5-ece0-4c59-989b-f6b7297c6ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294450442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1294450442
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3932817460
Short name T1141
Test name
Test status
Simulation time 49103263515 ps
CPU time 76.66 seconds
Started May 23 12:44:00 PM PDT 24
Finished May 23 12:45:19 PM PDT 24
Peak memory 200244 kb
Host smart-947e911a-938e-42dd-aa6c-8a477a8dec2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932817460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3932817460
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.897923259
Short name T449
Test name
Test status
Simulation time 47634145543 ps
CPU time 23.23 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 12:44:23 PM PDT 24
Peak memory 200320 kb
Host smart-ab1ac250-66a6-4054-9afc-520276187946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897923259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.897923259
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.121360024
Short name T335
Test name
Test status
Simulation time 10264925059 ps
CPU time 3.56 seconds
Started May 23 12:43:54 PM PDT 24
Finished May 23 12:43:59 PM PDT 24
Peak memory 197048 kb
Host smart-1dffa589-1c0b-49eb-a9a2-3a1605680672
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121360024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.121360024
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2296977051
Short name T1052
Test name
Test status
Simulation time 79047275047 ps
CPU time 73.61 seconds
Started May 23 12:43:55 PM PDT 24
Finished May 23 12:45:10 PM PDT 24
Peak memory 200292 kb
Host smart-6138a4f8-69e5-4d5a-8d17-f868f7994bd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296977051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2296977051
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.4021023487
Short name T801
Test name
Test status
Simulation time 7078364756 ps
CPU time 8.16 seconds
Started May 23 12:43:56 PM PDT 24
Finished May 23 12:44:06 PM PDT 24
Peak memory 198888 kb
Host smart-31693425-0a99-4fde-913e-729c8c3fc3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021023487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.4021023487
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1205394018
Short name T330
Test name
Test status
Simulation time 56378096751 ps
CPU time 237.39 seconds
Started May 23 12:44:02 PM PDT 24
Finished May 23 12:48:01 PM PDT 24
Peak memory 199848 kb
Host smart-b5800574-7701-46a1-9846-7c91f7800e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205394018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1205394018
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1696525745
Short name T430
Test name
Test status
Simulation time 7249775600 ps
CPU time 120.83 seconds
Started May 23 12:43:54 PM PDT 24
Finished May 23 12:45:56 PM PDT 24
Peak memory 200268 kb
Host smart-8ec2847c-7e3b-4f0d-92fe-16aadc6551ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1696525745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1696525745
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2329559641
Short name T948
Test name
Test status
Simulation time 3884320076 ps
CPU time 16.04 seconds
Started May 23 12:44:00 PM PDT 24
Finished May 23 12:44:18 PM PDT 24
Peak memory 198832 kb
Host smart-a0d1903e-dbfe-4f77-ac79-8d1c8c51d016
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2329559641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2329559641
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1093044073
Short name T1131
Test name
Test status
Simulation time 14708096239 ps
CPU time 23.18 seconds
Started May 23 12:43:59 PM PDT 24
Finished May 23 12:44:24 PM PDT 24
Peak memory 199932 kb
Host smart-1312009d-a959-49f4-bd50-3a4608af96eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093044073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1093044073
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1853863413
Short name T774
Test name
Test status
Simulation time 3110320755 ps
CPU time 1.81 seconds
Started May 23 12:43:57 PM PDT 24
Finished May 23 12:44:01 PM PDT 24
Peak memory 196332 kb
Host smart-d15bc86e-a794-46e9-9d68-f8d07ac53255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853863413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1853863413
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.4141400882
Short name T28
Test name
Test status
Simulation time 34938807 ps
CPU time 0.77 seconds
Started May 23 12:44:00 PM PDT 24
Finished May 23 12:44:03 PM PDT 24
Peak memory 218812 kb
Host smart-f4b070e9-5c53-4f48-a10f-73edde064fc1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141400882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.4141400882
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3315217979
Short name T986
Test name
Test status
Simulation time 5384475315 ps
CPU time 23.54 seconds
Started May 23 12:43:53 PM PDT 24
Finished May 23 12:44:17 PM PDT 24
Peak memory 200208 kb
Host smart-665d4d35-11d5-4859-9cc1-0722378c45f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315217979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3315217979
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2869647293
Short name T675
Test name
Test status
Simulation time 155176631975 ps
CPU time 75.75 seconds
Started May 23 12:43:55 PM PDT 24
Finished May 23 12:45:12 PM PDT 24
Peak memory 200404 kb
Host smart-8cfcbebb-c41d-41af-8f4d-bf9dd26e36af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869647293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2869647293
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.22708362
Short name T55
Test name
Test status
Simulation time 105545432792 ps
CPU time 1243.22 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 01:04:43 PM PDT 24
Peak memory 227964 kb
Host smart-bc8c4081-f5f3-4daa-a443-b488aa864ebe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22708362 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.22708362
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3886224217
Short name T285
Test name
Test status
Simulation time 998509531 ps
CPU time 1.54 seconds
Started May 23 12:44:09 PM PDT 24
Finished May 23 12:44:13 PM PDT 24
Peak memory 198996 kb
Host smart-0b93b260-1af3-4437-8b6f-1559572ab114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886224217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3886224217
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3250528845
Short name T36
Test name
Test status
Simulation time 78018098120 ps
CPU time 50.96 seconds
Started May 23 12:43:56 PM PDT 24
Finished May 23 12:44:48 PM PDT 24
Peak memory 200308 kb
Host smart-e470f890-1214-4f4f-b105-c298002175f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250528845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3250528845
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1996084863
Short name T432
Test name
Test status
Simulation time 15153067 ps
CPU time 0.54 seconds
Started May 23 12:46:13 PM PDT 24
Finished May 23 12:46:15 PM PDT 24
Peak memory 195840 kb
Host smart-18eb5331-3000-4625-b20c-fa7ab4199bde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996084863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1996084863
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.4166379628
Short name T662
Test name
Test status
Simulation time 94023931469 ps
CPU time 152.05 seconds
Started May 23 12:45:59 PM PDT 24
Finished May 23 12:48:33 PM PDT 24
Peak memory 200408 kb
Host smart-f4e9de8f-d5d4-42f6-b61b-0fa340454090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166379628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.4166379628
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.981301857
Short name T946
Test name
Test status
Simulation time 35375431218 ps
CPU time 33.78 seconds
Started May 23 12:45:55 PM PDT 24
Finished May 23 12:46:30 PM PDT 24
Peak memory 200432 kb
Host smart-14fbf8c6-e981-4336-be1c-8a520ce52ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981301857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.981301857
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3740320699
Short name T351
Test name
Test status
Simulation time 16938427154 ps
CPU time 30.82 seconds
Started May 23 12:45:59 PM PDT 24
Finished May 23 12:46:32 PM PDT 24
Peak memory 200452 kb
Host smart-f7692922-db5f-4d79-9565-7102aeb5828a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740320699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3740320699
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3471859530
Short name T949
Test name
Test status
Simulation time 30546366513 ps
CPU time 24.13 seconds
Started May 23 12:46:01 PM PDT 24
Finished May 23 12:46:26 PM PDT 24
Peak memory 199212 kb
Host smart-7ef343fb-2529-435f-ad2b-696c9504385c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471859530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3471859530
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3831629819
Short name T510
Test name
Test status
Simulation time 26276535575 ps
CPU time 204.63 seconds
Started May 23 12:46:01 PM PDT 24
Finished May 23 12:49:27 PM PDT 24
Peak memory 200284 kb
Host smart-e3101ebb-eacc-4bd2-8dc7-17a02f9e65e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3831629819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3831629819
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1580832699
Short name T1134
Test name
Test status
Simulation time 2509597310 ps
CPU time 2.69 seconds
Started May 23 12:46:01 PM PDT 24
Finished May 23 12:46:05 PM PDT 24
Peak memory 196532 kb
Host smart-6760d2a2-6cb0-41b5-87cb-e4fdf1116693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580832699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1580832699
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2125989416
Short name T405
Test name
Test status
Simulation time 64295637637 ps
CPU time 11.93 seconds
Started May 23 12:45:55 PM PDT 24
Finished May 23 12:46:08 PM PDT 24
Peak memory 200484 kb
Host smart-d6cfb9c5-83e1-4a06-95a8-af993e7538da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125989416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2125989416
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3461758612
Short name T546
Test name
Test status
Simulation time 24636469098 ps
CPU time 233.95 seconds
Started May 23 12:46:01 PM PDT 24
Finished May 23 12:49:56 PM PDT 24
Peak memory 200256 kb
Host smart-a70a11ac-42e8-4409-bbec-cc9729e06ed0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461758612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3461758612
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3535290063
Short name T453
Test name
Test status
Simulation time 5892607103 ps
CPU time 13.49 seconds
Started May 23 12:45:59 PM PDT 24
Finished May 23 12:46:14 PM PDT 24
Peak memory 198528 kb
Host smart-8299b874-e6ef-418a-8f82-4dfc7d7ef339
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3535290063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3535290063
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1235866379
Short name T776
Test name
Test status
Simulation time 76442684292 ps
CPU time 135.44 seconds
Started May 23 12:45:59 PM PDT 24
Finished May 23 12:48:16 PM PDT 24
Peak memory 200400 kb
Host smart-efd32a6c-def7-4adf-98b4-5475e78660a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235866379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1235866379
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.736975862
Short name T460
Test name
Test status
Simulation time 2573896905 ps
CPU time 1.74 seconds
Started May 23 12:45:58 PM PDT 24
Finished May 23 12:46:02 PM PDT 24
Peak memory 196472 kb
Host smart-cc28d7a1-2ec1-4d02-903c-22eb457de2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736975862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.736975862
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2995482362
Short name T1048
Test name
Test status
Simulation time 495291318 ps
CPU time 1.55 seconds
Started May 23 12:45:56 PM PDT 24
Finished May 23 12:45:59 PM PDT 24
Peak memory 199340 kb
Host smart-04c1753d-c02d-4412-b7fb-0b572d89e99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995482362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2995482362
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1661822118
Short name T729
Test name
Test status
Simulation time 193091139950 ps
CPU time 395.72 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:52:46 PM PDT 24
Peak memory 200480 kb
Host smart-360be5e0-d402-4041-bbb3-59762e95e740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661822118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1661822118
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3395125477
Short name T51
Test name
Test status
Simulation time 141365151685 ps
CPU time 2174.36 seconds
Started May 23 12:46:13 PM PDT 24
Finished May 23 01:22:29 PM PDT 24
Peak memory 231608 kb
Host smart-bbd9dd2c-5415-4f74-b3b4-7ab595e44133
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395125477 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3395125477
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3198225081
Short name T372
Test name
Test status
Simulation time 8152780773 ps
CPU time 8.84 seconds
Started May 23 12:45:54 PM PDT 24
Finished May 23 12:46:05 PM PDT 24
Peak memory 199928 kb
Host smart-876529c0-fc7c-4ff1-ac4b-4d8485cbcd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198225081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3198225081
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.4069725006
Short name T1068
Test name
Test status
Simulation time 188702125419 ps
CPU time 72.59 seconds
Started May 23 12:45:57 PM PDT 24
Finished May 23 12:47:11 PM PDT 24
Peak memory 200448 kb
Host smart-26d98865-a385-4dee-b07b-69f3d03070ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069725006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4069725006
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.4004534051
Short name T1042
Test name
Test status
Simulation time 42593447 ps
CPU time 0.55 seconds
Started May 23 12:46:11 PM PDT 24
Finished May 23 12:46:13 PM PDT 24
Peak memory 194740 kb
Host smart-ace646a1-99ea-4def-9aae-db2a17a4ec74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004534051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.4004534051
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1505939971
Short name T912
Test name
Test status
Simulation time 28295027297 ps
CPU time 42.72 seconds
Started May 23 12:46:11 PM PDT 24
Finished May 23 12:46:56 PM PDT 24
Peak memory 200428 kb
Host smart-4c644e16-11d0-4c22-a449-1bf33ad0b15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505939971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1505939971
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1800074020
Short name T1150
Test name
Test status
Simulation time 61837050525 ps
CPU time 105.52 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:47:56 PM PDT 24
Peak memory 200292 kb
Host smart-f8446df4-0c80-45b8-a58d-2ba4e324b187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800074020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1800074020
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.858712421
Short name T219
Test name
Test status
Simulation time 29457032662 ps
CPU time 24.66 seconds
Started May 23 12:46:08 PM PDT 24
Finished May 23 12:46:33 PM PDT 24
Peak memory 200316 kb
Host smart-28145435-86cd-4933-b19e-0192b9fd97ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858712421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.858712421
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.4273537361
Short name T1176
Test name
Test status
Simulation time 74603875940 ps
CPU time 123.9 seconds
Started May 23 12:46:11 PM PDT 24
Finished May 23 12:48:17 PM PDT 24
Peak memory 200440 kb
Host smart-6304e5fe-c485-4aa1-b25a-443c7d919d19
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273537361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.4273537361
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3684218983
Short name T408
Test name
Test status
Simulation time 21857797011 ps
CPU time 151.21 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:48:42 PM PDT 24
Peak memory 200452 kb
Host smart-a834c494-5b24-44d0-b446-4fd85f017ba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3684218983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3684218983
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.2870499332
Short name T935
Test name
Test status
Simulation time 1348852853 ps
CPU time 1.47 seconds
Started May 23 12:46:14 PM PDT 24
Finished May 23 12:46:16 PM PDT 24
Peak memory 198280 kb
Host smart-107d433a-a5e3-4253-99a8-5ab7de8f6cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870499332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2870499332
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1687024928
Short name T44
Test name
Test status
Simulation time 96805627171 ps
CPU time 102.11 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:47:53 PM PDT 24
Peak memory 208848 kb
Host smart-15f46f99-0ee8-4819-bcd4-cef02938cfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687024928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1687024928
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.578076237
Short name T1063
Test name
Test status
Simulation time 14483617068 ps
CPU time 177.47 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:49:08 PM PDT 24
Peak memory 200320 kb
Host smart-72271e91-4b26-4d0a-9c96-61d39a6c227c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578076237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.578076237
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2973341390
Short name T684
Test name
Test status
Simulation time 2337628260 ps
CPU time 6.94 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:46:17 PM PDT 24
Peak memory 198788 kb
Host smart-f78d2f71-c1bd-4311-a2aa-b405fdb28843
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2973341390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2973341390
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2580835851
Short name T390
Test name
Test status
Simulation time 52198983297 ps
CPU time 93.32 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:47:44 PM PDT 24
Peak memory 200320 kb
Host smart-7b296aa3-c644-49e3-b3dc-c8ec2c2a2e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580835851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2580835851
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.248792967
Short name T1016
Test name
Test status
Simulation time 2952631248 ps
CPU time 1.95 seconds
Started May 23 12:46:10 PM PDT 24
Finished May 23 12:46:13 PM PDT 24
Peak memory 196240 kb
Host smart-245bc273-627c-4a5f-a236-ea95d4825b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248792967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.248792967
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2133803109
Short name T283
Test name
Test status
Simulation time 6331686207 ps
CPU time 20.31 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:46:31 PM PDT 24
Peak memory 199628 kb
Host smart-fb735866-e5f0-414e-b473-73e20274dac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133803109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2133803109
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.4013299694
Short name T558
Test name
Test status
Simulation time 36781464826 ps
CPU time 61.83 seconds
Started May 23 12:46:10 PM PDT 24
Finished May 23 12:47:14 PM PDT 24
Peak memory 200372 kb
Host smart-dcaf5437-d2c0-4314-9e13-399a717b0610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013299694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.4013299694
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3665031573
Short name T323
Test name
Test status
Simulation time 72602190070 ps
CPU time 349.5 seconds
Started May 23 12:46:10 PM PDT 24
Finished May 23 12:52:02 PM PDT 24
Peak memory 208668 kb
Host smart-8936b11d-4ed9-410c-bc97-50f4d339fb8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665031573 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3665031573
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1874379483
Short name T314
Test name
Test status
Simulation time 14193439082 ps
CPU time 14.97 seconds
Started May 23 12:46:11 PM PDT 24
Finished May 23 12:46:28 PM PDT 24
Peak memory 200264 kb
Host smart-13c4fbbb-8e49-4986-8594-9f770683a72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874379483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1874379483
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1419554726
Short name T536
Test name
Test status
Simulation time 36644210063 ps
CPU time 56.26 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:47:07 PM PDT 24
Peak memory 200224 kb
Host smart-f5319be2-ec57-46a9-9d57-bb0b677f2460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419554726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1419554726
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3948540566
Short name T1003
Test name
Test status
Simulation time 11547285 ps
CPU time 0.57 seconds
Started May 23 12:46:12 PM PDT 24
Finished May 23 12:46:14 PM PDT 24
Peak memory 195800 kb
Host smart-12b97470-cd0a-4bac-aae8-e667485c5032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948540566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3948540566
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.296876035
Short name T288
Test name
Test status
Simulation time 33260772614 ps
CPU time 60.61 seconds
Started May 23 12:46:11 PM PDT 24
Finished May 23 12:47:13 PM PDT 24
Peak memory 200496 kb
Host smart-bc677a6c-3b98-4ca6-846e-ea06dbbb4486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296876035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.296876035
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.18425242
Short name T673
Test name
Test status
Simulation time 101813397270 ps
CPU time 210.38 seconds
Started May 23 12:46:12 PM PDT 24
Finished May 23 12:49:44 PM PDT 24
Peak memory 200336 kb
Host smart-6f45e223-c8eb-45c3-98d3-55c5bb80a61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18425242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.18425242
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2992207428
Short name T830
Test name
Test status
Simulation time 181220392940 ps
CPU time 81.56 seconds
Started May 23 12:46:10 PM PDT 24
Finished May 23 12:47:33 PM PDT 24
Peak memory 200324 kb
Host smart-eef41a02-b6d3-4487-b897-3193bf9967b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992207428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2992207428
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2144638846
Short name T411
Test name
Test status
Simulation time 3185040331 ps
CPU time 2.96 seconds
Started May 23 12:46:10 PM PDT 24
Finished May 23 12:46:15 PM PDT 24
Peak memory 196224 kb
Host smart-d205436b-286a-4068-b69d-101de854b2b0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144638846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2144638846
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.850882655
Short name T931
Test name
Test status
Simulation time 143645710003 ps
CPU time 685.08 seconds
Started May 23 12:46:12 PM PDT 24
Finished May 23 12:57:39 PM PDT 24
Peak memory 200384 kb
Host smart-82186809-13fd-42df-aced-46b3b74de7a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=850882655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.850882655
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2110167601
Short name T524
Test name
Test status
Simulation time 1704980902 ps
CPU time 1.42 seconds
Started May 23 12:46:12 PM PDT 24
Finished May 23 12:46:15 PM PDT 24
Peak memory 195804 kb
Host smart-2e766b71-1708-4dd0-811f-7306ba7634c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110167601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2110167601
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1020314990
Short name T393
Test name
Test status
Simulation time 179538244674 ps
CPU time 51.72 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:47:02 PM PDT 24
Peak memory 208732 kb
Host smart-a608891c-e830-48e1-8dbd-1f73a1253a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020314990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1020314990
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.908378005
Short name T318
Test name
Test status
Simulation time 4504411618 ps
CPU time 55.59 seconds
Started May 23 12:46:14 PM PDT 24
Finished May 23 12:47:11 PM PDT 24
Peak memory 200448 kb
Host smart-ba102061-4177-4ef3-96ce-5c4d6ce914d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=908378005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.908378005
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3576522949
Short name T3
Test name
Test status
Simulation time 5279783599 ps
CPU time 11.32 seconds
Started May 23 12:46:10 PM PDT 24
Finished May 23 12:46:23 PM PDT 24
Peak memory 199580 kb
Host smart-8253b926-af6e-42f8-81ec-fa6592cdd443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576522949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3576522949
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3857418197
Short name T461
Test name
Test status
Simulation time 29387846738 ps
CPU time 27.35 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:46:38 PM PDT 24
Peak memory 200268 kb
Host smart-2fbd79c1-2bda-4349-919c-e301c491a655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857418197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3857418197
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1323542797
Short name T625
Test name
Test status
Simulation time 4671092375 ps
CPU time 2.87 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:46:13 PM PDT 24
Peak memory 196304 kb
Host smart-1be333f2-eb45-4895-861c-f6324ee121ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323542797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1323542797
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3727703855
Short name T913
Test name
Test status
Simulation time 275258604 ps
CPU time 1.31 seconds
Started May 23 12:46:13 PM PDT 24
Finished May 23 12:46:16 PM PDT 24
Peak memory 199100 kb
Host smart-f1d18292-0db0-4256-9028-38344a50b95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727703855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3727703855
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3037773968
Short name T260
Test name
Test status
Simulation time 127160691670 ps
CPU time 23.9 seconds
Started May 23 12:46:11 PM PDT 24
Finished May 23 12:46:37 PM PDT 24
Peak memory 200356 kb
Host smart-b9e08c9f-5934-4b6a-ab2b-379323ac9822
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037773968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3037773968
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1534346003
Short name T1144
Test name
Test status
Simulation time 34628525272 ps
CPU time 402.05 seconds
Started May 23 12:46:13 PM PDT 24
Finished May 23 12:52:57 PM PDT 24
Peak memory 215300 kb
Host smart-16524051-d3ec-4170-8d26-991323ce8e7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534346003 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1534346003
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3246372164
Short name T737
Test name
Test status
Simulation time 960741091 ps
CPU time 2.39 seconds
Started May 23 12:46:10 PM PDT 24
Finished May 23 12:46:14 PM PDT 24
Peak memory 199012 kb
Host smart-6e8f3be5-b2d7-4c42-88d2-dd6dfa404d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246372164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3246372164
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2473845544
Short name T802
Test name
Test status
Simulation time 94299392863 ps
CPU time 28.42 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:46:39 PM PDT 24
Peak memory 200188 kb
Host smart-5aa4ef91-9aa4-4778-a07c-1484a4d7e20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473845544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2473845544
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.623035789
Short name T426
Test name
Test status
Simulation time 22869343 ps
CPU time 0.56 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:46:10 PM PDT 24
Peak memory 195200 kb
Host smart-f2a0d547-57d6-4a54-ac6e-f84463829b23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623035789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.623035789
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2040115339
Short name T1044
Test name
Test status
Simulation time 171787340036 ps
CPU time 80.28 seconds
Started May 23 12:46:13 PM PDT 24
Finished May 23 12:47:34 PM PDT 24
Peak memory 200300 kb
Host smart-7fea5c7f-1992-4ec6-8810-429582f61bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040115339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2040115339
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3323047501
Short name T1105
Test name
Test status
Simulation time 134887237401 ps
CPU time 58.48 seconds
Started May 23 12:46:11 PM PDT 24
Finished May 23 12:47:11 PM PDT 24
Peak memory 200292 kb
Host smart-ee8e17d7-7f01-4272-a656-340c9f6aaab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323047501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3323047501
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2100820867
Short name T132
Test name
Test status
Simulation time 140528798322 ps
CPU time 72.3 seconds
Started May 23 12:46:10 PM PDT 24
Finished May 23 12:47:24 PM PDT 24
Peak memory 200408 kb
Host smart-dc8ff836-d579-43fe-b751-8fd555ac401d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100820867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2100820867
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1091757612
Short name T465
Test name
Test status
Simulation time 17554907192 ps
CPU time 20.12 seconds
Started May 23 12:46:13 PM PDT 24
Finished May 23 12:46:35 PM PDT 24
Peak memory 198672 kb
Host smart-885cc89a-e6ca-4293-8207-be93039c46ae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091757612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1091757612
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3512470417
Short name T605
Test name
Test status
Simulation time 116143177519 ps
CPU time 830.98 seconds
Started May 23 12:46:10 PM PDT 24
Finished May 23 01:00:02 PM PDT 24
Peak memory 200388 kb
Host smart-55bfd627-a1f5-4040-ad27-e67b18cb35a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3512470417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3512470417
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3221220966
Short name T533
Test name
Test status
Simulation time 2784072536 ps
CPU time 5.16 seconds
Started May 23 12:46:11 PM PDT 24
Finished May 23 12:46:18 PM PDT 24
Peak memory 197780 kb
Host smart-641d682e-8f5e-49f1-844d-23f545ab9560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221220966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3221220966
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.443559987
Short name T69
Test name
Test status
Simulation time 100352640708 ps
CPU time 223.82 seconds
Started May 23 12:46:11 PM PDT 24
Finished May 23 12:49:56 PM PDT 24
Peak memory 200660 kb
Host smart-63c2fbc5-da0a-4b66-adb5-0e168925b12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443559987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.443559987
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2233303603
Short name T732
Test name
Test status
Simulation time 9309385220 ps
CPU time 34.78 seconds
Started May 23 12:46:10 PM PDT 24
Finished May 23 12:46:46 PM PDT 24
Peak memory 200396 kb
Host smart-2db0286d-5580-4ee3-a7e1-091a3f7626d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2233303603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2233303603
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.37216125
Short name T337
Test name
Test status
Simulation time 7449695657 ps
CPU time 31.8 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:46:42 PM PDT 24
Peak memory 198416 kb
Host smart-c022af71-0dfd-407c-a1ea-ab7dae4e15ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37216125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.37216125
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1605391028
Short name T696
Test name
Test status
Simulation time 89498997672 ps
CPU time 136.88 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:48:28 PM PDT 24
Peak memory 199804 kb
Host smart-e1c4ee00-6c94-4fdf-ab00-96a822bb444c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605391028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1605391028
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.198548954
Short name T654
Test name
Test status
Simulation time 483326340 ps
CPU time 1.32 seconds
Started May 23 12:46:10 PM PDT 24
Finished May 23 12:46:13 PM PDT 24
Peak memory 195800 kb
Host smart-1023938d-4aff-463f-a240-9bc98a66e681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198548954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.198548954
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3448683188
Short name T327
Test name
Test status
Simulation time 11588258350 ps
CPU time 16.29 seconds
Started May 23 12:46:09 PM PDT 24
Finished May 23 12:46:28 PM PDT 24
Peak memory 199880 kb
Host smart-0bee4ca0-2d96-4fd7-948f-d9864a1f2f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448683188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3448683188
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.427671121
Short name T494
Test name
Test status
Simulation time 594459951650 ps
CPU time 98.33 seconds
Started May 23 12:46:12 PM PDT 24
Finished May 23 12:47:52 PM PDT 24
Peak memory 209072 kb
Host smart-9dd552fa-75b8-46e1-8498-7a727612a7b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427671121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.427671121
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3876333687
Short name T30
Test name
Test status
Simulation time 37570945196 ps
CPU time 1117.8 seconds
Started May 23 12:46:13 PM PDT 24
Finished May 23 01:04:52 PM PDT 24
Peak memory 217116 kb
Host smart-ea647452-7293-46db-99d2-825dda054e0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876333687 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3876333687
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2273615460
Short name T856
Test name
Test status
Simulation time 847074913 ps
CPU time 1.55 seconds
Started May 23 12:46:11 PM PDT 24
Finished May 23 12:46:14 PM PDT 24
Peak memory 200036 kb
Host smart-0bd428d3-d931-414f-a76f-b01647f9aa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273615460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2273615460
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3763800191
Short name T485
Test name
Test status
Simulation time 54774168427 ps
CPU time 176.76 seconds
Started May 23 12:46:11 PM PDT 24
Finished May 23 12:49:10 PM PDT 24
Peak memory 200332 kb
Host smart-1ba1c1f1-b02d-47a0-8d4d-c94f9d16c285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763800191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3763800191
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3667301072
Short name T1035
Test name
Test status
Simulation time 11709358 ps
CPU time 0.55 seconds
Started May 23 12:46:21 PM PDT 24
Finished May 23 12:46:23 PM PDT 24
Peak memory 195744 kb
Host smart-4d830dc3-90cf-41f1-8be3-36e07101dee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667301072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3667301072
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.549573361
Short name T921
Test name
Test status
Simulation time 33287011882 ps
CPU time 56.29 seconds
Started May 23 12:46:13 PM PDT 24
Finished May 23 12:47:11 PM PDT 24
Peak memory 200400 kb
Host smart-58036172-dfe7-46d8-bbf9-d9e1895a74f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549573361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.549573361
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1553822275
Short name T577
Test name
Test status
Simulation time 76034010427 ps
CPU time 34.25 seconds
Started May 23 12:46:11 PM PDT 24
Finished May 23 12:46:47 PM PDT 24
Peak memory 200268 kb
Host smart-cc5fb319-e0ff-4939-9903-bb65d36bcf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553822275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1553822275
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2243569150
Short name T345
Test name
Test status
Simulation time 49208326040 ps
CPU time 20.34 seconds
Started May 23 12:46:21 PM PDT 24
Finished May 23 12:46:43 PM PDT 24
Peak memory 200016 kb
Host smart-05aede87-4af9-4abc-9d7d-2594b69bdca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243569150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2243569150
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.845724463
Short name T1162
Test name
Test status
Simulation time 42346124622 ps
CPU time 16.71 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:46:41 PM PDT 24
Peak memory 200432 kb
Host smart-2222dc02-60ee-4daf-9d92-7f8f2df3e0e0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845724463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.845724463
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1780956337
Short name T849
Test name
Test status
Simulation time 50766019484 ps
CPU time 72.6 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:47:38 PM PDT 24
Peak memory 200488 kb
Host smart-39127b27-ca34-4afe-b08f-241eb829b25a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1780956337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1780956337
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.184512731
Short name T520
Test name
Test status
Simulation time 101419470 ps
CPU time 0.98 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:46:24 PM PDT 24
Peak memory 198676 kb
Host smart-6ba416fc-27a3-4bb7-8b40-dd69e0ef58a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184512731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.184512731
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1500297101
Short name T383
Test name
Test status
Simulation time 37109011462 ps
CPU time 18.67 seconds
Started May 23 12:46:24 PM PDT 24
Finished May 23 12:46:45 PM PDT 24
Peak memory 200620 kb
Host smart-a2d5498b-b3d4-43d5-a82c-15780da31e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500297101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1500297101
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.417010905
Short name T908
Test name
Test status
Simulation time 32665755727 ps
CPU time 1834.5 seconds
Started May 23 12:46:27 PM PDT 24
Finished May 23 01:17:03 PM PDT 24
Peak memory 200448 kb
Host smart-ae90c2f0-cc48-45fc-b0b3-d1de3c73e3e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=417010905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.417010905
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3432290080
Short name T439
Test name
Test status
Simulation time 6433333606 ps
CPU time 11.19 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:46:36 PM PDT 24
Peak memory 198764 kb
Host smart-51ec33f2-837c-4f09-b279-9e96c1f8e1a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3432290080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3432290080
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.481016574
Short name T901
Test name
Test status
Simulation time 31615635126 ps
CPU time 52.84 seconds
Started May 23 12:46:21 PM PDT 24
Finished May 23 12:47:15 PM PDT 24
Peak memory 200204 kb
Host smart-ab66feea-2aa6-4f6b-8314-2b5b4624344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481016574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.481016574
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1449301287
Short name T570
Test name
Test status
Simulation time 3328653303 ps
CPU time 0.98 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:46:25 PM PDT 24
Peak memory 196644 kb
Host smart-3d5ab7bd-0247-43be-b70d-0ddab435554c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449301287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1449301287
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2409255372
Short name T409
Test name
Test status
Simulation time 5458924781 ps
CPU time 10.41 seconds
Started May 23 12:46:10 PM PDT 24
Finished May 23 12:46:23 PM PDT 24
Peak memory 200152 kb
Host smart-4c0f482a-b04e-49f6-a8ac-0a095a357d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409255372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2409255372
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2351912853
Short name T958
Test name
Test status
Simulation time 175430329038 ps
CPU time 120.51 seconds
Started May 23 12:46:24 PM PDT 24
Finished May 23 12:48:27 PM PDT 24
Peak memory 200332 kb
Host smart-fe98ad14-d77a-4d70-9613-e7140c972221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351912853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2351912853
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2460248944
Short name T862
Test name
Test status
Simulation time 9924045127 ps
CPU time 93.19 seconds
Started May 23 12:46:21 PM PDT 24
Finished May 23 12:47:56 PM PDT 24
Peak memory 216260 kb
Host smart-634d4449-9183-4286-9a32-8cbb76502036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460248944 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2460248944
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2894005205
Short name T617
Test name
Test status
Simulation time 542227213 ps
CPU time 2.39 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:46:27 PM PDT 24
Peak memory 198796 kb
Host smart-1e82d4b5-7110-4d0d-bc04-2f3b66899a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894005205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2894005205
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2601275822
Short name T942
Test name
Test status
Simulation time 48857806424 ps
CPU time 45.37 seconds
Started May 23 12:46:14 PM PDT 24
Finished May 23 12:47:01 PM PDT 24
Peak memory 200204 kb
Host smart-069e6925-6ceb-40c3-9b6b-3d8e5ce2ac7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601275822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2601275822
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1260665950
Short name T49
Test name
Test status
Simulation time 26340313 ps
CPU time 0.52 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:46:26 PM PDT 24
Peak memory 194732 kb
Host smart-20d8925b-7e56-410a-a6c9-aeeadc45e546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260665950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1260665950
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1746545328
Short name T1086
Test name
Test status
Simulation time 20894627289 ps
CPU time 10.41 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:46:35 PM PDT 24
Peak memory 200424 kb
Host smart-49ca3ef4-44b8-4df9-9ee0-123855e9ee29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746545328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1746545328
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.147484285
Short name T1047
Test name
Test status
Simulation time 150368824076 ps
CPU time 129.78 seconds
Started May 23 12:46:24 PM PDT 24
Finished May 23 12:48:36 PM PDT 24
Peak memory 200400 kb
Host smart-bf72292b-76e3-4248-a09a-48dbffe39ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147484285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.147484285
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1527472239
Short name T145
Test name
Test status
Simulation time 29315254852 ps
CPU time 31.58 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:46:55 PM PDT 24
Peak memory 200456 kb
Host smart-87ed2397-5784-4fa7-a73f-e8af1e086adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527472239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1527472239
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.4201821971
Short name T976
Test name
Test status
Simulation time 21643775866 ps
CPU time 31.89 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:46:56 PM PDT 24
Peak memory 198876 kb
Host smart-8998b563-5e6e-4057-8bed-327891c8da1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201821971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.4201821971
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_loopback.4270323120
Short name T602
Test name
Test status
Simulation time 4123806204 ps
CPU time 8.66 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:46:34 PM PDT 24
Peak memory 199116 kb
Host smart-36b76e65-6030-48d0-b845-75d2458bc323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270323120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.4270323120
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.760745508
Short name T1002
Test name
Test status
Simulation time 90383623632 ps
CPU time 61.13 seconds
Started May 23 12:46:21 PM PDT 24
Finished May 23 12:47:24 PM PDT 24
Peak memory 200172 kb
Host smart-13fa067f-b225-4869-9784-a8b7a157e750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760745508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.760745508
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1377070611
Short name T292
Test name
Test status
Simulation time 4876159048 ps
CPU time 226.87 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:50:11 PM PDT 24
Peak memory 200392 kb
Host smart-a01fcb8a-b28d-4ee4-a367-48732df88b0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1377070611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1377070611
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2392332323
Short name T361
Test name
Test status
Simulation time 1377258649 ps
CPU time 6.12 seconds
Started May 23 12:46:21 PM PDT 24
Finished May 23 12:46:28 PM PDT 24
Peak memory 198396 kb
Host smart-9e1ec30d-beee-448a-b0f6-3ce34d5e45ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392332323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2392332323
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3309629971
Short name T728
Test name
Test status
Simulation time 70298000590 ps
CPU time 44.64 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:47:11 PM PDT 24
Peak memory 200392 kb
Host smart-e0bbe8c6-01fa-4c0b-b89b-3b65d9956f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309629971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3309629971
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2711986188
Short name T961
Test name
Test status
Simulation time 4058976220 ps
CPU time 7.06 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:46:32 PM PDT 24
Peak memory 196456 kb
Host smart-efebab5e-e234-41da-af5b-94a9840a90c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711986188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2711986188
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2332321618
Short name T1005
Test name
Test status
Simulation time 293206471 ps
CPU time 1.36 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:46:26 PM PDT 24
Peak memory 199044 kb
Host smart-3776aaf0-7cf6-451f-b2f6-ca7004746ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332321618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2332321618
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.244170750
Short name T1111
Test name
Test status
Simulation time 224116803447 ps
CPU time 1588.91 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 01:12:54 PM PDT 24
Peak memory 200476 kb
Host smart-47f7a1a9-0def-40e2-b741-f44572d0f79a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244170750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.244170750
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1802843420
Short name T564
Test name
Test status
Simulation time 15022647446 ps
CPU time 198.8 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:49:45 PM PDT 24
Peak memory 215964 kb
Host smart-55a465b8-5513-4a71-9609-f0d446fdd500
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802843420 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1802843420
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.670522819
Short name T763
Test name
Test status
Simulation time 662929177 ps
CPU time 2.65 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:46:27 PM PDT 24
Peak memory 199460 kb
Host smart-aa3c76f0-0496-441a-96d9-7a699455c8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670522819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.670522819
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3792898238
Short name T433
Test name
Test status
Simulation time 216128635980 ps
CPU time 112.68 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:48:16 PM PDT 24
Peak memory 200380 kb
Host smart-6decb723-edc0-414d-8ceb-20b90d528b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792898238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3792898238
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2315857888
Short name T401
Test name
Test status
Simulation time 15069775 ps
CPU time 0.54 seconds
Started May 23 12:46:20 PM PDT 24
Finished May 23 12:46:21 PM PDT 24
Peak memory 195156 kb
Host smart-36a0917d-c295-408a-ac84-83a071582c61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315857888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2315857888
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1920777110
Short name T481
Test name
Test status
Simulation time 61311863694 ps
CPU time 82.39 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:47:48 PM PDT 24
Peak memory 200356 kb
Host smart-4a848e18-3f1d-4b96-be7f-ae52be3711c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920777110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1920777110
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1480668366
Short name T670
Test name
Test status
Simulation time 8147538783 ps
CPU time 40.07 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:47:03 PM PDT 24
Peak memory 200308 kb
Host smart-b765b5c8-015d-4745-a7cb-0bce8a151a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480668366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1480668366
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.811688655
Short name T161
Test name
Test status
Simulation time 139711351581 ps
CPU time 52.83 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:47:18 PM PDT 24
Peak memory 200412 kb
Host smart-a6d79afc-741f-4b9d-9298-be5c743d5af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811688655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.811688655
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1314365750
Short name T1138
Test name
Test status
Simulation time 145229971787 ps
CPU time 178.36 seconds
Started May 23 12:46:21 PM PDT 24
Finished May 23 12:49:20 PM PDT 24
Peak memory 198844 kb
Host smart-8be71f2a-d305-4724-960a-66c155fd613e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314365750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1314365750
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1907412089
Short name T571
Test name
Test status
Simulation time 101295274967 ps
CPU time 870.1 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 01:00:55 PM PDT 24
Peak memory 200380 kb
Host smart-91a5ab20-9982-4188-aaa2-da62cfe06a35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1907412089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1907412089
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.753536519
Short name T832
Test name
Test status
Simulation time 2505683227 ps
CPU time 8.36 seconds
Started May 23 12:46:21 PM PDT 24
Finished May 23 12:46:31 PM PDT 24
Peak memory 200240 kb
Host smart-ce3eb61b-0bc9-412b-a286-b37059014cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753536519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.753536519
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.305003522
Short name T743
Test name
Test status
Simulation time 66213835078 ps
CPU time 44.94 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:47:11 PM PDT 24
Peak memory 199748 kb
Host smart-66614f29-ef0a-4950-a949-fdcb63ddf16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305003522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.305003522
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.396492500
Short name T947
Test name
Test status
Simulation time 12987354565 ps
CPU time 167.42 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:49:11 PM PDT 24
Peak memory 200292 kb
Host smart-5814134a-fe72-4c92-85af-03cf1c784970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=396492500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.396492500
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.307584665
Short name T665
Test name
Test status
Simulation time 3097305944 ps
CPU time 6.44 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:46:32 PM PDT 24
Peak memory 199300 kb
Host smart-049ff328-8593-42fe-9039-8b86518adee6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=307584665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.307584665
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2885826200
Short name T615
Test name
Test status
Simulation time 174145890744 ps
CPU time 28.52 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:46:54 PM PDT 24
Peak memory 200512 kb
Host smart-bed08fde-1e9d-4885-b18d-42c70eebb017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885826200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2885826200
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3264510381
Short name T466
Test name
Test status
Simulation time 2954201615 ps
CPU time 5.22 seconds
Started May 23 12:46:26 PM PDT 24
Finished May 23 12:46:33 PM PDT 24
Peak memory 196256 kb
Host smart-67447700-02c2-4312-b92c-903f2cd3f821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264510381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3264510381
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1526528541
Short name T1175
Test name
Test status
Simulation time 910131086 ps
CPU time 1.55 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:46:25 PM PDT 24
Peak memory 198644 kb
Host smart-ad926c28-ae01-4be0-8361-50e08a626715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526528541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1526528541
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3732537978
Short name T266
Test name
Test status
Simulation time 163516476293 ps
CPU time 901.7 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 01:01:28 PM PDT 24
Peak memory 208924 kb
Host smart-447f0195-904c-449d-aa3b-f3cbc979c5c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732537978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3732537978
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3066442590
Short name T1077
Test name
Test status
Simulation time 69765653035 ps
CPU time 719.77 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:58:26 PM PDT 24
Peak memory 216112 kb
Host smart-37c622d5-5d42-402c-a085-ddc9b4dd8516
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066442590 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3066442590
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3379618514
Short name T1061
Test name
Test status
Simulation time 1230119162 ps
CPU time 2.66 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:46:29 PM PDT 24
Peak memory 199708 kb
Host smart-1234f903-e23d-43c0-983a-cbf672c0b899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379618514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3379618514
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1684259510
Short name T319
Test name
Test status
Simulation time 52655099202 ps
CPU time 77.93 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:47:43 PM PDT 24
Peak memory 200404 kb
Host smart-5aa37611-b9ca-4ce1-b84a-cc4bb604b6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684259510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1684259510
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3273206500
Short name T1009
Test name
Test status
Simulation time 22138459 ps
CPU time 0.54 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 12:46:39 PM PDT 24
Peak memory 194820 kb
Host smart-537f5610-36f1-4191-a900-592625c106ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273206500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3273206500
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2503963254
Short name T917
Test name
Test status
Simulation time 38549973587 ps
CPU time 18.36 seconds
Started May 23 12:46:24 PM PDT 24
Finished May 23 12:46:45 PM PDT 24
Peak memory 200432 kb
Host smart-42bcb709-04fb-4f00-b3fe-82984a9d471e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503963254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2503963254
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1105733908
Short name T334
Test name
Test status
Simulation time 107784199556 ps
CPU time 122.37 seconds
Started May 23 12:46:24 PM PDT 24
Finished May 23 12:48:29 PM PDT 24
Peak memory 200332 kb
Host smart-4f05bac4-ba39-4336-a59b-1162a97bcefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105733908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1105733908
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.404892482
Short name T565
Test name
Test status
Simulation time 13684176335 ps
CPU time 7.61 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:46:32 PM PDT 24
Peak memory 200348 kb
Host smart-dab05996-d7f4-4401-9394-a049a095e895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404892482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.404892482
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3427430637
Short name T956
Test name
Test status
Simulation time 91351329746 ps
CPU time 39.34 seconds
Started May 23 12:46:25 PM PDT 24
Finished May 23 12:47:06 PM PDT 24
Peak memory 200320 kb
Host smart-b35dad05-685e-4eb4-bb84-003a575dacd3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427430637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3427430637
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.4239582346
Short name T301
Test name
Test status
Simulation time 103665914875 ps
CPU time 338.5 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 12:52:16 PM PDT 24
Peak memory 200420 kb
Host smart-317c5caf-4fea-4516-8fe4-efbf911bb2d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4239582346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.4239582346
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.38863192
Short name T475
Test name
Test status
Simulation time 9658655940 ps
CPU time 8.66 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:46:34 PM PDT 24
Peak memory 200268 kb
Host smart-c8022540-bf17-4b0b-8227-91626ae9a3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38863192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.38863192
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2776540830
Short name T616
Test name
Test status
Simulation time 92131487719 ps
CPU time 180.35 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:49:26 PM PDT 24
Peak memory 200148 kb
Host smart-64f8e8bc-2d6e-47e2-b39b-faf657938629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776540830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2776540830
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3179629196
Short name T282
Test name
Test status
Simulation time 28142489680 ps
CPU time 154.45 seconds
Started May 23 12:46:34 PM PDT 24
Finished May 23 12:49:10 PM PDT 24
Peak memory 200304 kb
Host smart-13b30a47-3545-409b-8a61-71b1397b7a8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179629196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3179629196
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2734723037
Short name T999
Test name
Test status
Simulation time 4850089411 ps
CPU time 37.44 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:47:03 PM PDT 24
Peak memory 199588 kb
Host smart-5c06ef5c-f4ef-40f9-92cb-8495b7240a3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734723037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2734723037
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1055146975
Short name T312
Test name
Test status
Simulation time 155774281301 ps
CPU time 52.22 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:47:17 PM PDT 24
Peak memory 200392 kb
Host smart-35303f3a-436f-4a65-a12b-562dffe9b41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055146975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1055146975
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1829368367
Short name T1100
Test name
Test status
Simulation time 34483268649 ps
CPU time 24.79 seconds
Started May 23 12:46:26 PM PDT 24
Finished May 23 12:46:52 PM PDT 24
Peak memory 196748 kb
Host smart-6ad9b72b-4bfb-4b9d-a99e-ff407f593f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829368367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1829368367
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.787130698
Short name T407
Test name
Test status
Simulation time 5815885127 ps
CPU time 10.28 seconds
Started May 23 12:46:21 PM PDT 24
Finished May 23 12:46:32 PM PDT 24
Peak memory 199596 kb
Host smart-5c8209ec-c9c5-4f71-86ab-31667815ce76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787130698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.787130698
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2397024293
Short name T1139
Test name
Test status
Simulation time 290897022961 ps
CPU time 346.1 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 12:52:25 PM PDT 24
Peak memory 212320 kb
Host smart-d009db89-1131-4f9e-adc4-858a0415aba9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397024293 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2397024293
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2741875725
Short name T903
Test name
Test status
Simulation time 6494570166 ps
CPU time 22.21 seconds
Started May 23 12:46:23 PM PDT 24
Finished May 23 12:46:47 PM PDT 24
Peak memory 199700 kb
Host smart-3a500f37-8389-45d5-a2df-a89efe8a6bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741875725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2741875725
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2839436337
Short name T963
Test name
Test status
Simulation time 56955769523 ps
CPU time 53.03 seconds
Started May 23 12:46:22 PM PDT 24
Finished May 23 12:47:17 PM PDT 24
Peak memory 200312 kb
Host smart-ffdc9fb1-14d4-4657-ae6a-62e2dca38368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839436337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2839436337
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2059559302
Short name T940
Test name
Test status
Simulation time 14821594 ps
CPU time 0.56 seconds
Started May 23 12:46:35 PM PDT 24
Finished May 23 12:46:37 PM PDT 24
Peak memory 195748 kb
Host smart-72f3fb58-6e54-44a1-8ce3-f8bdbd5159d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059559302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2059559302
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3496850624
Short name T943
Test name
Test status
Simulation time 55741033458 ps
CPU time 98.55 seconds
Started May 23 12:46:33 PM PDT 24
Finished May 23 12:48:13 PM PDT 24
Peak memory 200340 kb
Host smart-b65760cb-ac6c-42e9-9d11-84db441ace42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496850624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3496850624
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2728985079
Short name T848
Test name
Test status
Simulation time 93760288171 ps
CPU time 168.2 seconds
Started May 23 12:46:34 PM PDT 24
Finished May 23 12:49:23 PM PDT 24
Peak memory 200320 kb
Host smart-de32fa6a-42a3-48cb-af9d-0e2c36ad3c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728985079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2728985079
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.261704648
Short name T186
Test name
Test status
Simulation time 55354443721 ps
CPU time 64.27 seconds
Started May 23 12:46:34 PM PDT 24
Finished May 23 12:47:40 PM PDT 24
Peak memory 200424 kb
Host smart-5b3d1740-5fbd-40bb-83ca-a1665c20bbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261704648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.261704648
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2724319549
Short name T587
Test name
Test status
Simulation time 15384043595 ps
CPU time 10.27 seconds
Started May 23 12:46:35 PM PDT 24
Finished May 23 12:46:46 PM PDT 24
Peak memory 200232 kb
Host smart-3f26d665-480d-4259-a799-e13acbcd16cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724319549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2724319549
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2637544238
Short name T850
Test name
Test status
Simulation time 142757919922 ps
CPU time 411.63 seconds
Started May 23 12:46:35 PM PDT 24
Finished May 23 12:53:28 PM PDT 24
Peak memory 200384 kb
Host smart-b800891a-bdca-46f7-b97d-f83a77695359
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637544238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2637544238
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2610452302
Short name T431
Test name
Test status
Simulation time 9063002920 ps
CPU time 3.12 seconds
Started May 23 12:46:34 PM PDT 24
Finished May 23 12:46:39 PM PDT 24
Peak memory 200304 kb
Host smart-831c0daa-061c-44bc-8c20-4b1105065d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610452302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2610452302
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1168458879
Short name T969
Test name
Test status
Simulation time 122570297172 ps
CPU time 55.85 seconds
Started May 23 12:46:34 PM PDT 24
Finished May 23 12:47:32 PM PDT 24
Peak memory 208600 kb
Host smart-a55f6251-0e94-4cda-8e25-2971f89b9045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168458879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1168458879
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.979326431
Short name T1137
Test name
Test status
Simulation time 8525984295 ps
CPU time 491.49 seconds
Started May 23 12:46:34 PM PDT 24
Finished May 23 12:54:46 PM PDT 24
Peak memory 200344 kb
Host smart-b8d5f95d-e044-4b61-8f59-cda74a245390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=979326431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.979326431
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.983754559
Short name T550
Test name
Test status
Simulation time 7521678899 ps
CPU time 3.9 seconds
Started May 23 12:46:37 PM PDT 24
Finished May 23 12:46:43 PM PDT 24
Peak memory 200264 kb
Host smart-b1e03e8d-6bc7-4f84-991f-d4f2b528d00b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983754559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.983754559
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1964113805
Short name T890
Test name
Test status
Simulation time 64192235083 ps
CPU time 107.46 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 12:48:25 PM PDT 24
Peak memory 200416 kb
Host smart-85505c1a-ca18-4466-abda-4ba10a021db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964113805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1964113805
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3278508806
Short name T364
Test name
Test status
Simulation time 42851840847 ps
CPU time 76.5 seconds
Started May 23 12:46:34 PM PDT 24
Finished May 23 12:47:52 PM PDT 24
Peak memory 196068 kb
Host smart-6d76c066-5193-40ce-a528-75a1e66ca121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278508806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3278508806
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1500624526
Short name T317
Test name
Test status
Simulation time 5489714214 ps
CPU time 8.49 seconds
Started May 23 12:46:34 PM PDT 24
Finished May 23 12:46:44 PM PDT 24
Peak memory 200348 kb
Host smart-564ff1e5-5bda-4317-a96d-c2d9a7798904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500624526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1500624526
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1734990875
Short name T882
Test name
Test status
Simulation time 288763097071 ps
CPU time 1508.35 seconds
Started May 23 12:46:35 PM PDT 24
Finished May 23 01:11:45 PM PDT 24
Peak memory 200484 kb
Host smart-5457767f-3621-4d8c-9221-e653c4e223e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734990875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1734990875
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3181489171
Short name T56
Test name
Test status
Simulation time 65987345667 ps
CPU time 530.01 seconds
Started May 23 12:46:35 PM PDT 24
Finished May 23 12:55:27 PM PDT 24
Peak memory 217164 kb
Host smart-ffd929e6-be4e-406b-80c5-c50aad3f8968
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181489171 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3181489171
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1629980751
Short name T548
Test name
Test status
Simulation time 1449779567 ps
CPU time 3.95 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 12:46:42 PM PDT 24
Peak memory 200108 kb
Host smart-41a02966-0aa4-4f2e-bc63-f35210ad585e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629980751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1629980751
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2000637802
Short name T106
Test name
Test status
Simulation time 89929139919 ps
CPU time 101.32 seconds
Started May 23 12:46:41 PM PDT 24
Finished May 23 12:48:24 PM PDT 24
Peak memory 200312 kb
Host smart-e0fcb027-b57a-4c14-aa0d-d799fbd0ca0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000637802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2000637802
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2319015485
Short name T766
Test name
Test status
Simulation time 33026478 ps
CPU time 0.54 seconds
Started May 23 12:46:38 PM PDT 24
Finished May 23 12:46:40 PM PDT 24
Peak memory 195332 kb
Host smart-841db000-5de7-404d-b142-562e25ff0519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319015485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2319015485
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3632064569
Short name T671
Test name
Test status
Simulation time 40978993437 ps
CPU time 87.54 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 12:48:05 PM PDT 24
Peak memory 200280 kb
Host smart-f3db853e-202f-4162-8ad9-2b5d483ad32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632064569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3632064569
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3348474021
Short name T1036
Test name
Test status
Simulation time 20753407728 ps
CPU time 35.04 seconds
Started May 23 12:46:35 PM PDT 24
Finished May 23 12:47:12 PM PDT 24
Peak memory 199780 kb
Host smart-55349e50-0334-4450-907b-6719ac10387f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348474021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3348474021
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.767245895
Short name T884
Test name
Test status
Simulation time 57464365347 ps
CPU time 93.86 seconds
Started May 23 12:46:35 PM PDT 24
Finished May 23 12:48:10 PM PDT 24
Peak memory 200348 kb
Host smart-8bb0b1c1-b1e7-432a-9f2c-f2b916d125e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767245895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.767245895
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1682120440
Short name T508
Test name
Test status
Simulation time 101406109818 ps
CPU time 421.66 seconds
Started May 23 12:46:35 PM PDT 24
Finished May 23 12:53:38 PM PDT 24
Peak memory 200408 kb
Host smart-09de397e-849c-4b1e-ae42-6c571c6b6fa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1682120440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1682120440
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1278310874
Short name T353
Test name
Test status
Simulation time 8363589800 ps
CPU time 16.2 seconds
Started May 23 12:46:35 PM PDT 24
Finished May 23 12:46:53 PM PDT 24
Peak memory 198872 kb
Host smart-c31ec562-0337-4e4f-9305-b862f711e90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278310874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1278310874
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3970258025
Short name T321
Test name
Test status
Simulation time 49758810111 ps
CPU time 18.49 seconds
Started May 23 12:46:40 PM PDT 24
Finished May 23 12:47:00 PM PDT 24
Peak memory 200664 kb
Host smart-21806f1e-69b5-4847-bbf2-1a279e878092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970258025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3970258025
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3192321757
Short name T842
Test name
Test status
Simulation time 29705394044 ps
CPU time 1357.46 seconds
Started May 23 12:46:34 PM PDT 24
Finished May 23 01:09:12 PM PDT 24
Peak memory 200392 kb
Host smart-c8fa21f9-5697-42dd-92b3-72101c7931b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3192321757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3192321757
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1121572657
Short name T941
Test name
Test status
Simulation time 4315393740 ps
CPU time 36.62 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 12:47:14 PM PDT 24
Peak memory 198592 kb
Host smart-fa3ecb10-800b-43ce-92b9-59d65f7fe577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121572657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1121572657
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2006240477
Short name T704
Test name
Test status
Simulation time 23923538168 ps
CPU time 19.09 seconds
Started May 23 12:46:34 PM PDT 24
Finished May 23 12:46:54 PM PDT 24
Peak memory 198888 kb
Host smart-e60df01c-5ae1-4b8a-9af9-851297e4f071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006240477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2006240477
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3039693740
Short name T304
Test name
Test status
Simulation time 40384559161 ps
CPU time 57.97 seconds
Started May 23 12:46:34 PM PDT 24
Finished May 23 12:47:34 PM PDT 24
Peak memory 196184 kb
Host smart-ed4d6912-bc8a-44d3-91ce-9a167640cd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039693740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3039693740
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.403827236
Short name T718
Test name
Test status
Simulation time 535270724 ps
CPU time 2.2 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 12:46:39 PM PDT 24
Peak memory 199240 kb
Host smart-501386ab-27e2-46fe-b824-40a6bbc22c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403827236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.403827236
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1388286463
Short name T923
Test name
Test status
Simulation time 212538615206 ps
CPU time 149.98 seconds
Started May 23 12:46:37 PM PDT 24
Finished May 23 12:49:09 PM PDT 24
Peak memory 200496 kb
Host smart-af47bb8b-9d66-4cf3-8267-96e8c4aa766e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388286463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1388286463
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2290223473
Short name T1104
Test name
Test status
Simulation time 390671864203 ps
CPU time 536.07 seconds
Started May 23 12:46:37 PM PDT 24
Finished May 23 12:55:35 PM PDT 24
Peak memory 217004 kb
Host smart-814040ea-84c9-474c-b917-f6cf22182dc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290223473 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2290223473
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1159471128
Short name T539
Test name
Test status
Simulation time 945138328 ps
CPU time 1.89 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 12:46:40 PM PDT 24
Peak memory 198788 kb
Host smart-3bf10fe7-53d4-4149-97bb-598dbb745cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159471128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1159471128
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2626143194
Short name T297
Test name
Test status
Simulation time 55772525374 ps
CPU time 26.85 seconds
Started May 23 12:46:33 PM PDT 24
Finished May 23 12:47:01 PM PDT 24
Peak memory 200348 kb
Host smart-cd22a368-a91a-40d9-bc78-6df9c40b4646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626143194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2626143194
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1504266467
Short name T992
Test name
Test status
Simulation time 12726901 ps
CPU time 0.56 seconds
Started May 23 12:43:59 PM PDT 24
Finished May 23 12:44:01 PM PDT 24
Peak memory 195736 kb
Host smart-92a699a7-0520-478d-ada0-ad3f27ef8b4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504266467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1504266467
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1006745462
Short name T788
Test name
Test status
Simulation time 53795385018 ps
CPU time 100.89 seconds
Started May 23 12:44:10 PM PDT 24
Finished May 23 12:45:53 PM PDT 24
Peak memory 200384 kb
Host smart-bdf49a72-d557-4ddf-9ab3-cd230d1510c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006745462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1006745462
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3491690201
Short name T691
Test name
Test status
Simulation time 26873216611 ps
CPU time 37.32 seconds
Started May 23 12:43:56 PM PDT 24
Finished May 23 12:44:35 PM PDT 24
Peak memory 200452 kb
Host smart-a37e1f73-d3db-46f9-94f8-6c290dc9a45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491690201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3491690201
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3532607318
Short name T204
Test name
Test status
Simulation time 80620560666 ps
CPU time 133.03 seconds
Started May 23 12:44:13 PM PDT 24
Finished May 23 12:46:27 PM PDT 24
Peak memory 200356 kb
Host smart-2c63d205-4de1-473c-bee9-00c4ce705626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532607318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3532607318
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3380447704
Short name T572
Test name
Test status
Simulation time 10745507658 ps
CPU time 9.69 seconds
Started May 23 12:43:59 PM PDT 24
Finished May 23 12:44:10 PM PDT 24
Peak memory 197296 kb
Host smart-2a8e16a8-a34b-4607-bd05-88f4d8a14571
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380447704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3380447704
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.186992238
Short name T1023
Test name
Test status
Simulation time 128756292894 ps
CPU time 327.98 seconds
Started May 23 12:43:56 PM PDT 24
Finished May 23 12:49:26 PM PDT 24
Peak memory 200448 kb
Host smart-a372cce5-fd76-4817-ab9f-c20d95eafb40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=186992238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.186992238
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2487652423
Short name T1083
Test name
Test status
Simulation time 12440731150 ps
CPU time 12.27 seconds
Started May 23 12:43:56 PM PDT 24
Finished May 23 12:44:09 PM PDT 24
Peak memory 199936 kb
Host smart-b0d39b25-4ecc-4594-8e81-84777548dd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487652423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2487652423
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3864775676
Short name T1108
Test name
Test status
Simulation time 147261199082 ps
CPU time 87.72 seconds
Started May 23 12:44:13 PM PDT 24
Finished May 23 12:45:42 PM PDT 24
Peak memory 200444 kb
Host smart-24dcadb0-e706-4ff2-b4da-01fd82084ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864775676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3864775676
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2657917420
Short name T101
Test name
Test status
Simulation time 8858206442 ps
CPU time 25.88 seconds
Started May 23 12:44:14 PM PDT 24
Finished May 23 12:44:42 PM PDT 24
Peak memory 200396 kb
Host smart-67d3220f-031c-4987-8b75-7c1832d07d0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2657917420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2657917420
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2692798854
Short name T446
Test name
Test status
Simulation time 4359185473 ps
CPU time 11 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 12:44:10 PM PDT 24
Peak memory 198432 kb
Host smart-aeb29c2d-ee2d-4608-9f52-6fe7f2f3a82c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2692798854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2692798854
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1951912609
Short name T545
Test name
Test status
Simulation time 62560069231 ps
CPU time 100.54 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 12:45:41 PM PDT 24
Peak memory 200300 kb
Host smart-8ef6f917-3774-4e23-bb2d-24b2bd53405b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951912609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1951912609
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.806955833
Short name T498
Test name
Test status
Simulation time 663265350 ps
CPU time 1.54 seconds
Started May 23 12:43:53 PM PDT 24
Finished May 23 12:43:56 PM PDT 24
Peak memory 195732 kb
Host smart-00b16d1c-b52e-466d-8130-a292b6157b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806955833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.806955833
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3748340619
Short name T310
Test name
Test status
Simulation time 5826793576 ps
CPU time 19.54 seconds
Started May 23 12:43:57 PM PDT 24
Finished May 23 12:44:18 PM PDT 24
Peak memory 200348 kb
Host smart-0ec2380c-4147-4566-ba2c-8924dfe3fbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748340619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3748340619
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3276381541
Short name T972
Test name
Test status
Simulation time 140040729349 ps
CPU time 72.91 seconds
Started May 23 12:43:57 PM PDT 24
Finished May 23 12:45:11 PM PDT 24
Peak memory 200436 kb
Host smart-d9d2cb72-6e75-47e4-8d88-8d4437602931
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276381541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3276381541
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1778127235
Short name T1089
Test name
Test status
Simulation time 24226126531 ps
CPU time 532.93 seconds
Started May 23 12:44:05 PM PDT 24
Finished May 23 12:52:59 PM PDT 24
Peak memory 208760 kb
Host smart-3f3c61c2-e705-4c5f-be0e-8ea0b6494cb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778127235 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1778127235
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1172831553
Short name T624
Test name
Test status
Simulation time 1234605552 ps
CPU time 4.62 seconds
Started May 23 12:44:04 PM PDT 24
Finished May 23 12:44:09 PM PDT 24
Peak memory 200320 kb
Host smart-918e2af6-0abd-4e68-bea0-4680b7abb581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172831553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1172831553
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.4154548008
Short name T716
Test name
Test status
Simulation time 58073573196 ps
CPU time 39.84 seconds
Started May 23 12:43:57 PM PDT 24
Finished May 23 12:44:38 PM PDT 24
Peak memory 200312 kb
Host smart-ef5c17db-d4fa-47e8-af15-8f55638639ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154548008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.4154548008
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.644144354
Short name T237
Test name
Test status
Simulation time 69459870697 ps
CPU time 77.63 seconds
Started May 23 12:46:39 PM PDT 24
Finished May 23 12:47:58 PM PDT 24
Peak memory 200500 kb
Host smart-d25c9aaf-8796-4a0c-8c49-fc2f67ad4cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644144354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.644144354
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1255092764
Short name T998
Test name
Test status
Simulation time 152184571390 ps
CPU time 82.04 seconds
Started May 23 12:46:39 PM PDT 24
Finished May 23 12:48:02 PM PDT 24
Peak memory 200344 kb
Host smart-fac8b280-f625-426d-aeb6-ad7d8f6c2eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255092764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1255092764
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.311563472
Short name T450
Test name
Test status
Simulation time 145862853009 ps
CPU time 583.63 seconds
Started May 23 12:46:39 PM PDT 24
Finished May 23 12:56:24 PM PDT 24
Peak memory 216860 kb
Host smart-48a65987-a16e-460c-a220-2b0e67fbb4ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311563472 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.311563472
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2328521588
Short name T257
Test name
Test status
Simulation time 18506016418 ps
CPU time 31.8 seconds
Started May 23 12:46:35 PM PDT 24
Finished May 23 12:47:08 PM PDT 24
Peak memory 200380 kb
Host smart-ed1a75a8-934b-414a-9766-84b060c9d3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328521588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2328521588
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1683105088
Short name T829
Test name
Test status
Simulation time 127785168140 ps
CPU time 619.1 seconds
Started May 23 12:46:33 PM PDT 24
Finished May 23 12:56:53 PM PDT 24
Peak memory 228520 kb
Host smart-f318e03e-9a2a-416b-99b0-916977b94e69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683105088 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1683105088
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.475529647
Short name T488
Test name
Test status
Simulation time 41097397624 ps
CPU time 61.88 seconds
Started May 23 12:46:40 PM PDT 24
Finished May 23 12:47:43 PM PDT 24
Peak memory 200504 kb
Host smart-23d41bf3-c7b5-44f9-8a4f-44d0e9e3b3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475529647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.475529647
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3551702218
Short name T1030
Test name
Test status
Simulation time 214628144626 ps
CPU time 775.64 seconds
Started May 23 12:46:40 PM PDT 24
Finished May 23 12:59:37 PM PDT 24
Peak memory 217008 kb
Host smart-6e902647-5a21-420d-a96d-2a963396efd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551702218 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3551702218
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.307585088
Short name T162
Test name
Test status
Simulation time 29547504527 ps
CPU time 318.76 seconds
Started May 23 12:46:40 PM PDT 24
Finished May 23 12:52:00 PM PDT 24
Peak memory 200400 kb
Host smart-2499c382-f14b-4b73-acbf-06fb13ee260c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307585088 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.307585088
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2052871932
Short name T223
Test name
Test status
Simulation time 270642183201 ps
CPU time 155.99 seconds
Started May 23 12:46:34 PM PDT 24
Finished May 23 12:49:11 PM PDT 24
Peak memory 200372 kb
Host smart-8e8ebf80-3603-4e11-a3b5-900ddc18da41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052871932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2052871932
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.678916078
Short name T706
Test name
Test status
Simulation time 96257073158 ps
CPU time 1877 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 01:17:55 PM PDT 24
Peak memory 228692 kb
Host smart-e5639d28-6473-4713-b192-527907c6f859
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678916078 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.678916078
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3341207079
Short name T1014
Test name
Test status
Simulation time 13508996344 ps
CPU time 21.08 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 12:46:58 PM PDT 24
Peak memory 200208 kb
Host smart-a29737a9-ffd8-491e-af4c-3b6536f99838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341207079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3341207079
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1453906104
Short name T687
Test name
Test status
Simulation time 118248442257 ps
CPU time 54.37 seconds
Started May 23 12:46:37 PM PDT 24
Finished May 23 12:47:33 PM PDT 24
Peak memory 200464 kb
Host smart-55044ae8-d91c-40b1-bebf-3dbd2c41d208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453906104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1453906104
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1944622266
Short name T54
Test name
Test status
Simulation time 65500186470 ps
CPU time 317.21 seconds
Started May 23 12:46:41 PM PDT 24
Finished May 23 12:52:00 PM PDT 24
Peak memory 216848 kb
Host smart-0c151769-a3ed-490a-bbef-437bb37d6c15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944622266 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1944622266
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.899288667
Short name T679
Test name
Test status
Simulation time 14544556578 ps
CPU time 27.45 seconds
Started May 23 12:46:36 PM PDT 24
Finished May 23 12:47:06 PM PDT 24
Peak memory 200360 kb
Host smart-bf94a653-2eda-48b7-81ae-14ad1e0ee702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899288667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.899288667
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2816116769
Short name T341
Test name
Test status
Simulation time 56754948564 ps
CPU time 294.92 seconds
Started May 23 12:46:35 PM PDT 24
Finished May 23 12:51:32 PM PDT 24
Peak memory 217204 kb
Host smart-c9023913-9ff7-415d-8fdd-8766dcd5928a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816116769 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2816116769
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.635309995
Short name T6
Test name
Test status
Simulation time 14019875 ps
CPU time 0.54 seconds
Started May 23 12:44:16 PM PDT 24
Finished May 23 12:44:18 PM PDT 24
Peak memory 195724 kb
Host smart-7b375472-dfb4-452a-960d-b897de8e043b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635309995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.635309995
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1674638362
Short name T864
Test name
Test status
Simulation time 56866760793 ps
CPU time 89.08 seconds
Started May 23 12:44:06 PM PDT 24
Finished May 23 12:45:36 PM PDT 24
Peak memory 200380 kb
Host smart-252eb0c4-16fd-41bf-8d64-67cb5856e39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674638362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1674638362
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.228160304
Short name T726
Test name
Test status
Simulation time 142500988191 ps
CPU time 189.7 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 12:47:10 PM PDT 24
Peak memory 200372 kb
Host smart-0107533d-bf3d-40b5-87cd-2e10312c743b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228160304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.228160304
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3183808681
Short name T1168
Test name
Test status
Simulation time 274438656996 ps
CPU time 65.48 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 12:45:05 PM PDT 24
Peak memory 200328 kb
Host smart-e7a91b7b-6349-4c3e-a46e-ea4943b7a9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183808681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3183808681
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2632009600
Short name T791
Test name
Test status
Simulation time 25620224440 ps
CPU time 45.58 seconds
Started May 23 12:44:00 PM PDT 24
Finished May 23 12:44:48 PM PDT 24
Peak memory 199856 kb
Host smart-62e24aa6-adbe-47fc-a33e-cf9b97635223
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632009600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2632009600
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2697260179
Short name T885
Test name
Test status
Simulation time 74865461887 ps
CPU time 315.08 seconds
Started May 23 12:44:16 PM PDT 24
Finished May 23 12:49:33 PM PDT 24
Peak memory 200312 kb
Host smart-f1593b20-8a10-40bb-84fc-02f659533b6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697260179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2697260179
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2537753843
Short name T844
Test name
Test status
Simulation time 3302461492 ps
CPU time 6.16 seconds
Started May 23 12:44:00 PM PDT 24
Finished May 23 12:44:09 PM PDT 24
Peak memory 199628 kb
Host smart-8778920c-2504-4481-9e5e-9e97ebfbea4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537753843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2537753843
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1913958753
Short name T274
Test name
Test status
Simulation time 142217582921 ps
CPU time 16.23 seconds
Started May 23 12:43:59 PM PDT 24
Finished May 23 12:44:17 PM PDT 24
Peak memory 199448 kb
Host smart-dbb933a5-777b-4666-b6a8-62e6983d0f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913958753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1913958753
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.650845382
Short name T1158
Test name
Test status
Simulation time 18534853237 ps
CPU time 1022.34 seconds
Started May 23 12:44:00 PM PDT 24
Finished May 23 01:01:05 PM PDT 24
Peak memory 200432 kb
Host smart-33fdbea6-5c38-4b31-ab29-f190b51b59bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=650845382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.650845382
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2427059500
Short name T389
Test name
Test status
Simulation time 5091924976 ps
CPU time 48.5 seconds
Started May 23 12:44:00 PM PDT 24
Finished May 23 12:44:50 PM PDT 24
Peak memory 198640 kb
Host smart-580d49da-a699-4f8f-a77e-4d9c18ca80ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2427059500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2427059500
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.4109644731
Short name T11
Test name
Test status
Simulation time 72047457389 ps
CPU time 62.03 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 12:45:06 PM PDT 24
Peak memory 200280 kb
Host smart-66d7cb3b-3389-431d-beda-6f897eb26826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109644731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.4109644731
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2368334497
Short name T1167
Test name
Test status
Simulation time 607306736 ps
CPU time 0.99 seconds
Started May 23 12:44:04 PM PDT 24
Finished May 23 12:44:06 PM PDT 24
Peak memory 196028 kb
Host smart-5d8c9ed4-931a-49aa-896c-f352dd2bc73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368334497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2368334497
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1282285675
Short name T765
Test name
Test status
Simulation time 112891734 ps
CPU time 0.81 seconds
Started May 23 12:43:55 PM PDT 24
Finished May 23 12:43:57 PM PDT 24
Peak memory 197344 kb
Host smart-eb0f558d-43e6-4291-a50f-f67403f868a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282285675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1282285675
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2739393241
Short name T816
Test name
Test status
Simulation time 131793719841 ps
CPU time 147.12 seconds
Started May 23 12:44:09 PM PDT 24
Finished May 23 12:46:38 PM PDT 24
Peak memory 200496 kb
Host smart-f2ec05b9-04f0-474d-a7e8-9596d64d1c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739393241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2739393241
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1472557197
Short name T1174
Test name
Test status
Simulation time 193682354850 ps
CPU time 321.57 seconds
Started May 23 12:44:06 PM PDT 24
Finished May 23 12:49:28 PM PDT 24
Peak memory 217052 kb
Host smart-12c1cb38-50c3-46c8-b457-ebf2c1969442
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472557197 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1472557197
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1373574597
Short name T20
Test name
Test status
Simulation time 799003985 ps
CPU time 2.88 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 12:44:03 PM PDT 24
Peak memory 200372 kb
Host smart-9b13b5d0-3907-44e7-9961-be5d446e38d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373574597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1373574597
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.4061271801
Short name T631
Test name
Test status
Simulation time 81088305060 ps
CPU time 92.68 seconds
Started May 23 12:43:58 PM PDT 24
Finished May 23 12:45:33 PM PDT 24
Peak memory 200384 kb
Host smart-db9a8243-ab0c-46c4-8b29-2fbb00f881e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061271801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.4061271801
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.190603709
Short name T67
Test name
Test status
Simulation time 48780582974 ps
CPU time 678.77 seconds
Started May 23 12:46:50 PM PDT 24
Finished May 23 12:58:11 PM PDT 24
Peak memory 216976 kb
Host smart-d53fa3c9-07f0-47b8-974b-ff89525c0f19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190603709 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.190603709
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.4081157176
Short name T1165
Test name
Test status
Simulation time 28152801583 ps
CPU time 27.66 seconds
Started May 23 12:46:48 PM PDT 24
Finished May 23 12:47:18 PM PDT 24
Peak memory 200484 kb
Host smart-2667a083-af1e-4b3d-ba50-fc8d46884c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081157176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.4081157176
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.983296948
Short name T839
Test name
Test status
Simulation time 20381089425 ps
CPU time 242.15 seconds
Started May 23 12:46:49 PM PDT 24
Finished May 23 12:50:53 PM PDT 24
Peak memory 216868 kb
Host smart-091005b2-0bd2-4df3-a600-4a1fe6cf7c42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983296948 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.983296948
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.197618933
Short name T458
Test name
Test status
Simulation time 17496295217 ps
CPU time 14.91 seconds
Started May 23 12:46:47 PM PDT 24
Finished May 23 12:47:03 PM PDT 24
Peak memory 200220 kb
Host smart-ecdd8032-df77-4b88-8bae-d5fda85d36ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197618933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.197618933
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3656004966
Short name T761
Test name
Test status
Simulation time 25264033519 ps
CPU time 45.46 seconds
Started May 23 12:46:49 PM PDT 24
Finished May 23 12:47:36 PM PDT 24
Peak memory 200240 kb
Host smart-ffc50023-6616-4de8-8ac5-ce0e9c73da65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656004966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3656004966
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3692754867
Short name T932
Test name
Test status
Simulation time 118886726656 ps
CPU time 646.18 seconds
Started May 23 12:46:57 PM PDT 24
Finished May 23 12:57:44 PM PDT 24
Peak memory 217116 kb
Host smart-baae5c2a-9d80-48ea-a778-22e0c9b4de39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692754867 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3692754867
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2806828401
Short name T974
Test name
Test status
Simulation time 9574925401 ps
CPU time 22.3 seconds
Started May 23 12:46:46 PM PDT 24
Finished May 23 12:47:11 PM PDT 24
Peak memory 200364 kb
Host smart-9056db0d-107b-40a1-8475-7b562f86d9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806828401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2806828401
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.990296531
Short name T224
Test name
Test status
Simulation time 66360925377 ps
CPU time 1320.77 seconds
Started May 23 12:46:48 PM PDT 24
Finished May 23 01:08:51 PM PDT 24
Peak memory 216800 kb
Host smart-4cec698d-aee2-43f5-be39-abdf2cf94140
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990296531 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.990296531
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3477245506
Short name T210
Test name
Test status
Simulation time 22102952731 ps
CPU time 18.08 seconds
Started May 23 12:46:48 PM PDT 24
Finished May 23 12:47:08 PM PDT 24
Peak memory 198784 kb
Host smart-e331af90-9189-4ee9-ad91-101d4689a49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477245506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3477245506
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2448151507
Short name T753
Test name
Test status
Simulation time 84758756757 ps
CPU time 527.51 seconds
Started May 23 12:46:47 PM PDT 24
Finished May 23 12:55:37 PM PDT 24
Peak memory 216948 kb
Host smart-c6fa2649-faa2-4516-aa70-344f1ba0f9ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448151507 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2448151507
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3398434967
Short name T226
Test name
Test status
Simulation time 137057147384 ps
CPU time 126.49 seconds
Started May 23 12:46:49 PM PDT 24
Finished May 23 12:48:58 PM PDT 24
Peak memory 200460 kb
Host smart-01b1bfd1-bb70-468a-830e-bf272c354470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398434967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3398434967
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.916752911
Short name T754
Test name
Test status
Simulation time 29970700496 ps
CPU time 97.85 seconds
Started May 23 12:46:49 PM PDT 24
Finished May 23 12:48:29 PM PDT 24
Peak memory 208720 kb
Host smart-a2ff7263-5665-4649-8cf8-16bcb1be2e46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916752911 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.916752911
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.621660314
Short name T1161
Test name
Test status
Simulation time 55450463693 ps
CPU time 117.05 seconds
Started May 23 12:46:48 PM PDT 24
Finished May 23 12:48:47 PM PDT 24
Peak memory 200404 kb
Host smart-c3920954-22bb-4331-94ee-5418cb41f34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621660314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.621660314
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2652997383
Short name T590
Test name
Test status
Simulation time 37552677392 ps
CPU time 377.55 seconds
Started May 23 12:46:46 PM PDT 24
Finished May 23 12:53:06 PM PDT 24
Peak memory 216060 kb
Host smart-033625ba-c483-42c1-b7d0-ca3fea988692
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652997383 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2652997383
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2726825395
Short name T308
Test name
Test status
Simulation time 9867941102 ps
CPU time 18.64 seconds
Started May 23 12:46:46 PM PDT 24
Finished May 23 12:47:06 PM PDT 24
Peak memory 200248 kb
Host smart-f085e10c-ed6e-429d-9ca3-0d63f8eabf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726825395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2726825395
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2346727708
Short name T267
Test name
Test status
Simulation time 163458273347 ps
CPU time 717.21 seconds
Started May 23 12:46:47 PM PDT 24
Finished May 23 12:58:47 PM PDT 24
Peak memory 216860 kb
Host smart-610a80ef-46f8-4bcd-9dd4-b3900f93d9ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346727708 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2346727708
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3261424926
Short name T1004
Test name
Test status
Simulation time 9431799900 ps
CPU time 16.34 seconds
Started May 23 12:46:50 PM PDT 24
Finished May 23 12:47:08 PM PDT 24
Peak memory 200312 kb
Host smart-037ad4ac-eb0c-4ba4-8153-af456c928d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261424926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3261424926
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.450758174
Short name T1178
Test name
Test status
Simulation time 90173604048 ps
CPU time 768.85 seconds
Started May 23 12:46:57 PM PDT 24
Finished May 23 12:59:46 PM PDT 24
Peak memory 216820 kb
Host smart-7f4a8087-39bc-4369-9a5a-a5564fe8d309
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450758174 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.450758174
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.751416333
Short name T996
Test name
Test status
Simulation time 22791230 ps
CPU time 0.55 seconds
Started May 23 12:44:20 PM PDT 24
Finished May 23 12:44:22 PM PDT 24
Peak memory 195748 kb
Host smart-6bd1753a-64f4-4738-bdcb-c32b26975238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751416333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.751416333
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1744259959
Short name T435
Test name
Test status
Simulation time 45919347761 ps
CPU time 24.9 seconds
Started May 23 12:44:07 PM PDT 24
Finished May 23 12:44:32 PM PDT 24
Peak memory 200332 kb
Host smart-351874de-7683-4ffb-a21a-da58c64f3fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744259959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1744259959
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2577634558
Short name T750
Test name
Test status
Simulation time 59029697858 ps
CPU time 46.03 seconds
Started May 23 12:44:08 PM PDT 24
Finished May 23 12:44:55 PM PDT 24
Peak memory 199984 kb
Host smart-253785ba-83f5-4ce1-9cec-b702a9b6119b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577634558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2577634558
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.253831596
Short name T480
Test name
Test status
Simulation time 135328561677 ps
CPU time 57.04 seconds
Started May 23 12:44:07 PM PDT 24
Finished May 23 12:45:05 PM PDT 24
Peak memory 200380 kb
Host smart-23c79b4c-713a-4e1b-b0ea-7bc25b78c1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253831596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.253831596
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2639210433
Short name T331
Test name
Test status
Simulation time 41528262713 ps
CPU time 15.38 seconds
Started May 23 12:44:16 PM PDT 24
Finished May 23 12:44:33 PM PDT 24
Peak memory 200336 kb
Host smart-889f1d0f-74e0-40c8-84ac-8f09d4f26fa1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639210433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2639210433
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3515994444
Short name T537
Test name
Test status
Simulation time 64885386344 ps
CPU time 610.72 seconds
Started May 23 12:44:11 PM PDT 24
Finished May 23 12:54:23 PM PDT 24
Peak memory 200280 kb
Host smart-704f3978-9bf0-419f-ad35-87cd4952baf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3515994444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3515994444
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3678269453
Short name T971
Test name
Test status
Simulation time 7118695131 ps
CPU time 4.26 seconds
Started May 23 12:44:18 PM PDT 24
Finished May 23 12:44:24 PM PDT 24
Peak memory 199492 kb
Host smart-1b457c2a-146c-4e82-89c5-a4b56087d49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678269453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3678269453
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2964173131
Short name T950
Test name
Test status
Simulation time 179480720612 ps
CPU time 198.04 seconds
Started May 23 12:44:15 PM PDT 24
Finished May 23 12:47:35 PM PDT 24
Peak memory 216204 kb
Host smart-c00ba404-6635-4f5e-bb2e-c7a744b5e98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964173131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2964173131
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2764004071
Short name T606
Test name
Test status
Simulation time 11503034688 ps
CPU time 260.38 seconds
Started May 23 12:44:19 PM PDT 24
Finished May 23 12:48:40 PM PDT 24
Peak memory 200376 kb
Host smart-4e5c9618-84aa-4bb8-af41-bd611fd1d0e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2764004071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2764004071
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.377370230
Short name T888
Test name
Test status
Simulation time 5898119921 ps
CPU time 54.95 seconds
Started May 23 12:44:15 PM PDT 24
Finished May 23 12:45:12 PM PDT 24
Peak memory 199488 kb
Host smart-7cd55642-d91b-4d64-b1d1-b9e1c669db52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377370230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.377370230
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3329963018
Short name T794
Test name
Test status
Simulation time 40707881664 ps
CPU time 40.19 seconds
Started May 23 12:44:08 PM PDT 24
Finished May 23 12:44:50 PM PDT 24
Peak memory 200340 kb
Host smart-388371cb-f186-4045-a0fd-c487e38c2d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329963018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3329963018
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2416575582
Short name T436
Test name
Test status
Simulation time 74143300222 ps
CPU time 108.26 seconds
Started May 23 12:44:09 PM PDT 24
Finished May 23 12:46:00 PM PDT 24
Peak memory 196444 kb
Host smart-227c7d40-fbdc-4856-b4e4-6acaae4fa52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416575582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2416575582
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2854988631
Short name T745
Test name
Test status
Simulation time 667756434 ps
CPU time 2.89 seconds
Started May 23 12:44:09 PM PDT 24
Finished May 23 12:44:14 PM PDT 24
Peak memory 198972 kb
Host smart-330faa5a-4fa4-4872-9822-bac24e0f5c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854988631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2854988631
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1500717400
Short name T656
Test name
Test status
Simulation time 60759430660 ps
CPU time 28.56 seconds
Started May 23 12:44:10 PM PDT 24
Finished May 23 12:44:40 PM PDT 24
Peak memory 216832 kb
Host smart-e303d47d-ec38-48b8-b891-296d54a8e5a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500717400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1500717400
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2638571763
Short name T987
Test name
Test status
Simulation time 78282667441 ps
CPU time 516.68 seconds
Started May 23 12:44:10 PM PDT 24
Finished May 23 12:52:49 PM PDT 24
Peak memory 217092 kb
Host smart-4372ea6f-5585-4fc9-ab93-5423793fabc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638571763 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2638571763
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2826872795
Short name T607
Test name
Test status
Simulation time 364821152 ps
CPU time 1.53 seconds
Started May 23 12:44:15 PM PDT 24
Finished May 23 12:44:18 PM PDT 24
Peak memory 198876 kb
Host smart-e21eddbf-7b9a-4987-84b8-5bc3d6d466c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826872795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2826872795
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2253415140
Short name T959
Test name
Test status
Simulation time 95529408646 ps
CPU time 46.33 seconds
Started May 23 12:44:09 PM PDT 24
Finished May 23 12:44:57 PM PDT 24
Peak memory 200344 kb
Host smart-7e3e8657-626b-4968-9e37-a71a74c227ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253415140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2253415140
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.205473349
Short name T220
Test name
Test status
Simulation time 92247866454 ps
CPU time 89.43 seconds
Started May 23 12:46:50 PM PDT 24
Finished May 23 12:48:21 PM PDT 24
Peak memory 200216 kb
Host smart-2c19087c-1af6-4108-97e0-13a266949254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205473349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.205473349
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.175561585
Short name T491
Test name
Test status
Simulation time 59740052576 ps
CPU time 431.1 seconds
Started May 23 12:46:54 PM PDT 24
Finished May 23 12:54:06 PM PDT 24
Peak memory 216496 kb
Host smart-f40ba397-b1d0-4f1e-a17b-dc1333afdd2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175561585 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.175561585
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.738668710
Short name T242
Test name
Test status
Simulation time 105335973441 ps
CPU time 35.74 seconds
Started May 23 12:46:50 PM PDT 24
Finished May 23 12:47:28 PM PDT 24
Peak memory 200368 kb
Host smart-3cb3b7ab-e113-4060-8cc0-0b516db5291c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738668710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.738668710
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.259300361
Short name T24
Test name
Test status
Simulation time 57343444187 ps
CPU time 263.12 seconds
Started May 23 12:46:57 PM PDT 24
Finished May 23 12:51:21 PM PDT 24
Peak memory 216004 kb
Host smart-46745096-36c1-4fc4-8416-6e0f666e4bfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259300361 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.259300361
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3336986768
Short name T289
Test name
Test status
Simulation time 88981998663 ps
CPU time 46.5 seconds
Started May 23 12:46:48 PM PDT 24
Finished May 23 12:47:36 PM PDT 24
Peak memory 199424 kb
Host smart-c36ecc46-b4ac-443d-a0ae-eda3cdfbaa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336986768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3336986768
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2555470111
Short name T724
Test name
Test status
Simulation time 15913904067 ps
CPU time 28.48 seconds
Started May 23 12:46:50 PM PDT 24
Finished May 23 12:47:20 PM PDT 24
Peak memory 200296 kb
Host smart-491373d6-a1ce-49ca-b61a-0afc9362f420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555470111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2555470111
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1449190756
Short name T575
Test name
Test status
Simulation time 93817961430 ps
CPU time 1133.85 seconds
Started May 23 12:46:49 PM PDT 24
Finished May 23 01:05:45 PM PDT 24
Peak memory 233500 kb
Host smart-425cdb7d-472e-4230-969d-c79061d3e83f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449190756 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1449190756
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3364128316
Short name T190
Test name
Test status
Simulation time 28878609736 ps
CPU time 44.2 seconds
Started May 23 12:46:50 PM PDT 24
Finished May 23 12:47:36 PM PDT 24
Peak memory 200308 kb
Host smart-07ea813d-2062-4b3c-9853-89fdb1cd077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364128316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3364128316
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1985891252
Short name T806
Test name
Test status
Simulation time 14131029082 ps
CPU time 447.29 seconds
Started May 23 12:46:49 PM PDT 24
Finished May 23 12:54:18 PM PDT 24
Peak memory 216000 kb
Host smart-91d342dc-d8c5-489b-abfa-66a5fd15378d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985891252 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1985891252
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3406310095
Short name T720
Test name
Test status
Simulation time 106551781486 ps
CPU time 176.41 seconds
Started May 23 12:46:46 PM PDT 24
Finished May 23 12:49:44 PM PDT 24
Peak memory 200368 kb
Host smart-6a4f1b24-8361-4313-b920-8214cd826e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406310095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3406310095
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3417149245
Short name T683
Test name
Test status
Simulation time 138461915022 ps
CPU time 1435.87 seconds
Started May 23 12:46:49 PM PDT 24
Finished May 23 01:10:47 PM PDT 24
Peak memory 225964 kb
Host smart-13f6918d-17bd-4134-b759-879386bedcc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417149245 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3417149245
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3897883593
Short name T1059
Test name
Test status
Simulation time 152093781935 ps
CPU time 226.68 seconds
Started May 23 12:46:47 PM PDT 24
Finished May 23 12:50:36 PM PDT 24
Peak memory 200340 kb
Host smart-ea4c3cc7-1edb-4b6c-ab16-c737b244ce4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897883593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3897883593
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1940826045
Short name T1117
Test name
Test status
Simulation time 46329279945 ps
CPU time 562.64 seconds
Started May 23 12:46:54 PM PDT 24
Finished May 23 12:56:17 PM PDT 24
Peak memory 217084 kb
Host smart-e30f147a-2952-47bd-9302-b095c162a870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940826045 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1940826045
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1875584231
Short name T192
Test name
Test status
Simulation time 29877249599 ps
CPU time 59.43 seconds
Started May 23 12:46:54 PM PDT 24
Finished May 23 12:47:54 PM PDT 24
Peak memory 200320 kb
Host smart-b8b15de4-2d2f-4c0f-a865-2d12030b9f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875584231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1875584231
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.530938690
Short name T58
Test name
Test status
Simulation time 147341473950 ps
CPU time 572.54 seconds
Started May 23 12:46:45 PM PDT 24
Finished May 23 12:56:19 PM PDT 24
Peak memory 216840 kb
Host smart-032bf73f-db18-4622-8e89-2f902e86ae28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530938690 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.530938690
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1899588497
Short name T251
Test name
Test status
Simulation time 9465506083 ps
CPU time 12.03 seconds
Started May 23 12:46:50 PM PDT 24
Finished May 23 12:47:04 PM PDT 24
Peak memory 200348 kb
Host smart-85835108-aa10-46c7-9e4d-40e6e3f07c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899588497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1899588497
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2763048348
Short name T336
Test name
Test status
Simulation time 42986638460 ps
CPU time 500.56 seconds
Started May 23 12:46:47 PM PDT 24
Finished May 23 12:55:09 PM PDT 24
Peak memory 226960 kb
Host smart-70047e5a-9531-4249-9965-2e9c8430c416
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763048348 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2763048348
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2442014355
Short name T1172
Test name
Test status
Simulation time 17573017838 ps
CPU time 26.84 seconds
Started May 23 12:46:57 PM PDT 24
Finished May 23 12:47:25 PM PDT 24
Peak memory 200372 kb
Host smart-2bb2a2fe-e6d4-420c-8afd-a211582aedaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442014355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2442014355
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.800433913
Short name T556
Test name
Test status
Simulation time 19752742190 ps
CPU time 138.65 seconds
Started May 23 12:46:58 PM PDT 24
Finished May 23 12:49:17 PM PDT 24
Peak memory 216024 kb
Host smart-2bccbf3d-1490-44c4-8c08-09670e3f6250
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800433913 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.800433913
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2330527870
Short name T381
Test name
Test status
Simulation time 11993595 ps
CPU time 0.66 seconds
Started May 23 12:44:12 PM PDT 24
Finished May 23 12:44:14 PM PDT 24
Peak memory 195812 kb
Host smart-037b1d12-a9de-4789-8f95-6a193c1b129c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330527870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2330527870
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.829276160
Short name T553
Test name
Test status
Simulation time 140516209954 ps
CPU time 114.27 seconds
Started May 23 12:44:09 PM PDT 24
Finished May 23 12:46:05 PM PDT 24
Peak memory 200336 kb
Host smart-cf697ec4-db4f-4e74-8092-1fcc5d757ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829276160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.829276160
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.4213646616
Short name T634
Test name
Test status
Simulation time 13224011967 ps
CPU time 22.82 seconds
Started May 23 12:44:16 PM PDT 24
Finished May 23 12:44:41 PM PDT 24
Peak memory 200368 kb
Host smart-021e91c8-ef21-4781-9536-76a03bba7315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213646616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.4213646616
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_intr.3852252476
Short name T456
Test name
Test status
Simulation time 46042593372 ps
CPU time 39.35 seconds
Started May 23 12:44:08 PM PDT 24
Finished May 23 12:44:50 PM PDT 24
Peak memory 200208 kb
Host smart-6ac7edfb-6032-461d-8c99-53854f042156
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852252476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3852252476
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3158135340
Short name T273
Test name
Test status
Simulation time 140771730404 ps
CPU time 625.25 seconds
Started May 23 12:44:13 PM PDT 24
Finished May 23 12:54:40 PM PDT 24
Peak memory 200324 kb
Host smart-a18ca943-cb23-44f1-a15c-a4060f2218ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3158135340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3158135340
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1140205054
Short name T658
Test name
Test status
Simulation time 2866478129 ps
CPU time 4.49 seconds
Started May 23 12:44:18 PM PDT 24
Finished May 23 12:44:24 PM PDT 24
Peak memory 199672 kb
Host smart-9bdf1e7a-a10c-42e1-b24c-f9ba067cecd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140205054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1140205054
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2511412870
Short name T628
Test name
Test status
Simulation time 299528056127 ps
CPU time 42.62 seconds
Started May 23 12:44:17 PM PDT 24
Finished May 23 12:45:01 PM PDT 24
Peak memory 200816 kb
Host smart-b70ffeb7-46b1-41c7-8b86-207d6dd66233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511412870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2511412870
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1063996447
Short name T1021
Test name
Test status
Simulation time 4458768945 ps
CPU time 248.5 seconds
Started May 23 12:44:14 PM PDT 24
Finished May 23 12:48:24 PM PDT 24
Peak memory 200464 kb
Host smart-dc9c15ec-122f-4d1d-8c40-6f768358800e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063996447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1063996447
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1928352934
Short name T783
Test name
Test status
Simulation time 6027463384 ps
CPU time 26.78 seconds
Started May 23 12:44:15 PM PDT 24
Finished May 23 12:44:43 PM PDT 24
Peak memory 198596 kb
Host smart-59c0e69d-a9e6-41ce-9058-d3bac5a6f6d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1928352934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1928352934
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2692961188
Short name T1066
Test name
Test status
Simulation time 19433026020 ps
CPU time 17.64 seconds
Started May 23 12:44:09 PM PDT 24
Finished May 23 12:44:28 PM PDT 24
Peak memory 200244 kb
Host smart-3d85195c-fcb9-49c6-a887-ddfa4330edf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692961188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2692961188
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.838639737
Short name T325
Test name
Test status
Simulation time 5323221439 ps
CPU time 5.13 seconds
Started May 23 12:44:17 PM PDT 24
Finished May 23 12:44:24 PM PDT 24
Peak memory 196428 kb
Host smart-43ab6693-d9bb-4a71-aa85-89d97e70c3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838639737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.838639737
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2091579955
Short name T416
Test name
Test status
Simulation time 6259514171 ps
CPU time 8.91 seconds
Started May 23 12:44:10 PM PDT 24
Finished May 23 12:44:21 PM PDT 24
Peak memory 199588 kb
Host smart-22c87ef3-500f-4dc9-9b29-5a25235605a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091579955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2091579955
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3826615418
Short name T734
Test name
Test status
Simulation time 36507826887 ps
CPU time 874.33 seconds
Started May 23 12:44:14 PM PDT 24
Finished May 23 12:58:50 PM PDT 24
Peak memory 200360 kb
Host smart-450540b6-7734-4dcc-86f4-b6d6cfe00eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826615418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3826615418
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2235460664
Short name T1106
Test name
Test status
Simulation time 77421218764 ps
CPU time 431.63 seconds
Started May 23 12:44:20 PM PDT 24
Finished May 23 12:51:33 PM PDT 24
Peak memory 217080 kb
Host smart-0c30a2f6-897d-4778-90f0-64c334f72f03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235460664 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2235460664
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2666511531
Short name T417
Test name
Test status
Simulation time 8016751318 ps
CPU time 11.61 seconds
Started May 23 12:44:15 PM PDT 24
Finished May 23 12:44:29 PM PDT 24
Peak memory 200420 kb
Host smart-5c6071a8-67f1-4619-b7a6-2294f65eb1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666511531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2666511531
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2673494649
Short name T392
Test name
Test status
Simulation time 49226717689 ps
CPU time 46.74 seconds
Started May 23 12:44:10 PM PDT 24
Finished May 23 12:44:58 PM PDT 24
Peak memory 200256 kb
Host smart-f659319f-e178-4dcf-a008-4338d7575fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673494649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2673494649
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3528794316
Short name T502
Test name
Test status
Simulation time 231554394143 ps
CPU time 75.8 seconds
Started May 23 12:46:57 PM PDT 24
Finished May 23 12:48:13 PM PDT 24
Peak memory 200312 kb
Host smart-93781a8f-9355-4402-a3a8-ff9462a113c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528794316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3528794316
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1511614841
Short name T1103
Test name
Test status
Simulation time 287295961420 ps
CPU time 931.39 seconds
Started May 23 12:46:49 PM PDT 24
Finished May 23 01:02:23 PM PDT 24
Peak memory 216820 kb
Host smart-c2364acc-0b4e-49d2-b8a5-a274cf2451fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511614841 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1511614841
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3154242302
Short name T1122
Test name
Test status
Simulation time 155307653436 ps
CPU time 82.47 seconds
Started May 23 12:46:48 PM PDT 24
Finished May 23 12:48:12 PM PDT 24
Peak memory 200392 kb
Host smart-fda4ecb8-cd17-4243-987f-e317f989cac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154242302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3154242302
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3024515143
Short name T983
Test name
Test status
Simulation time 27443604281 ps
CPU time 326.7 seconds
Started May 23 12:46:49 PM PDT 24
Finished May 23 12:52:17 PM PDT 24
Peak memory 215804 kb
Host smart-15b5fcdc-9346-4e0a-a5d7-b468bacb32dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024515143 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3024515143
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.4068478092
Short name T1046
Test name
Test status
Simulation time 76508899152 ps
CPU time 115.77 seconds
Started May 23 12:46:51 PM PDT 24
Finished May 23 12:48:48 PM PDT 24
Peak memory 200460 kb
Host smart-58cdbdd3-6c82-4899-81e6-51317f7a1609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068478092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.4068478092
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1162054967
Short name T110
Test name
Test status
Simulation time 31043406306 ps
CPU time 426.38 seconds
Started May 23 12:46:53 PM PDT 24
Finished May 23 12:54:00 PM PDT 24
Peak memory 217112 kb
Host smart-f5e1e397-a32b-4e45-a1f4-f0897319f64a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162054967 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1162054967
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.139332465
Short name T441
Test name
Test status
Simulation time 241093017002 ps
CPU time 46.39 seconds
Started May 23 12:46:49 PM PDT 24
Finished May 23 12:47:38 PM PDT 24
Peak memory 200280 kb
Host smart-5f79dc13-68ca-48b6-a1c6-6eb027ebf4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139332465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.139332465
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.309214752
Short name T16
Test name
Test status
Simulation time 38642464368 ps
CPU time 459.86 seconds
Started May 23 12:46:48 PM PDT 24
Finished May 23 12:54:30 PM PDT 24
Peak memory 216620 kb
Host smart-c254c4a5-abe3-4e2c-ba2f-bfb8f6c2e724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309214752 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.309214752
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2437264962
Short name T40
Test name
Test status
Simulation time 33630042078 ps
CPU time 15.97 seconds
Started May 23 12:46:57 PM PDT 24
Finished May 23 12:47:14 PM PDT 24
Peak memory 200372 kb
Host smart-2bc4979a-3797-4992-afe2-e599f9e0b56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437264962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2437264962
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1929098056
Short name T1140
Test name
Test status
Simulation time 66226793514 ps
CPU time 1574.22 seconds
Started May 23 12:47:02 PM PDT 24
Finished May 23 01:13:17 PM PDT 24
Peak memory 217196 kb
Host smart-7f447258-8237-4f68-a070-8214ba007ca5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929098056 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1929098056
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3637639353
Short name T234
Test name
Test status
Simulation time 37775960116 ps
CPU time 72.66 seconds
Started May 23 12:47:03 PM PDT 24
Finished May 23 12:48:17 PM PDT 24
Peak memory 200304 kb
Host smart-e26a6e43-fc4f-44db-80c6-ae17a3957669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637639353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3637639353
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.113031913
Short name T169
Test name
Test status
Simulation time 200852753552 ps
CPU time 738.8 seconds
Started May 23 12:47:03 PM PDT 24
Finished May 23 12:59:24 PM PDT 24
Peak memory 225268 kb
Host smart-d1a9c2e5-455f-43c9-89cf-a1aaa575dca8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113031913 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.113031913
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1981206427
Short name T236
Test name
Test status
Simulation time 119045583822 ps
CPU time 28.79 seconds
Started May 23 12:47:03 PM PDT 24
Finished May 23 12:47:33 PM PDT 24
Peak memory 200392 kb
Host smart-1290eb19-6961-454f-b045-ba5171d6c6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981206427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1981206427
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2144395076
Short name T228
Test name
Test status
Simulation time 79636631469 ps
CPU time 43.62 seconds
Started May 23 12:47:02 PM PDT 24
Finished May 23 12:47:46 PM PDT 24
Peak memory 200096 kb
Host smart-16b78a67-8ee1-4906-a08a-fe2058504d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144395076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2144395076
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.4240777620
Short name T621
Test name
Test status
Simulation time 115680034545 ps
CPU time 639.2 seconds
Started May 23 12:47:03 PM PDT 24
Finished May 23 12:57:43 PM PDT 24
Peak memory 217248 kb
Host smart-2e97911f-955e-486b-8d7c-0be521013557
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240777620 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.4240777620
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1434794415
Short name T767
Test name
Test status
Simulation time 114510304093 ps
CPU time 105.32 seconds
Started May 23 12:47:03 PM PDT 24
Finished May 23 12:48:50 PM PDT 24
Peak memory 200348 kb
Host smart-600455b1-ac4a-42bd-b570-80aefe4dd8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434794415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1434794415
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.767811759
Short name T609
Test name
Test status
Simulation time 149029239307 ps
CPU time 75.41 seconds
Started May 23 12:47:01 PM PDT 24
Finished May 23 12:48:17 PM PDT 24
Peak memory 200400 kb
Host smart-55aa4999-be3f-4097-a971-d29bc732a02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767811759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.767811759
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1591065409
Short name T121
Test name
Test status
Simulation time 184805940706 ps
CPU time 321.34 seconds
Started May 23 12:47:02 PM PDT 24
Finished May 23 12:52:24 PM PDT 24
Peak memory 211444 kb
Host smart-353ec0e6-0600-4579-b88a-e6730e20b018
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591065409 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1591065409
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1066377963
Short name T375
Test name
Test status
Simulation time 12264307 ps
CPU time 0.53 seconds
Started May 23 12:44:08 PM PDT 24
Finished May 23 12:44:10 PM PDT 24
Peak memory 195712 kb
Host smart-cf0adaab-3370-4bbb-a4f1-5dbe4b4a9051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066377963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1066377963
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.526548192
Short name T538
Test name
Test status
Simulation time 19154613173 ps
CPU time 31.96 seconds
Started May 23 12:44:11 PM PDT 24
Finished May 23 12:44:45 PM PDT 24
Peak memory 200452 kb
Host smart-4871236a-a037-45e0-b44e-15b1d36128ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526548192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.526548192
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.146517350
Short name T719
Test name
Test status
Simulation time 33243395760 ps
CPU time 27.27 seconds
Started May 23 12:44:12 PM PDT 24
Finished May 23 12:44:41 PM PDT 24
Peak memory 200444 kb
Host smart-11099157-2e44-42e8-8970-4da3d8b23632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146517350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.146517350
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.13204699
Short name T501
Test name
Test status
Simulation time 11131632684 ps
CPU time 34.55 seconds
Started May 23 12:44:14 PM PDT 24
Finished May 23 12:44:50 PM PDT 24
Peak memory 200456 kb
Host smart-adc9ca31-9339-4ab6-854d-2d1ac6f0ed4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13204699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.13204699
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2353892013
Short name T909
Test name
Test status
Simulation time 73846641676 ps
CPU time 75.84 seconds
Started May 23 12:44:13 PM PDT 24
Finished May 23 12:45:30 PM PDT 24
Peak memory 200460 kb
Host smart-0e17304b-f760-43bc-810f-f785d8b44632
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353892013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2353892013
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.4203613773
Short name T813
Test name
Test status
Simulation time 147639020507 ps
CPU time 643.54 seconds
Started May 23 12:44:08 PM PDT 24
Finished May 23 12:54:52 PM PDT 24
Peak memory 200324 kb
Host smart-5c17b9ce-5cd4-4b8f-a32b-b7be4726ecb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203613773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.4203613773
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.489564577
Short name T1000
Test name
Test status
Simulation time 1215972818 ps
CPU time 2.33 seconds
Started May 23 12:44:18 PM PDT 24
Finished May 23 12:44:22 PM PDT 24
Peak memory 197768 kb
Host smart-baca4635-5da8-44cf-8ed2-d7df99c2b3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489564577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.489564577
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2598459601
Short name T276
Test name
Test status
Simulation time 88409952797 ps
CPU time 182.11 seconds
Started May 23 12:44:14 PM PDT 24
Finished May 23 12:47:18 PM PDT 24
Peak memory 216360 kb
Host smart-be5053ea-8aa9-41a9-ad97-7ead20689622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598459601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2598459601
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.990162630
Short name T406
Test name
Test status
Simulation time 15712144299 ps
CPU time 393.3 seconds
Started May 23 12:44:10 PM PDT 24
Finished May 23 12:50:46 PM PDT 24
Peak memory 200484 kb
Host smart-346f87ca-1460-4d13-a732-2fa9358195b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=990162630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.990162630
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2530962588
Short name T938
Test name
Test status
Simulation time 7059829359 ps
CPU time 58.18 seconds
Started May 23 12:44:18 PM PDT 24
Finished May 23 12:45:18 PM PDT 24
Peak memory 199388 kb
Host smart-e7b86aa2-5ce1-4c95-8147-6566cf9f5533
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2530962588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2530962588
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1265412357
Short name T1177
Test name
Test status
Simulation time 60190739603 ps
CPU time 96.29 seconds
Started May 23 12:44:12 PM PDT 24
Finished May 23 12:45:51 PM PDT 24
Peak memory 200392 kb
Host smart-cafd2abf-d7a1-4dfa-be65-b58bd75222b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265412357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1265412357
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.808871309
Short name T892
Test name
Test status
Simulation time 1315403972 ps
CPU time 1.19 seconds
Started May 23 12:44:18 PM PDT 24
Finished May 23 12:44:21 PM PDT 24
Peak memory 196112 kb
Host smart-8e9109ae-bb56-47a4-b55d-9e26deeed0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808871309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.808871309
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3708876958
Short name T483
Test name
Test status
Simulation time 574326610 ps
CPU time 0.89 seconds
Started May 23 12:44:12 PM PDT 24
Finished May 23 12:44:15 PM PDT 24
Peak memory 199420 kb
Host smart-02c38fe1-b159-4e4b-8754-74f849534a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708876958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3708876958
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3635104825
Short name T513
Test name
Test status
Simulation time 141186966517 ps
CPU time 1058.55 seconds
Started May 23 12:44:13 PM PDT 24
Finished May 23 01:01:53 PM PDT 24
Peak memory 200424 kb
Host smart-f1c9ea3f-cf9a-490a-90e0-58f401276bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635104825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3635104825
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3756921336
Short name T1092
Test name
Test status
Simulation time 56320187761 ps
CPU time 432.18 seconds
Started May 23 12:44:11 PM PDT 24
Finished May 23 12:51:25 PM PDT 24
Peak memory 217116 kb
Host smart-d9491e10-192f-4d4e-b276-b1c85187517a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756921336 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3756921336
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.4194788421
Short name T1146
Test name
Test status
Simulation time 1065102792 ps
CPU time 3.42 seconds
Started May 23 12:44:16 PM PDT 24
Finished May 23 12:44:21 PM PDT 24
Peak memory 199160 kb
Host smart-dbba59fd-83c0-498c-8f54-e67dfa1b48ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194788421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.4194788421
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3333650198
Short name T1029
Test name
Test status
Simulation time 75588716731 ps
CPU time 145.01 seconds
Started May 23 12:44:13 PM PDT 24
Finished May 23 12:46:40 PM PDT 24
Peak memory 200380 kb
Host smart-fb7b96b7-e353-4a03-a63b-00ab1071ee8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333650198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3333650198
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.610625688
Short name T905
Test name
Test status
Simulation time 97823817160 ps
CPU time 95.42 seconds
Started May 23 12:47:03 PM PDT 24
Finished May 23 12:48:40 PM PDT 24
Peak memory 200432 kb
Host smart-fe1c89c2-c5f0-4b87-8f7f-3cfd0d3befcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610625688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.610625688
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2743755327
Short name T505
Test name
Test status
Simulation time 921868462093 ps
CPU time 739.74 seconds
Started May 23 12:47:03 PM PDT 24
Finished May 23 12:59:24 PM PDT 24
Peak memory 227140 kb
Host smart-3fcfa506-cc7a-4088-883c-590d8e44b1c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743755327 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2743755327
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.976151787
Short name T746
Test name
Test status
Simulation time 12286503390 ps
CPU time 11.83 seconds
Started May 23 12:47:04 PM PDT 24
Finished May 23 12:47:17 PM PDT 24
Peak memory 200504 kb
Host smart-55ca4768-5730-4f4f-bf10-b66cba8b25a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976151787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.976151787
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3682224034
Short name T52
Test name
Test status
Simulation time 108145133819 ps
CPU time 364.07 seconds
Started May 23 12:47:03 PM PDT 24
Finished May 23 12:53:08 PM PDT 24
Peak memory 216852 kb
Host smart-d8c372ef-f2e0-4ad3-961c-308165d097f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682224034 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3682224034
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3377218175
Short name T676
Test name
Test status
Simulation time 117827176745 ps
CPU time 727.81 seconds
Started May 23 12:47:01 PM PDT 24
Finished May 23 12:59:10 PM PDT 24
Peak memory 216936 kb
Host smart-a8455717-4d3f-46be-9cd1-b8cd4b454ac6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377218175 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3377218175
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3275616427
Short name T518
Test name
Test status
Simulation time 72226906321 ps
CPU time 50.65 seconds
Started May 23 12:47:02 PM PDT 24
Finished May 23 12:47:54 PM PDT 24
Peak memory 200432 kb
Host smart-6744dc86-18a8-4ba5-81b0-fe101927adee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275616427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3275616427
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.2713394577
Short name T12
Test name
Test status
Simulation time 20957220378 ps
CPU time 641.15 seconds
Started May 23 12:47:05 PM PDT 24
Finished May 23 12:57:47 PM PDT 24
Peak memory 211368 kb
Host smart-4320b25d-0d76-48e7-a01f-f8290734d735
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713394577 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2713394577
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.4207746988
Short name T540
Test name
Test status
Simulation time 29814736731 ps
CPU time 59.1 seconds
Started May 23 12:47:02 PM PDT 24
Finished May 23 12:48:02 PM PDT 24
Peak memory 200324 kb
Host smart-282ed8de-4fd5-4d54-a513-3e2a5ff50234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207746988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.4207746988
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3611823920
Short name T154
Test name
Test status
Simulation time 51951892513 ps
CPU time 606.29 seconds
Started May 23 12:47:09 PM PDT 24
Finished May 23 12:57:16 PM PDT 24
Peak memory 216828 kb
Host smart-1983b7b1-2b0c-406d-9fe2-6b2811c455e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611823920 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3611823920
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3316144710
Short name T1185
Test name
Test status
Simulation time 116882665418 ps
CPU time 104.4 seconds
Started May 23 12:47:04 PM PDT 24
Finished May 23 12:48:49 PM PDT 24
Peak memory 200304 kb
Host smart-292de1d1-28e0-488f-8a68-06cd846b8819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316144710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3316144710
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.945255164
Short name T4
Test name
Test status
Simulation time 9668817136 ps
CPU time 80.17 seconds
Started May 23 12:47:06 PM PDT 24
Finished May 23 12:48:27 PM PDT 24
Peak memory 216196 kb
Host smart-8983439e-ca78-476e-aa54-5d2171780cde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945255164 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.945255164
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3565274907
Short name T529
Test name
Test status
Simulation time 80098824257 ps
CPU time 28.22 seconds
Started May 23 12:47:01 PM PDT 24
Finished May 23 12:47:30 PM PDT 24
Peak memory 200276 kb
Host smart-a137c36e-657c-488f-b329-4f3994a13c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565274907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3565274907
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.782904108
Short name T506
Test name
Test status
Simulation time 15371110019 ps
CPU time 24.86 seconds
Started May 23 12:47:05 PM PDT 24
Finished May 23 12:47:31 PM PDT 24
Peak memory 200276 kb
Host smart-7ab1c93b-f768-4590-a3ab-959a3977bcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782904108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.782904108
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1148722324
Short name T222
Test name
Test status
Simulation time 85026845696 ps
CPU time 268.09 seconds
Started May 23 12:47:05 PM PDT 24
Finished May 23 12:51:34 PM PDT 24
Peak memory 215816 kb
Host smart-25bf2218-af23-47d9-8fd7-1bd5bc0279a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148722324 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1148722324
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1259095052
Short name T611
Test name
Test status
Simulation time 65542250923 ps
CPU time 12.52 seconds
Started May 23 12:47:04 PM PDT 24
Finished May 23 12:47:18 PM PDT 24
Peak memory 200348 kb
Host smart-3215b903-46f3-47bd-ab11-2a31dd0c597c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259095052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1259095052
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1038709956
Short name T32
Test name
Test status
Simulation time 22291819019 ps
CPU time 256.72 seconds
Started May 23 12:47:03 PM PDT 24
Finished May 23 12:51:21 PM PDT 24
Peak memory 217092 kb
Host smart-9566e045-bd08-4c48-9dbe-6f8cebe22b50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038709956 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1038709956
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1330791165
Short name T133
Test name
Test status
Simulation time 22413432524 ps
CPU time 23.27 seconds
Started May 23 12:47:03 PM PDT 24
Finished May 23 12:47:28 PM PDT 24
Peak memory 200356 kb
Host smart-a5523011-3ebf-4828-8f3c-980ed582924f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330791165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1330791165
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2419020073
Short name T328
Test name
Test status
Simulation time 25951711603 ps
CPU time 312.71 seconds
Started May 23 12:47:04 PM PDT 24
Finished May 23 12:52:18 PM PDT 24
Peak memory 216820 kb
Host smart-d3f95b96-5c08-4cef-a856-935700c6fb83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419020073 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2419020073
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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