Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	114393	1			T1	31		T2	138		T3	2
all_values[1]	114393	1			T1	31		T2	138		T3	2
all_values[2]	114393	1			T1	31		T2	138		T3	2
all_values[3]	114393	1			T1	31		T2	138		T3	2
all_values[4]	114393	1			T1	31		T2	138		T3	2
all_values[5]	114393	1			T1	31		T2	138		T3	2
all_values[6]	114393	1			T1	31		T2	138		T3	2
all_values[7]	114393	1			T1	31		T2	138		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

456835

1

T1

93

T2

423

T3

16

auto[1]

458309

1

T1

155

T2

681

T4

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

857654

1

T1

208

T2

997

T3

13

auto[1]

57490

1

T1

40

T2

107

T3

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	34515	1			T5	8		T6	16		T7	22
all_values[0]	auto[0]	auto[1]	23480	1			T1	12		T2	1		T3	2
all_values[0]	auto[1]	auto[0]	34216	1			T2	39		T9	4		T10	12
all_values[0]	auto[1]	auto[1]	22182	1			T1	19		T2	98		T6	6
all_values[1]	auto[0]	auto[0]	57039	1			T1	11		T2	110		T3	2
all_values[1]	auto[0]	auto[1]	1542	1			T6	1		T10	10		T12	3
all_values[1]	auto[1]	auto[0]	53952	1			T1	18		T2	28		T5	11
all_values[1]	auto[1]	auto[1]	1860	1			T1	2		T6	1		T17	4
all_values[2]	auto[0]	auto[0]	51686	1			T1	19		T2	107		T3	1
all_values[2]	auto[0]	auto[1]	2893	1			T2	4		T3	1		T5	1
all_values[2]	auto[1]	auto[0]	57264	1			T1	12		T2	23		T4	1
all_values[2]	auto[1]	auto[1]	2550	1			T2	4		T5	2		T6	11
all_values[3]	auto[0]	auto[0]	56603	1			T1	11		T2	6		T3	2
all_values[3]	auto[0]	auto[1]	312	1			T15	2		T14	3		T25	2
all_values[3]	auto[1]	auto[0]	57161	1			T1	19		T2	132		T5	11
all_values[3]	auto[1]	auto[1]	317	1			T1	1		T15	2		T13	2
all_values[4]	auto[0]	auto[0]	57209	1			T1	6		T2	35		T3	2
all_values[4]	auto[0]	auto[1]	578	1			T1	6		T15	5		T14	8
all_values[4]	auto[1]	auto[0]	56202	1			T1	19		T2	103		T5	3
all_values[4]	auto[1]	auto[1]	404	1			T15	1		T14	12		T24	1
all_values[5]	auto[0]	auto[0]	57567	1			T1	8		T2	27		T3	2
all_values[5]	auto[0]	auto[1]	177	1			T15	1		T25	1		T92	3
all_values[5]	auto[1]	auto[0]	56470	1			T1	23		T2	111		T5	6
all_values[5]	auto[1]	auto[1]	179	1			T15	3		T14	2		T25	1
all_values[6]	auto[0]	auto[0]	56721	1			T1	12		T2	99		T3	2
all_values[6]	auto[0]	auto[1]	182	1			T15	3		T14	3		T92	4
all_values[6]	auto[1]	auto[0]	57313	1			T1	19		T2	39		T4	1
all_values[6]	auto[1]	auto[1]	177	1			T15	5		T14	1		T92	1
all_values[7]	auto[0]	auto[0]	55999	1			T1	8		T2	34		T3	2
all_values[7]	auto[0]	auto[1]	332	1			T15	5		T24	2		T156	2
all_values[7]	auto[1]	auto[0]	57737	1			T1	23		T2	104		T5	10
all_values[7]	auto[1]	auto[1]	325	1			T7	6		T17	4		T15	1