Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2571

1

T1

1

T2

1

T3

1

auto[UartRx]

2571

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4519	1			T1	2		T2	2		T3	2
values[1]	49	1			T25	2		T26	2		T39	1
values[2]	66	1			T154	1		T61	1		T170	1
values[3]	60	1			T40	1		T295	2		T159	2
values[4]	51	1			T25	4		T295	2		T159	1
values[5]	54	1			T25	2		T26	1		T27	1
values[6]	75	1			T27	1		T37	1		T38	2
values[7]	62	1			T25	2		T36	1		T38	1
values[8]	56	1			T36	1		T38	3		T39	3
values[9]	57	1			T38	2		T41	2		T42	1
values[10]	60	1			T25	1		T36	2		T37	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2358	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	11	1			T295	1		T113	1		T336	1
auto[UartTx]	values[2]	24	1			T154	1		T61	1		T337	2
auto[UartTx]	values[3]	18	1			T159	1		T187	1		T336	1
auto[UartTx]	values[4]	20	1			T25	2		T295	2		T159	1
auto[UartTx]	values[5]	20	1			T40	1		T41	1		T113	1
auto[UartTx]	values[6]	24	1			T37	1		T38	1		T42	2
auto[UartTx]	values[7]	24	1			T25	1		T36	1		T41	2
auto[UartTx]	values[8]	15	1			T38	1		T39	1		T64	1
auto[UartTx]	values[9]	22	1			T38	1		T327	1		T304	1
auto[UartTx]	values[10]	24	1			T25	1		T36	1		T38	1
auto[UartRx]	values[0]	2161	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	38	1			T25	2		T26	2		T39	1
auto[UartRx]	values[2]	42	1			T170	1		T337	2		T336	2
auto[UartRx]	values[3]	42	1			T40	1		T295	2		T159	1
auto[UartRx]	values[4]	31	1			T25	2		T310	1		T327	1
auto[UartRx]	values[5]	34	1			T25	2		T26	1		T27	1
auto[UartRx]	values[6]	51	1			T27	1		T38	1		T42	1
auto[UartRx]	values[7]	38	1			T25	1		T38	1		T41	1
auto[UartRx]	values[8]	41	1			T36	1		T38	2		T39	2
auto[UartRx]	values[9]	35	1			T38	1		T41	2		T42	1
auto[UartRx]	values[10]	36	1			T36	1		T37	1		T39	1