Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2437	1			T2	2		T4	3		T5	2
auto[BaudRate115200]	2103	1			T1	1		T2	1		T4	3
auto[BaudRate230400]	2193	1			T4	17		T5	1		T6	1
auto[BaudRate128Kbps]	2093	1			T1	2		T3	1		T4	9
auto[BaudRate256Kbps]	2376	1			T2	1		T3	1		T4	9
auto[BaudRate1Mbps]	2017	1			T2	1		T9	2		T16	3
auto[BaudRate1p5Mbps]	1428	1			T2	2		T5	1		T10	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1663	1			T1	3		T7	6		T278	9
freqs[25]	1619	1			T292	2		T24	1		T149	10
freqs[48]	483	1			T12	5		T265	10		T338	12
freqs[50]	526	1			T270	10		T58	6		T125	9
freqs[100]	1388	1			T2	7		T28	2		T51	7

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	231	1			T7	1		T278	2		T274	2
auto[BaudRate9600]	freqs[25]	263	1			T156	2		T26	4		T258	3
auto[BaudRate9600]	freqs[48]	88	1			T12	1		T338	6		T339	13
auto[BaudRate9600]	freqs[50]	87	1			T270	1		T306	1		T113	14
auto[BaudRate9600]	freqs[100]	221	1			T2	2		T28	1		T51	1
auto[BaudRate115200]	freqs[24]	249	1			T1	1		T7	2		T259	2
auto[BaudRate115200]	freqs[25]	201	1			T292	1		T24	1		T149	3
auto[BaudRate115200]	freqs[48]	57	1			T12	2		T265	1		T273	2
auto[BaudRate115200]	freqs[50]	78	1			T125	1		T113	19		T340	1
auto[BaudRate115200]	freqs[100]	198	1			T2	1		T15	1		T262	1
auto[BaudRate230400]	freqs[24]	272	1			T7	1		T259	4		T92	2
auto[BaudRate230400]	freqs[25]	269	1			T292	1		T149	2		T156	5
auto[BaudRate230400]	freqs[48]	69	1			T265	2		T273	2		T242	1
auto[BaudRate230400]	freqs[50]	59	1			T270	4		T125	1		T306	2
auto[BaudRate230400]	freqs[100]	200	1			T15	2		T262	1		T134	9
auto[BaudRate128Kbps]	freqs[24]	261	1			T1	2		T278	1		T259	1
auto[BaudRate128Kbps]	freqs[25]	233	1			T149	2		T26	1		T258	1
auto[BaudRate128Kbps]	freqs[48]	63	1			T265	1		T273	2		T242	1
auto[BaudRate128Kbps]	freqs[50]	61	1			T270	1		T125	2		T306	1
auto[BaudRate128Kbps]	freqs[100]	179	1			T51	2		T15	1		T262	1
auto[BaudRate256Kbps]	freqs[24]	250	1			T7	2		T278	1		T259	1
auto[BaudRate256Kbps]	freqs[25]	236	1			T149	2		T156	1		T264	1
auto[BaudRate256Kbps]	freqs[48]	55	1			T279	1		T273	2		T242	1
auto[BaudRate256Kbps]	freqs[50]	76	1			T125	2		T113	21		T340	1
auto[BaudRate256Kbps]	freqs[100]	208	1			T2	1		T28	1		T15	3
auto[BaudRate1Mbps]	freqs[24]	258	1			T278	1		T282	3		T92	1
auto[BaudRate1Mbps]	freqs[25]	284	1			T156	1		T264	4		T26	1
auto[BaudRate1Mbps]	freqs[48]	72	1			T265	3		T338	3		T279	4
auto[BaudRate1Mbps]	freqs[50]	73	1			T270	2		T58	3		T125	2
auto[BaudRate1Mbps]	freqs[100]	167	1			T2	1		T51	1		T15	3
auto[BaudRate1p5Mbps]	freqs[25]	133	1			T149	1		T264	1		T258	2
auto[BaudRate1p5Mbps]	freqs[48]	79	1			T12	2		T265	3		T338	3
auto[BaudRate1p5Mbps]	freqs[50]	92	1			T270	2		T58	3		T125	1
auto[BaudRate1p5Mbps]	freqs[100]	215	1			T2	2		T51	3		T15	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded