Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.45	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	7	123	94.62

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	7	123	94.62	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	30704092	1			T1	27		T2	265		T4	6
all_levels[1]	216950	1			T2	76		T5	1		T6	7
all_levels[2]	2724	1			T2	6		T6	6		T7	9
all_levels[3]	1215	1			T6	8		T7	7		T9	2
all_levels[4]	801	1			T7	4		T17	3		T52	1
all_levels[5]	592	1			T6	3		T7	2		T16	1
all_levels[6]	444	1			T7	1		T10	1		T52	2
all_levels[7]	393	1			T6	2		T7	1		T17	1
all_levels[8]	311	1			T6	3		T17	1		T15	2
all_levels[9]	257	1			T6	2		T10	1		T50	1
all_levels[10]	221	1			T6	1		T17	1		T15	1
all_levels[11]	189	1			T5	1		T10	3		T12	1
all_levels[12]	157	1			T6	1		T10	1		T17	2
all_levels[13]	160	1			T7	1		T17	1		T14	1
all_levels[14]	129	1			T10	1		T45	1		T141	4
all_levels[15]	126	1			T5	2		T142	1		T143	1
all_levels[16]	86	1			T5	1		T13	1		T25	1
all_levels[17]	107	1			T10	1		T17	2		T144	1
all_levels[18]	91	1			T5	3		T17	1		T26	1
all_levels[19]	58	1			T142	2		T145	1		T38	1
all_levels[20]	73	1			T142	1		T129	1		T132	2
all_levels[21]	59	1			T13	1		T146	1		T27	1
all_levels[22]	54	1			T10	1		T13	1		T142	1
all_levels[23]	65	1			T10	2		T13	3		T25	2
all_levels[24]	67	1			T10	1		T144	2		T134	1
all_levels[25]	55	1			T10	2		T17	1		T13	2
all_levels[26]	53	1			T10	2		T122	1		T147	2
all_levels[27]	41	1			T51	1		T129	1		T39	1
all_levels[28]	42	1			T123	1		T147	1		T148	1
all_levels[29]	46	1			T13	1		T144	1		T132	1
all_levels[30]	37	1			T17	2		T149	1		T122	1
all_levels[31]	45	1			T13	2		T135	1		T146	1
all_levels[32]	19	1			T25	1		T150	1		T151	2
all_levels[33]	32	1			T6	1		T38	1		T152	1
all_levels[34]	32	1			T118	2		T153	1		T154	1
all_levels[35]	34	1			T133	1		T38	1		T155	4
all_levels[36]	27	1			T156	1		T134	1		T122	1
all_levels[37]	24	1			T142	1		T156	1		T157	1
all_levels[38]	14	1			T122	1		T158	2		T113	1
all_levels[39]	26	1			T142	1		T134	1		T129	1
all_levels[40]	25	1			T13	2		T129	1		T154	1
all_levels[41]	15	1			T135	1		T59	1		T159	2
all_levels[42]	17	1			T160	1		T161	1		T162	3
all_levels[43]	18	1			T45	1		T41	1		T113	1
all_levels[44]	13	1			T157	3		T132	1		T163	1
all_levels[45]	4	1			T118	1		T164	1		T165	1
all_levels[46]	17	1			T166	1		T167	1		T150	1
all_levels[47]	19	1			T59	1		T163	1		T154	1
all_levels[48]	9	1			T41	1		T168	1		T169	1
all_levels[49]	13	1			T118	1		T170	1		T171	1
all_levels[50]	11	1			T145	1		T122	1		T147	1
all_levels[51]	20	1			T145	1		T157	3		T118	1
all_levels[52]	10	1			T134	1		T147	1		T172	1
all_levels[53]	5	1			T122	1		T166	2		T173	1
all_levels[54]	19	1			T174	1		T175	2		T176	1
all_levels[55]	9	1			T133	1		T168	1		T177	1
all_levels[56]	16	1			T178	1		T179	5		T180	1
all_levels[57]	8	1			T14	2		T181	1		T182	1
all_levels[58]	14	1			T38	1		T183	2		T150	1
all_levels[59]	6	1			T38	1		T184	2		T185	1
all_levels[60]	5	1			T135	1		T163	1		T186	1
all_levels[61]	11	1			T15	1		T156	1		T134	1
all_levels[62]	6	1			T187	1		T188	1		T189	1
all_levels[63]	9	1			T190	1		T191	1		T192	2
all_levels[64]	119	1			T38	2		T39	3		T118	3

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30925770

1

T2

340

T5

20

T6

55

auto[1]

4596

1

T1

27

T2

7

T4

6

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	7	123	94.62	7

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[26]]	[auto[1]]	0	1	1
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[60] , all_levels[61] , all_levels[62]]	[auto[1]]	--	--	3

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	30699943	1			T2	258		T5	14		T6	24
all_levels[0]	auto[1]	4149	1			T1	27		T2	7		T4	6
all_levels[1]	auto[0]	216895	1			T2	76		T5	1		T6	7
all_levels[1]	auto[1]	55	1			T56	1		T193	1		T194	1
all_levels[2]	auto[0]	2691	1			T2	6		T6	6		T7	9
all_levels[2]	auto[1]	33	1			T25	1		T146	1		T195	1
all_levels[3]	auto[0]	1172	1			T6	5		T7	7		T9	2
all_levels[3]	auto[1]	43	1			T6	3		T157	1		T178	1
all_levels[4]	auto[0]	770	1			T7	4		T17	3		T52	1
all_levels[4]	auto[1]	31	1			T142	2		T21	1		T196	1
all_levels[5]	auto[0]	581	1			T6	3		T7	2		T16	1
all_levels[5]	auto[1]	11	1			T144	1		T25	1		T197	3
all_levels[6]	auto[0]	429	1			T7	1		T10	1		T52	2
all_levels[6]	auto[1]	15	1			T193	2		T198	2		T199	1
all_levels[7]	auto[0]	373	1			T6	2		T7	1		T17	1
all_levels[7]	auto[1]	20	1			T45	2		T200	1		T201	1
all_levels[8]	auto[0]	302	1			T6	3		T17	1		T15	2
all_levels[8]	auto[1]	9	1			T202	1		T203	2		T204	3
all_levels[9]	auto[0]	243	1			T6	2		T10	1		T50	1
all_levels[9]	auto[1]	14	1			T141	1		T194	2		T159	1
all_levels[10]	auto[0]	203	1			T6	1		T17	1		T15	1
all_levels[10]	auto[1]	18	1			T194	2		T202	2		T205	1
all_levels[11]	auto[0]	185	1			T5	1		T10	3		T12	1
all_levels[11]	auto[1]	4	1			T206	2		T207	1		T208	1
all_levels[12]	auto[0]	152	1			T6	1		T10	1		T17	2
all_levels[12]	auto[1]	5	1			T59	1		T209	2		T210	1
all_levels[13]	auto[0]	136	1			T7	1		T17	1		T14	1
all_levels[13]	auto[1]	24	1			T211	2		T212	1		T213	1
all_levels[14]	auto[0]	121	1			T10	1		T45	1		T141	4
all_levels[14]	auto[1]	8	1			T214	1		T162	1		T215	1
all_levels[15]	auto[0]	116	1			T5	2		T142	1		T143	1
all_levels[15]	auto[1]	10	1			T25	1		T146	2		T126	1
all_levels[16]	auto[0]	84	1			T5	1		T13	1		T25	1
all_levels[16]	auto[1]	2	1			T151	1		T216	1		-	-
all_levels[17]	auto[0]	98	1			T10	1		T17	2		T144	1
all_levels[17]	auto[1]	9	1			T146	1		T217	2		T218	2
all_levels[18]	auto[0]	81	1			T5	1		T17	1		T26	1
all_levels[18]	auto[1]	10	1			T5	2		T69	1		T219	3
all_levels[19]	auto[0]	56	1			T142	2		T145	1		T38	1
all_levels[19]	auto[1]	2	1			T110	1		T220	1		-	-
all_levels[20]	auto[0]	65	1			T142	1		T129	1		T132	2
all_levels[20]	auto[1]	8	1			T221	1		T218	1		T222	2
all_levels[21]	auto[0]	49	1			T13	1		T146	1		T27	1
all_levels[21]	auto[1]	10	1			T223	2		T224	2		T225	2
all_levels[22]	auto[0]	52	1			T10	1		T13	1		T142	1
all_levels[22]	auto[1]	2	1			T192	1		T151	1		-	-
all_levels[23]	auto[0]	60	1			T10	1		T13	3		T25	1
all_levels[23]	auto[1]	5	1			T10	1		T25	1		T226	1
all_levels[24]	auto[0]	61	1			T10	1		T144	1		T134	1
all_levels[24]	auto[1]	6	1			T144	1		T227	2		T174	1
all_levels[25]	auto[0]	52	1			T10	2		T17	1		T13	2
all_levels[25]	auto[1]	3	1			T228	1		T110	2		-	-
all_levels[26]	auto[0]	53	1			T10	2		T122	1		T147	2
all_levels[27]	auto[0]	39	1			T51	1		T129	1		T39	1
all_levels[27]	auto[1]	2	1			T229	2		-	-		-	-
all_levels[28]	auto[0]	40	1			T123	1		T147	1		T148	1
all_levels[28]	auto[1]	2	1			T230	2		-	-		-	-
all_levels[29]	auto[0]	45	1			T13	1		T144	1		T132	1
all_levels[29]	auto[1]	1	1			T231	1		-	-		-	-
all_levels[30]	auto[0]	34	1			T17	2		T149	1		T122	1
all_levels[30]	auto[1]	3	1			T232	1		T233	2		-	-
all_levels[31]	auto[0]	41	1			T13	2		T135	1		T146	1
all_levels[31]	auto[1]	4	1			T167	1		T234	2		T235	1
all_levels[32]	auto[0]	17	1			T25	1		T150	1		T151	1
all_levels[32]	auto[1]	2	1			T151	1		T236	1		-	-
all_levels[33]	auto[0]	28	1			T6	1		T38	1		T152	1
all_levels[33]	auto[1]	4	1			T166	2		T237	2		-	-
all_levels[34]	auto[0]	27	1			T118	2		T153	1		T154	1
all_levels[34]	auto[1]	5	1			T186	2		T238	2		T169	1
all_levels[35]	auto[0]	26	1			T133	1		T38	1		T155	1
all_levels[35]	auto[1]	8	1			T155	3		T239	3		T240	2
all_levels[36]	auto[0]	26	1			T156	1		T134	1		T122	1
all_levels[36]	auto[1]	1	1			T241	1		-	-		-	-
all_levels[37]	auto[0]	23	1			T142	1		T156	1		T157	1
all_levels[37]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[38]	auto[0]	12	1			T122	1		T158	1		T113	1
all_levels[38]	auto[1]	2	1			T158	1		T243	1		-	-
all_levels[39]	auto[0]	22	1			T142	1		T134	1		T129	1
all_levels[39]	auto[1]	4	1			T162	2		T244	1		T245	1
all_levels[40]	auto[0]	23	1			T13	2		T129	1		T154	1
all_levels[40]	auto[1]	2	1			T174	1		T246	1		-	-
all_levels[41]	auto[0]	14	1			T135	1		T59	1		T159	1
all_levels[41]	auto[1]	1	1			T159	1		-	-		-	-
all_levels[42]	auto[0]	12	1			T160	1		T161	1		T162	1
all_levels[42]	auto[1]	5	1			T162	2		T247	1		T219	2
all_levels[43]	auto[0]	17	1			T45	1		T41	1		T113	1
all_levels[43]	auto[1]	1	1			T228	1		-	-		-	-
all_levels[44]	auto[0]	11	1			T157	1		T132	1		T163	1
all_levels[44]	auto[1]	2	1			T157	2		-	-		-	-
all_levels[45]	auto[0]	4	1			T118	1		T164	1		T165	1
all_levels[46]	auto[0]	15	1			T166	1		T167	1		T150	1
all_levels[46]	auto[1]	2	1			T248	1		T68	1		-	-
all_levels[47]	auto[0]	18	1			T59	1		T163	1		T154	1
all_levels[47]	auto[1]	1	1			T249	1		-	-		-	-
all_levels[48]	auto[0]	8	1			T41	1		T168	1		T169	1
all_levels[48]	auto[1]	1	1			T250	1		-	-		-	-
all_levels[49]	auto[0]	12	1			T118	1		T170	1		T171	1
all_levels[49]	auto[1]	1	1			T232	1		-	-		-	-
all_levels[50]	auto[0]	11	1			T145	1		T122	1		T147	1
all_levels[51]	auto[0]	17	1			T145	1		T157	1		T118	1
all_levels[51]	auto[1]	3	1			T157	2		T251	1		-	-
all_levels[52]	auto[0]	10	1			T134	1		T147	1		T172	1
all_levels[53]	auto[0]	4	1			T122	1		T166	1		T173	1
all_levels[53]	auto[1]	1	1			T166	1		-	-		-	-
all_levels[54]	auto[0]	16	1			T174	1		T175	2		T176	1
all_levels[54]	auto[1]	3	1			T233	1		T252	2		-	-
all_levels[55]	auto[0]	8	1			T133	1		T168	1		T177	1
all_levels[55]	auto[1]	1	1			T253	1		-	-		-	-
all_levels[56]	auto[0]	9	1			T178	1		T179	1		T180	1
all_levels[56]	auto[1]	7	1			T179	4		T254	1		T255	2
all_levels[57]	auto[0]	7	1			T14	1		T181	1		T182	1
all_levels[57]	auto[1]	1	1			T14	1		-	-		-	-
all_levels[58]	auto[0]	9	1			T38	1		T183	1		T150	1
all_levels[58]	auto[1]	5	1			T183	1		T256	1		T257	2
all_levels[59]	auto[0]	5	1			T38	1		T184	1		T185	1
all_levels[59]	auto[1]	1	1			T184	1		-	-		-	-
all_levels[60]	auto[0]	5	1			T135	1		T163	1		T186	1
all_levels[61]	auto[0]	11	1			T15	1		T156	1		T134	1
all_levels[62]	auto[0]	6	1			T187	1		T188	1		T189	1
all_levels[63]	auto[0]	8	1			T190	1		T191	1		T192	1
all_levels[63]	auto[1]	1	1			T192	1		-	-		-	-
all_levels[64]	auto[0]	107	1			T38	2		T39	2		T118	3
all_levels[64]	auto[1]	12	1			T39	1		T188	3		T160	1