Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	114393	1			T1	31		T2	138		T3	2
all_pins[1]	114393	1			T1	31		T2	138		T3	2
all_pins[2]	114393	1			T1	31		T2	138		T3	2
all_pins[3]	114393	1			T1	31		T2	138		T3	2
all_pins[4]	114393	1			T1	31		T2	138		T3	2
all_pins[5]	114393	1			T1	31		T2	138		T3	2
all_pins[6]	114393	1			T1	31		T2	138		T3	2
all_pins[7]	114393	1			T1	31		T2	138		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	886228	1			T1	225		T2	1002		T3	16
values[0x1]	28916	1			T1	23		T2	102		T5	2
transitions[0x0=>0x1]	27576	1			T1	23		T2	102		T5	2
transitions[0x1=>0x0]	27124	1			T1	23		T2	101		T5	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	92150	1			T1	12		T2	40		T3	2
all_pins[0]	values[0x1]	22243	1			T1	19		T2	98		T6	6
all_pins[0]	transitions[0x0=>0x1]	21471	1			T1	19		T2	98		T6	6
all_pins[0]	transitions[0x1=>0x0]	1091	1			T1	2		T6	1		T17	4
all_pins[1]	values[0x0]	112530	1			T1	29		T2	138		T3	2
all_pins[1]	values[0x1]	1863	1			T1	2		T6	1		T17	4
all_pins[1]	transitions[0x0=>0x1]	1742	1			T1	2		T6	1		T17	4
all_pins[1]	transitions[0x1=>0x0]	2487	1			T2	4		T5	2		T6	11
all_pins[2]	values[0x0]	111785	1			T1	31		T2	134		T3	2
all_pins[2]	values[0x1]	2608	1			T2	4		T5	2		T6	11
all_pins[2]	transitions[0x0=>0x1]	2543	1			T2	4		T5	2		T6	11
all_pins[2]	transitions[0x1=>0x0]	252	1			T1	1		T15	2		T13	2
all_pins[3]	values[0x0]	114076	1			T1	30		T2	138		T3	2
all_pins[3]	values[0x1]	317	1			T1	1		T15	2		T13	2
all_pins[3]	transitions[0x0=>0x1]	255	1			T1	1		T15	2		T13	2
all_pins[3]	transitions[0x1=>0x0]	342	1			T15	1		T14	12		T24	1
all_pins[4]	values[0x0]	113989	1			T1	31		T2	138		T3	2
all_pins[4]	values[0x1]	404	1			T15	1		T14	12		T24	1
all_pins[4]	transitions[0x0=>0x1]	333	1			T14	10		T24	1		T25	1
all_pins[4]	transitions[0x1=>0x0]	162	1			T1	1		T15	2		T25	1
all_pins[5]	values[0x0]	114160	1			T1	30		T2	138		T3	2
all_pins[5]	values[0x1]	233	1			T1	1		T15	3		T14	2
all_pins[5]	transitions[0x0=>0x1]	182	1			T1	1		T15	3		T14	2
all_pins[5]	transitions[0x1=>0x0]	872	1			T6	1		T10	11		T16	1
all_pins[6]	values[0x0]	113470	1			T1	31		T2	138		T3	2
all_pins[6]	values[0x1]	923	1			T6	1		T10	11		T16	1
all_pins[6]	transitions[0x0=>0x1]	880	1			T6	1		T10	11		T16	1
all_pins[6]	transitions[0x1=>0x0]	282	1			T7	6		T17	4		T14	5
all_pins[7]	values[0x0]	114068	1			T1	31		T2	138		T3	2
all_pins[7]	values[0x1]	325	1			T7	6		T17	4		T15	1
all_pins[7]	transitions[0x0=>0x1]	170	1			T7	6		T17	4		T15	1
all_pins[7]	transitions[0x1=>0x0]	21636	1			T1	19		T2	97		T6	5