Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6970419	1			T1	24		T2	234		T5	6
all_levels[1]	1367544	1			T2	2		T5	2		T9	8
all_levels[2]	550388	1			T2	4		T6	3		T9	4
all_levels[3]	360805	1			T2	5		T6	1		T7	1
all_levels[4]	293521	1			T7	2		T12	22		T16	2
all_levels[5]	277659	1			T2	1		T6	2		T7	3
all_levels[6]	214128	1			T2	14		T7	1		T9	7
all_levels[7]	564327	1			T2	2		T6	1		T7	2
all_levels[8]	274506	1			T2	3		T6	2		T7	2
all_levels[9]	335128	1			T2	7		T5	2		T9	2
all_levels[10]	263562	1			T2	5		T5	2		T7	2
all_levels[11]	212581	1			T2	3		T6	2		T7	4
all_levels[12]	272227	1			T2	3		T7	3		T12	8
all_levels[13]	266074	1			T2	4		T12	13		T16	4
all_levels[14]	234410	1			T2	5		T6	2		T7	2
all_levels[15]	301479	1			T2	10		T6	1		T7	1
all_levels[16]	484478	1			T2	7		T9	2		T12	7
all_levels[17]	707021	1			T2	2		T9	14		T12	4
all_levels[18]	248171	1			T2	2		T6	2		T12	2
all_levels[19]	259134	1			T2	30		T6	1		T12	2
all_levels[20]	253680	1			T2	1		T7	2		T12	10
all_levels[21]	443223	1			T2	1		T6	1		T17	93
all_levels[22]	228127	1			T16	3		T17	94		T51	7
all_levels[23]	195272	1			T17	88		T53	327		T15	44
all_levels[24]	254085	1			T7	2		T17	85		T53	327
all_levels[25]	321933	1			T5	6		T7	95		T17	83
all_levels[26]	611733	1			T10	2		T16	2		T17	90
all_levels[27]	328603	1			T16	1		T17	95		T53	328
all_levels[28]	372137	1			T16	2		T17	115		T53	327
all_levels[29]	197463	1			T7	1		T9	1		T17	93
all_levels[30]	304320	1			T17	98		T53	327		T15	45
all_levels[31]	669919	1			T17	1595		T53	1411		T15	532
all_levels[32]	12291794	1			T5	8		T7	2		T9	37

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30925770

1

T2

340

T5

20

T6

55

auto[1]

4081

1

T1

24

T2

5

T5

6

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6968257	1			T2	230		T5	5		T6	38
all_levels[0]	auto[1]	2162	1			T1	24		T2	4		T5	1
all_levels[1]	auto[0]	1367252	1			T2	2		T5	2		T9	8
all_levels[1]	auto[1]	292	1			T10	1		T17	1		T144	1
all_levels[2]	auto[0]	550340	1			T2	4		T6	2		T9	4
all_levels[2]	auto[1]	48	1			T6	1		T10	3		T14	2
all_levels[3]	auto[0]	360678	1			T2	5		T6	1		T7	1
all_levels[3]	auto[1]	127	1			T49	7		T154	16		T315	1
all_levels[4]	auto[0]	293491	1			T7	2		T12	22		T16	2
all_levels[4]	auto[1]	30	1			T142	2		T149	1		T342	1
all_levels[5]	auto[0]	277628	1			T2	1		T6	2		T7	3
all_levels[5]	auto[1]	31	1			T141	1		T343	2		T344	1
all_levels[6]	auto[0]	214075	1			T2	13		T7	1		T9	7
all_levels[6]	auto[1]	53	1			T2	1		T45	1		T194	1
all_levels[7]	auto[0]	564148	1			T2	2		T6	1		T7	2
all_levels[7]	auto[1]	179	1			T8	13		T10	1		T227	1
all_levels[8]	auto[0]	274489	1			T2	3		T6	2		T7	2
all_levels[8]	auto[1]	17	1			T262	1		T193	2		T172	1
all_levels[9]	auto[0]	335094	1			T2	7		T5	2		T9	2
all_levels[9]	auto[1]	34	1			T21	3		T163	1		T195	1
all_levels[10]	auto[0]	263531	1			T2	5		T5	1		T7	2
all_levels[10]	auto[1]	31	1			T5	1		T45	2		T200	1
all_levels[11]	auto[0]	212539	1			T2	3		T6	2		T7	4
all_levels[11]	auto[1]	42	1			T262	2		T59	1		T311	1
all_levels[12]	auto[0]	272210	1			T2	3		T7	3		T12	8
all_levels[12]	auto[1]	17	1			T17	1		T25	1		T345	1
all_levels[13]	auto[0]	266026	1			T2	4		T12	13		T16	4
all_levels[13]	auto[1]	48	1			T13	1		T262	2		T258	1
all_levels[14]	auto[0]	234380	1			T2	5		T6	2		T7	2
all_levels[14]	auto[1]	30	1			T157	1		T346	2		T192	6
all_levels[15]	auto[0]	301340	1			T2	10		T6	1		T7	1
all_levels[15]	auto[1]	139	1			T134	1		T146	1		T148	1
all_levels[16]	auto[0]	484463	1			T2	7		T9	2		T12	7
all_levels[16]	auto[1]	15	1			T13	2		T344	1		T347	1
all_levels[17]	auto[0]	707003	1			T2	2		T9	14		T12	4
all_levels[17]	auto[1]	18	1			T132	1		T298	1		T348	2
all_levels[18]	auto[0]	248143	1			T2	2		T6	2		T12	2
all_levels[18]	auto[1]	28	1			T349	1		T228	1		T350	1
all_levels[19]	auto[0]	259124	1			T2	30		T6	1		T12	2
all_levels[19]	auto[1]	10	1			T142	1		T263	1		T351	2
all_levels[20]	auto[0]	253656	1			T2	1		T7	2		T12	10
all_levels[20]	auto[1]	24	1			T270	1		T152	1		T202	2
all_levels[21]	auto[0]	443196	1			T2	1		T6	1		T17	93
all_levels[21]	auto[1]	27	1			T170	2		T199	1		T126	1
all_levels[22]	auto[0]	228109	1			T16	3		T17	94		T51	7
all_levels[22]	auto[1]	18	1			T25	1		T285	1		T206	2
all_levels[23]	auto[0]	195252	1			T17	88		T53	327		T15	44
all_levels[23]	auto[1]	20	1			T278	1		T327	1		T344	2
all_levels[24]	auto[0]	254068	1			T7	2		T17	85		T53	327
all_levels[24]	auto[1]	17	1			T157	1		T141	2		T352	1
all_levels[25]	auto[0]	321911	1			T5	4		T7	95		T17	83
all_levels[25]	auto[1]	22	1			T5	2		T45	1		T141	1
all_levels[26]	auto[0]	611713	1			T10	2		T16	2		T17	90
all_levels[26]	auto[1]	20	1			T157	1		T194	3		T353	1
all_levels[27]	auto[0]	328582	1			T16	1		T17	95		T53	328
all_levels[27]	auto[1]	21	1			T180	4		T326	1		T184	1
all_levels[28]	auto[0]	372125	1			T16	2		T17	115		T53	327
all_levels[28]	auto[1]	12	1			T193	1		T354	2		T337	1
all_levels[29]	auto[0]	197442	1			T7	1		T9	1		T17	93
all_levels[29]	auto[1]	21	1			T206	2		T354	1		T355	3
all_levels[30]	auto[0]	304305	1			T17	98		T53	327		T15	45
all_levels[30]	auto[1]	15	1			T226	1		T356	1		T357	1
all_levels[31]	auto[0]	669898	1			T17	1595		T53	1411		T15	532
all_levels[31]	auto[1]	21	1			T326	1		T328	1		T358	1
all_levels[32]	auto[0]	12291302	1			T5	6		T7	2		T9	36
all_levels[32]	auto[1]	492	1			T5	2		T9	1		T17	1