Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	812	1			T15	11		T14	4		T25	4
all_values[1]	812	1			T15	11		T14	4		T25	4
all_values[2]	812	1			T15	11		T14	4		T25	4
all_values[3]	812	1			T15	11		T14	4		T25	4
all_values[4]	812	1			T15	11		T14	4		T25	4
all_values[5]	812	1			T15	11		T14	4		T25	4
all_values[6]	812	1			T15	11		T14	4		T25	4
all_values[7]	812	1			T15	11		T14	4		T25	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3451

1

T15

54

T14

19

T25

15

auto[1]

3045

1

T15

34

T14

13

T25

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2456

1

T15

30

T14

10

T25

16

auto[1]

4040

1

T15

58

T14

22

T25

16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3855

1

T15

51

T14

19

T25

19

auto[1]

2641

1

T15

37

T14

13

T25

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	257	1			T15	5		T14	2		T25	1
all_values[0]	auto[0]	auto[1]	auto[1]	222	1			T15	3		T92	1		T36	4
all_values[0]	auto[1]	auto[0]	auto[1]	195	1			T15	2		T14	2		T25	2
all_values[0]	auto[1]	auto[1]	auto[1]	138	1			T15	1		T25	1		T92	4
all_values[1]	auto[0]	auto[0]	auto[0]	278	1			T15	3		T14	2		T92	1
all_values[1]	auto[0]	auto[1]	auto[0]	219	1			T15	1		T25	1		T92	3
all_values[1]	auto[1]	auto[0]	auto[1]	167	1			T15	3		T25	2		T92	2
all_values[1]	auto[1]	auto[1]	auto[1]	148	1			T15	4		T14	2		T25	1
all_values[2]	auto[0]	auto[0]	auto[0]	163	1			T15	3		T14	1		T25	1
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T15	1		T14	2		T92	1
all_values[2]	auto[0]	auto[1]	auto[0]	147	1			T15	3		T25	1		T92	2
all_values[2]	auto[0]	auto[1]	auto[1]	75	1			T15	1		T25	1		T36	1
all_values[2]	auto[1]	auto[0]	auto[1]	178	1			T15	3		T14	1		T92	1
all_values[2]	auto[1]	auto[1]	auto[1]	172	1			T25	1		T92	1		T36	3
all_values[3]	auto[0]	auto[0]	auto[0]	172	1			T15	3		T14	2		T92	1
all_values[3]	auto[0]	auto[0]	auto[1]	76	1			T15	1		T14	1		T25	1
all_values[3]	auto[0]	auto[1]	auto[0]	153	1			T15	3		T25	1		T92	1
all_values[3]	auto[0]	auto[1]	auto[1]	89	1			T92	1		T38	2		T39	1
all_values[3]	auto[1]	auto[0]	auto[1]	186	1			T15	2		T14	1		T25	2
all_values[3]	auto[1]	auto[1]	auto[1]	136	1			T15	2		T92	1		T36	2
all_values[4]	auto[0]	auto[0]	auto[0]	155	1			T15	1		T14	1		T25	1
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T15	2		T92	3		T38	1
all_values[4]	auto[0]	auto[1]	auto[0]	156	1			T15	3		T25	2		T36	6
all_values[4]	auto[0]	auto[1]	auto[1]	81	1			T14	1		T36	1		T38	3
all_values[4]	auto[1]	auto[0]	auto[1]	168	1			T15	3		T25	1		T92	2
all_values[4]	auto[1]	auto[1]	auto[1]	169	1			T15	2		T14	2		T92	1
all_values[5]	auto[0]	auto[0]	auto[0]	178	1			T15	1		T14	1		T36	3
all_values[5]	auto[0]	auto[0]	auto[1]	82	1			T15	1		T92	2		T36	4
all_values[5]	auto[0]	auto[1]	auto[0]	163	1			T15	4		T14	1		T25	1
all_values[5]	auto[0]	auto[1]	auto[1]	65	1			T15	1		T14	1		T39	2
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T15	2		T25	1		T92	2
all_values[5]	auto[1]	auto[1]	auto[1]	150	1			T15	2		T14	1		T25	2
all_values[6]	auto[0]	auto[0]	auto[0]	172	1			T25	2		T92	1		T36	6
all_values[6]	auto[0]	auto[0]	auto[1]	84	1			T15	3		T14	1		T92	2
all_values[6]	auto[0]	auto[1]	auto[0]	170	1			T25	2		T36	2		T38	2
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T15	2		T92	1		T36	1
all_values[6]	auto[1]	auto[0]	auto[1]	174	1			T15	6		T14	1		T92	2
all_values[6]	auto[1]	auto[1]	auto[1]	137	1			T14	2		T92	1		T36	3
all_values[7]	auto[0]	auto[0]	auto[0]	171	1			T15	3		T14	1		T25	1
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T15	1		T92	1		T36	3
all_values[7]	auto[0]	auto[1]	auto[0]	159	1			T15	2		T14	1		T25	3
all_values[7]	auto[0]	auto[1]	auto[1]	57	1			T14	1		T92	2		T39	2
all_values[7]	auto[1]	auto[0]	auto[1]	185	1			T15	5		T92	3		T36	2
all_values[7]	auto[1]	auto[1]	auto[1]	164	1			T14	1		T36	6		T38	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal