Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.28 99.27 97.95 100.00 98.80 100.00 99.66


Total test records in report: 1316
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T1255 /workspace/coverage/cover_reg_top/26.uart_intr_test.1192427339 May 26 01:01:25 PM PDT 24 May 26 01:01:27 PM PDT 24 143554708 ps
T98 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1511251378 May 26 01:01:15 PM PDT 24 May 26 01:01:17 PM PDT 24 73160229 ps
T1256 /workspace/coverage/cover_reg_top/44.uart_intr_test.288510333 May 26 01:01:30 PM PDT 24 May 26 01:01:31 PM PDT 24 12585889 ps
T1257 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3821331692 May 26 01:01:04 PM PDT 24 May 26 01:01:05 PM PDT 24 13868287 ps
T1258 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1663028780 May 26 01:00:56 PM PDT 24 May 26 01:00:58 PM PDT 24 107967117 ps
T1259 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3964039696 May 26 01:00:54 PM PDT 24 May 26 01:00:56 PM PDT 24 103644588 ps
T1260 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2865122167 May 26 01:01:06 PM PDT 24 May 26 01:01:08 PM PDT 24 12803265 ps
T1261 /workspace/coverage/cover_reg_top/16.uart_csr_rw.920679395 May 26 01:01:16 PM PDT 24 May 26 01:01:18 PM PDT 24 35191366 ps
T1262 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3386281269 May 26 01:00:56 PM PDT 24 May 26 01:00:58 PM PDT 24 25146022 ps
T1263 /workspace/coverage/cover_reg_top/4.uart_intr_test.3672337284 May 26 01:01:09 PM PDT 24 May 26 01:01:10 PM PDT 24 29174133 ps
T1264 /workspace/coverage/cover_reg_top/29.uart_intr_test.721139335 May 26 01:01:23 PM PDT 24 May 26 01:01:25 PM PDT 24 13796612 ps
T1265 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.853170059 May 26 01:01:15 PM PDT 24 May 26 01:01:18 PM PDT 24 283660909 ps
T1266 /workspace/coverage/cover_reg_top/7.uart_csr_rw.598172380 May 26 01:01:04 PM PDT 24 May 26 01:01:05 PM PDT 24 15757596 ps
T1267 /workspace/coverage/cover_reg_top/16.uart_tl_errors.2515577340 May 26 01:01:17 PM PDT 24 May 26 01:01:20 PM PDT 24 52163989 ps
T1268 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.111055345 May 26 01:01:29 PM PDT 24 May 26 01:01:31 PM PDT 24 248810973 ps
T1269 /workspace/coverage/cover_reg_top/13.uart_csr_rw.157307122 May 26 01:01:13 PM PDT 24 May 26 01:01:15 PM PDT 24 29003473 ps
T1270 /workspace/coverage/cover_reg_top/41.uart_intr_test.2700577853 May 26 01:01:25 PM PDT 24 May 26 01:01:27 PM PDT 24 45486690 ps
T1271 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1758667120 May 26 01:01:07 PM PDT 24 May 26 01:01:09 PM PDT 24 224828684 ps
T77 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1682193105 May 26 01:00:56 PM PDT 24 May 26 01:00:58 PM PDT 24 15841000 ps
T1272 /workspace/coverage/cover_reg_top/23.uart_intr_test.1002354002 May 26 01:01:30 PM PDT 24 May 26 01:01:31 PM PDT 24 26422009 ps
T1273 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.833528305 May 26 01:01:09 PM PDT 24 May 26 01:01:10 PM PDT 24 109215426 ps
T1274 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3814299376 May 26 01:01:15 PM PDT 24 May 26 01:01:17 PM PDT 24 50258993 ps
T1275 /workspace/coverage/cover_reg_top/8.uart_intr_test.874008979 May 26 01:01:08 PM PDT 24 May 26 01:01:09 PM PDT 24 38114155 ps
T1276 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.878944569 May 26 01:00:57 PM PDT 24 May 26 01:00:59 PM PDT 24 41097182 ps
T1277 /workspace/coverage/cover_reg_top/12.uart_intr_test.3583025201 May 26 01:01:16 PM PDT 24 May 26 01:01:17 PM PDT 24 18110822 ps
T1278 /workspace/coverage/cover_reg_top/7.uart_tl_errors.1733300798 May 26 01:01:05 PM PDT 24 May 26 01:01:07 PM PDT 24 33168310 ps
T1279 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.318800727 May 26 01:01:05 PM PDT 24 May 26 01:01:07 PM PDT 24 86305178 ps
T1280 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2542344343 May 26 01:00:56 PM PDT 24 May 26 01:00:59 PM PDT 24 181321813 ps
T1281 /workspace/coverage/cover_reg_top/5.uart_intr_test.3603937772 May 26 01:01:09 PM PDT 24 May 26 01:01:10 PM PDT 24 17887870 ps
T1282 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.605795036 May 26 01:01:05 PM PDT 24 May 26 01:01:07 PM PDT 24 54307893 ps
T1283 /workspace/coverage/cover_reg_top/36.uart_intr_test.2226415340 May 26 01:01:26 PM PDT 24 May 26 01:01:28 PM PDT 24 22284111 ps
T1284 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2483280255 May 26 01:00:56 PM PDT 24 May 26 01:00:59 PM PDT 24 63310641 ps
T1285 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3215408327 May 26 01:01:05 PM PDT 24 May 26 01:01:08 PM PDT 24 31554284 ps
T1286 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2170845729 May 26 01:00:55 PM PDT 24 May 26 01:00:57 PM PDT 24 13925758 ps
T1287 /workspace/coverage/cover_reg_top/13.uart_tl_errors.879288901 May 26 01:01:17 PM PDT 24 May 26 01:01:20 PM PDT 24 78959667 ps
T1288 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.11294258 May 26 01:00:57 PM PDT 24 May 26 01:00:59 PM PDT 24 14775399 ps
T1289 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3171536302 May 26 01:01:26 PM PDT 24 May 26 01:01:28 PM PDT 24 135120115 ps
T1290 /workspace/coverage/cover_reg_top/0.uart_csr_rw.3244578138 May 26 01:01:01 PM PDT 24 May 26 01:01:02 PM PDT 24 19384453 ps
T1291 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2283900523 May 26 01:00:56 PM PDT 24 May 26 01:00:59 PM PDT 24 91060216 ps
T1292 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4135405823 May 26 01:01:13 PM PDT 24 May 26 01:01:15 PM PDT 24 101690018 ps
T1293 /workspace/coverage/cover_reg_top/3.uart_tl_errors.864231118 May 26 01:00:56 PM PDT 24 May 26 01:00:59 PM PDT 24 113593213 ps
T1294 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2781210911 May 26 01:01:00 PM PDT 24 May 26 01:01:02 PM PDT 24 13454782 ps
T1295 /workspace/coverage/cover_reg_top/2.uart_intr_test.3893653290 May 26 01:00:56 PM PDT 24 May 26 01:00:58 PM PDT 24 28603933 ps
T1296 /workspace/coverage/cover_reg_top/33.uart_intr_test.3675907813 May 26 01:01:23 PM PDT 24 May 26 01:01:25 PM PDT 24 13796465 ps
T1297 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4233635724 May 26 01:01:24 PM PDT 24 May 26 01:01:26 PM PDT 24 29261421 ps
T1298 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1506042361 May 26 01:01:26 PM PDT 24 May 26 01:01:29 PM PDT 24 102909045 ps
T1299 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2986940562 May 26 01:01:06 PM PDT 24 May 26 01:01:08 PM PDT 24 37084863 ps
T1300 /workspace/coverage/cover_reg_top/40.uart_intr_test.3563160955 May 26 01:01:24 PM PDT 24 May 26 01:01:25 PM PDT 24 13240213 ps
T1301 /workspace/coverage/cover_reg_top/22.uart_intr_test.1693805487 May 26 01:01:22 PM PDT 24 May 26 01:01:23 PM PDT 24 14247442 ps
T1302 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3444525218 May 26 01:01:15 PM PDT 24 May 26 01:01:17 PM PDT 24 123800012 ps
T1303 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2501258111 May 26 01:00:56 PM PDT 24 May 26 01:01:00 PM PDT 24 674024159 ps
T1304 /workspace/coverage/cover_reg_top/32.uart_intr_test.1874331812 May 26 01:01:26 PM PDT 24 May 26 01:01:28 PM PDT 24 16607524 ps
T78 /workspace/coverage/cover_reg_top/8.uart_csr_rw.244445342 May 26 01:01:05 PM PDT 24 May 26 01:01:07 PM PDT 24 210210864 ps
T140 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3224530567 May 26 01:01:11 PM PDT 24 May 26 01:01:13 PM PDT 24 438055518 ps
T1305 /workspace/coverage/cover_reg_top/46.uart_intr_test.3617710414 May 26 01:01:25 PM PDT 24 May 26 01:01:27 PM PDT 24 53987655 ps
T1306 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1625546230 May 26 01:01:16 PM PDT 24 May 26 01:01:18 PM PDT 24 113661930 ps
T1307 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2379331384 May 26 01:01:24 PM PDT 24 May 26 01:01:26 PM PDT 24 21843146 ps
T1308 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3278294651 May 26 01:01:04 PM PDT 24 May 26 01:01:06 PM PDT 24 45875681 ps
T1309 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4286299891 May 26 01:01:05 PM PDT 24 May 26 01:01:07 PM PDT 24 1084550004 ps
T1310 /workspace/coverage/cover_reg_top/1.uart_tl_errors.198716416 May 26 01:00:55 PM PDT 24 May 26 01:00:59 PM PDT 24 156293491 ps
T1311 /workspace/coverage/cover_reg_top/27.uart_intr_test.3790834046 May 26 01:01:30 PM PDT 24 May 26 01:01:31 PM PDT 24 32639735 ps
T1312 /workspace/coverage/cover_reg_top/6.uart_csr_rw.3177412056 May 26 01:01:08 PM PDT 24 May 26 01:01:10 PM PDT 24 25709714 ps
T1313 /workspace/coverage/cover_reg_top/5.uart_csr_rw.2689879085 May 26 01:01:04 PM PDT 24 May 26 01:01:05 PM PDT 24 95929825 ps
T1314 /workspace/coverage/cover_reg_top/11.uart_intr_test.2133438899 May 26 01:01:17 PM PDT 24 May 26 01:01:18 PM PDT 24 20200329 ps
T1315 /workspace/coverage/cover_reg_top/31.uart_intr_test.1646706916 May 26 01:01:26 PM PDT 24 May 26 01:01:28 PM PDT 24 11985079 ps
T1316 /workspace/coverage/cover_reg_top/5.uart_tl_errors.710130182 May 26 01:01:09 PM PDT 24 May 26 01:01:12 PM PDT 24 39251269 ps

Test location /workspace/coverage/default/180.uart_fifo_reset.365867397
Short name T5
Test name
Test status
Simulation time 11453427018 ps
CPU time 25.32 seconds
Started May 26 02:16:51 PM PDT 24
Finished May 26 02:17:17 PM PDT 24
Peak memory 200584 kb
Host smart-bbab5420-a8be-4a82-9c25-8f8413980d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365867397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.365867397
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1268501108
Short name T25
Test name
Test status
Simulation time 121694611866 ps
CPU time 2149.52 seconds
Started May 26 02:16:21 PM PDT 24
Finished May 26 02:52:12 PM PDT 24
Peak memory 233640 kb
Host smart-892de428-2cad-40d5-911d-485eb10dd1eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268501108 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1268501108
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all.2842556405
Short name T17
Test name
Test status
Simulation time 484302939195 ps
CPU time 877.64 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:29:59 PM PDT 24
Peak memory 200856 kb
Host smart-1f8f0bf8-f0ad-446e-981c-450fb78fe238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842556405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2842556405
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1674970030
Short name T38
Test name
Test status
Simulation time 356001619204 ps
CPU time 1267.06 seconds
Started May 26 02:15:57 PM PDT 24
Finished May 26 02:37:05 PM PDT 24
Peak memory 225480 kb
Host smart-448da92d-ab88-4c4f-9f3a-4b68868bf366
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674970030 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1674970030
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all.3720270358
Short name T21
Test name
Test status
Simulation time 391409308235 ps
CPU time 33.12 seconds
Started May 26 02:14:00 PM PDT 24
Finished May 26 02:14:34 PM PDT 24
Peak memory 200480 kb
Host smart-cf0bcf8d-983d-4b2c-a992-3f9e7e33f967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720270358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3720270358
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all.724316993
Short name T157
Test name
Test status
Simulation time 96395990989 ps
CPU time 528.11 seconds
Started May 26 02:14:15 PM PDT 24
Finished May 26 02:23:04 PM PDT 24
Peak memory 200552 kb
Host smart-1e7f5347-8159-4030-ad2e-007ea322ab6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724316993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.724316993
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all.2993300694
Short name T134
Test name
Test status
Simulation time 298804383658 ps
CPU time 580.29 seconds
Started May 26 02:13:59 PM PDT 24
Finished May 26 02:23:40 PM PDT 24
Peak memory 208992 kb
Host smart-ce5ab344-e6fc-4b17-b535-a1760d6c1661
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993300694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2993300694
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2706024299
Short name T154
Test name
Test status
Simulation time 368235528634 ps
CPU time 1282.7 seconds
Started May 26 02:16:20 PM PDT 24
Finished May 26 02:37:44 PM PDT 24
Peak memory 228748 kb
Host smart-92070ab5-143c-4dd7-a45a-64dc0e25fbdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706024299 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2706024299
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1955452879
Short name T327
Test name
Test status
Simulation time 751695066564 ps
CPU time 1260.1 seconds
Started May 26 02:16:20 PM PDT 24
Finished May 26 02:37:21 PM PDT 24
Peak memory 226456 kb
Host smart-cdc93690-1f61-4c3d-9261-186bbf694aeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955452879 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1955452879
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3845087745
Short name T64
Test name
Test status
Simulation time 201418318850 ps
CPU time 837.95 seconds
Started May 26 02:13:06 PM PDT 24
Finished May 26 02:27:06 PM PDT 24
Peak memory 225428 kb
Host smart-318e763b-2d18-4602-8d37-8da1e65e02f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845087745 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3845087745
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all.85972872
Short name T180
Test name
Test status
Simulation time 944711625911 ps
CPU time 97.58 seconds
Started May 26 02:12:44 PM PDT 24
Finished May 26 02:14:22 PM PDT 24
Peak memory 200488 kb
Host smart-7a067cec-06d9-4415-b2dc-09553d725ef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85972872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.85972872
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2124835019
Short name T102
Test name
Test status
Simulation time 138263752 ps
CPU time 0.83 seconds
Started May 26 02:12:41 PM PDT 24
Finished May 26 02:12:43 PM PDT 24
Peak memory 218992 kb
Host smart-c4ae1400-0e89-49c8-b503-cbd4eaa7b1db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124835019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2124835019
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/18.uart_alert_test.2735888649
Short name T31
Test name
Test status
Simulation time 42484978 ps
CPU time 0.57 seconds
Started May 26 02:13:36 PM PDT 24
Finished May 26 02:13:38 PM PDT 24
Peak memory 195884 kb
Host smart-a113ce44-afd3-4df3-90b6-246fd93fc4f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735888649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2735888649
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2230119507
Short name T288
Test name
Test status
Simulation time 301666864665 ps
CPU time 133.81 seconds
Started May 26 02:15:43 PM PDT 24
Finished May 26 02:17:58 PM PDT 24
Peak memory 200472 kb
Host smart-2e621085-a4c1-4fd1-80e9-4a58e749e29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230119507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2230119507
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.434479729
Short name T6
Test name
Test status
Simulation time 167967149999 ps
CPU time 47.48 seconds
Started May 26 02:16:52 PM PDT 24
Finished May 26 02:17:40 PM PDT 24
Peak memory 200484 kb
Host smart-dc424668-feed-417a-ac64-38f151b0fc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434479729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.434479729
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.2015585127
Short name T122
Test name
Test status
Simulation time 201047454090 ps
CPU time 98.6 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:14:56 PM PDT 24
Peak memory 200380 kb
Host smart-99114e32-1cca-438d-b420-4b4390a1ae76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015585127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2015585127
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.931266293
Short name T142
Test name
Test status
Simulation time 66041875875 ps
CPU time 90.61 seconds
Started May 26 02:17:24 PM PDT 24
Finished May 26 02:18:55 PM PDT 24
Peak memory 200548 kb
Host smart-7e9ee25d-6fdc-4a72-8831-6465da01c364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931266293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.931266293
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3592599951
Short name T70
Test name
Test status
Simulation time 22291847 ps
CPU time 0.63 seconds
Started May 26 01:01:16 PM PDT 24
Finished May 26 01:01:18 PM PDT 24
Peak memory 195236 kb
Host smart-25116644-09bd-4f2e-9b0e-34ffd5b59e7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592599951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3592599951
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1555985391
Short name T96
Test name
Test status
Simulation time 163749626 ps
CPU time 1.3 seconds
Started May 26 01:01:13 PM PDT 24
Finished May 26 01:01:16 PM PDT 24
Peak memory 199044 kb
Host smart-19d080b1-187a-4a60-b1a0-3bb2d0f0a701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555985391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1555985391
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.98546367
Short name T113
Test name
Test status
Simulation time 151316194526 ps
CPU time 643.66 seconds
Started May 26 02:14:20 PM PDT 24
Finished May 26 02:25:04 PM PDT 24
Peak memory 226940 kb
Host smart-de58da2e-f48e-4fd2-80a5-4b7686a796a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98546367 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.98546367
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1801711654
Short name T59
Test name
Test status
Simulation time 102593274779 ps
CPU time 50.95 seconds
Started May 26 02:17:01 PM PDT 24
Finished May 26 02:17:52 PM PDT 24
Peak memory 200536 kb
Host smart-a65833ee-2406-4302-bea1-39bbe648dde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801711654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1801711654
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2205429439
Short name T132
Test name
Test status
Simulation time 90565198372 ps
CPU time 34.7 seconds
Started May 26 02:15:13 PM PDT 24
Finished May 26 02:15:49 PM PDT 24
Peak memory 200560 kb
Host smart-32b82b18-0665-4d1e-b3dd-32cc5789082c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205429439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2205429439
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.711463481
Short name T174
Test name
Test status
Simulation time 221295716078 ps
CPU time 83.46 seconds
Started May 26 02:17:37 PM PDT 24
Finished May 26 02:19:01 PM PDT 24
Peak memory 200488 kb
Host smart-caf8aba5-3acd-4435-b918-338dc3031b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711463481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.711463481
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2485047970
Short name T147
Test name
Test status
Simulation time 170991380291 ps
CPU time 143.61 seconds
Started May 26 02:13:53 PM PDT 24
Finished May 26 02:16:19 PM PDT 24
Peak memory 200580 kb
Host smart-eec13a4a-c8cc-42e9-8b29-8ea08bb48993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485047970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2485047970
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.522252000
Short name T170
Test name
Test status
Simulation time 211402692435 ps
CPU time 1000.01 seconds
Started May 26 02:14:29 PM PDT 24
Finished May 26 02:31:10 PM PDT 24
Peak memory 233556 kb
Host smart-ca24db33-2035-40b8-9e52-85c72996ddae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522252000 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.522252000
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1614235500
Short name T190
Test name
Test status
Simulation time 248476513821 ps
CPU time 64.71 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:13:59 PM PDT 24
Peak memory 200364 kb
Host smart-67dc5615-db99-41c5-bdff-d0b78d6fcfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614235500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1614235500
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2444088152
Short name T166
Test name
Test status
Simulation time 34821755521 ps
CPU time 17.04 seconds
Started May 26 02:17:25 PM PDT 24
Finished May 26 02:17:43 PM PDT 24
Peak memory 200628 kb
Host smart-f75f1e05-4089-4b4d-8f52-24cdd9189ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444088152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2444088152
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.677059508
Short name T457
Test name
Test status
Simulation time 61772476335 ps
CPU time 59.6 seconds
Started May 26 02:12:45 PM PDT 24
Finished May 26 02:13:45 PM PDT 24
Peak memory 200544 kb
Host smart-e1a49b6d-9f68-46ca-a5d0-a96c89843a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677059508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.677059508
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3887627307
Short name T123
Test name
Test status
Simulation time 52260488260 ps
CPU time 93.35 seconds
Started May 26 02:14:44 PM PDT 24
Finished May 26 02:16:18 PM PDT 24
Peak memory 200580 kb
Host smart-9b0da621-4dd6-4ee3-8535-b93fe3ec11a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887627307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3887627307
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2393094652
Short name T101
Test name
Test status
Simulation time 308887561 ps
CPU time 1.32 seconds
Started May 26 01:01:13 PM PDT 24
Finished May 26 01:01:14 PM PDT 24
Peak memory 199100 kb
Host smart-24084a6d-1463-40fd-aeee-1d0ae783dd28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393094652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2393094652
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2030433182
Short name T162
Test name
Test status
Simulation time 83702757807 ps
CPU time 17.97 seconds
Started May 26 02:16:38 PM PDT 24
Finished May 26 02:16:56 PM PDT 24
Peak memory 200564 kb
Host smart-924576e2-14d2-4fda-9143-819f8674a7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030433182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2030433182
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3763745589
Short name T13
Test name
Test status
Simulation time 255316172217 ps
CPU time 112.49 seconds
Started May 26 02:17:18 PM PDT 24
Finished May 26 02:19:11 PM PDT 24
Peak memory 200660 kb
Host smart-63d973e5-4b61-4609-82fc-89022356e0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763745589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3763745589
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all.750638840
Short name T168
Test name
Test status
Simulation time 147038991548 ps
CPU time 70.33 seconds
Started May 26 02:15:37 PM PDT 24
Finished May 26 02:16:48 PM PDT 24
Peak memory 200544 kb
Host smart-cfd194b4-2a7e-447e-b8b9-60d1e0fb6603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750638840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.750638840
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3101841077
Short name T163
Test name
Test status
Simulation time 248374161438 ps
CPU time 76.73 seconds
Started May 26 02:12:58 PM PDT 24
Finished May 26 02:14:16 PM PDT 24
Peak memory 200476 kb
Host smart-678829b4-3a08-474e-8e62-7f4090225d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101841077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3101841077
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2570750692
Short name T357
Test name
Test status
Simulation time 70125175342 ps
CPU time 245.59 seconds
Started May 26 02:17:09 PM PDT 24
Finished May 26 02:21:15 PM PDT 24
Peak memory 200488 kb
Host smart-23b84ab9-2dfe-492a-b791-b16524e4b6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570750692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2570750692
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2085007764
Short name T232
Test name
Test status
Simulation time 35356677390 ps
CPU time 36 seconds
Started May 26 02:15:57 PM PDT 24
Finished May 26 02:16:34 PM PDT 24
Peak memory 200504 kb
Host smart-8b899da2-8e1c-4bca-919f-575ba5dd696a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085007764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2085007764
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3296073206
Short name T192
Test name
Test status
Simulation time 204353355886 ps
CPU time 23.65 seconds
Started May 26 02:16:29 PM PDT 24
Finished May 26 02:16:54 PM PDT 24
Peak memory 200464 kb
Host smart-74f4847d-2862-4abf-9e11-3bd75fa20d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296073206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3296073206
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all.2247824651
Short name T14
Test name
Test status
Simulation time 151455983725 ps
CPU time 732.95 seconds
Started May 26 02:13:10 PM PDT 24
Finished May 26 02:25:24 PM PDT 24
Peak memory 200352 kb
Host smart-39920dca-52a2-4e85-b0c7-957dd0e48e03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247824651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2247824651
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1735190337
Short name T228
Test name
Test status
Simulation time 31551612745 ps
CPU time 36.59 seconds
Started May 26 02:16:34 PM PDT 24
Finished May 26 02:17:11 PM PDT 24
Peak memory 200596 kb
Host smart-31b6ab04-6127-4519-9547-ef2785a0bdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735190337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1735190337
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3254263181
Short name T127
Test name
Test status
Simulation time 88310004325 ps
CPU time 17.3 seconds
Started May 26 02:16:37 PM PDT 24
Finished May 26 02:16:55 PM PDT 24
Peak memory 200472 kb
Host smart-21094380-d96b-4305-87df-ebf434ff7534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254263181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3254263181
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2836698
Short name T156
Test name
Test status
Simulation time 126197321545 ps
CPU time 58.96 seconds
Started May 26 02:14:54 PM PDT 24
Finished May 26 02:15:54 PM PDT 24
Peak memory 200272 kb
Host smart-a347e62c-2409-4ade-9368-e3a744db8ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2836698
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3465790219
Short name T317
Test name
Test status
Simulation time 138151084216 ps
CPU time 118.49 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:14:53 PM PDT 24
Peak memory 200512 kb
Host smart-3df49a5d-18f3-4102-b1a9-9418c0630b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465790219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3465790219
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3928814933
Short name T152
Test name
Test status
Simulation time 48327039178 ps
CPU time 21.93 seconds
Started May 26 02:12:54 PM PDT 24
Finished May 26 02:13:18 PM PDT 24
Peak memory 200448 kb
Host smart-4f234071-40b9-4cbf-bf4d-9c0130cd4b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928814933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3928814933
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2705672154
Short name T737
Test name
Test status
Simulation time 20918445907 ps
CPU time 142.87 seconds
Started May 26 02:13:07 PM PDT 24
Finished May 26 02:15:31 PM PDT 24
Peak memory 208744 kb
Host smart-85331cb0-a309-428a-9bed-ba71c8a00663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705672154 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2705672154
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1800566466
Short name T230
Test name
Test status
Simulation time 79567588039 ps
CPU time 22.77 seconds
Started May 26 02:16:36 PM PDT 24
Finished May 26 02:17:00 PM PDT 24
Peak memory 200272 kb
Host smart-405824d6-d0e8-49f8-a73f-d22d5d4bd409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800566466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1800566466
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1947573170
Short name T249
Test name
Test status
Simulation time 36622688547 ps
CPU time 13.25 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:13:30 PM PDT 24
Peak memory 200496 kb
Host smart-c2da3d12-4c7f-48c0-ad37-3db1ae116589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947573170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1947573170
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1664341478
Short name T165
Test name
Test status
Simulation time 20543818814 ps
CPU time 30.73 seconds
Started May 26 02:14:00 PM PDT 24
Finished May 26 02:14:31 PM PDT 24
Peak memory 200532 kb
Host smart-0780261c-d1ca-4ab9-ad34-6ef243d5421a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664341478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1664341478
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2117903304
Short name T151
Test name
Test status
Simulation time 47072492789 ps
CPU time 42.78 seconds
Started May 26 02:16:13 PM PDT 24
Finished May 26 02:16:56 PM PDT 24
Peak memory 200536 kb
Host smart-0c57636a-3264-4fc3-bfd3-5207f26b625b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117903304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2117903304
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2994315804
Short name T310
Test name
Test status
Simulation time 71576311066 ps
CPU time 418.88 seconds
Started May 26 02:16:19 PM PDT 24
Finished May 26 02:23:18 PM PDT 24
Peak memory 215944 kb
Host smart-7af2ca0b-9f32-4456-ac41-0bbf280d4804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994315804 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2994315804
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3224530567
Short name T140
Test name
Test status
Simulation time 438055518 ps
CPU time 0.97 seconds
Started May 26 01:01:11 PM PDT 24
Finished May 26 01:01:13 PM PDT 24
Peak memory 199064 kb
Host smart-9f69d747-5764-4c1e-a39a-66e4997f2ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224530567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3224530567
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_intr.1572014452
Short name T1031
Test name
Test status
Simulation time 53056425990 ps
CPU time 88.51 seconds
Started May 26 02:12:41 PM PDT 24
Finished May 26 02:14:10 PM PDT 24
Peak memory 198344 kb
Host smart-e9ac812d-e21a-421f-a6fd-a7b5356cbd53
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572014452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1572014452
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1067711783
Short name T186
Test name
Test status
Simulation time 76427882731 ps
CPU time 38.12 seconds
Started May 26 02:16:27 PM PDT 24
Finished May 26 02:17:06 PM PDT 24
Peak memory 200476 kb
Host smart-53962f9f-6089-4132-8a93-8de4842564a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067711783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1067711783
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1642358428
Short name T233
Test name
Test status
Simulation time 99490839099 ps
CPU time 40.33 seconds
Started May 26 02:17:05 PM PDT 24
Finished May 26 02:17:46 PM PDT 24
Peak memory 200548 kb
Host smart-202b800a-9951-48ba-9467-4942e3f4afa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642358428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1642358428
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.4211226163
Short name T1179
Test name
Test status
Simulation time 19650005547 ps
CPU time 28.87 seconds
Started May 26 02:16:35 PM PDT 24
Finished May 26 02:17:04 PM PDT 24
Peak memory 200540 kb
Host smart-12173b78-200f-4492-817f-90a20378444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211226163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.4211226163
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.430947441
Short name T1139
Test name
Test status
Simulation time 82630848282 ps
CPU time 26.74 seconds
Started May 26 02:16:34 PM PDT 24
Finished May 26 02:17:02 PM PDT 24
Peak memory 200472 kb
Host smart-783bdd88-6532-4dcf-8c4f-fe4bfa961a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430947441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.430947441
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.818347554
Short name T248
Test name
Test status
Simulation time 107041811348 ps
CPU time 177.54 seconds
Started May 26 02:16:34 PM PDT 24
Finished May 26 02:19:32 PM PDT 24
Peak memory 200516 kb
Host smart-9b8621a2-aa89-4190-88d7-75c899f337e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818347554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.818347554
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2918005460
Short name T207
Test name
Test status
Simulation time 17087259709 ps
CPU time 30.94 seconds
Started May 26 02:16:44 PM PDT 24
Finished May 26 02:17:15 PM PDT 24
Peak memory 200508 kb
Host smart-85e9b521-66d9-4d9b-91ee-bab746fe1ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918005460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2918005460
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3393449406
Short name T533
Test name
Test status
Simulation time 35839247651 ps
CPU time 52.36 seconds
Started May 26 02:13:23 PM PDT 24
Finished May 26 02:14:16 PM PDT 24
Peak memory 200432 kb
Host smart-87b47425-0cf2-4180-a72d-368c486c3999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393449406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3393449406
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2415540003
Short name T179
Test name
Test status
Simulation time 43078280321 ps
CPU time 47.95 seconds
Started May 26 02:16:53 PM PDT 24
Finished May 26 02:17:41 PM PDT 24
Peak memory 200452 kb
Host smart-681950fb-85df-4d0c-85a6-12b427bb6947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415540003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2415540003
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2871290785
Short name T39
Test name
Test status
Simulation time 36994544466 ps
CPU time 184.6 seconds
Started May 26 02:13:35 PM PDT 24
Finished May 26 02:16:41 PM PDT 24
Peak memory 217260 kb
Host smart-35a9c682-b439-4963-84d9-4741555ff5bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871290785 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2871290785
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3600988674
Short name T155
Test name
Test status
Simulation time 59514313745 ps
CPU time 15.57 seconds
Started May 26 02:16:59 PM PDT 24
Finished May 26 02:17:16 PM PDT 24
Peak memory 200464 kb
Host smart-6fe40f34-5158-4776-93fe-b530185b9757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600988674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3600988674
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3251649014
Short name T110
Test name
Test status
Simulation time 121484310504 ps
CPU time 38.62 seconds
Started May 26 02:16:58 PM PDT 24
Finished May 26 02:17:38 PM PDT 24
Peak memory 200564 kb
Host smart-ad6fe697-fc72-4973-a734-c28184c0ac60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251649014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3251649014
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.835343223
Short name T231
Test name
Test status
Simulation time 117722725653 ps
CPU time 45.1 seconds
Started May 26 02:16:59 PM PDT 24
Finished May 26 02:17:45 PM PDT 24
Peak memory 200484 kb
Host smart-63cc322e-9123-4ecd-a8d5-c6aecf5b1d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835343223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.835343223
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3238802944
Short name T241
Test name
Test status
Simulation time 69140196770 ps
CPU time 27.91 seconds
Started May 26 02:17:08 PM PDT 24
Finished May 26 02:17:36 PM PDT 24
Peak memory 200540 kb
Host smart-8e24d515-83be-42da-a831-0ca44ee1cf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238802944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3238802944
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2005059394
Short name T250
Test name
Test status
Simulation time 75639919882 ps
CPU time 292.67 seconds
Started May 26 02:17:18 PM PDT 24
Finished May 26 02:22:12 PM PDT 24
Peak memory 200496 kb
Host smart-93ace961-f7e0-4dd6-8321-332f9b6bfeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005059394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2005059394
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3223704632
Short name T243
Test name
Test status
Simulation time 14407725679 ps
CPU time 26.25 seconds
Started May 26 02:17:25 PM PDT 24
Finished May 26 02:17:52 PM PDT 24
Peak memory 200600 kb
Host smart-eacd8c66-ee0d-4196-8b4f-9872e63d0b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223704632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3223704632
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3748261651
Short name T167
Test name
Test status
Simulation time 50170519066 ps
CPU time 19.9 seconds
Started May 26 02:17:25 PM PDT 24
Finished May 26 02:17:45 PM PDT 24
Peak memory 200500 kb
Host smart-db8bcb8e-7dd7-4927-a41c-84d183d527b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748261651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3748261651
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2256903732
Short name T229
Test name
Test status
Simulation time 109135103809 ps
CPU time 45.91 seconds
Started May 26 02:17:42 PM PDT 24
Finished May 26 02:18:29 PM PDT 24
Peak memory 200476 kb
Host smart-e87b7823-e56d-4bc5-b3c1-71fb8160d7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256903732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2256903732
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.78285673
Short name T184
Test name
Test status
Simulation time 227496517757 ps
CPU time 110.86 seconds
Started May 26 02:15:57 PM PDT 24
Finished May 26 02:17:49 PM PDT 24
Peak memory 200484 kb
Host smart-d38b7cbd-81f7-4821-bc05-b9a58293e34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78285673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.78285673
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1141575571
Short name T253
Test name
Test status
Simulation time 64516697817 ps
CPU time 112.22 seconds
Started May 26 02:16:12 PM PDT 24
Finished May 26 02:18:05 PM PDT 24
Peak memory 200500 kb
Host smart-4e996b7a-fd1a-4542-a082-f3324a429577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141575571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1141575571
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2797294818
Short name T242
Test name
Test status
Simulation time 21113776548 ps
CPU time 29.75 seconds
Started May 26 02:16:20 PM PDT 24
Finished May 26 02:16:51 PM PDT 24
Peak memory 200524 kb
Host smart-87888691-725e-43a3-8680-6f88a23c5fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797294818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2797294818
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3540547964
Short name T159
Test name
Test status
Simulation time 67648615671 ps
CPU time 1236.55 seconds
Started May 26 02:16:25 PM PDT 24
Finished May 26 02:37:02 PM PDT 24
Peak memory 216992 kb
Host smart-9e68909f-3621-4ef7-9629-661e830824b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540547964 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3540547964
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3386281269
Short name T1262
Test name
Test status
Simulation time 25146022 ps
CPU time 0.77 seconds
Started May 26 01:00:56 PM PDT 24
Finished May 26 01:00:58 PM PDT 24
Peak memory 196160 kb
Host smart-26e23790-e248-4333-828e-73bc8efadee6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386281269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3386281269
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2501258111
Short name T1303
Test name
Test status
Simulation time 674024159 ps
CPU time 2.44 seconds
Started May 26 01:00:56 PM PDT 24
Finished May 26 01:01:00 PM PDT 24
Peak memory 197316 kb
Host smart-a99b90fa-4627-4754-b123-7249e77fdbd2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501258111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2501258111
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.600991558
Short name T1235
Test name
Test status
Simulation time 53831696 ps
CPU time 0.63 seconds
Started May 26 01:00:56 PM PDT 24
Finished May 26 01:00:59 PM PDT 24
Peak memory 195144 kb
Host smart-9931a7ce-5974-441a-a095-9a8b2240ba02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600991558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.600991558
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.679882630
Short name T1207
Test name
Test status
Simulation time 80483678 ps
CPU time 1 seconds
Started May 26 01:00:54 PM PDT 24
Finished May 26 01:00:56 PM PDT 24
Peak memory 199688 kb
Host smart-b52767d8-2130-4436-9edd-3122ec5a962d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679882630 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.679882630
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3244578138
Short name T1290
Test name
Test status
Simulation time 19384453 ps
CPU time 0.68 seconds
Started May 26 01:01:01 PM PDT 24
Finished May 26 01:01:02 PM PDT 24
Peak memory 195224 kb
Host smart-2b3dabab-b03c-49a1-90ec-bc587cef5458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244578138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3244578138
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.498816914
Short name T1249
Test name
Test status
Simulation time 18620634 ps
CPU time 0.56 seconds
Started May 26 01:00:54 PM PDT 24
Finished May 26 01:00:56 PM PDT 24
Peak memory 194188 kb
Host smart-873d9a10-366e-4f9c-9f5c-f481157668ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498816914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.498816914
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1515799724
Short name T91
Test name
Test status
Simulation time 43115389 ps
CPU time 0.73 seconds
Started May 26 01:00:56 PM PDT 24
Finished May 26 01:00:58 PM PDT 24
Peak memory 196768 kb
Host smart-6f55c293-6456-48b3-af97-fa1d067c9a6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515799724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1515799724
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2483280255
Short name T1284
Test name
Test status
Simulation time 63310641 ps
CPU time 1.04 seconds
Started May 26 01:00:56 PM PDT 24
Finished May 26 01:00:59 PM PDT 24
Peak memory 199584 kb
Host smart-fe80cf38-2fc5-4725-9a33-090d98e64d1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483280255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2483280255
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2542344343
Short name T1280
Test name
Test status
Simulation time 181321813 ps
CPU time 0.97 seconds
Started May 26 01:00:56 PM PDT 24
Finished May 26 01:00:59 PM PDT 24
Peak memory 198808 kb
Host smart-ee47d4ee-888c-4953-aef1-f4cc3eb2e57f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542344343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2542344343
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.11294258
Short name T1288
Test name
Test status
Simulation time 14775399 ps
CPU time 0.66 seconds
Started May 26 01:00:57 PM PDT 24
Finished May 26 01:00:59 PM PDT 24
Peak memory 194788 kb
Host smart-2843c47b-0bb5-4189-8894-8548cdd9081f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11294258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.11294258
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2283900523
Short name T1291
Test name
Test status
Simulation time 91060216 ps
CPU time 1.49 seconds
Started May 26 01:00:56 PM PDT 24
Finished May 26 01:00:59 PM PDT 24
Peak memory 197652 kb
Host smart-1771d42e-464c-4b6b-b991-4a8dba9bd12b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283900523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2283900523
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1663028780
Short name T1258
Test name
Test status
Simulation time 107967117 ps
CPU time 0.56 seconds
Started May 26 01:00:56 PM PDT 24
Finished May 26 01:00:58 PM PDT 24
Peak memory 195164 kb
Host smart-14e06224-f61f-4024-8ede-d6569ad6cbc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663028780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1663028780
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2850637636
Short name T1195
Test name
Test status
Simulation time 23206259 ps
CPU time 0.91 seconds
Started May 26 01:00:57 PM PDT 24
Finished May 26 01:01:00 PM PDT 24
Peak memory 199688 kb
Host smart-deabb65c-7e74-401c-9ea8-b86e4491081e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850637636 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2850637636
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.579830069
Short name T1193
Test name
Test status
Simulation time 108531205 ps
CPU time 0.61 seconds
Started May 26 01:00:59 PM PDT 24
Finished May 26 01:01:01 PM PDT 24
Peak memory 195324 kb
Host smart-6fd8df4c-5d81-496a-a0d8-28c1d1c0a695
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579830069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.579830069
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2580749357
Short name T1186
Test name
Test status
Simulation time 30145273 ps
CPU time 0.57 seconds
Started May 26 01:00:57 PM PDT 24
Finished May 26 01:00:59 PM PDT 24
Peak memory 194184 kb
Host smart-5bdf46cb-7353-468e-9305-8aca33433309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580749357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2580749357
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.878944569
Short name T1276
Test name
Test status
Simulation time 41097182 ps
CPU time 0.72 seconds
Started May 26 01:00:57 PM PDT 24
Finished May 26 01:00:59 PM PDT 24
Peak memory 196752 kb
Host smart-ea388386-3f10-4705-82d4-fade26df57d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878944569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.878944569
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.198716416
Short name T1310
Test name
Test status
Simulation time 156293491 ps
CPU time 2.2 seconds
Started May 26 01:00:55 PM PDT 24
Finished May 26 01:00:59 PM PDT 24
Peak memory 199796 kb
Host smart-5d1bdbf8-821c-4570-b0e0-d7f6f22d88ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198716416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.198716416
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3964039696
Short name T1259
Test name
Test status
Simulation time 103644588 ps
CPU time 1.25 seconds
Started May 26 01:00:54 PM PDT 24
Finished May 26 01:00:56 PM PDT 24
Peak memory 198848 kb
Host smart-9f7fdcec-af26-4eb8-9f3e-2369784f829f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964039696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3964039696
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3547678714
Short name T1198
Test name
Test status
Simulation time 37748984 ps
CPU time 0.72 seconds
Started May 26 01:01:13 PM PDT 24
Finished May 26 01:01:15 PM PDT 24
Peak memory 198524 kb
Host smart-d0a77adc-d4a3-4875-a7b9-83364c590805
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547678714 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3547678714
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.340747884
Short name T76
Test name
Test status
Simulation time 20035193 ps
CPU time 0.61 seconds
Started May 26 01:01:13 PM PDT 24
Finished May 26 01:01:15 PM PDT 24
Peak memory 195444 kb
Host smart-9d5241b1-066c-4f01-9c9f-0c309e42696d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340747884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.340747884
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2513418165
Short name T1209
Test name
Test status
Simulation time 17181670 ps
CPU time 0.59 seconds
Started May 26 01:01:17 PM PDT 24
Finished May 26 01:01:19 PM PDT 24
Peak memory 194260 kb
Host smart-f471566b-9464-45e5-aa9f-4b78ab4631d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513418165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2513418165
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2553351529
Short name T87
Test name
Test status
Simulation time 22200734 ps
CPU time 0.63 seconds
Started May 26 01:01:17 PM PDT 24
Finished May 26 01:01:19 PM PDT 24
Peak memory 195308 kb
Host smart-2943ac64-8502-48a1-822b-b56a5edbf43b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553351529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2553351529
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.530806762
Short name T1182
Test name
Test status
Simulation time 82320291 ps
CPU time 1.56 seconds
Started May 26 01:01:13 PM PDT 24
Finished May 26 01:01:16 PM PDT 24
Peak memory 199784 kb
Host smart-62849fcb-4ddf-4362-99a4-b62a4b2ec9bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530806762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.530806762
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1511251378
Short name T98
Test name
Test status
Simulation time 73160229 ps
CPU time 0.89 seconds
Started May 26 01:01:15 PM PDT 24
Finished May 26 01:01:17 PM PDT 24
Peak memory 198708 kb
Host smart-d5538581-f9b4-4db6-bd9c-ef21dca76280
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511251378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1511251378
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4201661296
Short name T1225
Test name
Test status
Simulation time 131807502 ps
CPU time 0.77 seconds
Started May 26 01:01:18 PM PDT 24
Finished May 26 01:01:20 PM PDT 24
Peak memory 199644 kb
Host smart-7a1bc047-3e0d-4076-b3e5-55b8ee07ded0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201661296 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.4201661296
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2133438899
Short name T1314
Test name
Test status
Simulation time 20200329 ps
CPU time 0.53 seconds
Started May 26 01:01:17 PM PDT 24
Finished May 26 01:01:18 PM PDT 24
Peak memory 194112 kb
Host smart-7778467a-36d2-4f5c-9a92-b499947238a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133438899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2133438899
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3185170812
Short name T85
Test name
Test status
Simulation time 77178080 ps
CPU time 0.68 seconds
Started May 26 01:01:13 PM PDT 24
Finished May 26 01:01:15 PM PDT 24
Peak memory 196476 kb
Host smart-886d8e85-6bc4-4425-9ac4-77d58d6548e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185170812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3185170812
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.70986254
Short name T1192
Test name
Test status
Simulation time 58674211 ps
CPU time 1.22 seconds
Started May 26 01:01:15 PM PDT 24
Finished May 26 01:01:17 PM PDT 24
Peak memory 199792 kb
Host smart-ad536ac2-b82e-407c-8d87-7cdebe25260a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70986254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.70986254
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.853170059
Short name T1265
Test name
Test status
Simulation time 283660909 ps
CPU time 1.43 seconds
Started May 26 01:01:15 PM PDT 24
Finished May 26 01:01:18 PM PDT 24
Peak memory 199036 kb
Host smart-0432cd98-457e-47f6-9064-5301ab820876
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853170059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.853170059
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2839187887
Short name T1242
Test name
Test status
Simulation time 28210910 ps
CPU time 0.77 seconds
Started May 26 01:01:16 PM PDT 24
Finished May 26 01:01:18 PM PDT 24
Peak memory 197924 kb
Host smart-5c96c602-b2c8-4421-bf4d-9d382dad9b5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839187887 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2839187887
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3782454248
Short name T1244
Test name
Test status
Simulation time 55200536 ps
CPU time 0.62 seconds
Started May 26 01:01:14 PM PDT 24
Finished May 26 01:01:16 PM PDT 24
Peak memory 195568 kb
Host smart-2570c836-48b9-42be-9b83-f9358de10139
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782454248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3782454248
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3583025201
Short name T1277
Test name
Test status
Simulation time 18110822 ps
CPU time 0.58 seconds
Started May 26 01:01:16 PM PDT 24
Finished May 26 01:01:17 PM PDT 24
Peak memory 194248 kb
Host smart-be0c4e1c-1eff-4587-bac5-645d9ec4cd32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583025201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3583025201
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1001556745
Short name T1214
Test name
Test status
Simulation time 125123405 ps
CPU time 0.77 seconds
Started May 26 01:01:17 PM PDT 24
Finished May 26 01:01:19 PM PDT 24
Peak memory 197028 kb
Host smart-6c3e351b-c9d3-4d0f-bdd4-3d56df207148
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001556745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1001556745
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1779941266
Short name T1250
Test name
Test status
Simulation time 112625903 ps
CPU time 2.17 seconds
Started May 26 01:01:15 PM PDT 24
Finished May 26 01:01:18 PM PDT 24
Peak memory 199820 kb
Host smart-6e104f46-c6e4-4ff9-8935-658fa96d7944
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779941266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1779941266
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3576956196
Short name T1202
Test name
Test status
Simulation time 646695657 ps
CPU time 1.37 seconds
Started May 26 01:01:14 PM PDT 24
Finished May 26 01:01:16 PM PDT 24
Peak memory 199136 kb
Host smart-fc4727a4-a63f-4ab6-95ec-0cb5778b44e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576956196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3576956196
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.540965388
Short name T1231
Test name
Test status
Simulation time 94951409 ps
CPU time 0.83 seconds
Started May 26 01:01:15 PM PDT 24
Finished May 26 01:01:17 PM PDT 24
Peak memory 199604 kb
Host smart-249873dc-4f68-4658-8953-08cbe0438fc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540965388 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.540965388
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.157307122
Short name T1269
Test name
Test status
Simulation time 29003473 ps
CPU time 0.55 seconds
Started May 26 01:01:13 PM PDT 24
Finished May 26 01:01:15 PM PDT 24
Peak memory 195116 kb
Host smart-c057d65b-bfee-4577-8271-9e429e92304e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157307122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.157307122
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2481464561
Short name T1197
Test name
Test status
Simulation time 12073874 ps
CPU time 0.61 seconds
Started May 26 01:01:13 PM PDT 24
Finished May 26 01:01:15 PM PDT 24
Peak memory 194268 kb
Host smart-07fb7180-e116-4de4-a888-0f6a18c6674d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481464561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2481464561
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4135405823
Short name T1292
Test name
Test status
Simulation time 101690018 ps
CPU time 0.75 seconds
Started May 26 01:01:13 PM PDT 24
Finished May 26 01:01:15 PM PDT 24
Peak memory 196768 kb
Host smart-f7303e82-1127-496e-820e-1b8acee3e731
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135405823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.4135405823
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.879288901
Short name T1287
Test name
Test status
Simulation time 78959667 ps
CPU time 1.58 seconds
Started May 26 01:01:17 PM PDT 24
Finished May 26 01:01:20 PM PDT 24
Peak memory 199884 kb
Host smart-6b0992f4-c1ed-4503-b5b0-4d505c6acae8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879288901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.879288901
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1025581363
Short name T1212
Test name
Test status
Simulation time 197967663 ps
CPU time 0.96 seconds
Started May 26 01:01:15 PM PDT 24
Finished May 26 01:01:17 PM PDT 24
Peak memory 198464 kb
Host smart-af919e7c-47d3-4a11-adce-479a7ecdaf39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025581363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1025581363
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4050619119
Short name T1222
Test name
Test status
Simulation time 27748963 ps
CPU time 0.88 seconds
Started May 26 01:01:15 PM PDT 24
Finished May 26 01:01:17 PM PDT 24
Peak memory 199580 kb
Host smart-543f81c6-283b-4517-be0e-f2ac0f5de9f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050619119 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.4050619119
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1584394545
Short name T1233
Test name
Test status
Simulation time 14395022 ps
CPU time 0.58 seconds
Started May 26 01:01:12 PM PDT 24
Finished May 26 01:01:13 PM PDT 24
Peak memory 195168 kb
Host smart-1e8ad536-2460-4d9e-84ea-e04f19ccf853
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584394545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1584394545
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.158296327
Short name T1205
Test name
Test status
Simulation time 34951715 ps
CPU time 0.62 seconds
Started May 26 01:01:15 PM PDT 24
Finished May 26 01:01:17 PM PDT 24
Peak memory 194128 kb
Host smart-e686e00e-e0a8-4136-84ab-64b866508403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158296327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.158296327
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1625546230
Short name T1306
Test name
Test status
Simulation time 113661930 ps
CPU time 0.77 seconds
Started May 26 01:01:16 PM PDT 24
Finished May 26 01:01:18 PM PDT 24
Peak memory 196768 kb
Host smart-6a7d39a6-429c-405a-9905-3218758ea3cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625546230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1625546230
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.336675495
Short name T1247
Test name
Test status
Simulation time 87091723 ps
CPU time 1.88 seconds
Started May 26 01:01:13 PM PDT 24
Finished May 26 01:01:15 PM PDT 24
Peak memory 199884 kb
Host smart-dca4c8b0-9b6a-40fe-b32d-6f8b7a324516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336675495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.336675495
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3444525218
Short name T1302
Test name
Test status
Simulation time 123800012 ps
CPU time 0.77 seconds
Started May 26 01:01:15 PM PDT 24
Finished May 26 01:01:17 PM PDT 24
Peak memory 198844 kb
Host smart-cb3090a3-59f4-4d55-8128-4ef8293f8537
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444525218 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3444525218
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.185867490
Short name T86
Test name
Test status
Simulation time 96940304 ps
CPU time 0.59 seconds
Started May 26 01:01:13 PM PDT 24
Finished May 26 01:01:14 PM PDT 24
Peak memory 195152 kb
Host smart-02d5e31f-11f6-45d7-82b2-f208c224cd66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185867490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.185867490
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.182739975
Short name T1251
Test name
Test status
Simulation time 10635155 ps
CPU time 0.57 seconds
Started May 26 01:01:17 PM PDT 24
Finished May 26 01:01:18 PM PDT 24
Peak memory 194168 kb
Host smart-0a28a7d3-4473-4bf7-94d6-5d90b839a443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182739975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.182739975
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.4084110218
Short name T1228
Test name
Test status
Simulation time 146351654 ps
CPU time 0.71 seconds
Started May 26 01:01:17 PM PDT 24
Finished May 26 01:01:19 PM PDT 24
Peak memory 196628 kb
Host smart-479039f0-c857-4dd6-9323-12e9bd3ac430
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084110218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.4084110218
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3154123220
Short name T1218
Test name
Test status
Simulation time 143237670 ps
CPU time 1.91 seconds
Started May 26 01:01:18 PM PDT 24
Finished May 26 01:01:21 PM PDT 24
Peak memory 199900 kb
Host smart-d7f00606-41ac-4b85-8a9e-946ec56761f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154123220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3154123220
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3814299376
Short name T1274
Test name
Test status
Simulation time 50258993 ps
CPU time 0.85 seconds
Started May 26 01:01:15 PM PDT 24
Finished May 26 01:01:17 PM PDT 24
Peak memory 199708 kb
Host smart-81bf639e-5b4b-4923-a0dc-99205a5cd882
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814299376 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3814299376
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.920679395
Short name T1261
Test name
Test status
Simulation time 35191366 ps
CPU time 0.57 seconds
Started May 26 01:01:16 PM PDT 24
Finished May 26 01:01:18 PM PDT 24
Peak memory 195152 kb
Host smart-06a665b7-4cdf-4aed-954a-2a2ba581d776
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920679395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.920679395
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2151671834
Short name T1241
Test name
Test status
Simulation time 37076426 ps
CPU time 0.57 seconds
Started May 26 01:01:14 PM PDT 24
Finished May 26 01:01:16 PM PDT 24
Peak memory 194428 kb
Host smart-a1f5a5fe-83ad-49de-92fe-e1c93a5e92b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151671834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2151671834
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1761642663
Short name T88
Test name
Test status
Simulation time 19819154 ps
CPU time 0.62 seconds
Started May 26 01:01:13 PM PDT 24
Finished May 26 01:01:15 PM PDT 24
Peak memory 195536 kb
Host smart-8fa09ad1-803e-4003-a10a-be280a3869e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761642663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1761642663
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2515577340
Short name T1267
Test name
Test status
Simulation time 52163989 ps
CPU time 1.3 seconds
Started May 26 01:01:17 PM PDT 24
Finished May 26 01:01:20 PM PDT 24
Peak memory 199828 kb
Host smart-b6491460-0e1e-440c-bab8-08c8c61d143c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515577340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2515577340
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2828119101
Short name T93
Test name
Test status
Simulation time 152398181 ps
CPU time 0.94 seconds
Started May 26 01:01:15 PM PDT 24
Finished May 26 01:01:17 PM PDT 24
Peak memory 199600 kb
Host smart-2ef4184d-06b1-492d-974c-696809d7f663
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828119101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2828119101
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4233635724
Short name T1297
Test name
Test status
Simulation time 29261421 ps
CPU time 0.87 seconds
Started May 26 01:01:24 PM PDT 24
Finished May 26 01:01:26 PM PDT 24
Peak memory 199612 kb
Host smart-ec7946fc-1fff-47ab-9836-7e05bfd38eaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233635724 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.4233635724
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.606054273
Short name T83
Test name
Test status
Simulation time 30392946 ps
CPU time 0.6 seconds
Started May 26 01:01:25 PM PDT 24
Finished May 26 01:01:26 PM PDT 24
Peak memory 195228 kb
Host smart-bc4d997b-9ac0-460b-a82f-9622b9fb7310
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606054273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.606054273
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3762965188
Short name T1219
Test name
Test status
Simulation time 41375899 ps
CPU time 0.64 seconds
Started May 26 01:01:15 PM PDT 24
Finished May 26 01:01:17 PM PDT 24
Peak memory 194200 kb
Host smart-0f8283a7-1068-4ec4-a38e-d080cff89b18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762965188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3762965188
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2379331384
Short name T1307
Test name
Test status
Simulation time 21843146 ps
CPU time 0.68 seconds
Started May 26 01:01:24 PM PDT 24
Finished May 26 01:01:26 PM PDT 24
Peak memory 195308 kb
Host smart-3e1b2847-18b9-4be9-934e-931b01b072fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379331384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2379331384
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2940456253
Short name T1239
Test name
Test status
Simulation time 29596985 ps
CPU time 1.52 seconds
Started May 26 01:01:15 PM PDT 24
Finished May 26 01:01:18 PM PDT 24
Peak memory 199820 kb
Host smart-f0d91645-5f47-41cd-a0ef-f606a1443d39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940456253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2940456253
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.110094278
Short name T1240
Test name
Test status
Simulation time 127588667 ps
CPU time 0.92 seconds
Started May 26 01:01:17 PM PDT 24
Finished May 26 01:01:19 PM PDT 24
Peak memory 198620 kb
Host smart-454c3964-a067-4ef8-8c66-0aac2614262f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110094278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.110094278
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.101462905
Short name T1243
Test name
Test status
Simulation time 147341299 ps
CPU time 1 seconds
Started May 26 01:01:25 PM PDT 24
Finished May 26 01:01:27 PM PDT 24
Peak memory 199532 kb
Host smart-6f207c0f-9a8a-4be6-9e6c-83ab5888f07b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101462905 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.101462905
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.359026177
Short name T74
Test name
Test status
Simulation time 64512717 ps
CPU time 0.66 seconds
Started May 26 01:01:30 PM PDT 24
Finished May 26 01:01:32 PM PDT 24
Peak memory 195192 kb
Host smart-a58f41d5-82ce-4788-8846-569117a718f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359026177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.359026177
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3474565414
Short name T1245
Test name
Test status
Simulation time 16982116 ps
CPU time 0.58 seconds
Started May 26 01:01:25 PM PDT 24
Finished May 26 01:01:27 PM PDT 24
Peak memory 194116 kb
Host smart-168e80bc-ac11-4287-8bac-3eeedd67375c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474565414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3474565414
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3171536302
Short name T1289
Test name
Test status
Simulation time 135120115 ps
CPU time 0.72 seconds
Started May 26 01:01:26 PM PDT 24
Finished May 26 01:01:28 PM PDT 24
Peak memory 197284 kb
Host smart-24055234-7e67-4d46-9692-d579c9e2ab99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171536302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3171536302
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2031991111
Short name T1216
Test name
Test status
Simulation time 483441062 ps
CPU time 2.09 seconds
Started May 26 01:01:30 PM PDT 24
Finished May 26 01:01:33 PM PDT 24
Peak memory 199736 kb
Host smart-c7b6b6f3-6c66-4b0c-a449-a1e56be523d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031991111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2031991111
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1506042361
Short name T1298
Test name
Test status
Simulation time 102909045 ps
CPU time 1.33 seconds
Started May 26 01:01:26 PM PDT 24
Finished May 26 01:01:29 PM PDT 24
Peak memory 198996 kb
Host smart-5b184c41-e1b7-4c5e-bdfe-44a7d690e04f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506042361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1506042361
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.111055345
Short name T1268
Test name
Test status
Simulation time 248810973 ps
CPU time 0.75 seconds
Started May 26 01:01:29 PM PDT 24
Finished May 26 01:01:31 PM PDT 24
Peak memory 198584 kb
Host smart-73dbcba8-16ce-49e4-be58-e3ca478134e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111055345 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.111055345
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.208149948
Short name T82
Test name
Test status
Simulation time 14261855 ps
CPU time 0.56 seconds
Started May 26 01:01:22 PM PDT 24
Finished May 26 01:01:23 PM PDT 24
Peak memory 195160 kb
Host smart-3a0a2e58-afa9-42ad-80ad-6c3c9f015946
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208149948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.208149948
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.178255017
Short name T1201
Test name
Test status
Simulation time 41590044 ps
CPU time 0.56 seconds
Started May 26 01:01:26 PM PDT 24
Finished May 26 01:01:28 PM PDT 24
Peak memory 194488 kb
Host smart-d1565ad6-a7a6-4676-90a8-be7151066fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178255017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.178255017
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1599461509
Short name T1238
Test name
Test status
Simulation time 19474664 ps
CPU time 0.64 seconds
Started May 26 01:01:24 PM PDT 24
Finished May 26 01:01:26 PM PDT 24
Peak memory 195436 kb
Host smart-6855409e-2ef3-4099-b08c-be92ae692f6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599461509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1599461509
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2885749669
Short name T1203
Test name
Test status
Simulation time 414377291 ps
CPU time 2.22 seconds
Started May 26 01:01:23 PM PDT 24
Finished May 26 01:01:26 PM PDT 24
Peak memory 199904 kb
Host smart-5533d821-e35b-4ed5-b518-ae0dc34ed10b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885749669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2885749669
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1642901477
Short name T1230
Test name
Test status
Simulation time 122059623 ps
CPU time 1.33 seconds
Started May 26 01:01:26 PM PDT 24
Finished May 26 01:01:29 PM PDT 24
Peak memory 198984 kb
Host smart-86d68eb2-5622-46cc-a2c1-50fcbb14b809
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642901477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1642901477
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2781210911
Short name T1294
Test name
Test status
Simulation time 13454782 ps
CPU time 0.71 seconds
Started May 26 01:01:00 PM PDT 24
Finished May 26 01:01:02 PM PDT 24
Peak memory 195040 kb
Host smart-9c9c687c-7333-48c8-b29c-9107c5ba5d5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781210911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2781210911
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1081371115
Short name T72
Test name
Test status
Simulation time 35475241 ps
CPU time 1.37 seconds
Started May 26 01:00:55 PM PDT 24
Finished May 26 01:00:57 PM PDT 24
Peak memory 197764 kb
Host smart-11d3810b-2f0f-4ac7-8d3d-1faf5e02146e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081371115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1081371115
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2170845729
Short name T1286
Test name
Test status
Simulation time 13925758 ps
CPU time 0.57 seconds
Started May 26 01:00:55 PM PDT 24
Finished May 26 01:00:57 PM PDT 24
Peak memory 195132 kb
Host smart-87b474bc-09e8-4189-9314-649a1be82d11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170845729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2170845729
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3553026159
Short name T1196
Test name
Test status
Simulation time 153971223 ps
CPU time 1.48 seconds
Started May 26 01:00:54 PM PDT 24
Finished May 26 01:00:56 PM PDT 24
Peak memory 199764 kb
Host smart-326a9544-417a-4af5-95e9-bed953d04522
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553026159 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3553026159
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3945362044
Short name T73
Test name
Test status
Simulation time 15868192 ps
CPU time 0.68 seconds
Started May 26 01:00:57 PM PDT 24
Finished May 26 01:00:59 PM PDT 24
Peak memory 195656 kb
Host smart-7b17a2f8-944b-40d2-a6d3-208151dd297a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945362044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3945362044
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3893653290
Short name T1295
Test name
Test status
Simulation time 28603933 ps
CPU time 0.56 seconds
Started May 26 01:00:56 PM PDT 24
Finished May 26 01:00:58 PM PDT 24
Peak memory 194188 kb
Host smart-47fd24b0-61d1-47c6-bf94-4e6e19c60bd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893653290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3893653290
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.694715361
Short name T1253
Test name
Test status
Simulation time 20559450 ps
CPU time 0.68 seconds
Started May 26 01:01:00 PM PDT 24
Finished May 26 01:01:02 PM PDT 24
Peak memory 194220 kb
Host smart-0b4a1df8-1559-40c5-9593-c3ebabf138ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694715361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.694715361
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.721480009
Short name T1185
Test name
Test status
Simulation time 187442647 ps
CPU time 2.11 seconds
Started May 26 01:00:55 PM PDT 24
Finished May 26 01:00:59 PM PDT 24
Peak memory 199848 kb
Host smart-cfbead5e-d69c-44db-a09b-422266c69133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721480009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.721480009
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3933924081
Short name T97
Test name
Test status
Simulation time 280974574 ps
CPU time 0.99 seconds
Started May 26 01:00:55 PM PDT 24
Finished May 26 01:00:56 PM PDT 24
Peak memory 198744 kb
Host smart-5932cbdc-c2a5-490c-8b28-fe5b37d55640
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933924081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3933924081
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2912077554
Short name T1237
Test name
Test status
Simulation time 44146349 ps
CPU time 0.6 seconds
Started May 26 01:01:25 PM PDT 24
Finished May 26 01:01:27 PM PDT 24
Peak memory 194244 kb
Host smart-f9ba27ae-c949-423e-a5ee-4f59ec8d269c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912077554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2912077554
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.769514133
Short name T1199
Test name
Test status
Simulation time 17023358 ps
CPU time 0.55 seconds
Started May 26 01:01:22 PM PDT 24
Finished May 26 01:01:24 PM PDT 24
Peak memory 194188 kb
Host smart-2b976fb5-5777-4542-b0c9-e923b66049b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769514133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.769514133
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1693805487
Short name T1301
Test name
Test status
Simulation time 14247442 ps
CPU time 0.55 seconds
Started May 26 01:01:22 PM PDT 24
Finished May 26 01:01:23 PM PDT 24
Peak memory 194132 kb
Host smart-dbfb8595-cb07-488d-96ef-1c649be739ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693805487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1693805487
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1002354002
Short name T1272
Test name
Test status
Simulation time 26422009 ps
CPU time 0.57 seconds
Started May 26 01:01:30 PM PDT 24
Finished May 26 01:01:31 PM PDT 24
Peak memory 194204 kb
Host smart-7d885585-4f3c-4b15-9d01-9292da69999b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002354002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1002354002
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1763490669
Short name T1184
Test name
Test status
Simulation time 24687416 ps
CPU time 0.56 seconds
Started May 26 01:01:26 PM PDT 24
Finished May 26 01:01:28 PM PDT 24
Peak memory 194264 kb
Host smart-ffd8d109-c4ed-49cd-9ff7-ca9a1106a086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763490669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1763490669
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1400207618
Short name T1215
Test name
Test status
Simulation time 16958460 ps
CPU time 0.61 seconds
Started May 26 01:01:24 PM PDT 24
Finished May 26 01:01:25 PM PDT 24
Peak memory 194212 kb
Host smart-7a256123-0c76-4500-9469-a67a1056b37a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400207618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1400207618
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1192427339
Short name T1255
Test name
Test status
Simulation time 143554708 ps
CPU time 0.56 seconds
Started May 26 01:01:25 PM PDT 24
Finished May 26 01:01:27 PM PDT 24
Peak memory 194140 kb
Host smart-3d7ab257-edd4-4a3e-9ce4-c5a1d48a0263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192427339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1192427339
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3790834046
Short name T1311
Test name
Test status
Simulation time 32639735 ps
CPU time 0.6 seconds
Started May 26 01:01:30 PM PDT 24
Finished May 26 01:01:31 PM PDT 24
Peak memory 194092 kb
Host smart-0d5ba121-eff0-4a2e-983d-a503e7a5cb7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790834046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3790834046
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2512955422
Short name T1232
Test name
Test status
Simulation time 13800642 ps
CPU time 0.54 seconds
Started May 26 01:01:21 PM PDT 24
Finished May 26 01:01:23 PM PDT 24
Peak memory 194136 kb
Host smart-b318a5e2-5982-4fa0-a95a-c2de65609ac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512955422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2512955422
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.721139335
Short name T1264
Test name
Test status
Simulation time 13796612 ps
CPU time 0.58 seconds
Started May 26 01:01:23 PM PDT 24
Finished May 26 01:01:25 PM PDT 24
Peak memory 194136 kb
Host smart-1b015bfc-f6c6-4b32-86e0-c14a7646ca97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721139335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.721139335
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1682193105
Short name T77
Test name
Test status
Simulation time 15841000 ps
CPU time 0.67 seconds
Started May 26 01:00:56 PM PDT 24
Finished May 26 01:00:58 PM PDT 24
Peak memory 194700 kb
Host smart-60f37e66-eae6-46e7-a047-741292141121
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682193105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1682193105
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4110269379
Short name T71
Test name
Test status
Simulation time 122036390 ps
CPU time 1.54 seconds
Started May 26 01:00:58 PM PDT 24
Finished May 26 01:01:00 PM PDT 24
Peak memory 196880 kb
Host smart-f6a10d3b-789c-428f-aa4a-fb7d6253addb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110269379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.4110269379
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4013758928
Short name T1252
Test name
Test status
Simulation time 19705581 ps
CPU time 0.59 seconds
Started May 26 01:00:55 PM PDT 24
Finished May 26 01:00:57 PM PDT 24
Peak memory 195168 kb
Host smart-8db0ac88-1462-4643-a3a9-fd976b79a555
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013758928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.4013758928
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.746243860
Short name T1236
Test name
Test status
Simulation time 20980880 ps
CPU time 0.92 seconds
Started May 26 01:01:03 PM PDT 24
Finished May 26 01:01:05 PM PDT 24
Peak memory 199584 kb
Host smart-13e5f336-ab68-4d65-8578-ffd8b550371d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746243860 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.746243860
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1769951828
Short name T89
Test name
Test status
Simulation time 14706955 ps
CPU time 0.6 seconds
Started May 26 01:00:58 PM PDT 24
Finished May 26 01:01:00 PM PDT 24
Peak memory 195228 kb
Host smart-98fe0fbc-b9d9-4b32-aad6-3a2a0779d5bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769951828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1769951828
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2724294593
Short name T1183
Test name
Test status
Simulation time 12871091 ps
CPU time 0.64 seconds
Started May 26 01:01:00 PM PDT 24
Finished May 26 01:01:02 PM PDT 24
Peak memory 194252 kb
Host smart-a65538a3-52f6-4103-822c-ee21ed4d0bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724294593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2724294593
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2374351781
Short name T1213
Test name
Test status
Simulation time 23774827 ps
CPU time 0.7 seconds
Started May 26 01:00:56 PM PDT 24
Finished May 26 01:00:59 PM PDT 24
Peak memory 195400 kb
Host smart-e48aabc9-3bd2-406f-b35f-00d8d228ecfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374351781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2374351781
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.864231118
Short name T1293
Test name
Test status
Simulation time 113593213 ps
CPU time 2.34 seconds
Started May 26 01:00:56 PM PDT 24
Finished May 26 01:00:59 PM PDT 24
Peak memory 199908 kb
Host smart-c95baaf4-1602-4a4b-bfbf-dc5a503cc237
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864231118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.864231118
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1897241140
Short name T95
Test name
Test status
Simulation time 110699565 ps
CPU time 0.99 seconds
Started May 26 01:00:54 PM PDT 24
Finished May 26 01:00:56 PM PDT 24
Peak memory 198888 kb
Host smart-5aa75256-ad0b-4a7d-8e4d-43ed288a302b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897241140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1897241140
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.4210101296
Short name T1194
Test name
Test status
Simulation time 48426597 ps
CPU time 0.56 seconds
Started May 26 01:01:23 PM PDT 24
Finished May 26 01:01:24 PM PDT 24
Peak memory 194272 kb
Host smart-596f09c4-ba90-46a3-ade6-74782dc2dfc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210101296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.4210101296
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1646706916
Short name T1315
Test name
Test status
Simulation time 11985079 ps
CPU time 0.58 seconds
Started May 26 01:01:26 PM PDT 24
Finished May 26 01:01:28 PM PDT 24
Peak memory 194200 kb
Host smart-085d6065-e686-40ac-b90b-3e9eb72d0fca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646706916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1646706916
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1874331812
Short name T1304
Test name
Test status
Simulation time 16607524 ps
CPU time 0.61 seconds
Started May 26 01:01:26 PM PDT 24
Finished May 26 01:01:28 PM PDT 24
Peak memory 194124 kb
Host smart-30186b7e-9853-492d-b3d7-7b8d90a5e884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874331812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1874331812
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3675907813
Short name T1296
Test name
Test status
Simulation time 13796465 ps
CPU time 0.58 seconds
Started May 26 01:01:23 PM PDT 24
Finished May 26 01:01:25 PM PDT 24
Peak memory 194268 kb
Host smart-8e82d31c-5d18-45d5-ae01-ad09aa973ace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675907813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3675907813
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2521836151
Short name T1227
Test name
Test status
Simulation time 47362623 ps
CPU time 0.58 seconds
Started May 26 01:01:23 PM PDT 24
Finished May 26 01:01:24 PM PDT 24
Peak memory 194264 kb
Host smart-364b422f-8fdf-4d45-8da1-e984138490db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521836151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2521836151
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2554318843
Short name T1206
Test name
Test status
Simulation time 19509935 ps
CPU time 0.57 seconds
Started May 26 01:01:29 PM PDT 24
Finished May 26 01:01:30 PM PDT 24
Peak memory 194200 kb
Host smart-bea02be1-1cb0-48b1-93e7-12d32096d0b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554318843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2554318843
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2226415340
Short name T1283
Test name
Test status
Simulation time 22284111 ps
CPU time 0.58 seconds
Started May 26 01:01:26 PM PDT 24
Finished May 26 01:01:28 PM PDT 24
Peak memory 194124 kb
Host smart-d1f15751-e84e-4a01-a8b3-4d24dcf116c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226415340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2226415340
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3699464880
Short name T1217
Test name
Test status
Simulation time 13659524 ps
CPU time 0.58 seconds
Started May 26 01:01:24 PM PDT 24
Finished May 26 01:01:26 PM PDT 24
Peak memory 194260 kb
Host smart-181422e4-94dd-4698-b6c6-ab7ff48cd824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699464880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3699464880
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3580251786
Short name T1254
Test name
Test status
Simulation time 14270724 ps
CPU time 0.58 seconds
Started May 26 01:01:26 PM PDT 24
Finished May 26 01:01:28 PM PDT 24
Peak memory 194420 kb
Host smart-1144f0d3-6744-42b4-8fa3-726c16bb5ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580251786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3580251786
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3123495422
Short name T1211
Test name
Test status
Simulation time 12067139 ps
CPU time 0.57 seconds
Started May 26 01:01:23 PM PDT 24
Finished May 26 01:01:25 PM PDT 24
Peak memory 194064 kb
Host smart-968b3862-2f73-41e8-8ecd-7f5a26bcbfea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123495422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3123495422
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.338510909
Short name T1208
Test name
Test status
Simulation time 28347704 ps
CPU time 0.84 seconds
Started May 26 01:01:09 PM PDT 24
Finished May 26 01:01:11 PM PDT 24
Peak memory 196084 kb
Host smart-763efc36-7cbf-4aff-9229-ab866f3382c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338510909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.338510909
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4286299891
Short name T1309
Test name
Test status
Simulation time 1084550004 ps
CPU time 1.59 seconds
Started May 26 01:01:05 PM PDT 24
Finished May 26 01:01:07 PM PDT 24
Peak memory 197628 kb
Host smart-be4d6858-5ea8-4d27-96f4-acda3c2275a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286299891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.4286299891
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3278294651
Short name T1308
Test name
Test status
Simulation time 45875681 ps
CPU time 0.6 seconds
Started May 26 01:01:04 PM PDT 24
Finished May 26 01:01:06 PM PDT 24
Peak memory 195148 kb
Host smart-b9722a34-954f-4e47-9ac5-7d98e6420464
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278294651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3278294651
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1379678248
Short name T1190
Test name
Test status
Simulation time 20080844 ps
CPU time 0.73 seconds
Started May 26 01:01:05 PM PDT 24
Finished May 26 01:01:07 PM PDT 24
Peak memory 198504 kb
Host smart-0407af1c-fad6-4784-a31e-49a8cc3ed783
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379678248 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1379678248
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2865122167
Short name T1260
Test name
Test status
Simulation time 12803265 ps
CPU time 0.62 seconds
Started May 26 01:01:06 PM PDT 24
Finished May 26 01:01:08 PM PDT 24
Peak memory 195160 kb
Host smart-883a49cf-e505-44a2-baca-9d8e1c29bfd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865122167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2865122167
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3672337284
Short name T1263
Test name
Test status
Simulation time 29174133 ps
CPU time 0.6 seconds
Started May 26 01:01:09 PM PDT 24
Finished May 26 01:01:10 PM PDT 24
Peak memory 194108 kb
Host smart-de6cd612-d1b0-4990-9c79-374e8b29eab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672337284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3672337284
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.345651877
Short name T90
Test name
Test status
Simulation time 47892158 ps
CPU time 0.61 seconds
Started May 26 01:01:06 PM PDT 24
Finished May 26 01:01:08 PM PDT 24
Peak memory 195264 kb
Host smart-b7df7f9f-a124-4bf3-b89c-9f492a7bd109
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345651877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.345651877
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.389263942
Short name T1189
Test name
Test status
Simulation time 111649839 ps
CPU time 1.38 seconds
Started May 26 01:01:05 PM PDT 24
Finished May 26 01:01:08 PM PDT 24
Peak memory 199828 kb
Host smart-c759d60c-ee51-406a-9687-40bd1743f386
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389263942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.389263942
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1649518068
Short name T99
Test name
Test status
Simulation time 182223048 ps
CPU time 1.5 seconds
Started May 26 01:01:03 PM PDT 24
Finished May 26 01:01:05 PM PDT 24
Peak memory 199012 kb
Host smart-27e4f39f-49ea-4f68-a485-8f0b3ea98601
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649518068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1649518068
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3563160955
Short name T1300
Test name
Test status
Simulation time 13240213 ps
CPU time 0.56 seconds
Started May 26 01:01:24 PM PDT 24
Finished May 26 01:01:25 PM PDT 24
Peak memory 194144 kb
Host smart-91debc8b-bd1c-418d-88f7-43675a033573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563160955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3563160955
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2700577853
Short name T1270
Test name
Test status
Simulation time 45486690 ps
CPU time 0.57 seconds
Started May 26 01:01:25 PM PDT 24
Finished May 26 01:01:27 PM PDT 24
Peak memory 194132 kb
Host smart-05ebba18-6475-4f6e-af69-ceaf40949b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700577853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2700577853
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.4202232920
Short name T1188
Test name
Test status
Simulation time 35675722 ps
CPU time 0.57 seconds
Started May 26 01:01:25 PM PDT 24
Finished May 26 01:01:27 PM PDT 24
Peak memory 194176 kb
Host smart-d153d835-745a-42b3-9ce5-a4355cc474ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202232920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.4202232920
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2905317472
Short name T1187
Test name
Test status
Simulation time 34515667 ps
CPU time 0.61 seconds
Started May 26 01:01:22 PM PDT 24
Finished May 26 01:01:23 PM PDT 24
Peak memory 194188 kb
Host smart-6bcfb719-091b-4f5e-b28c-7addb294e1be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905317472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2905317472
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.288510333
Short name T1256
Test name
Test status
Simulation time 12585889 ps
CPU time 0.6 seconds
Started May 26 01:01:30 PM PDT 24
Finished May 26 01:01:31 PM PDT 24
Peak memory 194076 kb
Host smart-e3d128a2-c514-46d7-b793-100f5816b06c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288510333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.288510333
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2839773662
Short name T1204
Test name
Test status
Simulation time 16804891 ps
CPU time 0.6 seconds
Started May 26 01:01:24 PM PDT 24
Finished May 26 01:01:26 PM PDT 24
Peak memory 194208 kb
Host smart-1fc240cf-153a-42f4-ad8e-6eadedeca17e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839773662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2839773662
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3617710414
Short name T1305
Test name
Test status
Simulation time 53987655 ps
CPU time 0.56 seconds
Started May 26 01:01:25 PM PDT 24
Finished May 26 01:01:27 PM PDT 24
Peak memory 194144 kb
Host smart-6fd642db-525c-4ef9-ad4d-a3f362eed209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617710414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3617710414
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.589862490
Short name T1246
Test name
Test status
Simulation time 14883162 ps
CPU time 0.59 seconds
Started May 26 01:01:32 PM PDT 24
Finished May 26 01:01:33 PM PDT 24
Peak memory 194252 kb
Host smart-b9ed41ef-1bc4-480d-86a9-7b53b14c0703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589862490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.589862490
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.4145118699
Short name T1191
Test name
Test status
Simulation time 35522640 ps
CPU time 0.56 seconds
Started May 26 01:01:24 PM PDT 24
Finished May 26 01:01:25 PM PDT 24
Peak memory 194140 kb
Host smart-30524f6d-360d-4205-9f7b-f0202ad4c2cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145118699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.4145118699
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1552266525
Short name T1226
Test name
Test status
Simulation time 11814537 ps
CPU time 0.65 seconds
Started May 26 01:01:25 PM PDT 24
Finished May 26 01:01:26 PM PDT 24
Peak memory 194140 kb
Host smart-24a094ec-5700-49e9-8ffe-e75b05be6cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552266525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1552266525
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3215408327
Short name T1285
Test name
Test status
Simulation time 31554284 ps
CPU time 0.9 seconds
Started May 26 01:01:05 PM PDT 24
Finished May 26 01:01:08 PM PDT 24
Peak memory 199632 kb
Host smart-5a2a392b-813f-474d-a717-28180ae02a65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215408327 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3215408327
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2689879085
Short name T1313
Test name
Test status
Simulation time 95929825 ps
CPU time 0.59 seconds
Started May 26 01:01:04 PM PDT 24
Finished May 26 01:01:05 PM PDT 24
Peak memory 195164 kb
Host smart-48eccfd9-7ea9-4f24-9c92-06a261cb3aaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689879085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2689879085
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3603937772
Short name T1281
Test name
Test status
Simulation time 17887870 ps
CPU time 0.62 seconds
Started May 26 01:01:09 PM PDT 24
Finished May 26 01:01:10 PM PDT 24
Peak memory 194188 kb
Host smart-8a1f10b4-17d6-451f-b267-cb1ae3e91d08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603937772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3603937772
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2986940562
Short name T1299
Test name
Test status
Simulation time 37084863 ps
CPU time 0.66 seconds
Started May 26 01:01:06 PM PDT 24
Finished May 26 01:01:08 PM PDT 24
Peak memory 195648 kb
Host smart-b3b4b85d-074e-4349-9517-1ec7e1110bea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986940562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2986940562
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.710130182
Short name T1316
Test name
Test status
Simulation time 39251269 ps
CPU time 1.52 seconds
Started May 26 01:01:09 PM PDT 24
Finished May 26 01:01:12 PM PDT 24
Peak memory 199840 kb
Host smart-2da01f66-020c-457a-88aa-deaa79c8eb8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710130182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.710130182
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.55900433
Short name T139
Test name
Test status
Simulation time 159193405 ps
CPU time 0.94 seconds
Started May 26 01:01:09 PM PDT 24
Finished May 26 01:01:11 PM PDT 24
Peak memory 198604 kb
Host smart-28d7d890-125f-4c8b-baa0-6b110f5c1e71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55900433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.55900433
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2119181215
Short name T1200
Test name
Test status
Simulation time 58962901 ps
CPU time 0.64 seconds
Started May 26 01:01:05 PM PDT 24
Finished May 26 01:01:07 PM PDT 24
Peak memory 196948 kb
Host smart-e4c88f7e-5ba9-44ca-a907-dfcf095f76a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119181215 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2119181215
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3177412056
Short name T1312
Test name
Test status
Simulation time 25709714 ps
CPU time 0.64 seconds
Started May 26 01:01:08 PM PDT 24
Finished May 26 01:01:10 PM PDT 24
Peak memory 195268 kb
Host smart-d6804270-10de-47e6-b599-b071251c0dba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177412056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3177412056
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.4068703380
Short name T1248
Test name
Test status
Simulation time 14311571 ps
CPU time 0.56 seconds
Started May 26 01:01:09 PM PDT 24
Finished May 26 01:01:10 PM PDT 24
Peak memory 193952 kb
Host smart-946af905-23c2-466d-b8f7-ad814d0035fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068703380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.4068703380
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.833528305
Short name T1273
Test name
Test status
Simulation time 109215426 ps
CPU time 0.71 seconds
Started May 26 01:01:09 PM PDT 24
Finished May 26 01:01:10 PM PDT 24
Peak memory 196532 kb
Host smart-81ed2ba9-89ea-4785-86cc-310a77b4b941
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833528305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.833528305
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2244030134
Short name T1221
Test name
Test status
Simulation time 49460600 ps
CPU time 1.26 seconds
Started May 26 01:01:07 PM PDT 24
Finished May 26 01:01:09 PM PDT 24
Peak memory 199820 kb
Host smart-120ad7e7-aeea-4c6c-9e10-381b2ccfb952
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244030134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2244030134
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.605795036
Short name T1282
Test name
Test status
Simulation time 54307893 ps
CPU time 0.64 seconds
Started May 26 01:01:05 PM PDT 24
Finished May 26 01:01:07 PM PDT 24
Peak memory 197200 kb
Host smart-8742025b-f07b-45ed-99f8-e5c8b8ab21f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605795036 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.605795036
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.598172380
Short name T1266
Test name
Test status
Simulation time 15757596 ps
CPU time 0.58 seconds
Started May 26 01:01:04 PM PDT 24
Finished May 26 01:01:05 PM PDT 24
Peak memory 195144 kb
Host smart-283404a8-f5fa-4f01-9e29-24b94615cdf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598172380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.598172380
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2734983115
Short name T1220
Test name
Test status
Simulation time 14076108 ps
CPU time 0.56 seconds
Started May 26 01:01:05 PM PDT 24
Finished May 26 01:01:07 PM PDT 24
Peak memory 194240 kb
Host smart-d0a88b7a-7e90-4e25-abaf-36e7c8a3dfa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734983115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2734983115
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.318800727
Short name T1279
Test name
Test status
Simulation time 86305178 ps
CPU time 0.75 seconds
Started May 26 01:01:05 PM PDT 24
Finished May 26 01:01:07 PM PDT 24
Peak memory 197572 kb
Host smart-b11818bb-1edf-446a-b79d-da8d663baadc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318800727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.318800727
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1733300798
Short name T1278
Test name
Test status
Simulation time 33168310 ps
CPU time 0.88 seconds
Started May 26 01:01:05 PM PDT 24
Finished May 26 01:01:07 PM PDT 24
Peak memory 199548 kb
Host smart-1e0b2e30-5929-4025-8776-b52a9b35833d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733300798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1733300798
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1758667120
Short name T1271
Test name
Test status
Simulation time 224828684 ps
CPU time 0.93 seconds
Started May 26 01:01:07 PM PDT 24
Finished May 26 01:01:09 PM PDT 24
Peak memory 198740 kb
Host smart-e061a549-eda4-446c-b7b8-94496a145a39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758667120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1758667120
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.602537894
Short name T1224
Test name
Test status
Simulation time 46850888 ps
CPU time 0.72 seconds
Started May 26 01:01:06 PM PDT 24
Finished May 26 01:01:08 PM PDT 24
Peak memory 197984 kb
Host smart-886291cd-7a1b-4e11-b8a6-57a71cc515cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602537894 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.602537894
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.244445342
Short name T78
Test name
Test status
Simulation time 210210864 ps
CPU time 0.6 seconds
Started May 26 01:01:05 PM PDT 24
Finished May 26 01:01:07 PM PDT 24
Peak memory 195140 kb
Host smart-65ceb30d-d0d6-41b7-a27d-84c6f425b4f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244445342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.244445342
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.874008979
Short name T1275
Test name
Test status
Simulation time 38114155 ps
CPU time 0.57 seconds
Started May 26 01:01:08 PM PDT 24
Finished May 26 01:01:09 PM PDT 24
Peak memory 194208 kb
Host smart-a3293e34-939c-41cb-a794-04f8834e3d4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874008979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.874008979
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1558424709
Short name T84
Test name
Test status
Simulation time 20588181 ps
CPU time 0.68 seconds
Started May 26 01:01:04 PM PDT 24
Finished May 26 01:01:05 PM PDT 24
Peak memory 194680 kb
Host smart-aab7ef63-7561-4316-9219-e1b94960171e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558424709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1558424709
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.4052692164
Short name T1210
Test name
Test status
Simulation time 423027939 ps
CPU time 2.19 seconds
Started May 26 01:01:05 PM PDT 24
Finished May 26 01:01:09 PM PDT 24
Peak memory 199824 kb
Host smart-ba4653e3-d805-411b-a840-0a50fa4aa966
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052692164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.4052692164
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2876118677
Short name T100
Test name
Test status
Simulation time 321213012 ps
CPU time 1.39 seconds
Started May 26 01:01:08 PM PDT 24
Finished May 26 01:01:11 PM PDT 24
Peak memory 199144 kb
Host smart-c3cd4613-3b29-424f-a5cb-c68e48ad68fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876118677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2876118677
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1155234348
Short name T1229
Test name
Test status
Simulation time 123022739 ps
CPU time 0.9 seconds
Started May 26 01:01:13 PM PDT 24
Finished May 26 01:01:15 PM PDT 24
Peak memory 199620 kb
Host smart-56097540-8e22-491e-bc52-31192001bbbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155234348 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1155234348
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1618423360
Short name T75
Test name
Test status
Simulation time 55979089 ps
CPU time 0.56 seconds
Started May 26 01:01:04 PM PDT 24
Finished May 26 01:01:06 PM PDT 24
Peak memory 195164 kb
Host smart-d57dd6b1-8245-4a77-894d-9b3cbab9923b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618423360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1618423360
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1005805004
Short name T1234
Test name
Test status
Simulation time 13482563 ps
CPU time 0.56 seconds
Started May 26 01:01:06 PM PDT 24
Finished May 26 01:01:08 PM PDT 24
Peak memory 194116 kb
Host smart-5c49e6f0-b3a0-402e-b319-d3a1101b7500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005805004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1005805004
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3821331692
Short name T1257
Test name
Test status
Simulation time 13868287 ps
CPU time 0.64 seconds
Started May 26 01:01:04 PM PDT 24
Finished May 26 01:01:05 PM PDT 24
Peak memory 194284 kb
Host smart-c0ae0d91-bd03-4916-9739-62266201903b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821331692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3821331692
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1559930692
Short name T1223
Test name
Test status
Simulation time 42243138 ps
CPU time 1.04 seconds
Started May 26 01:01:07 PM PDT 24
Finished May 26 01:01:09 PM PDT 24
Peak memory 199604 kb
Host smart-b8c9ed1b-dcd9-4a1b-b4bc-da8acb5d5ff7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559930692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1559930692
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3496403283
Short name T94
Test name
Test status
Simulation time 183471547 ps
CPU time 0.91 seconds
Started May 26 01:01:04 PM PDT 24
Finished May 26 01:01:06 PM PDT 24
Peak memory 198716 kb
Host smart-85e1c361-8ada-4932-8d54-8ec55fc6a13d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496403283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3496403283
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2767992674
Short name T564
Test name
Test status
Simulation time 14621913 ps
CPU time 0.58 seconds
Started May 26 02:12:38 PM PDT 24
Finished May 26 02:12:40 PM PDT 24
Peak memory 195380 kb
Host smart-9b6a894a-86ca-49a1-b5cb-de6750973da2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767992674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2767992674
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.4272870557
Short name T911
Test name
Test status
Simulation time 241473427940 ps
CPU time 208.97 seconds
Started May 26 02:12:43 PM PDT 24
Finished May 26 02:16:13 PM PDT 24
Peak memory 200480 kb
Host smart-f632b6c9-3bd7-4558-8a54-1210551c2311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272870557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.4272870557
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1418313489
Short name T109
Test name
Test status
Simulation time 107355384868 ps
CPU time 28.85 seconds
Started May 26 02:12:44 PM PDT 24
Finished May 26 02:13:14 PM PDT 24
Peak memory 200152 kb
Host smart-920a1299-c8f9-49fd-bfbb-4f0645e05554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418313489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1418313489
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.403755576
Short name T195
Test name
Test status
Simulation time 47167579847 ps
CPU time 85.38 seconds
Started May 26 02:12:40 PM PDT 24
Finished May 26 02:14:07 PM PDT 24
Peak memory 200408 kb
Host smart-924f4ef8-2387-43f5-8893-8ad0463ae1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403755576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.403755576
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1655416850
Short name T496
Test name
Test status
Simulation time 40624346227 ps
CPU time 226.16 seconds
Started May 26 02:12:41 PM PDT 24
Finished May 26 02:16:28 PM PDT 24
Peak memory 200488 kb
Host smart-165d9b77-531c-40a5-b3af-0fba1b350239
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655416850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1655416850
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3569518132
Short name T361
Test name
Test status
Simulation time 3169689977 ps
CPU time 5.75 seconds
Started May 26 02:12:41 PM PDT 24
Finished May 26 02:12:48 PM PDT 24
Peak memory 196936 kb
Host smart-98cb4e2c-f28c-48a1-bc02-46d68944d504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569518132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3569518132
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.4253958092
Short name T328
Test name
Test status
Simulation time 68489563490 ps
CPU time 153.05 seconds
Started May 26 02:12:45 PM PDT 24
Finished May 26 02:15:18 PM PDT 24
Peak memory 199404 kb
Host smart-3191f2be-e535-4599-8b7d-be5ea5dd8d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253958092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.4253958092
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3192848194
Short name T863
Test name
Test status
Simulation time 13903936458 ps
CPU time 395.22 seconds
Started May 26 02:12:42 PM PDT 24
Finished May 26 02:19:18 PM PDT 24
Peak memory 200540 kb
Host smart-47e2d195-8efb-4e4c-9ca9-ffa9da019e7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3192848194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3192848194
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2243077351
Short name T339
Test name
Test status
Simulation time 5544650757 ps
CPU time 21.84 seconds
Started May 26 02:12:41 PM PDT 24
Finished May 26 02:13:03 PM PDT 24
Peak memory 198528 kb
Host smart-d9274cdc-7cd6-4cfc-845f-9428eac00e6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2243077351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2243077351
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1760651672
Short name T289
Test name
Test status
Simulation time 35422245863 ps
CPU time 53.09 seconds
Started May 26 02:12:41 PM PDT 24
Finished May 26 02:13:35 PM PDT 24
Peak memory 196224 kb
Host smart-f80a6644-a81a-459e-adde-c2b75ee311a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760651672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1760651672
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.52899114
Short name T1120
Test name
Test status
Simulation time 873903478 ps
CPU time 1.18 seconds
Started May 26 02:12:38 PM PDT 24
Finished May 26 02:12:40 PM PDT 24
Peak memory 198800 kb
Host smart-dc1ffeda-8574-4238-98ba-ceda8192f630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52899114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.52899114
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1251640090
Short name T211
Test name
Test status
Simulation time 28174595931 ps
CPU time 408.57 seconds
Started May 26 02:12:44 PM PDT 24
Finished May 26 02:19:33 PM PDT 24
Peak memory 217228 kb
Host smart-e4351b74-36ad-4c74-8c3b-a0cb637d556e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251640090 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1251640090
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2343197314
Short name T1039
Test name
Test status
Simulation time 12532044102 ps
CPU time 4.78 seconds
Started May 26 02:12:39 PM PDT 24
Finished May 26 02:12:44 PM PDT 24
Peak memory 200480 kb
Host smart-b74948ef-a3b9-4df6-8658-f7953dfccf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343197314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2343197314
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1881498715
Short name T274
Test name
Test status
Simulation time 73799224461 ps
CPU time 25.83 seconds
Started May 26 02:12:39 PM PDT 24
Finished May 26 02:13:05 PM PDT 24
Peak memory 200464 kb
Host smart-d123cb29-51f8-4116-a4b8-789bb1a1971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881498715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1881498715
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1330917446
Short name T580
Test name
Test status
Simulation time 26364669 ps
CPU time 0.61 seconds
Started May 26 02:12:41 PM PDT 24
Finished May 26 02:12:42 PM PDT 24
Peak memory 195892 kb
Host smart-9eb87d55-3305-460b-9e6b-8eae9897af9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330917446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1330917446
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1429146904
Short name T961
Test name
Test status
Simulation time 70104303321 ps
CPU time 57.75 seconds
Started May 26 02:12:39 PM PDT 24
Finished May 26 02:13:37 PM PDT 24
Peak memory 200460 kb
Host smart-d9ce4122-3e20-4c98-9c64-1f6d2f1d9ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429146904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1429146904
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3745798459
Short name T283
Test name
Test status
Simulation time 70470431341 ps
CPU time 32.52 seconds
Started May 26 02:12:40 PM PDT 24
Finished May 26 02:13:14 PM PDT 24
Peak memory 199908 kb
Host smart-6abd8625-a609-46d2-bf88-53cc9b56c681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745798459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3745798459
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3135940194
Short name T1000
Test name
Test status
Simulation time 29893628128 ps
CPU time 41.11 seconds
Started May 26 02:12:41 PM PDT 24
Finished May 26 02:13:23 PM PDT 24
Peak memory 200480 kb
Host smart-46b4e4ed-9c01-462c-83d1-884fb4b84ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135940194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3135940194
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.1258103350
Short name T8
Test name
Test status
Simulation time 27063266650 ps
CPU time 43.18 seconds
Started May 26 02:12:44 PM PDT 24
Finished May 26 02:13:28 PM PDT 24
Peak memory 200488 kb
Host smart-d5124265-8e31-47bb-96d3-6cd2ea26a264
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258103350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1258103350
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.173679246
Short name T873
Test name
Test status
Simulation time 82650720695 ps
CPU time 367.35 seconds
Started May 26 02:12:42 PM PDT 24
Finished May 26 02:18:50 PM PDT 24
Peak memory 200480 kb
Host smart-26680285-800c-41a3-adec-25c89d0dee8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=173679246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.173679246
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1023411805
Short name T574
Test name
Test status
Simulation time 9526236526 ps
CPU time 6.4 seconds
Started May 26 02:12:37 PM PDT 24
Finished May 26 02:12:44 PM PDT 24
Peak memory 200432 kb
Host smart-37f924ed-c2d8-472d-99cd-209303c12891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023411805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1023411805
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2702634895
Short name T436
Test name
Test status
Simulation time 13179002129 ps
CPU time 22.94 seconds
Started May 26 02:12:44 PM PDT 24
Finished May 26 02:13:08 PM PDT 24
Peak memory 200736 kb
Host smart-c221480b-28de-46dd-aa69-9ef3f80433ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702634895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2702634895
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.605155410
Short name T747
Test name
Test status
Simulation time 23918869463 ps
CPU time 263.03 seconds
Started May 26 02:12:41 PM PDT 24
Finished May 26 02:17:05 PM PDT 24
Peak memory 200560 kb
Host smart-f1293f2d-f737-4910-bf89-879b1f263c9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=605155410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.605155410
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1699326548
Short name T713
Test name
Test status
Simulation time 6599002891 ps
CPU time 53.39 seconds
Started May 26 02:12:40 PM PDT 24
Finished May 26 02:13:35 PM PDT 24
Peak memory 198684 kb
Host smart-03798831-4421-4c16-bf3d-c931d416bce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699326548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1699326548
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3507072112
Short name T400
Test name
Test status
Simulation time 14412388118 ps
CPU time 26.13 seconds
Started May 26 02:12:41 PM PDT 24
Finished May 26 02:13:08 PM PDT 24
Peak memory 200436 kb
Host smart-ee90b895-8816-402e-a5bd-05294f14b80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507072112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3507072112
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3145196652
Short name T505
Test name
Test status
Simulation time 2348771947 ps
CPU time 1.56 seconds
Started May 26 02:12:40 PM PDT 24
Finished May 26 02:12:43 PM PDT 24
Peak memory 196240 kb
Host smart-cdedead3-818e-4833-9411-fe63fbc41267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145196652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3145196652
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2074343080
Short name T34
Test name
Test status
Simulation time 62877295 ps
CPU time 0.89 seconds
Started May 26 02:12:39 PM PDT 24
Finished May 26 02:12:41 PM PDT 24
Peak memory 219012 kb
Host smart-0ff91b4c-62dc-4ef7-80d9-d56e927fe711
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074343080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2074343080
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.224039413
Short name T387
Test name
Test status
Simulation time 504776273 ps
CPU time 5.54 seconds
Started May 26 02:12:40 PM PDT 24
Finished May 26 02:12:46 PM PDT 24
Peak memory 199420 kb
Host smart-f3eee232-9215-403c-b364-95d8e7f3a5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224039413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.224039413
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3091105685
Short name T1138
Test name
Test status
Simulation time 255173121801 ps
CPU time 482.91 seconds
Started May 26 02:12:41 PM PDT 24
Finished May 26 02:20:45 PM PDT 24
Peak memory 216328 kb
Host smart-a5655d55-8370-4570-9e9d-c70983a0b71c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091105685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3091105685
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1154438998
Short name T840
Test name
Test status
Simulation time 79575890556 ps
CPU time 423.02 seconds
Started May 26 02:12:40 PM PDT 24
Finished May 26 02:19:44 PM PDT 24
Peak memory 217400 kb
Host smart-f3fa03b9-5b50-4e34-af64-f283912fb63d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154438998 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1154438998
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2158542714
Short name T1126
Test name
Test status
Simulation time 2249422984 ps
CPU time 2.38 seconds
Started May 26 02:12:41 PM PDT 24
Finished May 26 02:12:45 PM PDT 24
Peak memory 200504 kb
Host smart-fe6acd08-b2cb-431c-8e05-ae28302fdf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158542714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2158542714
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1904778225
Short name T401
Test name
Test status
Simulation time 102911205265 ps
CPU time 42.14 seconds
Started May 26 02:12:41 PM PDT 24
Finished May 26 02:13:24 PM PDT 24
Peak memory 200500 kb
Host smart-310b0ab3-d2d7-469c-a313-c515016eb168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904778225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1904778225
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2047818445
Short name T858
Test name
Test status
Simulation time 14548235 ps
CPU time 0.57 seconds
Started May 26 02:13:08 PM PDT 24
Finished May 26 02:13:10 PM PDT 24
Peak memory 195900 kb
Host smart-047234c2-f397-40d9-aa78-e96c6edbad3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047818445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2047818445
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1681495894
Short name T432
Test name
Test status
Simulation time 124917219575 ps
CPU time 51.19 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:13:53 PM PDT 24
Peak memory 200472 kb
Host smart-bece06a0-ea0c-4341-afdf-bcdecc915b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681495894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1681495894
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.622845407
Short name T554
Test name
Test status
Simulation time 71122868108 ps
CPU time 20.53 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:13:24 PM PDT 24
Peak memory 200484 kb
Host smart-29a7537b-618c-4f6d-834a-e7b8a82fd315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622845407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.622845407
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1775735435
Short name T244
Test name
Test status
Simulation time 20888294020 ps
CPU time 12.49 seconds
Started May 26 02:13:08 PM PDT 24
Finished May 26 02:13:22 PM PDT 24
Peak memory 200544 kb
Host smart-afa77928-360c-428e-96e8-4c91e422b045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775735435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1775735435
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2473798408
Short name T324
Test name
Test status
Simulation time 35389865020 ps
CPU time 11.64 seconds
Started May 26 02:13:09 PM PDT 24
Finished May 26 02:13:22 PM PDT 24
Peak memory 200492 kb
Host smart-ea5e15c3-07d0-413b-8da8-de88b14f534e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473798408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2473798408
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.139817141
Short name T674
Test name
Test status
Simulation time 92970711427 ps
CPU time 706.99 seconds
Started May 26 02:13:10 PM PDT 24
Finished May 26 02:24:57 PM PDT 24
Peak memory 200460 kb
Host smart-4362f214-c512-4824-9b18-1b9dfd3224c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139817141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.139817141
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.227549315
Short name T741
Test name
Test status
Simulation time 1321828001 ps
CPU time 1.36 seconds
Started May 26 02:13:11 PM PDT 24
Finished May 26 02:13:13 PM PDT 24
Peak memory 196528 kb
Host smart-3915c020-c0b5-4a15-b89c-1b01aa9f6348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227549315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.227549315
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2286343008
Short name T1027
Test name
Test status
Simulation time 68062395778 ps
CPU time 40.72 seconds
Started May 26 02:13:07 PM PDT 24
Finished May 26 02:13:49 PM PDT 24
Peak memory 200808 kb
Host smart-2c37afec-4d62-4a9b-9675-d60fc3d8511c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286343008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2286343008
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.564795944
Short name T461
Test name
Test status
Simulation time 9423478078 ps
CPU time 281.74 seconds
Started May 26 02:13:08 PM PDT 24
Finished May 26 02:17:51 PM PDT 24
Peak memory 200472 kb
Host smart-c4b03406-93a3-40f0-86fc-cfed091cdfba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564795944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.564795944
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2195432237
Short name T724
Test name
Test status
Simulation time 6384821779 ps
CPU time 52.54 seconds
Started May 26 02:13:06 PM PDT 24
Finished May 26 02:13:59 PM PDT 24
Peak memory 198636 kb
Host smart-275fed5e-11d9-4981-9460-84c4ddadb8be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2195432237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2195432237
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.4248473430
Short name T1051
Test name
Test status
Simulation time 23612554686 ps
CPU time 22.55 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:13:39 PM PDT 24
Peak memory 200544 kb
Host smart-da3bd2c0-72d7-43cd-8253-483e3f39d975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248473430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.4248473430
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.366423035
Short name T385
Test name
Test status
Simulation time 1890507110 ps
CPU time 2.29 seconds
Started May 26 02:13:05 PM PDT 24
Finished May 26 02:13:08 PM PDT 24
Peak memory 195904 kb
Host smart-19e38601-cdd7-47bd-8bc0-217dde593c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366423035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.366423035
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.68776693
Short name T322
Test name
Test status
Simulation time 531718266 ps
CPU time 1.82 seconds
Started May 26 02:13:03 PM PDT 24
Finished May 26 02:13:07 PM PDT 24
Peak memory 199212 kb
Host smart-88e63528-60d7-4e19-92f4-831eb6cb4713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68776693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.68776693
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2183812224
Short name T826
Test name
Test status
Simulation time 53857273081 ps
CPU time 1195.36 seconds
Started May 26 02:13:09 PM PDT 24
Finished May 26 02:33:05 PM PDT 24
Peak memory 200536 kb
Host smart-acf7f185-ff3d-4806-931c-55815911999a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183812224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2183812224
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1348914667
Short name T1059
Test name
Test status
Simulation time 866295906 ps
CPU time 3.61 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:13:20 PM PDT 24
Peak memory 200252 kb
Host smart-82429db5-6371-4838-b807-5d9f650ca3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348914667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1348914667
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3477981671
Short name T630
Test name
Test status
Simulation time 22297947873 ps
CPU time 19.82 seconds
Started May 26 02:13:05 PM PDT 24
Finished May 26 02:13:26 PM PDT 24
Peak memory 200560 kb
Host smart-e1340c4a-7cfd-465c-9ad0-c4fe6be8e698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477981671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3477981671
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.88552812
Short name T837
Test name
Test status
Simulation time 59379999410 ps
CPU time 50.43 seconds
Started May 26 02:16:27 PM PDT 24
Finished May 26 02:17:18 PM PDT 24
Peak memory 200520 kb
Host smart-e4da267a-71a9-4df5-819a-f741146434e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88552812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.88552812
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2000222781
Short name T1025
Test name
Test status
Simulation time 20428449655 ps
CPU time 17.07 seconds
Started May 26 02:16:27 PM PDT 24
Finished May 26 02:16:45 PM PDT 24
Peak memory 200496 kb
Host smart-ae0d94ad-20eb-4f20-9fa0-c4f75650f858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000222781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2000222781
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.619846937
Short name T2
Test name
Test status
Simulation time 121877923951 ps
CPU time 220.46 seconds
Started May 26 02:16:29 PM PDT 24
Finished May 26 02:20:10 PM PDT 24
Peak memory 200464 kb
Host smart-76849c2a-16d4-4276-a5a2-2782d70bd67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619846937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.619846937
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.226942356
Short name T668
Test name
Test status
Simulation time 33936231896 ps
CPU time 16.09 seconds
Started May 26 02:16:25 PM PDT 24
Finished May 26 02:16:42 PM PDT 24
Peak memory 200572 kb
Host smart-ba621759-ba39-43d3-9ca6-4d094869f4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226942356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.226942356
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.390832340
Short name T653
Test name
Test status
Simulation time 62491350835 ps
CPU time 28.17 seconds
Started May 26 02:16:27 PM PDT 24
Finished May 26 02:16:56 PM PDT 24
Peak memory 200484 kb
Host smart-a2db3e8a-e6c6-4416-96f7-b034876ad8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390832340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.390832340
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.4083374315
Short name T784
Test name
Test status
Simulation time 45287943037 ps
CPU time 25.92 seconds
Started May 26 02:16:27 PM PDT 24
Finished May 26 02:16:54 PM PDT 24
Peak memory 200540 kb
Host smart-5558734d-fe04-419d-8691-ee04f17b5844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083374315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.4083374315
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2537335387
Short name T788
Test name
Test status
Simulation time 59066593460 ps
CPU time 89.44 seconds
Started May 26 02:16:28 PM PDT 24
Finished May 26 02:17:58 PM PDT 24
Peak memory 200564 kb
Host smart-8e0ceff1-1959-43e6-a834-c3419263756a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537335387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2537335387
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3183651003
Short name T769
Test name
Test status
Simulation time 144449794940 ps
CPU time 63.05 seconds
Started May 26 02:16:30 PM PDT 24
Finished May 26 02:17:33 PM PDT 24
Peak memory 200504 kb
Host smart-fbdbe99a-201c-48f8-8029-0ed28ddc1ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183651003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3183651003
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.186309842
Short name T779
Test name
Test status
Simulation time 23274732 ps
CPU time 0.6 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:13:17 PM PDT 24
Peak memory 194900 kb
Host smart-f7acff46-f38e-4d91-a14d-3144707135e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186309842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.186309842
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3017644760
Short name T340
Test name
Test status
Simulation time 64951891329 ps
CPU time 56.89 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:14:13 PM PDT 24
Peak memory 200468 kb
Host smart-1cdc9992-a7d4-469d-8be3-d81999b72b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017644760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3017644760
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2561596264
Short name T427
Test name
Test status
Simulation time 203602053108 ps
CPU time 92.13 seconds
Started May 26 02:13:10 PM PDT 24
Finished May 26 02:14:43 PM PDT 24
Peak memory 200336 kb
Host smart-0b5c0681-a703-475b-91fe-849561c8335d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561596264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2561596264
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2450544204
Short name T818
Test name
Test status
Simulation time 75518401532 ps
CPU time 61 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:14:19 PM PDT 24
Peak memory 200492 kb
Host smart-a2c07e0a-3d58-42a0-85bf-f89ce58fbce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450544204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2450544204
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.20752320
Short name T136
Test name
Test status
Simulation time 36789959704 ps
CPU time 69.42 seconds
Started May 26 02:13:09 PM PDT 24
Finished May 26 02:14:20 PM PDT 24
Peak memory 200524 kb
Host smart-e3b6bcd2-465e-49a9-9ac4-296ec95a7327
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20752320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.20752320
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1496606232
Short name T652
Test name
Test status
Simulation time 58084544493 ps
CPU time 124.16 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:15:21 PM PDT 24
Peak memory 200560 kb
Host smart-bbb1d222-5793-429a-985d-4888e180a316
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496606232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1496606232
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.3172231912
Short name T633
Test name
Test status
Simulation time 11998576609 ps
CPU time 5.49 seconds
Started May 26 02:13:09 PM PDT 24
Finished May 26 02:13:16 PM PDT 24
Peak memory 200328 kb
Host smart-9593c9e3-db99-48d2-87fd-f962ed29d64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172231912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3172231912
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1433972861
Short name T613
Test name
Test status
Simulation time 48667252797 ps
CPU time 132.78 seconds
Started May 26 02:13:08 PM PDT 24
Finished May 26 02:15:22 PM PDT 24
Peak memory 201000 kb
Host smart-b64b9f90-ddc9-4a16-8224-304f90b2ee20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433972861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1433972861
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1175696903
Short name T413
Test name
Test status
Simulation time 11225098862 ps
CPU time 169.84 seconds
Started May 26 02:13:06 PM PDT 24
Finished May 26 02:15:57 PM PDT 24
Peak memory 200584 kb
Host smart-158efb8b-9130-4e60-bc86-b2a09a7a8cc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1175696903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1175696903
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.141949498
Short name T727
Test name
Test status
Simulation time 4448812352 ps
CPU time 3.42 seconds
Started May 26 02:13:06 PM PDT 24
Finished May 26 02:13:10 PM PDT 24
Peak memory 199184 kb
Host smart-e74189b2-7478-4741-b0c4-7d53fee60179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=141949498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.141949498
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2130938424
Short name T926
Test name
Test status
Simulation time 32243461266 ps
CPU time 4.07 seconds
Started May 26 02:13:07 PM PDT 24
Finished May 26 02:13:12 PM PDT 24
Peak memory 200512 kb
Host smart-a08e41be-b486-448b-afe0-c97440989c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130938424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2130938424
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3435540919
Short name T591
Test name
Test status
Simulation time 4747087850 ps
CPU time 1.44 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:13:18 PM PDT 24
Peak memory 196532 kb
Host smart-6bb3aa63-102e-42c2-ad4f-0018e9a623d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435540919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3435540919
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.278720389
Short name T552
Test name
Test status
Simulation time 681652164 ps
CPU time 2 seconds
Started May 26 02:13:06 PM PDT 24
Finished May 26 02:13:09 PM PDT 24
Peak memory 199924 kb
Host smart-64856296-be39-48ac-9397-dbe036e8b299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278720389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.278720389
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1740659285
Short name T515
Test name
Test status
Simulation time 172725456359 ps
CPU time 252.73 seconds
Started May 26 02:13:10 PM PDT 24
Finished May 26 02:17:23 PM PDT 24
Peak memory 200576 kb
Host smart-964277c8-7f2a-42de-90a6-1a18d1c33b5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740659285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1740659285
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1745986402
Short name T469
Test name
Test status
Simulation time 831771571 ps
CPU time 2.7 seconds
Started May 26 02:13:08 PM PDT 24
Finished May 26 02:13:12 PM PDT 24
Peak memory 199036 kb
Host smart-7d92fcd3-6c16-45fe-84a9-e7a7bd74478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745986402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1745986402
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.181706837
Short name T675
Test name
Test status
Simulation time 19856552187 ps
CPU time 18.54 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:13:34 PM PDT 24
Peak memory 200500 kb
Host smart-7e0aa2b9-4281-46af-88e8-9af8353c3604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181706837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.181706837
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3321323005
Short name T754
Test name
Test status
Simulation time 17742654939 ps
CPU time 29.03 seconds
Started May 26 02:16:27 PM PDT 24
Finished May 26 02:16:57 PM PDT 24
Peak memory 200544 kb
Host smart-8bfc392c-3071-4794-baa7-47e5aac503ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321323005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3321323005
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1229400327
Short name T146
Test name
Test status
Simulation time 88818666865 ps
CPU time 154.59 seconds
Started May 26 02:16:27 PM PDT 24
Finished May 26 02:19:02 PM PDT 24
Peak memory 200500 kb
Host smart-b70368c6-e63d-43fc-b655-458c9d2597b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229400327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1229400327
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2676162534
Short name T175
Test name
Test status
Simulation time 86943510736 ps
CPU time 37.76 seconds
Started May 26 02:16:27 PM PDT 24
Finished May 26 02:17:06 PM PDT 24
Peak memory 200540 kb
Host smart-2eaf2ae5-4dbe-47ac-90d9-afdc68b84790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676162534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2676162534
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3304240250
Short name T1166
Test name
Test status
Simulation time 16295906231 ps
CPU time 24.61 seconds
Started May 26 02:16:29 PM PDT 24
Finished May 26 02:16:55 PM PDT 24
Peak memory 200440 kb
Host smart-259c6865-139f-41f9-accd-3c3d308292d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304240250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3304240250
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3015396394
Short name T969
Test name
Test status
Simulation time 113433813924 ps
CPU time 59.17 seconds
Started May 26 02:16:36 PM PDT 24
Finished May 26 02:17:36 PM PDT 24
Peak memory 200536 kb
Host smart-00dc3fdc-3c96-4bdf-98cd-ac3fc3b4c677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015396394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3015396394
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2149956349
Short name T830
Test name
Test status
Simulation time 122819961680 ps
CPU time 140.52 seconds
Started May 26 02:16:35 PM PDT 24
Finished May 26 02:18:56 PM PDT 24
Peak memory 200544 kb
Host smart-36e7bb2a-8dfe-4c61-a28d-68fd0f3ecc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149956349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2149956349
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3274508760
Short name T641
Test name
Test status
Simulation time 230530971964 ps
CPU time 48.21 seconds
Started May 26 02:16:35 PM PDT 24
Finished May 26 02:17:24 PM PDT 24
Peak memory 200504 kb
Host smart-0c1a81b5-2ead-47c8-925f-a39e2cf06a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274508760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3274508760
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3542476485
Short name T332
Test name
Test status
Simulation time 16165457688 ps
CPU time 7.97 seconds
Started May 26 02:16:35 PM PDT 24
Finished May 26 02:16:44 PM PDT 24
Peak memory 200520 kb
Host smart-f9e0eb99-2634-486f-ae95-1103955c9c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542476485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3542476485
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.4259401809
Short name T638
Test name
Test status
Simulation time 63388955276 ps
CPU time 135.14 seconds
Started May 26 02:16:35 PM PDT 24
Finished May 26 02:18:51 PM PDT 24
Peak memory 200560 kb
Host smart-3d98b528-19b3-4cec-91aa-09a0d6734e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259401809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.4259401809
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.293310544
Short name T471
Test name
Test status
Simulation time 43016745 ps
CPU time 0.55 seconds
Started May 26 02:13:10 PM PDT 24
Finished May 26 02:13:11 PM PDT 24
Peak memory 195744 kb
Host smart-9fe795cd-3dcd-4b93-b184-a0fdebf7a4d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293310544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.293310544
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2009434359
Short name T928
Test name
Test status
Simulation time 71803430221 ps
CPU time 91.19 seconds
Started May 26 02:13:06 PM PDT 24
Finished May 26 02:14:38 PM PDT 24
Peak memory 200480 kb
Host smart-7c4bbeb9-cf5d-4cc7-b29c-114779290143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009434359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2009434359
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1146284090
Short name T407
Test name
Test status
Simulation time 64105631137 ps
CPU time 51.34 seconds
Started May 26 02:13:08 PM PDT 24
Finished May 26 02:14:01 PM PDT 24
Peak memory 200608 kb
Host smart-b40d7ec2-aa55-49c4-8005-f918e9a8abf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146284090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1146284090
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.672977298
Short name T404
Test name
Test status
Simulation time 10602963261 ps
CPU time 27.82 seconds
Started May 26 02:13:09 PM PDT 24
Finished May 26 02:13:38 PM PDT 24
Peak memory 200492 kb
Host smart-8c8a418a-1a90-44c5-ae5f-1163db273028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672977298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.672977298
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1810206707
Short name T875
Test name
Test status
Simulation time 41965598330 ps
CPU time 62.75 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:14:19 PM PDT 24
Peak memory 199428 kb
Host smart-d96f8726-54b5-4cac-8d2b-f85966ad868c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810206707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1810206707
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3967364816
Short name T271
Test name
Test status
Simulation time 159580433152 ps
CPU time 253.95 seconds
Started May 26 02:13:10 PM PDT 24
Finished May 26 02:17:25 PM PDT 24
Peak memory 200340 kb
Host smart-fff1e4df-2b0f-4913-979b-1add14de1489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3967364816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3967364816
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3147454152
Short name T1045
Test name
Test status
Simulation time 1660997158 ps
CPU time 4.69 seconds
Started May 26 02:13:08 PM PDT 24
Finished May 26 02:13:14 PM PDT 24
Peak memory 200096 kb
Host smart-2fcb0c04-066b-4f56-adf7-5e797aa940f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147454152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3147454152
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2960629797
Short name T1090
Test name
Test status
Simulation time 242644323886 ps
CPU time 198.23 seconds
Started May 26 02:13:09 PM PDT 24
Finished May 26 02:16:28 PM PDT 24
Peak memory 208888 kb
Host smart-1c050c30-9294-4de4-bd12-f39ea5e0fa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960629797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2960629797
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1893838199
Short name T119
Test name
Test status
Simulation time 3594164501 ps
CPU time 198.69 seconds
Started May 26 02:13:10 PM PDT 24
Finished May 26 02:16:30 PM PDT 24
Peak memory 200580 kb
Host smart-1b625c43-83ff-415a-a2cc-84b01bc6d536
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893838199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1893838199
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.902917653
Short name T447
Test name
Test status
Simulation time 2867519275 ps
CPU time 20.77 seconds
Started May 26 02:13:07 PM PDT 24
Finished May 26 02:13:29 PM PDT 24
Peak memory 198820 kb
Host smart-8e1a9b90-aad0-4537-879c-f391dfeeab94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=902917653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.902917653
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.4020862044
Short name T611
Test name
Test status
Simulation time 26513450782 ps
CPU time 8.96 seconds
Started May 26 02:13:07 PM PDT 24
Finished May 26 02:13:17 PM PDT 24
Peak memory 198272 kb
Host smart-604110ab-26e9-4568-ad5b-79549941791a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020862044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.4020862044
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.139214296
Short name T382
Test name
Test status
Simulation time 2032639386 ps
CPU time 2.18 seconds
Started May 26 02:13:07 PM PDT 24
Finished May 26 02:13:11 PM PDT 24
Peak memory 195892 kb
Host smart-c9e0b1e0-75be-4788-a040-82a315b65f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139214296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.139214296
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2705517115
Short name T589
Test name
Test status
Simulation time 5522065162 ps
CPU time 19.34 seconds
Started May 26 02:13:08 PM PDT 24
Finished May 26 02:13:29 PM PDT 24
Peak memory 200328 kb
Host smart-4009fdec-9318-4fd0-8349-a4180eb9698a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705517115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2705517115
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3007852433
Short name T169
Test name
Test status
Simulation time 44143889948 ps
CPU time 251.68 seconds
Started May 26 02:13:07 PM PDT 24
Finished May 26 02:17:20 PM PDT 24
Peak memory 208764 kb
Host smart-013b036d-7513-46e0-bb03-2a2f5fa03a7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007852433 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3007852433
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1637448422
Short name T617
Test name
Test status
Simulation time 1245695280 ps
CPU time 1.42 seconds
Started May 26 02:13:07 PM PDT 24
Finished May 26 02:13:10 PM PDT 24
Peak memory 199256 kb
Host smart-8b3681ba-1962-4cf7-98e7-d49d18299c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637448422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1637448422
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.944646622
Short name T316
Test name
Test status
Simulation time 131546841196 ps
CPU time 115.65 seconds
Started May 26 02:13:07 PM PDT 24
Finished May 26 02:15:03 PM PDT 24
Peak memory 200472 kb
Host smart-3c2ab332-914a-42dd-aee3-69d0e0d2b9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944646622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.944646622
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3151472390
Short name T514
Test name
Test status
Simulation time 14227952218 ps
CPU time 16.43 seconds
Started May 26 02:16:38 PM PDT 24
Finished May 26 02:16:55 PM PDT 24
Peak memory 200548 kb
Host smart-7613f054-0ff2-47b6-94d0-b62fb68e125a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151472390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3151472390
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3740232669
Short name T389
Test name
Test status
Simulation time 15128706101 ps
CPU time 29.41 seconds
Started May 26 02:16:37 PM PDT 24
Finished May 26 02:17:07 PM PDT 24
Peak memory 200512 kb
Host smart-5439e6b4-5667-439e-b745-7d2234cc9fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740232669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3740232669
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.955114874
Short name T755
Test name
Test status
Simulation time 78428976756 ps
CPU time 34.31 seconds
Started May 26 02:16:35 PM PDT 24
Finished May 26 02:17:11 PM PDT 24
Peak memory 200520 kb
Host smart-0716424b-1305-4ead-835c-728b8073f20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955114874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.955114874
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3623163643
Short name T918
Test name
Test status
Simulation time 32142220256 ps
CPU time 48.07 seconds
Started May 26 02:16:37 PM PDT 24
Finished May 26 02:17:26 PM PDT 24
Peak memory 200444 kb
Host smart-a726f05b-7ed0-4867-8497-f8340517354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623163643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3623163643
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2385835316
Short name T803
Test name
Test status
Simulation time 66152201701 ps
CPU time 52.96 seconds
Started May 26 02:16:38 PM PDT 24
Finished May 26 02:17:32 PM PDT 24
Peak memory 200508 kb
Host smart-3f100fc7-82f0-46c7-bf97-502353c03568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385835316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2385835316
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.965324675
Short name T963
Test name
Test status
Simulation time 121724454474 ps
CPU time 116.31 seconds
Started May 26 02:16:34 PM PDT 24
Finished May 26 02:18:30 PM PDT 24
Peak memory 200488 kb
Host smart-90498aa8-4594-4a2c-82d4-ae7e8dc84014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965324675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.965324675
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2878449457
Short name T955
Test name
Test status
Simulation time 54470555614 ps
CPU time 171.65 seconds
Started May 26 02:16:34 PM PDT 24
Finished May 26 02:19:26 PM PDT 24
Peak memory 200456 kb
Host smart-1b6eb478-d761-434d-98bc-c9943ac79391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878449457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2878449457
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.425404848
Short name T438
Test name
Test status
Simulation time 15509708 ps
CPU time 0.55 seconds
Started May 26 02:13:13 PM PDT 24
Finished May 26 02:13:14 PM PDT 24
Peak memory 195904 kb
Host smart-8dd8109b-b38f-44ec-9293-024220572091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425404848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.425404848
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3497424078
Short name T579
Test name
Test status
Simulation time 107787265384 ps
CPU time 217.13 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:16:55 PM PDT 24
Peak memory 200456 kb
Host smart-ee65eb08-9c7b-4aaf-b7bb-41b9509e2c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497424078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3497424078
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1232667899
Short name T905
Test name
Test status
Simulation time 24909155161 ps
CPU time 37.53 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:13:53 PM PDT 24
Peak memory 199896 kb
Host smart-6a676de3-27a6-4624-b91f-01b14a086872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232667899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1232667899
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.4086936478
Short name T1168
Test name
Test status
Simulation time 36127612903 ps
CPU time 65.48 seconds
Started May 26 02:13:13 PM PDT 24
Finished May 26 02:14:19 PM PDT 24
Peak memory 200436 kb
Host smart-72bae205-60e0-4247-8c7c-830d82b5b141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086936478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.4086936478
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2752385106
Short name T834
Test name
Test status
Simulation time 26190517223 ps
CPU time 44.45 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:14:01 PM PDT 24
Peak memory 198816 kb
Host smart-cfb2c54a-9df3-4a8c-b76d-011422f7a413
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752385106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2752385106
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_loopback.2285728849
Short name T566
Test name
Test status
Simulation time 11766482871 ps
CPU time 3.96 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:13:20 PM PDT 24
Peak memory 200328 kb
Host smart-8ec144fc-a419-4fba-9807-778c7c770eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285728849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2285728849
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2810184172
Short name T822
Test name
Test status
Simulation time 90521819887 ps
CPU time 45.39 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:14:03 PM PDT 24
Peak memory 200808 kb
Host smart-30ecb5b6-0903-4fad-89e3-d21eb1ea0733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810184172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2810184172
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3102544608
Short name T868
Test name
Test status
Simulation time 17606525438 ps
CPU time 954.08 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:29:10 PM PDT 24
Peak memory 200428 kb
Host smart-b4a5f81f-61b9-48e5-bebb-5a9a702f3f3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3102544608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3102544608
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3395383655
Short name T622
Test name
Test status
Simulation time 4113158610 ps
CPU time 5.97 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:13:24 PM PDT 24
Peak memory 199664 kb
Host smart-d563f35e-31d3-4b8c-9852-e6a7963925d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395383655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3395383655
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2354891050
Short name T1104
Test name
Test status
Simulation time 171403945079 ps
CPU time 35.74 seconds
Started May 26 02:13:17 PM PDT 24
Finished May 26 02:13:54 PM PDT 24
Peak memory 200380 kb
Host smart-4bf0bcfe-b4e9-4e0e-a75c-cda863d8293c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354891050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2354891050
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1414993899
Short name T1171
Test name
Test status
Simulation time 43328287779 ps
CPU time 68.26 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:14:26 PM PDT 24
Peak memory 196272 kb
Host smart-5f80961b-3f52-40b1-bc3f-9aa1efd5f8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414993899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1414993899
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1529182137
Short name T276
Test name
Test status
Simulation time 482000768 ps
CPU time 1.09 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:13:16 PM PDT 24
Peak memory 198840 kb
Host smart-199dc536-7685-455b-be58-4186fbbd0135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529182137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1529182137
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1843234021
Short name T492
Test name
Test status
Simulation time 225950363903 ps
CPU time 66.74 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:14:25 PM PDT 24
Peak memory 200452 kb
Host smart-0e2e90c0-c105-4734-a29c-a719e3985a82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843234021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1843234021
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3248816580
Short name T62
Test name
Test status
Simulation time 74356426029 ps
CPU time 1225.17 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:33:42 PM PDT 24
Peak memory 225492 kb
Host smart-6ad12d2c-5917-4990-bcf6-80d453b5de6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248816580 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3248816580
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1330129974
Short name T290
Test name
Test status
Simulation time 2943887588 ps
CPU time 1.8 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:13:17 PM PDT 24
Peak memory 200492 kb
Host smart-41ed360e-3e44-479c-8a1f-87df6f7224b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330129974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1330129974
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1920090530
Short name T689
Test name
Test status
Simulation time 24406614737 ps
CPU time 16.21 seconds
Started May 26 02:13:13 PM PDT 24
Finished May 26 02:13:30 PM PDT 24
Peak memory 198464 kb
Host smart-28b290c9-447a-4a6c-9af8-0a7000442330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920090530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1920090530
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1694327220
Short name T1152
Test name
Test status
Simulation time 15718973115 ps
CPU time 21.31 seconds
Started May 26 02:16:36 PM PDT 24
Finished May 26 02:16:58 PM PDT 24
Peak memory 200464 kb
Host smart-f5b68470-055b-4237-b07c-392bbf391d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694327220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1694327220
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1293082044
Short name T745
Test name
Test status
Simulation time 48193122147 ps
CPU time 20.4 seconds
Started May 26 02:16:35 PM PDT 24
Finished May 26 02:16:57 PM PDT 24
Peak memory 200484 kb
Host smart-0f2b4e22-c8ee-43be-aa91-1b2741972ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293082044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1293082044
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2505735160
Short name T761
Test name
Test status
Simulation time 81203838498 ps
CPU time 25.09 seconds
Started May 26 02:16:34 PM PDT 24
Finished May 26 02:17:00 PM PDT 24
Peak memory 200556 kb
Host smart-52d1b204-98a4-4e60-8954-70239234a3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505735160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2505735160
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3281149627
Short name T738
Test name
Test status
Simulation time 138342807334 ps
CPU time 228.98 seconds
Started May 26 02:16:36 PM PDT 24
Finished May 26 02:20:26 PM PDT 24
Peak memory 200600 kb
Host smart-10923b00-072a-41ae-806c-4eddd7075252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281149627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3281149627
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.591591438
Short name T734
Test name
Test status
Simulation time 82140291481 ps
CPU time 117.44 seconds
Started May 26 02:16:43 PM PDT 24
Finished May 26 02:18:41 PM PDT 24
Peak memory 200568 kb
Host smart-59f0dfb6-8b58-4723-9172-25632e9ceb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591591438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.591591438
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1247081252
Short name T449
Test name
Test status
Simulation time 67748108154 ps
CPU time 141.29 seconds
Started May 26 02:16:43 PM PDT 24
Finished May 26 02:19:05 PM PDT 24
Peak memory 200556 kb
Host smart-efbeb48d-e352-4216-b24b-263373b90c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247081252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1247081252
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3218591921
Short name T456
Test name
Test status
Simulation time 36437964 ps
CPU time 0.58 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:13:18 PM PDT 24
Peak memory 195924 kb
Host smart-92daa070-89af-4ec6-a3d6-cfcebbab0fba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218591921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3218591921
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1927821588
Short name T392
Test name
Test status
Simulation time 28380670385 ps
CPU time 32.13 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:13:48 PM PDT 24
Peak memory 200620 kb
Host smart-7d458e67-f6fb-43ed-bbff-fdf86b5a89ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927821588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1927821588
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1820206950
Short name T486
Test name
Test status
Simulation time 298012229988 ps
CPU time 35.58 seconds
Started May 26 02:13:16 PM PDT 24
Finished May 26 02:13:54 PM PDT 24
Peak memory 200416 kb
Host smart-8ed56966-6490-4035-bdd3-f377a7592e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820206950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1820206950
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.3439853713
Short name T1140
Test name
Test status
Simulation time 239710233313 ps
CPU time 179.9 seconds
Started May 26 02:13:13 PM PDT 24
Finished May 26 02:16:13 PM PDT 24
Peak memory 198556 kb
Host smart-4ee422b3-df12-43b4-a4ef-33ad37cca86d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439853713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3439853713
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2055178348
Short name T775
Test name
Test status
Simulation time 140534069551 ps
CPU time 258.9 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:17:36 PM PDT 24
Peak memory 200392 kb
Host smart-afe9e48e-28c6-4e57-b30a-42fb97e89e56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055178348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2055178348
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.475977152
Short name T681
Test name
Test status
Simulation time 6835790622 ps
CPU time 12.93 seconds
Started May 26 02:13:18 PM PDT 24
Finished May 26 02:13:32 PM PDT 24
Peak memory 200504 kb
Host smart-ec0b762a-dea0-4137-9140-fc3f9e6c9998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475977152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.475977152
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.1644882789
Short name T817
Test name
Test status
Simulation time 22499345238 ps
CPU time 413.41 seconds
Started May 26 02:13:42 PM PDT 24
Finished May 26 02:20:35 PM PDT 24
Peak memory 200516 kb
Host smart-c4674b57-3afa-4643-8949-ff90a53b2348
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1644882789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1644882789
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2177971995
Short name T384
Test name
Test status
Simulation time 7179744990 ps
CPU time 36.59 seconds
Started May 26 02:13:17 PM PDT 24
Finished May 26 02:13:55 PM PDT 24
Peak memory 199988 kb
Host smart-7d7e88e9-c540-420b-89b1-67d7052e38b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177971995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2177971995
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1691314509
Short name T521
Test name
Test status
Simulation time 88698139695 ps
CPU time 158.91 seconds
Started May 26 02:13:12 PM PDT 24
Finished May 26 02:15:52 PM PDT 24
Peak memory 200484 kb
Host smart-acfea4e6-5488-4a10-ad65-76784ac8ee1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691314509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1691314509
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1327641030
Short name T386
Test name
Test status
Simulation time 4931165185 ps
CPU time 4.47 seconds
Started May 26 02:13:13 PM PDT 24
Finished May 26 02:13:19 PM PDT 24
Peak memory 196536 kb
Host smart-2d5f205a-e03b-491a-a66d-4920359acd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327641030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1327641030
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2260848891
Short name T1009
Test name
Test status
Simulation time 945411819 ps
CPU time 2.31 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:13:18 PM PDT 24
Peak memory 200008 kb
Host smart-e051e9fb-a81d-4e63-be35-c4568487636f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260848891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2260848891
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2316402805
Short name T462
Test name
Test status
Simulation time 46011364087 ps
CPU time 49.35 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:14:06 PM PDT 24
Peak memory 200476 kb
Host smart-052dc676-d51c-429d-845c-25bc372facdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316402805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2316402805
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1603910793
Short name T847
Test name
Test status
Simulation time 265868882226 ps
CPU time 800.43 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:26:37 PM PDT 24
Peak memory 217296 kb
Host smart-f0035c56-2da6-430c-bd50-b7cede5c9598
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603910793 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1603910793
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1801195887
Short name T558
Test name
Test status
Simulation time 468772809 ps
CPU time 1.56 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:13:18 PM PDT 24
Peak memory 197148 kb
Host smart-399983b4-5ece-4df6-a7c7-e372e93298db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801195887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1801195887
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2781676377
Short name T801
Test name
Test status
Simulation time 36652237595 ps
CPU time 65.77 seconds
Started May 26 02:13:17 PM PDT 24
Finished May 26 02:14:24 PM PDT 24
Peak memory 200544 kb
Host smart-cf44feb0-e605-4ff3-924b-8bbb0c942201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781676377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2781676377
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2931900264
Short name T181
Test name
Test status
Simulation time 44814955816 ps
CPU time 38.15 seconds
Started May 26 02:16:41 PM PDT 24
Finished May 26 02:17:20 PM PDT 24
Peak memory 200552 kb
Host smart-d4da60be-9e58-4ddb-96d5-b4470cdbb693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931900264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2931900264
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.520881819
Short name T1128
Test name
Test status
Simulation time 43081021431 ps
CPU time 20.11 seconds
Started May 26 02:16:46 PM PDT 24
Finished May 26 02:17:07 PM PDT 24
Peak memory 200404 kb
Host smart-3a07e4d6-fa58-4b0f-a928-80178edc8e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520881819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.520881819
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2317421108
Short name T43
Test name
Test status
Simulation time 60519504606 ps
CPU time 15.32 seconds
Started May 26 02:16:42 PM PDT 24
Finished May 26 02:16:58 PM PDT 24
Peak memory 199628 kb
Host smart-8dd6652b-7965-4bec-9a82-877a4d970c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317421108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2317421108
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.285424409
Short name T294
Test name
Test status
Simulation time 60817238720 ps
CPU time 36.37 seconds
Started May 26 02:16:46 PM PDT 24
Finished May 26 02:17:23 PM PDT 24
Peak memory 200480 kb
Host smart-eac6f6c2-7c0c-4642-b028-7dddbf45e95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285424409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.285424409
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2498645395
Short name T252
Test name
Test status
Simulation time 93517088099 ps
CPU time 77.2 seconds
Started May 26 02:16:42 PM PDT 24
Finished May 26 02:18:00 PM PDT 24
Peak memory 200532 kb
Host smart-9e4ee9b6-ff9d-40e4-9391-4d4f6a630afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498645395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2498645395
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2999837139
Short name T329
Test name
Test status
Simulation time 84173789729 ps
CPU time 128.04 seconds
Started May 26 02:16:42 PM PDT 24
Finished May 26 02:18:51 PM PDT 24
Peak memory 200520 kb
Host smart-152b7a19-3d3a-4775-95cd-b3489821b16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999837139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2999837139
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3335567608
Short name T968
Test name
Test status
Simulation time 259345545298 ps
CPU time 114.37 seconds
Started May 26 02:16:44 PM PDT 24
Finished May 26 02:18:39 PM PDT 24
Peak memory 200532 kb
Host smart-1e86e241-795f-402f-a2bb-aa399b915c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335567608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3335567608
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2797269617
Short name T1060
Test name
Test status
Simulation time 149032216765 ps
CPU time 65.52 seconds
Started May 26 02:16:41 PM PDT 24
Finished May 26 02:17:47 PM PDT 24
Peak memory 200480 kb
Host smart-f2711788-9932-4ff7-ab95-019ba6a6aff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797269617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2797269617
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2669691618
Short name T353
Test name
Test status
Simulation time 68540156299 ps
CPU time 70.39 seconds
Started May 26 02:16:45 PM PDT 24
Finished May 26 02:17:56 PM PDT 24
Peak memory 200468 kb
Host smart-c5ad015a-5eb2-4500-a261-0b32ee114fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669691618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2669691618
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1622552257
Short name T829
Test name
Test status
Simulation time 18160506 ps
CPU time 0.56 seconds
Started May 26 02:13:13 PM PDT 24
Finished May 26 02:13:15 PM PDT 24
Peak memory 195296 kb
Host smart-a4fcbe64-5c0b-4414-8a0d-6b138506552f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622552257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1622552257
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2437707646
Short name T671
Test name
Test status
Simulation time 153876015170 ps
CPU time 55.87 seconds
Started May 26 02:13:13 PM PDT 24
Finished May 26 02:14:10 PM PDT 24
Peak memory 200604 kb
Host smart-cfda54c3-8de0-4e27-87df-6556ee90c274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437707646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2437707646
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2181659075
Short name T1062
Test name
Test status
Simulation time 88937472559 ps
CPU time 179.04 seconds
Started May 26 02:13:18 PM PDT 24
Finished May 26 02:16:18 PM PDT 24
Peak memory 200540 kb
Host smart-d65f19d2-8902-4462-bfd9-bf50b176eed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181659075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2181659075
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.729596556
Short name T714
Test name
Test status
Simulation time 139013218659 ps
CPU time 38.64 seconds
Started May 26 02:13:13 PM PDT 24
Finished May 26 02:13:52 PM PDT 24
Peak memory 200344 kb
Host smart-57ea1f93-6e45-4d69-8dd6-ff8b05086fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729596556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.729596556
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.4222987136
Short name T1012
Test name
Test status
Simulation time 19973613168 ps
CPU time 29.45 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:13:45 PM PDT 24
Peak memory 199428 kb
Host smart-d6af83f1-fb4a-445d-8047-7e9d4b596626
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222987136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.4222987136
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2700515669
Short name T940
Test name
Test status
Simulation time 150098227274 ps
CPU time 396.47 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:19:52 PM PDT 24
Peak memory 200520 kb
Host smart-559ae72c-33ca-48af-83e9-8d1b8a0d5a7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2700515669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2700515669
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3302076950
Short name T484
Test name
Test status
Simulation time 2955100675 ps
CPU time 5.11 seconds
Started May 26 02:13:17 PM PDT 24
Finished May 26 02:13:24 PM PDT 24
Peak memory 198488 kb
Host smart-c391b2fd-18af-40aa-a88b-636772bd7c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302076950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3302076950
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.4007583530
Short name T894
Test name
Test status
Simulation time 2716274166 ps
CPU time 5.54 seconds
Started May 26 02:13:16 PM PDT 24
Finished May 26 02:13:23 PM PDT 24
Peak memory 195476 kb
Host smart-3e0cfbe3-9549-4563-91aa-224f93593069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007583530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.4007583530
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1879103556
Short name T752
Test name
Test status
Simulation time 19441017740 ps
CPU time 49.41 seconds
Started May 26 02:13:16 PM PDT 24
Finished May 26 02:14:08 PM PDT 24
Peak memory 200532 kb
Host smart-a794e527-e7f9-4641-ad1a-71699f49a942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879103556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1879103556
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2394426665
Short name T986
Test name
Test status
Simulation time 6610344630 ps
CPU time 29.28 seconds
Started May 26 02:13:17 PM PDT 24
Finished May 26 02:13:48 PM PDT 24
Peak memory 199052 kb
Host smart-46eb0a7d-0b27-4def-8d53-883860fb7288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2394426665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2394426665
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1094702059
Short name T454
Test name
Test status
Simulation time 104286523944 ps
CPU time 213.04 seconds
Started May 26 02:13:12 PM PDT 24
Finished May 26 02:16:46 PM PDT 24
Peak memory 200484 kb
Host smart-ec36314f-f011-44e8-8fe1-a5be8a2f9bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094702059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1094702059
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3912637119
Short name T28
Test name
Test status
Simulation time 42072011637 ps
CPU time 66.49 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:14:22 PM PDT 24
Peak memory 196544 kb
Host smart-77a0b9dc-2c53-4caf-9eab-1c8c2d4a7649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912637119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3912637119
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1287322182
Short name T606
Test name
Test status
Simulation time 668303686 ps
CPU time 3.17 seconds
Started May 26 02:13:13 PM PDT 24
Finished May 26 02:13:17 PM PDT 24
Peak memory 198796 kb
Host smart-942a357b-a4a3-401f-9612-696960205199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287322182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1287322182
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.341379370
Short name T491
Test name
Test status
Simulation time 103198883705 ps
CPU time 841.21 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:27:18 PM PDT 24
Peak memory 216964 kb
Host smart-5847ac29-fe65-4b02-9a42-7e4f7547a61d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341379370 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.341379370
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1186104379
Short name T891
Test name
Test status
Simulation time 7176063515 ps
CPU time 14.17 seconds
Started May 26 02:13:16 PM PDT 24
Finished May 26 02:13:32 PM PDT 24
Peak memory 200480 kb
Host smart-28194fd6-437b-4f09-8689-77e28c0aad64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186104379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1186104379
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.25106380
Short name T578
Test name
Test status
Simulation time 26598003754 ps
CPU time 12.4 seconds
Started May 26 02:13:16 PM PDT 24
Finished May 26 02:13:30 PM PDT 24
Peak memory 200520 kb
Host smart-05575b57-99f2-476d-a053-0c5b8a0123f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25106380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.25106380
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1493025597
Short name T892
Test name
Test status
Simulation time 13427179426 ps
CPU time 7.43 seconds
Started May 26 02:16:51 PM PDT 24
Finished May 26 02:16:59 PM PDT 24
Peak memory 200532 kb
Host smart-21c2bd1f-f3cd-4ccd-9fc8-5ea2ec2f68f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493025597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1493025597
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3459400166
Short name T992
Test name
Test status
Simulation time 77933208575 ps
CPU time 41.27 seconds
Started May 26 02:16:42 PM PDT 24
Finished May 26 02:17:24 PM PDT 24
Peak memory 200524 kb
Host smart-09167ee3-6f71-4b09-b867-f25cd1521e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459400166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3459400166
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.491139815
Short name T756
Test name
Test status
Simulation time 114649491977 ps
CPU time 19.6 seconds
Started May 26 02:16:44 PM PDT 24
Finished May 26 02:17:04 PM PDT 24
Peak memory 200548 kb
Host smart-187e0e8b-a5d8-403c-a8a3-b5b9069d0830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491139815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.491139815
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3765258814
Short name T998
Test name
Test status
Simulation time 52764414853 ps
CPU time 54.85 seconds
Started May 26 02:16:42 PM PDT 24
Finished May 26 02:17:38 PM PDT 24
Peak memory 200492 kb
Host smart-88db463b-76a4-4dc8-8222-272e90a0bb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765258814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3765258814
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.543372993
Short name T50
Test name
Test status
Simulation time 27605455260 ps
CPU time 44.3 seconds
Started May 26 02:16:42 PM PDT 24
Finished May 26 02:17:27 PM PDT 24
Peak memory 200488 kb
Host smart-1ea28b31-e49f-4e30-99f3-b67ca28b021f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543372993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.543372993
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.4101750105
Short name T609
Test name
Test status
Simulation time 26439094811 ps
CPU time 41.86 seconds
Started May 26 02:16:44 PM PDT 24
Finished May 26 02:17:26 PM PDT 24
Peak memory 200496 kb
Host smart-897d21f1-0fb7-4da1-af9e-e7d6fb61db69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101750105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.4101750105
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2139505574
Short name T467
Test name
Test status
Simulation time 50792909999 ps
CPU time 15.24 seconds
Started May 26 02:16:40 PM PDT 24
Finished May 26 02:16:56 PM PDT 24
Peak memory 200252 kb
Host smart-2ffa7469-ac70-48e7-bbe1-65efbfa23c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139505574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2139505574
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.306363343
Short name T1108
Test name
Test status
Simulation time 18651990326 ps
CPU time 34.67 seconds
Started May 26 02:16:41 PM PDT 24
Finished May 26 02:17:16 PM PDT 24
Peak memory 200484 kb
Host smart-1e84625a-8a50-4f2e-a0c2-369c419910f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306363343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.306363343
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2915012485
Short name T1097
Test name
Test status
Simulation time 20825225294 ps
CPU time 36.31 seconds
Started May 26 02:16:41 PM PDT 24
Finished May 26 02:17:18 PM PDT 24
Peak memory 200456 kb
Host smart-f2450e53-e0ad-4592-908d-9b95c2199d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915012485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2915012485
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.4180409389
Short name T494
Test name
Test status
Simulation time 29268422511 ps
CPU time 15.49 seconds
Started May 26 02:16:43 PM PDT 24
Finished May 26 02:16:59 PM PDT 24
Peak memory 200548 kb
Host smart-a88793bf-8484-4a0a-b022-640f963e0e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180409389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.4180409389
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.4264372006
Short name T995
Test name
Test status
Simulation time 16134677 ps
CPU time 0.6 seconds
Started May 26 02:13:20 PM PDT 24
Finished May 26 02:13:21 PM PDT 24
Peak memory 196036 kb
Host smart-a20fb0f9-75e4-41df-943e-cd265e3ba5bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264372006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.4264372006
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1247883615
Short name T418
Test name
Test status
Simulation time 102841940330 ps
CPU time 170.05 seconds
Started May 26 02:13:21 PM PDT 24
Finished May 26 02:16:12 PM PDT 24
Peak memory 200528 kb
Host smart-fac07c5b-6b6d-4308-be6e-48dcd3dcda99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247883615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1247883615
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.688576123
Short name T601
Test name
Test status
Simulation time 49648144258 ps
CPU time 37.51 seconds
Started May 26 02:13:20 PM PDT 24
Finished May 26 02:13:58 PM PDT 24
Peak memory 200456 kb
Host smart-6773bcbf-5fd6-4ffb-afc2-fdc2a8808388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688576123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.688576123
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.2977767646
Short name T708
Test name
Test status
Simulation time 246081386841 ps
CPU time 187.95 seconds
Started May 26 02:13:23 PM PDT 24
Finished May 26 02:16:32 PM PDT 24
Peak memory 198340 kb
Host smart-0c87442c-e887-423c-9062-7009c29bf861
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977767646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2977767646
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3411034428
Short name T414
Test name
Test status
Simulation time 203262363399 ps
CPU time 117.65 seconds
Started May 26 02:13:25 PM PDT 24
Finished May 26 02:15:23 PM PDT 24
Peak memory 200532 kb
Host smart-18a23182-c5e7-46b0-aca9-e47fcf13b132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3411034428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3411034428
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.117286231
Short name T364
Test name
Test status
Simulation time 3895989266 ps
CPU time 6.82 seconds
Started May 26 02:13:20 PM PDT 24
Finished May 26 02:13:27 PM PDT 24
Peak memory 199560 kb
Host smart-d04d49f2-0abb-457f-b5d1-407c9646dbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117286231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.117286231
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1039598593
Short name T429
Test name
Test status
Simulation time 34066611799 ps
CPU time 57.82 seconds
Started May 26 02:13:20 PM PDT 24
Finished May 26 02:14:19 PM PDT 24
Peak memory 199420 kb
Host smart-31264ff7-914e-4de6-b284-a3280f53111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039598593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1039598593
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.3488939948
Short name T112
Test name
Test status
Simulation time 11960415547 ps
CPU time 166.72 seconds
Started May 26 02:13:24 PM PDT 24
Finished May 26 02:16:12 PM PDT 24
Peak memory 200488 kb
Host smart-90fdd83c-951a-49ff-a881-e2c3d3ee75a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488939948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3488939948
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.164732271
Short name T1046
Test name
Test status
Simulation time 5645545647 ps
CPU time 13.64 seconds
Started May 26 02:13:23 PM PDT 24
Finished May 26 02:13:37 PM PDT 24
Peak memory 199688 kb
Host smart-7cbb6274-e962-4049-b078-d622df3c6038
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=164732271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.164732271
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.4151697750
Short name T887
Test name
Test status
Simulation time 198809611362 ps
CPU time 25.35 seconds
Started May 26 02:13:26 PM PDT 24
Finished May 26 02:13:52 PM PDT 24
Peak memory 200492 kb
Host smart-bc6aa81c-3595-4582-b912-f282fd6c92c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151697750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.4151697750
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1713397235
Short name T735
Test name
Test status
Simulation time 2724753730 ps
CPU time 1.33 seconds
Started May 26 02:13:26 PM PDT 24
Finished May 26 02:13:28 PM PDT 24
Peak memory 196048 kb
Host smart-3229a59a-43c7-4203-8c7e-f9fce236d787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713397235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1713397235
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1164747414
Short name T57
Test name
Test status
Simulation time 555813208 ps
CPU time 1.95 seconds
Started May 26 02:13:17 PM PDT 24
Finished May 26 02:13:21 PM PDT 24
Peak memory 199248 kb
Host smart-e43067a8-eaf6-4fca-a8a4-d65cf32aefd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164747414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1164747414
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.323526660
Short name T15
Test name
Test status
Simulation time 155884706418 ps
CPU time 498.26 seconds
Started May 26 02:13:21 PM PDT 24
Finished May 26 02:21:40 PM PDT 24
Peak memory 200524 kb
Host smart-3265c404-cdd8-4f18-bd47-88537e6cea1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323526660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.323526660
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1912322321
Short name T729
Test name
Test status
Simulation time 1552974765 ps
CPU time 1.81 seconds
Started May 26 02:13:20 PM PDT 24
Finished May 26 02:13:22 PM PDT 24
Peak memory 199044 kb
Host smart-80522d1e-6b2c-46e1-9345-ca9df2eefe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912322321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1912322321
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1012070609
Short name T286
Test name
Test status
Simulation time 38491502082 ps
CPU time 20.95 seconds
Started May 26 02:13:14 PM PDT 24
Finished May 26 02:13:37 PM PDT 24
Peak memory 200516 kb
Host smart-664a880d-3477-40be-b069-41460c39c3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012070609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1012070609
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.811219330
Short name T224
Test name
Test status
Simulation time 23277918943 ps
CPU time 35.69 seconds
Started May 26 02:16:45 PM PDT 24
Finished May 26 02:17:21 PM PDT 24
Peak memory 200544 kb
Host smart-74370827-b053-4ea2-beb2-2a3c8eb56123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811219330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.811219330
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2643728774
Short name T966
Test name
Test status
Simulation time 127519105833 ps
CPU time 113.08 seconds
Started May 26 02:16:50 PM PDT 24
Finished May 26 02:18:44 PM PDT 24
Peak memory 200480 kb
Host smart-949f0570-005f-442a-ac79-a8fcd5f0e963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643728774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2643728774
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.840595810
Short name T183
Test name
Test status
Simulation time 83049386388 ps
CPU time 120.5 seconds
Started May 26 02:16:51 PM PDT 24
Finished May 26 02:18:52 PM PDT 24
Peak memory 200572 kb
Host smart-c0c195e3-da8b-47ff-a8b7-3e1b09d87818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840595810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.840595810
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.826045035
Short name T303
Test name
Test status
Simulation time 34129723349 ps
CPU time 114.38 seconds
Started May 26 02:16:49 PM PDT 24
Finished May 26 02:18:44 PM PDT 24
Peak memory 200568 kb
Host smart-8e2816f9-da1c-47e6-9eca-adba5f1d51b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826045035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.826045035
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.55750123
Short name T879
Test name
Test status
Simulation time 18971180289 ps
CPU time 39.32 seconds
Started May 26 02:16:52 PM PDT 24
Finished May 26 02:17:33 PM PDT 24
Peak memory 200544 kb
Host smart-47a250c7-d1f2-4599-b2dc-e0b39b050f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55750123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.55750123
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2015747939
Short name T884
Test name
Test status
Simulation time 52834769504 ps
CPU time 27.32 seconds
Started May 26 02:16:53 PM PDT 24
Finished May 26 02:17:20 PM PDT 24
Peak memory 200540 kb
Host smart-649694e0-7045-4947-a4f2-3a85fb8255a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015747939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2015747939
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1961091989
Short name T570
Test name
Test status
Simulation time 77617503168 ps
CPU time 128.88 seconds
Started May 26 02:16:49 PM PDT 24
Finished May 26 02:18:59 PM PDT 24
Peak memory 200544 kb
Host smart-56cc768a-f518-4f34-b75f-0d49d90c4286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961091989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1961091989
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.241066873
Short name T205
Test name
Test status
Simulation time 225806554853 ps
CPU time 22.76 seconds
Started May 26 02:16:50 PM PDT 24
Finished May 26 02:17:13 PM PDT 24
Peak memory 200404 kb
Host smart-4ee80d26-a864-4748-8574-e8b75382d287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241066873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.241066873
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2177091577
Short name T635
Test name
Test status
Simulation time 53638628 ps
CPU time 0.6 seconds
Started May 26 02:13:33 PM PDT 24
Finished May 26 02:13:34 PM PDT 24
Peak memory 195876 kb
Host smart-b8d9d3e4-a7d4-4c87-85e5-40b55c17ab15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177091577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2177091577
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1755618320
Short name T642
Test name
Test status
Simulation time 77849508173 ps
CPU time 24.48 seconds
Started May 26 02:13:20 PM PDT 24
Finished May 26 02:13:45 PM PDT 24
Peak memory 200480 kb
Host smart-ecc463ee-bdba-4306-807c-f26174a0f333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755618320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1755618320
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3241338036
Short name T51
Test name
Test status
Simulation time 43474369301 ps
CPU time 68.56 seconds
Started May 26 02:13:21 PM PDT 24
Finished May 26 02:14:30 PM PDT 24
Peak memory 200492 kb
Host smart-2366e354-bb6b-4da1-aa03-a101aa1a02bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241338036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3241338036
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.72105632
Short name T861
Test name
Test status
Simulation time 25073540452 ps
CPU time 6.32 seconds
Started May 26 02:13:21 PM PDT 24
Finished May 26 02:13:27 PM PDT 24
Peak memory 200472 kb
Host smart-3264890d-5216-42bb-a0ba-7a03fabfa89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72105632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.72105632
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.622595445
Short name T44
Test name
Test status
Simulation time 3672741342 ps
CPU time 6.04 seconds
Started May 26 02:13:26 PM PDT 24
Finished May 26 02:13:32 PM PDT 24
Peak memory 197316 kb
Host smart-3d4811f8-5f67-440e-8d39-e3b07c0ed92b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622595445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.622595445
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2807721527
Short name T1103
Test name
Test status
Simulation time 76828905205 ps
CPU time 217.01 seconds
Started May 26 02:13:27 PM PDT 24
Finished May 26 02:17:05 PM PDT 24
Peak memory 200528 kb
Host smart-50b99e84-0d96-4258-a55a-7fdb55df22d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2807721527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2807721527
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3314502650
Short name T519
Test name
Test status
Simulation time 2150654158 ps
CPU time 1.25 seconds
Started May 26 02:13:35 PM PDT 24
Finished May 26 02:13:37 PM PDT 24
Peak memory 198228 kb
Host smart-22f7e2ca-1e58-432e-87d8-71b9d8a5162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314502650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3314502650
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1485561479
Short name T548
Test name
Test status
Simulation time 103639265734 ps
CPU time 212.69 seconds
Started May 26 02:13:22 PM PDT 24
Finished May 26 02:16:55 PM PDT 24
Peak memory 200812 kb
Host smart-4f8c3ce6-078b-41ac-a597-32342896009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485561479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1485561479
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.3036355952
Short name T636
Test name
Test status
Simulation time 14978667216 ps
CPU time 157.55 seconds
Started May 26 02:13:28 PM PDT 24
Finished May 26 02:16:06 PM PDT 24
Peak memory 200532 kb
Host smart-78331518-74b1-4c70-84bf-26f832a1c2e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3036355952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3036355952
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.175900991
Short name T651
Test name
Test status
Simulation time 7384153756 ps
CPU time 57 seconds
Started May 26 02:13:26 PM PDT 24
Finished May 26 02:14:24 PM PDT 24
Peak memory 200536 kb
Host smart-7ec32cbd-2645-48fc-ad48-94274752be92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=175900991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.175900991
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3151232713
Short name T150
Test name
Test status
Simulation time 37140205662 ps
CPU time 23.65 seconds
Started May 26 02:13:25 PM PDT 24
Finished May 26 02:13:49 PM PDT 24
Peak memory 200516 kb
Host smart-06943260-f5c6-42fe-a25b-e19e77e045cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151232713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3151232713
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.878469854
Short name T1131
Test name
Test status
Simulation time 44509517327 ps
CPU time 71.75 seconds
Started May 26 02:13:23 PM PDT 24
Finished May 26 02:14:35 PM PDT 24
Peak memory 196820 kb
Host smart-42cfc00a-7d47-4b37-bd58-fb4a4b061da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878469854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.878469854
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3322316942
Short name T48
Test name
Test status
Simulation time 852245637 ps
CPU time 2.8 seconds
Started May 26 02:13:21 PM PDT 24
Finished May 26 02:13:25 PM PDT 24
Peak memory 199228 kb
Host smart-19653202-fc63-4889-85e3-3c98f434f93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322316942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3322316942
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2814713023
Short name T488
Test name
Test status
Simulation time 14508632908 ps
CPU time 17.69 seconds
Started May 26 02:13:28 PM PDT 24
Finished May 26 02:13:47 PM PDT 24
Peak memory 200456 kb
Host smart-88115817-50a2-4ab6-a373-4b16f0e6d8a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814713023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2814713023
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.500289358
Short name T583
Test name
Test status
Simulation time 27755693159 ps
CPU time 297.1 seconds
Started May 26 02:13:29 PM PDT 24
Finished May 26 02:18:27 PM PDT 24
Peak memory 216704 kb
Host smart-3834a176-dcf3-4b99-a010-ff60359db3a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500289358 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.500289358
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.567819494
Short name T18
Test name
Test status
Simulation time 480120894 ps
CPU time 1.52 seconds
Started May 26 02:13:35 PM PDT 24
Finished May 26 02:13:37 PM PDT 24
Peak memory 198496 kb
Host smart-8159c43d-2d9a-431e-a7b8-b00c8bb5ab26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567819494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.567819494
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1728923036
Short name T1173
Test name
Test status
Simulation time 123722995094 ps
CPU time 59.47 seconds
Started May 26 02:13:20 PM PDT 24
Finished May 26 02:14:21 PM PDT 24
Peak memory 200524 kb
Host smart-308758f1-3c8c-439a-a241-7054eb266e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728923036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1728923036
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3057625105
Short name T744
Test name
Test status
Simulation time 65784576542 ps
CPU time 66.29 seconds
Started May 26 02:16:53 PM PDT 24
Finished May 26 02:18:00 PM PDT 24
Peak memory 200552 kb
Host smart-d082be46-f9bd-4549-98a6-1861c8223105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057625105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3057625105
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1131649369
Short name T597
Test name
Test status
Simulation time 18324090209 ps
CPU time 8.6 seconds
Started May 26 02:16:50 PM PDT 24
Finished May 26 02:16:59 PM PDT 24
Peak memory 200376 kb
Host smart-3f91957f-adb4-4ae4-aead-9e39fbb0ef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131649369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1131649369
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1967925689
Short name T543
Test name
Test status
Simulation time 113609605321 ps
CPU time 49.29 seconds
Started May 26 02:16:50 PM PDT 24
Finished May 26 02:17:40 PM PDT 24
Peak memory 200508 kb
Host smart-99dbb7c3-1da5-4481-b70e-8b9bcfc75472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967925689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1967925689
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1036891261
Short name T845
Test name
Test status
Simulation time 6631901595 ps
CPU time 10.34 seconds
Started May 26 02:16:50 PM PDT 24
Finished May 26 02:17:01 PM PDT 24
Peak memory 200312 kb
Host smart-4162ed03-ebf3-4843-959e-8c94fd7c6e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036891261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1036891261
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1177659586
Short name T193
Test name
Test status
Simulation time 276040193999 ps
CPU time 73.76 seconds
Started May 26 02:16:49 PM PDT 24
Finished May 26 02:18:04 PM PDT 24
Peak memory 200460 kb
Host smart-883c4625-fceb-4a44-b297-67682ee2f3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177659586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1177659586
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.797724631
Short name T509
Test name
Test status
Simulation time 39469368130 ps
CPU time 13.23 seconds
Started May 26 02:16:51 PM PDT 24
Finished May 26 02:17:05 PM PDT 24
Peak memory 200264 kb
Host smart-250e88c0-6f92-4ef5-847f-301846ddc490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797724631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.797724631
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.958415431
Short name T855
Test name
Test status
Simulation time 63717895861 ps
CPU time 28.63 seconds
Started May 26 02:16:53 PM PDT 24
Finished May 26 02:17:22 PM PDT 24
Peak memory 200576 kb
Host smart-f77feb0d-18b0-4b1e-883b-0f503bb30ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958415431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.958415431
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.83110640
Short name T481
Test name
Test status
Simulation time 20220528896 ps
CPU time 31.19 seconds
Started May 26 02:16:49 PM PDT 24
Finished May 26 02:17:21 PM PDT 24
Peak memory 199028 kb
Host smart-e4e8cb29-7cab-4d05-92ea-69a34124906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83110640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.83110640
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1343457193
Short name T893
Test name
Test status
Simulation time 7247045767 ps
CPU time 12.45 seconds
Started May 26 02:16:49 PM PDT 24
Finished May 26 02:17:02 PM PDT 24
Peak memory 200444 kb
Host smart-e1f98e81-5650-4399-84f3-779bdc4d2f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343457193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1343457193
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1262230842
Short name T261
Test name
Test status
Simulation time 9556648692 ps
CPU time 18.5 seconds
Started May 26 02:16:52 PM PDT 24
Finished May 26 02:17:11 PM PDT 24
Peak memory 200496 kb
Host smart-eb1464cc-2ba2-42a7-b3a5-03102dde0d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262230842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1262230842
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3834825092
Short name T391
Test name
Test status
Simulation time 48835636505 ps
CPU time 23.41 seconds
Started May 26 02:13:29 PM PDT 24
Finished May 26 02:13:53 PM PDT 24
Peak memory 200572 kb
Host smart-f89a6ec3-eb6d-4695-a98e-bb38e4317ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834825092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3834825092
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2910231794
Short name T914
Test name
Test status
Simulation time 48151996753 ps
CPU time 46.61 seconds
Started May 26 02:13:29 PM PDT 24
Finished May 26 02:14:16 PM PDT 24
Peak memory 200488 kb
Host smart-9d13fdd6-6c21-44af-97d6-491cc4468b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910231794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2910231794
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.4075778644
Short name T178
Test name
Test status
Simulation time 38104585292 ps
CPU time 60.41 seconds
Started May 26 02:13:33 PM PDT 24
Finished May 26 02:14:34 PM PDT 24
Peak memory 200452 kb
Host smart-fd0497ff-feee-461b-993a-53fe5df4f17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075778644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.4075778644
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3733899556
Short name T777
Test name
Test status
Simulation time 26451128030 ps
CPU time 48.24 seconds
Started May 26 02:13:27 PM PDT 24
Finished May 26 02:14:16 PM PDT 24
Peak memory 200536 kb
Host smart-231f2df3-857e-4c42-831b-fb53d15023dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733899556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3733899556
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.405303684
Short name T1124
Test name
Test status
Simulation time 94865074245 ps
CPU time 480.42 seconds
Started May 26 02:13:35 PM PDT 24
Finished May 26 02:21:37 PM PDT 24
Peak memory 200500 kb
Host smart-9ad13347-7668-4637-a26c-cce6c40595fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405303684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.405303684
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2838463377
Short name T442
Test name
Test status
Simulation time 2299379696 ps
CPU time 4.77 seconds
Started May 26 02:13:36 PM PDT 24
Finished May 26 02:13:41 PM PDT 24
Peak memory 196300 kb
Host smart-c45b0128-201a-4dbe-8ab8-21c68c52f37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838463377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2838463377
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.664627867
Short name T898
Test name
Test status
Simulation time 89866380583 ps
CPU time 52.44 seconds
Started May 26 02:13:38 PM PDT 24
Finished May 26 02:14:31 PM PDT 24
Peak memory 200768 kb
Host smart-59d179d3-45da-4e0d-8814-ae5a05d8a1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664627867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.664627867
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1953838433
Short name T1143
Test name
Test status
Simulation time 9813765646 ps
CPU time 282.83 seconds
Started May 26 02:13:37 PM PDT 24
Finished May 26 02:18:21 PM PDT 24
Peak memory 200556 kb
Host smart-2504efd5-66ab-4570-97ad-e84137137b43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1953838433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1953838433
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2287257051
Short name T29
Test name
Test status
Simulation time 4214936716 ps
CPU time 36.02 seconds
Started May 26 02:13:27 PM PDT 24
Finished May 26 02:14:03 PM PDT 24
Peak memory 198820 kb
Host smart-21e99f27-bdcc-416f-ba1f-dd07f787357f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287257051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2287257051
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.389820017
Short name T789
Test name
Test status
Simulation time 167696812232 ps
CPU time 14.47 seconds
Started May 26 02:13:37 PM PDT 24
Finished May 26 02:13:53 PM PDT 24
Peak memory 200440 kb
Host smart-b5c25e07-944f-4706-ad06-de99601c098e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389820017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.389820017
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.907450139
Short name T131
Test name
Test status
Simulation time 32845396606 ps
CPU time 48.16 seconds
Started May 26 02:13:38 PM PDT 24
Finished May 26 02:14:27 PM PDT 24
Peak memory 196556 kb
Host smart-44b6669f-4526-4e1c-a227-edfe0478dd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907450139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.907450139
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2282506820
Short name T450
Test name
Test status
Simulation time 105364326 ps
CPU time 0.94 seconds
Started May 26 02:13:28 PM PDT 24
Finished May 26 02:13:30 PM PDT 24
Peak memory 197536 kb
Host smart-fc446943-7bdb-494f-94b8-d2d877ba4002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282506820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2282506820
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.2250444540
Short name T624
Test name
Test status
Simulation time 52203892145 ps
CPU time 88.23 seconds
Started May 26 02:13:36 PM PDT 24
Finished May 26 02:15:05 PM PDT 24
Peak memory 209148 kb
Host smart-cf0821d0-c044-4e75-9591-c06ed72d43f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250444540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2250444540
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3362059876
Short name T556
Test name
Test status
Simulation time 1224430430 ps
CPU time 2.03 seconds
Started May 26 02:13:37 PM PDT 24
Finished May 26 02:13:40 PM PDT 24
Peak memory 199048 kb
Host smart-fc1224d0-bd98-4c63-9b55-c47381c86a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362059876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3362059876
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1582177033
Short name T885
Test name
Test status
Simulation time 90246323586 ps
CPU time 191.48 seconds
Started May 26 02:13:33 PM PDT 24
Finished May 26 02:16:46 PM PDT 24
Peak memory 200508 kb
Host smart-ac66d236-84ab-41ab-b356-b4533577c884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582177033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1582177033
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3206373828
Short name T208
Test name
Test status
Simulation time 96017693321 ps
CPU time 140.91 seconds
Started May 26 02:16:54 PM PDT 24
Finished May 26 02:19:15 PM PDT 24
Peak memory 200508 kb
Host smart-d0b44695-b103-4622-a04f-bb7b826324c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206373828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3206373828
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3659191332
Short name T1050
Test name
Test status
Simulation time 80437787373 ps
CPU time 83.84 seconds
Started May 26 02:16:59 PM PDT 24
Finished May 26 02:18:24 PM PDT 24
Peak memory 200536 kb
Host smart-47a66e57-927a-4333-bc1a-e369cd0f138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659191332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3659191332
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2229495442
Short name T768
Test name
Test status
Simulation time 98476284595 ps
CPU time 158.78 seconds
Started May 26 02:17:01 PM PDT 24
Finished May 26 02:19:40 PM PDT 24
Peak memory 200496 kb
Host smart-a1093ebb-0678-40a7-b226-dd4291ec0e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229495442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2229495442
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2751895858
Short name T188
Test name
Test status
Simulation time 109973808955 ps
CPU time 88.72 seconds
Started May 26 02:16:59 PM PDT 24
Finished May 26 02:18:29 PM PDT 24
Peak memory 200476 kb
Host smart-4257f59c-bb39-4521-be6d-b249c99ed7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751895858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2751895858
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3068216800
Short name T197
Test name
Test status
Simulation time 29697587533 ps
CPU time 47.68 seconds
Started May 26 02:16:58 PM PDT 24
Finished May 26 02:17:46 PM PDT 24
Peak memory 200680 kb
Host smart-eec142b0-f4f0-4d9a-99e6-2c3a656397c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068216800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3068216800
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.778236896
Short name T983
Test name
Test status
Simulation time 141586078759 ps
CPU time 52.34 seconds
Started May 26 02:16:59 PM PDT 24
Finished May 26 02:17:53 PM PDT 24
Peak memory 200484 kb
Host smart-a902ea75-fe03-465b-b8ae-42d330f9b1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778236896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.778236896
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1745006566
Short name T480
Test name
Test status
Simulation time 20170923991 ps
CPU time 30.22 seconds
Started May 26 02:16:59 PM PDT 24
Finished May 26 02:17:30 PM PDT 24
Peak memory 200524 kb
Host smart-ed857bdf-2b51-446c-8298-a6b157949d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745006566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1745006566
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.4232130927
Short name T1134
Test name
Test status
Simulation time 83032205 ps
CPU time 0.58 seconds
Started May 26 02:13:37 PM PDT 24
Finished May 26 02:13:39 PM PDT 24
Peak memory 195912 kb
Host smart-ed4489a5-37f6-4a28-af62-2fbcf15daff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232130927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.4232130927
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.449842174
Short name T544
Test name
Test status
Simulation time 166875100307 ps
CPU time 66.99 seconds
Started May 26 02:13:38 PM PDT 24
Finished May 26 02:14:46 PM PDT 24
Peak memory 200524 kb
Host smart-aa78d392-8092-4f04-b88d-14ae97b8370c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449842174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.449842174
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.921373337
Short name T658
Test name
Test status
Simulation time 145898737725 ps
CPU time 59.04 seconds
Started May 26 02:13:38 PM PDT 24
Finished May 26 02:14:38 PM PDT 24
Peak memory 200308 kb
Host smart-f7bd9bf3-14f8-43a8-aca6-38d0785dfd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921373337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.921373337
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2196035396
Short name T874
Test name
Test status
Simulation time 100935219711 ps
CPU time 93.01 seconds
Started May 26 02:13:36 PM PDT 24
Finished May 26 02:15:10 PM PDT 24
Peak memory 200496 kb
Host smart-f84d9c28-3e67-4a35-b50d-03cf5221abb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196035396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2196035396
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3470225148
Short name T586
Test name
Test status
Simulation time 15375930883 ps
CPU time 8.78 seconds
Started May 26 02:13:37 PM PDT 24
Finished May 26 02:13:47 PM PDT 24
Peak memory 200504 kb
Host smart-552a14a1-b138-43dc-890e-664f084c29d0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470225148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3470225148
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.721899250
Short name T1160
Test name
Test status
Simulation time 87153087918 ps
CPU time 698.42 seconds
Started May 26 02:13:36 PM PDT 24
Finished May 26 02:25:15 PM PDT 24
Peak memory 200560 kb
Host smart-a83a409f-cd59-41e8-9ffc-0a999b2ddae3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=721899250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.721899250
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1276303865
Short name T685
Test name
Test status
Simulation time 5488798972 ps
CPU time 11.05 seconds
Started May 26 02:13:38 PM PDT 24
Finished May 26 02:13:50 PM PDT 24
Peak memory 198808 kb
Host smart-469a232d-458d-40a9-af7c-2d3f997da21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276303865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1276303865
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2464239209
Short name T460
Test name
Test status
Simulation time 159971570384 ps
CPU time 324.76 seconds
Started May 26 02:13:39 PM PDT 24
Finished May 26 02:19:04 PM PDT 24
Peak memory 200644 kb
Host smart-4dd13935-3902-42eb-a06c-a5b3e2862f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464239209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2464239209
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3618629882
Short name T536
Test name
Test status
Simulation time 19489335771 ps
CPU time 1136.39 seconds
Started May 26 02:13:37 PM PDT 24
Finished May 26 02:32:34 PM PDT 24
Peak memory 200376 kb
Host smart-11a79fe7-ab5d-46cf-af27-916c90b4502d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618629882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3618629882
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3477318440
Short name T370
Test name
Test status
Simulation time 4985763564 ps
CPU time 11.76 seconds
Started May 26 02:13:38 PM PDT 24
Finished May 26 02:13:51 PM PDT 24
Peak memory 198676 kb
Host smart-4b2e8b85-e9ab-488c-bb97-668bf32f8518
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3477318440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3477318440
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3974387316
Short name T1036
Test name
Test status
Simulation time 30504506356 ps
CPU time 27.88 seconds
Started May 26 02:13:36 PM PDT 24
Finished May 26 02:14:05 PM PDT 24
Peak memory 200380 kb
Host smart-ddbd23a7-da40-4620-85b1-b5828dab6dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974387316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3974387316
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1043711253
Short name T812
Test name
Test status
Simulation time 5111136428 ps
CPU time 6.87 seconds
Started May 26 02:13:36 PM PDT 24
Finished May 26 02:13:43 PM PDT 24
Peak memory 196528 kb
Host smart-1cd81d0e-d472-4882-9875-c0f1e0897053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043711253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1043711253
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.839629065
Short name T1165
Test name
Test status
Simulation time 713788726 ps
CPU time 5.22 seconds
Started May 26 02:13:37 PM PDT 24
Finished May 26 02:13:44 PM PDT 24
Peak memory 199372 kb
Host smart-c5de1d8a-b21a-43a3-b2bc-c9fd5cc876ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839629065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.839629065
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1609553136
Short name T126
Test name
Test status
Simulation time 158773615062 ps
CPU time 95.76 seconds
Started May 26 02:13:36 PM PDT 24
Finished May 26 02:15:13 PM PDT 24
Peak memory 200512 kb
Host smart-5c3f7645-bd10-465a-b48f-336d683f0044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609553136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1609553136
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1586101648
Short name T66
Test name
Test status
Simulation time 312912469628 ps
CPU time 854.75 seconds
Started May 26 02:13:37 PM PDT 24
Finished May 26 02:27:52 PM PDT 24
Peak memory 217164 kb
Host smart-b27e746d-073d-43c4-b7a6-26cacec89eb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586101648 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1586101648
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3125198837
Short name T330
Test name
Test status
Simulation time 880570417 ps
CPU time 3.61 seconds
Started May 26 02:13:38 PM PDT 24
Finished May 26 02:13:43 PM PDT 24
Peak memory 198864 kb
Host smart-3ba9f437-6240-4f08-b290-660ab31daa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125198837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3125198837
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.917508563
Short name T637
Test name
Test status
Simulation time 111692666878 ps
CPU time 46.3 seconds
Started May 26 02:13:36 PM PDT 24
Finished May 26 02:14:23 PM PDT 24
Peak memory 200528 kb
Host smart-6a2083db-0b5e-4ca7-b7bb-f025f93e2c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917508563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.917508563
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1652952157
Short name T813
Test name
Test status
Simulation time 108408465148 ps
CPU time 934.34 seconds
Started May 26 02:16:59 PM PDT 24
Finished May 26 02:32:35 PM PDT 24
Peak memory 200520 kb
Host smart-f27c29c9-6971-48bb-ad55-b3de1febe70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652952157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1652952157
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1390561949
Short name T135
Test name
Test status
Simulation time 60411821647 ps
CPU time 52.38 seconds
Started May 26 02:16:58 PM PDT 24
Finished May 26 02:17:51 PM PDT 24
Peak memory 200544 kb
Host smart-b32fc7b4-9ad8-4ac1-93dc-093569271091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390561949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1390561949
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2702201621
Short name T557
Test name
Test status
Simulation time 594773506093 ps
CPU time 63.22 seconds
Started May 26 02:16:59 PM PDT 24
Finished May 26 02:18:03 PM PDT 24
Peak memory 200540 kb
Host smart-712d435f-7bd5-422b-a327-e2666ab116ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702201621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2702201621
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2707731488
Short name T876
Test name
Test status
Simulation time 15454064196 ps
CPU time 15.62 seconds
Started May 26 02:16:59 PM PDT 24
Finished May 26 02:17:16 PM PDT 24
Peak memory 200488 kb
Host smart-8edb8a5f-6e2a-4105-a2d6-c4365ac442f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707731488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2707731488
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1896493172
Short name T219
Test name
Test status
Simulation time 36997590602 ps
CPU time 36.71 seconds
Started May 26 02:16:59 PM PDT 24
Finished May 26 02:17:37 PM PDT 24
Peak memory 200496 kb
Host smart-f84aca3a-12d2-4ece-a185-3791e4d76035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896493172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1896493172
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2254244378
Short name T346
Test name
Test status
Simulation time 265558380646 ps
CPU time 113.78 seconds
Started May 26 02:16:59 PM PDT 24
Finished May 26 02:18:54 PM PDT 24
Peak memory 200476 kb
Host smart-56284973-b089-4681-8fec-4cc35b0ab272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254244378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2254244378
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2801568632
Short name T623
Test name
Test status
Simulation time 223064936870 ps
CPU time 144.11 seconds
Started May 26 02:16:58 PM PDT 24
Finished May 26 02:19:24 PM PDT 24
Peak memory 200500 kb
Host smart-b0b4779a-9c06-4751-bf57-1882f49c3f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801568632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2801568632
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2289016749
Short name T1170
Test name
Test status
Simulation time 34077477915 ps
CPU time 60.67 seconds
Started May 26 02:17:01 PM PDT 24
Finished May 26 02:18:02 PM PDT 24
Peak memory 200500 kb
Host smart-46f16e07-feb3-46f5-bb11-ac5b3e20c6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289016749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2289016749
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.822462822
Short name T883
Test name
Test status
Simulation time 17625551436 ps
CPU time 43.66 seconds
Started May 26 02:17:00 PM PDT 24
Finished May 26 02:17:44 PM PDT 24
Peak memory 200572 kb
Host smart-237c8c19-ede2-47c6-bac0-c9f3179426fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822462822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.822462822
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1032607875
Short name T32
Test name
Test status
Simulation time 101879597 ps
CPU time 0.61 seconds
Started May 26 02:12:51 PM PDT 24
Finished May 26 02:12:53 PM PDT 24
Peak memory 196028 kb
Host smart-dcdf5ba7-64e9-47a6-9642-1b5c52962343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032607875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1032607875
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1590400370
Short name T634
Test name
Test status
Simulation time 31824815852 ps
CPU time 12.31 seconds
Started May 26 02:12:52 PM PDT 24
Finished May 26 02:13:07 PM PDT 24
Peak memory 200208 kb
Host smart-e94fb44a-3d02-4f72-ad32-0fec3608c7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590400370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1590400370
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.878346020
Short name T956
Test name
Test status
Simulation time 67280984939 ps
CPU time 33.62 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:13:29 PM PDT 24
Peak memory 200544 kb
Host smart-faf5cd67-fefa-494a-844d-713bda0caa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878346020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.878346020
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.696498093
Short name T1040
Test name
Test status
Simulation time 15393745835 ps
CPU time 7.89 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:13:03 PM PDT 24
Peak memory 200184 kb
Host smart-ba1c8011-f090-4e7a-bc72-aed0f6967282
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696498093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.696498093
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.4186817823
Short name T530
Test name
Test status
Simulation time 79991378572 ps
CPU time 284.05 seconds
Started May 26 02:12:52 PM PDT 24
Finished May 26 02:17:38 PM PDT 24
Peak memory 200452 kb
Host smart-209fb9f8-e2af-494b-8061-b9b5a14fc711
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4186817823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4186817823
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.340842032
Short name T415
Test name
Test status
Simulation time 2955482158 ps
CPU time 7.19 seconds
Started May 26 02:12:52 PM PDT 24
Finished May 26 02:13:00 PM PDT 24
Peak memory 198832 kb
Host smart-a202113f-d6d2-455f-8e48-0694dfaeaff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340842032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.340842032
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1314012081
Short name T420
Test name
Test status
Simulation time 79003210319 ps
CPU time 23.97 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:13:19 PM PDT 24
Peak memory 199616 kb
Host smart-32306cdd-8325-46bc-ab78-18f4bd8c1a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314012081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1314012081
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3673130718
Short name T1037
Test name
Test status
Simulation time 9282896393 ps
CPU time 46.77 seconds
Started May 26 02:12:50 PM PDT 24
Finished May 26 02:13:38 PM PDT 24
Peak memory 200552 kb
Host smart-e66d8ab3-bc20-4258-88b1-36e3984ce936
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3673130718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3673130718
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2158459098
Short name T732
Test name
Test status
Simulation time 6947163980 ps
CPU time 35.36 seconds
Started May 26 02:12:50 PM PDT 24
Finished May 26 02:13:26 PM PDT 24
Peak memory 199848 kb
Host smart-9d07fb20-5eff-47d5-ba5d-9689183c7fa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158459098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2158459098
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3208216496
Short name T594
Test name
Test status
Simulation time 76708474475 ps
CPU time 114.97 seconds
Started May 26 02:12:56 PM PDT 24
Finished May 26 02:14:52 PM PDT 24
Peak memory 196448 kb
Host smart-7901ad79-85a0-4fdd-85d3-482b994d9fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208216496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3208216496
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3377973104
Short name T33
Test name
Test status
Simulation time 55985175 ps
CPU time 0.88 seconds
Started May 26 02:12:56 PM PDT 24
Finished May 26 02:12:58 PM PDT 24
Peak memory 219072 kb
Host smart-dfd223c3-a241-4e3c-b46c-5934c2a0f39a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377973104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3377973104
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2336175166
Short name T947
Test name
Test status
Simulation time 290394612 ps
CPU time 1.58 seconds
Started May 26 02:12:42 PM PDT 24
Finished May 26 02:12:44 PM PDT 24
Peak memory 200436 kb
Host smart-dab2292f-f509-4f45-92d2-c6e92697b1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336175166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2336175166
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.394745488
Short name T588
Test name
Test status
Simulation time 106173087371 ps
CPU time 108.32 seconds
Started May 26 02:12:52 PM PDT 24
Finished May 26 02:14:42 PM PDT 24
Peak memory 200552 kb
Host smart-21e4b69c-1d40-48d8-b45d-f64ed989f5f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394745488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.394745488
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.193661815
Short name T1130
Test name
Test status
Simulation time 42379787944 ps
CPU time 559.94 seconds
Started May 26 02:12:51 PM PDT 24
Finished May 26 02:22:12 PM PDT 24
Peak memory 213536 kb
Host smart-66c5dfd6-9a73-4757-9189-e9c191ba52ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193661815 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.193661815
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1721101589
Short name T545
Test name
Test status
Simulation time 1597342093 ps
CPU time 1.61 seconds
Started May 26 02:12:49 PM PDT 24
Finished May 26 02:12:51 PM PDT 24
Peak memory 199336 kb
Host smart-88a34ee9-6a1e-4004-914e-786ae9c1f57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721101589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1721101589
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1283390887
Short name T726
Test name
Test status
Simulation time 30456843536 ps
CPU time 15.72 seconds
Started May 26 02:12:41 PM PDT 24
Finished May 26 02:12:58 PM PDT 24
Peak memory 200532 kb
Host smart-1abb093a-b3d4-4c30-8e42-eb3e8b42b9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283390887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1283390887
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.4071166695
Short name T398
Test name
Test status
Simulation time 11972933 ps
CPU time 0.57 seconds
Started May 26 02:13:45 PM PDT 24
Finished May 26 02:13:46 PM PDT 24
Peak memory 195348 kb
Host smart-a0c47ead-6077-43ec-9ad5-826ee5e86415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071166695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.4071166695
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.4280773662
Short name T799
Test name
Test status
Simulation time 40989999496 ps
CPU time 80.9 seconds
Started May 26 02:13:39 PM PDT 24
Finished May 26 02:15:01 PM PDT 24
Peak memory 200544 kb
Host smart-bb8de250-7392-4600-ab63-fd38804b4aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280773662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.4280773662
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2709111632
Short name T825
Test name
Test status
Simulation time 254062591811 ps
CPU time 145.42 seconds
Started May 26 02:13:37 PM PDT 24
Finished May 26 02:16:03 PM PDT 24
Peak memory 200440 kb
Host smart-9ef8bca2-8f94-476d-82c3-40bb0c733199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709111632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2709111632
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2760019943
Short name T216
Test name
Test status
Simulation time 21732589511 ps
CPU time 38.57 seconds
Started May 26 02:13:36 PM PDT 24
Finished May 26 02:14:15 PM PDT 24
Peak memory 200540 kb
Host smart-bd5a0a9a-aba0-47df-ac48-2e32e1899263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760019943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2760019943
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1251050364
Short name T881
Test name
Test status
Simulation time 6022878742 ps
CPU time 2.81 seconds
Started May 26 02:13:43 PM PDT 24
Finished May 26 02:13:47 PM PDT 24
Peak memory 197192 kb
Host smart-c79a2822-24a2-4e47-b584-381b21fbac7a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251050364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1251050364
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2884654048
Short name T682
Test name
Test status
Simulation time 99827679870 ps
CPU time 312.99 seconds
Started May 26 02:13:46 PM PDT 24
Finished May 26 02:18:59 PM PDT 24
Peak memory 200552 kb
Host smart-9aacca45-7d7a-4a3e-a42d-e5be2df28e16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884654048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2884654048
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1922706889
Short name T22
Test name
Test status
Simulation time 2817390760 ps
CPU time 5.89 seconds
Started May 26 02:13:43 PM PDT 24
Finished May 26 02:13:50 PM PDT 24
Peak memory 199280 kb
Host smart-a737de45-1e9f-4c7e-b686-1b8a0499a5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922706889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1922706889
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3510360595
Short name T302
Test name
Test status
Simulation time 71656446230 ps
CPU time 40.7 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:14:26 PM PDT 24
Peak memory 199432 kb
Host smart-58cdc1c9-d965-472f-bf0b-fc8bc37fd720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510360595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3510360595
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1737181910
Short name T383
Test name
Test status
Simulation time 19489729212 ps
CPU time 616.88 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:24:02 PM PDT 24
Peak memory 200552 kb
Host smart-b33c6d40-bfc7-4da1-be6b-83f5f06d75b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737181910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1737181910
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.4166822602
Short name T512
Test name
Test status
Simulation time 4666488399 ps
CPU time 10.66 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:13:56 PM PDT 24
Peak memory 198708 kb
Host smart-39b80b98-0040-4034-8cc1-646a7084b73f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4166822602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.4166822602
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3008907613
Short name T723
Test name
Test status
Simulation time 108190150519 ps
CPU time 90.37 seconds
Started May 26 02:13:46 PM PDT 24
Finished May 26 02:15:17 PM PDT 24
Peak memory 200508 kb
Host smart-2b44d71b-bdda-46a8-a9df-939020bf2940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008907613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3008907613
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3639435373
Short name T293
Test name
Test status
Simulation time 2900559161 ps
CPU time 5.26 seconds
Started May 26 02:13:46 PM PDT 24
Finished May 26 02:13:52 PM PDT 24
Peak memory 196308 kb
Host smart-dd641a8a-918d-4341-85f3-d2f174cccc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639435373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3639435373
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1244261382
Short name T1159
Test name
Test status
Simulation time 284583714 ps
CPU time 1.42 seconds
Started May 26 02:13:38 PM PDT 24
Finished May 26 02:13:41 PM PDT 24
Peak memory 198748 kb
Host smart-a6dda197-0a8d-4e74-8fe9-de9166209801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244261382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1244261382
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.291159469
Short name T453
Test name
Test status
Simulation time 207885710043 ps
CPU time 311.78 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:18:57 PM PDT 24
Peak memory 208920 kb
Host smart-67e81dcd-a709-4524-a410-1ff99daf8fe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291159469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.291159469
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3238309080
Short name T1072
Test name
Test status
Simulation time 279439352882 ps
CPU time 1219.17 seconds
Started May 26 02:13:48 PM PDT 24
Finished May 26 02:34:08 PM PDT 24
Peak memory 233188 kb
Host smart-b4776611-32c2-4530-adfe-1398219db9fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238309080 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3238309080
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.842959450
Short name T1003
Test name
Test status
Simulation time 941360062 ps
CPU time 2.12 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:13:48 PM PDT 24
Peak memory 200256 kb
Host smart-c5d684eb-2bf5-4bba-9046-4f35b19d376d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842959450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.842959450
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1631453295
Short name T913
Test name
Test status
Simulation time 40103387777 ps
CPU time 63.74 seconds
Started May 26 02:13:36 PM PDT 24
Finished May 26 02:14:41 PM PDT 24
Peak memory 200536 kb
Host smart-120f357d-8984-4fd9-b0c8-37e3a7ff782e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631453295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1631453295
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1215361374
Short name T710
Test name
Test status
Simulation time 38056850919 ps
CPU time 38.07 seconds
Started May 26 02:16:59 PM PDT 24
Finished May 26 02:17:38 PM PDT 24
Peak memory 200492 kb
Host smart-3341921e-6ff1-4a86-8275-f271341eb59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215361374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1215361374
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3868106866
Short name T282
Test name
Test status
Simulation time 60401027128 ps
CPU time 25.65 seconds
Started May 26 02:17:10 PM PDT 24
Finished May 26 02:17:36 PM PDT 24
Peak memory 200496 kb
Host smart-639674b9-97e4-42ea-9e63-8bcbb3b28eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868106866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3868106866
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.208928357
Short name T833
Test name
Test status
Simulation time 17249228862 ps
CPU time 16.11 seconds
Started May 26 02:17:10 PM PDT 24
Finished May 26 02:17:26 PM PDT 24
Peak memory 200464 kb
Host smart-f5fc62af-a5a8-471a-b35b-e3e0768d6a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208928357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.208928357
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2999285557
Short name T667
Test name
Test status
Simulation time 10279433973 ps
CPU time 9.26 seconds
Started May 26 02:17:09 PM PDT 24
Finished May 26 02:17:19 PM PDT 24
Peak memory 198328 kb
Host smart-93f045c8-b9e3-4cf3-b874-77eee63ad543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999285557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2999285557
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3823812798
Short name T331
Test name
Test status
Simulation time 81344814814 ps
CPU time 33.04 seconds
Started May 26 02:17:08 PM PDT 24
Finished May 26 02:17:42 PM PDT 24
Peak memory 200540 kb
Host smart-03b075e5-e68f-4054-bea2-b614d5be6cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823812798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3823812798
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3319875784
Short name T226
Test name
Test status
Simulation time 112312405479 ps
CPU time 520.91 seconds
Started May 26 02:17:08 PM PDT 24
Finished May 26 02:25:49 PM PDT 24
Peak memory 200560 kb
Host smart-9a89907b-ab8a-46be-a62a-88166426cfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319875784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3319875784
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2952274229
Short name T605
Test name
Test status
Simulation time 340470916115 ps
CPU time 51.78 seconds
Started May 26 02:17:10 PM PDT 24
Finished May 26 02:18:03 PM PDT 24
Peak memory 200512 kb
Host smart-4eb37d94-947c-4e23-b938-03eb419c72c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952274229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2952274229
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1714053806
Short name T395
Test name
Test status
Simulation time 99864783162 ps
CPU time 66.21 seconds
Started May 26 02:17:09 PM PDT 24
Finished May 26 02:18:16 PM PDT 24
Peak memory 200404 kb
Host smart-90ef71e4-86ae-44ff-9963-10b3444f3cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714053806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1714053806
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.981901949
Short name T269
Test name
Test status
Simulation time 88842122420 ps
CPU time 151.25 seconds
Started May 26 02:17:09 PM PDT 24
Finished May 26 02:19:41 PM PDT 24
Peak memory 200496 kb
Host smart-44da237f-94d8-4503-97bf-b4bd685d8f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981901949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.981901949
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2804078886
Short name T443
Test name
Test status
Simulation time 17604881 ps
CPU time 0.56 seconds
Started May 26 02:13:43 PM PDT 24
Finished May 26 02:13:44 PM PDT 24
Peak memory 195924 kb
Host smart-dd9a963d-6155-4079-8a8f-4af84732223c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804078886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2804078886
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3727231927
Short name T1018
Test name
Test status
Simulation time 287883184326 ps
CPU time 57.83 seconds
Started May 26 02:13:43 PM PDT 24
Finished May 26 02:14:42 PM PDT 24
Peak memory 200484 kb
Host smart-bfdf320a-2033-469e-9487-a8bd33bc37b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727231927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3727231927
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2002607829
Short name T161
Test name
Test status
Simulation time 194452090529 ps
CPU time 71.41 seconds
Started May 26 02:13:46 PM PDT 24
Finished May 26 02:14:58 PM PDT 24
Peak memory 200452 kb
Host smart-0e5505a7-6fde-4a68-ab70-98b67d68070c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002607829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2002607829
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.873077563
Short name T795
Test name
Test status
Simulation time 18199729119 ps
CPU time 25.68 seconds
Started May 26 02:13:43 PM PDT 24
Finished May 26 02:14:10 PM PDT 24
Peak memory 200532 kb
Host smart-e5a486dc-5d06-4e98-9636-da7df7ca583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873077563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.873077563
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1260428805
Short name T1148
Test name
Test status
Simulation time 44033289548 ps
CPU time 24.43 seconds
Started May 26 02:13:46 PM PDT 24
Finished May 26 02:14:11 PM PDT 24
Peak memory 200512 kb
Host smart-4922a8c2-7c22-44c9-9524-e01ed1cf9d03
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260428805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1260428805
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.501885140
Short name T1034
Test name
Test status
Simulation time 283023487179 ps
CPU time 623.96 seconds
Started May 26 02:13:45 PM PDT 24
Finished May 26 02:24:10 PM PDT 24
Peak memory 200520 kb
Host smart-b105dd09-a51d-49e0-9293-7873818f3988
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=501885140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.501885140
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.4232226312
Short name T672
Test name
Test status
Simulation time 9620096773 ps
CPU time 12.22 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:13:58 PM PDT 24
Peak memory 199272 kb
Host smart-f5d15570-430a-4260-a51b-b81159c72660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232226312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.4232226312
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.893759835
Short name T16
Test name
Test status
Simulation time 34253492009 ps
CPU time 58.99 seconds
Started May 26 02:13:42 PM PDT 24
Finished May 26 02:14:42 PM PDT 24
Peak memory 200848 kb
Host smart-5af30306-2323-46e5-9498-2e7c23c33e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893759835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.893759835
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1216418329
Short name T758
Test name
Test status
Simulation time 10389194894 ps
CPU time 139.15 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:16:05 PM PDT 24
Peak memory 200444 kb
Host smart-83a6e3f9-08cf-48dc-bbd0-1229b768c71e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216418329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1216418329
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2828238208
Short name T593
Test name
Test status
Simulation time 7255245021 ps
CPU time 33.15 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:14:19 PM PDT 24
Peak memory 198628 kb
Host smart-d5d2c4b1-ef41-4030-b5db-32d99b583918
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2828238208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2828238208
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.730397605
Short name T816
Test name
Test status
Simulation time 141406860077 ps
CPU time 92.05 seconds
Started May 26 02:13:43 PM PDT 24
Finished May 26 02:15:16 PM PDT 24
Peak memory 200448 kb
Host smart-f35e91e8-972a-4d62-8611-7b62813895b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730397605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.730397605
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1404000116
Short name T441
Test name
Test status
Simulation time 2652325239 ps
CPU time 4.89 seconds
Started May 26 02:13:41 PM PDT 24
Finished May 26 02:13:46 PM PDT 24
Peak memory 196252 kb
Host smart-29acd795-bea6-4d2b-b7cc-6b3e6759826f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404000116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1404000116
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3896868363
Short name T798
Test name
Test status
Simulation time 459210954 ps
CPU time 1.88 seconds
Started May 26 02:13:47 PM PDT 24
Finished May 26 02:13:49 PM PDT 24
Peak memory 198808 kb
Host smart-90230b6c-45b9-45dc-ad4e-ff2af35db707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896868363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3896868363
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1829902686
Short name T1028
Test name
Test status
Simulation time 427151161095 ps
CPU time 430.45 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:20:56 PM PDT 24
Peak memory 200508 kb
Host smart-7c83a72d-54fe-4779-98bc-12b161e72000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829902686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1829902686
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1529843875
Short name T921
Test name
Test status
Simulation time 62626439853 ps
CPU time 219.48 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:17:25 PM PDT 24
Peak memory 208776 kb
Host smart-34ef5448-6683-4d83-b3b8-0cb29176b92f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529843875 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1529843875
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.190620685
Short name T423
Test name
Test status
Simulation time 6448802251 ps
CPU time 18.91 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:14:04 PM PDT 24
Peak memory 199876 kb
Host smart-0f388e6f-868c-4a1c-8f45-13c9eec9cbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190620685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.190620685
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.278554531
Short name T1137
Test name
Test status
Simulation time 146949798735 ps
CPU time 341.53 seconds
Started May 26 02:13:43 PM PDT 24
Finished May 26 02:19:26 PM PDT 24
Peak memory 200520 kb
Host smart-c955b601-ed34-4e31-a60e-8f6fdf3f647a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278554531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.278554531
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.63035496
Short name T104
Test name
Test status
Simulation time 31672783413 ps
CPU time 49.19 seconds
Started May 26 02:17:09 PM PDT 24
Finished May 26 02:17:58 PM PDT 24
Peak memory 200580 kb
Host smart-35d5af3b-b5d1-4e91-828e-bb0886141daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63035496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.63035496
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2730523790
Short name T859
Test name
Test status
Simulation time 47968472798 ps
CPU time 18.12 seconds
Started May 26 02:17:08 PM PDT 24
Finished May 26 02:17:27 PM PDT 24
Peak memory 200536 kb
Host smart-6c68afdb-f0e0-4109-b85a-ec2acaea7296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730523790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2730523790
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1850045099
Short name T189
Test name
Test status
Simulation time 115350021071 ps
CPU time 32.24 seconds
Started May 26 02:17:10 PM PDT 24
Finished May 26 02:17:43 PM PDT 24
Peak memory 200480 kb
Host smart-641e0440-a313-4b85-ad55-9a97a05ba2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850045099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1850045099
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2319289156
Short name T620
Test name
Test status
Simulation time 129886489548 ps
CPU time 52.41 seconds
Started May 26 02:17:07 PM PDT 24
Finished May 26 02:18:01 PM PDT 24
Peak memory 200260 kb
Host smart-0a812b92-84bc-401f-87c9-22d7f2732cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319289156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2319289156
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1933395075
Short name T661
Test name
Test status
Simulation time 53106027280 ps
CPU time 86.42 seconds
Started May 26 02:17:10 PM PDT 24
Finished May 26 02:18:37 PM PDT 24
Peak memory 200488 kb
Host smart-fefe4655-d77d-4b1e-9798-916e83fbbb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933395075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1933395075
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3752654611
Short name T210
Test name
Test status
Simulation time 31518411333 ps
CPU time 16.03 seconds
Started May 26 02:17:11 PM PDT 24
Finished May 26 02:17:28 PM PDT 24
Peak memory 200540 kb
Host smart-850120d7-78d3-4070-a04b-0f59373ea062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752654611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3752654611
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1382852956
Short name T214
Test name
Test status
Simulation time 30519175686 ps
CPU time 49.13 seconds
Started May 26 02:17:09 PM PDT 24
Finished May 26 02:17:58 PM PDT 24
Peak memory 200508 kb
Host smart-923ae613-7347-41b4-a3bc-f02586a8115d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382852956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1382852956
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.731010260
Short name T805
Test name
Test status
Simulation time 9918826826 ps
CPU time 8.69 seconds
Started May 26 02:17:09 PM PDT 24
Finished May 26 02:17:19 PM PDT 24
Peak memory 199572 kb
Host smart-595c32a7-e539-45a1-8e6b-9ab126f5ac53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731010260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.731010260
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3569033820
Short name T435
Test name
Test status
Simulation time 20852987 ps
CPU time 0.59 seconds
Started May 26 02:13:56 PM PDT 24
Finished May 26 02:13:58 PM PDT 24
Peak memory 195376 kb
Host smart-bbf0d50d-74bf-41fd-a7f9-0fb0b0128112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569033820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3569033820
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2348904060
Short name T996
Test name
Test status
Simulation time 125335910790 ps
CPU time 115.18 seconds
Started May 26 02:13:46 PM PDT 24
Finished May 26 02:15:42 PM PDT 24
Peak memory 200568 kb
Host smart-056e49d0-55df-4b71-bd58-4355eb78f1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348904060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2348904060
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3521015651
Short name T1132
Test name
Test status
Simulation time 85462915731 ps
CPU time 35.72 seconds
Started May 26 02:13:43 PM PDT 24
Finished May 26 02:14:20 PM PDT 24
Peak memory 200408 kb
Host smart-2e0e4332-3c2f-46b4-b42a-60f90c9988f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521015651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3521015651
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3146615928
Short name T610
Test name
Test status
Simulation time 112160183091 ps
CPU time 36.3 seconds
Started May 26 02:13:45 PM PDT 24
Finished May 26 02:14:22 PM PDT 24
Peak memory 200464 kb
Host smart-f8b400bc-e97c-4639-bbf8-a3a68f36e14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146615928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3146615928
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1736666094
Short name T699
Test name
Test status
Simulation time 6694237532 ps
CPU time 6.34 seconds
Started May 26 02:13:43 PM PDT 24
Finished May 26 02:13:51 PM PDT 24
Peak memory 200444 kb
Host smart-9a5c5623-90b4-4e1f-9fec-94e279594967
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736666094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1736666094
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1286805137
Short name T725
Test name
Test status
Simulation time 68597805897 ps
CPU time 475.74 seconds
Started May 26 02:13:46 PM PDT 24
Finished May 26 02:21:43 PM PDT 24
Peak memory 200524 kb
Host smart-8397ae26-3a6c-441f-8584-1d4d7aef9575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1286805137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1286805137
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.156650626
Short name T518
Test name
Test status
Simulation time 1342103782 ps
CPU time 2.73 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:13:48 PM PDT 24
Peak memory 196520 kb
Host smart-ede453c2-decf-411e-b9b6-09f864fb6dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156650626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.156650626
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3960156176
Short name T12
Test name
Test status
Simulation time 45813473932 ps
CPU time 214.28 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:17:20 PM PDT 24
Peak memory 199272 kb
Host smart-34ab4cab-4de7-4f6d-83d3-2e5c173f397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960156176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3960156176
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3868689157
Short name T571
Test name
Test status
Simulation time 17638833620 ps
CPU time 1045.9 seconds
Started May 26 02:13:46 PM PDT 24
Finished May 26 02:31:13 PM PDT 24
Peak memory 200476 kb
Host smart-3d481f7d-23bf-4e69-bf47-806af1823ff2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3868689157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3868689157
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.626124683
Short name T1118
Test name
Test status
Simulation time 5551355062 ps
CPU time 13.9 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:13:59 PM PDT 24
Peak memory 199340 kb
Host smart-ae1dd8c8-514e-4624-9ee0-b9cd0e75335d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626124683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.626124683
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2505839388
Short name T1109
Test name
Test status
Simulation time 146377213600 ps
CPU time 60.85 seconds
Started May 26 02:13:45 PM PDT 24
Finished May 26 02:14:47 PM PDT 24
Peak memory 200468 kb
Host smart-ff06483b-ce25-4a3c-b569-49a1c1d1c289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505839388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2505839388
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1052546995
Short name T539
Test name
Test status
Simulation time 2807070619 ps
CPU time 5.37 seconds
Started May 26 02:13:45 PM PDT 24
Finished May 26 02:13:51 PM PDT 24
Peak memory 196496 kb
Host smart-e03e1827-3692-44a3-8914-b5e48521fb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052546995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1052546995
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.423290741
Short name T584
Test name
Test status
Simulation time 90309984 ps
CPU time 0.85 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:13:46 PM PDT 24
Peak memory 197612 kb
Host smart-d4e4c31b-66cb-4e34-ad05-ea6ee6f70207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423290741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.423290741
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1593462463
Short name T649
Test name
Test status
Simulation time 315546933075 ps
CPU time 416.22 seconds
Started May 26 02:13:43 PM PDT 24
Finished May 26 02:20:40 PM PDT 24
Peak memory 217052 kb
Host smart-b93906d8-7e39-4b1f-8c5b-76dec70ba8f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593462463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1593462463
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2435858514
Short name T889
Test name
Test status
Simulation time 92718708828 ps
CPU time 1796.66 seconds
Started May 26 02:13:44 PM PDT 24
Finished May 26 02:43:42 PM PDT 24
Peak memory 217028 kb
Host smart-5912c3f9-376b-4d9f-a96b-550a8e2b581f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435858514 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2435858514
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1418999206
Short name T458
Test name
Test status
Simulation time 583687514 ps
CPU time 3.17 seconds
Started May 26 02:13:43 PM PDT 24
Finished May 26 02:13:47 PM PDT 24
Peak memory 199868 kb
Host smart-6a3d5398-836d-4504-9fa0-f99abc1ed0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418999206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1418999206
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.4183319848
Short name T301
Test name
Test status
Simulation time 28863839616 ps
CPU time 11.8 seconds
Started May 26 02:13:43 PM PDT 24
Finished May 26 02:13:57 PM PDT 24
Peak memory 198596 kb
Host smart-093852f3-ebb6-4a48-932f-ab686f8c6ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183319848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.4183319848
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.2788223574
Short name T202
Test name
Test status
Simulation time 100630031876 ps
CPU time 230.99 seconds
Started May 26 02:17:09 PM PDT 24
Finished May 26 02:21:00 PM PDT 24
Peak memory 200548 kb
Host smart-0ea783e3-764c-4fe9-99af-929871735a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788223574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2788223574
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1374517684
Short name T256
Test name
Test status
Simulation time 39252770257 ps
CPU time 18.5 seconds
Started May 26 02:17:09 PM PDT 24
Finished May 26 02:17:28 PM PDT 24
Peak memory 200496 kb
Host smart-0f478a89-a16a-442c-bb88-26b4d60202dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374517684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1374517684
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.770653156
Short name T160
Test name
Test status
Simulation time 159228529670 ps
CPU time 59.74 seconds
Started May 26 02:17:12 PM PDT 24
Finished May 26 02:18:12 PM PDT 24
Peak memory 200528 kb
Host smart-2b25e956-c80d-4286-bfb8-cfd98f97a3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770653156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.770653156
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3877507207
Short name T1176
Test name
Test status
Simulation time 170788496125 ps
CPU time 72.39 seconds
Started May 26 02:17:20 PM PDT 24
Finished May 26 02:18:33 PM PDT 24
Peak memory 200524 kb
Host smart-c2e7ee3d-3739-4ee8-9f62-ed70f062ae1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877507207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3877507207
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3817624104
Short name T640
Test name
Test status
Simulation time 108669145325 ps
CPU time 134 seconds
Started May 26 02:17:18 PM PDT 24
Finished May 26 02:19:32 PM PDT 24
Peak memory 200504 kb
Host smart-fcea0f6e-9c5e-496c-963e-e781757a550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817624104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3817624104
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.927197880
Short name T254
Test name
Test status
Simulation time 52575594100 ps
CPU time 28.42 seconds
Started May 26 02:17:18 PM PDT 24
Finished May 26 02:17:47 PM PDT 24
Peak memory 200512 kb
Host smart-68c98223-846a-4460-bf37-b690da76bf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927197880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.927197880
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3319679057
Short name T815
Test name
Test status
Simulation time 49476692805 ps
CPU time 97.18 seconds
Started May 26 02:17:21 PM PDT 24
Finished May 26 02:18:58 PM PDT 24
Peak memory 200564 kb
Host smart-1104a2f0-fc8c-420d-b1d0-3e212fc49bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319679057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3319679057
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1208764304
Short name T144
Test name
Test status
Simulation time 24651075619 ps
CPU time 38.91 seconds
Started May 26 02:17:20 PM PDT 24
Finished May 26 02:18:00 PM PDT 24
Peak memory 200432 kb
Host smart-c6bd6a39-7754-4d04-8853-47b29ae0832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208764304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1208764304
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1071564079
Short name T924
Test name
Test status
Simulation time 65896839280 ps
CPU time 57.31 seconds
Started May 26 02:17:17 PM PDT 24
Finished May 26 02:18:15 PM PDT 24
Peak memory 200568 kb
Host smart-32d85460-167b-4dca-b82d-178743dd2e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071564079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1071564079
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.844094586
Short name T567
Test name
Test status
Simulation time 12091346 ps
CPU time 0.63 seconds
Started May 26 02:13:54 PM PDT 24
Finished May 26 02:13:56 PM PDT 24
Peak memory 195908 kb
Host smart-e1531539-2a3d-4e7a-86f0-b19d2f66df66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844094586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.844094586
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1733188492
Short name T176
Test name
Test status
Simulation time 150708222786 ps
CPU time 74.99 seconds
Started May 26 02:13:53 PM PDT 24
Finished May 26 02:15:10 PM PDT 24
Peak memory 200512 kb
Host smart-b7f66857-024b-46a7-9f97-1739378b7c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733188492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1733188492
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2808473703
Short name T939
Test name
Test status
Simulation time 19372487957 ps
CPU time 17.04 seconds
Started May 26 02:13:54 PM PDT 24
Finished May 26 02:14:12 PM PDT 24
Peak memory 200424 kb
Host smart-d0dc294d-2530-4bbb-bbcb-00099c4be392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808473703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2808473703
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3621822664
Short name T344
Test name
Test status
Simulation time 65038132876 ps
CPU time 93.08 seconds
Started May 26 02:13:54 PM PDT 24
Finished May 26 02:15:29 PM PDT 24
Peak memory 200500 kb
Host smart-35d885e6-a1aa-46eb-bdba-e505aa90c991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621822664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3621822664
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3886697331
Short name T341
Test name
Test status
Simulation time 121658417992 ps
CPU time 208.13 seconds
Started May 26 02:13:52 PM PDT 24
Finished May 26 02:17:21 PM PDT 24
Peak memory 199452 kb
Host smart-0f3818da-5cf1-4d05-9541-df875d847daf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886697331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3886697331
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.4280443158
Short name T987
Test name
Test status
Simulation time 128237465894 ps
CPU time 489.89 seconds
Started May 26 02:13:56 PM PDT 24
Finished May 26 02:22:06 PM PDT 24
Peak memory 200548 kb
Host smart-1a477ae9-2598-4983-88be-3474d4e35ca7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4280443158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.4280443158
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.76645006
Short name T535
Test name
Test status
Simulation time 2326096283 ps
CPU time 3.98 seconds
Started May 26 02:13:53 PM PDT 24
Finished May 26 02:13:59 PM PDT 24
Peak memory 199208 kb
Host smart-e8d7b1b7-d337-4037-9e67-b53081fc3d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76645006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.76645006
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1934072596
Short name T1030
Test name
Test status
Simulation time 78991535270 ps
CPU time 138.57 seconds
Started May 26 02:13:54 PM PDT 24
Finished May 26 02:16:14 PM PDT 24
Peak memory 200752 kb
Host smart-0ce84771-0ef2-459c-b8f9-ee244f1cf457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934072596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1934072596
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.614534983
Short name T522
Test name
Test status
Simulation time 7928824272 ps
CPU time 240.31 seconds
Started May 26 02:13:53 PM PDT 24
Finished May 26 02:17:55 PM PDT 24
Peak memory 200556 kb
Host smart-785dbbc9-059f-43cc-a51c-991a8d4f5fdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614534983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.614534983
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2707967249
Short name T590
Test name
Test status
Simulation time 2811676126 ps
CPU time 16.42 seconds
Started May 26 02:13:53 PM PDT 24
Finished May 26 02:14:11 PM PDT 24
Peak memory 198608 kb
Host smart-30b9c801-f359-496a-9e2f-dd7f37e3c7dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2707967249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2707967249
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2103735744
Short name T145
Test name
Test status
Simulation time 45817562201 ps
CPU time 35.6 seconds
Started May 26 02:13:53 PM PDT 24
Finished May 26 02:14:30 PM PDT 24
Peak memory 200512 kb
Host smart-f3b02f43-73b9-4d9b-bd7f-8725c2db30d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103735744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2103735744
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1939571125
Short name T393
Test name
Test status
Simulation time 1786001255 ps
CPU time 2.14 seconds
Started May 26 02:13:54 PM PDT 24
Finished May 26 02:13:58 PM PDT 24
Peak memory 195892 kb
Host smart-bd744fa2-9297-4fad-bd4f-4b3ab5161b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939571125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1939571125
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.329121517
Short name T673
Test name
Test status
Simulation time 866093272 ps
CPU time 2.21 seconds
Started May 26 02:13:52 PM PDT 24
Finished May 26 02:13:56 PM PDT 24
Peak memory 198852 kb
Host smart-f8b65a51-e4e4-4a97-87a5-07432e3c0b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329121517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.329121517
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.3449316326
Short name T1084
Test name
Test status
Simulation time 232632420305 ps
CPU time 222.86 seconds
Started May 26 02:13:53 PM PDT 24
Finished May 26 02:17:37 PM PDT 24
Peak memory 208968 kb
Host smart-65cf0bbf-58f5-4658-8ad7-fe83fbdc5dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449316326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3449316326
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1939581716
Short name T1035
Test name
Test status
Simulation time 28011718331 ps
CPU time 744.77 seconds
Started May 26 02:13:52 PM PDT 24
Finished May 26 02:26:18 PM PDT 24
Peak memory 217288 kb
Host smart-15bc7fc8-633e-43a2-979a-b353c8053382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939581716 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1939581716
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2325632134
Short name T931
Test name
Test status
Simulation time 6055818733 ps
CPU time 16.93 seconds
Started May 26 02:13:55 PM PDT 24
Finished May 26 02:14:13 PM PDT 24
Peak memory 200416 kb
Host smart-a3c10cc8-2c9c-4be8-ab0f-ef87b89f8b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325632134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2325632134
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.180965639
Short name T1172
Test name
Test status
Simulation time 20943725627 ps
CPU time 13.38 seconds
Started May 26 02:13:53 PM PDT 24
Finished May 26 02:14:08 PM PDT 24
Peak memory 197172 kb
Host smart-4c7858d1-d79c-49f8-a8d2-62fc9942e4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180965639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.180965639
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.431629715
Short name T56
Test name
Test status
Simulation time 12336883601 ps
CPU time 9.37 seconds
Started May 26 02:17:17 PM PDT 24
Finished May 26 02:17:27 PM PDT 24
Peak memory 198872 kb
Host smart-58a486ae-af2c-4a0b-a8cd-f45e031a050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431629715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.431629715
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1319079079
Short name T596
Test name
Test status
Simulation time 61575797351 ps
CPU time 32.45 seconds
Started May 26 02:17:16 PM PDT 24
Finished May 26 02:17:48 PM PDT 24
Peak memory 200536 kb
Host smart-7ea79691-11f0-49e4-b1c4-7c3f3ab80a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319079079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1319079079
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.4185052411
Short name T869
Test name
Test status
Simulation time 110084827327 ps
CPU time 170.73 seconds
Started May 26 02:17:23 PM PDT 24
Finished May 26 02:20:14 PM PDT 24
Peak memory 200564 kb
Host smart-a404418a-18ef-4732-8d06-01db021dc8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185052411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.4185052411
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3046841468
Short name T1158
Test name
Test status
Simulation time 37274912332 ps
CPU time 68.22 seconds
Started May 26 02:17:19 PM PDT 24
Finished May 26 02:18:28 PM PDT 24
Peak memory 200404 kb
Host smart-46dd79c2-03b1-41db-8956-a1bc8ea1d9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046841468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3046841468
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3915890225
Short name T920
Test name
Test status
Simulation time 110672192078 ps
CPU time 92.95 seconds
Started May 26 02:17:18 PM PDT 24
Finished May 26 02:18:52 PM PDT 24
Peak memory 200496 kb
Host smart-c85fa434-e0f5-470b-beb1-16a0e30c1ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915890225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3915890225
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.4131139577
Short name T218
Test name
Test status
Simulation time 27659460633 ps
CPU time 24.58 seconds
Started May 26 02:17:18 PM PDT 24
Finished May 26 02:17:44 PM PDT 24
Peak memory 200568 kb
Host smart-3c95c53f-440e-4064-8f21-4643b888d59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131139577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.4131139577
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1749143435
Short name T1063
Test name
Test status
Simulation time 11920761642 ps
CPU time 20.93 seconds
Started May 26 02:17:19 PM PDT 24
Finished May 26 02:17:41 PM PDT 24
Peak memory 200488 kb
Host smart-96c414e2-0af6-49f0-842e-cc9032d7deab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749143435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1749143435
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.4285783318
Short name T665
Test name
Test status
Simulation time 224691893213 ps
CPU time 21.15 seconds
Started May 26 02:17:17 PM PDT 24
Finished May 26 02:17:39 PM PDT 24
Peak memory 200316 kb
Host smart-7ef8d9f9-2d15-4c47-8046-2b199947c640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285783318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.4285783318
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3896480066
Short name T600
Test name
Test status
Simulation time 76289507832 ps
CPU time 241.76 seconds
Started May 26 02:17:19 PM PDT 24
Finished May 26 02:21:21 PM PDT 24
Peak memory 200500 kb
Host smart-c042f9d3-7075-487b-999f-1353e790f315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896480066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3896480066
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4224551235
Short name T433
Test name
Test status
Simulation time 20450294 ps
CPU time 0.59 seconds
Started May 26 02:14:00 PM PDT 24
Finished May 26 02:14:02 PM PDT 24
Peak memory 195876 kb
Host smart-8cae06ea-2fa0-4277-b381-c11d0c9289d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224551235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4224551235
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.4221230408
Short name T1119
Test name
Test status
Simulation time 19973266911 ps
CPU time 17.54 seconds
Started May 26 02:13:53 PM PDT 24
Finished May 26 02:14:12 PM PDT 24
Peak memory 200412 kb
Host smart-4ceb01a7-2be5-440d-af06-dddc3df7dce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221230408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.4221230408
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1553420738
Short name T236
Test name
Test status
Simulation time 150188575547 ps
CPU time 309.03 seconds
Started May 26 02:13:54 PM PDT 24
Finished May 26 02:19:05 PM PDT 24
Peak memory 200460 kb
Host smart-a292da41-32b6-44d4-8c1e-c5236a2d4866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553420738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1553420738
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2644852460
Short name T797
Test name
Test status
Simulation time 56960092951 ps
CPU time 27.53 seconds
Started May 26 02:13:55 PM PDT 24
Finished May 26 02:14:23 PM PDT 24
Peak memory 200352 kb
Host smart-be01e5ef-0fce-406d-9626-467836cd3504
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644852460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2644852460
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.469272985
Short name T781
Test name
Test status
Simulation time 102832580775 ps
CPU time 403.18 seconds
Started May 26 02:13:53 PM PDT 24
Finished May 26 02:20:38 PM PDT 24
Peak memory 200512 kb
Host smart-25df96ca-028d-4fc8-b3c5-bf4955e2ab9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469272985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.469272985
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.4223713241
Short name T706
Test name
Test status
Simulation time 8468515474 ps
CPU time 7.56 seconds
Started May 26 02:13:56 PM PDT 24
Finished May 26 02:14:04 PM PDT 24
Peak memory 198936 kb
Host smart-b360fa48-d971-4c55-9d7e-29a1bb13ee90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223713241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.4223713241
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1302457896
Short name T999
Test name
Test status
Simulation time 158174246989 ps
CPU time 75.02 seconds
Started May 26 02:13:51 PM PDT 24
Finished May 26 02:15:07 PM PDT 24
Peak memory 200800 kb
Host smart-7fd1b5e3-53a5-455c-8388-e25a78edbb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302457896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1302457896
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.161370509
Short name T464
Test name
Test status
Simulation time 17094421167 ps
CPU time 261.82 seconds
Started May 26 02:13:53 PM PDT 24
Finished May 26 02:18:17 PM PDT 24
Peak memory 200396 kb
Host smart-1f442a84-1e2b-402c-a7cb-69d51aa82a2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=161370509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.161370509
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1168529128
Short name T11
Test name
Test status
Simulation time 4422623358 ps
CPU time 12.9 seconds
Started May 26 02:13:53 PM PDT 24
Finished May 26 02:14:08 PM PDT 24
Peak memory 200036 kb
Host smart-9d641261-50ed-4662-bcc9-16398229badc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1168529128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1168529128
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.595654968
Short name T278
Test name
Test status
Simulation time 88014658012 ps
CPU time 34.5 seconds
Started May 26 02:13:56 PM PDT 24
Finished May 26 02:14:31 PM PDT 24
Peak memory 200328 kb
Host smart-18ba8bef-18d8-48ae-820e-5c1c80875325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595654968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.595654968
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.873026757
Short name T120
Test name
Test status
Simulation time 3603698849 ps
CPU time 4.95 seconds
Started May 26 02:13:57 PM PDT 24
Finished May 26 02:14:02 PM PDT 24
Peak memory 196540 kb
Host smart-5aa45e09-860e-47eb-b698-12bdde0dd65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873026757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.873026757
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2597714237
Short name T1125
Test name
Test status
Simulation time 11590198445 ps
CPU time 20.91 seconds
Started May 26 02:13:52 PM PDT 24
Finished May 26 02:14:15 PM PDT 24
Peak memory 200448 kb
Host smart-09908374-6811-4919-995b-db861eb3b309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597714237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2597714237
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3507051951
Short name T872
Test name
Test status
Simulation time 38888017868 ps
CPU time 357.54 seconds
Started May 26 02:13:56 PM PDT 24
Finished May 26 02:19:54 PM PDT 24
Peak memory 214304 kb
Host smart-43538ad2-f2a1-4dad-944c-8ffaf35c7b37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507051951 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3507051951
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.4136008046
Short name T465
Test name
Test status
Simulation time 6535205431 ps
CPU time 13.04 seconds
Started May 26 02:13:53 PM PDT 24
Finished May 26 02:14:07 PM PDT 24
Peak memory 200292 kb
Host smart-7e92dda4-1c61-4a3e-898d-91153496785c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136008046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.4136008046
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3196196065
Short name T639
Test name
Test status
Simulation time 30487485323 ps
CPU time 54.12 seconds
Started May 26 02:13:53 PM PDT 24
Finished May 26 02:14:48 PM PDT 24
Peak memory 200568 kb
Host smart-7b7389f5-d8b0-45a4-95d1-8716571b20de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196196065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3196196065
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2628309843
Short name T200
Test name
Test status
Simulation time 77976800116 ps
CPU time 222.95 seconds
Started May 26 02:17:18 PM PDT 24
Finished May 26 02:21:01 PM PDT 24
Peak memory 200452 kb
Host smart-04cd05d6-cd0e-4711-a93f-7d2e8ffa112a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628309843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2628309843
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2379268043
Short name T223
Test name
Test status
Simulation time 7681036368 ps
CPU time 13.79 seconds
Started May 26 02:17:22 PM PDT 24
Finished May 26 02:17:36 PM PDT 24
Peak memory 200268 kb
Host smart-d7a52940-5842-434c-8070-f845e12f8809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379268043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2379268043
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.412347911
Short name T355
Test name
Test status
Simulation time 84788420822 ps
CPU time 78.53 seconds
Started May 26 02:17:19 PM PDT 24
Finished May 26 02:18:39 PM PDT 24
Peak memory 200520 kb
Host smart-86ad9ecf-0989-42ed-b64d-25e294d12b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412347911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.412347911
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2518631903
Short name T334
Test name
Test status
Simulation time 82388681652 ps
CPU time 33.26 seconds
Started May 26 02:17:16 PM PDT 24
Finished May 26 02:17:50 PM PDT 24
Peak memory 200184 kb
Host smart-1637ba7f-04e3-4557-a2f4-4a28b5c4b4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518631903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2518631903
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2544103962
Short name T1101
Test name
Test status
Simulation time 105052405981 ps
CPU time 83.97 seconds
Started May 26 02:17:22 PM PDT 24
Finished May 26 02:18:46 PM PDT 24
Peak memory 200476 kb
Host smart-7c658ff5-49c9-4ccd-8114-b2bd3a1486e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544103962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2544103962
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.566909171
Short name T751
Test name
Test status
Simulation time 57609165520 ps
CPU time 148.71 seconds
Started May 26 02:17:17 PM PDT 24
Finished May 26 02:19:46 PM PDT 24
Peak memory 200548 kb
Host smart-5ac8be11-dd16-4e88-b697-502eb8f5d1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566909171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.566909171
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1631569688
Short name T251
Test name
Test status
Simulation time 103658083421 ps
CPU time 33.35 seconds
Started May 26 02:17:18 PM PDT 24
Finished May 26 02:17:52 PM PDT 24
Peak memory 200512 kb
Host smart-b0c22a01-443f-424b-929a-58a445f35c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631569688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1631569688
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2467493262
Short name T1082
Test name
Test status
Simulation time 42373289307 ps
CPU time 88.05 seconds
Started May 26 02:17:19 PM PDT 24
Finished May 26 02:18:48 PM PDT 24
Peak memory 200544 kb
Host smart-ce545be7-524f-4a79-bde1-266ac09665cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467493262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2467493262
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1747283964
Short name T711
Test name
Test status
Simulation time 42801975577 ps
CPU time 13.97 seconds
Started May 26 02:17:19 PM PDT 24
Finished May 26 02:17:34 PM PDT 24
Peak memory 200536 kb
Host smart-3f36e10d-0370-479a-acfb-caa947c2d973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747283964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1747283964
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3514494704
Short name T629
Test name
Test status
Simulation time 223147163661 ps
CPU time 44.01 seconds
Started May 26 02:17:19 PM PDT 24
Finished May 26 02:18:04 PM PDT 24
Peak memory 200472 kb
Host smart-c2cc988f-5599-4df8-9e45-f8e02137522a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514494704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3514494704
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1267243244
Short name T695
Test name
Test status
Simulation time 14542146 ps
CPU time 0.59 seconds
Started May 26 02:14:05 PM PDT 24
Finished May 26 02:14:06 PM PDT 24
Peak memory 195892 kb
Host smart-70cf2a3b-11f5-4a48-8157-2a17755e1edc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267243244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1267243244
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2963768934
Short name T899
Test name
Test status
Simulation time 57175158650 ps
CPU time 108.28 seconds
Started May 26 02:14:02 PM PDT 24
Finished May 26 02:15:51 PM PDT 24
Peak memory 200468 kb
Host smart-bf0271d0-0c7a-401a-b502-2e0480ca5187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963768934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2963768934
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3947381099
Short name T870
Test name
Test status
Simulation time 238328004171 ps
CPU time 124.44 seconds
Started May 26 02:14:00 PM PDT 24
Finished May 26 02:16:05 PM PDT 24
Peak memory 200320 kb
Host smart-76164208-c150-499e-8ab6-ca5c48018748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947381099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3947381099
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3584352324
Short name T222
Test name
Test status
Simulation time 29837365471 ps
CPU time 46.19 seconds
Started May 26 02:14:00 PM PDT 24
Finished May 26 02:14:47 PM PDT 24
Peak memory 200404 kb
Host smart-d191b0f8-9337-4975-a307-047aedc08a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584352324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3584352324
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3562898229
Short name T24
Test name
Test status
Simulation time 14214884255 ps
CPU time 7.43 seconds
Started May 26 02:13:59 PM PDT 24
Finished May 26 02:14:07 PM PDT 24
Peak memory 198204 kb
Host smart-e6d2d2f5-20c3-414b-8303-a5b2b8c89107
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562898229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3562898229
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.4001455372
Short name T616
Test name
Test status
Simulation time 103318009740 ps
CPU time 283.04 seconds
Started May 26 02:14:00 PM PDT 24
Finished May 26 02:18:43 PM PDT 24
Peak memory 200460 kb
Host smart-2f1ca8c1-8d91-4bd5-84e3-2ae3f40f87ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4001455372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.4001455372
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.485770934
Short name T402
Test name
Test status
Simulation time 11195763509 ps
CPU time 13.82 seconds
Started May 26 02:14:00 PM PDT 24
Finished May 26 02:14:15 PM PDT 24
Peak memory 200444 kb
Host smart-80f8981a-ee4b-4c6b-b1ac-9eeaf3961f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485770934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.485770934
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2833728504
Short name T909
Test name
Test status
Simulation time 61390480885 ps
CPU time 39.01 seconds
Started May 26 02:14:03 PM PDT 24
Finished May 26 02:14:43 PM PDT 24
Peak memory 200028 kb
Host smart-39297f0a-bee7-4000-a876-03be6cc78f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833728504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2833728504
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1017002299
Short name T771
Test name
Test status
Simulation time 6820524725 ps
CPU time 89.15 seconds
Started May 26 02:14:01 PM PDT 24
Finished May 26 02:15:31 PM PDT 24
Peak memory 200480 kb
Host smart-030545b5-cd37-4678-aadc-a8e5d31f1f1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1017002299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1017002299
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3012689407
Short name T379
Test name
Test status
Simulation time 6598920427 ps
CPU time 16.96 seconds
Started May 26 02:13:59 PM PDT 24
Finished May 26 02:14:17 PM PDT 24
Peak memory 199752 kb
Host smart-178a69a1-e50e-42c4-b2c8-9656cab01a7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3012689407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3012689407
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1348617421
Short name T177
Test name
Test status
Simulation time 85910067788 ps
CPU time 41.91 seconds
Started May 26 02:13:59 PM PDT 24
Finished May 26 02:14:42 PM PDT 24
Peak memory 200480 kb
Host smart-0ef97243-5014-44e9-ae84-30ea2ca1408e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348617421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1348617421
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1214118293
Short name T297
Test name
Test status
Simulation time 3269813906 ps
CPU time 3.5 seconds
Started May 26 02:14:01 PM PDT 24
Finished May 26 02:14:06 PM PDT 24
Peak memory 196560 kb
Host smart-d2c2ea66-5489-43b5-9b67-115e9491abaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214118293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1214118293
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2791232327
Short name T715
Test name
Test status
Simulation time 5384548639 ps
CPU time 16.95 seconds
Started May 26 02:14:02 PM PDT 24
Finished May 26 02:14:20 PM PDT 24
Peak memory 200432 kb
Host smart-821edc2e-5112-4bc0-b124-b0b22a376364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791232327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2791232327
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2212202256
Short name T37
Test name
Test status
Simulation time 15777196281 ps
CPU time 167.92 seconds
Started May 26 02:14:02 PM PDT 24
Finished May 26 02:16:51 PM PDT 24
Peak memory 216472 kb
Host smart-2983e127-b2b7-4dbb-af53-613995e9b864
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212202256 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2212202256
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2868337491
Short name T531
Test name
Test status
Simulation time 6960376857 ps
CPU time 18.08 seconds
Started May 26 02:14:01 PM PDT 24
Finished May 26 02:14:20 PM PDT 24
Peak memory 200508 kb
Host smart-f9ab770b-ff17-4771-b348-13c85171a944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868337491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2868337491
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2538746992
Short name T831
Test name
Test status
Simulation time 32926181532 ps
CPU time 17.86 seconds
Started May 26 02:14:04 PM PDT 24
Finished May 26 02:14:23 PM PDT 24
Peak memory 200524 kb
Host smart-c20bf978-8821-4e6c-81f8-ba0ebe7ce6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538746992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2538746992
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1164917963
Short name T1099
Test name
Test status
Simulation time 155528523060 ps
CPU time 245.95 seconds
Started May 26 02:17:18 PM PDT 24
Finished May 26 02:21:25 PM PDT 24
Peak memory 200468 kb
Host smart-f3cc93b5-833a-4115-817f-527a9283e4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164917963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1164917963
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2753057022
Short name T619
Test name
Test status
Simulation time 129437199701 ps
CPU time 203.67 seconds
Started May 26 02:17:22 PM PDT 24
Finished May 26 02:20:46 PM PDT 24
Peak memory 200476 kb
Host smart-cf0b1c63-480f-4ff2-ad18-856db0277ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753057022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2753057022
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3734509560
Short name T358
Test name
Test status
Simulation time 116196739553 ps
CPU time 59.54 seconds
Started May 26 02:17:25 PM PDT 24
Finished May 26 02:18:26 PM PDT 24
Peak memory 200476 kb
Host smart-3780af3d-9516-4b95-b48a-d097ca31e491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734509560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3734509560
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1788217529
Short name T575
Test name
Test status
Simulation time 11631139980 ps
CPU time 18.89 seconds
Started May 26 02:17:27 PM PDT 24
Finished May 26 02:17:46 PM PDT 24
Peak memory 200532 kb
Host smart-db491151-bf90-42be-80c4-e22505eef530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788217529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1788217529
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3503296570
Short name T213
Test name
Test status
Simulation time 15453878423 ps
CPU time 32.04 seconds
Started May 26 02:17:26 PM PDT 24
Finished May 26 02:17:59 PM PDT 24
Peak memory 200520 kb
Host smart-74fa7cf9-b166-4155-8492-3592ff9b96f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503296570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3503296570
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.4128781495
Short name T569
Test name
Test status
Simulation time 469598911245 ps
CPU time 130.3 seconds
Started May 26 02:17:26 PM PDT 24
Finished May 26 02:19:37 PM PDT 24
Peak memory 200488 kb
Host smart-9be088f6-cf31-424b-bad5-f8d43203222d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128781495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.4128781495
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2141180430
Short name T306
Test name
Test status
Simulation time 118295382790 ps
CPU time 95.37 seconds
Started May 26 02:17:24 PM PDT 24
Finished May 26 02:19:00 PM PDT 24
Peak memory 200472 kb
Host smart-161175c3-9c81-4ce9-a662-fb608fcd5104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141180430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2141180430
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.690016631
Short name T343
Test name
Test status
Simulation time 28158875929 ps
CPU time 51.12 seconds
Started May 26 02:17:26 PM PDT 24
Finished May 26 02:18:18 PM PDT 24
Peak memory 200440 kb
Host smart-1846e02a-3a8e-4772-b66e-f73de41a7e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690016631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.690016631
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.4036356235
Short name T848
Test name
Test status
Simulation time 49277954 ps
CPU time 0.57 seconds
Started May 26 02:14:11 PM PDT 24
Finished May 26 02:14:12 PM PDT 24
Peak memory 195924 kb
Host smart-9938c5ca-246d-4a12-a33c-9e471e065b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036356235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4036356235
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1767830636
Short name T375
Test name
Test status
Simulation time 88437562967 ps
CPU time 35 seconds
Started May 26 02:14:03 PM PDT 24
Finished May 26 02:14:38 PM PDT 24
Peak memory 200632 kb
Host smart-4a483b31-1913-4370-b12b-31efaf605937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767830636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1767830636
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1535900348
Short name T677
Test name
Test status
Simulation time 237985948822 ps
CPU time 156.36 seconds
Started May 26 02:14:00 PM PDT 24
Finished May 26 02:16:37 PM PDT 24
Peak memory 200512 kb
Host smart-882e7916-b76c-475d-936f-4d27edc85c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535900348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1535900348
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_intr.3335596777
Short name T1005
Test name
Test status
Simulation time 30646647708 ps
CPU time 19.82 seconds
Started May 26 02:14:01 PM PDT 24
Finished May 26 02:14:22 PM PDT 24
Peak memory 200468 kb
Host smart-7da1a279-0d1e-4d59-91be-f0e14907a050
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335596777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3335596777
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3838787820
Short name T390
Test name
Test status
Simulation time 77503280847 ps
CPU time 388.39 seconds
Started May 26 02:14:08 PM PDT 24
Finished May 26 02:20:37 PM PDT 24
Peak memory 200524 kb
Host smart-3528547e-2711-4a88-9681-d4fa9de3c358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3838787820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3838787820
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2194361058
Short name T864
Test name
Test status
Simulation time 2632272543 ps
CPU time 2.35 seconds
Started May 26 02:14:02 PM PDT 24
Finished May 26 02:14:05 PM PDT 24
Peak memory 199428 kb
Host smart-9c0f0d0c-eed4-4d16-aa69-e80e4e54a1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194361058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2194361058
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3873094700
Short name T1086
Test name
Test status
Simulation time 17730030196 ps
CPU time 28.41 seconds
Started May 26 02:14:02 PM PDT 24
Finished May 26 02:14:32 PM PDT 24
Peak memory 199772 kb
Host smart-066ef384-775e-49f8-9f7f-31b05e3e0bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873094700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3873094700
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2886930113
Short name T746
Test name
Test status
Simulation time 19196221272 ps
CPU time 865.76 seconds
Started May 26 02:14:03 PM PDT 24
Finished May 26 02:28:29 PM PDT 24
Peak memory 200556 kb
Host smart-53cf7541-deae-4670-8572-ea45cbc34924
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886930113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2886930113
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2188032891
Short name T878
Test name
Test status
Simulation time 1269970393 ps
CPU time 2.9 seconds
Started May 26 02:14:06 PM PDT 24
Finished May 26 02:14:09 PM PDT 24
Peak memory 198324 kb
Host smart-90116a57-d8b1-426b-b135-2493ee3d6390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2188032891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2188032891
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2481387086
Short name T960
Test name
Test status
Simulation time 24196221026 ps
CPU time 41.64 seconds
Started May 26 02:14:03 PM PDT 24
Finished May 26 02:14:45 PM PDT 24
Peak memory 200628 kb
Host smart-3d6dfde4-80c4-45c3-a553-a0a52a54058f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481387086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2481387086
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3529253320
Short name T660
Test name
Test status
Simulation time 35252809096 ps
CPU time 49.82 seconds
Started May 26 02:14:01 PM PDT 24
Finished May 26 02:14:52 PM PDT 24
Peak memory 196504 kb
Host smart-30814f1f-4c35-4d83-b64a-f1ebeb57585a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529253320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3529253320
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1181378074
Short name T743
Test name
Test status
Simulation time 917632881 ps
CPU time 1.97 seconds
Started May 26 02:14:01 PM PDT 24
Finished May 26 02:14:04 PM PDT 24
Peak memory 199716 kb
Host smart-da71144f-cde0-4df0-bbea-813dcd67eddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181378074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1181378074
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3069794590
Short name T1076
Test name
Test status
Simulation time 30476216121 ps
CPU time 1152.88 seconds
Started May 26 02:14:09 PM PDT 24
Finished May 26 02:33:22 PM PDT 24
Peak memory 200484 kb
Host smart-f3b8774d-984f-4d6c-9061-681434dc9b84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069794590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3069794590
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3349548161
Short name T1122
Test name
Test status
Simulation time 97662594900 ps
CPU time 395 seconds
Started May 26 02:14:08 PM PDT 24
Finished May 26 02:20:43 PM PDT 24
Peak memory 216840 kb
Host smart-c7f60e10-a3b4-4d4a-b820-4c70b4a93b22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349548161 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3349548161
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1136541295
Short name T945
Test name
Test status
Simulation time 2736600587 ps
CPU time 2.46 seconds
Started May 26 02:14:02 PM PDT 24
Finished May 26 02:14:05 PM PDT 24
Peak memory 199124 kb
Host smart-46e58cfc-8ea2-4178-ba5e-95d4a34ef5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136541295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1136541295
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3615526595
Short name T524
Test name
Test status
Simulation time 27728554349 ps
CPU time 49.65 seconds
Started May 26 02:14:03 PM PDT 24
Finished May 26 02:14:53 PM PDT 24
Peak memory 200500 kb
Host smart-59a0d88a-5f34-4284-82a5-29302209b50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615526595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3615526595
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3764246874
Short name T1083
Test name
Test status
Simulation time 77635437805 ps
CPU time 69.49 seconds
Started May 26 02:17:25 PM PDT 24
Finished May 26 02:18:35 PM PDT 24
Peak memory 200432 kb
Host smart-f8a18e30-b6d1-42b5-9faf-a24c60603a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764246874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3764246874
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3423078049
Short name T468
Test name
Test status
Simulation time 13228448283 ps
CPU time 10.51 seconds
Started May 26 02:17:26 PM PDT 24
Finished May 26 02:17:37 PM PDT 24
Peak memory 200536 kb
Host smart-aff6c210-d2f4-4342-885c-518c9f69d91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423078049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3423078049
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1331506072
Short name T1180
Test name
Test status
Simulation time 39630235718 ps
CPU time 18.87 seconds
Started May 26 02:17:25 PM PDT 24
Finished May 26 02:17:45 PM PDT 24
Peak memory 200284 kb
Host smart-29934563-46be-4268-9021-2ff91890837b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331506072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1331506072
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1876882339
Short name T1149
Test name
Test status
Simulation time 122540842262 ps
CPU time 269.08 seconds
Started May 26 02:17:26 PM PDT 24
Finished May 26 02:21:56 PM PDT 24
Peak memory 200472 kb
Host smart-48263e61-bda3-4ece-9b7a-4ef2d47323f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876882339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1876882339
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1470377457
Short name T199
Test name
Test status
Simulation time 153131401095 ps
CPU time 106.07 seconds
Started May 26 02:17:25 PM PDT 24
Finished May 26 02:19:12 PM PDT 24
Peak memory 200456 kb
Host smart-7c2711a6-1795-4287-994d-379c6afc0625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470377457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1470377457
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.668704127
Short name T922
Test name
Test status
Simulation time 68838693030 ps
CPU time 19.31 seconds
Started May 26 02:17:27 PM PDT 24
Finished May 26 02:17:47 PM PDT 24
Peak memory 200552 kb
Host smart-513c86e3-a020-493f-a1f5-694692d5336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668704127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.668704127
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1256865906
Short name T1052
Test name
Test status
Simulation time 14828265073 ps
CPU time 25.01 seconds
Started May 26 02:17:26 PM PDT 24
Finished May 26 02:17:51 PM PDT 24
Peak memory 200296 kb
Host smart-c4e589f8-2ccf-49a6-9d49-95c338c06dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256865906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1256865906
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.430975749
Short name T625
Test name
Test status
Simulation time 99745044804 ps
CPU time 166.79 seconds
Started May 26 02:17:25 PM PDT 24
Finished May 26 02:20:13 PM PDT 24
Peak memory 200512 kb
Host smart-fa82abff-50b1-4caa-868f-b81437cc6208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430975749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.430975749
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2607868863
Short name T1117
Test name
Test status
Simulation time 39922198331 ps
CPU time 20.44 seconds
Started May 26 02:17:25 PM PDT 24
Finished May 26 02:17:46 PM PDT 24
Peak memory 200524 kb
Host smart-09c02eaf-2e65-4f38-b155-9765c6fd8322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607868863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2607868863
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2783061037
Short name T1167
Test name
Test status
Simulation time 124173225 ps
CPU time 0.59 seconds
Started May 26 02:14:11 PM PDT 24
Finished May 26 02:14:13 PM PDT 24
Peak memory 195896 kb
Host smart-8c1999aa-6a85-49ec-9fcd-a6537bfee3cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783061037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2783061037
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3853251114
Short name T912
Test name
Test status
Simulation time 41972172816 ps
CPU time 17.45 seconds
Started May 26 02:14:11 PM PDT 24
Finished May 26 02:14:30 PM PDT 24
Peak memory 200540 kb
Host smart-a800b3b1-856f-4b25-9623-c0b1bbf9e647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853251114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3853251114
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2906054911
Short name T835
Test name
Test status
Simulation time 12574619508 ps
CPU time 11.54 seconds
Started May 26 02:14:08 PM PDT 24
Finished May 26 02:14:20 PM PDT 24
Peak memory 199908 kb
Host smart-ac3826cc-4766-48e9-91b0-e8f1190d60d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906054911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2906054911
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3115680535
Short name T1100
Test name
Test status
Simulation time 91985177882 ps
CPU time 133.59 seconds
Started May 26 02:14:09 PM PDT 24
Finished May 26 02:16:23 PM PDT 24
Peak memory 200484 kb
Host smart-72aa37ff-891e-42c2-bd35-a6a17af60751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115680535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3115680535
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1587440070
Short name T380
Test name
Test status
Simulation time 6190432984 ps
CPU time 3.64 seconds
Started May 26 02:14:10 PM PDT 24
Finished May 26 02:14:15 PM PDT 24
Peak memory 197184 kb
Host smart-173685db-2d73-45ba-8374-e103ca03c35c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587440070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1587440070
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2506239739
Short name T828
Test name
Test status
Simulation time 123746099166 ps
CPU time 295.91 seconds
Started May 26 02:14:10 PM PDT 24
Finished May 26 02:19:06 PM PDT 24
Peak memory 200556 kb
Host smart-c5bd5653-c5e2-41c3-b216-3cd942115f1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2506239739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2506239739
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3925800843
Short name T948
Test name
Test status
Simulation time 1315846831 ps
CPU time 1.62 seconds
Started May 26 02:14:08 PM PDT 24
Finished May 26 02:14:11 PM PDT 24
Peak memory 195964 kb
Host smart-d1245eef-7f23-4b87-8956-2857d7cbbf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925800843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3925800843
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1836422203
Short name T716
Test name
Test status
Simulation time 30142510786 ps
CPU time 14.53 seconds
Started May 26 02:14:09 PM PDT 24
Finished May 26 02:14:24 PM PDT 24
Peak memory 197628 kb
Host smart-1b5ad41e-6a22-4874-8f82-2d79c837f8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836422203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1836422203
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2363531496
Short name T426
Test name
Test status
Simulation time 23999393568 ps
CPU time 325.25 seconds
Started May 26 02:14:10 PM PDT 24
Finished May 26 02:19:36 PM PDT 24
Peak memory 200464 kb
Host smart-0f19a272-9fce-4eab-a93c-ed5e49e06424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2363531496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2363531496
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1884970149
Short name T1006
Test name
Test status
Simulation time 7072137136 ps
CPU time 15.42 seconds
Started May 26 02:14:08 PM PDT 24
Finished May 26 02:14:24 PM PDT 24
Peak memory 198648 kb
Host smart-0e445a86-ae8b-44f2-bde6-61c80512bcb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1884970149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1884970149
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2704492059
Short name T455
Test name
Test status
Simulation time 19546886132 ps
CPU time 46.57 seconds
Started May 26 02:14:10 PM PDT 24
Finished May 26 02:14:57 PM PDT 24
Peak memory 200460 kb
Host smart-8d5bd304-13b8-483b-8f5e-29ae37072070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704492059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2704492059
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2539443079
Short name T368
Test name
Test status
Simulation time 3357694133 ps
CPU time 5.7 seconds
Started May 26 02:14:11 PM PDT 24
Finished May 26 02:14:18 PM PDT 24
Peak memory 196316 kb
Host smart-12856354-5e79-4cde-ac21-64c04d62f21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539443079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2539443079
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2102937614
Short name T1163
Test name
Test status
Simulation time 752990056 ps
CPU time 1.17 seconds
Started May 26 02:14:11 PM PDT 24
Finished May 26 02:14:13 PM PDT 24
Peak memory 198992 kb
Host smart-8c7581e7-ee93-4a1b-8e9c-a0c0390b4ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102937614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2102937614
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.378614974
Short name T550
Test name
Test status
Simulation time 135141123320 ps
CPU time 76.77 seconds
Started May 26 02:14:07 PM PDT 24
Finished May 26 02:15:24 PM PDT 24
Peak memory 216160 kb
Host smart-f96ab8a3-9ac5-4cda-9ed6-00a0baa0701c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378614974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.378614974
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1878725137
Short name T182
Test name
Test status
Simulation time 153845794859 ps
CPU time 861.2 seconds
Started May 26 02:14:08 PM PDT 24
Finished May 26 02:28:30 PM PDT 24
Peak memory 227412 kb
Host smart-e40c6c90-0681-4ed5-bf91-db2fd27308f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878725137 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1878725137
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2233857672
Short name T730
Test name
Test status
Simulation time 1046646652 ps
CPU time 3.26 seconds
Started May 26 02:14:08 PM PDT 24
Finished May 26 02:14:11 PM PDT 24
Peak memory 200420 kb
Host smart-3398da37-c5fb-420b-b064-7080c33f78b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233857672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2233857672
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.4057081658
Short name T690
Test name
Test status
Simulation time 33929923838 ps
CPU time 63.61 seconds
Started May 26 02:14:09 PM PDT 24
Finished May 26 02:15:13 PM PDT 24
Peak memory 200488 kb
Host smart-3c379d9f-31a4-4f30-ba20-d4ee39c5852b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057081658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.4057081658
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3431043280
Short name T240
Test name
Test status
Simulation time 13444345185 ps
CPU time 6.55 seconds
Started May 26 02:17:33 PM PDT 24
Finished May 26 02:17:40 PM PDT 24
Peak memory 200272 kb
Host smart-d9cd9946-c7b1-4664-8034-808b0fafc8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431043280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3431043280
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2890108532
Short name T1127
Test name
Test status
Simulation time 110976742307 ps
CPU time 25.23 seconds
Started May 26 02:17:35 PM PDT 24
Finished May 26 02:18:00 PM PDT 24
Peak memory 200528 kb
Host smart-7877aaa0-176b-4ce4-a3fd-337cfd46e351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890108532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2890108532
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3952286885
Short name T997
Test name
Test status
Simulation time 149613793282 ps
CPU time 16.53 seconds
Started May 26 02:17:34 PM PDT 24
Finished May 26 02:17:51 PM PDT 24
Peak memory 200592 kb
Host smart-3515ac83-e251-4844-adad-1de7810dac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952286885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3952286885
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1379564145
Short name T644
Test name
Test status
Simulation time 166295643055 ps
CPU time 296.02 seconds
Started May 26 02:17:34 PM PDT 24
Finished May 26 02:22:31 PM PDT 24
Peak memory 200448 kb
Host smart-b7f119f2-8624-410a-9465-80ff555c257e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379564145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1379564145
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3144697175
Short name T646
Test name
Test status
Simulation time 125222131649 ps
CPU time 53.82 seconds
Started May 26 02:17:31 PM PDT 24
Finished May 26 02:18:26 PM PDT 24
Peak memory 200504 kb
Host smart-5a15082c-e06e-4b46-b92d-b68448664d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144697175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3144697175
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3053790958
Short name T221
Test name
Test status
Simulation time 87766979869 ps
CPU time 149.39 seconds
Started May 26 02:17:33 PM PDT 24
Finished May 26 02:20:03 PM PDT 24
Peak memory 200524 kb
Host smart-6a7e9374-9377-4c5c-9955-b37c01382496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053790958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3053790958
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.665009230
Short name T198
Test name
Test status
Simulation time 188446367152 ps
CPU time 91.73 seconds
Started May 26 02:17:33 PM PDT 24
Finished May 26 02:19:05 PM PDT 24
Peak memory 200448 kb
Host smart-ae0b0513-a8b2-4c41-875e-1e3879a4af11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665009230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.665009230
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2412152650
Short name T516
Test name
Test status
Simulation time 109156280262 ps
CPU time 18.78 seconds
Started May 26 02:17:34 PM PDT 24
Finished May 26 02:17:54 PM PDT 24
Peak memory 200564 kb
Host smart-8b5bacd0-81ca-4c69-b899-762d1fdb9f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412152650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2412152650
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1416795804
Short name T703
Test name
Test status
Simulation time 93383776814 ps
CPU time 83.64 seconds
Started May 26 02:17:32 PM PDT 24
Finished May 26 02:18:57 PM PDT 24
Peak memory 200568 kb
Host smart-5037d4ea-380e-402b-b034-30468df16065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416795804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1416795804
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2921872165
Short name T1038
Test name
Test status
Simulation time 115252101 ps
CPU time 0.55 seconds
Started May 26 02:14:16 PM PDT 24
Finished May 26 02:14:17 PM PDT 24
Peak memory 195920 kb
Host smart-a3e12c8f-beaa-498d-8b97-a51823ee8ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921872165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2921872165
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2755214084
Short name T529
Test name
Test status
Simulation time 328441372469 ps
CPU time 627.72 seconds
Started May 26 02:14:10 PM PDT 24
Finished May 26 02:24:38 PM PDT 24
Peak memory 200408 kb
Host smart-723ff924-83a6-4f09-8598-167689681fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755214084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2755214084
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3785939659
Short name T938
Test name
Test status
Simulation time 22095622753 ps
CPU time 45.02 seconds
Started May 26 02:14:10 PM PDT 24
Finished May 26 02:14:55 PM PDT 24
Peak memory 200668 kb
Host smart-eda6c477-5082-4311-8eb5-293139414823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785939659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3785939659
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2048375484
Short name T227
Test name
Test status
Simulation time 66564363086 ps
CPU time 27.37 seconds
Started May 26 02:14:11 PM PDT 24
Finished May 26 02:14:40 PM PDT 24
Peak memory 200456 kb
Host smart-4c9095f5-f9c5-4cb8-adee-d917a6d4b2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048375484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2048375484
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2732571284
Short name T679
Test name
Test status
Simulation time 17725833884 ps
CPU time 6.97 seconds
Started May 26 02:14:10 PM PDT 24
Finished May 26 02:14:18 PM PDT 24
Peak memory 200052 kb
Host smart-67d0abb9-0e12-43b7-b0e2-55f57fa3f32e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732571284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2732571284
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.731403977
Short name T275
Test name
Test status
Simulation time 188666896510 ps
CPU time 1199.01 seconds
Started May 26 02:14:14 PM PDT 24
Finished May 26 02:34:14 PM PDT 24
Peak memory 200436 kb
Host smart-5ca6b091-8c3a-4059-b100-d3abf8a46085
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=731403977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.731403977
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2338994792
Short name T394
Test name
Test status
Simulation time 10146428108 ps
CPU time 27.03 seconds
Started May 26 02:14:14 PM PDT 24
Finished May 26 02:14:41 PM PDT 24
Peak memory 200356 kb
Host smart-937bc7fb-0e33-4da8-8bd4-89f5b266d40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338994792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2338994792
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2610556528
Short name T867
Test name
Test status
Simulation time 17055065931 ps
CPU time 32.25 seconds
Started May 26 02:14:14 PM PDT 24
Finished May 26 02:14:47 PM PDT 24
Peak memory 200740 kb
Host smart-ef087a3a-9bd7-4ed2-a432-2722f9fb7d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610556528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2610556528
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3922285909
Short name T844
Test name
Test status
Simulation time 9184863319 ps
CPU time 131.96 seconds
Started May 26 02:14:14 PM PDT 24
Finished May 26 02:16:27 PM PDT 24
Peak memory 200444 kb
Host smart-5f659295-e7aa-4b33-ae01-7fa2bda1fb49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922285909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3922285909
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3490813236
Short name T684
Test name
Test status
Simulation time 3556111211 ps
CPU time 24.67 seconds
Started May 26 02:14:09 PM PDT 24
Finished May 26 02:14:34 PM PDT 24
Peak memory 199468 kb
Host smart-96d86d4c-7d93-493b-8d62-2947de792b7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3490813236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3490813236
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.309338730
Short name T485
Test name
Test status
Simulation time 136008440290 ps
CPU time 65.34 seconds
Started May 26 02:14:15 PM PDT 24
Finished May 26 02:15:21 PM PDT 24
Peak memory 200576 kb
Host smart-ef106f2f-4b45-4705-a340-f4cfda36f6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309338730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.309338730
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3067068849
Short name T602
Test name
Test status
Simulation time 4212188731 ps
CPU time 2.25 seconds
Started May 26 02:14:16 PM PDT 24
Finished May 26 02:14:19 PM PDT 24
Peak memory 196820 kb
Host smart-27f98286-f84a-476c-872c-d678dd7b4ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067068849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3067068849
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.853344990
Short name T431
Test name
Test status
Simulation time 5685028145 ps
CPU time 20.07 seconds
Started May 26 02:14:11 PM PDT 24
Finished May 26 02:14:31 PM PDT 24
Peak memory 200344 kb
Host smart-c4432066-c2e7-4722-bbb2-152f22c099bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853344990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.853344990
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2268020761
Short name T981
Test name
Test status
Simulation time 263770740414 ps
CPU time 101.79 seconds
Started May 26 02:14:16 PM PDT 24
Finished May 26 02:15:59 PM PDT 24
Peak memory 200532 kb
Host smart-6dbc3297-b9d0-4f24-bd20-223d3fa234c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268020761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2268020761
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2785571564
Short name T783
Test name
Test status
Simulation time 196153064984 ps
CPU time 235.75 seconds
Started May 26 02:14:16 PM PDT 24
Finished May 26 02:18:12 PM PDT 24
Peak memory 217036 kb
Host smart-023deb33-581b-452d-8fbe-536fcb8af10b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785571564 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2785571564
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3892207582
Short name T542
Test name
Test status
Simulation time 6911594491 ps
CPU time 19.66 seconds
Started May 26 02:14:16 PM PDT 24
Finished May 26 02:14:37 PM PDT 24
Peak memory 200340 kb
Host smart-fd004181-adfe-42ae-856e-418664dbd1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892207582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3892207582
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1821169699
Short name T1098
Test name
Test status
Simulation time 36456287389 ps
CPU time 7.07 seconds
Started May 26 02:14:09 PM PDT 24
Finished May 26 02:14:16 PM PDT 24
Peak memory 200296 kb
Host smart-30c290cb-d886-4608-b979-975e95cbe605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821169699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1821169699
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3430571267
Short name T296
Test name
Test status
Simulation time 66899101992 ps
CPU time 111.87 seconds
Started May 26 02:17:34 PM PDT 24
Finished May 26 02:19:26 PM PDT 24
Peak memory 200512 kb
Host smart-d05fe63a-6d03-4e2d-b447-7745d1c8e24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430571267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3430571267
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2092887560
Short name T472
Test name
Test status
Simulation time 54167588804 ps
CPU time 141.09 seconds
Started May 26 02:17:33 PM PDT 24
Finished May 26 02:19:54 PM PDT 24
Peak memory 200540 kb
Host smart-8792899c-66e0-4cd3-b0cd-e33ae08c6b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092887560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2092887560
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2207892165
Short name T604
Test name
Test status
Simulation time 48510148088 ps
CPU time 77.89 seconds
Started May 26 02:17:32 PM PDT 24
Finished May 26 02:18:50 PM PDT 24
Peak memory 200132 kb
Host smart-7f821f32-77df-4fa7-91d0-b1b08f23245f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207892165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2207892165
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2227371982
Short name T705
Test name
Test status
Simulation time 20051678041 ps
CPU time 53.66 seconds
Started May 26 02:17:33 PM PDT 24
Finished May 26 02:18:27 PM PDT 24
Peak memory 200484 kb
Host smart-16217434-03e1-4993-9e9d-b0b9e6c6ca83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227371982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2227371982
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3524059102
Short name T573
Test name
Test status
Simulation time 84585572451 ps
CPU time 30.51 seconds
Started May 26 02:17:33 PM PDT 24
Finished May 26 02:18:04 PM PDT 24
Peak memory 200472 kb
Host smart-51ad8856-2f78-45e9-94bc-cb1adf507445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524059102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3524059102
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.20675031
Short name T172
Test name
Test status
Simulation time 101543610506 ps
CPU time 82.71 seconds
Started May 26 02:17:32 PM PDT 24
Finished May 26 02:18:55 PM PDT 24
Peak memory 200480 kb
Host smart-85977d55-a59f-45a3-80be-29f062e2ef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20675031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.20675031
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3566664870
Short name T105
Test name
Test status
Simulation time 29293705754 ps
CPU time 45.66 seconds
Started May 26 02:17:33 PM PDT 24
Finished May 26 02:18:19 PM PDT 24
Peak memory 200384 kb
Host smart-53f745a0-9bc0-4c3a-9064-c11ed5e8302b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566664870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3566664870
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.4021735113
Short name T782
Test name
Test status
Simulation time 69142463478 ps
CPU time 31.24 seconds
Started May 26 02:17:34 PM PDT 24
Finished May 26 02:18:06 PM PDT 24
Peak memory 200412 kb
Host smart-299bf24e-f8df-4b25-8ac3-465fcbc516cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021735113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.4021735113
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3381029207
Short name T790
Test name
Test status
Simulation time 54930680523 ps
CPU time 20.71 seconds
Started May 26 02:17:34 PM PDT 24
Finished May 26 02:17:55 PM PDT 24
Peak memory 200352 kb
Host smart-b9e6d3c7-1daa-427a-b466-85eeb1d5735f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381029207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3381029207
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.269760195
Short name T824
Test name
Test status
Simulation time 14988021 ps
CPU time 0.57 seconds
Started May 26 02:14:23 PM PDT 24
Finished May 26 02:14:24 PM PDT 24
Peak memory 195832 kb
Host smart-d7b20a25-f8d5-4343-9739-6388634223f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269760195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.269760195
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1900080602
Short name T1178
Test name
Test status
Simulation time 77389048586 ps
CPU time 137.44 seconds
Started May 26 02:14:15 PM PDT 24
Finished May 26 02:16:33 PM PDT 24
Peak memory 200436 kb
Host smart-3b43c981-b61f-41e4-9cef-fce1908c89d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900080602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1900080602
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2780892724
Short name T409
Test name
Test status
Simulation time 29885914137 ps
CPU time 50.25 seconds
Started May 26 02:14:19 PM PDT 24
Finished May 26 02:15:10 PM PDT 24
Peak memory 200548 kb
Host smart-8c95d929-2546-4bbb-b994-745f1784cf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780892724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2780892724
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3452756938
Short name T595
Test name
Test status
Simulation time 33669751797 ps
CPU time 18.73 seconds
Started May 26 02:14:16 PM PDT 24
Finished May 26 02:14:36 PM PDT 24
Peak memory 200440 kb
Host smart-9f587d36-a801-4c6c-b240-0011e2154cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452756938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3452756938
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2036004253
Short name T1153
Test name
Test status
Simulation time 78839176240 ps
CPU time 57.31 seconds
Started May 26 02:14:16 PM PDT 24
Finished May 26 02:15:14 PM PDT 24
Peak memory 200468 kb
Host smart-97696ace-98c3-431a-950c-cb1722f1daef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036004253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2036004253
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2055335355
Short name T697
Test name
Test status
Simulation time 91942490488 ps
CPU time 768.42 seconds
Started May 26 02:14:16 PM PDT 24
Finished May 26 02:27:06 PM PDT 24
Peak memory 200520 kb
Host smart-77223279-fb09-46b8-a6fa-3c0a332b3cf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055335355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2055335355
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2321384458
Short name T774
Test name
Test status
Simulation time 6961196553 ps
CPU time 8.18 seconds
Started May 26 02:14:16 PM PDT 24
Finished May 26 02:14:25 PM PDT 24
Peak memory 200524 kb
Host smart-75f38785-f7f9-4ad3-842f-3f346810f252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321384458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2321384458
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1175926193
Short name T513
Test name
Test status
Simulation time 45273458795 ps
CPU time 65.39 seconds
Started May 26 02:14:14 PM PDT 24
Finished May 26 02:15:20 PM PDT 24
Peak memory 208484 kb
Host smart-211d1f55-01b0-470f-8280-2e813b7d810f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175926193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1175926193
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.641502684
Short name T259
Test name
Test status
Simulation time 24948943714 ps
CPU time 349.76 seconds
Started May 26 02:14:16 PM PDT 24
Finished May 26 02:20:06 PM PDT 24
Peak memory 200556 kb
Host smart-c818720c-c8ef-46f3-8976-2962f48975a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641502684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.641502684
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.930600148
Short name T680
Test name
Test status
Simulation time 2011792890 ps
CPU time 8.92 seconds
Started May 26 02:14:16 PM PDT 24
Finished May 26 02:14:26 PM PDT 24
Peak memory 198640 kb
Host smart-436ba4db-1f9e-4d9a-85c6-021d64770418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=930600148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.930600148
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1453419824
Short name T850
Test name
Test status
Simulation time 84207222687 ps
CPU time 36.15 seconds
Started May 26 02:14:17 PM PDT 24
Finished May 26 02:14:54 PM PDT 24
Peak memory 200496 kb
Host smart-43407e11-20f6-4fd2-8821-52ec4f8fc79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453419824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1453419824
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.4177895070
Short name T437
Test name
Test status
Simulation time 5619112121 ps
CPU time 2.81 seconds
Started May 26 02:14:19 PM PDT 24
Finished May 26 02:14:23 PM PDT 24
Peak memory 196532 kb
Host smart-c0429ec1-29e7-41e0-b2e9-7d7903849ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177895070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.4177895070
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2467642651
Short name T846
Test name
Test status
Simulation time 507643451 ps
CPU time 1.18 seconds
Started May 26 02:14:17 PM PDT 24
Finished May 26 02:14:19 PM PDT 24
Peak memory 198724 kb
Host smart-12c56950-a7ba-486a-aa84-fabba26339c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467642651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2467642651
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3202871701
Short name T683
Test name
Test status
Simulation time 168422821466 ps
CPU time 375.07 seconds
Started May 26 02:14:19 PM PDT 24
Finished May 26 02:20:34 PM PDT 24
Peak memory 216948 kb
Host smart-34992089-1bce-4b1d-a9b0-686ec0b64d7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202871701 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3202871701
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.407999681
Short name T907
Test name
Test status
Simulation time 6815740688 ps
CPU time 14.85 seconds
Started May 26 02:14:15 PM PDT 24
Finished May 26 02:14:31 PM PDT 24
Peak memory 200460 kb
Host smart-6d1d8038-8cf8-414d-8500-2b19405fb2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407999681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.407999681
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2080814603
Short name T319
Test name
Test status
Simulation time 80068862204 ps
CPU time 126.02 seconds
Started May 26 02:14:14 PM PDT 24
Finished May 26 02:16:21 PM PDT 24
Peak memory 200548 kb
Host smart-45bc215e-66b7-4d80-9270-f4080129c7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080814603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2080814603
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2504641364
Short name T1010
Test name
Test status
Simulation time 70671492368 ps
CPU time 220.42 seconds
Started May 26 02:17:34 PM PDT 24
Finished May 26 02:21:15 PM PDT 24
Peak memory 200484 kb
Host smart-b804da61-04dc-4486-b157-e4d5d109d661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504641364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2504641364
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1804691563
Short name T964
Test name
Test status
Simulation time 109429987064 ps
CPU time 51.68 seconds
Started May 26 02:17:32 PM PDT 24
Finished May 26 02:18:24 PM PDT 24
Peak memory 200564 kb
Host smart-a6323b61-5987-4a26-9c60-9aef3c7cf576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804691563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1804691563
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3242893595
Short name T770
Test name
Test status
Simulation time 10641848963 ps
CPU time 8.98 seconds
Started May 26 02:17:31 PM PDT 24
Finished May 26 02:17:41 PM PDT 24
Peak memory 200532 kb
Host smart-721df3af-1a39-4def-b347-3c7b40d58e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242893595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3242893595
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3645492320
Short name T890
Test name
Test status
Simulation time 131129592830 ps
CPU time 61.71 seconds
Started May 26 02:17:33 PM PDT 24
Finished May 26 02:18:35 PM PDT 24
Peak memory 200584 kb
Host smart-2f06cb5a-a3be-4ed2-a176-4f11bbe17694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645492320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3645492320
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.4225562788
Short name T141
Test name
Test status
Simulation time 12444835738 ps
CPU time 20.33 seconds
Started May 26 02:17:33 PM PDT 24
Finished May 26 02:17:54 PM PDT 24
Peak memory 200320 kb
Host smart-b53feb7c-2a48-4d88-bb1f-78080c8afde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225562788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.4225562788
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1134738555
Short name T563
Test name
Test status
Simulation time 122421900117 ps
CPU time 89.37 seconds
Started May 26 02:17:32 PM PDT 24
Finished May 26 02:19:02 PM PDT 24
Peak memory 200460 kb
Host smart-cf4bbcdb-48ca-40c0-86ba-b4ba09bc27d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134738555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1134738555
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2711620919
Short name T974
Test name
Test status
Simulation time 17207102441 ps
CPU time 22.63 seconds
Started May 26 02:17:32 PM PDT 24
Finished May 26 02:17:55 PM PDT 24
Peak memory 200452 kb
Host smart-9b15dd18-f852-44d9-850b-9f163615fb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711620919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2711620919
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.686259507
Short name T348
Test name
Test status
Simulation time 84859868939 ps
CPU time 73.48 seconds
Started May 26 02:17:31 PM PDT 24
Finished May 26 02:18:45 PM PDT 24
Peak memory 200604 kb
Host smart-a672d011-a877-4b34-8c47-b987447bcdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686259507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.686259507
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2322837188
Short name T326
Test name
Test status
Simulation time 39977578927 ps
CPU time 58.89 seconds
Started May 26 02:17:39 PM PDT 24
Finished May 26 02:18:39 PM PDT 24
Peak memory 200476 kb
Host smart-e427d3ff-c3d4-43a7-8a42-b2caac72a023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322837188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2322837188
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2823286997
Short name T1133
Test name
Test status
Simulation time 44864823 ps
CPU time 0.56 seconds
Started May 26 02:12:50 PM PDT 24
Finished May 26 02:12:51 PM PDT 24
Peak memory 195900 kb
Host smart-b0e7a5b3-77cf-42f6-b6bf-da045195306f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823286997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2823286997
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.304829855
Short name T410
Test name
Test status
Simulation time 32480779261 ps
CPU time 14.2 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:13:09 PM PDT 24
Peak memory 200288 kb
Host smart-af278c84-9479-4811-9506-27bbbbf18a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304829855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.304829855
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3994853021
Short name T489
Test name
Test status
Simulation time 198069962907 ps
CPU time 67.89 seconds
Started May 26 02:12:52 PM PDT 24
Finished May 26 02:14:02 PM PDT 24
Peak memory 200472 kb
Host smart-147cad1d-6ac8-481e-ba13-0e8cbfbfee87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994853021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3994853021
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1985359440
Short name T354
Test name
Test status
Simulation time 97158926697 ps
CPU time 158.72 seconds
Started May 26 02:12:50 PM PDT 24
Finished May 26 02:15:29 PM PDT 24
Peak memory 200552 kb
Host smart-9e1bc9e8-a8cb-4177-a20a-7cacd3299e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985359440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1985359440
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.104336816
Short name T908
Test name
Test status
Simulation time 247035985863 ps
CPU time 134.32 seconds
Started May 26 02:12:50 PM PDT 24
Finished May 26 02:15:05 PM PDT 24
Peak memory 200364 kb
Host smart-430a8c69-43d5-4bed-8a18-72673cb4e865
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104336816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.104336816
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1417896555
Short name T378
Test name
Test status
Simulation time 90284421951 ps
CPU time 273.93 seconds
Started May 26 02:12:49 PM PDT 24
Finished May 26 02:17:24 PM PDT 24
Peak memory 200568 kb
Host smart-20c8882c-86c1-4f2f-bd42-3db46615a35f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1417896555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1417896555
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.4126246335
Short name T1077
Test name
Test status
Simulation time 11533304227 ps
CPU time 3.48 seconds
Started May 26 02:12:54 PM PDT 24
Finished May 26 02:12:59 PM PDT 24
Peak memory 199660 kb
Host smart-3b7e0031-8767-4bcf-aa8c-6092983514d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126246335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.4126246335
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1667349203
Short name T1135
Test name
Test status
Simulation time 174413344801 ps
CPU time 436.55 seconds
Started May 26 02:12:51 PM PDT 24
Finished May 26 02:20:09 PM PDT 24
Peak memory 200760 kb
Host smart-22460ec6-259f-4d4e-8f38-1ca24b183526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667349203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1667349203
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.471751372
Short name T305
Test name
Test status
Simulation time 8840009387 ps
CPU time 388.49 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:19:23 PM PDT 24
Peak memory 200540 kb
Host smart-04da89bf-65f0-4c07-b60f-2f65a27677a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=471751372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.471751372
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1769206812
Short name T108
Test name
Test status
Simulation time 1612112605 ps
CPU time 1.95 seconds
Started May 26 02:12:50 PM PDT 24
Finished May 26 02:12:53 PM PDT 24
Peak memory 199620 kb
Host smart-b8714abf-7604-4133-accf-fb83cb88cbab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769206812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1769206812
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2764619621
Short name T687
Test name
Test status
Simulation time 49085144930 ps
CPU time 55.2 seconds
Started May 26 02:12:52 PM PDT 24
Finished May 26 02:13:49 PM PDT 24
Peak memory 200500 kb
Host smart-43824172-80ea-497c-9508-188846980d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764619621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2764619621
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3076019598
Short name T365
Test name
Test status
Simulation time 1332989123 ps
CPU time 1.84 seconds
Started May 26 02:12:50 PM PDT 24
Finished May 26 02:12:53 PM PDT 24
Peak memory 195908 kb
Host smart-1cf8f0af-b5fe-491d-b844-d3b37dc4a871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076019598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3076019598
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3393073373
Short name T35
Test name
Test status
Simulation time 79141387 ps
CPU time 0.82 seconds
Started May 26 02:12:56 PM PDT 24
Finished May 26 02:12:58 PM PDT 24
Peak memory 218972 kb
Host smart-0360195b-e91e-41f4-ad88-17ec44c6cfd2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393073373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3393073373
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3923815709
Short name T537
Test name
Test status
Simulation time 5840859903 ps
CPU time 36.66 seconds
Started May 26 02:12:54 PM PDT 24
Finished May 26 02:13:32 PM PDT 24
Peak memory 199680 kb
Host smart-ff605014-4a66-4eae-87f5-e0e651e8a38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923815709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3923815709
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3514967193
Short name T445
Test name
Test status
Simulation time 142571638499 ps
CPU time 122.98 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:14:58 PM PDT 24
Peak memory 208964 kb
Host smart-514891ae-8ceb-48a0-823c-c2649ce0a90f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514967193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3514967193
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2411589385
Short name T1049
Test name
Test status
Simulation time 67574400244 ps
CPU time 953.62 seconds
Started May 26 02:12:52 PM PDT 24
Finished May 26 02:28:47 PM PDT 24
Peak memory 225484 kb
Host smart-1ac28caf-b94a-4ca6-b655-8aaf36493337
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411589385 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2411589385
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1801504265
Short name T1112
Test name
Test status
Simulation time 967059720 ps
CPU time 2.39 seconds
Started May 26 02:12:51 PM PDT 24
Finished May 26 02:12:55 PM PDT 24
Peak memory 200376 kb
Host smart-df98c220-265a-499b-a765-7a0941ae78c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801504265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1801504265
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3096095167
Short name T648
Test name
Test status
Simulation time 50017304879 ps
CPU time 15.6 seconds
Started May 26 02:12:52 PM PDT 24
Finished May 26 02:13:09 PM PDT 24
Peak memory 200064 kb
Host smart-f85898b6-3af1-4ec0-80dc-8d73b88dda17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096095167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3096095167
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2006015772
Short name T688
Test name
Test status
Simulation time 71962265 ps
CPU time 0.55 seconds
Started May 26 02:14:27 PM PDT 24
Finished May 26 02:14:28 PM PDT 24
Peak memory 194868 kb
Host smart-245f5a2d-88c0-4935-9417-bd4bff5e0f5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006015772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2006015772
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.892185014
Short name T965
Test name
Test status
Simulation time 28734787461 ps
CPU time 48.18 seconds
Started May 26 02:14:22 PM PDT 24
Finished May 26 02:15:11 PM PDT 24
Peak memory 200456 kb
Host smart-b5aa9f79-f1f6-4e98-bc52-8e12a2e3bcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892185014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.892185014
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3117329945
Short name T118
Test name
Test status
Simulation time 28321386538 ps
CPU time 31.12 seconds
Started May 26 02:14:22 PM PDT 24
Finished May 26 02:14:54 PM PDT 24
Peak memory 200536 kb
Host smart-c0822c68-c873-4bd0-b2b5-35a28485d4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117329945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3117329945
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.694150384
Short name T238
Test name
Test status
Simulation time 12972478822 ps
CPU time 22.95 seconds
Started May 26 02:14:23 PM PDT 24
Finished May 26 02:14:47 PM PDT 24
Peak memory 200508 kb
Host smart-5e95c994-e186-4b21-9038-79a61e9b7f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694150384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.694150384
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3385493780
Short name T843
Test name
Test status
Simulation time 22197291197 ps
CPU time 41.29 seconds
Started May 26 02:14:23 PM PDT 24
Finished May 26 02:15:05 PM PDT 24
Peak memory 200516 kb
Host smart-608233a3-8256-457f-8a94-8f07d1c68834
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385493780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3385493780
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2648123232
Short name T982
Test name
Test status
Simulation time 81804175561 ps
CPU time 442.83 seconds
Started May 26 02:14:25 PM PDT 24
Finished May 26 02:21:49 PM PDT 24
Peak memory 200548 kb
Host smart-aed27200-8371-4da8-b276-f6d760fdf19c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648123232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2648123232
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1123917151
Short name T417
Test name
Test status
Simulation time 55013128 ps
CPU time 0.68 seconds
Started May 26 02:14:23 PM PDT 24
Finished May 26 02:14:25 PM PDT 24
Peak memory 196308 kb
Host smart-7a00c90a-0a23-44cc-aaf3-a752a162a4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123917151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1123917151
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1546749360
Short name T1092
Test name
Test status
Simulation time 58157332586 ps
CPU time 97.59 seconds
Started May 26 02:14:25 PM PDT 24
Finished May 26 02:16:04 PM PDT 24
Peak memory 200652 kb
Host smart-57316994-f62f-4661-ba47-d3a0da13029f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546749360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1546749360
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1550062937
Short name T1089
Test name
Test status
Simulation time 20471197205 ps
CPU time 582.07 seconds
Started May 26 02:14:24 PM PDT 24
Finished May 26 02:24:07 PM PDT 24
Peak memory 200548 kb
Host smart-2633ce8b-bbd4-4128-a8f2-9176ae88df5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1550062937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1550062937
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3665688755
Short name T1043
Test name
Test status
Simulation time 4668687708 ps
CPU time 43.19 seconds
Started May 26 02:14:22 PM PDT 24
Finished May 26 02:15:06 PM PDT 24
Peak memory 200484 kb
Host smart-e0045c92-5a7e-4b7f-86ca-037a3b34deb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3665688755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3665688755
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2249124742
Short name T372
Test name
Test status
Simulation time 28230427875 ps
CPU time 19.17 seconds
Started May 26 02:14:24 PM PDT 24
Finished May 26 02:14:44 PM PDT 24
Peak memory 200268 kb
Host smart-516dc00c-dc63-4dec-8b62-dda2d9f01cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249124742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2249124742
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1850550385
Short name T46
Test name
Test status
Simulation time 4662647937 ps
CPU time 2.43 seconds
Started May 26 02:14:25 PM PDT 24
Finished May 26 02:14:29 PM PDT 24
Peak memory 196664 kb
Host smart-f4c9e17b-6048-486c-96b6-fa53da54d8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850550385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1850550385
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3189785916
Short name T645
Test name
Test status
Simulation time 547909116 ps
CPU time 2.75 seconds
Started May 26 02:14:27 PM PDT 24
Finished May 26 02:14:30 PM PDT 24
Peak memory 199116 kb
Host smart-f43c8425-8d1e-46ad-a896-7466c2127db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189785916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3189785916
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.86559706
Short name T1150
Test name
Test status
Simulation time 221464715248 ps
CPU time 1047.14 seconds
Started May 26 02:14:25 PM PDT 24
Finished May 26 02:31:53 PM PDT 24
Peak memory 200524 kb
Host smart-557ebc37-4a9f-4ceb-88a8-fbb8c66fd3f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86559706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.86559706
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3540463817
Short name T720
Test name
Test status
Simulation time 2889085731 ps
CPU time 2.31 seconds
Started May 26 02:14:23 PM PDT 24
Finished May 26 02:14:26 PM PDT 24
Peak memory 199240 kb
Host smart-c9c5b8bd-7b35-43b3-9346-8681b340abe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540463817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3540463817
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2621928283
Short name T985
Test name
Test status
Simulation time 129007601545 ps
CPU time 63.85 seconds
Started May 26 02:14:24 PM PDT 24
Finished May 26 02:15:30 PM PDT 24
Peak memory 200504 kb
Host smart-11bdb5b8-84be-4091-a676-3211da7427b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621928283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2621928283
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3832548987
Short name T839
Test name
Test status
Simulation time 94540212 ps
CPU time 0.62 seconds
Started May 26 02:14:30 PM PDT 24
Finished May 26 02:14:32 PM PDT 24
Peak memory 195892 kb
Host smart-09d8df63-bb6a-4e15-a4aa-8d02bc50d7c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832548987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3832548987
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.389468759
Short name T944
Test name
Test status
Simulation time 33877611841 ps
CPU time 15.6 seconds
Started May 26 02:14:23 PM PDT 24
Finished May 26 02:14:39 PM PDT 24
Peak memory 200460 kb
Host smart-a34262f6-7374-4e2d-abd1-eb6554cb776c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389468759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.389468759
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3116939584
Short name T871
Test name
Test status
Simulation time 61550174988 ps
CPU time 24.06 seconds
Started May 26 02:14:22 PM PDT 24
Finished May 26 02:14:47 PM PDT 24
Peak memory 198764 kb
Host smart-7661cb36-0132-465b-9468-0d775b8e893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116939584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3116939584
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3496401302
Short name T733
Test name
Test status
Simulation time 12426465464 ps
CPU time 22.82 seconds
Started May 26 02:14:26 PM PDT 24
Finished May 26 02:14:49 PM PDT 24
Peak memory 200648 kb
Host smart-866bdaf3-f143-4b82-9125-a87f4d966804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496401302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3496401302
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2551383896
Short name T932
Test name
Test status
Simulation time 24503068597 ps
CPU time 11.72 seconds
Started May 26 02:14:24 PM PDT 24
Finished May 26 02:14:37 PM PDT 24
Peak memory 200416 kb
Host smart-a9e4243d-d53d-4d60-ad32-d812a1c69784
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551383896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2551383896
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.150535411
Short name T517
Test name
Test status
Simulation time 99291559227 ps
CPU time 552.57 seconds
Started May 26 02:14:32 PM PDT 24
Finished May 26 02:23:45 PM PDT 24
Peak memory 200508 kb
Host smart-7cd91bcf-a0af-43e1-b6dc-ffc1d15ad5fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=150535411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.150535411
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3097824463
Short name T1154
Test name
Test status
Simulation time 3609281588 ps
CPU time 2.81 seconds
Started May 26 02:14:30 PM PDT 24
Finished May 26 02:14:34 PM PDT 24
Peak memory 198924 kb
Host smart-9177d55b-a03b-414a-8719-51fc9d9ff9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097824463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3097824463
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.606863567
Short name T463
Test name
Test status
Simulation time 66714093174 ps
CPU time 37.36 seconds
Started May 26 02:14:23 PM PDT 24
Finished May 26 02:15:01 PM PDT 24
Peak memory 208912 kb
Host smart-4117655e-e2bf-4934-9525-541633de144c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606863567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.606863567
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2821245874
Short name T888
Test name
Test status
Simulation time 22440569598 ps
CPU time 227.95 seconds
Started May 26 02:14:30 PM PDT 24
Finished May 26 02:18:19 PM PDT 24
Peak memory 200556 kb
Host smart-75d8af59-2fa2-41e1-b202-57cc45695ed8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821245874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2821245874
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.4042085047
Short name T1147
Test name
Test status
Simulation time 6850059064 ps
CPU time 17.11 seconds
Started May 26 02:14:25 PM PDT 24
Finished May 26 02:14:43 PM PDT 24
Peak memory 198624 kb
Host smart-2c9bcee7-b72f-493c-9288-9cff1050e1ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4042085047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.4042085047
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3526384849
Short name T555
Test name
Test status
Simulation time 87830259782 ps
CPU time 101.58 seconds
Started May 26 02:14:23 PM PDT 24
Finished May 26 02:16:06 PM PDT 24
Peak memory 200512 kb
Host smart-47e4ceb4-a6ed-418f-8d2f-1fe7288140a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526384849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3526384849
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3175995872
Short name T1123
Test name
Test status
Simulation time 2906875932 ps
CPU time 2.01 seconds
Started May 26 02:14:24 PM PDT 24
Finished May 26 02:14:28 PM PDT 24
Peak memory 196252 kb
Host smart-993c368c-9e61-4bf0-951a-92be19d55251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175995872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3175995872
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3233572449
Short name T994
Test name
Test status
Simulation time 668175745 ps
CPU time 1.37 seconds
Started May 26 02:14:24 PM PDT 24
Finished May 26 02:14:26 PM PDT 24
Peak memory 198800 kb
Host smart-d79ff4e5-a9c9-470f-9c7d-09f0e8756aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233572449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3233572449
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3671878121
Short name T1094
Test name
Test status
Simulation time 572490560583 ps
CPU time 1478.86 seconds
Started May 26 02:14:31 PM PDT 24
Finished May 26 02:39:11 PM PDT 24
Peak memory 200572 kb
Host smart-5781765d-540d-4d25-a627-c8195d9358b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671878121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3671878121
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3664650342
Short name T1021
Test name
Test status
Simulation time 107330000635 ps
CPU time 635.78 seconds
Started May 26 02:14:31 PM PDT 24
Finished May 26 02:25:08 PM PDT 24
Peak memory 229188 kb
Host smart-38c29258-c7da-4e45-abfb-e34959edf5bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664650342 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3664650342
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1130834413
Short name T498
Test name
Test status
Simulation time 6859240727 ps
CPU time 38.17 seconds
Started May 26 02:14:26 PM PDT 24
Finished May 26 02:15:05 PM PDT 24
Peak memory 200500 kb
Host smart-d2b2e01c-49b8-41d9-81e5-c3f12789251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130834413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1130834413
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2593817697
Short name T1169
Test name
Test status
Simulation time 39046787385 ps
CPU time 15.96 seconds
Started May 26 02:14:24 PM PDT 24
Finished May 26 02:14:41 PM PDT 24
Peak memory 198896 kb
Host smart-977261ce-3598-4a0a-87ed-4dedf05a8c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593817697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2593817697
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1508366386
Short name T958
Test name
Test status
Simulation time 34695728 ps
CPU time 0.55 seconds
Started May 26 02:14:30 PM PDT 24
Finished May 26 02:14:31 PM PDT 24
Peak memory 195360 kb
Host smart-34843890-3471-410b-804d-d9d0aa1bb270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508366386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1508366386
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1991807771
Short name T121
Test name
Test status
Simulation time 14417344027 ps
CPU time 24.52 seconds
Started May 26 02:14:30 PM PDT 24
Finished May 26 02:14:56 PM PDT 24
Peak memory 200512 kb
Host smart-5021d552-f941-4839-a8a6-f1badc5e4dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991807771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1991807771
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.561189197
Short name T654
Test name
Test status
Simulation time 138919542749 ps
CPU time 119.86 seconds
Started May 26 02:14:32 PM PDT 24
Finished May 26 02:16:32 PM PDT 24
Peak memory 200500 kb
Host smart-b9815b81-8374-4a76-bb1e-a1865aff7e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561189197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.561189197
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1220824115
Short name T1095
Test name
Test status
Simulation time 100761570169 ps
CPU time 385.07 seconds
Started May 26 02:14:30 PM PDT 24
Finished May 26 02:20:56 PM PDT 24
Peak memory 200476 kb
Host smart-bff58da7-5ca0-4bac-ae26-399c89040d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220824115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1220824115
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1399371249
Short name T856
Test name
Test status
Simulation time 29121042336 ps
CPU time 48.78 seconds
Started May 26 02:14:30 PM PDT 24
Finished May 26 02:15:20 PM PDT 24
Peak memory 200560 kb
Host smart-53660470-1b14-482b-88d5-d06d0f620533
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399371249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1399371249
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.4001856303
Short name T540
Test name
Test status
Simulation time 114966381176 ps
CPU time 849.78 seconds
Started May 26 02:14:30 PM PDT 24
Finished May 26 02:28:41 PM PDT 24
Peak memory 200560 kb
Host smart-83d5ce22-c92f-4af2-97ba-b1ae0e6b5dd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4001856303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.4001856303
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3407589339
Short name T23
Test name
Test status
Simulation time 5084601088 ps
CPU time 3.28 seconds
Started May 26 02:14:29 PM PDT 24
Finished May 26 02:14:33 PM PDT 24
Peak memory 199304 kb
Host smart-96bce369-4b94-4d26-82e4-6a20ec08a259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407589339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3407589339
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1827541092
Short name T895
Test name
Test status
Simulation time 45996758906 ps
CPU time 71.25 seconds
Started May 26 02:14:30 PM PDT 24
Finished May 26 02:15:42 PM PDT 24
Peak memory 200708 kb
Host smart-6fc700b1-e93b-4ea8-888f-c3a27218f82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827541092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1827541092
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2570576986
Short name T479
Test name
Test status
Simulation time 28105280388 ps
CPU time 196.22 seconds
Started May 26 02:14:31 PM PDT 24
Finished May 26 02:17:48 PM PDT 24
Peak memory 200520 kb
Host smart-9c1d3bcc-d1b1-4b1c-bc7d-b426786b18ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2570576986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2570576986
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3762635872
Short name T107
Test name
Test status
Simulation time 5875133684 ps
CPU time 23.9 seconds
Started May 26 02:14:32 PM PDT 24
Finished May 26 02:14:56 PM PDT 24
Peak memory 200328 kb
Host smart-c01ec9ea-89c9-4a66-98f0-2a70c2648051
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3762635872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3762635872
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3989712745
Short name T1155
Test name
Test status
Simulation time 149024587300 ps
CPU time 30.49 seconds
Started May 26 02:14:33 PM PDT 24
Finished May 26 02:15:04 PM PDT 24
Peak memory 200540 kb
Host smart-19e84a21-8fe9-41f6-8819-9e54fd0a0bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989712745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3989712745
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3820744337
Short name T1019
Test name
Test status
Simulation time 422600340 ps
CPU time 1.01 seconds
Started May 26 02:14:31 PM PDT 24
Finished May 26 02:14:33 PM PDT 24
Peak memory 196156 kb
Host smart-e2349372-84c5-4d26-aa39-e955a2c1749f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820744337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3820744337
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.669584558
Short name T300
Test name
Test status
Simulation time 10541115049 ps
CPU time 22.61 seconds
Started May 26 02:14:30 PM PDT 24
Finished May 26 02:14:53 PM PDT 24
Peak memory 200220 kb
Host smart-64a5c374-cf07-4f5e-8b85-d150358c1891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669584558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.669584558
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3600071591
Short name T528
Test name
Test status
Simulation time 262767173006 ps
CPU time 689.43 seconds
Started May 26 02:14:31 PM PDT 24
Finished May 26 02:26:01 PM PDT 24
Peak memory 200568 kb
Host smart-130c1b0d-8e57-4287-b008-5ed3ec917746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600071591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3600071591
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1323874363
Short name T572
Test name
Test status
Simulation time 7482235597 ps
CPU time 10.84 seconds
Started May 26 02:14:30 PM PDT 24
Finished May 26 02:14:42 PM PDT 24
Peak memory 200448 kb
Host smart-852c33a4-cf79-482b-a341-d3ed1bb37ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323874363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1323874363
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3853087614
Short name T740
Test name
Test status
Simulation time 15347776829 ps
CPU time 24.64 seconds
Started May 26 02:14:33 PM PDT 24
Finished May 26 02:14:58 PM PDT 24
Peak memory 200556 kb
Host smart-3d1a470a-5470-4a8b-9427-12798c1c873a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853087614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3853087614
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2386688656
Short name T369
Test name
Test status
Simulation time 18520537 ps
CPU time 0.57 seconds
Started May 26 02:14:36 PM PDT 24
Finished May 26 02:14:37 PM PDT 24
Peak memory 195900 kb
Host smart-bb22e6fe-1df2-4a9f-ac94-57da014e7a84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386688656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2386688656
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1377663620
Short name T664
Test name
Test status
Simulation time 208812569834 ps
CPU time 84.08 seconds
Started May 26 02:14:33 PM PDT 24
Finished May 26 02:15:58 PM PDT 24
Peak memory 200516 kb
Host smart-e0f1b609-c12e-49c0-97f2-93f5ea0916a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377663620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1377663620
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.770973140
Short name T1067
Test name
Test status
Simulation time 200043514933 ps
CPU time 152.32 seconds
Started May 26 02:14:32 PM PDT 24
Finished May 26 02:17:05 PM PDT 24
Peak memory 200432 kb
Host smart-3cd4ca61-3995-45cf-b8fc-61bf246d2593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770973140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.770973140
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1519680495
Short name T561
Test name
Test status
Simulation time 77874318863 ps
CPU time 39.63 seconds
Started May 26 02:14:39 PM PDT 24
Finished May 26 02:15:20 PM PDT 24
Peak memory 200500 kb
Host smart-59835913-6e06-4f97-9d9d-eebe8f1c6ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519680495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1519680495
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1396560286
Short name T538
Test name
Test status
Simulation time 28077513484 ps
CPU time 16.69 seconds
Started May 26 02:14:37 PM PDT 24
Finished May 26 02:14:55 PM PDT 24
Peak memory 200172 kb
Host smart-9f8e8163-1055-4de8-949a-6bcbad7e9220
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396560286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1396560286
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.82719358
Short name T882
Test name
Test status
Simulation time 89710776691 ps
CPU time 156.83 seconds
Started May 26 02:14:38 PM PDT 24
Finished May 26 02:17:16 PM PDT 24
Peak memory 200472 kb
Host smart-33faa794-d877-442e-94b1-d8015880b769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82719358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.82719358
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.229287853
Short name T614
Test name
Test status
Simulation time 2369999159 ps
CPU time 2.09 seconds
Started May 26 02:14:40 PM PDT 24
Finished May 26 02:14:44 PM PDT 24
Peak memory 196788 kb
Host smart-234a8908-1610-400f-bce6-c0f842c5f9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229287853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.229287853
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.4241559872
Short name T111
Test name
Test status
Simulation time 54786089451 ps
CPU time 68.35 seconds
Started May 26 02:14:38 PM PDT 24
Finished May 26 02:15:48 PM PDT 24
Peak memory 200340 kb
Host smart-7d9f8b2e-7d42-4848-9221-d987d7b6667b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241559872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.4241559872
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1727674219
Short name T266
Test name
Test status
Simulation time 10797238823 ps
CPU time 134.86 seconds
Started May 26 02:14:39 PM PDT 24
Finished May 26 02:16:55 PM PDT 24
Peak memory 200436 kb
Host smart-db0076a2-405d-4cee-9d9a-fccd9e721982
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1727674219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1727674219
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2949936381
Short name T852
Test name
Test status
Simulation time 7594545136 ps
CPU time 35.11 seconds
Started May 26 02:14:38 PM PDT 24
Finished May 26 02:15:15 PM PDT 24
Peak memory 198628 kb
Host smart-188b8f18-82cb-45ab-acad-b2eb95129f5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2949936381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2949936381
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.336845363
Short name T832
Test name
Test status
Simulation time 5827161667 ps
CPU time 11.25 seconds
Started May 26 02:14:37 PM PDT 24
Finished May 26 02:14:49 PM PDT 24
Peak memory 200260 kb
Host smart-d7f4eac1-77f2-47fc-9ab5-719ce6c0647a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336845363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.336845363
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3129341783
Short name T55
Test name
Test status
Simulation time 34133394651 ps
CPU time 56.33 seconds
Started May 26 02:14:38 PM PDT 24
Finished May 26 02:15:35 PM PDT 24
Peak memory 196552 kb
Host smart-3cd81296-86e3-47e7-a125-379be5a98aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129341783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3129341783
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3623870474
Short name T1121
Test name
Test status
Simulation time 6257547478 ps
CPU time 12.33 seconds
Started May 26 02:14:32 PM PDT 24
Finished May 26 02:14:45 PM PDT 24
Peak memory 200460 kb
Host smart-281fe8d9-f920-4e66-9386-10f53f609757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623870474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3623870474
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.169754487
Short name T225
Test name
Test status
Simulation time 440964431705 ps
CPU time 504.38 seconds
Started May 26 02:14:39 PM PDT 24
Finished May 26 02:23:05 PM PDT 24
Peak memory 208980 kb
Host smart-8797278d-dfb8-496f-8b63-a63ade4ba679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169754487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.169754487
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2200328831
Short name T1073
Test name
Test status
Simulation time 323364005284 ps
CPU time 1234.09 seconds
Started May 26 02:14:39 PM PDT 24
Finished May 26 02:35:15 PM PDT 24
Peak memory 225116 kb
Host smart-3428cd01-3b2c-4979-b533-32401350f269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200328831 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2200328831
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1774322808
Short name T806
Test name
Test status
Simulation time 2138695370 ps
CPU time 1.77 seconds
Started May 26 02:14:39 PM PDT 24
Finished May 26 02:14:42 PM PDT 24
Peak memory 199592 kb
Host smart-4d618056-60f9-4451-aa6f-3a9e80781245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774322808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1774322808
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2511871208
Short name T780
Test name
Test status
Simulation time 79551016217 ps
CPU time 145.32 seconds
Started May 26 02:14:29 PM PDT 24
Finished May 26 02:16:55 PM PDT 24
Peak memory 200556 kb
Host smart-93a62f1a-4f3d-47db-b434-1b399fab4e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511871208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2511871208
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.152070229
Short name T397
Test name
Test status
Simulation time 60660450 ps
CPU time 0.57 seconds
Started May 26 02:14:41 PM PDT 24
Finished May 26 02:14:43 PM PDT 24
Peak memory 195900 kb
Host smart-c8e07e5a-b7a7-4d0f-a530-e0fca8875b63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152070229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.152070229
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1328210103
Short name T678
Test name
Test status
Simulation time 95934809667 ps
CPU time 45.13 seconds
Started May 26 02:14:38 PM PDT 24
Finished May 26 02:15:24 PM PDT 24
Peak memory 200572 kb
Host smart-e0810a23-8530-481c-999c-c22a7ea53db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328210103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1328210103
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.95102850
Short name T916
Test name
Test status
Simulation time 17308483817 ps
CPU time 17.64 seconds
Started May 26 02:14:38 PM PDT 24
Finished May 26 02:14:56 PM PDT 24
Peak memory 200196 kb
Host smart-77a4df7f-c232-47d9-bafc-714fdc3175cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95102850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.95102850
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1851079354
Short name T800
Test name
Test status
Simulation time 10392772287 ps
CPU time 18.3 seconds
Started May 26 02:14:38 PM PDT 24
Finished May 26 02:14:58 PM PDT 24
Peak memory 200492 kb
Host smart-395be89a-e8b9-4a8d-9a5c-e1c1016981e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851079354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1851079354
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2973835013
Short name T598
Test name
Test status
Simulation time 253142673403 ps
CPU time 429.2 seconds
Started May 26 02:14:37 PM PDT 24
Finished May 26 02:21:47 PM PDT 24
Peak memory 199524 kb
Host smart-e1f40b81-b8b4-43b2-aed3-7fe8005e9145
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973835013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2973835013
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1737050666
Short name T405
Test name
Test status
Simulation time 63133826639 ps
CPU time 219.96 seconds
Started May 26 02:14:39 PM PDT 24
Finished May 26 02:18:21 PM PDT 24
Peak memory 200532 kb
Host smart-80ffb41f-4c72-4742-a54f-f352c6cd44dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737050666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1737050666
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2837414354
Short name T4
Test name
Test status
Simulation time 5573117562 ps
CPU time 2.24 seconds
Started May 26 02:14:38 PM PDT 24
Finished May 26 02:14:41 PM PDT 24
Peak memory 199692 kb
Host smart-d1d2ecbd-6649-4f1b-956e-e88329152ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837414354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2837414354
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.659613833
Short name T608
Test name
Test status
Simulation time 111520306379 ps
CPU time 111.69 seconds
Started May 26 02:14:40 PM PDT 24
Finished May 26 02:16:33 PM PDT 24
Peak memory 209024 kb
Host smart-85ff7d43-94cc-48aa-a552-dd8f1b047f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659613833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.659613833
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.328991800
Short name T973
Test name
Test status
Simulation time 11150330866 ps
CPU time 192.59 seconds
Started May 26 02:14:39 PM PDT 24
Finished May 26 02:17:53 PM PDT 24
Peak memory 200500 kb
Host smart-39b4550e-6e84-4a13-95d9-be6d42e6884e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328991800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.328991800
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.585101361
Short name T952
Test name
Test status
Simulation time 2648435389 ps
CPU time 20.5 seconds
Started May 26 02:14:39 PM PDT 24
Finished May 26 02:15:01 PM PDT 24
Peak memory 198888 kb
Host smart-441db0a6-2845-489b-9dad-edfbd87b24ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585101361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.585101361
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3557319261
Short name T7
Test name
Test status
Simulation time 147173227056 ps
CPU time 63.82 seconds
Started May 26 02:14:39 PM PDT 24
Finished May 26 02:15:44 PM PDT 24
Peak memory 200408 kb
Host smart-afebd899-4c2b-46bb-b137-c01b2d194242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557319261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3557319261
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.4222510526
Short name T663
Test name
Test status
Simulation time 539170202 ps
CPU time 1.56 seconds
Started May 26 02:14:40 PM PDT 24
Finished May 26 02:14:43 PM PDT 24
Peak memory 196308 kb
Host smart-a94b447a-adaa-433a-8218-db35282e5f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222510526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.4222510526
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1526039509
Short name T967
Test name
Test status
Simulation time 697744315 ps
CPU time 2.27 seconds
Started May 26 02:14:39 PM PDT 24
Finished May 26 02:14:43 PM PDT 24
Peak memory 200404 kb
Host smart-99f14619-ae60-4c7f-baf0-e6b2006fd7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526039509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1526039509
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3015458967
Short name T474
Test name
Test status
Simulation time 140970511395 ps
CPU time 173.31 seconds
Started May 26 02:14:40 PM PDT 24
Finished May 26 02:17:35 PM PDT 24
Peak memory 200924 kb
Host smart-27d394f2-4ecd-4f6f-ade0-e2f4642481e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015458967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3015458967
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2066844675
Short name T41
Test name
Test status
Simulation time 56105109478 ps
CPU time 519.71 seconds
Started May 26 02:14:38 PM PDT 24
Finished May 26 02:23:19 PM PDT 24
Peak memory 227872 kb
Host smart-0c96b5ba-99ee-42b7-b74f-213aae50024e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066844675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2066844675
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2996566719
Short name T880
Test name
Test status
Simulation time 2634535207 ps
CPU time 1.66 seconds
Started May 26 02:14:38 PM PDT 24
Finished May 26 02:14:41 PM PDT 24
Peak memory 199508 kb
Host smart-90a428bf-8d5a-4376-b5d5-c6f175b0b462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996566719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2996566719
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2257956660
Short name T399
Test name
Test status
Simulation time 30127097893 ps
CPU time 19.03 seconds
Started May 26 02:14:37 PM PDT 24
Finished May 26 02:14:57 PM PDT 24
Peak memory 200320 kb
Host smart-5668124d-14ea-4074-9954-e985319543f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257956660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2257956660
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2886190786
Short name T54
Test name
Test status
Simulation time 21672631 ps
CPU time 0.54 seconds
Started May 26 02:14:45 PM PDT 24
Finished May 26 02:14:46 PM PDT 24
Peak memory 195804 kb
Host smart-60641c16-bace-4370-88e4-858dfe0a9d3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886190786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2886190786
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2911167163
Short name T284
Test name
Test status
Simulation time 40774840837 ps
CPU time 34.97 seconds
Started May 26 02:14:53 PM PDT 24
Finished May 26 02:15:29 PM PDT 24
Peak memory 200532 kb
Host smart-db79c279-e754-4a70-835e-34ea88f0cf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911167163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2911167163
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1600324527
Short name T133
Test name
Test status
Simulation time 59488283237 ps
CPU time 27.23 seconds
Started May 26 02:14:43 PM PDT 24
Finished May 26 02:15:11 PM PDT 24
Peak memory 200556 kb
Host smart-5ca0c2c2-f593-43c1-9134-e3a610952349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600324527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1600324527
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1006100153
Short name T446
Test name
Test status
Simulation time 32028902881 ps
CPU time 12.11 seconds
Started May 26 02:14:46 PM PDT 24
Finished May 26 02:14:59 PM PDT 24
Peak memory 200564 kb
Host smart-8de44aab-5632-4d74-9ea1-9e5a3a698da4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006100153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1006100153
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3244614286
Short name T470
Test name
Test status
Simulation time 167804736130 ps
CPU time 453.79 seconds
Started May 26 02:14:53 PM PDT 24
Finished May 26 02:22:28 PM PDT 24
Peak memory 200476 kb
Host smart-8595248a-7622-4c1c-80b7-8c53df7fcf7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244614286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3244614286
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2711488340
Short name T1111
Test name
Test status
Simulation time 2839112535 ps
CPU time 2.74 seconds
Started May 26 02:14:56 PM PDT 24
Finished May 26 02:14:59 PM PDT 24
Peak memory 198032 kb
Host smart-f87f77fc-928d-404d-a353-6e84b37b6db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711488340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2711488340
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.686128938
Short name T718
Test name
Test status
Simulation time 16625608374 ps
CPU time 14.03 seconds
Started May 26 02:14:45 PM PDT 24
Finished May 26 02:15:00 PM PDT 24
Peak memory 198872 kb
Host smart-067801b9-07c4-4b9e-8e0f-4787426da4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686128938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.686128938
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2219406580
Short name T759
Test name
Test status
Simulation time 14530524780 ps
CPU time 454.03 seconds
Started May 26 02:14:57 PM PDT 24
Finished May 26 02:22:32 PM PDT 24
Peak memory 200548 kb
Host smart-44386f4b-0a85-460c-a827-cf37b39368a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2219406580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2219406580
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2656417077
Short name T937
Test name
Test status
Simulation time 2540425081 ps
CPU time 11.84 seconds
Started May 26 02:14:53 PM PDT 24
Finished May 26 02:15:06 PM PDT 24
Peak memory 198676 kb
Host smart-1199bc85-d7ad-4dc6-8ebc-e7608d1a7af7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656417077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2656417077
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3655761207
Short name T934
Test name
Test status
Simulation time 31386495078 ps
CPU time 12.24 seconds
Started May 26 02:14:55 PM PDT 24
Finished May 26 02:15:08 PM PDT 24
Peak memory 196224 kb
Host smart-209f98ba-1235-449c-8f03-d69b1c87bd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655761207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3655761207
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3222699029
Short name T1142
Test name
Test status
Simulation time 5579784861 ps
CPU time 7.36 seconds
Started May 26 02:14:54 PM PDT 24
Finished May 26 02:15:03 PM PDT 24
Peak memory 200484 kb
Host smart-4d7d43e8-79fa-4a51-82d9-48fac6e3d131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222699029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3222699029
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1575175392
Short name T975
Test name
Test status
Simulation time 17851880318 ps
CPU time 180.26 seconds
Started May 26 02:14:55 PM PDT 24
Finished May 26 02:17:56 PM PDT 24
Peak memory 200500 kb
Host smart-86639ef0-c385-46fb-a97b-d8016a364d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575175392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1575175392
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2431476194
Short name T116
Test name
Test status
Simulation time 80074256078 ps
CPU time 805.15 seconds
Started May 26 02:14:54 PM PDT 24
Finished May 26 02:28:21 PM PDT 24
Peak memory 225408 kb
Host smart-f6f7ad25-42fe-4602-aeee-1e229b9f3c00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431476194 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2431476194
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2731641159
Short name T321
Test name
Test status
Simulation time 1149022752 ps
CPU time 2.61 seconds
Started May 26 02:14:54 PM PDT 24
Finished May 26 02:14:58 PM PDT 24
Peak memory 198920 kb
Host smart-a6a664db-521c-48fa-8cb5-1c91e4e623e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731641159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2731641159
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1308346530
Short name T263
Test name
Test status
Simulation time 60162503375 ps
CPU time 7.81 seconds
Started May 26 02:14:52 PM PDT 24
Finished May 26 02:15:00 PM PDT 24
Peak memory 200512 kb
Host smart-d893d033-9a61-4bf2-b3b8-6eb13db99a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308346530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1308346530
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2037664024
Short name T877
Test name
Test status
Simulation time 14282645 ps
CPU time 0.57 seconds
Started May 26 02:14:52 PM PDT 24
Finished May 26 02:14:53 PM PDT 24
Peak memory 195924 kb
Host smart-807268c5-5d1e-430c-b725-5d7ebfe96ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037664024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2037664024
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3010707112
Short name T707
Test name
Test status
Simulation time 144391762551 ps
CPU time 195.33 seconds
Started May 26 02:14:45 PM PDT 24
Finished May 26 02:18:00 PM PDT 24
Peak memory 200468 kb
Host smart-bd80f00a-e320-409b-95a2-35e580b6614f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010707112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3010707112
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.868834682
Short name T1015
Test name
Test status
Simulation time 79962339960 ps
CPU time 130.76 seconds
Started May 26 02:14:53 PM PDT 24
Finished May 26 02:17:05 PM PDT 24
Peak memory 200492 kb
Host smart-2cd2efd1-f6d8-4a31-bf66-1e5348447f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868834682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.868834682
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3049666308
Short name T1029
Test name
Test status
Simulation time 117693948399 ps
CPU time 49.05 seconds
Started May 26 02:14:53 PM PDT 24
Finished May 26 02:15:43 PM PDT 24
Peak memory 200528 kb
Host smart-3e7b85fe-8372-40c6-8be2-5193b12e6657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049666308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3049666308
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.59048085
Short name T49
Test name
Test status
Simulation time 22531828330 ps
CPU time 39.76 seconds
Started May 26 02:14:55 PM PDT 24
Finished May 26 02:15:36 PM PDT 24
Peak memory 199528 kb
Host smart-dfbcfef3-470d-40ef-97e6-7887a9648dc7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59048085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.59048085
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3703948154
Short name T919
Test name
Test status
Simulation time 109855440661 ps
CPU time 281.96 seconds
Started May 26 02:14:55 PM PDT 24
Finished May 26 02:19:38 PM PDT 24
Peak memory 200456 kb
Host smart-44606c56-4faf-472b-8953-9e0c24198d94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3703948154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3703948154
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1110114520
Short name T338
Test name
Test status
Simulation time 2551477642 ps
CPU time 3.97 seconds
Started May 26 02:14:53 PM PDT 24
Finished May 26 02:14:58 PM PDT 24
Peak memory 199292 kb
Host smart-d13fdef1-ceb1-4316-a06f-a16bbf1397ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110114520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1110114520
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2168287220
Short name T1113
Test name
Test status
Simulation time 230828850447 ps
CPU time 43 seconds
Started May 26 02:14:53 PM PDT 24
Finished May 26 02:15:37 PM PDT 24
Peak memory 200888 kb
Host smart-41f9e921-d611-4b48-b9a7-e58e19f13f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168287220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2168287220
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.475036150
Short name T860
Test name
Test status
Simulation time 24513956061 ps
CPU time 299.27 seconds
Started May 26 02:14:56 PM PDT 24
Finished May 26 02:19:56 PM PDT 24
Peak memory 200492 kb
Host smart-c2c7d3c3-c33b-42d0-97f9-7ad1630fbb82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=475036150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.475036150
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3986472855
Short name T977
Test name
Test status
Simulation time 4583237544 ps
CPU time 9.5 seconds
Started May 26 02:14:52 PM PDT 24
Finished May 26 02:15:02 PM PDT 24
Peak memory 199272 kb
Host smart-1f37e614-fa21-45d1-8be5-8e657130c742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986472855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3986472855
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1577443944
Short name T796
Test name
Test status
Simulation time 186379148813 ps
CPU time 15.27 seconds
Started May 26 02:14:53 PM PDT 24
Finished May 26 02:15:09 PM PDT 24
Peak memory 200492 kb
Host smart-e414961d-56a3-46dc-8bec-fe34f6280927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577443944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1577443944
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1106438945
Short name T1091
Test name
Test status
Simulation time 2854124413 ps
CPU time 5.47 seconds
Started May 26 02:14:57 PM PDT 24
Finished May 26 02:15:03 PM PDT 24
Peak memory 196240 kb
Host smart-951ff27b-f5a2-48c6-8489-238b639d35b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106438945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1106438945
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2710672674
Short name T757
Test name
Test status
Simulation time 464599673 ps
CPU time 2.23 seconds
Started May 26 02:14:45 PM PDT 24
Finished May 26 02:14:47 PM PDT 24
Peak memory 200396 kb
Host smart-42496576-4279-4ae3-9298-1130a8d5e398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710672674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2710672674
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3020487031
Short name T1151
Test name
Test status
Simulation time 221234951607 ps
CPU time 104.44 seconds
Started May 26 02:14:54 PM PDT 24
Finished May 26 02:16:40 PM PDT 24
Peak memory 200944 kb
Host smart-559f445e-b83b-43e3-8f28-4550be2795ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020487031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3020487031
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3888612795
Short name T312
Test name
Test status
Simulation time 61520135380 ps
CPU time 727.08 seconds
Started May 26 02:14:53 PM PDT 24
Finished May 26 02:27:01 PM PDT 24
Peak memory 216928 kb
Host smart-57671820-d47c-4701-945b-bdfb66af27fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888612795 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3888612795
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2675537256
Short name T696
Test name
Test status
Simulation time 1525237707 ps
CPU time 1.38 seconds
Started May 26 02:14:54 PM PDT 24
Finished May 26 02:14:56 PM PDT 24
Peak memory 197456 kb
Host smart-4fb474f2-3994-4cd1-806f-e6a3607bd9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675537256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2675537256
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3654770369
Short name T656
Test name
Test status
Simulation time 32955680052 ps
CPU time 48.88 seconds
Started May 26 02:14:56 PM PDT 24
Finished May 26 02:15:45 PM PDT 24
Peak memory 200496 kb
Host smart-3d5c162e-767e-4671-badc-00205e035d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654770369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3654770369
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2378625091
Short name T585
Test name
Test status
Simulation time 11939900 ps
CPU time 0.56 seconds
Started May 26 02:15:03 PM PDT 24
Finished May 26 02:15:05 PM PDT 24
Peak memory 195908 kb
Host smart-f07491c3-d6fa-4f50-8e8c-43ff44b5284a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378625091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2378625091
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3069227245
Short name T655
Test name
Test status
Simulation time 184483558047 ps
CPU time 74.32 seconds
Started May 26 02:14:54 PM PDT 24
Finished May 26 02:16:10 PM PDT 24
Peak memory 200500 kb
Host smart-d5d10b38-7bd2-4cfa-b0b7-3850cdd8bc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069227245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3069227245
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.4074246014
Short name T902
Test name
Test status
Simulation time 111844305949 ps
CPU time 73.65 seconds
Started May 26 02:14:57 PM PDT 24
Finished May 26 02:16:12 PM PDT 24
Peak memory 200448 kb
Host smart-a8df3418-0880-4f7d-82f1-970334a2d26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074246014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.4074246014
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3376675137
Short name T1164
Test name
Test status
Simulation time 62019113471 ps
CPU time 61.88 seconds
Started May 26 02:14:55 PM PDT 24
Finished May 26 02:15:58 PM PDT 24
Peak memory 200584 kb
Host smart-d2cc9d41-bbdd-46be-9958-e156ca12b994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376675137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3376675137
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.454514232
Short name T425
Test name
Test status
Simulation time 40424328675 ps
CPU time 17.87 seconds
Started May 26 02:14:54 PM PDT 24
Finished May 26 02:15:13 PM PDT 24
Peak memory 199388 kb
Host smart-c2b0e7cc-b7d3-4fa1-8165-2927de5d5d3b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454514232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.454514232
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.622384868
Short name T739
Test name
Test status
Simulation time 127593011938 ps
CPU time 486.68 seconds
Started May 26 02:14:54 PM PDT 24
Finished May 26 02:23:01 PM PDT 24
Peak memory 200456 kb
Host smart-62e988de-8e7e-40fc-b264-ff9cc64fbd5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=622384868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.622384868
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1945825978
Short name T587
Test name
Test status
Simulation time 7393678540 ps
CPU time 4.03 seconds
Started May 26 02:14:54 PM PDT 24
Finished May 26 02:14:59 PM PDT 24
Peak memory 199524 kb
Host smart-a51ed748-f7e1-499b-911f-249782882abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945825978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1945825978
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3950375117
Short name T949
Test name
Test status
Simulation time 169667839460 ps
CPU time 73.47 seconds
Started May 26 02:14:55 PM PDT 24
Finished May 26 02:16:09 PM PDT 24
Peak memory 200068 kb
Host smart-2056a238-b34d-49af-afec-c9acf60f1674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950375117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3950375117
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.155428843
Short name T265
Test name
Test status
Simulation time 5893590339 ps
CPU time 166.07 seconds
Started May 26 02:14:55 PM PDT 24
Finished May 26 02:17:42 PM PDT 24
Peak memory 200560 kb
Host smart-eedd4ee5-b6c3-400c-889b-5e42c8776f85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=155428843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.155428843
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3553165652
Short name T483
Test name
Test status
Simulation time 1818623333 ps
CPU time 2.75 seconds
Started May 26 02:14:55 PM PDT 24
Finished May 26 02:14:58 PM PDT 24
Peak memory 198364 kb
Host smart-f0044401-7fc9-4ee4-a48e-f221cf149193
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3553165652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3553165652
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1122065309
Short name T772
Test name
Test status
Simulation time 117565593181 ps
CPU time 32.61 seconds
Started May 26 02:14:56 PM PDT 24
Finished May 26 02:15:29 PM PDT 24
Peak memory 200476 kb
Host smart-264dbae2-8de9-47dd-8ecd-57e41d149d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122065309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1122065309
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1235431212
Short name T534
Test name
Test status
Simulation time 5489029744 ps
CPU time 2.11 seconds
Started May 26 02:14:55 PM PDT 24
Finished May 26 02:14:58 PM PDT 24
Peak memory 196792 kb
Host smart-40d2947a-143b-43ff-ab69-2ac075a8d46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235431212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1235431212
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3054585320
Short name T933
Test name
Test status
Simulation time 5362500262 ps
CPU time 11.26 seconds
Started May 26 02:14:54 PM PDT 24
Finished May 26 02:15:07 PM PDT 24
Peak memory 199692 kb
Host smart-cf52ad91-e197-40fb-abc9-4cf287c3c17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054585320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3054585320
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.2186027698
Short name T164
Test name
Test status
Simulation time 594711606726 ps
CPU time 366.51 seconds
Started May 26 02:15:03 PM PDT 24
Finished May 26 02:21:11 PM PDT 24
Peak memory 209032 kb
Host smart-ba5807d5-f5fe-405d-b266-8a695a8ba283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186027698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2186027698
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.820057159
Short name T950
Test name
Test status
Simulation time 682329211627 ps
CPU time 641.31 seconds
Started May 26 02:14:55 PM PDT 24
Finished May 26 02:25:37 PM PDT 24
Peak memory 225496 kb
Host smart-7a89eee7-d892-47ef-89df-b81b512ae180
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820057159 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.820057159
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1733280003
Short name T778
Test name
Test status
Simulation time 6237689705 ps
CPU time 10.31 seconds
Started May 26 02:14:54 PM PDT 24
Finished May 26 02:15:06 PM PDT 24
Peak memory 200252 kb
Host smart-0ed934a1-91e7-4f4c-93c7-61d6989bc36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733280003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1733280003
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3931254211
Short name T273
Test name
Test status
Simulation time 67064511834 ps
CPU time 53.23 seconds
Started May 26 02:14:53 PM PDT 24
Finished May 26 02:15:47 PM PDT 24
Peak memory 200472 kb
Host smart-cb2acdec-7ccb-4f0c-9103-612ba9618cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931254211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3931254211
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1299396013
Short name T903
Test name
Test status
Simulation time 37203728 ps
CPU time 0.57 seconds
Started May 26 02:15:04 PM PDT 24
Finished May 26 02:15:07 PM PDT 24
Peak memory 195924 kb
Host smart-46f1a052-b6ec-4589-ae49-da5a2ec4e31c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299396013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1299396013
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.97500396
Short name T148
Test name
Test status
Simulation time 55367020574 ps
CPU time 53.27 seconds
Started May 26 02:15:05 PM PDT 24
Finished May 26 02:16:00 PM PDT 24
Peak memory 200560 kb
Host smart-7380cdae-b8b4-4e9c-92a0-439df0a1dc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97500396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.97500396
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2203692226
Short name T565
Test name
Test status
Simulation time 205673849019 ps
CPU time 265.2 seconds
Started May 26 02:15:04 PM PDT 24
Finished May 26 02:19:31 PM PDT 24
Peak memory 200468 kb
Host smart-7ca5431f-b2c2-4953-b538-c18bc7f821c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203692226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2203692226
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2239586080
Short name T632
Test name
Test status
Simulation time 10346944700 ps
CPU time 13.89 seconds
Started May 26 02:15:04 PM PDT 24
Finished May 26 02:15:20 PM PDT 24
Peak memory 200492 kb
Host smart-d083d299-1576-4ea7-9a3a-3aae9b9a00c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239586080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2239586080
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.620475856
Short name T989
Test name
Test status
Simulation time 72986057189 ps
CPU time 30.59 seconds
Started May 26 02:15:06 PM PDT 24
Finished May 26 02:15:38 PM PDT 24
Peak memory 200560 kb
Host smart-30781b61-4b1f-45d8-80ea-6bb3390487fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620475856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.620475856
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.299045735
Short name T666
Test name
Test status
Simulation time 78860129356 ps
CPU time 854.35 seconds
Started May 26 02:15:03 PM PDT 24
Finished May 26 02:29:19 PM PDT 24
Peak memory 200492 kb
Host smart-464c79f4-d198-4957-859a-a0d936fe9c35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=299045735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.299045735
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1570469171
Short name T793
Test name
Test status
Simulation time 4906206826 ps
CPU time 13.87 seconds
Started May 26 02:15:05 PM PDT 24
Finished May 26 02:15:21 PM PDT 24
Peak memory 199572 kb
Host smart-f2bda640-dd73-43e4-928c-3f3b947b8157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570469171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1570469171
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.4155240105
Short name T342
Test name
Test status
Simulation time 17717211235 ps
CPU time 16.5 seconds
Started May 26 02:15:05 PM PDT 24
Finished May 26 02:15:23 PM PDT 24
Peak memory 195192 kb
Host smart-3dab5156-9ba8-4fa6-8bd2-f7159af0de00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155240105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.4155240105
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3185772767
Short name T53
Test name
Test status
Simulation time 18481289240 ps
CPU time 145.85 seconds
Started May 26 02:15:05 PM PDT 24
Finished May 26 02:17:33 PM PDT 24
Peak memory 200448 kb
Host smart-b552616d-6a43-4485-af05-1fd701092a9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3185772767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3185772767
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3646314168
Short name T669
Test name
Test status
Simulation time 5187015750 ps
CPU time 10.22 seconds
Started May 26 02:15:07 PM PDT 24
Finished May 26 02:15:18 PM PDT 24
Peak memory 199856 kb
Host smart-c9180383-17ef-457e-8429-f892a53209d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646314168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3646314168
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.709079644
Short name T277
Test name
Test status
Simulation time 152848664304 ps
CPU time 194.3 seconds
Started May 26 02:15:02 PM PDT 24
Finished May 26 02:18:18 PM PDT 24
Peak memory 200500 kb
Host smart-e8ebfbaf-64b3-4f23-aa02-0d3da7b7f155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709079644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.709079644
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3635118525
Short name T809
Test name
Test status
Simulation time 42323857221 ps
CPU time 18.9 seconds
Started May 26 02:15:05 PM PDT 24
Finished May 26 02:15:26 PM PDT 24
Peak memory 196548 kb
Host smart-51da9373-4035-4f35-88e5-9df1a74df67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635118525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3635118525
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3555361375
Short name T320
Test name
Test status
Simulation time 678307867 ps
CPU time 1.95 seconds
Started May 26 02:15:06 PM PDT 24
Finished May 26 02:15:09 PM PDT 24
Peak memory 199128 kb
Host smart-c844a521-e028-4092-aa50-d9242d6af032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555361375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3555361375
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1613345031
Short name T1114
Test name
Test status
Simulation time 769621749443 ps
CPU time 579.87 seconds
Started May 26 02:15:07 PM PDT 24
Finished May 26 02:24:49 PM PDT 24
Peak memory 209060 kb
Host smart-d3a1bd94-5a26-4273-9e22-37378805221d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613345031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1613345031
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2086502809
Short name T26
Test name
Test status
Simulation time 94972147251 ps
CPU time 280.71 seconds
Started May 26 02:15:04 PM PDT 24
Finished May 26 02:19:46 PM PDT 24
Peak memory 209560 kb
Host smart-82bbb65e-3bc5-4bd1-84ed-3d6bdf077274
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086502809 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2086502809
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2949532783
Short name T1146
Test name
Test status
Simulation time 7112934531 ps
CPU time 9.59 seconds
Started May 26 02:15:06 PM PDT 24
Finished May 26 02:15:17 PM PDT 24
Peak memory 200520 kb
Host smart-e9209b08-39ea-4536-a0d9-4d1a67078894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949532783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2949532783
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1252781862
Short name T906
Test name
Test status
Simulation time 44492751258 ps
CPU time 72.06 seconds
Started May 26 02:15:04 PM PDT 24
Finished May 26 02:16:18 PM PDT 24
Peak memory 200548 kb
Host smart-8da2338d-640a-4106-be2f-3ab7e36627bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252781862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1252781862
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1480385489
Short name T388
Test name
Test status
Simulation time 13286041 ps
CPU time 0.6 seconds
Started May 26 02:15:04 PM PDT 24
Finished May 26 02:15:07 PM PDT 24
Peak memory 195924 kb
Host smart-234d5c6a-6686-4346-89a6-e33a21b4e003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480385489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1480385489
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3527913867
Short name T153
Test name
Test status
Simulation time 148409967471 ps
CPU time 62.28 seconds
Started May 26 02:15:03 PM PDT 24
Finished May 26 02:16:06 PM PDT 24
Peak memory 200476 kb
Host smart-220dfe4b-5f8f-4f41-8e04-caa7a47352f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527913867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3527913867
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3018382773
Short name T143
Test name
Test status
Simulation time 79238212098 ps
CPU time 64.58 seconds
Started May 26 02:15:07 PM PDT 24
Finished May 26 02:16:13 PM PDT 24
Peak memory 200444 kb
Host smart-e34eaeb3-9bd2-46a1-afc9-b5ac45725e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018382773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3018382773
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1289117220
Short name T451
Test name
Test status
Simulation time 30943573118 ps
CPU time 24.75 seconds
Started May 26 02:15:07 PM PDT 24
Finished May 26 02:15:33 PM PDT 24
Peak memory 200508 kb
Host smart-e9b19500-16fb-469e-a308-21e2aa7398e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289117220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1289117220
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3216767922
Short name T794
Test name
Test status
Simulation time 84893916060 ps
CPU time 48.11 seconds
Started May 26 02:15:04 PM PDT 24
Finished May 26 02:15:54 PM PDT 24
Peak memory 200244 kb
Host smart-c5d0adb4-270a-45f5-9e8e-4595f5570e20
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216767922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3216767922
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3037661509
Short name T979
Test name
Test status
Simulation time 295939061752 ps
CPU time 437.31 seconds
Started May 26 02:15:03 PM PDT 24
Finished May 26 02:22:22 PM PDT 24
Peak memory 200552 kb
Host smart-29f48f0e-0cb4-4af2-b173-4802ac51e9ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037661509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3037661509
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.974040342
Short name T943
Test name
Test status
Simulation time 3893894134 ps
CPU time 1.96 seconds
Started May 26 02:15:02 PM PDT 24
Finished May 26 02:15:06 PM PDT 24
Peak memory 197836 kb
Host smart-8ffc87ea-9fa0-4a55-96db-12d2003e6fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974040342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.974040342
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2127595315
Short name T851
Test name
Test status
Simulation time 2188930738 ps
CPU time 4.52 seconds
Started May 26 02:15:05 PM PDT 24
Finished May 26 02:15:12 PM PDT 24
Peak memory 197712 kb
Host smart-5edf3fc8-bd02-436e-a7ee-12136282eae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127595315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2127595315
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3408322324
Short name T626
Test name
Test status
Simulation time 18989322272 ps
CPU time 921.28 seconds
Started May 26 02:15:04 PM PDT 24
Finished May 26 02:30:27 PM PDT 24
Peak memory 200668 kb
Host smart-37ae588a-1fe9-4a0a-b104-d12025c2e38d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3408322324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3408322324
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1106866418
Short name T416
Test name
Test status
Simulation time 1661699677 ps
CPU time 1.14 seconds
Started May 26 02:15:07 PM PDT 24
Finished May 26 02:15:09 PM PDT 24
Peak memory 198984 kb
Host smart-674d217c-6e5c-46cb-a626-8774b4783915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106866418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1106866418
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.4269783255
Short name T1177
Test name
Test status
Simulation time 298762928750 ps
CPU time 79.97 seconds
Started May 26 02:15:09 PM PDT 24
Finished May 26 02:16:29 PM PDT 24
Peak memory 200512 kb
Host smart-7e11f080-04a6-41a9-aada-1f6bec839a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269783255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.4269783255
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.98677920
Short name T362
Test name
Test status
Simulation time 2257387286 ps
CPU time 1.65 seconds
Started May 26 02:15:07 PM PDT 24
Finished May 26 02:15:10 PM PDT 24
Peak memory 195968 kb
Host smart-2729cd21-2171-4fae-a558-3c61c8ee006c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98677920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.98677920
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2955412156
Short name T292
Test name
Test status
Simulation time 710351342 ps
CPU time 2.08 seconds
Started May 26 02:15:06 PM PDT 24
Finished May 26 02:15:10 PM PDT 24
Peak memory 199452 kb
Host smart-e9c0d49d-5a19-42ed-8952-7829b5097bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955412156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2955412156
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.194476678
Short name T350
Test name
Test status
Simulation time 555214788935 ps
CPU time 233.72 seconds
Started May 26 02:15:07 PM PDT 24
Finished May 26 02:19:02 PM PDT 24
Peak memory 216644 kb
Host smart-fc9f3b91-ee2b-4a2e-a434-e46ae8573329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194476678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.194476678
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.280045383
Short name T209
Test name
Test status
Simulation time 175422956502 ps
CPU time 806.49 seconds
Started May 26 02:15:03 PM PDT 24
Finished May 26 02:28:31 PM PDT 24
Peak memory 225468 kb
Host smart-8d232465-5c16-4f53-a893-6b0ce022dd55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280045383 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.280045383
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3439406256
Short name T560
Test name
Test status
Simulation time 859506886 ps
CPU time 2.06 seconds
Started May 26 02:15:03 PM PDT 24
Finished May 26 02:15:07 PM PDT 24
Peak memory 199208 kb
Host smart-8d0e5541-e6d5-4c7d-981a-b29c771783d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439406256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3439406256
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.541262634
Short name T976
Test name
Test status
Simulation time 56609761710 ps
CPU time 34.31 seconds
Started May 26 02:15:04 PM PDT 24
Finished May 26 02:15:40 PM PDT 24
Peak memory 200560 kb
Host smart-ce159052-8ae1-4a88-b22c-acb661dc779c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541262634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.541262634
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.858410956
Short name T428
Test name
Test status
Simulation time 43177150 ps
CPU time 0.55 seconds
Started May 26 02:12:51 PM PDT 24
Finished May 26 02:12:53 PM PDT 24
Peak memory 194876 kb
Host smart-b864e59e-0a54-4292-8017-e0316870e68a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858410956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.858410956
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1348536795
Short name T786
Test name
Test status
Simulation time 50381944880 ps
CPU time 77.6 seconds
Started May 26 02:12:55 PM PDT 24
Finished May 26 02:14:14 PM PDT 24
Peak memory 200560 kb
Host smart-1c9a152b-dd63-4bf6-b147-14b8d806d1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348536795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1348536795
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3054966328
Short name T430
Test name
Test status
Simulation time 120410684699 ps
CPU time 15.42 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:13:10 PM PDT 24
Peak memory 200488 kb
Host smart-ebcb4a56-f925-4f68-a99b-573a2ce84be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054966328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3054966328
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1061553765
Short name T915
Test name
Test status
Simulation time 40853562883 ps
CPU time 65.54 seconds
Started May 26 02:12:54 PM PDT 24
Finished May 26 02:14:01 PM PDT 24
Peak memory 200572 kb
Host smart-d06f1f2e-b344-4a06-beef-d610c8296d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061553765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1061553765
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.997556656
Short name T1
Test name
Test status
Simulation time 20961294160 ps
CPU time 8.65 seconds
Started May 26 02:12:49 PM PDT 24
Finished May 26 02:12:58 PM PDT 24
Peak memory 198300 kb
Host smart-569ae3e6-04c0-4f5a-9cf7-baf8f44f9ef3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997556656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.997556656
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2180440179
Short name T279
Test name
Test status
Simulation time 69338450737 ps
CPU time 284.06 seconds
Started May 26 02:12:51 PM PDT 24
Finished May 26 02:17:37 PM PDT 24
Peak memory 200504 kb
Host smart-ee60fefd-de4f-4322-95d5-e6b2d6c96ae5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2180440179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2180440179
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2449354117
Short name T459
Test name
Test status
Simulation time 10242658003 ps
CPU time 6.53 seconds
Started May 26 02:12:57 PM PDT 24
Finished May 26 02:13:04 PM PDT 24
Peak memory 200568 kb
Host smart-80c60e5b-15d0-49fd-9120-a4d6b4b9018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449354117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2449354117
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.972978107
Short name T9
Test name
Test status
Simulation time 46344547759 ps
CPU time 43.08 seconds
Started May 26 02:12:50 PM PDT 24
Finished May 26 02:13:34 PM PDT 24
Peak memory 200748 kb
Host smart-8d8f710e-7b7a-4127-b30c-c23cc418d1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972978107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.972978107
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2990904724
Short name T313
Test name
Test status
Simulation time 14894626634 ps
CPU time 653.93 seconds
Started May 26 02:12:52 PM PDT 24
Finished May 26 02:23:47 PM PDT 24
Peak memory 200516 kb
Host smart-3ec8c9f9-8694-48af-ac57-b7d4b5043425
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2990904724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2990904724
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.920596301
Short name T647
Test name
Test status
Simulation time 6101744703 ps
CPU time 53.37 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:13:48 PM PDT 24
Peak memory 199312 kb
Host smart-85b603a0-9a37-4292-897a-bdbb89ce1bf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920596301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.920596301
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3788769604
Short name T506
Test name
Test status
Simulation time 133216853433 ps
CPU time 77.49 seconds
Started May 26 02:12:52 PM PDT 24
Finished May 26 02:14:12 PM PDT 24
Peak memory 200520 kb
Host smart-c04acbaa-4ae6-4398-8ca1-d74de5583abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788769604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3788769604
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2857995166
Short name T854
Test name
Test status
Simulation time 2902070518 ps
CPU time 3.08 seconds
Started May 26 02:12:54 PM PDT 24
Finished May 26 02:12:59 PM PDT 24
Peak memory 196268 kb
Host smart-9f722f1d-9848-4216-8800-0d282ced3983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857995166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2857995166
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2875766114
Short name T103
Test name
Test status
Simulation time 109396469 ps
CPU time 0.89 seconds
Started May 26 02:12:51 PM PDT 24
Finished May 26 02:12:54 PM PDT 24
Peak memory 219096 kb
Host smart-714797e7-b478-4248-bd87-d89daffd818c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875766114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2875766114
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2503734297
Short name T750
Test name
Test status
Simulation time 562319886 ps
CPU time 2.67 seconds
Started May 26 02:12:51 PM PDT 24
Finished May 26 02:12:54 PM PDT 24
Peak memory 198884 kb
Host smart-7e176296-e8c4-4fab-b133-7899285c1605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503734297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2503734297
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.1963047501
Short name T323
Test name
Test status
Simulation time 228241961757 ps
CPU time 733.46 seconds
Started May 26 02:12:50 PM PDT 24
Finished May 26 02:25:05 PM PDT 24
Peak memory 200500 kb
Host smart-35cbe415-107f-4811-b13e-e8663dafe43b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963047501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1963047501
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3127487489
Short name T1002
Test name
Test status
Simulation time 68003365292 ps
CPU time 383.75 seconds
Started May 26 02:12:51 PM PDT 24
Finished May 26 02:19:15 PM PDT 24
Peak memory 216196 kb
Host smart-d8a68654-477a-4716-9690-525f28ed3a97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127487489 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3127487489
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1789178131
Short name T1105
Test name
Test status
Simulation time 559260761 ps
CPU time 2.36 seconds
Started May 26 02:12:50 PM PDT 24
Finished May 26 02:12:53 PM PDT 24
Peak memory 199336 kb
Host smart-428a6782-ebd4-4aff-8749-1551f9168023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789178131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1789178131
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2601292115
Short name T1070
Test name
Test status
Simulation time 61877197888 ps
CPU time 24.71 seconds
Started May 26 02:12:51 PM PDT 24
Finished May 26 02:13:16 PM PDT 24
Peak memory 200468 kb
Host smart-ba165e31-97ce-4f34-9a9e-6dcd8dfc4ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601292115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2601292115
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2406851294
Short name T728
Test name
Test status
Simulation time 67712910 ps
CPU time 0.57 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:15:22 PM PDT 24
Peak memory 195288 kb
Host smart-0a184440-ca7a-49da-ac27-018b7ae637e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406851294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2406851294
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.4111844095
Short name T923
Test name
Test status
Simulation time 181091220304 ps
CPU time 51.74 seconds
Started May 26 02:15:05 PM PDT 24
Finished May 26 02:15:58 PM PDT 24
Peak memory 200512 kb
Host smart-81dd2985-e50d-4d06-9486-b46209ee04f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111844095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.4111844095
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.660554813
Short name T1056
Test name
Test status
Simulation time 47246499861 ps
CPU time 31.83 seconds
Started May 26 02:15:12 PM PDT 24
Finished May 26 02:15:45 PM PDT 24
Peak memory 200476 kb
Host smart-f3f6bb5c-2680-4179-8fe8-655c0737ee70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660554813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.660554813
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3693434292
Short name T10
Test name
Test status
Simulation time 24556844196 ps
CPU time 27.42 seconds
Started May 26 02:15:14 PM PDT 24
Finished May 26 02:15:42 PM PDT 24
Peak memory 200116 kb
Host smart-d13c3b11-bb1e-450b-a9f1-4aa7012e4a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693434292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3693434292
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3242704420
Short name T1020
Test name
Test status
Simulation time 51789096722 ps
CPU time 25.5 seconds
Started May 26 02:15:12 PM PDT 24
Finished May 26 02:15:38 PM PDT 24
Peak memory 200540 kb
Host smart-124bd0f9-eb12-4ba2-b818-b714af3a5a59
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242704420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3242704420
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2708763736
Short name T559
Test name
Test status
Simulation time 115053457672 ps
CPU time 390.42 seconds
Started May 26 02:15:13 PM PDT 24
Finished May 26 02:21:44 PM PDT 24
Peak memory 200480 kb
Host smart-890bf613-cd9d-4a51-8ff6-6205a3958e4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2708763736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2708763736
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3107094858
Short name T628
Test name
Test status
Simulation time 11148933170 ps
CPU time 4.28 seconds
Started May 26 02:15:14 PM PDT 24
Finished May 26 02:15:19 PM PDT 24
Peak memory 199944 kb
Host smart-ce70cfb3-29a7-4014-9c35-bd758f3e2407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107094858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3107094858
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.289623179
Short name T841
Test name
Test status
Simulation time 36876926279 ps
CPU time 65.31 seconds
Started May 26 02:15:11 PM PDT 24
Finished May 26 02:16:17 PM PDT 24
Peak memory 200736 kb
Host smart-f9843156-d0f6-41e8-8991-9edf2b30de2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289623179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.289623179
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3519954217
Short name T125
Test name
Test status
Simulation time 11805501469 ps
CPU time 344.02 seconds
Started May 26 02:15:11 PM PDT 24
Finished May 26 02:20:56 PM PDT 24
Peak memory 200472 kb
Host smart-441d16b6-32c5-4013-bfac-dbe1aad4daf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3519954217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3519954217
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.727567911
Short name T520
Test name
Test status
Simulation time 6305415521 ps
CPU time 58.56 seconds
Started May 26 02:15:13 PM PDT 24
Finished May 26 02:16:12 PM PDT 24
Peak memory 199756 kb
Host smart-2d9a0c43-fa3d-4e65-b0b0-b8b4bca45157
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=727567911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.727567911
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3100715621
Short name T917
Test name
Test status
Simulation time 20829802946 ps
CPU time 9.92 seconds
Started May 26 02:15:12 PM PDT 24
Finished May 26 02:15:23 PM PDT 24
Peak memory 199980 kb
Host smart-cc3fefcb-750d-4c0e-97c1-211aac5975eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100715621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3100715621
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.240813604
Short name T827
Test name
Test status
Simulation time 6789584451 ps
CPU time 11.42 seconds
Started May 26 02:15:15 PM PDT 24
Finished May 26 02:15:27 PM PDT 24
Peak memory 196520 kb
Host smart-ff6b915c-0676-4c3a-bb05-965fcc8188fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240813604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.240813604
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3755701510
Short name T532
Test name
Test status
Simulation time 844170008 ps
CPU time 3.4 seconds
Started May 26 02:15:03 PM PDT 24
Finished May 26 02:15:08 PM PDT 24
Peak memory 200036 kb
Host smart-fbebeb5d-e1c5-49b7-92d2-90a39835da13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755701510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3755701510
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.444146871
Short name T1106
Test name
Test status
Simulation time 107735402110 ps
CPU time 50.65 seconds
Started May 26 02:15:11 PM PDT 24
Finished May 26 02:16:03 PM PDT 24
Peak memory 200476 kb
Host smart-dd4c8698-4145-4993-b7fd-b3128c1a4a9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444146871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.444146871
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.4224083926
Short name T1175
Test name
Test status
Simulation time 336468239205 ps
CPU time 354.74 seconds
Started May 26 02:15:13 PM PDT 24
Finished May 26 02:21:09 PM PDT 24
Peak memory 217404 kb
Host smart-baaffc46-af01-4352-a0d2-6aabc6c1c961
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224083926 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.4224083926
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1034200394
Short name T526
Test name
Test status
Simulation time 1082109051 ps
CPU time 3.68 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:15:25 PM PDT 24
Peak memory 198924 kb
Host smart-b89d093c-8d03-487f-a80c-300d10d1f65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034200394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1034200394
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1192342853
Short name T473
Test name
Test status
Simulation time 67294111188 ps
CPU time 56.87 seconds
Started May 26 02:15:04 PM PDT 24
Finished May 26 02:16:03 PM PDT 24
Peak memory 200464 kb
Host smart-d8819bb6-1277-438a-a2cc-ebc5c7025ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192342853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1192342853
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1282766601
Short name T1013
Test name
Test status
Simulation time 23228767 ps
CPU time 0.55 seconds
Started May 26 02:15:11 PM PDT 24
Finished May 26 02:15:13 PM PDT 24
Peak memory 195296 kb
Host smart-12a98d0b-e706-40c0-93dc-d948c5805929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282766601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1282766601
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.856818313
Short name T499
Test name
Test status
Simulation time 51406386002 ps
CPU time 79.66 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:16:41 PM PDT 24
Peak memory 200444 kb
Host smart-4c750ffa-98ab-4482-821c-85f5cddc11fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856818313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.856818313
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2310042267
Short name T45
Test name
Test status
Simulation time 92904842608 ps
CPU time 34.28 seconds
Started May 26 02:15:14 PM PDT 24
Finished May 26 02:15:49 PM PDT 24
Peak memory 200500 kb
Host smart-019945b8-2388-4a07-bb43-e43d71d76ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310042267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2310042267
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3965543541
Short name T377
Test name
Test status
Simulation time 50282212122 ps
CPU time 31.3 seconds
Started May 26 02:15:12 PM PDT 24
Finished May 26 02:15:45 PM PDT 24
Peak memory 200552 kb
Host smart-54e81f07-0fad-44b3-8721-525db5ba1823
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965543541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3965543541
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.709650768
Short name T408
Test name
Test status
Simulation time 115341952821 ps
CPU time 447.07 seconds
Started May 26 02:15:12 PM PDT 24
Finished May 26 02:22:40 PM PDT 24
Peak memory 200560 kb
Host smart-130a83e4-7079-43b6-ac34-65478b9e1ae9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709650768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.709650768
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1190263339
Short name T694
Test name
Test status
Simulation time 9681622946 ps
CPU time 17.97 seconds
Started May 26 02:15:11 PM PDT 24
Finished May 26 02:15:30 PM PDT 24
Peak memory 200228 kb
Host smart-23a1c786-a700-478f-ae5f-400e633a1b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190263339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1190263339
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2970776481
Short name T298
Test name
Test status
Simulation time 59770381376 ps
CPU time 114.48 seconds
Started May 26 02:15:12 PM PDT 24
Finished May 26 02:17:07 PM PDT 24
Peak memory 200812 kb
Host smart-34189cca-a432-47a0-bda4-7d35fadab006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970776481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2970776481
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.556737576
Short name T1032
Test name
Test status
Simulation time 21509531845 ps
CPU time 1274.21 seconds
Started May 26 02:15:12 PM PDT 24
Finished May 26 02:36:28 PM PDT 24
Peak memory 200488 kb
Host smart-5186b12f-e5a2-449e-81aa-4d9774f3a6d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=556737576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.556737576
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.232326684
Short name T621
Test name
Test status
Simulation time 1592971649 ps
CPU time 9 seconds
Started May 26 02:15:12 PM PDT 24
Finished May 26 02:15:22 PM PDT 24
Peak memory 198720 kb
Host smart-e6a66be6-62ef-484e-8467-a05cf195a9a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232326684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.232326684
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.4126944834
Short name T810
Test name
Test status
Simulation time 100336271820 ps
CPU time 44.86 seconds
Started May 26 02:15:14 PM PDT 24
Finished May 26 02:15:59 PM PDT 24
Peak memory 200468 kb
Host smart-317415b9-c8a0-49a6-8b34-62e1114a2cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126944834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.4126944834
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2359834451
Short name T722
Test name
Test status
Simulation time 33833449141 ps
CPU time 25.98 seconds
Started May 26 02:15:14 PM PDT 24
Finished May 26 02:15:41 PM PDT 24
Peak memory 196552 kb
Host smart-fd3770f8-2d49-4e6a-9252-bd6e854afe69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359834451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2359834451
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.301423565
Short name T849
Test name
Test status
Simulation time 5366561948 ps
CPU time 9.19 seconds
Started May 26 02:15:13 PM PDT 24
Finished May 26 02:15:23 PM PDT 24
Peak memory 200384 kb
Host smart-5db0e856-a18e-41a5-b87e-466ed6335d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301423565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.301423565
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.830763525
Short name T709
Test name
Test status
Simulation time 191469054959 ps
CPU time 426.3 seconds
Started May 26 02:15:10 PM PDT 24
Finished May 26 02:22:17 PM PDT 24
Peak memory 200520 kb
Host smart-0277cc9c-1793-41cc-bd3e-3c046d95badd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830763525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.830763525
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3842218967
Short name T821
Test name
Test status
Simulation time 39431125714 ps
CPU time 279.79 seconds
Started May 26 02:15:14 PM PDT 24
Finished May 26 02:19:54 PM PDT 24
Peak memory 216260 kb
Host smart-2f12d51d-25b6-4960-897a-3ac6f1fbf669
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842218967 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3842218967
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3280738421
Short name T631
Test name
Test status
Simulation time 573435705 ps
CPU time 1.73 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:15:23 PM PDT 24
Peak memory 198704 kb
Host smart-6c860c25-5214-4dbf-a64e-877beecf14c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280738421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3280738421
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.541939823
Short name T612
Test name
Test status
Simulation time 137668592299 ps
CPU time 59.21 seconds
Started May 26 02:15:14 PM PDT 24
Finished May 26 02:16:14 PM PDT 24
Peak memory 200500 kb
Host smart-58b6b8c2-94ed-46b5-98e9-06c7c21edaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541939823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.541939823
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.722122021
Short name T117
Test name
Test status
Simulation time 19517441 ps
CPU time 0.57 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:15:22 PM PDT 24
Peak memory 195920 kb
Host smart-efcbfcde-49a7-40d2-8204-9b63f7e9af8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722122021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.722122021
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1520149201
Short name T1053
Test name
Test status
Simulation time 125014215629 ps
CPU time 209.09 seconds
Started May 26 02:15:17 PM PDT 24
Finished May 26 02:18:46 PM PDT 24
Peak memory 200324 kb
Host smart-14890fce-7b0d-4fea-8373-886d939cd885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520149201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1520149201
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1041838690
Short name T698
Test name
Test status
Simulation time 14348188006 ps
CPU time 6.91 seconds
Started May 26 02:15:17 PM PDT 24
Finished May 26 02:15:24 PM PDT 24
Peak memory 200400 kb
Host smart-806904f7-a7ad-4e6c-b924-d901f7eec511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041838690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1041838690
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3185261020
Short name T237
Test name
Test status
Simulation time 64197546001 ps
CPU time 25.64 seconds
Started May 26 02:15:19 PM PDT 24
Finished May 26 02:15:45 PM PDT 24
Peak memory 200524 kb
Host smart-f3f723a1-2866-42e2-93ab-f12473d64833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185261020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3185261020
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3704649630
Short name T717
Test name
Test status
Simulation time 14307887298 ps
CPU time 21.83 seconds
Started May 26 02:15:19 PM PDT 24
Finished May 26 02:15:41 PM PDT 24
Peak memory 197580 kb
Host smart-f473376e-c677-4e6b-925d-e3488142be48
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704649630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3704649630
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3849689804
Short name T124
Test name
Test status
Simulation time 386727176750 ps
CPU time 240.7 seconds
Started May 26 02:15:18 PM PDT 24
Finished May 26 02:19:19 PM PDT 24
Peak memory 200536 kb
Host smart-5cfb3da3-0754-4684-a60f-70dc81320d55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849689804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3849689804
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3200064922
Short name T1057
Test name
Test status
Simulation time 7930485835 ps
CPU time 16.94 seconds
Started May 26 02:15:18 PM PDT 24
Finished May 26 02:15:35 PM PDT 24
Peak memory 200464 kb
Host smart-32a6aded-ef34-43ac-b279-0032b755039f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200064922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3200064922
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3970899000
Short name T988
Test name
Test status
Simulation time 251170862800 ps
CPU time 58.34 seconds
Started May 26 02:15:21 PM PDT 24
Finished May 26 02:16:20 PM PDT 24
Peak memory 200840 kb
Host smart-3c0f8c1e-8e1d-47fa-9e23-293ea19f2663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970899000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3970899000
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2989494635
Short name T603
Test name
Test status
Simulation time 21393520960 ps
CPU time 583.48 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:25:05 PM PDT 24
Peak memory 200652 kb
Host smart-d21a7b4d-d840-464b-ac1c-4f867334e470
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2989494635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2989494635
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3376196664
Short name T47
Test name
Test status
Simulation time 7606463435 ps
CPU time 64.37 seconds
Started May 26 02:15:19 PM PDT 24
Finished May 26 02:16:25 PM PDT 24
Peak memory 199848 kb
Host smart-7446af90-63d2-4458-9abd-86104783ed9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3376196664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3376196664
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1328247210
Short name T984
Test name
Test status
Simulation time 30979373017 ps
CPU time 14.56 seconds
Started May 26 02:15:22 PM PDT 24
Finished May 26 02:15:37 PM PDT 24
Peak memory 200236 kb
Host smart-dcaf6f81-ddc7-4f51-9eb9-614f0560b54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328247210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1328247210
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.2008878300
Short name T1042
Test name
Test status
Simulation time 29578342475 ps
CPU time 8.16 seconds
Started May 26 02:15:19 PM PDT 24
Finished May 26 02:15:28 PM PDT 24
Peak memory 196452 kb
Host smart-f9eff83b-7034-4879-a52f-f2e7b8cfe591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008878300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2008878300
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1017978172
Short name T1065
Test name
Test status
Simulation time 554368302 ps
CPU time 2.19 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:15:24 PM PDT 24
Peak memory 200076 kb
Host smart-38e2cabf-132a-4205-ac10-160218e4b698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017978172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1017978172
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.296946590
Short name T691
Test name
Test status
Simulation time 192084388387 ps
CPU time 411.68 seconds
Started May 26 02:15:19 PM PDT 24
Finished May 26 02:22:11 PM PDT 24
Peak memory 209044 kb
Host smart-5394b8c8-7fad-478e-89fe-c0306419144a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296946590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.296946590
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1197733257
Short name T42
Test name
Test status
Simulation time 23038590745 ps
CPU time 319.5 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:20:41 PM PDT 24
Peak memory 216340 kb
Host smart-65bf9be1-debc-4f95-820a-2922df16dbcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197733257 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1197733257
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1790395769
Short name T503
Test name
Test status
Simulation time 12477588440 ps
CPU time 42.15 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:16:04 PM PDT 24
Peak memory 200464 kb
Host smart-61ca6e76-3e25-47a7-8297-a4c6ed0b36e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790395769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1790395769
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3064002011
Short name T493
Test name
Test status
Simulation time 24475407757 ps
CPU time 21.58 seconds
Started May 26 02:15:17 PM PDT 24
Finished May 26 02:15:39 PM PDT 24
Peak memory 199600 kb
Host smart-cd533385-da50-4e7d-b6c6-e569e0e87b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064002011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3064002011
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1555825021
Short name T487
Test name
Test status
Simulation time 23457246 ps
CPU time 0.57 seconds
Started May 26 02:15:18 PM PDT 24
Finished May 26 02:15:19 PM PDT 24
Peak memory 195920 kb
Host smart-cb43db4e-7d27-4fd6-9dcd-e8e603d828aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555825021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1555825021
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2387555507
Short name T376
Test name
Test status
Simulation time 40110128912 ps
CPU time 63.64 seconds
Started May 26 02:15:19 PM PDT 24
Finished May 26 02:16:23 PM PDT 24
Peak memory 200480 kb
Host smart-71803219-c442-4006-be7e-a764da202aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387555507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2387555507
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.761216106
Short name T285
Test name
Test status
Simulation time 40045099376 ps
CPU time 17.14 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:15:39 PM PDT 24
Peak memory 198912 kb
Host smart-73beba43-de4b-4da6-94cb-35b27937215f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761216106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.761216106
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1798268469
Short name T767
Test name
Test status
Simulation time 17561348254 ps
CPU time 36.96 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:15:58 PM PDT 24
Peak memory 200492 kb
Host smart-a030ec54-11ec-4712-ad74-4755543be8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798268469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1798268469
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.506422943
Short name T615
Test name
Test status
Simulation time 43683245705 ps
CPU time 35.85 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:15:58 PM PDT 24
Peak memory 199472 kb
Host smart-f355657c-3723-4a3f-a10a-6f510a2be95f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506422943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.506422943
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1714518367
Short name T406
Test name
Test status
Simulation time 96843824063 ps
CPU time 225.32 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:19:07 PM PDT 24
Peak memory 200588 kb
Host smart-54630659-d537-45d7-a6b3-1cbd73016bee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1714518367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1714518367
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2673019103
Short name T1022
Test name
Test status
Simulation time 11047879946 ps
CPU time 19.69 seconds
Started May 26 02:15:19 PM PDT 24
Finished May 26 02:15:40 PM PDT 24
Peak memory 200532 kb
Host smart-9f1718f4-af09-425f-8264-62378d748238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673019103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2673019103
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3216747046
Short name T1161
Test name
Test status
Simulation time 56167987635 ps
CPU time 50.63 seconds
Started May 26 02:15:19 PM PDT 24
Finished May 26 02:16:11 PM PDT 24
Peak memory 199528 kb
Host smart-f312dfa9-2c5c-4677-9b8a-0330a47ffb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216747046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3216747046
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3748308154
Short name T807
Test name
Test status
Simulation time 5026059102 ps
CPU time 311.76 seconds
Started May 26 02:15:21 PM PDT 24
Finished May 26 02:20:34 PM PDT 24
Peak memory 200500 kb
Host smart-7bcafa28-98be-420d-b180-30d50e1ac2d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748308154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3748308154
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.46541289
Short name T1144
Test name
Test status
Simulation time 3162333763 ps
CPU time 13.33 seconds
Started May 26 02:15:17 PM PDT 24
Finished May 26 02:15:31 PM PDT 24
Peak memory 198852 kb
Host smart-82164717-dfab-40fe-8195-988b17e411ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=46541289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.46541289
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1171614777
Short name T1066
Test name
Test status
Simulation time 128521787250 ps
CPU time 219.42 seconds
Started May 26 02:15:19 PM PDT 24
Finished May 26 02:19:00 PM PDT 24
Peak memory 200516 kb
Host smart-5cfd1d01-e2d7-4461-86e8-bb4d43f5f544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171614777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1171614777
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2373505848
Short name T972
Test name
Test status
Simulation time 4161846888 ps
CPU time 2.47 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:15:24 PM PDT 24
Peak memory 196800 kb
Host smart-469507ac-90d1-41e5-aae0-5c476ffdc120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373505848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2373505848
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.470399989
Short name T1069
Test name
Test status
Simulation time 453958510 ps
CPU time 1.68 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:15:23 PM PDT 24
Peak memory 198836 kb
Host smart-62ccf489-b841-4194-9cbf-2979c4fe56e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470399989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.470399989
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2281637484
Short name T546
Test name
Test status
Simulation time 13704100336 ps
CPU time 247.35 seconds
Started May 26 02:15:18 PM PDT 24
Finished May 26 02:19:26 PM PDT 24
Peak memory 208836 kb
Host smart-5eeaff7e-44df-4b19-9acc-ff93e9400379
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281637484 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2281637484
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1548795404
Short name T367
Test name
Test status
Simulation time 1567711062 ps
CPU time 3.19 seconds
Started May 26 02:15:20 PM PDT 24
Finished May 26 02:15:25 PM PDT 24
Peak memory 198848 kb
Host smart-dad65177-b7bc-44a4-866f-211b33c069f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548795404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1548795404
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1502127790
Short name T311
Test name
Test status
Simulation time 71831608700 ps
CPU time 36.27 seconds
Started May 26 02:15:19 PM PDT 24
Finished May 26 02:15:56 PM PDT 24
Peak memory 200556 kb
Host smart-a3c8b6bd-072a-4bb4-9026-9a98eb70632c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502127790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1502127790
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3057060035
Short name T1075
Test name
Test status
Simulation time 12170261 ps
CPU time 0.58 seconds
Started May 26 02:15:33 PM PDT 24
Finished May 26 02:15:34 PM PDT 24
Peak memory 195916 kb
Host smart-0fca421e-169a-4d58-82ad-76786f4d2911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057060035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3057060035
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3921706607
Short name T1011
Test name
Test status
Simulation time 168806893661 ps
CPU time 149.42 seconds
Started May 26 02:15:27 PM PDT 24
Finished May 26 02:17:57 PM PDT 24
Peak memory 200488 kb
Host smart-3223566d-3fd0-4319-8a2e-b1b13547c668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921706607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3921706607
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3387579980
Short name T356
Test name
Test status
Simulation time 148063349110 ps
CPU time 144.54 seconds
Started May 26 02:15:26 PM PDT 24
Finished May 26 02:17:51 PM PDT 24
Peak memory 200464 kb
Host smart-e91ae36e-afbf-4b75-9fc2-f9f765724af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387579980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3387579980
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3089399407
Short name T201
Test name
Test status
Simulation time 25286984425 ps
CPU time 67.28 seconds
Started May 26 02:15:33 PM PDT 24
Finished May 26 02:16:42 PM PDT 24
Peak memory 200488 kb
Host smart-4f6edb4c-3df6-4c1a-bc0f-35aa534a5e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089399407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3089399407
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3616449465
Short name T1004
Test name
Test status
Simulation time 35860994474 ps
CPU time 55.92 seconds
Started May 26 02:15:26 PM PDT 24
Finished May 26 02:16:23 PM PDT 24
Peak memory 200492 kb
Host smart-08b8d312-fdee-4f67-b666-7fd549144a63
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616449465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3616449465
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1510967944
Short name T510
Test name
Test status
Simulation time 221782614443 ps
CPU time 476.58 seconds
Started May 26 02:15:26 PM PDT 24
Finished May 26 02:23:23 PM PDT 24
Peak memory 200564 kb
Host smart-32f23513-8d62-4111-ae03-7a21d4f98a87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1510967944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1510967944
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3716841871
Short name T1061
Test name
Test status
Simulation time 3472390331 ps
CPU time 6.54 seconds
Started May 26 02:15:27 PM PDT 24
Finished May 26 02:15:34 PM PDT 24
Peak memory 199304 kb
Host smart-d7890aea-3471-470a-9477-8d992150df99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716841871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3716841871
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1249305958
Short name T562
Test name
Test status
Simulation time 69678358607 ps
CPU time 65.69 seconds
Started May 26 02:15:33 PM PDT 24
Finished May 26 02:16:40 PM PDT 24
Peak memory 200536 kb
Host smart-f4a105e5-28c0-4300-9eeb-22ef5b03d962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249305958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1249305958
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1531725960
Short name T345
Test name
Test status
Simulation time 6506026525 ps
CPU time 207.82 seconds
Started May 26 02:15:33 PM PDT 24
Finished May 26 02:19:02 PM PDT 24
Peak memory 200572 kb
Host smart-bab63411-2a44-4355-872e-675373348493
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531725960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1531725960
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3358457309
Short name T553
Test name
Test status
Simulation time 7406759259 ps
CPU time 29.96 seconds
Started May 26 02:15:25 PM PDT 24
Finished May 26 02:15:56 PM PDT 24
Peak memory 199372 kb
Host smart-60bb21cc-eed7-4494-8fa6-78e3ea9b0068
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3358457309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3358457309
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3936431801
Short name T1162
Test name
Test status
Simulation time 20940210140 ps
CPU time 37.85 seconds
Started May 26 02:15:28 PM PDT 24
Finished May 26 02:16:06 PM PDT 24
Peak memory 200480 kb
Host smart-a38ef550-eeb8-482c-9c84-eaffcbf89340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936431801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3936431801
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2717443956
Short name T686
Test name
Test status
Simulation time 4756296936 ps
CPU time 1.12 seconds
Started May 26 02:15:27 PM PDT 24
Finished May 26 02:15:29 PM PDT 24
Peak memory 196540 kb
Host smart-b270541c-4529-474f-b2a5-90b942a5b579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717443956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2717443956
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.410346942
Short name T3
Test name
Test status
Simulation time 645157432 ps
CPU time 3 seconds
Started May 26 02:15:28 PM PDT 24
Finished May 26 02:15:31 PM PDT 24
Peak memory 200068 kb
Host smart-38446903-556e-46fe-bd65-d585bdfd12c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410346942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.410346942
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2225387758
Short name T1033
Test name
Test status
Simulation time 95561501886 ps
CPU time 203.34 seconds
Started May 26 02:15:28 PM PDT 24
Finished May 26 02:18:52 PM PDT 24
Peak memory 200572 kb
Host smart-7f62e871-eb45-4948-bfa4-24ee339ae8a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225387758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2225387758
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1331881474
Short name T114
Test name
Test status
Simulation time 182454231624 ps
CPU time 177.99 seconds
Started May 26 02:15:29 PM PDT 24
Finished May 26 02:18:27 PM PDT 24
Peak memory 217304 kb
Host smart-1d20b7ee-8c56-4a21-ae72-32e2b3a80f70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331881474 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1331881474
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.941073213
Short name T808
Test name
Test status
Simulation time 7497088589 ps
CPU time 12.2 seconds
Started May 26 02:15:33 PM PDT 24
Finished May 26 02:15:45 PM PDT 24
Peak memory 200064 kb
Host smart-44990aeb-6821-440a-9a43-530b83cb9712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941073213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.941073213
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2115550785
Short name T1096
Test name
Test status
Simulation time 118725398513 ps
CPU time 84.69 seconds
Started May 26 02:15:28 PM PDT 24
Finished May 26 02:16:53 PM PDT 24
Peak memory 200444 kb
Host smart-9c9c8053-5b46-4a25-9a95-2edd89e94077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115550785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2115550785
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.76403957
Short name T1093
Test name
Test status
Simulation time 11871045 ps
CPU time 0.57 seconds
Started May 26 02:15:33 PM PDT 24
Finished May 26 02:15:35 PM PDT 24
Peak memory 195360 kb
Host smart-3bd8172d-6f20-45dc-aa4a-1ae3ad4c4db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76403957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.76403957
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3782583722
Short name T318
Test name
Test status
Simulation time 199240949442 ps
CPU time 82.3 seconds
Started May 26 02:15:37 PM PDT 24
Finished May 26 02:17:00 PM PDT 24
Peak memory 200552 kb
Host smart-654b824c-d98d-49d4-8e56-210b3a1996e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782583722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3782583722
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.103256982
Short name T900
Test name
Test status
Simulation time 17718636941 ps
CPU time 32.06 seconds
Started May 26 02:15:35 PM PDT 24
Finished May 26 02:16:08 PM PDT 24
Peak memory 200452 kb
Host smart-d6448a83-f059-4428-a0ea-61c37acc6c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103256982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.103256982
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1278937500
Short name T158
Test name
Test status
Simulation time 62692788874 ps
CPU time 20.74 seconds
Started May 26 02:15:59 PM PDT 24
Finished May 26 02:16:20 PM PDT 24
Peak memory 200316 kb
Host smart-46e4e804-516a-44d8-a488-6231f7c0318c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278937500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1278937500
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3695357009
Short name T1110
Test name
Test status
Simulation time 1363395149 ps
CPU time 2.96 seconds
Started May 26 02:15:36 PM PDT 24
Finished May 26 02:15:40 PM PDT 24
Peak memory 196564 kb
Host smart-705cae00-5a02-4743-adc0-b709cbd2659f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695357009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3695357009
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3625302336
Short name T422
Test name
Test status
Simulation time 210382506735 ps
CPU time 274.38 seconds
Started May 26 02:15:34 PM PDT 24
Finished May 26 02:20:09 PM PDT 24
Peak memory 200464 kb
Host smart-0ac5e6dd-6e10-4a22-b0f5-3b2cc3c902a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625302336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3625302336
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3924909851
Short name T511
Test name
Test status
Simulation time 7249275081 ps
CPU time 4.74 seconds
Started May 26 02:15:36 PM PDT 24
Finished May 26 02:15:41 PM PDT 24
Peak memory 199228 kb
Host smart-533cb16b-64b3-4bd1-8ebc-8cb523de4192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924909851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3924909851
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1210884412
Short name T820
Test name
Test status
Simulation time 51696257629 ps
CPU time 40.52 seconds
Started May 26 02:15:35 PM PDT 24
Finished May 26 02:16:17 PM PDT 24
Peak memory 200700 kb
Host smart-ba7a9830-cec6-4399-879b-d6d15a359596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210884412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1210884412
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1222663322
Short name T60
Test name
Test status
Simulation time 12179796586 ps
CPU time 749.21 seconds
Started May 26 02:15:34 PM PDT 24
Finished May 26 02:28:04 PM PDT 24
Peak memory 200468 kb
Host smart-eefac98d-449e-4d96-a9ca-54d212fc2ea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222663322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1222663322
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3298573322
Short name T936
Test name
Test status
Simulation time 6160672791 ps
CPU time 3.78 seconds
Started May 26 02:15:34 PM PDT 24
Finished May 26 02:15:38 PM PDT 24
Peak memory 198596 kb
Host smart-68ff3e2a-4e76-44de-9c93-f436c1421036
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298573322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3298573322
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.749326184
Short name T712
Test name
Test status
Simulation time 77180495167 ps
CPU time 47.21 seconds
Started May 26 02:15:36 PM PDT 24
Finished May 26 02:16:24 PM PDT 24
Peak memory 200444 kb
Host smart-9d902c4a-067c-42bb-9efd-1fdfc6f08fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749326184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.749326184
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.515040451
Short name T838
Test name
Test status
Simulation time 2008285677 ps
CPU time 1.56 seconds
Started May 26 02:15:33 PM PDT 24
Finished May 26 02:15:35 PM PDT 24
Peak memory 196164 kb
Host smart-7b3a7d0f-8973-4851-a03f-0fead8002e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515040451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.515040451
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3254150118
Short name T434
Test name
Test status
Simulation time 701254908 ps
CPU time 1.59 seconds
Started May 26 02:15:27 PM PDT 24
Finished May 26 02:15:29 PM PDT 24
Peak memory 199112 kb
Host smart-d3f746be-56f6-4aca-85d2-3c222255359c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254150118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3254150118
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1077479707
Short name T65
Test name
Test status
Simulation time 104875472059 ps
CPU time 610.29 seconds
Started May 26 02:15:36 PM PDT 24
Finished May 26 02:25:47 PM PDT 24
Peak memory 225472 kb
Host smart-55f958e1-a729-485a-a8ad-0aed6e808a49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077479707 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1077479707
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.652499353
Short name T1054
Test name
Test status
Simulation time 812167557 ps
CPU time 2.08 seconds
Started May 26 02:15:35 PM PDT 24
Finished May 26 02:15:38 PM PDT 24
Peak memory 198984 kb
Host smart-6b949245-c152-4c85-bc58-3e9a42436bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652499353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.652499353
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1195133910
Short name T1014
Test name
Test status
Simulation time 69620544247 ps
CPU time 125.31 seconds
Started May 26 02:15:27 PM PDT 24
Finished May 26 02:17:33 PM PDT 24
Peak memory 200556 kb
Host smart-4077254c-2c6c-4acb-882c-dbdd9d742880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195133910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1195133910
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.82800924
Short name T495
Test name
Test status
Simulation time 24484686 ps
CPU time 0.54 seconds
Started May 26 02:15:41 PM PDT 24
Finished May 26 02:15:43 PM PDT 24
Peak memory 195364 kb
Host smart-976508d2-c90c-4060-8e5f-72ec22d03ca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82800924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.82800924
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1813469668
Short name T568
Test name
Test status
Simulation time 90267930141 ps
CPU time 32.07 seconds
Started May 26 02:15:35 PM PDT 24
Finished May 26 02:16:08 PM PDT 24
Peak memory 200432 kb
Host smart-e10a49c4-ce43-4e80-b2ae-5e3a32279f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813469668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1813469668
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.723346099
Short name T444
Test name
Test status
Simulation time 59900813092 ps
CPU time 52.28 seconds
Started May 26 02:15:34 PM PDT 24
Finished May 26 02:16:27 PM PDT 24
Peak memory 200328 kb
Host smart-adee38af-b1e5-4e75-a721-e1f345e6dd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723346099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.723346099
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3829139714
Short name T239
Test name
Test status
Simulation time 56907711254 ps
CPU time 99.86 seconds
Started May 26 02:15:38 PM PDT 24
Finished May 26 02:17:19 PM PDT 24
Peak memory 200492 kb
Host smart-5427fff9-dc7a-44a3-914c-b51cd153e742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829139714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3829139714
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3165994061
Short name T138
Test name
Test status
Simulation time 30398762748 ps
CPU time 14.65 seconds
Started May 26 02:15:35 PM PDT 24
Finished May 26 02:15:50 PM PDT 24
Peak memory 199900 kb
Host smart-65dc96d7-3b4d-483f-abde-eef5b8e27a96
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165994061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3165994061
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2398440052
Short name T676
Test name
Test status
Simulation time 102441209583 ps
CPU time 617.32 seconds
Started May 26 02:15:36 PM PDT 24
Finished May 26 02:25:54 PM PDT 24
Peak memory 200572 kb
Host smart-6cb746b4-4ec7-4429-a5a2-4de79f02d500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398440052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2398440052
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2252812188
Short name T701
Test name
Test status
Simulation time 4203772944 ps
CPU time 9.63 seconds
Started May 26 02:15:37 PM PDT 24
Finished May 26 02:15:47 PM PDT 24
Peak memory 199944 kb
Host smart-4c207e1a-a6bc-4383-9692-f8d5b4193c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252812188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2252812188
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3211936307
Short name T1048
Test name
Test status
Simulation time 173906816298 ps
CPU time 117.03 seconds
Started May 26 02:15:36 PM PDT 24
Finished May 26 02:17:34 PM PDT 24
Peak memory 200760 kb
Host smart-c603488d-3c90-47a0-a9cf-20f17565f8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211936307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3211936307
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3722477222
Short name T475
Test name
Test status
Simulation time 3577507003 ps
CPU time 47.64 seconds
Started May 26 02:15:35 PM PDT 24
Finished May 26 02:16:23 PM PDT 24
Peak memory 200528 kb
Host smart-be318f00-3143-43b1-9d61-6cc587989462
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3722477222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3722477222
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.286767419
Short name T359
Test name
Test status
Simulation time 5575237463 ps
CPU time 52.76 seconds
Started May 26 02:15:35 PM PDT 24
Finished May 26 02:16:29 PM PDT 24
Peak memory 199592 kb
Host smart-da28bf6e-e048-476f-a752-c16da9ef6ee7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=286767419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.286767419
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2070692506
Short name T325
Test name
Test status
Simulation time 174758380078 ps
CPU time 118.56 seconds
Started May 26 02:15:34 PM PDT 24
Finished May 26 02:17:34 PM PDT 24
Peak memory 200472 kb
Host smart-190eeacf-61cc-4087-a435-2c1b397fd9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070692506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2070692506
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1497297334
Short name T857
Test name
Test status
Simulation time 3385762866 ps
CPU time 2.03 seconds
Started May 26 02:15:36 PM PDT 24
Finished May 26 02:15:39 PM PDT 24
Peak memory 196848 kb
Host smart-580d0118-caed-4fbb-bd5b-ff02b3ea7ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497297334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1497297334
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1481709078
Short name T307
Test name
Test status
Simulation time 937605157 ps
CPU time 3.03 seconds
Started May 26 02:15:35 PM PDT 24
Finished May 26 02:15:39 PM PDT 24
Peak memory 200012 kb
Host smart-78287a64-273a-40c2-9c54-50357cd39ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481709078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1481709078
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.861690558
Short name T791
Test name
Test status
Simulation time 155904411686 ps
CPU time 289.57 seconds
Started May 26 02:15:35 PM PDT 24
Finished May 26 02:20:26 PM PDT 24
Peak memory 200604 kb
Host smart-50ff0aa9-fe00-4aee-9b71-76429c815ee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861690558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.861690558
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2230870285
Short name T304
Test name
Test status
Simulation time 124939522096 ps
CPU time 603.21 seconds
Started May 26 02:15:36 PM PDT 24
Finished May 26 02:25:40 PM PDT 24
Peak memory 217232 kb
Host smart-1efd5e27-1628-4ed4-9d4b-5600431b9b91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230870285 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2230870285
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1478119811
Short name T736
Test name
Test status
Simulation time 401602094 ps
CPU time 1.32 seconds
Started May 26 02:15:33 PM PDT 24
Finished May 26 02:15:36 PM PDT 24
Peak memory 199008 kb
Host smart-dd8471a4-5dee-4020-93eb-a72544bea4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478119811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1478119811
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2610894708
Short name T333
Test name
Test status
Simulation time 91443486801 ps
CPU time 121.66 seconds
Started May 26 02:15:36 PM PDT 24
Finished May 26 02:17:39 PM PDT 24
Peak memory 200452 kb
Host smart-b950099b-aaf3-45d3-9164-4542ed67a0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610894708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2610894708
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3160433719
Short name T30
Test name
Test status
Simulation time 12006153 ps
CPU time 0.59 seconds
Started May 26 02:15:45 PM PDT 24
Finished May 26 02:15:47 PM PDT 24
Peak memory 195924 kb
Host smart-31738c2f-25ac-41f1-a12a-b92fe188b82e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160433719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3160433719
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3870449959
Short name T419
Test name
Test status
Simulation time 189245097457 ps
CPU time 99.02 seconds
Started May 26 02:15:42 PM PDT 24
Finished May 26 02:17:22 PM PDT 24
Peak memory 200576 kb
Host smart-6ea5475c-b7f6-4bb5-8a8f-e0d81031bdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870449959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3870449959
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2116709096
Short name T291
Test name
Test status
Simulation time 71417119364 ps
CPU time 28.77 seconds
Started May 26 02:15:41 PM PDT 24
Finished May 26 02:16:11 PM PDT 24
Peak memory 200368 kb
Host smart-5b6d7102-4c50-4ec9-ae13-334864c5a62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116709096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2116709096
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.652836782
Short name T962
Test name
Test status
Simulation time 24365640385 ps
CPU time 34.46 seconds
Started May 26 02:15:43 PM PDT 24
Finished May 26 02:16:18 PM PDT 24
Peak memory 200492 kb
Host smart-b936f521-1d6c-4902-b668-8f6250559204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652836782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.652836782
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3521197585
Short name T335
Test name
Test status
Simulation time 22319496222 ps
CPU time 30.36 seconds
Started May 26 02:15:44 PM PDT 24
Finished May 26 02:16:15 PM PDT 24
Peak memory 197484 kb
Host smart-637ac2c3-3c18-424f-b867-2d656ad8b360
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521197585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3521197585
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.629124589
Short name T452
Test name
Test status
Simulation time 164081229658 ps
CPU time 486.29 seconds
Started May 26 02:15:43 PM PDT 24
Finished May 26 02:23:50 PM PDT 24
Peak memory 200528 kb
Host smart-ff4b2fc2-25b0-4ac8-b360-e469f221969b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=629124589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.629124589
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3526654249
Short name T374
Test name
Test status
Simulation time 5289448388 ps
CPU time 4.69 seconds
Started May 26 02:15:41 PM PDT 24
Finished May 26 02:15:47 PM PDT 24
Peak memory 199348 kb
Host smart-ccd8b6f1-05e4-4ac1-920b-efcc9829b166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526654249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3526654249
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3169313632
Short name T52
Test name
Test status
Simulation time 498332131590 ps
CPU time 58.53 seconds
Started May 26 02:15:42 PM PDT 24
Finished May 26 02:16:41 PM PDT 24
Peak memory 200720 kb
Host smart-f01fa4ea-64e8-44c5-97bb-92e2ac4e7f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169313632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3169313632
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3763877492
Short name T448
Test name
Test status
Simulation time 14932442512 ps
CPU time 237.51 seconds
Started May 26 02:15:40 PM PDT 24
Finished May 26 02:19:38 PM PDT 24
Peak memory 200556 kb
Host smart-7a6c5bae-733f-4e42-a7f8-c3c5326041d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3763877492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3763877492
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.4111887237
Short name T1087
Test name
Test status
Simulation time 2974036557 ps
CPU time 21.5 seconds
Started May 26 02:15:41 PM PDT 24
Finished May 26 02:16:04 PM PDT 24
Peak memory 199432 kb
Host smart-9ce48cdf-0d48-467a-97b5-4dacd9f250cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4111887237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4111887237
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2501682480
Short name T504
Test name
Test status
Simulation time 182681680910 ps
CPU time 72.35 seconds
Started May 26 02:15:43 PM PDT 24
Finished May 26 02:16:56 PM PDT 24
Peak memory 200512 kb
Host smart-bddc6bf7-182c-49bb-bf4c-998bef07e737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501682480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2501682480
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2190590854
Short name T267
Test name
Test status
Simulation time 38237458253 ps
CPU time 62.38 seconds
Started May 26 02:15:40 PM PDT 24
Finished May 26 02:16:43 PM PDT 24
Peak memory 196672 kb
Host smart-998665f8-d6cd-43da-8464-6c2bb0c8671c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190590854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2190590854
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.353615938
Short name T549
Test name
Test status
Simulation time 5986490728 ps
CPU time 17.07 seconds
Started May 26 02:15:41 PM PDT 24
Finished May 26 02:16:00 PM PDT 24
Peak memory 200436 kb
Host smart-02c6c25b-5703-4c46-8920-257318cfd431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353615938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.353615938
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2943073741
Short name T206
Test name
Test status
Simulation time 452812719265 ps
CPU time 415.91 seconds
Started May 26 02:15:44 PM PDT 24
Finished May 26 02:22:41 PM PDT 24
Peak memory 200588 kb
Host smart-fa65e989-33cc-4c29-9820-592f19f0e3f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943073741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2943073741
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2379095728
Short name T618
Test name
Test status
Simulation time 327644571705 ps
CPU time 1139.31 seconds
Started May 26 02:15:41 PM PDT 24
Finished May 26 02:34:41 PM PDT 24
Peak memory 226028 kb
Host smart-8620df6d-e403-4900-8b07-a49b49b2f7b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379095728 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2379095728
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3781295557
Short name T281
Test name
Test status
Simulation time 925810141 ps
CPU time 2.8 seconds
Started May 26 02:15:44 PM PDT 24
Finished May 26 02:15:47 PM PDT 24
Peak memory 199616 kb
Host smart-ab5857a6-aebf-4ed9-aab5-778a7e11f7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781295557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3781295557
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.714026220
Short name T440
Test name
Test status
Simulation time 24878043350 ps
CPU time 11.1 seconds
Started May 26 02:15:41 PM PDT 24
Finished May 26 02:15:53 PM PDT 24
Peak memory 200568 kb
Host smart-fd9afa65-1e78-42c6-a3f5-57ab32a4dc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714026220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.714026220
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1126611052
Short name T1008
Test name
Test status
Simulation time 50227142 ps
CPU time 0.61 seconds
Started May 26 02:15:51 PM PDT 24
Finished May 26 02:15:52 PM PDT 24
Peak memory 195924 kb
Host smart-ceff0cb9-12bd-4fe5-b58a-b3ba01710041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126611052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1126611052
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.611750977
Short name T507
Test name
Test status
Simulation time 79449866465 ps
CPU time 36.88 seconds
Started May 26 02:15:40 PM PDT 24
Finished May 26 02:16:17 PM PDT 24
Peak memory 200488 kb
Host smart-ca51dbd7-6b32-439b-9e96-57f08c156652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611750977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.611750977
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2874823752
Short name T235
Test name
Test status
Simulation time 223215560485 ps
CPU time 54.74 seconds
Started May 26 02:15:41 PM PDT 24
Finished May 26 02:16:37 PM PDT 24
Peak memory 200556 kb
Host smart-8eac99bf-4b2a-4569-99f6-76cae242157d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874823752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2874823752
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1540235357
Short name T1081
Test name
Test status
Simulation time 54054405978 ps
CPU time 27.29 seconds
Started May 26 02:15:43 PM PDT 24
Finished May 26 02:16:11 PM PDT 24
Peak memory 200268 kb
Host smart-558e07a4-53f5-47a4-95dc-2da15786bfde
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540235357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1540235357
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1919595142
Short name T106
Test name
Test status
Simulation time 116985623757 ps
CPU time 1185.06 seconds
Started May 26 02:15:52 PM PDT 24
Finished May 26 02:35:38 PM PDT 24
Peak memory 200500 kb
Host smart-01a3548a-2d69-458b-93f9-a0eb2f14938a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919595142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1919595142
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.4028447153
Short name T551
Test name
Test status
Simulation time 1495337111 ps
CPU time 5.38 seconds
Started May 26 02:15:51 PM PDT 24
Finished May 26 02:15:57 PM PDT 24
Peak memory 200392 kb
Host smart-70c5cbcd-245f-4683-8e3c-0a648cc405dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028447153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.4028447153
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.557340869
Short name T270
Test name
Test status
Simulation time 42474443377 ps
CPU time 37.88 seconds
Started May 26 02:15:50 PM PDT 24
Finished May 26 02:16:28 PM PDT 24
Peak memory 199588 kb
Host smart-6d4c4046-0cd8-4f78-9939-0865be08d154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557340869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.557340869
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.306751687
Short name T502
Test name
Test status
Simulation time 18468777005 ps
CPU time 245.88 seconds
Started May 26 02:15:50 PM PDT 24
Finished May 26 02:19:56 PM PDT 24
Peak memory 200500 kb
Host smart-a294d494-cd58-45f9-b5c1-43b3d2dcbda0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=306751687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.306751687
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.474518009
Short name T742
Test name
Test status
Simulation time 5249603262 ps
CPU time 12.39 seconds
Started May 26 02:15:42 PM PDT 24
Finished May 26 02:15:56 PM PDT 24
Peak memory 199300 kb
Host smart-3f97bfe9-e2f4-4e91-9aa3-1e7c3a460ddc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=474518009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.474518009
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3123041420
Short name T523
Test name
Test status
Simulation time 139406986192 ps
CPU time 53.83 seconds
Started May 26 02:15:49 PM PDT 24
Finished May 26 02:16:44 PM PDT 24
Peak memory 200464 kb
Host smart-ae1154e3-2759-4913-9b65-c8fb1c3bd4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123041420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3123041420
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2487888949
Short name T1141
Test name
Test status
Simulation time 3680946490 ps
CPU time 1.85 seconds
Started May 26 02:15:50 PM PDT 24
Finished May 26 02:15:53 PM PDT 24
Peak memory 196328 kb
Host smart-2e1bfb39-fdcc-499e-950a-19635a73abcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487888949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2487888949
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.669741535
Short name T490
Test name
Test status
Simulation time 483208967 ps
CPU time 1.29 seconds
Started May 26 02:15:42 PM PDT 24
Finished May 26 02:15:44 PM PDT 24
Peak memory 199148 kb
Host smart-ffd9556b-452c-4ede-bd4f-e6eae279325c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669741535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.669741535
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.4184377821
Short name T1079
Test name
Test status
Simulation time 135583209745 ps
CPU time 67.9 seconds
Started May 26 02:15:50 PM PDT 24
Finished May 26 02:16:59 PM PDT 24
Peak memory 200844 kb
Host smart-9e4921c4-4442-4afe-8f7e-69113d55548d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184377821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.4184377821
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3476273214
Short name T478
Test name
Test status
Simulation time 50084506994 ps
CPU time 592.69 seconds
Started May 26 02:15:52 PM PDT 24
Finished May 26 02:25:45 PM PDT 24
Peak memory 217012 kb
Host smart-d71cde0a-84b1-47c3-95eb-256936608cd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476273214 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3476273214
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1855227200
Short name T1064
Test name
Test status
Simulation time 7442478186 ps
CPU time 11.59 seconds
Started May 26 02:15:48 PM PDT 24
Finished May 26 02:16:01 PM PDT 24
Peak memory 200276 kb
Host smart-c1a80355-6940-43b0-86f5-03b98214c248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855227200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1855227200
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.181529760
Short name T865
Test name
Test status
Simulation time 71383105269 ps
CPU time 21.11 seconds
Started May 26 02:15:45 PM PDT 24
Finished May 26 02:16:07 PM PDT 24
Peak memory 200496 kb
Host smart-c2493933-4913-49c1-8b0b-27fea5c44ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181529760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.181529760
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3852409827
Short name T363
Test name
Test status
Simulation time 107344021 ps
CPU time 0.54 seconds
Started May 26 02:16:01 PM PDT 24
Finished May 26 02:16:02 PM PDT 24
Peak memory 194868 kb
Host smart-eb40d607-df4f-4017-92e2-6dcdbefad0ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852409827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3852409827
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.570056563
Short name T260
Test name
Test status
Simulation time 80467347308 ps
CPU time 51.8 seconds
Started May 26 02:15:50 PM PDT 24
Finished May 26 02:16:42 PM PDT 24
Peak memory 200496 kb
Host smart-1e237f87-ee03-48b8-92a9-63ad100e2a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570056563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.570056563
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2483680625
Short name T692
Test name
Test status
Simulation time 30891210129 ps
CPU time 12.19 seconds
Started May 26 02:15:50 PM PDT 24
Finished May 26 02:16:03 PM PDT 24
Peak memory 199148 kb
Host smart-6f809a7f-0671-4efe-bb3a-5501e94be2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483680625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2483680625
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.8722681
Short name T246
Test name
Test status
Simulation time 142419428718 ps
CPU time 131.28 seconds
Started May 26 02:15:52 PM PDT 24
Finished May 26 02:18:04 PM PDT 24
Peak memory 200516 kb
Host smart-f585bff8-93f4-405f-82bf-0aaa4ec842f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8722681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.8722681
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3481327798
Short name T814
Test name
Test status
Simulation time 228761659980 ps
CPU time 522.47 seconds
Started May 26 02:15:50 PM PDT 24
Finished May 26 02:24:33 PM PDT 24
Peak memory 200492 kb
Host smart-7cdd4430-0596-41ed-8a88-1ee64a61dfa1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481327798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3481327798
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3092441741
Short name T946
Test name
Test status
Simulation time 84514088010 ps
CPU time 632.57 seconds
Started May 26 02:15:56 PM PDT 24
Finished May 26 02:26:30 PM PDT 24
Peak memory 200532 kb
Host smart-9fc5d43e-922f-44e4-8e36-7e72cd0b00b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3092441741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3092441741
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2321377196
Short name T582
Test name
Test status
Simulation time 9382220503 ps
CPU time 5.1 seconds
Started May 26 02:15:52 PM PDT 24
Finished May 26 02:15:58 PM PDT 24
Peak memory 198964 kb
Host smart-372aff58-b331-424b-97ac-91ebc8b23dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321377196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2321377196
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.851531095
Short name T1174
Test name
Test status
Simulation time 59587972400 ps
CPU time 61.48 seconds
Started May 26 02:15:49 PM PDT 24
Finished May 26 02:16:51 PM PDT 24
Peak memory 200752 kb
Host smart-2fb1939f-37d3-49c7-b252-35785ad9c63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851531095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.851531095
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3208137982
Short name T272
Test name
Test status
Simulation time 10439780333 ps
CPU time 220.99 seconds
Started May 26 02:15:49 PM PDT 24
Finished May 26 02:19:31 PM PDT 24
Peak memory 200504 kb
Host smart-81d46759-5e44-410e-9b1c-2d421e1a3417
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3208137982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3208137982
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3678640399
Short name T412
Test name
Test status
Simulation time 2414670652 ps
CPU time 16.54 seconds
Started May 26 02:15:50 PM PDT 24
Finished May 26 02:16:07 PM PDT 24
Peak memory 199944 kb
Host smart-32d533df-bde5-4082-92d2-0317aa9a60d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3678640399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3678640399
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1098096201
Short name T901
Test name
Test status
Simulation time 7056503915 ps
CPU time 12.7 seconds
Started May 26 02:15:49 PM PDT 24
Finished May 26 02:16:02 PM PDT 24
Peak memory 198420 kb
Host smart-09e06cc6-a985-4c37-b4fe-da793f93a1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098096201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1098096201
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3362181967
Short name T980
Test name
Test status
Simulation time 6343568771 ps
CPU time 1.51 seconds
Started May 26 02:15:49 PM PDT 24
Finished May 26 02:15:51 PM PDT 24
Peak memory 196472 kb
Host smart-b64f8ee3-4caf-45e7-a2dd-da879a38ec7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362181967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3362181967
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1492817574
Short name T308
Test name
Test status
Simulation time 463479328 ps
CPU time 2.21 seconds
Started May 26 02:15:49 PM PDT 24
Finished May 26 02:15:52 PM PDT 24
Peak memory 199076 kb
Host smart-6cc3ea39-cd7c-4cf7-913a-3cc1797b1bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492817574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1492817574
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1511374157
Short name T1088
Test name
Test status
Simulation time 233789230026 ps
CPU time 282.82 seconds
Started May 26 02:15:57 PM PDT 24
Finished May 26 02:20:41 PM PDT 24
Peak memory 216568 kb
Host smart-024318ab-46b2-4ae6-abe8-4e6755d4fed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511374157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1511374157
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1851555125
Short name T36
Test name
Test status
Simulation time 12138094844 ps
CPU time 139.79 seconds
Started May 26 02:16:00 PM PDT 24
Finished May 26 02:18:20 PM PDT 24
Peak memory 216668 kb
Host smart-00523f97-5ac8-4864-8652-f6777e84ac79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851555125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1851555125
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2450236816
Short name T1156
Test name
Test status
Simulation time 7103516847 ps
CPU time 12.32 seconds
Started May 26 02:15:51 PM PDT 24
Finished May 26 02:16:05 PM PDT 24
Peak memory 200428 kb
Host smart-6e21de80-aeb1-4c8e-8e96-4769aa13e073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450236816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2450236816
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2086801868
Short name T1074
Test name
Test status
Simulation time 43430056659 ps
CPU time 21.17 seconds
Started May 26 02:15:50 PM PDT 24
Finished May 26 02:16:12 PM PDT 24
Peak memory 200528 kb
Host smart-a5d08c0c-c0b6-4eb1-8a38-86514135dba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086801868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2086801868
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2710575180
Short name T1102
Test name
Test status
Simulation time 44386460 ps
CPU time 0.56 seconds
Started May 26 02:12:59 PM PDT 24
Finished May 26 02:13:01 PM PDT 24
Peak memory 194884 kb
Host smart-fbdff69e-aa34-4cac-9811-2d9cb4d020d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710575180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2710575180
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3028697983
Short name T287
Test name
Test status
Simulation time 41151318247 ps
CPU time 68.64 seconds
Started May 26 02:12:50 PM PDT 24
Finished May 26 02:14:00 PM PDT 24
Peak memory 200500 kb
Host smart-9b5a3cf5-489f-42d9-ac33-a7f7a4c91793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028697983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3028697983
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.475464271
Short name T1136
Test name
Test status
Simulation time 50252669206 ps
CPU time 22.23 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:13:17 PM PDT 24
Peak memory 200376 kb
Host smart-853d78e5-e4c7-4ccb-9f34-c4474691eba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475464271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.475464271
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_intr.1773632458
Short name T670
Test name
Test status
Simulation time 219694815085 ps
CPU time 440.63 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:20:16 PM PDT 24
Peak memory 199768 kb
Host smart-5bbac655-b83f-4fb4-8b6e-ab444255fa6c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773632458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1773632458
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3428095587
Short name T836
Test name
Test status
Simulation time 155760568139 ps
CPU time 433.49 seconds
Started May 26 02:12:54 PM PDT 24
Finished May 26 02:20:09 PM PDT 24
Peak memory 200472 kb
Host smart-179b6a0e-cce5-4baf-a6ea-37eb8a85253c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3428095587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3428095587
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.4002749635
Short name T403
Test name
Test status
Simulation time 1449774926 ps
CPU time 1.24 seconds
Started May 26 02:12:52 PM PDT 24
Finished May 26 02:12:56 PM PDT 24
Peak memory 196560 kb
Host smart-61842f22-e6e2-44be-a769-cb9bbc9e7c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002749635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.4002749635
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3556044935
Short name T853
Test name
Test status
Simulation time 59506271773 ps
CPU time 55.86 seconds
Started May 26 02:12:54 PM PDT 24
Finished May 26 02:13:51 PM PDT 24
Peak memory 200336 kb
Host smart-7623f314-de72-4ee9-b891-6b8e1d9e2f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556044935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3556044935
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2726314526
Short name T971
Test name
Test status
Simulation time 10680525554 ps
CPU time 239.97 seconds
Started May 26 02:12:56 PM PDT 24
Finished May 26 02:16:57 PM PDT 24
Peak memory 200428 kb
Host smart-85596858-cb20-4bd1-b00d-db416932c203
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726314526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2726314526
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2289842847
Short name T396
Test name
Test status
Simulation time 4056241013 ps
CPU time 12.35 seconds
Started May 26 02:12:55 PM PDT 24
Finished May 26 02:13:09 PM PDT 24
Peak memory 198992 kb
Host smart-b8244faf-1641-4c8f-b079-778fe647178f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2289842847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2289842847
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2461209608
Short name T1041
Test name
Test status
Simulation time 40458938808 ps
CPU time 6.97 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:13:02 PM PDT 24
Peak memory 200476 kb
Host smart-e7606dce-554e-4829-8ae8-bfa7d90130ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461209608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2461209608
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.4145767289
Short name T811
Test name
Test status
Simulation time 4192272218 ps
CPU time 2.02 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:12:56 PM PDT 24
Peak memory 196836 kb
Host smart-c312d3e9-8497-4438-a702-8316a5f348c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145767289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.4145767289
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1215777956
Short name T957
Test name
Test status
Simulation time 436411688 ps
CPU time 1.72 seconds
Started May 26 02:12:52 PM PDT 24
Finished May 26 02:12:55 PM PDT 24
Peak memory 199352 kb
Host smart-62e2dcce-3d64-4a50-975a-390d2c9bf3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215777956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1215777956
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2225892989
Short name T299
Test name
Test status
Simulation time 99420653195 ps
CPU time 517.62 seconds
Started May 26 02:12:54 PM PDT 24
Finished May 26 02:21:33 PM PDT 24
Peak memory 200496 kb
Host smart-35a32fba-8104-4820-8809-a9ac35b5eeb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225892989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2225892989
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.944317638
Short name T212
Test name
Test status
Simulation time 84954497054 ps
CPU time 755.11 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:25:30 PM PDT 24
Peak memory 217048 kb
Host smart-f60d6be5-eb51-4be7-9a6b-7e9c479a9853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944317638 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.944317638
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.288185944
Short name T280
Test name
Test status
Simulation time 6137952005 ps
CPU time 7.99 seconds
Started May 26 02:12:53 PM PDT 24
Finished May 26 02:13:03 PM PDT 24
Peak memory 200544 kb
Host smart-85c9da02-01ee-4c10-b00d-e26e125b4991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288185944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.288185944
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3842608600
Short name T904
Test name
Test status
Simulation time 27787590003 ps
CPU time 11.68 seconds
Started May 26 02:12:54 PM PDT 24
Finished May 26 02:13:07 PM PDT 24
Peak memory 200424 kb
Host smart-b702d9d8-bb2d-4cc5-ba09-a9ec90865f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842608600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3842608600
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.927349646
Short name T823
Test name
Test status
Simulation time 260214493660 ps
CPU time 391.34 seconds
Started May 26 02:16:00 PM PDT 24
Finished May 26 02:22:32 PM PDT 24
Peak memory 200436 kb
Host smart-15d8b386-46f5-4eeb-aaf5-a8ca74d795e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927349646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.927349646
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1718549350
Short name T373
Test name
Test status
Simulation time 78820192133 ps
CPU time 59.11 seconds
Started May 26 02:15:59 PM PDT 24
Finished May 26 02:16:58 PM PDT 24
Peak memory 200284 kb
Host smart-64459b91-01f1-40fb-9a7c-6406eaeb81a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718549350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1718549350
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.605493317
Short name T40
Test name
Test status
Simulation time 76823960516 ps
CPU time 782.66 seconds
Started May 26 02:16:03 PM PDT 24
Finished May 26 02:29:06 PM PDT 24
Peak memory 225516 kb
Host smart-ba036e36-20dd-4242-920a-dfe126aad2f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605493317 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.605493317
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1604612054
Short name T719
Test name
Test status
Simulation time 62864418875 ps
CPU time 93.12 seconds
Started May 26 02:15:58 PM PDT 24
Finished May 26 02:17:32 PM PDT 24
Peak memory 200552 kb
Host smart-be598d46-4823-4dd6-b2c6-7fbdafc9def0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604612054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1604612054
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.914757737
Short name T1047
Test name
Test status
Simulation time 115730263374 ps
CPU time 441.26 seconds
Started May 26 02:15:57 PM PDT 24
Finished May 26 02:23:20 PM PDT 24
Peak memory 217264 kb
Host smart-74f61e78-2dff-4c95-b47f-bb5119895317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914757737 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.914757737
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3924926501
Short name T171
Test name
Test status
Simulation time 286421903294 ps
CPU time 776.58 seconds
Started May 26 02:15:58 PM PDT 24
Finished May 26 02:28:55 PM PDT 24
Peak memory 217220 kb
Host smart-520b5b4b-ae4c-4ae7-83ae-67823c74da34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924926501 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3924926501
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3794859126
Short name T245
Test name
Test status
Simulation time 35492795636 ps
CPU time 39.38 seconds
Started May 26 02:16:00 PM PDT 24
Finished May 26 02:16:40 PM PDT 24
Peak memory 200536 kb
Host smart-6010f3b4-8205-4af8-ac9e-ed04df9561eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794859126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3794859126
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2370248231
Short name T1026
Test name
Test status
Simulation time 24290828718 ps
CPU time 718.65 seconds
Started May 26 02:16:00 PM PDT 24
Finished May 26 02:27:59 PM PDT 24
Peak memory 217164 kb
Host smart-f98db19d-b1b1-4bee-a74f-836145c59b47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370248231 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2370248231
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1686332712
Short name T129
Test name
Test status
Simulation time 15623191846 ps
CPU time 26.08 seconds
Started May 26 02:15:57 PM PDT 24
Finished May 26 02:16:25 PM PDT 24
Peak memory 200532 kb
Host smart-5aecf0fc-29c5-44db-8fb2-c086adb145aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686332712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1686332712
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.777289452
Short name T336
Test name
Test status
Simulation time 76850894302 ps
CPU time 766.7 seconds
Started May 26 02:16:00 PM PDT 24
Finished May 26 02:28:47 PM PDT 24
Peak memory 217004 kb
Host smart-50013aa7-b0cd-4a6d-a65e-2ab9aec2a88f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777289452 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.777289452
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2005656682
Short name T599
Test name
Test status
Simulation time 11056429412 ps
CPU time 16.48 seconds
Started May 26 02:15:57 PM PDT 24
Finished May 26 02:16:14 PM PDT 24
Peak memory 200552 kb
Host smart-d4058dfb-3a62-4672-acee-1da0bdac8fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005656682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2005656682
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3793727624
Short name T215
Test name
Test status
Simulation time 61465004801 ps
CPU time 719.66 seconds
Started May 26 02:15:59 PM PDT 24
Finished May 26 02:27:59 PM PDT 24
Peak memory 225420 kb
Host smart-1ac51c14-2065-462f-92fa-a09e4f9649df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793727624 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3793727624
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.895583203
Short name T970
Test name
Test status
Simulation time 74097405875 ps
CPU time 32.18 seconds
Started May 26 02:15:58 PM PDT 24
Finished May 26 02:16:31 PM PDT 24
Peak memory 200548 kb
Host smart-0612731c-5951-4b1a-924f-cc4e1ee8c361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895583203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.895583203
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1014268242
Short name T173
Test name
Test status
Simulation time 244134967412 ps
CPU time 1078.29 seconds
Started May 26 02:16:02 PM PDT 24
Finished May 26 02:34:01 PM PDT 24
Peak memory 225500 kb
Host smart-28e8f523-c9e8-4159-8444-87cb6fb1da7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014268242 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1014268242
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.328329118
Short name T577
Test name
Test status
Simulation time 315509522730 ps
CPU time 28.92 seconds
Started May 26 02:16:02 PM PDT 24
Finished May 26 02:16:31 PM PDT 24
Peak memory 200568 kb
Host smart-13002a71-10f8-4116-8534-464975433fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328329118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.328329118
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.335155
Short name T81
Test name
Test status
Simulation time 35223580197 ps
CPU time 682.43 seconds
Started May 26 02:15:58 PM PDT 24
Finished May 26 02:27:21 PM PDT 24
Peak memory 217288 kb
Host smart-ae93de43-c224-4381-8e83-3c282fda5cfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335155 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.335155
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1646077888
Short name T1181
Test name
Test status
Simulation time 71699068845 ps
CPU time 29.85 seconds
Started May 26 02:15:56 PM PDT 24
Finished May 26 02:16:27 PM PDT 24
Peak memory 200460 kb
Host smart-1bbf22b0-9f36-433a-9b5e-52039eb87caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646077888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1646077888
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3375680019
Short name T1001
Test name
Test status
Simulation time 17965265683 ps
CPU time 187.92 seconds
Started May 26 02:16:02 PM PDT 24
Finished May 26 02:19:11 PM PDT 24
Peak memory 216496 kb
Host smart-8d359544-8ded-4bed-b543-0218326a6e0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375680019 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3375680019
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.621750821
Short name T360
Test name
Test status
Simulation time 19212952 ps
CPU time 0.59 seconds
Started May 26 02:12:59 PM PDT 24
Finished May 26 02:13:00 PM PDT 24
Peak memory 195868 kb
Host smart-700eedf3-069c-4bd2-9a10-4c4820c60508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621750821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.621750821
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3117756173
Short name T762
Test name
Test status
Simulation time 23358929944 ps
CPU time 43.86 seconds
Started May 26 02:12:58 PM PDT 24
Finished May 26 02:13:43 PM PDT 24
Peak memory 200504 kb
Host smart-0c1d1f55-b92f-401d-ada0-a19afe09bec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117756173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3117756173
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.973616353
Short name T763
Test name
Test status
Simulation time 94473738597 ps
CPU time 92.3 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:14:36 PM PDT 24
Peak memory 200504 kb
Host smart-f5bc4cd5-90a4-4e66-b6d1-8298612fa6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973616353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.973616353
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1310315448
Short name T929
Test name
Test status
Simulation time 102081981249 ps
CPU time 39.68 seconds
Started May 26 02:12:59 PM PDT 24
Finished May 26 02:13:40 PM PDT 24
Peak memory 200496 kb
Host smart-d5dde7f5-65fc-441b-8c59-923bb57782e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310315448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1310315448
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3341252712
Short name T466
Test name
Test status
Simulation time 10077276208 ps
CPU time 8.49 seconds
Started May 26 02:12:58 PM PDT 24
Finished May 26 02:13:07 PM PDT 24
Peak memory 200200 kb
Host smart-e4a5f2c1-d46d-43f7-b17b-097baf8ea8c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341252712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3341252712
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1439374996
Short name T581
Test name
Test status
Simulation time 32753356493 ps
CPU time 285.32 seconds
Started May 26 02:12:59 PM PDT 24
Finished May 26 02:17:46 PM PDT 24
Peak memory 200516 kb
Host smart-5b0a6d39-68c1-4b05-a77e-bfd973ee25a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1439374996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1439374996
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1007263332
Short name T371
Test name
Test status
Simulation time 2897430761 ps
CPU time 2.15 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:13:04 PM PDT 24
Peak memory 197032 kb
Host smart-db369a67-e20f-44bf-9818-0484a01babdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007263332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1007263332
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2322557515
Short name T886
Test name
Test status
Simulation time 156360118301 ps
CPU time 101.39 seconds
Started May 26 02:13:03 PM PDT 24
Finished May 26 02:14:46 PM PDT 24
Peak memory 200844 kb
Host smart-ca9f03ea-3602-4eb1-9689-457cff28dc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322557515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2322557515
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3488824661
Short name T268
Test name
Test status
Simulation time 19001314715 ps
CPU time 904.44 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:28:08 PM PDT 24
Peak memory 200496 kb
Host smart-35df17c1-eaac-4a0e-8ee2-3f10e5f2ddf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488824661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3488824661
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.343409715
Short name T366
Test name
Test status
Simulation time 3678931882 ps
CPU time 3.05 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:13:07 PM PDT 24
Peak memory 199380 kb
Host smart-a973d568-ae31-4add-9ea0-29deea66724a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=343409715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.343409715
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1456606570
Short name T627
Test name
Test status
Simulation time 50490834452 ps
CPU time 72.07 seconds
Started May 26 02:12:58 PM PDT 24
Finished May 26 02:14:11 PM PDT 24
Peak memory 200540 kb
Host smart-12330c9b-d592-4e80-8d98-4ff1ad3867ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456606570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1456606570
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1545935539
Short name T314
Test name
Test status
Simulation time 35256683744 ps
CPU time 55.81 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:13:58 PM PDT 24
Peak memory 196220 kb
Host smart-e985f3ca-b2e0-434f-8859-49d9e2871074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545935539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1545935539
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.105143355
Short name T748
Test name
Test status
Simulation time 493184567 ps
CPU time 1.82 seconds
Started May 26 02:13:05 PM PDT 24
Finished May 26 02:13:07 PM PDT 24
Peak memory 199060 kb
Host smart-4c0ace6f-3fe3-4901-bd5c-35342a3eb936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105143355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.105143355
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2353865370
Short name T92
Test name
Test status
Simulation time 234028574803 ps
CPU time 455.17 seconds
Started May 26 02:12:58 PM PDT 24
Finished May 26 02:20:34 PM PDT 24
Peak memory 200496 kb
Host smart-f11d539f-74bc-4ada-a222-dda760c6806b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353865370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2353865370
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3385624825
Short name T527
Test name
Test status
Simulation time 599413723 ps
CPU time 1.88 seconds
Started May 26 02:13:04 PM PDT 24
Finished May 26 02:13:07 PM PDT 24
Peak memory 199116 kb
Host smart-eb2d4e17-2130-40f9-a1ad-170506dd4705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385624825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3385624825
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3590296367
Short name T1055
Test name
Test status
Simulation time 13983106751 ps
CPU time 7.29 seconds
Started May 26 02:13:03 PM PDT 24
Finished May 26 02:13:13 PM PDT 24
Peak memory 200456 kb
Host smart-6bf0dc5d-73c9-4d87-95b4-0c3adfe7ebcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590296367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3590296367
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3694644454
Short name T1115
Test name
Test status
Simulation time 69149133785 ps
CPU time 771.25 seconds
Started May 26 02:15:59 PM PDT 24
Finished May 26 02:28:51 PM PDT 24
Peak memory 217312 kb
Host smart-f1ab8a34-fc28-43d8-abd7-31bcc644679d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694644454 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3694644454
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.4043377047
Short name T935
Test name
Test status
Simulation time 19457977947 ps
CPU time 35.69 seconds
Started May 26 02:15:58 PM PDT 24
Finished May 26 02:16:35 PM PDT 24
Peak memory 200444 kb
Host smart-7fca784b-ef36-4b3f-ae38-b143f6342f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043377047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.4043377047
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1312149520
Short name T819
Test name
Test status
Simulation time 32662028184 ps
CPU time 390.41 seconds
Started May 26 02:15:57 PM PDT 24
Finished May 26 02:22:29 PM PDT 24
Peak memory 213144 kb
Host smart-ea541871-cc47-4f37-86af-2ee9a58feac3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312149520 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1312149520
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.981091594
Short name T776
Test name
Test status
Simulation time 40703750517 ps
CPU time 70.82 seconds
Started May 26 02:15:59 PM PDT 24
Finished May 26 02:17:11 PM PDT 24
Peak memory 200496 kb
Host smart-902e10ef-500b-4b80-a3cc-fe247b856f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981091594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.981091594
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.4101440340
Short name T650
Test name
Test status
Simulation time 111096131135 ps
CPU time 413.14 seconds
Started May 26 02:16:05 PM PDT 24
Finished May 26 02:22:59 PM PDT 24
Peak memory 216372 kb
Host smart-09621d30-dfd4-4bc9-9861-1df27e935c90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101440340 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.4101440340
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1587713650
Short name T541
Test name
Test status
Simulation time 130731053753 ps
CPU time 283.03 seconds
Started May 26 02:16:05 PM PDT 24
Finished May 26 02:20:48 PM PDT 24
Peak memory 200560 kb
Host smart-0475bf1b-cb19-4dfe-a59f-aa7014b5a45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587713650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1587713650
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1203054272
Short name T866
Test name
Test status
Simulation time 260322889812 ps
CPU time 749.42 seconds
Started May 26 02:16:05 PM PDT 24
Finished May 26 02:28:35 PM PDT 24
Peak memory 225460 kb
Host smart-876b2fd4-32a7-40fe-afd9-3d66c19e8685
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203054272 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1203054272
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1077383334
Short name T991
Test name
Test status
Simulation time 118361827573 ps
CPU time 85.27 seconds
Started May 26 02:16:05 PM PDT 24
Finished May 26 02:17:31 PM PDT 24
Peak memory 200556 kb
Host smart-f4a2f597-5206-47e8-add8-98e0dbffc210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077383334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1077383334
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.775611472
Short name T1017
Test name
Test status
Simulation time 391829090861 ps
CPU time 1268.92 seconds
Started May 26 02:16:06 PM PDT 24
Finished May 26 02:37:16 PM PDT 24
Peak memory 233344 kb
Host smart-cf8d3e02-aa9d-4b72-b63f-28a36c3bce0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775611472 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.775611472
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1085686959
Short name T592
Test name
Test status
Simulation time 84353966952 ps
CPU time 27.61 seconds
Started May 26 02:16:05 PM PDT 24
Finished May 26 02:16:33 PM PDT 24
Peak memory 200524 kb
Host smart-aaa91ff6-2242-4eb3-899e-a3e735aab2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085686959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1085686959
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.961005954
Short name T910
Test name
Test status
Simulation time 216678302774 ps
CPU time 694.6 seconds
Started May 26 02:16:05 PM PDT 24
Finished May 26 02:27:40 PM PDT 24
Peak memory 214196 kb
Host smart-53ab240f-d71a-4898-bc3c-af9f86e2c7f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961005954 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.961005954
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3320291012
Short name T352
Test name
Test status
Simulation time 190279546283 ps
CPU time 336.94 seconds
Started May 26 02:16:04 PM PDT 24
Finished May 26 02:21:41 PM PDT 24
Peak memory 200552 kb
Host smart-68b60917-0e4c-4fa9-bcd2-b116567bca03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320291012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3320291012
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3350313804
Short name T69
Test name
Test status
Simulation time 92007804331 ps
CPU time 699.54 seconds
Started May 26 02:16:07 PM PDT 24
Finished May 26 02:27:47 PM PDT 24
Peak memory 225332 kb
Host smart-06ceba8c-657b-4c90-a39e-a8a54152f17a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350313804 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3350313804
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.591094332
Short name T525
Test name
Test status
Simulation time 81049030319 ps
CPU time 72.08 seconds
Started May 26 02:16:05 PM PDT 24
Finished May 26 02:17:17 PM PDT 24
Peak memory 200520 kb
Host smart-55a1310d-edd6-4be8-8331-785ef7ba6daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591094332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.591094332
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3051268582
Short name T1044
Test name
Test status
Simulation time 111150316810 ps
CPU time 637.55 seconds
Started May 26 02:16:04 PM PDT 24
Finished May 26 02:26:42 PM PDT 24
Peak memory 216968 kb
Host smart-f9332101-520c-4c83-bcde-0e70007cb6d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051268582 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3051268582
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2010571782
Short name T476
Test name
Test status
Simulation time 29712683816 ps
CPU time 5.66 seconds
Started May 26 02:16:06 PM PDT 24
Finished May 26 02:16:12 PM PDT 24
Peak memory 200580 kb
Host smart-0945c239-5217-4c13-9d2c-f6f2b7de8939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010571782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2010571782
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3600179121
Short name T115
Test name
Test status
Simulation time 28180146978 ps
CPU time 270.13 seconds
Started May 26 02:16:05 PM PDT 24
Finished May 26 02:20:36 PM PDT 24
Peak memory 217172 kb
Host smart-27e041f9-e6a2-4d26-a2f8-8d794dc39640
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600179121 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3600179121
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2421263748
Short name T149
Test name
Test status
Simulation time 136871999600 ps
CPU time 57.6 seconds
Started May 26 02:16:08 PM PDT 24
Finished May 26 02:17:06 PM PDT 24
Peak memory 200464 kb
Host smart-fb034de2-0c5b-472d-bc6c-c402614f6808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421263748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2421263748
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.12274319
Short name T951
Test name
Test status
Simulation time 360131448919 ps
CPU time 858.43 seconds
Started May 26 02:16:04 PM PDT 24
Finished May 26 02:30:24 PM PDT 24
Peak memory 217300 kb
Host smart-9b2c4942-9462-48a9-be0e-8d20de8554b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12274319 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.12274319
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2480377271
Short name T1085
Test name
Test status
Simulation time 11443180 ps
CPU time 0.61 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:13:03 PM PDT 24
Peak memory 194896 kb
Host smart-f9af6aa6-f038-4d6c-938a-bb09a471459f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480377271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2480377271
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1989600805
Short name T547
Test name
Test status
Simulation time 37216440670 ps
CPU time 63.52 seconds
Started May 26 02:13:03 PM PDT 24
Finished May 26 02:14:09 PM PDT 24
Peak memory 200556 kb
Host smart-69504731-505e-41b2-ad81-9b0c1bf71789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989600805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1989600805
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.4195423570
Short name T501
Test name
Test status
Simulation time 13527171575 ps
CPU time 13.67 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:13:18 PM PDT 24
Peak memory 200536 kb
Host smart-3b152fc3-1e1a-46ff-94e6-c1f99a6e50cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195423570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.4195423570
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1200965500
Short name T785
Test name
Test status
Simulation time 53536453644 ps
CPU time 23.21 seconds
Started May 26 02:13:03 PM PDT 24
Finished May 26 02:13:28 PM PDT 24
Peak memory 198652 kb
Host smart-a3dc3897-43fc-4419-9b28-3c6c154ec384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200965500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1200965500
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2827719075
Short name T792
Test name
Test status
Simulation time 26945139630 ps
CPU time 8.46 seconds
Started May 26 02:12:59 PM PDT 24
Finished May 26 02:13:09 PM PDT 24
Peak memory 198060 kb
Host smart-a98cc00d-1f33-48db-97e6-bccecfacdc78
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827719075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2827719075
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.868788118
Short name T424
Test name
Test status
Simulation time 186152514681 ps
CPU time 182.41 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:16:04 PM PDT 24
Peak memory 200492 kb
Host smart-b260fc1c-7cad-4a53-813c-a703474dd31b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868788118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.868788118
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3724632442
Short name T1157
Test name
Test status
Simulation time 81931209 ps
CPU time 0.63 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:13:05 PM PDT 24
Peak memory 196252 kb
Host smart-83374738-9562-4da0-8e67-5bd1f6a15577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724632442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3724632442
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.3460117294
Short name T925
Test name
Test status
Simulation time 19581772548 ps
CPU time 8.85 seconds
Started May 26 02:13:06 PM PDT 24
Finished May 26 02:13:16 PM PDT 24
Peak memory 195496 kb
Host smart-b402e923-3993-4c6d-8477-e650ce53c4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460117294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3460117294
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1373167626
Short name T497
Test name
Test status
Simulation time 5263426621 ps
CPU time 310.09 seconds
Started May 26 02:12:59 PM PDT 24
Finished May 26 02:18:10 PM PDT 24
Peak memory 200548 kb
Host smart-26cb442e-aa8c-4925-8ec4-e2994a7ad5c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373167626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1373167626
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3645485266
Short name T381
Test name
Test status
Simulation time 5469727647 ps
CPU time 30.87 seconds
Started May 26 02:12:58 PM PDT 24
Finished May 26 02:13:29 PM PDT 24
Peak memory 199692 kb
Host smart-0f31935b-14b2-4853-8e77-096fa7a3dcff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3645485266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3645485266
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3681282139
Short name T721
Test name
Test status
Simulation time 103246104796 ps
CPU time 18.36 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:13:21 PM PDT 24
Peak memory 200196 kb
Host smart-54fb8e20-b746-4a24-9de7-dcd949126672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681282139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3681282139
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2248452264
Short name T773
Test name
Test status
Simulation time 34585143436 ps
CPU time 3.73 seconds
Started May 26 02:12:58 PM PDT 24
Finished May 26 02:13:03 PM PDT 24
Peak memory 196556 kb
Host smart-12de3432-f3d3-40b0-93c5-c4b5f17158bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248452264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2248452264
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.714791350
Short name T1071
Test name
Test status
Simulation time 436815220 ps
CPU time 1.17 seconds
Started May 26 02:12:58 PM PDT 24
Finished May 26 02:13:01 PM PDT 24
Peak memory 199096 kb
Host smart-ff4ed20f-6baa-422b-98f4-a0ea68d037f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714791350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.714791350
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.114286629
Short name T731
Test name
Test status
Simulation time 758319697751 ps
CPU time 563.92 seconds
Started May 26 02:13:03 PM PDT 24
Finished May 26 02:22:29 PM PDT 24
Peak memory 217096 kb
Host smart-68a93daa-2852-44e5-93e1-50c019a567a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114286629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.114286629
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.868663969
Short name T842
Test name
Test status
Simulation time 21721914205 ps
CPU time 256.02 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:17:20 PM PDT 24
Peak memory 216860 kb
Host smart-8fb84e93-bf53-4d3d-935a-c815b6a534bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868663969 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.868663969
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1257896936
Short name T749
Test name
Test status
Simulation time 1854480573 ps
CPU time 1.61 seconds
Started May 26 02:13:03 PM PDT 24
Finished May 26 02:13:07 PM PDT 24
Peak memory 199000 kb
Host smart-b1ef7efa-43bd-4ad1-b817-1a073713f36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257896936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1257896936
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2192732818
Short name T411
Test name
Test status
Simulation time 17045512671 ps
CPU time 5.95 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:13:08 PM PDT 24
Peak memory 200156 kb
Host smart-5e4c72dc-2dbf-42e6-84cb-086a8a5f4138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192732818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2192732818
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1778677215
Short name T482
Test name
Test status
Simulation time 56975180980 ps
CPU time 19.82 seconds
Started May 26 02:16:05 PM PDT 24
Finished May 26 02:16:25 PM PDT 24
Peak memory 200440 kb
Host smart-004647b1-7f2b-4eff-9249-f3156915ab54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778677215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1778677215
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1587172632
Short name T978
Test name
Test status
Simulation time 87967996876 ps
CPU time 264.7 seconds
Started May 26 02:16:04 PM PDT 24
Finished May 26 02:20:29 PM PDT 24
Peak memory 217172 kb
Host smart-72f10769-63b5-4e5a-a9bb-3f3ce6d05452
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587172632 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1587172632
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3505483767
Short name T959
Test name
Test status
Simulation time 126547478493 ps
CPU time 55.2 seconds
Started May 26 02:16:06 PM PDT 24
Finished May 26 02:17:02 PM PDT 24
Peak memory 200540 kb
Host smart-ebcbc5c5-bc15-408f-a205-c394e9c2f45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505483767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3505483767
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3903141041
Short name T787
Test name
Test status
Simulation time 365350302494 ps
CPU time 1832.16 seconds
Started May 26 02:16:05 PM PDT 24
Finished May 26 02:46:38 PM PDT 24
Peak memory 230160 kb
Host smart-496607d7-27a8-4806-8184-1fd2bbfc0def
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903141041 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3903141041
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3477694081
Short name T927
Test name
Test status
Simulation time 32440463272 ps
CPU time 60.02 seconds
Started May 26 02:16:05 PM PDT 24
Finished May 26 02:17:05 PM PDT 24
Peak memory 200448 kb
Host smart-57994eb9-c8ba-44fd-9281-5574e8f4764d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477694081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3477694081
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.476138166
Short name T67
Test name
Test status
Simulation time 79945218176 ps
CPU time 190.26 seconds
Started May 26 02:16:04 PM PDT 24
Finished May 26 02:19:15 PM PDT 24
Peak memory 208696 kb
Host smart-79a243a6-10db-428b-81ff-8f5aba4ec71f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476138166 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.476138166
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2582817616
Short name T217
Test name
Test status
Simulation time 16881285927 ps
CPU time 26.34 seconds
Started May 26 02:16:05 PM PDT 24
Finished May 26 02:16:33 PM PDT 24
Peak memory 200496 kb
Host smart-2918be60-4419-4e43-95e9-375ad0dec322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582817616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2582817616
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2792493507
Short name T80
Test name
Test status
Simulation time 24215397688 ps
CPU time 775.34 seconds
Started May 26 02:16:12 PM PDT 24
Finished May 26 02:29:08 PM PDT 24
Peak memory 208804 kb
Host smart-e4683f82-d6f2-441e-91e2-b96089d7b4c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792493507 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2792493507
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3487939333
Short name T1145
Test name
Test status
Simulation time 115350536726 ps
CPU time 152.19 seconds
Started May 26 02:16:13 PM PDT 24
Finished May 26 02:18:46 PM PDT 24
Peak memory 200520 kb
Host smart-e956aa89-87d7-4013-becc-0414dec007f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487939333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3487939333
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.784735813
Short name T804
Test name
Test status
Simulation time 39899434525 ps
CPU time 350.01 seconds
Started May 26 02:16:11 PM PDT 24
Finished May 26 02:22:02 PM PDT 24
Peak memory 217268 kb
Host smart-fc68b45b-f303-471d-8511-4c09da28f001
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784735813 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.784735813
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.639645694
Short name T662
Test name
Test status
Simulation time 183349036358 ps
CPU time 336.18 seconds
Started May 26 02:16:13 PM PDT 24
Finished May 26 02:21:50 PM PDT 24
Peak memory 200552 kb
Host smart-45afca55-f919-41d5-b321-dd13ae13b206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639645694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.639645694
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2269711430
Short name T137
Test name
Test status
Simulation time 64687217443 ps
CPU time 206.28 seconds
Started May 26 02:16:13 PM PDT 24
Finished May 26 02:19:40 PM PDT 24
Peak memory 208844 kb
Host smart-03295f7b-8577-4c62-9568-4bc722d341bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269711430 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2269711430
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2552875041
Short name T191
Test name
Test status
Simulation time 32166909152 ps
CPU time 13.42 seconds
Started May 26 02:16:15 PM PDT 24
Finished May 26 02:16:29 PM PDT 24
Peak memory 200532 kb
Host smart-b0fab7ce-0069-4542-bb06-a4c1c1e9f7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552875041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2552875041
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.655326275
Short name T63
Test name
Test status
Simulation time 214622568439 ps
CPU time 594.28 seconds
Started May 26 02:16:11 PM PDT 24
Finished May 26 02:26:07 PM PDT 24
Peak memory 226468 kb
Host smart-a312707f-d235-4eff-bd5e-8bfb566834ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655326275 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.655326275
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.4010790978
Short name T1023
Test name
Test status
Simulation time 14850204069 ps
CPU time 31.91 seconds
Started May 26 02:16:13 PM PDT 24
Finished May 26 02:16:46 PM PDT 24
Peak memory 200532 kb
Host smart-b27c90f2-ce62-4f0c-a1e8-fdc318f3ca0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010790978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.4010790978
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2548380314
Short name T700
Test name
Test status
Simulation time 21870988256 ps
CPU time 250.79 seconds
Started May 26 02:16:13 PM PDT 24
Finished May 26 02:20:25 PM PDT 24
Peak memory 215984 kb
Host smart-dbba739d-1ae6-4a28-b71f-67e4e735c0d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548380314 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2548380314
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2184888494
Short name T1129
Test name
Test status
Simulation time 52361331004 ps
CPU time 21.94 seconds
Started May 26 02:16:11 PM PDT 24
Finished May 26 02:16:34 PM PDT 24
Peak memory 200528 kb
Host smart-6bce63d5-caa3-45ca-8d22-9f62e1399cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184888494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2184888494
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2484387074
Short name T257
Test name
Test status
Simulation time 182463637729 ps
CPU time 1052.51 seconds
Started May 26 02:16:10 PM PDT 24
Finished May 26 02:33:43 PM PDT 24
Peak memory 217024 kb
Host smart-55d3a8bb-786e-4a59-8b16-5b6dac9ad576
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484387074 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2484387074
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1508269899
Short name T993
Test name
Test status
Simulation time 206632316519 ps
CPU time 92.95 seconds
Started May 26 02:16:16 PM PDT 24
Finished May 26 02:17:49 PM PDT 24
Peak memory 200512 kb
Host smart-7ca165f4-ec99-4392-b41c-80f3c5b14188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508269899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1508269899
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.957561840
Short name T753
Test name
Test status
Simulation time 622369240754 ps
CPU time 498.36 seconds
Started May 26 02:16:12 PM PDT 24
Finished May 26 02:24:31 PM PDT 24
Peak memory 213452 kb
Host smart-be8f5434-95d2-4645-93db-8eb47b1ce3db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957561840 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.957561840
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3739060047
Short name T897
Test name
Test status
Simulation time 14464062 ps
CPU time 0.59 seconds
Started May 26 02:12:59 PM PDT 24
Finished May 26 02:13:01 PM PDT 24
Peak memory 195924 kb
Host smart-956de85c-a675-4214-ab32-6f59bbbf01d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739060047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3739060047
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3203957896
Short name T477
Test name
Test status
Simulation time 77998636091 ps
CPU time 35.28 seconds
Started May 26 02:12:59 PM PDT 24
Finished May 26 02:13:35 PM PDT 24
Peak memory 200540 kb
Host smart-af0fa38a-9418-4e8b-9fef-1b8b0e855ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203957896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3203957896
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1883760838
Short name T1080
Test name
Test status
Simulation time 143533828800 ps
CPU time 124.98 seconds
Started May 26 02:13:03 PM PDT 24
Finished May 26 02:15:10 PM PDT 24
Peak memory 200540 kb
Host smart-cbb9e30f-1e20-4daa-948e-22566923de95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883760838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1883760838
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.801200481
Short name T185
Test name
Test status
Simulation time 18694801477 ps
CPU time 8.62 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:13:11 PM PDT 24
Peak memory 200492 kb
Host smart-897de174-2acb-430f-9866-95dfe4c652af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801200481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.801200481
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.67260453
Short name T1116
Test name
Test status
Simulation time 55026811955 ps
CPU time 9.34 seconds
Started May 26 02:12:59 PM PDT 24
Finished May 26 02:13:10 PM PDT 24
Peak memory 200400 kb
Host smart-e57d169a-af71-4086-a4a8-5f0f1e27e9a1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67260453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.67260453
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2673723423
Short name T58
Test name
Test status
Simulation time 50615397589 ps
CPU time 159.35 seconds
Started May 26 02:12:58 PM PDT 24
Finished May 26 02:15:39 PM PDT 24
Peak memory 200452 kb
Host smart-61850928-33de-42a5-9087-efcf8c811e1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2673723423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2673723423
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.961573641
Short name T659
Test name
Test status
Simulation time 213208284 ps
CPU time 0.87 seconds
Started May 26 02:12:59 PM PDT 24
Finished May 26 02:13:01 PM PDT 24
Peak memory 196524 kb
Host smart-8a4b4e86-a9d2-4ba3-b880-f06a5a68723c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961573641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.961573641
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1622692014
Short name T349
Test name
Test status
Simulation time 37214944711 ps
CPU time 28.41 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:13:32 PM PDT 24
Peak memory 198948 kb
Host smart-ff924821-6fcc-4b9c-97e7-261660d6f5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622692014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1622692014
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.285876524
Short name T1058
Test name
Test status
Simulation time 18791340245 ps
CPU time 886.12 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:27:48 PM PDT 24
Peak memory 200656 kb
Host smart-99a926e8-414c-4028-9299-1f499121b4ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=285876524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.285876524
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.599329776
Short name T576
Test name
Test status
Simulation time 2539859968 ps
CPU time 4.14 seconds
Started May 26 02:12:59 PM PDT 24
Finished May 26 02:13:04 PM PDT 24
Peak memory 198700 kb
Host smart-de8979ea-0370-4688-b0fc-00a68d63c171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=599329776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.599329776
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2463461428
Short name T990
Test name
Test status
Simulation time 1560298925 ps
CPU time 3 seconds
Started May 26 02:13:00 PM PDT 24
Finished May 26 02:13:04 PM PDT 24
Peak memory 195924 kb
Host smart-788875b6-c438-4630-94bb-6201a38aeed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463461428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2463461428
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.513238297
Short name T508
Test name
Test status
Simulation time 6187502456 ps
CPU time 5.23 seconds
Started May 26 02:13:00 PM PDT 24
Finished May 26 02:13:07 PM PDT 24
Peak memory 200236 kb
Host smart-5d185d7a-6910-4750-afcd-2055d85dda28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513238297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.513238297
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2945832033
Short name T954
Test name
Test status
Simulation time 88057795793 ps
CPU time 361.75 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:19:04 PM PDT 24
Peak memory 200468 kb
Host smart-8a953979-a39c-44fc-90ab-7960cd949c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945832033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2945832033
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2816866638
Short name T1016
Test name
Test status
Simulation time 18731413376 ps
CPU time 220.49 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:16:45 PM PDT 24
Peak memory 216172 kb
Host smart-8f3e5aa1-37de-433e-8639-a19b17cac698
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816866638 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2816866638
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1143772641
Short name T19
Test name
Test status
Simulation time 2817283267 ps
CPU time 2.42 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:13:05 PM PDT 24
Peak memory 199064 kb
Host smart-398e8506-0696-491d-a6b5-d172ad1509c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143772641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1143772641
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3521134815
Short name T258
Test name
Test status
Simulation time 116539292948 ps
CPU time 72.7 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:14:14 PM PDT 24
Peak memory 200468 kb
Host smart-6b846937-ad30-4132-b39c-7fd82f52a825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521134815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3521134815
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2691758419
Short name T766
Test name
Test status
Simulation time 54121131685 ps
CPU time 1055.91 seconds
Started May 26 02:16:13 PM PDT 24
Finished May 26 02:33:50 PM PDT 24
Peak memory 217388 kb
Host smart-fa303f18-c211-45e1-baa4-8dc3be59ca3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691758419 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2691758419
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.673592207
Short name T607
Test name
Test status
Simulation time 39222154386 ps
CPU time 57.29 seconds
Started May 26 02:16:15 PM PDT 24
Finished May 26 02:17:13 PM PDT 24
Peak memory 200508 kb
Host smart-f605cdca-2d86-49bc-b454-ce2e1667bedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673592207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.673592207
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2169930198
Short name T702
Test name
Test status
Simulation time 240869593995 ps
CPU time 1118.6 seconds
Started May 26 02:16:14 PM PDT 24
Finished May 26 02:34:53 PM PDT 24
Peak memory 217248 kb
Host smart-dee669dc-f7dc-4010-9bcf-dcb9f5e0763c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169930198 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2169930198
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.4023318365
Short name T953
Test name
Test status
Simulation time 17206775382 ps
CPU time 29.6 seconds
Started May 26 02:16:15 PM PDT 24
Finished May 26 02:16:46 PM PDT 24
Peak memory 200404 kb
Host smart-1671ba69-99ca-4e22-87ad-8928b6e98a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023318365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.4023318365
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1262719205
Short name T1078
Test name
Test status
Simulation time 90438848117 ps
CPU time 453.27 seconds
Started May 26 02:16:10 PM PDT 24
Finished May 26 02:23:44 PM PDT 24
Peak memory 216496 kb
Host smart-a43cb7ca-4799-4183-bc2a-f3ce2d846546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262719205 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1262719205
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3867386696
Short name T247
Test name
Test status
Simulation time 501286242305 ps
CPU time 1374.02 seconds
Started May 26 02:16:19 PM PDT 24
Finished May 26 02:39:14 PM PDT 24
Peak memory 225488 kb
Host smart-8f2914dd-6b3d-4b18-8fbd-5c23deb29fe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867386696 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3867386696
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1298450164
Short name T309
Test name
Test status
Simulation time 53594926871 ps
CPU time 56.97 seconds
Started May 26 02:16:22 PM PDT 24
Finished May 26 02:17:19 PM PDT 24
Peak memory 200556 kb
Host smart-11159580-0ec6-4671-b618-c8560b01c9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298450164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1298450164
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.248349785
Short name T27
Test name
Test status
Simulation time 126713722711 ps
CPU time 513.26 seconds
Started May 26 02:16:19 PM PDT 24
Finished May 26 02:24:54 PM PDT 24
Peak memory 216940 kb
Host smart-eae5bc25-9aad-4a84-9b3e-00982663e961
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248349785 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.248349785
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3043936641
Short name T194
Test name
Test status
Simulation time 18474936208 ps
CPU time 18.5 seconds
Started May 26 02:16:19 PM PDT 24
Finished May 26 02:16:39 PM PDT 24
Peak memory 200468 kb
Host smart-4309acd5-550a-4c95-b527-76a13d0e5d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043936641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3043936641
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3840537639
Short name T295
Test name
Test status
Simulation time 67056597963 ps
CPU time 188.53 seconds
Started May 26 02:16:25 PM PDT 24
Finished May 26 02:19:34 PM PDT 24
Peak memory 208832 kb
Host smart-73636d45-dc86-4988-bf6a-0566e9d2ca54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840537639 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3840537639
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1739871137
Short name T930
Test name
Test status
Simulation time 42454283796 ps
CPU time 32.41 seconds
Started May 26 02:16:20 PM PDT 24
Finished May 26 02:16:53 PM PDT 24
Peak memory 200348 kb
Host smart-4df856eb-5025-4d3a-b66a-8f2ee5db9d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739871137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1739871137
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2736190801
Short name T421
Test name
Test status
Simulation time 66611192123 ps
CPU time 51.9 seconds
Started May 26 02:16:18 PM PDT 24
Finished May 26 02:17:10 PM PDT 24
Peak memory 200488 kb
Host smart-ab00b346-bbab-480c-b2c0-199b948c1203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736190801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2736190801
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3705152250
Short name T1007
Test name
Test status
Simulation time 104396679307 ps
CPU time 785.48 seconds
Started May 26 02:16:19 PM PDT 24
Finished May 26 02:29:25 PM PDT 24
Peak memory 224872 kb
Host smart-f03d6c61-5e22-4a0d-a8a1-c65ed4137ada
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705152250 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3705152250
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.4160946097
Short name T1068
Test name
Test status
Simulation time 105376607844 ps
CPU time 276.04 seconds
Started May 26 02:16:20 PM PDT 24
Finished May 26 02:20:57 PM PDT 24
Peak memory 200492 kb
Host smart-f100f0e7-787e-454f-ba79-9d0496cbcf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160946097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.4160946097
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.174444132
Short name T941
Test name
Test status
Simulation time 52376862219 ps
CPU time 863.97 seconds
Started May 26 02:16:20 PM PDT 24
Finished May 26 02:30:45 PM PDT 24
Peak memory 217028 kb
Host smart-b0f62560-ae00-424a-a705-ed0c7264918b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174444132 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.174444132
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3131544412
Short name T220
Test name
Test status
Simulation time 10139940950 ps
CPU time 19.88 seconds
Started May 26 02:16:21 PM PDT 24
Finished May 26 02:16:42 PM PDT 24
Peak memory 200540 kb
Host smart-16215096-c729-438c-899e-091a92bf1c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131544412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3131544412
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2724331195
Short name T802
Test name
Test status
Simulation time 74577439530 ps
CPU time 931.32 seconds
Started May 26 02:16:20 PM PDT 24
Finished May 26 02:31:53 PM PDT 24
Peak memory 226852 kb
Host smart-90b4749a-2e9d-4a22-b6db-dd26b84c44f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724331195 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2724331195
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.349472972
Short name T439
Test name
Test status
Simulation time 21258447 ps
CPU time 0.61 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:13:03 PM PDT 24
Peak memory 195840 kb
Host smart-2b03f818-fe2b-4709-bb4b-b4e869b4deab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349472972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.349472972
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2191708051
Short name T760
Test name
Test status
Simulation time 166501946706 ps
CPU time 102.31 seconds
Started May 26 02:13:06 PM PDT 24
Finished May 26 02:14:49 PM PDT 24
Peak memory 200556 kb
Host smart-7915cb83-ae80-452c-99be-ae7a61daf1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191708051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2191708051
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1945759808
Short name T657
Test name
Test status
Simulation time 23788138263 ps
CPU time 22.31 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:13:26 PM PDT 24
Peak memory 200456 kb
Host smart-9d6b826c-768e-4081-b126-0c5b9004f8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945759808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1945759808
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3107866889
Short name T196
Test name
Test status
Simulation time 53716254930 ps
CPU time 121.92 seconds
Started May 26 02:13:00 PM PDT 24
Finished May 26 02:15:03 PM PDT 24
Peak memory 200572 kb
Host smart-db83161d-c151-4481-8fd1-3281a5510078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107866889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3107866889
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.149474800
Short name T128
Test name
Test status
Simulation time 8484451245 ps
CPU time 7.08 seconds
Started May 26 02:13:03 PM PDT 24
Finished May 26 02:13:12 PM PDT 24
Peak memory 199948 kb
Host smart-c20603b1-1c21-4eea-8b8a-526b025a747f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149474800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.149474800
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1094387335
Short name T264
Test name
Test status
Simulation time 59246972633 ps
CPU time 204.88 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:16:27 PM PDT 24
Peak memory 200464 kb
Host smart-3aa4677e-976d-4fea-99c3-46630de05552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1094387335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1094387335
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3991381240
Short name T1024
Test name
Test status
Simulation time 1306922711 ps
CPU time 4.61 seconds
Started May 26 02:13:03 PM PDT 24
Finished May 26 02:13:09 PM PDT 24
Peak memory 198244 kb
Host smart-cee57134-47da-4c42-9b2d-fae18955d6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991381240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3991381240
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3128400357
Short name T643
Test name
Test status
Simulation time 121399397187 ps
CPU time 57.85 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:14:01 PM PDT 24
Peak memory 200200 kb
Host smart-c3d489b0-af5f-4f9b-8187-0e4c1e5d583f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128400357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3128400357
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.812679386
Short name T693
Test name
Test status
Simulation time 17356769536 ps
CPU time 952.61 seconds
Started May 26 02:13:15 PM PDT 24
Finished May 26 02:29:11 PM PDT 24
Peak memory 200572 kb
Host smart-68d6341a-2b53-42f4-ad80-bfcb94360f13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=812679386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.812679386
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1565034940
Short name T130
Test name
Test status
Simulation time 6960394184 ps
CPU time 16.74 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:13:20 PM PDT 24
Peak memory 198860 kb
Host smart-fa42e96f-2447-47bc-a79c-c5bbeb3c8380
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1565034940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1565034940
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3256080105
Short name T896
Test name
Test status
Simulation time 23219326603 ps
CPU time 11.73 seconds
Started May 26 02:13:04 PM PDT 24
Finished May 26 02:13:17 PM PDT 24
Peak memory 200488 kb
Host smart-3303ae80-6672-4dce-8817-8b58b971a274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256080105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3256080105
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1107122079
Short name T1107
Test name
Test status
Simulation time 37936511224 ps
CPU time 56.34 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:14:00 PM PDT 24
Peak memory 196348 kb
Host smart-c4eeecbd-04ff-4f5a-92e2-9311244df24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107122079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1107122079
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3605919801
Short name T862
Test name
Test status
Simulation time 317450368 ps
CPU time 1.01 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:13:05 PM PDT 24
Peak memory 198848 kb
Host smart-88c21529-dcf5-4a00-913e-33e396fb0c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605919801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3605919801
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3844729149
Short name T204
Test name
Test status
Simulation time 442317422901 ps
CPU time 219.29 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:16:43 PM PDT 24
Peak memory 200524 kb
Host smart-31224055-e1d0-48db-9963-0b67c8c15c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844729149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3844729149
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1546235814
Short name T337
Test name
Test status
Simulation time 26816659585 ps
CPU time 327.36 seconds
Started May 26 02:13:02 PM PDT 24
Finished May 26 02:18:31 PM PDT 24
Peak memory 216664 kb
Host smart-37a8636a-4342-43fa-a5d3-f21c4c39d266
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546235814 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1546235814
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.450264087
Short name T20
Test name
Test status
Simulation time 1648951565 ps
CPU time 1.49 seconds
Started May 26 02:13:05 PM PDT 24
Finished May 26 02:13:07 PM PDT 24
Peak memory 198456 kb
Host smart-c3465757-5829-44e1-a672-a537b5a08459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450264087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.450264087
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.183539226
Short name T942
Test name
Test status
Simulation time 64684413635 ps
CPU time 31 seconds
Started May 26 02:13:01 PM PDT 24
Finished May 26 02:13:33 PM PDT 24
Peak memory 200616 kb
Host smart-cbb3acd1-f64c-4ab1-a855-6729cf707886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183539226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.183539226
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3707050445
Short name T234
Test name
Test status
Simulation time 243631218925 ps
CPU time 69.92 seconds
Started May 26 02:16:20 PM PDT 24
Finished May 26 02:17:31 PM PDT 24
Peak memory 200556 kb
Host smart-07226b72-8845-4b5c-b4a5-bae28429419c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707050445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3707050445
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2633378257
Short name T500
Test name
Test status
Simulation time 38516589911 ps
CPU time 111.71 seconds
Started May 26 02:16:24 PM PDT 24
Finished May 26 02:18:17 PM PDT 24
Peak memory 211828 kb
Host smart-4dca8484-b9b3-4d70-becf-0379019a36db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633378257 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2633378257
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3002099735
Short name T315
Test name
Test status
Simulation time 208249065587 ps
CPU time 31.62 seconds
Started May 26 02:16:20 PM PDT 24
Finished May 26 02:16:52 PM PDT 24
Peak memory 199444 kb
Host smart-6149427d-5a69-49a9-b074-00a416514396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002099735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3002099735
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3828860638
Short name T255
Test name
Test status
Simulation time 145295882101 ps
CPU time 65.79 seconds
Started May 26 02:16:21 PM PDT 24
Finished May 26 02:17:28 PM PDT 24
Peak memory 200508 kb
Host smart-8f3c4549-fb3c-40ac-9db7-d01a06072069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828860638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3828860638
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3466742024
Short name T187
Test name
Test status
Simulation time 92744044104 ps
CPU time 547.33 seconds
Started May 26 02:16:19 PM PDT 24
Finished May 26 02:25:28 PM PDT 24
Peak memory 211200 kb
Host smart-6a8e3ca2-beb1-4fc6-a8a5-91fabcb485df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466742024 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3466742024
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.4288750313
Short name T262
Test name
Test status
Simulation time 79609016481 ps
CPU time 157.26 seconds
Started May 26 02:16:20 PM PDT 24
Finished May 26 02:18:58 PM PDT 24
Peak memory 200536 kb
Host smart-de86c757-242a-46aa-9cf7-1e7b63c62bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288750313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.4288750313
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.875150283
Short name T347
Test name
Test status
Simulation time 108118888663 ps
CPU time 184.18 seconds
Started May 26 02:16:20 PM PDT 24
Finished May 26 02:19:25 PM PDT 24
Peak memory 200576 kb
Host smart-185fbd86-1afd-40e5-bf1f-f47109e073b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875150283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.875150283
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.848968847
Short name T61
Test name
Test status
Simulation time 52205269135 ps
CPU time 585.98 seconds
Started May 26 02:16:20 PM PDT 24
Finished May 26 02:26:07 PM PDT 24
Peak memory 225444 kb
Host smart-2851437e-d974-4f21-b465-1116f1ee9671
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848968847 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.848968847
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3936910699
Short name T351
Test name
Test status
Simulation time 35026959730 ps
CPU time 54.14 seconds
Started May 26 02:16:21 PM PDT 24
Finished May 26 02:17:16 PM PDT 24
Peak memory 200584 kb
Host smart-c91800b9-5512-4afe-b16c-c326b2a9d50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936910699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3936910699
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1252953277
Short name T764
Test name
Test status
Simulation time 63581497202 ps
CPU time 111.01 seconds
Started May 26 02:16:21 PM PDT 24
Finished May 26 02:18:13 PM PDT 24
Peak memory 200524 kb
Host smart-774494fa-9459-4a94-8c7a-98dd0a040ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252953277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1252953277
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.583373012
Short name T79
Test name
Test status
Simulation time 335997893016 ps
CPU time 2249.51 seconds
Started May 26 02:16:21 PM PDT 24
Finished May 26 02:53:52 PM PDT 24
Peak memory 241596 kb
Host smart-b4066607-d4ed-4380-ac1d-bbc8cbdf19e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583373012 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.583373012
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1833080109
Short name T704
Test name
Test status
Simulation time 256427308427 ps
CPU time 84.84 seconds
Started May 26 02:16:27 PM PDT 24
Finished May 26 02:17:53 PM PDT 24
Peak memory 200560 kb
Host smart-34452937-9afa-4f10-bdf7-eab3ba1367d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833080109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1833080109
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3481000022
Short name T68
Test name
Test status
Simulation time 323719272166 ps
CPU time 618.33 seconds
Started May 26 02:16:28 PM PDT 24
Finished May 26 02:26:47 PM PDT 24
Peak memory 217032 kb
Host smart-9aaf4538-a425-409d-b1b1-e9f003409eb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481000022 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3481000022
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.4199500016
Short name T203
Test name
Test status
Simulation time 112969103444 ps
CPU time 334.02 seconds
Started May 26 02:16:28 PM PDT 24
Finished May 26 02:22:03 PM PDT 24
Peak memory 200452 kb
Host smart-937b4d6c-9451-45a7-bd77-bd8f13d2edbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199500016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.4199500016
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3743051872
Short name T765
Test name
Test status
Simulation time 215544639729 ps
CPU time 661.51 seconds
Started May 26 02:16:27 PM PDT 24
Finished May 26 02:27:29 PM PDT 24
Peak memory 216232 kb
Host smart-1ca961be-0889-4d2d-8a0f-0fe0bf518249
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743051872 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3743051872
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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