Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	106980	1			T1	164		T2	2		T3	1
all_values[1]	106980	1			T1	164		T2	2		T3	1
all_values[2]	106980	1			T1	164		T2	2		T3	1
all_values[3]	106980	1			T1	164		T2	2		T3	1
all_values[4]	106980	1			T1	164		T2	2		T3	1
all_values[5]	106980	1			T1	164		T2	2		T3	1
all_values[6]	106980	1			T1	164		T2	2		T3	1
all_values[7]	106980	1			T1	164		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

435941

1

T1

588

T2

16

T3

5

auto[1]

419899

1

T1

724

T3

3

T4

141

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

801476

1

T1

1162

T2

13

T3

7

auto[1]

54364

1

T1

150

T2

3

T3

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	33032	1			T1	32		T4	9		T5	46
all_values[0]	auto[0]	auto[1]	22094	1			T1	88		T2	2		T5	3
all_values[0]	auto[1]	auto[0]	30876	1			T1	15		T4	7		T5	4
all_values[0]	auto[1]	auto[1]	20978	1			T1	29		T3	1		T4	18
all_values[1]	auto[0]	auto[0]	52084	1			T1	35		T2	2		T3	1
all_values[1]	auto[0]	auto[1]	1703	1			T1	2		T4	7		T5	3
all_values[1]	auto[1]	auto[0]	51535	1			T1	121		T4	26		T5	59
all_values[1]	auto[1]	auto[1]	1658	1			T1	6		T5	2		T12	24
all_values[2]	auto[0]	auto[0]	49322	1			T1	53		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2577	1			T1	3		T2	1		T4	2
all_values[2]	auto[1]	auto[0]	52703	1			T1	96		T5	21		T6	17
all_values[2]	auto[1]	auto[1]	2378	1			T1	12		T4	2		T5	1
all_values[3]	auto[0]	auto[0]	53440	1			T1	103		T2	2		T4	23
all_values[3]	auto[0]	auto[1]	293	1			T12	1		T15	1		T13	1
all_values[3]	auto[1]	auto[0]	52939	1			T1	61		T3	1		T4	11
all_values[3]	auto[1]	auto[1]	308	1			T12	1		T14	1		T48	1
all_values[4]	auto[0]	auto[0]	55643	1			T1	63		T2	2		T3	1
all_values[4]	auto[0]	auto[1]	470	1			T1	1		T17	6		T27	1
all_values[4]	auto[1]	auto[0]	50377	1			T1	99		T4	8		T5	34
all_values[4]	auto[1]	auto[1]	490	1			T1	1		T15	1		T18	2
all_values[5]	auto[0]	auto[0]	56048	1			T1	74		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	178	1			T15	1		T18	1		T35	2
all_values[5]	auto[1]	auto[0]	50585	1			T1	90		T4	17		T5	27
all_values[5]	auto[1]	auto[1]	169	1			T15	1		T18	2		T27	3
all_values[6]	auto[0]	auto[0]	56576	1			T1	94		T2	2		T4	8
all_values[6]	auto[0]	auto[1]	205	1			T1	2		T15	2		T18	1
all_values[6]	auto[1]	auto[0]	50022	1			T1	66		T3	1		T4	26
all_values[6]	auto[1]	auto[1]	177	1			T1	2		T35	2		T36	1
all_values[7]	auto[0]	auto[0]	51973	1			T1	35		T2	2		T3	1
all_values[7]	auto[0]	auto[1]	303	1			T1	3		T18	2		T27	1
all_values[7]	auto[1]	auto[0]	54321	1			T1	125		T4	26		T5	43
all_values[7]	auto[1]	auto[1]	383	1			T1	1		T18	2		T27	2