Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2231	1			T1	8		T3	16		T4	2
auto[BaudRate115200]	1923	1			T1	3		T4	1		T5	3
auto[BaudRate230400]	2001	1			T1	2		T2	1		T4	1
auto[BaudRate128Kbps]	1878	1			T1	3		T2	1		T4	1
auto[BaudRate256Kbps]	2012	1			T1	8		T4	2		T5	2
auto[BaudRate1Mbps]	1777	1			T1	3		T4	3		T8	3
auto[BaudRate1p5Mbps]	1258	1			T1	4		T5	2		T6	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1352	1			T7	2		T130	1		T132	9
freqs[25]	1166	1			T44	5		T197	9		T300	2
freqs[48]	499	1			T13	21		T46	12		T278	7
freqs[50]	666	1			T12	8		T105	11		T134	36
freqs[100]	1306	1			T1	31		T2	2		T126	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	218	1			T132	2		T296	1		T339	10
auto[BaudRate9600]	freqs[25]	178	1			T44	2		T197	2		T340	3
auto[BaudRate9600]	freqs[48]	102	1			T46	3		T278	2		T279	2
auto[BaudRate9600]	freqs[50]	116	1			T12	3		T105	4		T294	2
auto[BaudRate9600]	freqs[100]	211	1			T1	8		T289	1		T281	1
auto[BaudRate115200]	freqs[24]	207	1			T132	2		T271	1		T274	2
auto[BaudRate115200]	freqs[25]	188	1			T44	2		T197	1		T340	6
auto[BaudRate115200]	freqs[48]	62	1			T13	4		T46	1		T278	2
auto[BaudRate115200]	freqs[50]	94	1			T105	2		T134	2		T294	1
auto[BaudRate115200]	freqs[100]	201	1			T1	3		T126	1		T24	3
auto[BaudRate230400]	freqs[24]	183	1			T7	1		T132	1		T296	1
auto[BaudRate230400]	freqs[25]	185	1			T197	2		T300	2		T340	3
auto[BaudRate230400]	freqs[48]	65	1			T51	2		T279	2		T191	1
auto[BaudRate230400]	freqs[50]	100	1			T12	3		T105	1		T134	7
auto[BaudRate230400]	freqs[100]	183	1			T1	2		T2	1		T126	1
auto[BaudRate128Kbps]	freqs[24]	232	1			T7	1		T132	2		T271	1
auto[BaudRate128Kbps]	freqs[25]	159	1			T44	1		T197	1		T340	3
auto[BaudRate128Kbps]	freqs[48]	57	1			T13	2		T46	1		T278	2
auto[BaudRate128Kbps]	freqs[50]	76	1			T105	1		T294	1		T58	12
auto[BaudRate128Kbps]	freqs[100]	157	1			T1	3		T2	1		T126	1
auto[BaudRate256Kbps]	freqs[24]	192	1			T132	1		T271	1		T274	2
auto[BaudRate256Kbps]	freqs[25]	182	1			T197	1		T340	6		T341	6
auto[BaudRate256Kbps]	freqs[48]	81	1			T13	10		T46	1		T278	1
auto[BaudRate256Kbps]	freqs[50]	83	1			T12	1		T105	1		T134	12
auto[BaudRate256Kbps]	freqs[100]	191	1			T1	8		T24	6		T26	2
auto[BaudRate1Mbps]	freqs[24]	215	1			T132	1		T271	1		T274	2
auto[BaudRate1Mbps]	freqs[25]	171	1			T197	2		T341	15		T103	1
auto[BaudRate1Mbps]	freqs[48]	76	1			T13	2		T46	2		T279	2
auto[BaudRate1Mbps]	freqs[50]	100	1			T134	5		T294	3		T58	13
auto[BaudRate1Mbps]	freqs[100]	160	1			T1	3		T126	2		T26	1
auto[BaudRate1p5Mbps]	freqs[25]	103	1			T340	3		T341	3		T18	8
auto[BaudRate1p5Mbps]	freqs[48]	56	1			T13	3		T46	4		T279	3
auto[BaudRate1p5Mbps]	freqs[50]	97	1			T12	1		T105	2		T134	10
auto[BaudRate1p5Mbps]	freqs[100]	203	1			T1	4		T26	1		T273	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded