Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	8	122	93.85

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	8	122	93.85	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	31431050	1			T1	346		T3	1		T4	48
all_levels[1]	188134	1			T1	77		T5	31		T6	5
all_levels[2]	2561	1			T1	11		T5	3		T6	1
all_levels[3]	1055	1			T1	16		T44	4		T125	1
all_levels[4]	709	1			T1	7		T5	1		T12	1
all_levels[5]	477	1			T1	5		T5	1		T44	2
all_levels[6]	421	1			T1	5		T42	1		T126	1
all_levels[7]	318	1			T1	5		T127	3		T128	1
all_levels[8]	304	1			T1	6		T128	1		T129	2
all_levels[9]	267	1			T127	1		T13	2		T128	1
all_levels[10]	182	1			T1	2		T5	3		T128	1
all_levels[11]	179	1			T1	2		T17	1		T129	2
all_levels[12]	152	1			T4	1		T127	1		T130	1
all_levels[13]	141	1			T1	2		T127	1		T47	1
all_levels[14]	118	1			T1	1		T4	2		T44	1
all_levels[15]	124	1			T47	1		T103	2		T131	1
all_levels[16]	100	1			T1	1		T127	1		T13	1
all_levels[17]	97	1			T1	1		T12	1		T125	1
all_levels[18]	81	1			T1	1		T14	1		T113	1
all_levels[19]	94	1			T1	1		T4	2		T12	1
all_levels[20]	73	1			T129	1		T113	1		T131	2
all_levels[21]	67	1			T129	1		T132	1		T113	1
all_levels[22]	51	1			T14	1		T133	1		T134	1
all_levels[23]	58	1			T4	1		T135	2		T53	1
all_levels[24]	51	1			T115	1		T14	2		T26	2
all_levels[25]	57	1			T5	1		T136	1		T115	1
all_levels[26]	54	1			T12	4		T113	1		T137	1
all_levels[27]	62	1			T125	1		T47	1		T129	1
all_levels[28]	40	1			T44	1		T135	2		T138	1
all_levels[29]	45	1			T1	1		T12	1		T129	2
all_levels[30]	31	1			T125	1		T135	1		T26	1
all_levels[31]	39	1			T127	1		T139	1		T134	1
all_levels[32]	34	1			T1	1		T35	1		T54	1
all_levels[33]	23	1			T129	2		T136	1		T140	1
all_levels[34]	28	1			T135	2		T54	2		T114	1
all_levels[35]	34	1			T13	3		T139	1		T141	1
all_levels[36]	33	1			T142	1		T143	1		T144	1
all_levels[37]	47	1			T145	2		T131	1		T139	1
all_levels[38]	21	1			T145	1		T146	1		T147	1
all_levels[39]	18	1			T148	1		T149	2		T150	1
all_levels[40]	29	1			T115	1		T28	1		T151	2
all_levels[41]	14	1			T150	1		T152	1		T153	1
all_levels[42]	17	1			T28	1		T140	1		T154	2
all_levels[43]	16	1			T1	1		T155	1		T156	1
all_levels[44]	23	1			T39	1		T157	1		T147	1
all_levels[45]	11	1			T143	1		T158	1		T159	1
all_levels[46]	11	1			T132	2		T160	1		T161	2
all_levels[47]	8	1			T150	1		T144	1		T162	1
all_levels[48]	16	1			T163	1		T164	1		T165	1
all_levels[49]	12	1			T111	1		T166	1		T167	1
all_levels[50]	22	1			T1	1		T156	1		T168	1
all_levels[51]	14	1			T124	1		T111	1		T169	1
all_levels[52]	7	1			T170	1		T171	1		T172	1
all_levels[53]	10	1			T140	1		T147	1		T173	3
all_levels[54]	9	1			T174	1		T175	1		T176	1
all_levels[55]	12	1			T146	1		T111	1		T177	1
all_levels[56]	11	1			T151	1		T175	1		T143	1
all_levels[57]	4	1			T178	1		T179	1		T180	1
all_levels[58]	7	1			T181	2		T182	1		T183	1
all_levels[59]	3	1			T175	1		T184	1		T185	1
all_levels[60]	9	1			T144	1		T186	1		T187	1
all_levels[61]	14	1			T47	2		T188	3		T139	1
all_levels[62]	11	1			T189	1		T38	1		T190	2
all_levels[63]	10	1			T174	1		T111	1		T176	1
all_levels[64]	130	1			T14	1		T48	2		T191	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31623316

1

T1

493

T4

45

T5

269

auto[1]

4544

1

T3

1

T4

9

T5

8

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	8	122	93.85	8

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[31]]	[auto[1]]	0	1	1
[all_levels[47] , all_levels[48] , all_levels[49]]	[auto[1]]	--	--	3
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[57]]	[auto[1]]	0	1	1
[all_levels[59]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	31426940	1			T1	346		T4	41		T5	233
all_levels[0]	auto[1]	4110	1			T3	1		T4	7		T5	4
all_levels[1]	auto[0]	188059	1			T1	77		T5	29		T6	5
all_levels[1]	auto[1]	75	1			T5	2		T129	3		T135	3
all_levels[2]	auto[0]	2545	1			T1	11		T5	3		T6	1
all_levels[2]	auto[1]	16	1			T192	1		T193	1		T194	1
all_levels[3]	auto[0]	1040	1			T1	16		T44	3		T125	1
all_levels[3]	auto[1]	15	1			T44	1		T147	2		T195	1
all_levels[4]	auto[0]	681	1			T1	7		T5	1		T12	1
all_levels[4]	auto[1]	28	1			T56	3		T77	1		T196	1
all_levels[5]	auto[0]	457	1			T1	5		T5	1		T44	2
all_levels[5]	auto[1]	20	1			T127	2		T197	1		T135	1
all_levels[6]	auto[0]	399	1			T1	5		T42	1		T126	1
all_levels[6]	auto[1]	22	1			T56	1		T116	1		T147	1
all_levels[7]	auto[0]	310	1			T1	5		T127	3		T128	1
all_levels[7]	auto[1]	8	1			T188	1		T55	2		T198	1
all_levels[8]	auto[0]	290	1			T1	6		T128	1		T129	2
all_levels[8]	auto[1]	14	1			T48	1		T199	1		T200	2
all_levels[9]	auto[0]	258	1			T127	1		T13	2		T128	1
all_levels[9]	auto[1]	9	1			T201	2		T202	2		T203	1
all_levels[10]	auto[0]	173	1			T1	2		T5	1		T128	1
all_levels[10]	auto[1]	9	1			T5	2		T135	1		T204	1
all_levels[11]	auto[0]	166	1			T1	2		T17	1		T129	2
all_levels[11]	auto[1]	13	1			T205	2		T206	2		T207	1
all_levels[12]	auto[0]	145	1			T4	1		T127	1		T130	1
all_levels[12]	auto[1]	7	1			T208	1		T209	1		T210	1
all_levels[13]	auto[0]	132	1			T1	2		T127	1		T47	1
all_levels[13]	auto[1]	9	1			T147	1		T211	1		T160	2
all_levels[14]	auto[0]	115	1			T1	1		T4	1		T44	1
all_levels[14]	auto[1]	3	1			T4	1		T126	1		T212	1
all_levels[15]	auto[0]	111	1			T47	1		T103	1		T131	1
all_levels[15]	auto[1]	13	1			T103	1		T213	1		T214	1
all_levels[16]	auto[0]	92	1			T1	1		T127	1		T13	1
all_levels[16]	auto[1]	8	1			T215	1		T216	1		T217	1
all_levels[17]	auto[0]	92	1			T1	1		T12	1		T125	1
all_levels[17]	auto[1]	5	1			T177	3		T218	1		T219	1
all_levels[18]	auto[0]	75	1			T1	1		T14	1		T113	1
all_levels[18]	auto[1]	6	1			T220	1		T221	1		T222	2
all_levels[19]	auto[0]	86	1			T1	1		T4	1		T12	1
all_levels[19]	auto[1]	8	1			T4	1		T223	1		T159	1
all_levels[20]	auto[0]	70	1			T129	1		T113	1		T131	2
all_levels[20]	auto[1]	3	1			T224	2		T225	1		-	-
all_levels[21]	auto[0]	61	1			T129	1		T132	1		T113	1
all_levels[21]	auto[1]	6	1			T151	1		T226	2		T171	1
all_levels[22]	auto[0]	48	1			T14	1		T133	1		T134	1
all_levels[22]	auto[1]	3	1			T227	1		T228	2		-	-
all_levels[23]	auto[0]	52	1			T4	1		T135	2		T53	1
all_levels[23]	auto[1]	6	1			T229	1		T230	1		T231	1
all_levels[24]	auto[0]	49	1			T115	1		T14	2		T26	2
all_levels[24]	auto[1]	2	1			T232	1		T233	1		-	-
all_levels[25]	auto[0]	51	1			T5	1		T136	1		T115	1
all_levels[25]	auto[1]	6	1			T234	2		T235	1		T236	3
all_levels[26]	auto[0]	46	1			T12	1		T113	1		T137	1
all_levels[26]	auto[1]	8	1			T12	3		T203	2		T237	1
all_levels[27]	auto[0]	58	1			T125	1		T47	1		T129	1
all_levels[27]	auto[1]	4	1			T138	1		T238	1		T182	1
all_levels[28]	auto[0]	37	1			T44	1		T135	1		T138	1
all_levels[28]	auto[1]	3	1			T135	1		T223	1		T239	1
all_levels[29]	auto[0]	36	1			T1	1		T12	1		T129	1
all_levels[29]	auto[1]	9	1			T129	1		T77	2		T220	1
all_levels[30]	auto[0]	29	1			T125	1		T135	1		T26	1
all_levels[30]	auto[1]	2	1			T208	1		T240	1		-	-
all_levels[31]	auto[0]	39	1			T127	1		T139	1		T134	1
all_levels[32]	auto[0]	30	1			T1	1		T35	1		T54	1
all_levels[32]	auto[1]	4	1			T241	1		T242	1		T243	2
all_levels[33]	auto[0]	21	1			T129	1		T136	1		T140	1
all_levels[33]	auto[1]	2	1			T129	1		T244	1		-	-
all_levels[34]	auto[0]	24	1			T135	2		T54	2		T114	1
all_levels[34]	auto[1]	4	1			T177	2		T245	1		T210	1
all_levels[35]	auto[0]	30	1			T13	1		T139	1		T141	1
all_levels[35]	auto[1]	4	1			T13	2		T171	1		T246	1
all_levels[36]	auto[0]	31	1			T142	1		T143	1		T144	1
all_levels[36]	auto[1]	2	1			T247	1		T248	1		-	-
all_levels[37]	auto[0]	38	1			T145	2		T131	1		T139	1
all_levels[37]	auto[1]	9	1			T194	3		T249	4		T250	1
all_levels[38]	auto[0]	19	1			T145	1		T146	1		T147	1
all_levels[38]	auto[1]	2	1			T181	1		T251	1		-	-
all_levels[39]	auto[0]	17	1			T148	1		T149	2		T150	1
all_levels[39]	auto[1]	1	1			T252	1		-	-		-	-
all_levels[40]	auto[0]	26	1			T115	1		T28	1		T151	2
all_levels[40]	auto[1]	3	1			T141	3		-	-		-	-
all_levels[41]	auto[0]	13	1			T150	1		T152	1		T153	1
all_levels[41]	auto[1]	1	1			T253	1		-	-		-	-
all_levels[42]	auto[0]	16	1			T28	1		T140	1		T154	1
all_levels[42]	auto[1]	1	1			T154	1		-	-		-	-
all_levels[43]	auto[0]	15	1			T1	1		T155	1		T156	1
all_levels[43]	auto[1]	1	1			T254	1		-	-		-	-
all_levels[44]	auto[0]	18	1			T39	1		T157	1		T147	1
all_levels[44]	auto[1]	5	1			T255	2		T256	1		T257	2
all_levels[45]	auto[0]	10	1			T143	1		T158	1		T159	1
all_levels[45]	auto[1]	1	1			T258	1		-	-		-	-
all_levels[46]	auto[0]	9	1			T132	1		T160	1		T161	1
all_levels[46]	auto[1]	2	1			T132	1		T161	1		-	-
all_levels[47]	auto[0]	8	1			T150	1		T144	1		T162	1
all_levels[48]	auto[0]	16	1			T163	1		T164	1		T165	1
all_levels[49]	auto[0]	12	1			T111	1		T166	1		T167	1
all_levels[50]	auto[0]	18	1			T1	1		T156	1		T168	1
all_levels[50]	auto[1]	4	1			T259	3		T260	1		-	-
all_levels[51]	auto[0]	12	1			T124	1		T111	1		T169	1
all_levels[51]	auto[1]	2	1			T261	1		T262	1		-	-
all_levels[52]	auto[0]	7	1			T170	1		T171	1		T172	1
all_levels[53]	auto[0]	6	1			T140	1		T147	1		T173	1
all_levels[53]	auto[1]	4	1			T173	2		T60	2		-	-
all_levels[54]	auto[0]	9	1			T174	1		T175	1		T176	1
all_levels[55]	auto[0]	11	1			T146	1		T111	1		T177	1
all_levels[55]	auto[1]	1	1			T212	1		-	-		-	-
all_levels[56]	auto[0]	10	1			T151	1		T175	1		T143	1
all_levels[56]	auto[1]	1	1			T263	1		-	-		-	-
all_levels[57]	auto[0]	4	1			T178	1		T179	1		T180	1
all_levels[58]	auto[0]	5	1			T181	1		T182	1		T183	1
all_levels[58]	auto[1]	2	1			T181	1		T264	1		-	-
all_levels[59]	auto[0]	3	1			T175	1		T184	1		T185	1
all_levels[60]	auto[0]	7	1			T144	1		T186	1		T187	1
all_levels[60]	auto[1]	2	1			T265	2		-	-		-	-
all_levels[61]	auto[0]	11	1			T47	1		T188	1		T139	1
all_levels[61]	auto[1]	3	1			T47	1		T188	2		-	-
all_levels[62]	auto[0]	8	1			T189	1		T38	1		T190	1
all_levels[62]	auto[1]	3	1			T190	1		T266	2		-	-
all_levels[63]	auto[0]	9	1			T174	1		T111	1		T176	1
all_levels[63]	auto[1]	1	1			T221	1		-	-		-	-
all_levels[64]	auto[0]	101	1			T14	1		T48	1		T191	1
all_levels[64]	auto[1]	29	1			T48	1		T267	1		T168	4