Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	106980	1			T1	164		T2	2		T3	1
all_pins[1]	106980	1			T1	164		T2	2		T3	1
all_pins[2]	106980	1			T1	164		T2	2		T3	1
all_pins[3]	106980	1			T1	164		T2	2		T3	1
all_pins[4]	106980	1			T1	164		T2	2		T3	1
all_pins[5]	106980	1			T1	164		T2	2		T3	1
all_pins[6]	106980	1			T1	164		T2	2		T3	1
all_pins[7]	106980	1			T1	164		T2	2		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	828525	1			T1	1251		T2	16		T3	7
values[0x1]	27315	1			T1	61		T3	1		T4	21
transitions[0x0=>0x1]	26330	1			T1	54		T3	1		T4	21
transitions[0x1=>0x0]	25904	1			T1	53		T4	20		T5	43

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	85940	1			T1	135		T2	2		T4	16
all_pins[0]	values[0x1]	21040	1			T1	29		T3	1		T4	18
all_pins[0]	transitions[0x0=>0x1]	20581	1			T1	24		T3	1		T4	18
all_pins[0]	transitions[0x1=>0x0]	1196	1			T1	1		T12	20		T17	7
all_pins[1]	values[0x0]	105325	1			T1	158		T2	2		T3	1
all_pins[1]	values[0x1]	1655	1			T1	6		T5	2		T12	24
all_pins[1]	transitions[0x0=>0x1]	1551	1			T1	5		T5	2		T12	23
all_pins[1]	transitions[0x1=>0x0]	2348	1			T1	11		T4	2		T5	1
all_pins[2]	values[0x0]	104528	1			T1	152		T2	2		T3	1
all_pins[2]	values[0x1]	2452	1			T1	12		T4	2		T5	1
all_pins[2]	transitions[0x0=>0x1]	2398	1			T1	12		T4	2		T5	1
all_pins[2]	transitions[0x1=>0x0]	254	1			T14	1		T48	1		T27	2
all_pins[3]	values[0x0]	106672	1			T1	164		T2	2		T3	1
all_pins[3]	values[0x1]	308	1			T12	1		T14	1		T48	1
all_pins[3]	transitions[0x0=>0x1]	279	1			T12	1		T14	1		T48	1
all_pins[3]	transitions[0x1=>0x0]	461	1			T1	1		T15	1		T18	2
all_pins[4]	values[0x0]	106490	1			T1	163		T2	2		T3	1
all_pins[4]	values[0x1]	490	1			T1	1		T15	1		T18	2
all_pins[4]	transitions[0x0=>0x1]	428	1			T1	1		T15	1		T35	5
all_pins[4]	transitions[0x1=>0x0]	156	1			T15	1		T17	1		T27	3
all_pins[5]	values[0x0]	106762	1			T1	164		T2	2		T3	1
all_pins[5]	values[0x1]	218	1			T15	1		T17	1		T18	2
all_pins[5]	transitions[0x0=>0x1]	176	1			T15	1		T17	1		T18	2
all_pins[5]	transitions[0x1=>0x0]	727	1			T1	12		T4	1		T12	8
all_pins[6]	values[0x0]	106211	1			T1	152		T2	2		T3	1
all_pins[6]	values[0x1]	769	1			T1	12		T4	1		T12	8
all_pins[6]	transitions[0x0=>0x1]	705	1			T1	12		T4	1		T12	8
all_pins[6]	transitions[0x1=>0x0]	319	1			T1	1		T18	2		T27	2
all_pins[7]	values[0x0]	106597	1			T1	163		T2	2		T3	1
all_pins[7]	values[0x1]	383	1			T1	1		T18	2		T27	2
all_pins[7]	transitions[0x0=>0x1]	212	1			T18	1		T27	1		T35	2
all_pins[7]	transitions[0x1=>0x0]	20443	1			T1	27		T4	17		T5	42