Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7235145	1			T1	144		T3	1		T4	21
all_levels[1]	1664083	1			T1	149		T5	15		T6	20
all_levels[2]	578715	1			T1	15		T5	3		T6	3
all_levels[3]	510737	1			T5	6		T6	1		T8	19
all_levels[4]	225799	1			T1	7		T5	1		T8	21
all_levels[5]	202125	1			T1	4		T5	5		T6	1
all_levels[6]	195659	1			T1	5		T5	3		T6	2
all_levels[7]	359630	1			T1	4		T5	7		T6	4
all_levels[8]	213470	1			T1	3		T5	29		T6	1
all_levels[9]	438969	1			T1	6		T4	3		T5	13
all_levels[10]	254628	1			T1	5		T4	3		T6	35
all_levels[11]	280280	1			T5	3		T6	2		T8	27
all_levels[12]	213832	1			T1	7		T6	9		T8	25
all_levels[13]	174262	1			T1	11		T6	1		T8	17
all_levels[14]	182673	1			T6	25		T8	20		T11	122
all_levels[15]	171121	1			T1	4		T5	4		T8	24
all_levels[16]	309945	1			T1	15		T5	9		T6	1
all_levels[17]	274720	1			T1	1		T8	22		T11	140
all_levels[18]	169613	1			T1	2		T5	9		T8	27
all_levels[19]	274848	1			T6	1		T8	25		T11	132
all_levels[20]	274288	1			T8	25		T11	129		T125	1
all_levels[21]	179361	1			T5	11		T6	1		T8	28
all_levels[22]	184865	1			T1	9		T5	2		T6	1
all_levels[23]	242163	1			T1	6		T8	28		T11	128
all_levels[24]	469433	1			T8	20		T11	119		T44	2
all_levels[25]	167480	1			T6	1		T8	30		T11	143
all_levels[26]	245177	1			T8	22		T11	135		T44	1
all_levels[27]	406100	1			T8	25		T11	146		T44	1
all_levels[28]	180300	1			T4	3		T8	27		T11	126
all_levels[29]	403240	1			T5	15		T6	1		T8	21
all_levels[30]	251466	1			T1	5		T5	18		T6	1
all_levels[31]	633456	1			T1	2		T5	20		T6	711
all_levels[32]	14059938	1			T1	90		T4	25		T5	6

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31623316

1

T1

493

T4

45

T5

269

auto[1]

4205

1

T1

1

T3

1

T4

10

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7233007	1			T1	144		T4	18		T5	94
all_levels[0]	auto[1]	2138	1			T3	1		T4	3		T5	5
all_levels[1]	auto[0]	1663727	1			T1	149		T5	14		T6	20
all_levels[1]	auto[1]	356	1			T5	1		T197	1		T135	1
all_levels[2]	auto[0]	578680	1			T1	15		T5	3		T6	3
all_levels[2]	auto[1]	35	1			T132	1		T138	1		T290	1
all_levels[3]	auto[0]	510519	1			T5	6		T6	1		T8	19
all_levels[3]	auto[1]	218	1			T103	1		T51	6		T37	17
all_levels[4]	auto[0]	225771	1			T1	7		T5	1		T8	21
all_levels[4]	auto[1]	28	1			T17	2		T115	1		T28	3
all_levels[5]	auto[0]	202105	1			T1	4		T5	5		T6	1
all_levels[5]	auto[1]	20	1			T286	2		T270	2		T111	1
all_levels[6]	auto[0]	195639	1			T1	5		T5	3		T6	2
all_levels[6]	auto[1]	20	1			T126	1		T148	1		T216	1
all_levels[7]	auto[0]	359556	1			T1	4		T5	7		T6	4
all_levels[7]	auto[1]	74	1			T126	1		T103	1		T286	1
all_levels[8]	auto[0]	213431	1			T1	3		T5	29		T6	1
all_levels[8]	auto[1]	39	1			T12	2		T127	1		T132	1
all_levels[9]	auto[0]	438943	1			T1	6		T4	1		T5	12
all_levels[9]	auto[1]	26	1			T4	2		T5	1		T128	1
all_levels[10]	auto[0]	254602	1			T1	5		T4	1		T6	35
all_levels[10]	auto[1]	26	1			T4	2		T127	2		T198	1
all_levels[11]	auto[0]	280251	1			T5	3		T6	2		T8	27
all_levels[11]	auto[1]	29	1			T131	1		T135	2		T188	1
all_levels[12]	auto[0]	213808	1			T1	7		T6	9		T8	25
all_levels[12]	auto[1]	24	1			T114	1		T206	1		T342	1
all_levels[13]	auto[0]	174244	1			T1	11		T6	1		T8	17
all_levels[13]	auto[1]	18	1			T107	1		T54	1		T291	1
all_levels[14]	auto[0]	182637	1			T6	25		T8	20		T11	122
all_levels[14]	auto[1]	36	1			T43	1		T13	2		T132	1
all_levels[15]	auto[0]	170926	1			T1	4		T5	4		T8	24
all_levels[15]	auto[1]	195	1			T278	1		T21	4		T49	1
all_levels[16]	auto[0]	309922	1			T1	15		T5	9		T6	1
all_levels[16]	auto[1]	23	1			T201	1		T270	1		T263	3
all_levels[17]	auto[0]	274696	1			T1	1		T8	22		T11	140
all_levels[17]	auto[1]	24	1			T291	3		T199	1		T343	1
all_levels[18]	auto[0]	169571	1			T1	2		T5	9		T8	27
all_levels[18]	auto[1]	42	1			T279	1		T198	2		T284	1
all_levels[19]	auto[0]	274824	1			T6	1		T8	25		T11	132
all_levels[19]	auto[1]	24	1			T17	9		T56	4		T344	1
all_levels[20]	auto[0]	274263	1			T8	25		T11	129		T125	1
all_levels[20]	auto[1]	25	1			T47	1		T103	3		T345	1
all_levels[21]	auto[0]	179343	1			T5	10		T6	1		T8	28
all_levels[21]	auto[1]	18	1			T5	1		T105	1		T226	1
all_levels[22]	auto[0]	184846	1			T1	8		T5	2		T6	1
all_levels[22]	auto[1]	19	1			T1	1		T48	1		T205	1
all_levels[23]	auto[0]	242144	1			T1	6		T8	28		T11	128
all_levels[23]	auto[1]	19	1			T129	1		T313	2		T261	3
all_levels[24]	auto[0]	469400	1			T8	20		T11	119		T44	2
all_levels[24]	auto[1]	33	1			T55	2		T56	1		T168	1
all_levels[25]	auto[0]	167455	1			T6	1		T8	30		T11	143
all_levels[25]	auto[1]	25	1			T138	1		T346	2		T347	1
all_levels[26]	auto[0]	245157	1			T8	22		T11	135		T44	1
all_levels[26]	auto[1]	20	1			T151	2		T291	1		T263	1
all_levels[27]	auto[0]	406093	1			T8	25		T11	146		T44	1
all_levels[27]	auto[1]	7	1			T232	1		T216	1		T330	1
all_levels[28]	auto[0]	180288	1			T4	1		T8	27		T11	126
all_levels[28]	auto[1]	12	1			T4	2		T348	1		T161	1
all_levels[29]	auto[0]	403212	1			T5	15		T6	1		T8	21
all_levels[29]	auto[1]	28	1			T197	1		T198	1		T138	1
all_levels[30]	auto[0]	251446	1			T1	5		T5	18		T6	1
all_levels[30]	auto[1]	20	1			T126	1		T47	2		T54	1
all_levels[31]	auto[0]	633425	1			T1	2		T5	20		T6	711
all_levels[31]	auto[1]	31	1			T342	1		T203	1		T349	1
all_levels[32]	auto[0]	14059385	1			T1	90		T4	24		T5	5
all_levels[32]	auto[1]	553	1			T4	1		T5	1		T11	1