Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	745	1			T1	4		T15	4		T18	4
all_values[1]	745	1			T1	4		T15	4		T18	4
all_values[2]	745	1			T1	4		T15	4		T18	4
all_values[3]	745	1			T1	4		T15	4		T18	4
all_values[4]	745	1			T1	4		T15	4		T18	4
all_values[5]	745	1			T1	4		T15	4		T18	4
all_values[6]	745	1			T1	4		T15	4		T18	4
all_values[7]	745	1			T1	4		T15	4		T18	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3103

1

T1

18

T15

18

T18

12

auto[1]

2857

1

T1

14

T15

14

T18

20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2163

1

T1

11

T15

14

T18

14

auto[1]

3797

1

T1

21

T15

18

T18

18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3492

1

T1

20

T15

21

T18

21

auto[1]

2468

1

T1

12

T15

11

T18

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	210	1			T1	3		T15	1		T18	1
all_values[0]	auto[0]	auto[1]	auto[1]	205	1			T15	1		T18	1		T35	4
all_values[0]	auto[1]	auto[0]	auto[1]	192	1			T1	1		T18	1		T27	3
all_values[0]	auto[1]	auto[1]	auto[1]	138	1			T15	2		T18	1		T35	2
all_values[1]	auto[0]	auto[0]	auto[0]	246	1			T1	1		T15	1		T18	1
all_values[1]	auto[0]	auto[1]	auto[0]	191	1			T15	1		T18	2		T35	3
all_values[1]	auto[1]	auto[0]	auto[1]	162	1			T1	1		T15	2		T18	1
all_values[1]	auto[1]	auto[1]	auto[1]	146	1			T1	2		T35	2		T36	3
all_values[2]	auto[0]	auto[0]	auto[0]	167	1			T1	2		T15	1		T18	3
all_values[2]	auto[0]	auto[0]	auto[1]	61	1			T35	2		T36	2		T124	1
all_values[2]	auto[0]	auto[1]	auto[0]	145	1			T15	3		T18	1		T27	1
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T35	3		T124	1		T58	1
all_values[2]	auto[1]	auto[0]	auto[1]	155	1			T1	2		T35	1		T36	2
all_values[2]	auto[1]	auto[1]	auto[1]	143	1			T35	1		T36	2		T37	5
all_values[3]	auto[0]	auto[0]	auto[0]	155	1			T1	2		T15	1		T35	5
all_values[3]	auto[0]	auto[0]	auto[1]	86	1			T15	1		T27	1		T36	3
all_values[3]	auto[0]	auto[1]	auto[0]	137	1			T1	1		T18	3		T35	2
all_values[3]	auto[0]	auto[1]	auto[1]	66	1			T35	1		T36	1		T37	1
all_values[3]	auto[1]	auto[0]	auto[1]	160	1			T15	2		T27	2		T36	1
all_values[3]	auto[1]	auto[1]	auto[1]	141	1			T1	1		T18	1		T27	1
all_values[4]	auto[0]	auto[0]	auto[0]	139	1			T27	1		T36	4		T37	3
all_values[4]	auto[0]	auto[0]	auto[1]	86	1			T1	1		T35	2		T36	1
all_values[4]	auto[0]	auto[1]	auto[0]	119	1			T1	1		T15	2		T18	2
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T18	1		T35	5		T37	4
all_values[4]	auto[1]	auto[0]	auto[1]	173	1			T1	1		T27	1		T35	1
all_values[4]	auto[1]	auto[1]	auto[1]	150	1			T1	1		T15	2		T18	1
all_values[5]	auto[0]	auto[0]	auto[0]	154	1			T15	1		T27	1		T35	6
all_values[5]	auto[0]	auto[0]	auto[1]	62	1			T35	2		T36	1		T37	1
all_values[5]	auto[0]	auto[1]	auto[0]	153	1			T1	4		T36	5		T37	3
all_values[5]	auto[0]	auto[1]	auto[1]	83	1			T15	2		T18	1		T27	2
all_values[5]	auto[1]	auto[0]	auto[1]	153	1			T15	1		T18	1		T35	1
all_values[5]	auto[1]	auto[1]	auto[1]	140	1			T18	2		T27	1		T35	1
all_values[6]	auto[0]	auto[0]	auto[0]	134	1			T15	1		T18	1		T27	1
all_values[6]	auto[0]	auto[0]	auto[1]	91	1			T1	1		T15	2		T18	1
all_values[6]	auto[0]	auto[1]	auto[0]	131	1			T18	1		T27	2		T36	2
all_values[6]	auto[0]	auto[1]	auto[1]	78	1			T1	1		T35	1		T37	1
all_values[6]	auto[1]	auto[0]	auto[1]	181	1			T1	1		T15	1		T18	1
all_values[6]	auto[1]	auto[1]	auto[1]	130	1			T1	1		T35	1		T36	1
all_values[7]	auto[0]	auto[0]	auto[0]	134	1			T15	2		T27	1		T35	2
all_values[7]	auto[0]	auto[0]	auto[1]	62	1			T1	2		T18	1		T35	1
all_values[7]	auto[0]	auto[1]	auto[0]	158	1			T15	1		T35	1		T36	3
all_values[7]	auto[0]	auto[1]	auto[1]	87	1			T1	1		T18	1		T27	1
all_values[7]	auto[1]	auto[0]	auto[1]	140	1			T15	1		T36	1		T37	2
all_values[7]	auto[1]	auto[1]	auto[1]	164	1			T1	1		T18	2		T27	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal