Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.28 99.27 97.95 100.00 98.80 100.00 99.64


Total test records in report: 1319
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T1257 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1724458093 May 28 01:03:08 PM PDT 24 May 28 01:03:15 PM PDT 24 11146111 ps
T1258 /workspace/coverage/cover_reg_top/11.uart_csr_rw.3996357735 May 28 01:03:31 PM PDT 24 May 28 01:03:40 PM PDT 24 24272676 ps
T1259 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2830620698 May 28 01:03:24 PM PDT 24 May 28 01:03:35 PM PDT 24 212314578 ps
T1260 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.654432673 May 28 01:03:20 PM PDT 24 May 28 01:03:30 PM PDT 24 92158936 ps
T1261 /workspace/coverage/cover_reg_top/36.uart_intr_test.3296958163 May 28 01:03:22 PM PDT 24 May 28 01:03:33 PM PDT 24 153662951 ps
T1262 /workspace/coverage/cover_reg_top/15.uart_intr_test.2226883548 May 28 01:03:43 PM PDT 24 May 28 01:03:49 PM PDT 24 11377126 ps
T1263 /workspace/coverage/cover_reg_top/6.uart_intr_test.3691406110 May 28 01:03:16 PM PDT 24 May 28 01:03:26 PM PDT 24 13223813 ps
T95 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.4241740576 May 28 01:03:56 PM PDT 24 May 28 01:04:00 PM PDT 24 292537305 ps
T1264 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4033432670 May 28 01:03:20 PM PDT 24 May 28 01:03:32 PM PDT 24 123885844 ps
T1265 /workspace/coverage/cover_reg_top/30.uart_intr_test.3336420747 May 28 01:03:37 PM PDT 24 May 28 01:03:45 PM PDT 24 25708411 ps
T1266 /workspace/coverage/cover_reg_top/12.uart_tl_errors.82822490 May 28 01:03:37 PM PDT 24 May 28 01:03:46 PM PDT 24 40970317 ps
T1267 /workspace/coverage/cover_reg_top/16.uart_intr_test.2924092247 May 28 01:03:26 PM PDT 24 May 28 01:03:36 PM PDT 24 13408409 ps
T1268 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3752333136 May 28 01:03:21 PM PDT 24 May 28 01:03:32 PM PDT 24 32043464 ps
T1269 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.550305673 May 28 01:03:31 PM PDT 24 May 28 01:03:40 PM PDT 24 51355067 ps
T1270 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2879254657 May 28 01:03:30 PM PDT 24 May 28 01:03:39 PM PDT 24 22804023 ps
T1271 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2270719278 May 28 01:03:22 PM PDT 24 May 28 01:03:32 PM PDT 24 63261978 ps
T1272 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.565012894 May 28 01:03:30 PM PDT 24 May 28 01:03:40 PM PDT 24 722164471 ps
T121 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.912183646 May 28 01:03:30 PM PDT 24 May 28 01:03:39 PM PDT 24 184704580 ps
T1273 /workspace/coverage/cover_reg_top/9.uart_tl_errors.2238443664 May 28 01:03:28 PM PDT 24 May 28 01:03:38 PM PDT 24 50022930 ps
T1274 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3720544635 May 28 01:03:20 PM PDT 24 May 28 01:03:31 PM PDT 24 242162930 ps
T1275 /workspace/coverage/cover_reg_top/29.uart_intr_test.1178983422 May 28 01:03:23 PM PDT 24 May 28 01:03:34 PM PDT 24 48769086 ps
T1276 /workspace/coverage/cover_reg_top/25.uart_intr_test.1987796543 May 28 01:03:37 PM PDT 24 May 28 01:03:44 PM PDT 24 40083281 ps
T1277 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2535063456 May 28 01:03:31 PM PDT 24 May 28 01:03:41 PM PDT 24 24743359 ps
T1278 /workspace/coverage/cover_reg_top/13.uart_csr_rw.721093268 May 28 01:03:20 PM PDT 24 May 28 01:03:31 PM PDT 24 38201472 ps
T1279 /workspace/coverage/cover_reg_top/27.uart_intr_test.2778329804 May 28 01:03:24 PM PDT 24 May 28 01:03:35 PM PDT 24 43306167 ps
T69 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2571185286 May 28 01:03:21 PM PDT 24 May 28 01:03:32 PM PDT 24 24009505 ps
T1280 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3269475657 May 28 01:03:27 PM PDT 24 May 28 01:03:37 PM PDT 24 69056108 ps
T1281 /workspace/coverage/cover_reg_top/28.uart_intr_test.816919274 May 28 01:03:32 PM PDT 24 May 28 01:03:40 PM PDT 24 14459116 ps
T1282 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1277570080 May 28 01:03:04 PM PDT 24 May 28 01:03:09 PM PDT 24 19522652 ps
T1283 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.184386282 May 28 01:03:36 PM PDT 24 May 28 01:03:44 PM PDT 24 34983681 ps
T96 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3942397281 May 28 01:03:29 PM PDT 24 May 28 01:03:39 PM PDT 24 51012400 ps
T1284 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3067309006 May 28 01:03:30 PM PDT 24 May 28 01:03:39 PM PDT 24 20821324 ps
T70 /workspace/coverage/cover_reg_top/19.uart_csr_rw.3408179092 May 28 01:03:37 PM PDT 24 May 28 01:03:45 PM PDT 24 23297507 ps
T1285 /workspace/coverage/cover_reg_top/7.uart_intr_test.948646752 May 28 01:03:11 PM PDT 24 May 28 01:03:19 PM PDT 24 17202579 ps
T1286 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2359404189 May 28 01:03:29 PM PDT 24 May 28 01:03:38 PM PDT 24 17788620 ps
T1287 /workspace/coverage/cover_reg_top/24.uart_intr_test.1932305561 May 28 01:03:40 PM PDT 24 May 28 01:03:52 PM PDT 24 16629390 ps
T1288 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2690042818 May 28 01:03:28 PM PDT 24 May 28 01:03:38 PM PDT 24 60417007 ps
T1289 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1049764043 May 28 01:03:24 PM PDT 24 May 28 01:03:36 PM PDT 24 102566600 ps
T1290 /workspace/coverage/cover_reg_top/41.uart_intr_test.3916724332 May 28 01:03:24 PM PDT 24 May 28 01:03:34 PM PDT 24 23637170 ps
T1291 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1120179585 May 28 01:03:43 PM PDT 24 May 28 01:03:49 PM PDT 24 65241748 ps
T1292 /workspace/coverage/cover_reg_top/5.uart_tl_errors.247184129 May 28 01:03:24 PM PDT 24 May 28 01:03:35 PM PDT 24 63018960 ps
T1293 /workspace/coverage/cover_reg_top/5.uart_intr_test.3168785455 May 28 01:03:28 PM PDT 24 May 28 01:03:38 PM PDT 24 12175795 ps
T1294 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2836306213 May 28 01:03:20 PM PDT 24 May 28 01:03:32 PM PDT 24 93833649 ps
T1295 /workspace/coverage/cover_reg_top/14.uart_tl_errors.185821754 May 28 01:03:29 PM PDT 24 May 28 01:03:40 PM PDT 24 517983750 ps
T1296 /workspace/coverage/cover_reg_top/12.uart_csr_rw.3472011805 May 28 01:03:32 PM PDT 24 May 28 01:03:41 PM PDT 24 64904604 ps
T1297 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2847990659 May 28 01:03:49 PM PDT 24 May 28 01:03:55 PM PDT 24 79970406 ps
T1298 /workspace/coverage/cover_reg_top/26.uart_intr_test.1650059173 May 28 01:03:28 PM PDT 24 May 28 01:03:37 PM PDT 24 16711436 ps
T1299 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.604737196 May 28 01:03:15 PM PDT 24 May 28 01:03:25 PM PDT 24 25626865 ps
T1300 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2549444129 May 28 01:03:19 PM PDT 24 May 28 01:03:31 PM PDT 24 455001079 ps
T122 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.264369189 May 28 01:03:31 PM PDT 24 May 28 01:03:41 PM PDT 24 547645418 ps
T1301 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2480116008 May 28 01:03:31 PM PDT 24 May 28 01:03:42 PM PDT 24 1452063571 ps
T1302 /workspace/coverage/cover_reg_top/6.uart_tl_errors.294304449 May 28 01:03:23 PM PDT 24 May 28 01:03:34 PM PDT 24 197646677 ps
T1303 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3673549201 May 28 01:03:24 PM PDT 24 May 28 01:03:34 PM PDT 24 70357333 ps
T1304 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2510138174 May 28 01:03:28 PM PDT 24 May 28 01:03:38 PM PDT 24 43451037 ps
T1305 /workspace/coverage/cover_reg_top/42.uart_intr_test.2758352731 May 28 01:03:44 PM PDT 24 May 28 01:03:50 PM PDT 24 21647944 ps
T1306 /workspace/coverage/cover_reg_top/9.uart_intr_test.2769807398 May 28 01:03:23 PM PDT 24 May 28 01:03:34 PM PDT 24 15305544 ps
T1307 /workspace/coverage/cover_reg_top/44.uart_intr_test.3846595578 May 28 01:03:36 PM PDT 24 May 28 01:03:44 PM PDT 24 20806931 ps
T1308 /workspace/coverage/cover_reg_top/38.uart_intr_test.2917513350 May 28 01:03:41 PM PDT 24 May 28 01:03:47 PM PDT 24 14530822 ps
T1309 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1687858556 May 28 01:03:34 PM PDT 24 May 28 01:03:43 PM PDT 24 165904594 ps
T1310 /workspace/coverage/cover_reg_top/1.uart_intr_test.4161477872 May 28 01:03:07 PM PDT 24 May 28 01:03:12 PM PDT 24 36558392 ps
T1311 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3332768331 May 28 01:03:28 PM PDT 24 May 28 01:03:38 PM PDT 24 23540186 ps
T1312 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.603309328 May 28 01:03:29 PM PDT 24 May 28 01:03:39 PM PDT 24 61061338 ps
T1313 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2422261595 May 28 01:03:20 PM PDT 24 May 28 01:03:32 PM PDT 24 23584919 ps
T1314 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.719607470 May 28 01:03:15 PM PDT 24 May 28 01:03:25 PM PDT 24 90370049 ps
T1315 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2746698218 May 28 01:03:27 PM PDT 24 May 28 01:03:37 PM PDT 24 50743066 ps
T1316 /workspace/coverage/cover_reg_top/14.uart_intr_test.567573588 May 28 01:03:23 PM PDT 24 May 28 01:03:34 PM PDT 24 42508003 ps
T1317 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1770319952 May 28 01:03:20 PM PDT 24 May 28 01:03:31 PM PDT 24 27998932 ps
T1318 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1965988751 May 28 01:03:32 PM PDT 24 May 28 01:03:45 PM PDT 24 32583152 ps
T1319 /workspace/coverage/cover_reg_top/0.uart_csr_rw.3366779814 May 28 01:03:21 PM PDT 24 May 28 01:03:32 PM PDT 24 16048828 ps

Test location /workspace/coverage/default/3.uart_stress_all.512295653
Short name T1
Test name
Test status
Simulation time 259611570947 ps
CPU time 428.82 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:56:18 PM PDT 24
Peak memory 200544 kb
Host smart-d050ef3f-f7ef-4d05-be9a-69105d33f3d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512295653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.512295653
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3348855682
Short name T36
Test name
Test status
Simulation time 345189714658 ps
CPU time 1110.93 seconds
Started May 28 01:52:12 PM PDT 24
Finished May 28 02:10:44 PM PDT 24
Peak memory 225432 kb
Host smart-b40140bd-512c-46a5-aabb-fb3fc115d399
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348855682 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3348855682
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2377896251
Short name T37
Test name
Test status
Simulation time 192095832854 ps
CPU time 1049.28 seconds
Started May 28 01:49:24 PM PDT 24
Finished May 28 02:06:56 PM PDT 24
Peak memory 225456 kb
Host smart-937f2293-92ca-4832-be15-d6753c052b3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377896251 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2377896251
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3766188505
Short name T38
Test name
Test status
Simulation time 142787664590 ps
CPU time 1299.73 seconds
Started May 28 01:48:55 PM PDT 24
Finished May 28 02:10:36 PM PDT 24
Peak memory 227244 kb
Host smart-e3367c1f-dc97-42a1-bb33-754feb348ead
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766188505 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3766188505
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all.1984307753
Short name T17
Test name
Test status
Simulation time 649648306414 ps
CPU time 514.35 seconds
Started May 28 01:50:39 PM PDT 24
Finished May 28 01:59:15 PM PDT 24
Peak memory 209040 kb
Host smart-fd2b4056-b32d-40d5-8daa-a9db15ddb0f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984307753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1984307753
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.92627560
Short name T175
Test name
Test status
Simulation time 324817073784 ps
CPU time 1233.76 seconds
Started May 28 01:52:16 PM PDT 24
Finished May 28 02:12:52 PM PDT 24
Peak memory 230008 kb
Host smart-81bbe12f-d551-499e-999e-87376872227f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92627560 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.92627560
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.1100218797
Short name T114
Test name
Test status
Simulation time 149202819576 ps
CPU time 368.73 seconds
Started May 28 01:49:39 PM PDT 24
Finished May 28 01:55:50 PM PDT 24
Peak memory 200188 kb
Host smart-f955c553-471c-480d-bdd6-32dbb5acebca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100218797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1100218797
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1764311079
Short name T32
Test name
Test status
Simulation time 69177631 ps
CPU time 0.89 seconds
Started May 28 01:48:55 PM PDT 24
Finished May 28 01:48:57 PM PDT 24
Peak memory 219116 kb
Host smart-663a1870-3ab0-4270-b30a-63bcfc3df296
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764311079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1764311079
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3225336008
Short name T58
Test name
Test status
Simulation time 189136190048 ps
CPU time 785.58 seconds
Started May 28 01:51:57 PM PDT 24
Finished May 28 02:05:06 PM PDT 24
Peak memory 217236 kb
Host smart-418548c0-837f-466f-9ba5-6c2fd102ffbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225336008 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3225336008
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.337101911
Short name T4
Test name
Test status
Simulation time 108841633259 ps
CPU time 31.43 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:49 PM PDT 24
Peak memory 200528 kb
Host smart-eb3f89e3-7849-4611-8315-4e55129c2ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337101911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.337101911
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all.3531037589
Short name T308
Test name
Test status
Simulation time 163985006099 ps
CPU time 938.15 seconds
Started May 28 01:50:24 PM PDT 24
Finished May 28 02:06:07 PM PDT 24
Peak memory 200480 kb
Host smart-7996c86d-1af9-4039-9f1f-d54f98724b25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531037589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3531037589
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2081212205
Short name T188
Test name
Test status
Simulation time 222871899099 ps
CPU time 193.32 seconds
Started May 28 01:52:54 PM PDT 24
Finished May 28 01:56:09 PM PDT 24
Peak memory 200352 kb
Host smart-5c4479ca-9a04-4cfd-954c-3d656b752173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081212205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2081212205
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_perf.1654315338
Short name T274
Test name
Test status
Simulation time 33067323118 ps
CPU time 411.62 seconds
Started May 28 01:49:21 PM PDT 24
Finished May 28 01:56:15 PM PDT 24
Peak memory 200508 kb
Host smart-61e5a21a-e12d-49f5-a54c-f70253a6182e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1654315338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1654315338
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.329174623
Short name T12
Test name
Test status
Simulation time 87687351659 ps
CPU time 220.09 seconds
Started May 28 01:53:19 PM PDT 24
Finished May 28 01:57:01 PM PDT 24
Peak memory 200540 kb
Host smart-c7ebb07c-71b5-4cc6-afbe-10cb4ab7f3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329174623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.329174623
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1693335138
Short name T215
Test name
Test status
Simulation time 76409724989 ps
CPU time 19.54 seconds
Started May 28 01:50:39 PM PDT 24
Finished May 28 01:51:00 PM PDT 24
Peak memory 200428 kb
Host smart-0b03d945-d41d-4efa-8260-7c35520e1090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693335138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1693335138
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2211700692
Short name T49
Test name
Test status
Simulation time 42539876867 ps
CPU time 71.73 seconds
Started May 28 01:49:43 PM PDT 24
Finished May 28 01:50:56 PM PDT 24
Peak memory 200464 kb
Host smart-deb014c4-1570-4e4e-a437-4e5519c92495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211700692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2211700692
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3141346356
Short name T100
Test name
Test status
Simulation time 82834916 ps
CPU time 1.21 seconds
Started May 28 01:03:32 PM PDT 24
Finished May 28 01:03:41 PM PDT 24
Peak memory 199164 kb
Host smart-899803ad-5b32-4bf3-97d2-fa1479403312
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141346356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3141346356
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.426411829
Short name T150
Test name
Test status
Simulation time 161897324048 ps
CPU time 122.84 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 01:53:22 PM PDT 24
Peak memory 200340 kb
Host smart-3ac4b598-93f6-4bfe-88e7-1d8bd46eae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426411829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.426411829
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_alert_test.3975661663
Short name T374
Test name
Test status
Simulation time 38315860 ps
CPU time 0.55 seconds
Started May 28 01:49:31 PM PDT 24
Finished May 28 01:49:34 PM PDT 24
Peak memory 195684 kb
Host smart-d631a0a6-d863-476d-8400-bc4056d2cb6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975661663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3975661663
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3601629986
Short name T111
Test name
Test status
Simulation time 355145862576 ps
CPU time 755.03 seconds
Started May 28 01:50:49 PM PDT 24
Finished May 28 02:03:25 PM PDT 24
Peak memory 225336 kb
Host smart-b5280f5c-4d4e-4246-993f-a0f765355d1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601629986 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3601629986
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all.4069935163
Short name T13
Test name
Test status
Simulation time 193112321854 ps
CPU time 511.08 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:57:47 PM PDT 24
Peak memory 200468 kb
Host smart-1aa37168-4462-4e1c-bcdb-fb76b7ecee5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069935163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.4069935163
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2866692549
Short name T44
Test name
Test status
Simulation time 103153753126 ps
CPU time 54.46 seconds
Started May 28 01:53:16 PM PDT 24
Finished May 28 01:54:13 PM PDT 24
Peak memory 200636 kb
Host smart-ed9e4bfe-7ad8-4dde-8efa-e71a30dfad03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866692549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2866692549
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3358323037
Short name T155
Test name
Test status
Simulation time 218647814799 ps
CPU time 445.03 seconds
Started May 28 01:49:14 PM PDT 24
Finished May 28 01:56:44 PM PDT 24
Peak memory 200476 kb
Host smart-0d7d189f-3f49-4927-a689-6113299e01ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358323037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3358323037
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3019474655
Short name T146
Test name
Test status
Simulation time 26532114551 ps
CPU time 11.74 seconds
Started May 28 01:50:13 PM PDT 24
Finished May 28 01:50:30 PM PDT 24
Peak memory 200556 kb
Host smart-f799dbac-26f7-4e69-8c6d-64f85d021fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019474655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3019474655
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_stress_all.898675696
Short name T134
Test name
Test status
Simulation time 60506513296 ps
CPU time 66.95 seconds
Started May 28 01:50:51 PM PDT 24
Finished May 28 01:52:00 PM PDT 24
Peak memory 200444 kb
Host smart-20a58a09-23e1-4619-b4f0-95302a122556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898675696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.898675696
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_perf.3736376340
Short name T311
Test name
Test status
Simulation time 19259586169 ps
CPU time 194.25 seconds
Started May 28 01:48:49 PM PDT 24
Finished May 28 01:52:07 PM PDT 24
Peak memory 200480 kb
Host smart-8d40b48a-1a4b-4239-8fb4-67ba0cb3dd6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3736376340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3736376340
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1309100445
Short name T208
Test name
Test status
Simulation time 79991948301 ps
CPU time 166.43 seconds
Started May 28 01:53:20 PM PDT 24
Finished May 28 01:56:10 PM PDT 24
Peak memory 200556 kb
Host smart-f880961e-9618-4330-a96c-5767174a0cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309100445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1309100445
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1044344400
Short name T129
Test name
Test status
Simulation time 127176102607 ps
CPU time 205.25 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:52:33 PM PDT 24
Peak memory 200548 kb
Host smart-e01df213-51a0-40db-af38-b0b41a8b7b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044344400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1044344400
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3934948357
Short name T68
Test name
Test status
Simulation time 18836170 ps
CPU time 0.62 seconds
Started May 28 01:03:07 PM PDT 24
Finished May 28 01:03:13 PM PDT 24
Peak memory 195172 kb
Host smart-e6d0a4b3-37fe-4b88-a949-77d62c0e0d89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934948357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3934948357
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3808572145
Short name T85
Test name
Test status
Simulation time 63491889 ps
CPU time 0.73 seconds
Started May 28 01:03:27 PM PDT 24
Finished May 28 01:03:37 PM PDT 24
Peak memory 195944 kb
Host smart-021237a1-16db-4801-a03e-7e663cde3d72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808572145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3808572145
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.906547504
Short name T200
Test name
Test status
Simulation time 23372085522 ps
CPU time 44.83 seconds
Started May 28 01:49:09 PM PDT 24
Finished May 28 01:49:57 PM PDT 24
Peak memory 200564 kb
Host smart-a9bd8cbf-9ceb-4bde-9f88-fa76d1aa27ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906547504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.906547504
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.4241740576
Short name T95
Test name
Test status
Simulation time 292537305 ps
CPU time 0.93 seconds
Started May 28 01:03:56 PM PDT 24
Finished May 28 01:04:00 PM PDT 24
Peak memory 198708 kb
Host smart-e2a39df1-fef3-413b-b855-eed4d1e95928
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241740576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.4241740576
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1705848000
Short name T349
Test name
Test status
Simulation time 264398624415 ps
CPU time 104.3 seconds
Started May 28 01:52:34 PM PDT 24
Finished May 28 01:54:22 PM PDT 24
Peak memory 200464 kb
Host smart-c03bfbb4-2ef4-484b-9083-405ee6bcfb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705848000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1705848000
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3531612624
Short name T138
Test name
Test status
Simulation time 122435016388 ps
CPU time 346.66 seconds
Started May 28 01:50:22 PM PDT 24
Finished May 28 01:56:09 PM PDT 24
Peak memory 200536 kb
Host smart-84c94ac5-f084-4a6e-8176-5403ebd49a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531612624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3531612624
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3166095272
Short name T171
Test name
Test status
Simulation time 36053349768 ps
CPU time 33.43 seconds
Started May 28 01:52:35 PM PDT 24
Finished May 28 01:53:13 PM PDT 24
Peak memory 200488 kb
Host smart-f5df12f1-50f6-4b5f-8fc0-8d95976d8944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166095272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3166095272
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1120793321
Short name T321
Test name
Test status
Simulation time 50489890227 ps
CPU time 892.02 seconds
Started May 28 01:49:37 PM PDT 24
Finished May 28 02:04:30 PM PDT 24
Peak memory 217016 kb
Host smart-ee27e6e0-fad3-4adf-bab4-20349c5f75c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120793321 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1120793321
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.665585931
Short name T211
Test name
Test status
Simulation time 43029830935 ps
CPU time 38.74 seconds
Started May 28 01:53:33 PM PDT 24
Finished May 28 01:54:17 PM PDT 24
Peak memory 200488 kb
Host smart-0f63a847-438d-4137-a911-a97e48616840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665585931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.665585931
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2368190261
Short name T183
Test name
Test status
Simulation time 16196749613 ps
CPU time 37.64 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 01:51:46 PM PDT 24
Peak memory 200408 kb
Host smart-044b5f00-2ed0-4023-a855-ee6e95b099be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368190261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2368190261
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.432821431
Short name T335
Test name
Test status
Simulation time 236295509385 ps
CPU time 1245.43 seconds
Started May 28 01:51:55 PM PDT 24
Finished May 28 02:12:45 PM PDT 24
Peak memory 216976 kb
Host smart-9654ab86-b47b-454f-aad1-f1e870a23c15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432821431 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.432821431
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3615777628
Short name T194
Test name
Test status
Simulation time 151932154287 ps
CPU time 101.58 seconds
Started May 28 01:52:33 PM PDT 24
Finished May 28 01:54:17 PM PDT 24
Peak memory 200492 kb
Host smart-263a5a01-5217-477c-b9ec-ec2fad3eeb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615777628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3615777628
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3702016937
Short name T108
Test name
Test status
Simulation time 178629363990 ps
CPU time 106.69 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:51:04 PM PDT 24
Peak memory 199892 kb
Host smart-e2d6c830-5ddf-48a6-a29f-47acd23d51ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702016937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3702016937
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1957696770
Short name T192
Test name
Test status
Simulation time 280705093286 ps
CPU time 141.68 seconds
Started May 28 01:52:50 PM PDT 24
Finished May 28 01:55:15 PM PDT 24
Peak memory 200508 kb
Host smart-2a99bf4d-9dc2-4df1-a286-ef7801e1e0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957696770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1957696770
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_noise_filter.932691728
Short name T283
Test name
Test status
Simulation time 125691442789 ps
CPU time 119.95 seconds
Started May 28 01:51:06 PM PDT 24
Finished May 28 01:53:09 PM PDT 24
Peak memory 208824 kb
Host smart-48b93cad-abb4-4271-8f02-e6ec47a28eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932691728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.932691728
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.431636748
Short name T5
Test name
Test status
Simulation time 104456590045 ps
CPU time 128.52 seconds
Started May 28 01:51:54 PM PDT 24
Finished May 28 01:54:06 PM PDT 24
Peak memory 200560 kb
Host smart-3771b50c-7cc2-4038-9fd0-4e5a4d00bacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431636748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.431636748
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.419755037
Short name T179
Test name
Test status
Simulation time 106028458863 ps
CPU time 605.25 seconds
Started May 28 01:48:49 PM PDT 24
Finished May 28 01:58:58 PM PDT 24
Peak memory 225420 kb
Host smart-009cd074-68d7-444c-8413-951692e2d180
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419755037 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.419755037
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1304699679
Short name T206
Test name
Test status
Simulation time 193986493670 ps
CPU time 38.98 seconds
Started May 28 01:52:58 PM PDT 24
Finished May 28 01:53:39 PM PDT 24
Peak memory 200520 kb
Host smart-1c64cba9-c05e-4010-a225-f3575209aa65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304699679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1304699679
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3119162911
Short name T161
Test name
Test status
Simulation time 141477884272 ps
CPU time 291.09 seconds
Started May 28 01:53:05 PM PDT 24
Finished May 28 01:57:58 PM PDT 24
Peak memory 200544 kb
Host smart-017e64db-3270-442d-b488-5a8f1dcd9cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119162911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3119162911
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.439775405
Short name T214
Test name
Test status
Simulation time 83828567718 ps
CPU time 59.29 seconds
Started May 28 01:53:15 PM PDT 24
Finished May 28 01:54:16 PM PDT 24
Peak memory 200516 kb
Host smart-0a4e0773-1b2c-475e-9632-85c1aeaab330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439775405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.439775405
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all.2915622920
Short name T251
Test name
Test status
Simulation time 431518392897 ps
CPU time 1556.19 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 02:17:15 PM PDT 24
Peak memory 200456 kb
Host smart-3205a734-5c89-46da-9b74-8e0d33a2c9b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915622920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2915622920
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.58252194
Short name T154
Test name
Test status
Simulation time 19892390451 ps
CPU time 34.79 seconds
Started May 28 01:52:12 PM PDT 24
Finished May 28 01:52:48 PM PDT 24
Peak memory 200376 kb
Host smart-83013eb2-15e3-4227-b585-2a21ccba027f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58252194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.58252194
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.912183646
Short name T121
Test name
Test status
Simulation time 184704580 ps
CPU time 0.9 seconds
Started May 28 01:03:30 PM PDT 24
Finished May 28 01:03:39 PM PDT 24
Peak memory 198492 kb
Host smart-b77a463a-19a5-4269-a33a-508e72c6402b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912183646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.912183646
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3516107949
Short name T221
Test name
Test status
Simulation time 24933807523 ps
CPU time 25.03 seconds
Started May 28 01:52:33 PM PDT 24
Finished May 28 01:53:02 PM PDT 24
Peak memory 200488 kb
Host smart-a9472a79-197d-4f01-b6a8-c17067e0c7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516107949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3516107949
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3643224348
Short name T60
Test name
Test status
Simulation time 127784607334 ps
CPU time 1031.29 seconds
Started May 28 01:49:17 PM PDT 24
Finished May 28 02:06:32 PM PDT 24
Peak memory 225172 kb
Host smart-5e3e6be5-5805-4a87-9eb0-5f82c74b918b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643224348 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3643224348
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.819873147
Short name T526
Test name
Test status
Simulation time 134610429622 ps
CPU time 158.69 seconds
Started May 28 01:53:14 PM PDT 24
Finished May 28 01:55:54 PM PDT 24
Peak memory 200508 kb
Host smart-5979300f-c454-4c01-8bd7-79f50d82f605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819873147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.819873147
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3365954745
Short name T177
Test name
Test status
Simulation time 129394181664 ps
CPU time 48.04 seconds
Started May 28 01:53:33 PM PDT 24
Finished May 28 01:54:26 PM PDT 24
Peak memory 200528 kb
Host smart-090c9f74-4d96-47e8-8925-5d705c73b357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365954745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3365954745
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2666443729
Short name T866
Test name
Test status
Simulation time 49028522652 ps
CPU time 73.93 seconds
Started May 28 01:52:32 PM PDT 24
Finished May 28 01:53:47 PM PDT 24
Peak memory 200492 kb
Host smart-3c28411f-6380-405e-8766-7d6885d34391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666443729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2666443729
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3585788750
Short name T225
Test name
Test status
Simulation time 122177174731 ps
CPU time 42.39 seconds
Started May 28 01:52:31 PM PDT 24
Finished May 28 01:53:15 PM PDT 24
Peak memory 200452 kb
Host smart-77557d2a-ac79-43fa-aaa4-8522a5fd3ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585788750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3585788750
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_loopback.3564739250
Short name T507
Test name
Test status
Simulation time 3067386638 ps
CPU time 6.69 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:49:23 PM PDT 24
Peak memory 199456 kb
Host smart-d2c8ba13-c5ee-49b7-92cf-aa1fb0b93706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564739250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3564739250
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3322946054
Short name T236
Test name
Test status
Simulation time 10967415489 ps
CPU time 16.65 seconds
Started May 28 01:52:36 PM PDT 24
Finished May 28 01:52:57 PM PDT 24
Peak memory 200264 kb
Host smart-768e1272-df80-4dba-9741-634f55c7960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322946054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3322946054
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3003443686
Short name T976
Test name
Test status
Simulation time 19152964440 ps
CPU time 31.2 seconds
Started May 28 01:52:32 PM PDT 24
Finished May 28 01:53:06 PM PDT 24
Peak memory 200528 kb
Host smart-e4c8456c-84bf-4337-b2fe-912f2ffbaa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003443686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3003443686
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1744273420
Short name T260
Test name
Test status
Simulation time 34157707364 ps
CPU time 28.96 seconds
Started May 28 01:49:19 PM PDT 24
Finished May 28 01:49:51 PM PDT 24
Peak memory 200356 kb
Host smart-dc04e4b3-d789-4432-8917-b6fbdcaa1d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744273420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1744273420
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2612539969
Short name T190
Test name
Test status
Simulation time 41161531909 ps
CPU time 18.92 seconds
Started May 28 01:52:37 PM PDT 24
Finished May 28 01:53:00 PM PDT 24
Peak memory 200484 kb
Host smart-6df0f68f-969d-4204-a501-fa9c39a44b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612539969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2612539969
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2003360685
Short name T241
Test name
Test status
Simulation time 14655804877 ps
CPU time 28.13 seconds
Started May 28 01:52:38 PM PDT 24
Finished May 28 01:53:10 PM PDT 24
Peak memory 200532 kb
Host smart-97567d71-9b9e-4ed0-ac3b-d6dd36b492d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003360685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2003360685
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3118399583
Short name T264
Test name
Test status
Simulation time 28301237275 ps
CPU time 28.52 seconds
Started May 28 01:52:37 PM PDT 24
Finished May 28 01:53:10 PM PDT 24
Peak memory 200348 kb
Host smart-d73c6cd2-2106-471d-8923-eaf8f076e831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118399583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3118399583
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1729696242
Short name T223
Test name
Test status
Simulation time 100560669304 ps
CPU time 102.68 seconds
Started May 28 01:52:48 PM PDT 24
Finished May 28 01:54:32 PM PDT 24
Peak memory 200680 kb
Host smart-cc280bc3-d463-424f-910c-c56f8e4c813d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729696242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1729696242
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3257425733
Short name T212
Test name
Test status
Simulation time 17127064161 ps
CPU time 14.69 seconds
Started May 28 01:52:51 PM PDT 24
Finished May 28 01:53:08 PM PDT 24
Peak memory 200536 kb
Host smart-8be37b7b-5ff1-4164-9365-e4d77934c382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257425733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3257425733
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.4153800278
Short name T253
Test name
Test status
Simulation time 47686020142 ps
CPU time 34.46 seconds
Started May 28 01:52:59 PM PDT 24
Finished May 28 01:53:35 PM PDT 24
Peak memory 200552 kb
Host smart-2d35d288-7c58-42d1-9c93-12640e7889b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153800278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.4153800278
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1173297852
Short name T256
Test name
Test status
Simulation time 17437682906 ps
CPU time 23.19 seconds
Started May 28 01:52:52 PM PDT 24
Finished May 28 01:53:17 PM PDT 24
Peak memory 200488 kb
Host smart-c0dbac03-9d2f-4230-86d6-0a36c9a134e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173297852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1173297852
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.547060771
Short name T228
Test name
Test status
Simulation time 121780228826 ps
CPU time 17.42 seconds
Started May 28 01:52:48 PM PDT 24
Finished May 28 01:53:08 PM PDT 24
Peak memory 200528 kb
Host smart-7753f333-f120-4159-93e5-693c460f948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547060771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.547060771
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.241038023
Short name T248
Test name
Test status
Simulation time 25798798054 ps
CPU time 24.27 seconds
Started May 28 01:53:00 PM PDT 24
Finished May 28 01:53:27 PM PDT 24
Peak memory 200556 kb
Host smart-9682d694-4528-4c9b-b4a8-c9860d7842c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241038023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.241038023
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.290349584
Short name T232
Test name
Test status
Simulation time 185635324811 ps
CPU time 146.67 seconds
Started May 28 01:53:15 PM PDT 24
Finished May 28 01:55:43 PM PDT 24
Peak memory 200572 kb
Host smart-7ea6d811-6cfe-44b1-a195-6c8dd1e96991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290349584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.290349584
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.449931488
Short name T265
Test name
Test status
Simulation time 39296501608 ps
CPU time 18.11 seconds
Started May 28 01:50:50 PM PDT 24
Finished May 28 01:51:09 PM PDT 24
Peak memory 200424 kb
Host smart-8c539250-f702-4c43-bdb2-a6eac93fe085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449931488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.449931488
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1557218233
Short name T262
Test name
Test status
Simulation time 387209053392 ps
CPU time 90.98 seconds
Started May 28 01:50:43 PM PDT 24
Finished May 28 01:52:15 PM PDT 24
Peak memory 200524 kb
Host smart-6ee9acce-dc6e-400b-8df2-98c36ba4e180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557218233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1557218233
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.143373818
Short name T141
Test name
Test status
Simulation time 123728880104 ps
CPU time 209.45 seconds
Started May 28 01:50:56 PM PDT 24
Finished May 28 01:54:26 PM PDT 24
Peak memory 200504 kb
Host smart-3f139363-a488-4ae2-b12f-0adafb835f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143373818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.143373818
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2665560063
Short name T263
Test name
Test status
Simulation time 14710360539 ps
CPU time 26.36 seconds
Started May 28 01:48:59 PM PDT 24
Finished May 28 01:49:29 PM PDT 24
Peak memory 200532 kb
Host smart-791b68c5-771e-4223-b141-8340ab755a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665560063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2665560063
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3992286484
Short name T252
Test name
Test status
Simulation time 210143555372 ps
CPU time 804.37 seconds
Started May 28 01:51:44 PM PDT 24
Finished May 28 02:05:11 PM PDT 24
Peak memory 216616 kb
Host smart-f01c0c15-330e-4b3e-80d5-31e77f98a80a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992286484 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3992286484
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3361677345
Short name T258
Test name
Test status
Simulation time 18256844658 ps
CPU time 214.97 seconds
Started May 28 01:51:55 PM PDT 24
Finished May 28 01:55:34 PM PDT 24
Peak memory 208824 kb
Host smart-56ee456c-a64d-4b5b-8911-e74997817e01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361677345 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3361677345
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3585941806
Short name T254
Test name
Test status
Simulation time 439572744715 ps
CPU time 2223.19 seconds
Started May 28 01:51:56 PM PDT 24
Finished May 28 02:29:03 PM PDT 24
Peak memory 225168 kb
Host smart-131649f9-cdb1-4d7c-ba91-a34dce8eb2d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585941806 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3585941806
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2270719278
Short name T1271
Test name
Test status
Simulation time 63261978 ps
CPU time 0.65 seconds
Started May 28 01:03:22 PM PDT 24
Finished May 28 01:03:32 PM PDT 24
Peak memory 194836 kb
Host smart-474e65ea-f4f3-43d4-bcf7-a74ba55b86e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270719278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2270719278
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2417613129
Short name T1221
Test name
Test status
Simulation time 208652353 ps
CPU time 2.19 seconds
Started May 28 01:03:30 PM PDT 24
Finished May 28 01:03:40 PM PDT 24
Peak memory 197596 kb
Host smart-7a6500d0-45c8-424f-ba45-6bd0ebc25e49
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417613129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2417613129
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2510138174
Short name T1304
Test name
Test status
Simulation time 43451037 ps
CPU time 0.56 seconds
Started May 28 01:03:28 PM PDT 24
Finished May 28 01:03:38 PM PDT 24
Peak memory 195168 kb
Host smart-0498521b-edcd-4156-81e4-224282ab6570
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510138174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2510138174
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2473921871
Short name T1189
Test name
Test status
Simulation time 18470666 ps
CPU time 0.66 seconds
Started May 28 01:03:15 PM PDT 24
Finished May 28 01:03:24 PM PDT 24
Peak memory 197588 kb
Host smart-f61f6fc9-88ca-493a-9156-c1f65047813b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473921871 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2473921871
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3366779814
Short name T1319
Test name
Test status
Simulation time 16048828 ps
CPU time 0.59 seconds
Started May 28 01:03:21 PM PDT 24
Finished May 28 01:03:32 PM PDT 24
Peak memory 195164 kb
Host smart-15163133-74bb-43f8-ad71-6468bf04e07a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366779814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3366779814
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3915202024
Short name T1206
Test name
Test status
Simulation time 61660181 ps
CPU time 0.59 seconds
Started May 28 01:03:07 PM PDT 24
Finished May 28 01:03:12 PM PDT 24
Peak memory 194164 kb
Host smart-163b43c5-6675-4e9e-beed-c367f4834c14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915202024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3915202024
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2017879783
Short name T1255
Test name
Test status
Simulation time 27845819 ps
CPU time 0.79 seconds
Started May 28 01:03:24 PM PDT 24
Finished May 28 01:03:34 PM PDT 24
Peak memory 196308 kb
Host smart-188e47da-0179-4450-a0de-bb6949086e2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017879783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2017879783
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2836306213
Short name T1294
Test name
Test status
Simulation time 93833649 ps
CPU time 2.03 seconds
Started May 28 01:03:20 PM PDT 24
Finished May 28 01:03:32 PM PDT 24
Peak memory 199828 kb
Host smart-f11c3414-bab1-4832-abc5-156d87de9775
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836306213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2836306213
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.809435427
Short name T93
Test name
Test status
Simulation time 85514264 ps
CPU time 1.3 seconds
Started May 28 01:03:07 PM PDT 24
Finished May 28 01:03:13 PM PDT 24
Peak memory 199084 kb
Host smart-dc1f429c-5add-4656-9961-045d29648cd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809435427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.809435427
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1277570080
Short name T1282
Test name
Test status
Simulation time 19522652 ps
CPU time 0.67 seconds
Started May 28 01:03:04 PM PDT 24
Finished May 28 01:03:09 PM PDT 24
Peak memory 194824 kb
Host smart-e0e7541b-b6fd-4347-af7d-c1d75780e118
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277570080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1277570080
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.565012894
Short name T1272
Test name
Test status
Simulation time 722164471 ps
CPU time 1.54 seconds
Started May 28 01:03:30 PM PDT 24
Finished May 28 01:03:40 PM PDT 24
Peak memory 197364 kb
Host smart-53ff0aa2-bafe-4376-863c-4b3b985af64d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565012894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.565012894
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.4115564231
Short name T1234
Test name
Test status
Simulation time 15828172 ps
CPU time 0.6 seconds
Started May 28 01:03:23 PM PDT 24
Finished May 28 01:03:34 PM PDT 24
Peak memory 195168 kb
Host smart-2adafa49-c157-48a7-8e1b-f0057bbe1ad8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115564231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.4115564231
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3888684526
Short name T1252
Test name
Test status
Simulation time 17676131 ps
CPU time 0.7 seconds
Started May 28 01:03:20 PM PDT 24
Finished May 28 01:03:31 PM PDT 24
Peak memory 197984 kb
Host smart-2708fb3e-645c-447a-84c7-d40071aa8a59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888684526 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3888684526
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.4161477872
Short name T1310
Test name
Test status
Simulation time 36558392 ps
CPU time 0.56 seconds
Started May 28 01:03:07 PM PDT 24
Finished May 28 01:03:12 PM PDT 24
Peak memory 194112 kb
Host smart-143bd5ee-7ab2-49ce-95a3-48d96e307fe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161477872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.4161477872
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3741875455
Short name T1210
Test name
Test status
Simulation time 20358964 ps
CPU time 0.61 seconds
Started May 28 01:03:17 PM PDT 24
Finished May 28 01:03:27 PM PDT 24
Peak memory 194272 kb
Host smart-e99a3f34-9d5f-4a63-8126-75a6c2edb71a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741875455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3741875455
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2392959865
Short name T1197
Test name
Test status
Simulation time 798835457 ps
CPU time 1.45 seconds
Started May 28 01:03:13 PM PDT 24
Finished May 28 01:03:22 PM PDT 24
Peak memory 199828 kb
Host smart-1232ea45-4fc6-4283-aba2-f4fa36ebc3c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392959865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2392959865
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.719607470
Short name T1314
Test name
Test status
Simulation time 90370049 ps
CPU time 1.33 seconds
Started May 28 01:03:15 PM PDT 24
Finished May 28 01:03:25 PM PDT 24
Peak memory 199192 kb
Host smart-bb79c8cd-5817-456d-a779-d55ae3fe4916
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719607470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.719607470
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2830620698
Short name T1259
Test name
Test status
Simulation time 212314578 ps
CPU time 0.78 seconds
Started May 28 01:03:24 PM PDT 24
Finished May 28 01:03:35 PM PDT 24
Peak memory 199672 kb
Host smart-0f98961f-872b-4489-b2b7-1219173c91c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830620698 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2830620698
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3752333136
Short name T1268
Test name
Test status
Simulation time 32043464 ps
CPU time 0.59 seconds
Started May 28 01:03:21 PM PDT 24
Finished May 28 01:03:32 PM PDT 24
Peak memory 195492 kb
Host smart-d78f8f92-e1bd-4f1d-a1f4-e090647e6e91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752333136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3752333136
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2393684916
Short name T1233
Test name
Test status
Simulation time 12722254 ps
CPU time 0.58 seconds
Started May 28 01:03:31 PM PDT 24
Finished May 28 01:03:40 PM PDT 24
Peak memory 194204 kb
Host smart-860507f7-6f46-4149-b8c1-a2149ff5054c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393684916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2393684916
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.4057064746
Short name T1230
Test name
Test status
Simulation time 133057313 ps
CPU time 2.69 seconds
Started May 28 01:03:36 PM PDT 24
Finished May 28 01:03:46 PM PDT 24
Peak memory 199840 kb
Host smart-9f0a7cfd-90c0-4827-8014-9869208a7f34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057064746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.4057064746
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3406812214
Short name T98
Test name
Test status
Simulation time 52684423 ps
CPU time 0.96 seconds
Started May 28 01:03:36 PM PDT 24
Finished May 28 01:03:45 PM PDT 24
Peak memory 198752 kb
Host smart-05c88820-b60c-4466-ac81-51b3cda83f61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406812214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3406812214
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3474279352
Short name T1190
Test name
Test status
Simulation time 17775895 ps
CPU time 0.63 seconds
Started May 28 01:03:24 PM PDT 24
Finished May 28 01:03:35 PM PDT 24
Peak memory 197296 kb
Host smart-9a2c66b9-8df2-4ad2-aee4-1fcdf3d2bb54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474279352 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3474279352
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3996357735
Short name T1258
Test name
Test status
Simulation time 24272676 ps
CPU time 0.59 seconds
Started May 28 01:03:31 PM PDT 24
Finished May 28 01:03:40 PM PDT 24
Peak memory 195172 kb
Host smart-929c38bc-6141-441f-9f38-9c7f3ff40208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996357735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3996357735
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1985075467
Short name T1191
Test name
Test status
Simulation time 13315779 ps
CPU time 0.58 seconds
Started May 28 01:03:22 PM PDT 24
Finished May 28 01:03:37 PM PDT 24
Peak memory 194100 kb
Host smart-70d38280-9aa9-4c83-99f6-f61bb91fd8b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985075467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1985075467
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2832859396
Short name T82
Test name
Test status
Simulation time 66905263 ps
CPU time 0.65 seconds
Started May 28 01:03:29 PM PDT 24
Finished May 28 01:03:38 PM PDT 24
Peak memory 195440 kb
Host smart-0417343b-6ef4-4a4e-be7a-46d9b044d27d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832859396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2832859396
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2348358225
Short name T1237
Test name
Test status
Simulation time 23275399 ps
CPU time 1.1 seconds
Started May 28 01:03:25 PM PDT 24
Finished May 28 01:03:36 PM PDT 24
Peak memory 199844 kb
Host smart-06dd6862-7872-45c5-922d-11d1877bcfa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348358225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2348358225
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.615662481
Short name T91
Test name
Test status
Simulation time 235074252 ps
CPU time 1.24 seconds
Started May 28 01:03:31 PM PDT 24
Finished May 28 01:03:41 PM PDT 24
Peak memory 199172 kb
Host smart-e7a54ea3-49d6-4efe-846c-bbe93440d8bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615662481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.615662481
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2847990659
Short name T1297
Test name
Test status
Simulation time 79970406 ps
CPU time 0.68 seconds
Started May 28 01:03:49 PM PDT 24
Finished May 28 01:03:55 PM PDT 24
Peak memory 197540 kb
Host smart-e93e8edc-bbd7-48d1-8f5a-a4fa465494ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847990659 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2847990659
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3472011805
Short name T1296
Test name
Test status
Simulation time 64904604 ps
CPU time 0.61 seconds
Started May 28 01:03:32 PM PDT 24
Finished May 28 01:03:41 PM PDT 24
Peak memory 195228 kb
Host smart-e3e2ca6f-c8d2-44f8-bdaf-f04c99bc39e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472011805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3472011805
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2444281250
Short name T1203
Test name
Test status
Simulation time 36385009 ps
CPU time 0.57 seconds
Started May 28 01:03:33 PM PDT 24
Finished May 28 01:03:42 PM PDT 24
Peak memory 194208 kb
Host smart-4617bb41-3622-4fcd-a0f0-e055458e4276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444281250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2444281250
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2746698218
Short name T1315
Test name
Test status
Simulation time 50743066 ps
CPU time 0.67 seconds
Started May 28 01:03:27 PM PDT 24
Finished May 28 01:03:37 PM PDT 24
Peak memory 196596 kb
Host smart-779929b5-81e7-4349-9ca8-abfb94aab44a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746698218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2746698218
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.82822490
Short name T1266
Test name
Test status
Simulation time 40970317 ps
CPU time 2.15 seconds
Started May 28 01:03:37 PM PDT 24
Finished May 28 01:03:46 PM PDT 24
Peak memory 199828 kb
Host smart-8a76f173-85c1-43cf-a2f1-9d8cdbba6877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82822490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.82822490
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1008005953
Short name T92
Test name
Test status
Simulation time 1392022121 ps
CPU time 1.49 seconds
Started May 28 01:03:45 PM PDT 24
Finished May 28 01:03:52 PM PDT 24
Peak memory 199012 kb
Host smart-ef071efb-ef40-410f-b4c5-b3b8d9e51a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008005953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1008005953
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.184386282
Short name T1283
Test name
Test status
Simulation time 34983681 ps
CPU time 0.69 seconds
Started May 28 01:03:36 PM PDT 24
Finished May 28 01:03:44 PM PDT 24
Peak memory 197756 kb
Host smart-0a0069f2-6432-4b1b-b090-92596a8b3533
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184386282 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.184386282
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.721093268
Short name T1278
Test name
Test status
Simulation time 38201472 ps
CPU time 0.6 seconds
Started May 28 01:03:20 PM PDT 24
Finished May 28 01:03:31 PM PDT 24
Peak memory 195160 kb
Host smart-e940f8b9-14cc-4004-9efd-062a2a035708
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721093268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.721093268
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1810679175
Short name T1256
Test name
Test status
Simulation time 42329293 ps
CPU time 0.59 seconds
Started May 28 01:03:34 PM PDT 24
Finished May 28 01:03:42 PM PDT 24
Peak memory 194132 kb
Host smart-578d1dd1-db84-4327-b03c-b69bed057fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810679175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1810679175
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2680249613
Short name T87
Test name
Test status
Simulation time 18521353 ps
CPU time 0.61 seconds
Started May 28 01:03:35 PM PDT 24
Finished May 28 01:03:43 PM PDT 24
Peak memory 195368 kb
Host smart-a5b70246-e75a-4403-9365-6afd87703923
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680249613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2680249613
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.956437592
Short name T1195
Test name
Test status
Simulation time 291119479 ps
CPU time 0.97 seconds
Started May 28 01:03:23 PM PDT 24
Finished May 28 01:03:34 PM PDT 24
Peak memory 199612 kb
Host smart-bd8d5194-5e1d-4e7f-88f7-4d83ca184c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956437592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.956437592
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3926281594
Short name T1229
Test name
Test status
Simulation time 50827973 ps
CPU time 0.95 seconds
Started May 28 01:03:29 PM PDT 24
Finished May 28 01:03:39 PM PDT 24
Peak memory 198860 kb
Host smart-7f77299c-e75a-4b7b-baf2-d9b7b3bc7ea3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926281594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3926281594
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2359404189
Short name T1286
Test name
Test status
Simulation time 17788620 ps
CPU time 0.81 seconds
Started May 28 01:03:29 PM PDT 24
Finished May 28 01:03:38 PM PDT 24
Peak memory 199660 kb
Host smart-2da438df-e047-4f43-a2a1-fa928024c506
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359404189 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2359404189
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.4024794887
Short name T1247
Test name
Test status
Simulation time 15775506 ps
CPU time 0.56 seconds
Started May 28 01:03:32 PM PDT 24
Finished May 28 01:03:41 PM PDT 24
Peak memory 195152 kb
Host smart-838a3ce9-055a-4036-8b61-48a4c6605500
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024794887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.4024794887
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.567573588
Short name T1316
Test name
Test status
Simulation time 42508003 ps
CPU time 0.59 seconds
Started May 28 01:03:23 PM PDT 24
Finished May 28 01:03:34 PM PDT 24
Peak memory 194192 kb
Host smart-1bf4cfef-f357-4d2b-a002-93a204082156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567573588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.567573588
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3332768331
Short name T1311
Test name
Test status
Simulation time 23540186 ps
CPU time 0.72 seconds
Started May 28 01:03:28 PM PDT 24
Finished May 28 01:03:38 PM PDT 24
Peak memory 195492 kb
Host smart-1859e1b3-74d2-405d-91dd-200e145e2265
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332768331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3332768331
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.185821754
Short name T1295
Test name
Test status
Simulation time 517983750 ps
CPU time 1.75 seconds
Started May 28 01:03:29 PM PDT 24
Finished May 28 01:03:40 PM PDT 24
Peak memory 199788 kb
Host smart-2e0171dd-73a1-45a1-a87e-9f966657d0d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185821754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.185821754
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3942397281
Short name T96
Test name
Test status
Simulation time 51012400 ps
CPU time 1.02 seconds
Started May 28 01:03:29 PM PDT 24
Finished May 28 01:03:39 PM PDT 24
Peak memory 198684 kb
Host smart-5400550d-0b85-48a8-b2ad-623e88788331
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942397281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3942397281
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1120179585
Short name T1291
Test name
Test status
Simulation time 65241748 ps
CPU time 0.68 seconds
Started May 28 01:03:43 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 197196 kb
Host smart-35845b9f-4217-4e2e-9c6f-cc3eed306884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120179585 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1120179585
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2879254657
Short name T1270
Test name
Test status
Simulation time 22804023 ps
CPU time 0.58 seconds
Started May 28 01:03:30 PM PDT 24
Finished May 28 01:03:39 PM PDT 24
Peak memory 195172 kb
Host smart-4f785f93-3a28-4039-9fdb-5f1f3528bab2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879254657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2879254657
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2226883548
Short name T1262
Test name
Test status
Simulation time 11377126 ps
CPU time 0.59 seconds
Started May 28 01:03:43 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 194140 kb
Host smart-8f8db0e3-0a8f-479c-8a53-1da0b7ce7c59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226883548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2226883548
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3673549201
Short name T1303
Test name
Test status
Simulation time 70357333 ps
CPU time 0.62 seconds
Started May 28 01:03:24 PM PDT 24
Finished May 28 01:03:34 PM PDT 24
Peak memory 195348 kb
Host smart-5008d74d-e491-4ed7-9454-a34b2acd5fca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673549201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3673549201
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2347851454
Short name T1240
Test name
Test status
Simulation time 559847338 ps
CPU time 1.89 seconds
Started May 28 01:03:36 PM PDT 24
Finished May 28 01:03:45 PM PDT 24
Peak memory 199868 kb
Host smart-20c304f2-f1ba-4344-a6e4-b737c4719802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347851454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2347851454
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1687858556
Short name T1309
Test name
Test status
Simulation time 165904594 ps
CPU time 0.97 seconds
Started May 28 01:03:34 PM PDT 24
Finished May 28 01:03:43 PM PDT 24
Peak memory 198728 kb
Host smart-1d100fc5-a343-4c20-a649-a4c927dd3d04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687858556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1687858556
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2581166016
Short name T1187
Test name
Test status
Simulation time 72023757 ps
CPU time 1.26 seconds
Started May 28 01:03:34 PM PDT 24
Finished May 28 01:03:43 PM PDT 24
Peak memory 199872 kb
Host smart-078ceab8-2fd6-4813-9562-112d5a762ddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581166016 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2581166016
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.640118269
Short name T1186
Test name
Test status
Simulation time 55152114 ps
CPU time 0.61 seconds
Started May 28 01:03:30 PM PDT 24
Finished May 28 01:03:39 PM PDT 24
Peak memory 195240 kb
Host smart-e786d820-445b-4cde-bce2-32db9b119b7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640118269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.640118269
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2924092247
Short name T1267
Test name
Test status
Simulation time 13408409 ps
CPU time 0.58 seconds
Started May 28 01:03:26 PM PDT 24
Finished May 28 01:03:36 PM PDT 24
Peak memory 194144 kb
Host smart-2e2a1ca1-83d5-412c-a2f9-af53475f8411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924092247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2924092247
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1005902334
Short name T89
Test name
Test status
Simulation time 163847337 ps
CPU time 0.64 seconds
Started May 28 01:03:35 PM PDT 24
Finished May 28 01:03:43 PM PDT 24
Peak memory 194512 kb
Host smart-30ccdd09-a5a6-486e-b561-d7cdf5561c55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005902334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1005902334
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2097046434
Short name T1235
Test name
Test status
Simulation time 192324761 ps
CPU time 1.98 seconds
Started May 28 01:03:22 PM PDT 24
Finished May 28 01:03:34 PM PDT 24
Peak memory 199828 kb
Host smart-95484348-d04e-4488-88fc-bad718a6b980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097046434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2097046434
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.264369189
Short name T122
Test name
Test status
Simulation time 547645418 ps
CPU time 1.28 seconds
Started May 28 01:03:31 PM PDT 24
Finished May 28 01:03:41 PM PDT 24
Peak memory 199012 kb
Host smart-34cdd5d3-5ef0-4afd-a196-247aa4109a16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264369189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.264369189
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2538604456
Short name T1183
Test name
Test status
Simulation time 21664505 ps
CPU time 0.67 seconds
Started May 28 01:03:20 PM PDT 24
Finished May 28 01:03:31 PM PDT 24
Peak memory 197448 kb
Host smart-f27ccd53-87d8-410e-b102-3bd180c11cf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538604456 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2538604456
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2582448679
Short name T1238
Test name
Test status
Simulation time 14982717 ps
CPU time 0.61 seconds
Started May 28 01:03:37 PM PDT 24
Finished May 28 01:03:45 PM PDT 24
Peak memory 195168 kb
Host smart-732fac76-33de-4861-a036-ab86afdb19e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582448679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2582448679
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.463979582
Short name T1196
Test name
Test status
Simulation time 11119150 ps
CPU time 0.56 seconds
Started May 28 01:03:24 PM PDT 24
Finished May 28 01:03:35 PM PDT 24
Peak memory 194188 kb
Host smart-37b107b6-8e03-43d9-a707-41590f93f9fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463979582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.463979582
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1830399920
Short name T86
Test name
Test status
Simulation time 67415231 ps
CPU time 0.7 seconds
Started May 28 01:03:43 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 195540 kb
Host smart-cf3293e8-b733-4f35-aa5a-c507dbc1accd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830399920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1830399920
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1049764043
Short name T1289
Test name
Test status
Simulation time 102566600 ps
CPU time 1.86 seconds
Started May 28 01:03:24 PM PDT 24
Finished May 28 01:03:36 PM PDT 24
Peak memory 199824 kb
Host smart-bb9588dd-742a-48a1-b238-b6dd64423ec4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049764043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1049764043
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1098265809
Short name T123
Test name
Test status
Simulation time 290494773 ps
CPU time 1.23 seconds
Started May 28 01:03:27 PM PDT 24
Finished May 28 01:03:37 PM PDT 24
Peak memory 199040 kb
Host smart-5ca88f16-414f-4fb6-bf14-c46f86dbb95f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098265809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1098265809
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2919233884
Short name T1253
Test name
Test status
Simulation time 44226996 ps
CPU time 0.93 seconds
Started May 28 01:03:41 PM PDT 24
Finished May 28 01:03:48 PM PDT 24
Peak memory 199664 kb
Host smart-f980da13-c833-4983-9a38-bc4779611630
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919233884 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2919233884
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1287602362
Short name T90
Test name
Test status
Simulation time 14456776 ps
CPU time 0.66 seconds
Started May 28 01:03:18 PM PDT 24
Finished May 28 01:03:28 PM PDT 24
Peak memory 195268 kb
Host smart-c32f716a-42fb-4213-b667-c1cab383adb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287602362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1287602362
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.569361309
Short name T1194
Test name
Test status
Simulation time 21604491 ps
CPU time 0.54 seconds
Started May 28 01:03:24 PM PDT 24
Finished May 28 01:03:35 PM PDT 24
Peak memory 194180 kb
Host smart-e62d1fac-8a81-4212-b459-6d4efba8706e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569361309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.569361309
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1724815749
Short name T1243
Test name
Test status
Simulation time 25439517 ps
CPU time 0.73 seconds
Started May 28 01:03:42 PM PDT 24
Finished May 28 01:03:48 PM PDT 24
Peak memory 196888 kb
Host smart-5c319f5c-3893-4b03-a8b6-cf82935f7986
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724815749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1724815749
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2480116008
Short name T1301
Test name
Test status
Simulation time 1452063571 ps
CPU time 2.14 seconds
Started May 28 01:03:31 PM PDT 24
Finished May 28 01:03:42 PM PDT 24
Peak memory 199724 kb
Host smart-2f2f7195-1270-46fb-a5dc-ad612516d79f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480116008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2480116008
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1965988751
Short name T1318
Test name
Test status
Simulation time 32583152 ps
CPU time 1.21 seconds
Started May 28 01:03:32 PM PDT 24
Finished May 28 01:03:45 PM PDT 24
Peak memory 199868 kb
Host smart-fbf805fb-528b-4a14-868a-6c3522ae207c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965988751 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1965988751
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3408179092
Short name T70
Test name
Test status
Simulation time 23297507 ps
CPU time 0.59 seconds
Started May 28 01:03:37 PM PDT 24
Finished May 28 01:03:45 PM PDT 24
Peak memory 195220 kb
Host smart-a22e6526-d3f2-4ec6-b9c2-85f74bf68c62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408179092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3408179092
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1661821905
Short name T1209
Test name
Test status
Simulation time 42757022 ps
CPU time 0.55 seconds
Started May 28 01:03:32 PM PDT 24
Finished May 28 01:03:41 PM PDT 24
Peak memory 194140 kb
Host smart-18426955-b7f9-4b56-93e9-5b7458221dce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661821905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1661821905
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1031014647
Short name T1232
Test name
Test status
Simulation time 189275895 ps
CPU time 0.77 seconds
Started May 28 01:03:42 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 197428 kb
Host smart-a21f72ef-89fb-4aae-a561-f27c3c2d6c7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031014647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1031014647
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.971753753
Short name T1218
Test name
Test status
Simulation time 127773630 ps
CPU time 1.33 seconds
Started May 28 01:03:31 PM PDT 24
Finished May 28 01:03:40 PM PDT 24
Peak memory 199824 kb
Host smart-253b3e84-bf83-4db8-ac3b-f97496b443a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971753753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.971753753
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.4250344723
Short name T99
Test name
Test status
Simulation time 56459887 ps
CPU time 0.93 seconds
Started May 28 01:03:32 PM PDT 24
Finished May 28 01:03:41 PM PDT 24
Peak memory 198668 kb
Host smart-7287e745-60c9-4493-a443-48691500efea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250344723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.4250344723
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2994096553
Short name T1204
Test name
Test status
Simulation time 21501193 ps
CPU time 0.7 seconds
Started May 28 01:03:12 PM PDT 24
Finished May 28 01:03:21 PM PDT 24
Peak memory 195392 kb
Host smart-8e584b70-32fb-4a4e-b5e8-21fb160dfbbf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994096553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2994096553
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4033432670
Short name T1264
Test name
Test status
Simulation time 123885844 ps
CPU time 1.44 seconds
Started May 28 01:03:20 PM PDT 24
Finished May 28 01:03:32 PM PDT 24
Peak memory 197712 kb
Host smart-fb4e628b-b431-44f8-91c3-c514205d3870
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033432670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.4033432670
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4160243551
Short name T1223
Test name
Test status
Simulation time 14010194 ps
CPU time 0.59 seconds
Started May 28 01:03:34 PM PDT 24
Finished May 28 01:03:42 PM PDT 24
Peak memory 195168 kb
Host smart-bb5a153b-bfd9-4925-9c04-afde6c492fe6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160243551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.4160243551
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4138152983
Short name T1224
Test name
Test status
Simulation time 20479465 ps
CPU time 0.7 seconds
Started May 28 01:03:27 PM PDT 24
Finished May 28 01:03:37 PM PDT 24
Peak memory 198132 kb
Host smart-4701a247-6009-4e93-b64f-0e7776120812
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138152983 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.4138152983
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2392274603
Short name T1227
Test name
Test status
Simulation time 24100492 ps
CPU time 0.56 seconds
Started May 28 01:03:22 PM PDT 24
Finished May 28 01:03:33 PM PDT 24
Peak memory 195164 kb
Host smart-af5b2f9d-1195-4627-b066-aac02f3165e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392274603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2392274603
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1377385279
Short name T1250
Test name
Test status
Simulation time 41364887 ps
CPU time 0.58 seconds
Started May 28 01:03:10 PM PDT 24
Finished May 28 01:03:17 PM PDT 24
Peak memory 194116 kb
Host smart-f2e0a5e2-2b14-4f08-99aa-9b89c26d28fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377385279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1377385279
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.49224885
Short name T1239
Test name
Test status
Simulation time 29559416 ps
CPU time 0.77 seconds
Started May 28 01:03:18 PM PDT 24
Finished May 28 01:03:28 PM PDT 24
Peak memory 196792 kb
Host smart-a069aaa3-414e-43d3-9076-65942b28cee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49224885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_o
utstanding.49224885
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.1804495168
Short name T1242
Test name
Test status
Simulation time 177438357 ps
CPU time 1.09 seconds
Started May 28 01:03:15 PM PDT 24
Finished May 28 01:03:30 PM PDT 24
Peak memory 199764 kb
Host smart-40c32b00-9203-4cb6-85ba-85d7b1d61ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804495168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1804495168
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2656143888
Short name T120
Test name
Test status
Simulation time 137837798 ps
CPU time 0.92 seconds
Started May 28 01:03:15 PM PDT 24
Finished May 28 01:03:24 PM PDT 24
Peak memory 198512 kb
Host smart-15734966-994f-4490-b623-35eead1fc3d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656143888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2656143888
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2803310459
Short name T1198
Test name
Test status
Simulation time 31313913 ps
CPU time 0.56 seconds
Started May 28 01:03:36 PM PDT 24
Finished May 28 01:03:43 PM PDT 24
Peak memory 194184 kb
Host smart-b94256a9-db39-4a76-b5a4-f677fe3a0c59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803310459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2803310459
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1039553981
Short name T1246
Test name
Test status
Simulation time 15258348 ps
CPU time 0.59 seconds
Started May 28 01:03:37 PM PDT 24
Finished May 28 01:03:45 PM PDT 24
Peak memory 194144 kb
Host smart-a7cba5de-bd31-4c58-9c01-f9cffe8405a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039553981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1039553981
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2151343218
Short name T1199
Test name
Test status
Simulation time 15440377 ps
CPU time 0.57 seconds
Started May 28 01:03:37 PM PDT 24
Finished May 28 01:03:45 PM PDT 24
Peak memory 194200 kb
Host smart-6e262dc0-a8a8-45a0-a73d-877ce39ddfca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151343218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2151343218
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.135860977
Short name T1226
Test name
Test status
Simulation time 40262947 ps
CPU time 0.6 seconds
Started May 28 01:03:28 PM PDT 24
Finished May 28 01:03:38 PM PDT 24
Peak memory 194124 kb
Host smart-1cd62eed-8a64-42f2-9999-8289fea51003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135860977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.135860977
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1932305561
Short name T1287
Test name
Test status
Simulation time 16629390 ps
CPU time 0.58 seconds
Started May 28 01:03:40 PM PDT 24
Finished May 28 01:03:52 PM PDT 24
Peak memory 194208 kb
Host smart-3f7e229d-52be-495b-b2f5-8138d174422f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932305561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1932305561
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1987796543
Short name T1276
Test name
Test status
Simulation time 40083281 ps
CPU time 0.6 seconds
Started May 28 01:03:37 PM PDT 24
Finished May 28 01:03:44 PM PDT 24
Peak memory 194204 kb
Host smart-db6f05bc-6aa9-4e08-ba81-507c35cbdece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987796543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1987796543
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1650059173
Short name T1298
Test name
Test status
Simulation time 16711436 ps
CPU time 0.56 seconds
Started May 28 01:03:28 PM PDT 24
Finished May 28 01:03:37 PM PDT 24
Peak memory 194144 kb
Host smart-79e4854d-b490-446d-b2dc-a502698310a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650059173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1650059173
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2778329804
Short name T1279
Test name
Test status
Simulation time 43306167 ps
CPU time 0.57 seconds
Started May 28 01:03:24 PM PDT 24
Finished May 28 01:03:35 PM PDT 24
Peak memory 194144 kb
Host smart-ed24ec22-e9b3-4a5b-b288-0e51f8a65393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778329804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2778329804
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.816919274
Short name T1281
Test name
Test status
Simulation time 14459116 ps
CPU time 0.56 seconds
Started May 28 01:03:32 PM PDT 24
Finished May 28 01:03:40 PM PDT 24
Peak memory 194124 kb
Host smart-626f74a9-d592-4798-8541-0f4df5dafc5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816919274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.816919274
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1178983422
Short name T1275
Test name
Test status
Simulation time 48769086 ps
CPU time 0.55 seconds
Started May 28 01:03:23 PM PDT 24
Finished May 28 01:03:34 PM PDT 24
Peak memory 194132 kb
Host smart-d93b5647-53e9-4de5-932f-edf6eb8055ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178983422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1178983422
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1770319952
Short name T1317
Test name
Test status
Simulation time 27998932 ps
CPU time 0.79 seconds
Started May 28 01:03:20 PM PDT 24
Finished May 28 01:03:31 PM PDT 24
Peak memory 196348 kb
Host smart-1482794c-5fa1-4c66-97e2-ad0c0fb6bf3e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770319952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1770319952
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2549444129
Short name T1300
Test name
Test status
Simulation time 455001079 ps
CPU time 2.59 seconds
Started May 28 01:03:19 PM PDT 24
Finished May 28 01:03:31 PM PDT 24
Peak memory 197476 kb
Host smart-68e698f8-893d-4dde-aaef-6d73061d7995
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549444129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2549444129
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.109905111
Short name T1241
Test name
Test status
Simulation time 23776064 ps
CPU time 0.58 seconds
Started May 28 01:03:27 PM PDT 24
Finished May 28 01:03:37 PM PDT 24
Peak memory 195164 kb
Host smart-a6e402b1-cc48-49d5-adae-ef637a0b7aba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109905111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.109905111
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2336308567
Short name T1214
Test name
Test status
Simulation time 45630066 ps
CPU time 1.19 seconds
Started May 28 01:03:12 PM PDT 24
Finished May 28 01:03:22 PM PDT 24
Peak memory 199836 kb
Host smart-e2457a7d-8cd9-4376-9143-a7db1ec2ffa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336308567 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2336308567
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1294866328
Short name T1236
Test name
Test status
Simulation time 29410116 ps
CPU time 0.62 seconds
Started May 28 01:03:21 PM PDT 24
Finished May 28 01:03:32 PM PDT 24
Peak memory 195068 kb
Host smart-0d812da3-4eb0-49a7-9302-b8bfc84b73e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294866328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1294866328
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1019338754
Short name T1254
Test name
Test status
Simulation time 12808132 ps
CPU time 0.55 seconds
Started May 28 01:03:14 PM PDT 24
Finished May 28 01:03:22 PM PDT 24
Peak memory 194112 kb
Host smart-d3b7f2d2-4e7f-4fa6-b06e-fe8646794ff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019338754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1019338754
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1265941263
Short name T1219
Test name
Test status
Simulation time 13215511 ps
CPU time 0.66 seconds
Started May 28 01:03:17 PM PDT 24
Finished May 28 01:03:27 PM PDT 24
Peak memory 194368 kb
Host smart-8aad4d47-40b1-4f98-b867-6d5cc87febd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265941263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1265941263
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1656015840
Short name T1216
Test name
Test status
Simulation time 250798456 ps
CPU time 1.28 seconds
Started May 28 01:03:17 PM PDT 24
Finished May 28 01:03:27 PM PDT 24
Peak memory 199828 kb
Host smart-5b2cf1d0-aeb0-45b5-95a8-5f8a6ac41318
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656015840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1656015840
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2788740889
Short name T94
Test name
Test status
Simulation time 48653550 ps
CPU time 0.94 seconds
Started May 28 01:03:16 PM PDT 24
Finished May 28 01:03:26 PM PDT 24
Peak memory 198792 kb
Host smart-1bb9617b-68e9-4619-aec5-6313c93572b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788740889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2788740889
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3336420747
Short name T1265
Test name
Test status
Simulation time 25708411 ps
CPU time 0.57 seconds
Started May 28 01:03:37 PM PDT 24
Finished May 28 01:03:45 PM PDT 24
Peak memory 194144 kb
Host smart-fee8934e-a717-49f5-bbf7-b102196c9f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336420747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3336420747
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2074313485
Short name T1201
Test name
Test status
Simulation time 16814684 ps
CPU time 0.56 seconds
Started May 28 01:03:36 PM PDT 24
Finished May 28 01:03:44 PM PDT 24
Peak memory 194144 kb
Host smart-74f167a5-e24c-4e00-a1f5-03ef32400d18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074313485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2074313485
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1623348915
Short name T1231
Test name
Test status
Simulation time 15143863 ps
CPU time 0.57 seconds
Started May 28 01:03:31 PM PDT 24
Finished May 28 01:03:40 PM PDT 24
Peak memory 194084 kb
Host smart-1cbae789-7366-45c1-bf42-c7f3a127b44e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623348915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1623348915
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3985630548
Short name T1208
Test name
Test status
Simulation time 18931063 ps
CPU time 0.54 seconds
Started May 28 01:03:43 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 194140 kb
Host smart-3510a369-d5fc-49a6-b370-0abee86ddc4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985630548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3985630548
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1035380842
Short name T1217
Test name
Test status
Simulation time 38958743 ps
CPU time 0.57 seconds
Started May 28 01:03:27 PM PDT 24
Finished May 28 01:03:36 PM PDT 24
Peak memory 194140 kb
Host smart-a4db70f4-f02c-4195-a306-2645d3ab9d2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035380842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1035380842
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1296818333
Short name T1207
Test name
Test status
Simulation time 94619276 ps
CPU time 0.55 seconds
Started May 28 01:03:52 PM PDT 24
Finished May 28 01:03:56 PM PDT 24
Peak memory 194200 kb
Host smart-cd00eeb2-4309-4c04-933b-43cb6ee9f953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296818333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1296818333
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3296958163
Short name T1261
Test name
Test status
Simulation time 153662951 ps
CPU time 0.58 seconds
Started May 28 01:03:22 PM PDT 24
Finished May 28 01:03:33 PM PDT 24
Peak memory 194208 kb
Host smart-aad733b8-e670-46ea-a762-5f9f13a8d7e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296958163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3296958163
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.4284530864
Short name T1225
Test name
Test status
Simulation time 31398911 ps
CPU time 0.61 seconds
Started May 28 01:03:38 PM PDT 24
Finished May 28 01:03:46 PM PDT 24
Peak memory 194148 kb
Host smart-fd65abe4-5755-43d6-bb7a-9748e6c1ca53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284530864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.4284530864
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2917513350
Short name T1308
Test name
Test status
Simulation time 14530822 ps
CPU time 0.57 seconds
Started May 28 01:03:41 PM PDT 24
Finished May 28 01:03:47 PM PDT 24
Peak memory 194200 kb
Host smart-a34a0ec5-178c-4852-b26d-bf93e793b2b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917513350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2917513350
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.815811570
Short name T1184
Test name
Test status
Simulation time 50962277 ps
CPU time 0.54 seconds
Started May 28 01:03:28 PM PDT 24
Finished May 28 01:03:38 PM PDT 24
Peak memory 194188 kb
Host smart-73ed51fc-8a58-45bf-92f4-e75a661993b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815811570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.815811570
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2571185286
Short name T69
Test name
Test status
Simulation time 24009505 ps
CPU time 0.66 seconds
Started May 28 01:03:21 PM PDT 24
Finished May 28 01:03:32 PM PDT 24
Peak memory 194676 kb
Host smart-58cab87f-ed0c-492c-b094-22e0a520246c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571185286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2571185286
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.484663445
Short name T1248
Test name
Test status
Simulation time 35949178 ps
CPU time 1.4 seconds
Started May 28 01:03:27 PM PDT 24
Finished May 28 01:03:38 PM PDT 24
Peak memory 197312 kb
Host smart-95903c01-2597-4d25-8d59-4c5acb5994d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484663445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.484663445
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.494119484
Short name T1220
Test name
Test status
Simulation time 25445737 ps
CPU time 0.55 seconds
Started May 28 01:03:23 PM PDT 24
Finished May 28 01:03:33 PM PDT 24
Peak memory 195164 kb
Host smart-9d05040d-bcd6-4d13-b807-af4c5999d955
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494119484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.494119484
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3282567787
Short name T1228
Test name
Test status
Simulation time 21906219 ps
CPU time 1.05 seconds
Started May 28 01:03:13 PM PDT 24
Finished May 28 01:03:22 PM PDT 24
Peak memory 199776 kb
Host smart-8b665f85-3367-495d-80c2-8e3186b6ed3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282567787 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3282567787
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3576470155
Short name T1215
Test name
Test status
Simulation time 18540054 ps
CPU time 0.6 seconds
Started May 28 01:03:08 PM PDT 24
Finished May 28 01:03:14 PM PDT 24
Peak memory 195232 kb
Host smart-22165f2c-bc81-4021-92a5-89bdf6251840
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576470155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3576470155
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.4239750332
Short name T1202
Test name
Test status
Simulation time 12031655 ps
CPU time 0.57 seconds
Started May 28 01:03:18 PM PDT 24
Finished May 28 01:03:28 PM PDT 24
Peak memory 194144 kb
Host smart-e086efb6-6fd2-40d8-99d5-7ef08a94b610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239750332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4239750332
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1602780269
Short name T81
Test name
Test status
Simulation time 19774057 ps
CPU time 0.63 seconds
Started May 28 01:03:29 PM PDT 24
Finished May 28 01:03:38 PM PDT 24
Peak memory 195424 kb
Host smart-bfa39bf9-769b-4256-8e5c-9f3f9eed5008
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602780269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1602780269
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1216201287
Short name T1211
Test name
Test status
Simulation time 186493826 ps
CPU time 2.38 seconds
Started May 28 01:03:20 PM PDT 24
Finished May 28 01:03:32 PM PDT 24
Peak memory 199732 kb
Host smart-63fc67d6-c0bb-4753-8580-2fd53b487a92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216201287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1216201287
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3720544635
Short name T1274
Test name
Test status
Simulation time 242162930 ps
CPU time 0.9 seconds
Started May 28 01:03:20 PM PDT 24
Finished May 28 01:03:31 PM PDT 24
Peak memory 198656 kb
Host smart-27c006bf-7ea0-4577-ba20-6a556e5df776
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720544635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3720544635
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2556183096
Short name T1213
Test name
Test status
Simulation time 37857540 ps
CPU time 0.54 seconds
Started May 28 01:03:30 PM PDT 24
Finished May 28 01:03:39 PM PDT 24
Peak memory 194132 kb
Host smart-5a77cc96-9ccd-48b3-baff-85074607e281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556183096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2556183096
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3916724332
Short name T1290
Test name
Test status
Simulation time 23637170 ps
CPU time 0.57 seconds
Started May 28 01:03:24 PM PDT 24
Finished May 28 01:03:34 PM PDT 24
Peak memory 194144 kb
Host smart-b31e6965-7e68-4257-b4f6-e51a05c558d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916724332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3916724332
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2758352731
Short name T1305
Test name
Test status
Simulation time 21647944 ps
CPU time 0.61 seconds
Started May 28 01:03:44 PM PDT 24
Finished May 28 01:03:50 PM PDT 24
Peak memory 194140 kb
Host smart-a1f1d1e3-600d-4439-8e40-1dba9875fea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758352731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2758352731
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3311253802
Short name T1251
Test name
Test status
Simulation time 12007130 ps
CPU time 0.57 seconds
Started May 28 01:03:38 PM PDT 24
Finished May 28 01:03:45 PM PDT 24
Peak memory 194112 kb
Host smart-0dbaae2d-076a-4f8a-8e88-b66227b0a874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311253802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3311253802
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3846595578
Short name T1307
Test name
Test status
Simulation time 20806931 ps
CPU time 0.56 seconds
Started May 28 01:03:36 PM PDT 24
Finished May 28 01:03:44 PM PDT 24
Peak memory 194196 kb
Host smart-533c20b7-dd4b-4f8b-8b58-70187cb6c653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846595578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3846595578
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1591719194
Short name T1185
Test name
Test status
Simulation time 15719546 ps
CPU time 0.54 seconds
Started May 28 01:03:25 PM PDT 24
Finished May 28 01:03:35 PM PDT 24
Peak memory 194128 kb
Host smart-ec77af87-9923-4416-a97d-e64bba558a1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591719194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1591719194
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.475603098
Short name T1193
Test name
Test status
Simulation time 32657947 ps
CPU time 0.55 seconds
Started May 28 01:03:34 PM PDT 24
Finished May 28 01:03:42 PM PDT 24
Peak memory 194128 kb
Host smart-fa058a1e-2ec4-411a-8f2f-0cb7f717a280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475603098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.475603098
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3598178320
Short name T1200
Test name
Test status
Simulation time 21098827 ps
CPU time 0.57 seconds
Started May 28 01:03:40 PM PDT 24
Finished May 28 01:03:47 PM PDT 24
Peak memory 194208 kb
Host smart-00aa7d3d-36d4-4bc1-86c8-0a97bd505588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598178320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3598178320
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3501625538
Short name T1205
Test name
Test status
Simulation time 46846135 ps
CPU time 0.6 seconds
Started May 28 01:03:30 PM PDT 24
Finished May 28 01:03:39 PM PDT 24
Peak memory 194096 kb
Host smart-b8357d53-a410-4d9a-89d9-203a053388bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501625538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3501625538
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.4044780241
Short name T1245
Test name
Test status
Simulation time 144191023 ps
CPU time 0.57 seconds
Started May 28 01:03:38 PM PDT 24
Finished May 28 01:03:45 PM PDT 24
Peak memory 194100 kb
Host smart-cb07de25-f722-4f14-9641-cfc459f94b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044780241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.4044780241
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2690042818
Short name T1288
Test name
Test status
Simulation time 60417007 ps
CPU time 0.63 seconds
Started May 28 01:03:28 PM PDT 24
Finished May 28 01:03:38 PM PDT 24
Peak memory 196736 kb
Host smart-a5e5c043-2bb8-451d-9842-efd244572b31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690042818 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2690042818
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2507144175
Short name T88
Test name
Test status
Simulation time 21669629 ps
CPU time 0.6 seconds
Started May 28 01:03:20 PM PDT 24
Finished May 28 01:03:31 PM PDT 24
Peak memory 195164 kb
Host smart-ff00b35b-b938-4b70-befe-955f2680d791
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507144175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2507144175
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3168785455
Short name T1293
Test name
Test status
Simulation time 12175795 ps
CPU time 0.55 seconds
Started May 28 01:03:28 PM PDT 24
Finished May 28 01:03:38 PM PDT 24
Peak memory 194120 kb
Host smart-a8c20f68-b761-455d-b903-2f218d90d4f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168785455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3168785455
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1717657355
Short name T83
Test name
Test status
Simulation time 61479480 ps
CPU time 0.68 seconds
Started May 28 01:03:38 PM PDT 24
Finished May 28 01:03:45 PM PDT 24
Peak memory 195348 kb
Host smart-b5225baa-cdb7-4fa7-a381-f39f493a0c27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717657355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1717657355
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.247184129
Short name T1292
Test name
Test status
Simulation time 63018960 ps
CPU time 1.28 seconds
Started May 28 01:03:24 PM PDT 24
Finished May 28 01:03:35 PM PDT 24
Peak memory 199848 kb
Host smart-6e96d43d-1f5d-40f0-b302-407cc921b76c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247184129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.247184129
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.4248780906
Short name T97
Test name
Test status
Simulation time 86951494 ps
CPU time 0.92 seconds
Started May 28 01:03:41 PM PDT 24
Finished May 28 01:03:48 PM PDT 24
Peak memory 198568 kb
Host smart-7867473b-4f12-4c18-ae8f-420f514263d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248780906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.4248780906
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.918164957
Short name T1188
Test name
Test status
Simulation time 27353490 ps
CPU time 0.94 seconds
Started May 28 01:03:21 PM PDT 24
Finished May 28 01:03:32 PM PDT 24
Peak memory 199624 kb
Host smart-cefcbf47-a67d-40a5-827b-f5b03e1a6700
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918164957 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.918164957
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1146087106
Short name T84
Test name
Test status
Simulation time 33282072 ps
CPU time 0.57 seconds
Started May 28 01:03:14 PM PDT 24
Finished May 28 01:03:24 PM PDT 24
Peak memory 195292 kb
Host smart-164e4491-bd32-4432-b6b7-177316d40492
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146087106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1146087106
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3691406110
Short name T1263
Test name
Test status
Simulation time 13223813 ps
CPU time 0.57 seconds
Started May 28 01:03:16 PM PDT 24
Finished May 28 01:03:26 PM PDT 24
Peak memory 194136 kb
Host smart-a9b9d29c-5147-4215-8f04-ce691fb1119c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691406110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3691406110
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.604737196
Short name T1299
Test name
Test status
Simulation time 25626865 ps
CPU time 0.62 seconds
Started May 28 01:03:15 PM PDT 24
Finished May 28 01:03:25 PM PDT 24
Peak memory 195328 kb
Host smart-5a1e6d05-71c9-4b11-bc1f-37d650f398b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604737196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.604737196
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.294304449
Short name T1302
Test name
Test status
Simulation time 197646677 ps
CPU time 1.17 seconds
Started May 28 01:03:23 PM PDT 24
Finished May 28 01:03:34 PM PDT 24
Peak memory 199848 kb
Host smart-5689b179-1af1-4823-bc7e-795a1bad213c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294304449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.294304449
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.654432673
Short name T1260
Test name
Test status
Simulation time 92158936 ps
CPU time 0.79 seconds
Started May 28 01:03:20 PM PDT 24
Finished May 28 01:03:30 PM PDT 24
Peak memory 199616 kb
Host smart-594a5d91-4710-4470-ae52-c990013f77cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654432673 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.654432673
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1724458093
Short name T1257
Test name
Test status
Simulation time 11146111 ps
CPU time 0.59 seconds
Started May 28 01:03:08 PM PDT 24
Finished May 28 01:03:15 PM PDT 24
Peak memory 195164 kb
Host smart-052b4241-a54c-43e3-b476-b09b74eb3d43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724458093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1724458093
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.948646752
Short name T1285
Test name
Test status
Simulation time 17202579 ps
CPU time 0.59 seconds
Started May 28 01:03:11 PM PDT 24
Finished May 28 01:03:19 PM PDT 24
Peak memory 194208 kb
Host smart-a23d9c3b-585e-4826-9956-59270718a977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948646752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.948646752
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2923631904
Short name T1212
Test name
Test status
Simulation time 17746292 ps
CPU time 0.69 seconds
Started May 28 01:03:30 PM PDT 24
Finished May 28 01:03:39 PM PDT 24
Peak memory 196608 kb
Host smart-765568f3-8fc2-4a6e-9594-f2110bdd742e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923631904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2923631904
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2422261595
Short name T1313
Test name
Test status
Simulation time 23584919 ps
CPU time 1.13 seconds
Started May 28 01:03:20 PM PDT 24
Finished May 28 01:03:32 PM PDT 24
Peak memory 199812 kb
Host smart-b9c67d50-ca0f-4fb2-a4d6-87d6230405b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422261595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2422261595
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1113697324
Short name T1244
Test name
Test status
Simulation time 71465535 ps
CPU time 1.31 seconds
Started May 28 01:03:17 PM PDT 24
Finished May 28 01:03:28 PM PDT 24
Peak memory 199272 kb
Host smart-9e1eed1f-ff78-4d10-b0fe-effc88ff5787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113697324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1113697324
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.603309328
Short name T1312
Test name
Test status
Simulation time 61061338 ps
CPU time 1.45 seconds
Started May 28 01:03:29 PM PDT 24
Finished May 28 01:03:39 PM PDT 24
Peak memory 199832 kb
Host smart-1c8b60c9-2663-47d4-8c8d-248b0ce3d56a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603309328 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.603309328
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3528330269
Short name T1222
Test name
Test status
Simulation time 30109024 ps
CPU time 0.58 seconds
Started May 28 01:03:40 PM PDT 24
Finished May 28 01:03:46 PM PDT 24
Peak memory 195204 kb
Host smart-00397ee3-5d32-4e10-ad05-81f04031f833
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528330269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3528330269
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1541149959
Short name T1249
Test name
Test status
Simulation time 12952906 ps
CPU time 0.58 seconds
Started May 28 01:03:34 PM PDT 24
Finished May 28 01:03:43 PM PDT 24
Peak memory 194124 kb
Host smart-172df5a4-f75c-438e-9228-29ad8b990067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541149959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1541149959
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2535063456
Short name T1277
Test name
Test status
Simulation time 24743359 ps
CPU time 0.75 seconds
Started May 28 01:03:31 PM PDT 24
Finished May 28 01:03:41 PM PDT 24
Peak memory 196856 kb
Host smart-443a7624-eaa3-4b23-9dd6-c0457de444b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535063456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2535063456
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3027579076
Short name T1192
Test name
Test status
Simulation time 85114968 ps
CPU time 1.99 seconds
Started May 28 01:03:26 PM PDT 24
Finished May 28 01:03:37 PM PDT 24
Peak memory 199828 kb
Host smart-b0b7480e-3e17-4291-9c0e-4c812f6f4c98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027579076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3027579076
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3269475657
Short name T1280
Test name
Test status
Simulation time 69056108 ps
CPU time 0.94 seconds
Started May 28 01:03:27 PM PDT 24
Finished May 28 01:03:37 PM PDT 24
Peak memory 198756 kb
Host smart-6fca66fc-5132-48e5-ab96-a735dd47f739
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269475657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3269475657
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3067309006
Short name T1284
Test name
Test status
Simulation time 20821324 ps
CPU time 0.88 seconds
Started May 28 01:03:30 PM PDT 24
Finished May 28 01:03:39 PM PDT 24
Peak memory 199628 kb
Host smart-ee4f00b4-3306-4ecd-bf1f-21d0793eb18c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067309006 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3067309006
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1259425061
Short name T67
Test name
Test status
Simulation time 67841485 ps
CPU time 0.6 seconds
Started May 28 01:03:40 PM PDT 24
Finished May 28 01:03:47 PM PDT 24
Peak memory 195128 kb
Host smart-2195387e-4b63-4b79-b3a0-1a5be91cbc92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259425061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1259425061
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2769807398
Short name T1306
Test name
Test status
Simulation time 15305544 ps
CPU time 0.59 seconds
Started May 28 01:03:23 PM PDT 24
Finished May 28 01:03:34 PM PDT 24
Peak memory 194132 kb
Host smart-7a3b638c-ea98-47c7-93e1-df54a9a5a129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769807398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2769807398
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.550305673
Short name T1269
Test name
Test status
Simulation time 51355067 ps
CPU time 0.64 seconds
Started May 28 01:03:31 PM PDT 24
Finished May 28 01:03:40 PM PDT 24
Peak memory 194432 kb
Host smart-0834aa77-c162-4aa7-8f02-df15df997542
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550305673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.550305673
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2238443664
Short name T1273
Test name
Test status
Simulation time 50022930 ps
CPU time 1.39 seconds
Started May 28 01:03:28 PM PDT 24
Finished May 28 01:03:38 PM PDT 24
Peak memory 199776 kb
Host smart-1b244709-07ab-4214-bdca-fd6153c23ace
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238443664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2238443664
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/default/0.uart_alert_test.3298466491
Short name T1020
Test name
Test status
Simulation time 38597354 ps
CPU time 0.59 seconds
Started May 28 01:48:48 PM PDT 24
Finished May 28 01:48:53 PM PDT 24
Peak memory 195900 kb
Host smart-77192746-3a94-4270-a265-3f5c95b20189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298466491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3298466491
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.103879522
Short name T302
Test name
Test status
Simulation time 34550943329 ps
CPU time 60.78 seconds
Started May 28 01:48:45 PM PDT 24
Finished May 28 01:49:51 PM PDT 24
Peak memory 200456 kb
Host smart-68b9a4cb-665e-43a9-865f-6ebc845c6959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103879522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.103879522
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1324371249
Short name T626
Test name
Test status
Simulation time 84180909426 ps
CPU time 211.5 seconds
Started May 28 01:48:45 PM PDT 24
Finished May 28 01:52:22 PM PDT 24
Peak memory 200260 kb
Host smart-d672dfcf-0d27-470f-988a-8ad98bfbf169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324371249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1324371249
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3001006394
Short name T506
Test name
Test status
Simulation time 73922238852 ps
CPU time 28.78 seconds
Started May 28 01:48:49 PM PDT 24
Finished May 28 01:49:22 PM PDT 24
Peak memory 200540 kb
Host smart-f7cabe2e-86bc-48d6-8b4c-e2a8d4dc3fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001006394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3001006394
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2325049893
Short name T1019
Test name
Test status
Simulation time 22745218343 ps
CPU time 42.76 seconds
Started May 28 01:48:43 PM PDT 24
Finished May 28 01:49:31 PM PDT 24
Peak memory 200448 kb
Host smart-3f7fb369-54fe-4f88-9baa-bf802622fe73
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325049893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2325049893
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1760535968
Short name T609
Test name
Test status
Simulation time 73439717295 ps
CPU time 241.31 seconds
Started May 28 01:48:45 PM PDT 24
Finished May 28 01:52:51 PM PDT 24
Peak memory 200436 kb
Host smart-a8a8b507-abfb-455e-a33c-1dd2872d1e95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760535968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1760535968
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2596201200
Short name T987
Test name
Test status
Simulation time 1434539653 ps
CPU time 2.94 seconds
Started May 28 01:48:49 PM PDT 24
Finished May 28 01:48:56 PM PDT 24
Peak memory 197364 kb
Host smart-8376db6f-f38b-4c9e-9f29-64e4c39d8f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596201200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2596201200
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.181786825
Short name T877
Test name
Test status
Simulation time 114796141730 ps
CPU time 51.65 seconds
Started May 28 01:48:45 PM PDT 24
Finished May 28 01:49:42 PM PDT 24
Peak memory 210144 kb
Host smart-5a5c6f32-ffa3-48c1-979f-3053408fc1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181786825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.181786825
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1290847812
Short name T617
Test name
Test status
Simulation time 12701208184 ps
CPU time 357 seconds
Started May 28 01:48:47 PM PDT 24
Finished May 28 01:54:48 PM PDT 24
Peak memory 200512 kb
Host smart-84ae8dd7-a530-4251-8140-630e1d02fd6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290847812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1290847812
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3402279654
Short name T627
Test name
Test status
Simulation time 5168779550 ps
CPU time 42.15 seconds
Started May 28 01:48:45 PM PDT 24
Finished May 28 01:49:32 PM PDT 24
Peak memory 198856 kb
Host smart-a932ecf5-d6f6-4e00-9eb0-006d8ababc1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3402279654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3402279654
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2157539885
Short name T312
Test name
Test status
Simulation time 42009757207 ps
CPU time 34.93 seconds
Started May 28 01:48:46 PM PDT 24
Finished May 28 01:49:26 PM PDT 24
Peak memory 200432 kb
Host smart-691a55ad-42eb-4534-bf56-b086732b7951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157539885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2157539885
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1447525839
Short name T394
Test name
Test status
Simulation time 5791973800 ps
CPU time 5.11 seconds
Started May 28 01:48:49 PM PDT 24
Finished May 28 01:48:58 PM PDT 24
Peak memory 196448 kb
Host smart-183c4053-fbaf-47c8-9dbd-8a3c4b188f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447525839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1447525839
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3690403996
Short name T33
Test name
Test status
Simulation time 35106535 ps
CPU time 0.79 seconds
Started May 28 01:48:43 PM PDT 24
Finished May 28 01:48:49 PM PDT 24
Peak memory 218936 kb
Host smart-ec5f5ddc-0a4f-4a40-a99b-90a4107f9366
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690403996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3690403996
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.3193403902
Short name T362
Test name
Test status
Simulation time 5464321016 ps
CPU time 38.13 seconds
Started May 28 01:48:45 PM PDT 24
Finished May 28 01:49:28 PM PDT 24
Peak memory 200280 kb
Host smart-05701b77-6eec-4444-bbb1-03a5ba521515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193403902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3193403902
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.1318376140
Short name T910
Test name
Test status
Simulation time 223673695250 ps
CPU time 388.2 seconds
Started May 28 01:48:47 PM PDT 24
Finished May 28 01:55:20 PM PDT 24
Peak memory 200448 kb
Host smart-a80411bd-3ff8-4a72-baaa-7f5226b88bd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318376140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1318376140
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.250979716
Short name T1064
Test name
Test status
Simulation time 2239283174 ps
CPU time 2.03 seconds
Started May 28 01:48:44 PM PDT 24
Finished May 28 01:48:51 PM PDT 24
Peak memory 198968 kb
Host smart-a095621a-3a50-4c65-b837-b579ebd7b34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250979716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.250979716
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3717884883
Short name T914
Test name
Test status
Simulation time 16256280119 ps
CPU time 19.13 seconds
Started May 28 01:48:46 PM PDT 24
Finished May 28 01:49:10 PM PDT 24
Peak memory 200496 kb
Host smart-9f88e022-f6a0-47b6-be85-882dd18d3c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717884883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3717884883
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3386727583
Short name T950
Test name
Test status
Simulation time 178414115 ps
CPU time 0.56 seconds
Started May 28 01:48:48 PM PDT 24
Finished May 28 01:48:53 PM PDT 24
Peak memory 195908 kb
Host smart-14a42f6c-2dd6-4d2c-a386-83f550c2e3af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386727583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3386727583
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3382799348
Short name T475
Test name
Test status
Simulation time 48673704804 ps
CPU time 44.74 seconds
Started May 28 01:48:43 PM PDT 24
Finished May 28 01:49:33 PM PDT 24
Peak memory 200544 kb
Host smart-f84d257e-9aa6-4415-85bc-41736a054d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382799348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3382799348
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.330261130
Short name T600
Test name
Test status
Simulation time 65726058513 ps
CPU time 100.51 seconds
Started May 28 01:48:45 PM PDT 24
Finished May 28 01:50:30 PM PDT 24
Peak memory 200456 kb
Host smart-323b728c-6b7b-4d4a-a1ea-9d799a61867b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330261130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.330261130
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.671255421
Short name T286
Test name
Test status
Simulation time 11469026978 ps
CPU time 18.67 seconds
Started May 28 01:48:47 PM PDT 24
Finished May 28 01:49:10 PM PDT 24
Peak memory 200432 kb
Host smart-0d1dcc57-9ff8-45e9-9c5d-27b0217a0e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671255421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.671255421
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3551668730
Short name T695
Test name
Test status
Simulation time 3703399667 ps
CPU time 6.14 seconds
Started May 28 01:48:45 PM PDT 24
Finished May 28 01:48:56 PM PDT 24
Peak memory 197176 kb
Host smart-99e793f5-716f-4cec-9100-abf925d5fa6e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551668730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3551668730
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3429833286
Short name T781
Test name
Test status
Simulation time 121828013695 ps
CPU time 647.17 seconds
Started May 28 01:48:48 PM PDT 24
Finished May 28 01:59:39 PM PDT 24
Peak memory 200544 kb
Host smart-e5897e8f-aaa7-49fe-aa31-36638a600fb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3429833286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3429833286
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.228691487
Short name T24
Test name
Test status
Simulation time 3021823437 ps
CPU time 5.34 seconds
Started May 28 01:48:50 PM PDT 24
Finished May 28 01:48:59 PM PDT 24
Peak memory 196944 kb
Host smart-27d0b035-f60d-44c5-8dab-1734d6077b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228691487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.228691487
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1239147676
Short name T734
Test name
Test status
Simulation time 304590410383 ps
CPU time 127.08 seconds
Started May 28 01:48:50 PM PDT 24
Finished May 28 01:51:00 PM PDT 24
Peak memory 200560 kb
Host smart-9eb0613a-321d-48eb-ba7a-54367d284ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239147676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1239147676
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.899421895
Short name T355
Test name
Test status
Simulation time 5718370681 ps
CPU time 13.36 seconds
Started May 28 01:48:45 PM PDT 24
Finished May 28 01:49:04 PM PDT 24
Peak memory 200492 kb
Host smart-c326ebf3-0c7e-4667-b9dd-9c97daf4737f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=899421895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.899421895
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1703896440
Short name T975
Test name
Test status
Simulation time 10089840914 ps
CPU time 10.34 seconds
Started May 28 01:48:46 PM PDT 24
Finished May 28 01:49:01 PM PDT 24
Peak memory 200356 kb
Host smart-72ebe73b-14b4-45f6-bb9e-81a6cdf4c087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703896440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1703896440
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.4266088269
Short name T443
Test name
Test status
Simulation time 625068679 ps
CPU time 1.69 seconds
Started May 28 01:48:44 PM PDT 24
Finished May 28 01:48:51 PM PDT 24
Peak memory 196140 kb
Host smart-0a2c1ef7-fe1e-45b7-8bc4-34591419f112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266088269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4266088269
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.4229971577
Short name T880
Test name
Test status
Simulation time 5884522509 ps
CPU time 10.17 seconds
Started May 28 01:48:48 PM PDT 24
Finished May 28 01:49:03 PM PDT 24
Peak memory 200532 kb
Host smart-3276d0a5-fecc-4107-989d-f5692c059253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229971577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4229971577
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.877696741
Short name T285
Test name
Test status
Simulation time 210259205224 ps
CPU time 163.22 seconds
Started May 28 01:48:51 PM PDT 24
Finished May 28 01:51:37 PM PDT 24
Peak memory 201084 kb
Host smart-5937bfa2-2e97-4a30-b5a2-7a23cc605a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877696741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.877696741
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2593095274
Short name T594
Test name
Test status
Simulation time 196468176383 ps
CPU time 387.24 seconds
Started May 28 01:48:55 PM PDT 24
Finished May 28 01:55:23 PM PDT 24
Peak memory 217164 kb
Host smart-445b9606-9bfe-4d31-834d-08f71542d3d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593095274 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2593095274
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.759988949
Short name T1100
Test name
Test status
Simulation time 5003800544 ps
CPU time 1.37 seconds
Started May 28 01:48:47 PM PDT 24
Finished May 28 01:48:53 PM PDT 24
Peak memory 198988 kb
Host smart-42bb4cf8-1af0-482a-87ee-c978a477e64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759988949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.759988949
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2049090026
Short name T647
Test name
Test status
Simulation time 25804970335 ps
CPU time 53.57 seconds
Started May 28 01:48:46 PM PDT 24
Finished May 28 01:49:44 PM PDT 24
Peak memory 200424 kb
Host smart-0ffce9ee-137e-4d63-a527-8fa923989642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049090026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2049090026
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1535088392
Short name T1170
Test name
Test status
Simulation time 36586211 ps
CPU time 0.57 seconds
Started May 28 01:49:16 PM PDT 24
Finished May 28 01:49:20 PM PDT 24
Peak memory 195848 kb
Host smart-4ec19c9e-6434-4a9b-a010-0d5ceb3594f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535088392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1535088392
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3213778733
Short name T875
Test name
Test status
Simulation time 78099224984 ps
CPU time 13 seconds
Started May 28 01:49:10 PM PDT 24
Finished May 28 01:49:27 PM PDT 24
Peak memory 200748 kb
Host smart-45610e7b-43c0-41bf-b519-1522521c29f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213778733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3213778733
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3260283061
Short name T597
Test name
Test status
Simulation time 61465042172 ps
CPU time 25.48 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:49:43 PM PDT 24
Peak memory 200460 kb
Host smart-5c9b41f1-78ee-46b7-bc6f-29c2f63e58b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260283061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3260283061
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.2894360393
Short name T117
Test name
Test status
Simulation time 48789340749 ps
CPU time 22.61 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:49:39 PM PDT 24
Peak memory 199012 kb
Host smart-c9d62553-7871-4ad5-b52a-c59dd29c4a5e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894360393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2894360393
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2095279657
Short name T706
Test name
Test status
Simulation time 28701534950 ps
CPU time 115.06 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:51:12 PM PDT 24
Peak memory 200464 kb
Host smart-d489f4d8-c7df-4f60-8000-b221bf1519fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095279657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2095279657
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.652790506
Short name T613
Test name
Test status
Simulation time 4525044794 ps
CPU time 3 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:49:20 PM PDT 24
Peak memory 199796 kb
Host smart-e7dc844a-5be4-45c2-9564-d8fbad17ad81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652790506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.652790506
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3472660794
Short name T477
Test name
Test status
Simulation time 52666785802 ps
CPU time 96.76 seconds
Started May 28 01:49:10 PM PDT 24
Finished May 28 01:50:50 PM PDT 24
Peak memory 200752 kb
Host smart-e6a7ebed-610e-4b5d-83b6-6f281c88d43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472660794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3472660794
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.4056403249
Short name T1096
Test name
Test status
Simulation time 21193397675 ps
CPU time 190.28 seconds
Started May 28 01:49:10 PM PDT 24
Finished May 28 01:52:24 PM PDT 24
Peak memory 200508 kb
Host smart-0023a318-d95b-4c9a-9cfc-642fb9a06460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056403249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.4056403249
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2097273854
Short name T685
Test name
Test status
Simulation time 1296652494 ps
CPU time 1.87 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:18 PM PDT 24
Peak memory 198824 kb
Host smart-7a0510e4-737d-4040-88f8-506524658bc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2097273854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2097273854
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1410844852
Short name T578
Test name
Test status
Simulation time 17336634200 ps
CPU time 29.52 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:49:46 PM PDT 24
Peak memory 200468 kb
Host smart-5146c361-d0ae-4650-b77b-2e0b1202a864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410844852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1410844852
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3086301385
Short name T331
Test name
Test status
Simulation time 39172747583 ps
CPU time 15.95 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:49:33 PM PDT 24
Peak memory 196512 kb
Host smart-0c2856e5-b05e-4748-a069-5d9010e930bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086301385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3086301385
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.949104291
Short name T723
Test name
Test status
Simulation time 5753646609 ps
CPU time 12.79 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:28 PM PDT 24
Peak memory 200364 kb
Host smart-817508ca-9324-4c8f-a39c-3d7149b0dcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949104291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.949104291
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1368502930
Short name T72
Test name
Test status
Simulation time 56607902461 ps
CPU time 616.69 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:59:32 PM PDT 24
Peak memory 217276 kb
Host smart-e12c5236-52fb-44e3-9330-b1aaf9af1e35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368502930 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1368502930
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.201208303
Short name T956
Test name
Test status
Simulation time 1428504353 ps
CPU time 5.1 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:21 PM PDT 24
Peak memory 200180 kb
Host smart-890467f6-bfcc-40dd-871f-e066cc3578c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201208303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.201208303
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3953579313
Short name T105
Test name
Test status
Simulation time 116148066793 ps
CPU time 125.77 seconds
Started May 28 01:49:09 PM PDT 24
Finished May 28 01:51:18 PM PDT 24
Peak memory 200452 kb
Host smart-de63db7a-c180-404a-8b60-e3b9e2785d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953579313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3953579313
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.4293521044
Short name T948
Test name
Test status
Simulation time 227401978998 ps
CPU time 98.67 seconds
Started May 28 01:52:34 PM PDT 24
Finished May 28 01:54:16 PM PDT 24
Peak memory 200548 kb
Host smart-618c785a-e244-4b36-bd27-c3b3f8354a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293521044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.4293521044
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1549590332
Short name T448
Test name
Test status
Simulation time 62076768639 ps
CPU time 25.77 seconds
Started May 28 01:52:33 PM PDT 24
Finished May 28 01:53:01 PM PDT 24
Peak memory 200428 kb
Host smart-8bf5dbe2-5b19-45ef-a777-d080acde43ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549590332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1549590332
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2792399286
Short name T656
Test name
Test status
Simulation time 62473709538 ps
CPU time 78.66 seconds
Started May 28 01:52:35 PM PDT 24
Finished May 28 01:53:58 PM PDT 24
Peak memory 200224 kb
Host smart-4aee984f-80a1-42e3-a179-ba6cc645e928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792399286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2792399286
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1173184664
Short name T127
Test name
Test status
Simulation time 22439069568 ps
CPU time 33.02 seconds
Started May 28 01:52:36 PM PDT 24
Finished May 28 01:53:14 PM PDT 24
Peak memory 200520 kb
Host smart-c4258952-29a3-4383-8c61-738ace6ed799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173184664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1173184664
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.662798196
Short name T874
Test name
Test status
Simulation time 106907956940 ps
CPU time 90.56 seconds
Started May 28 01:52:34 PM PDT 24
Finished May 28 01:54:08 PM PDT 24
Peak memory 200524 kb
Host smart-e356f4df-0087-49eb-a28d-43e25b83b123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662798196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.662798196
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2867394948
Short name T965
Test name
Test status
Simulation time 31726795535 ps
CPU time 13.46 seconds
Started May 28 01:52:33 PM PDT 24
Finished May 28 01:52:50 PM PDT 24
Peak memory 200504 kb
Host smart-f5b51b5e-284e-4940-9318-a042af684eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867394948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2867394948
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.100391568
Short name T560
Test name
Test status
Simulation time 56236423876 ps
CPU time 91.84 seconds
Started May 28 01:52:31 PM PDT 24
Finished May 28 01:54:03 PM PDT 24
Peak memory 200468 kb
Host smart-ed6d10e4-b50b-424a-b74e-e7cecdc99a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100391568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.100391568
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.402276804
Short name T668
Test name
Test status
Simulation time 39297179 ps
CPU time 0.58 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:49:19 PM PDT 24
Peak memory 195896 kb
Host smart-cd01065b-9db2-4ed2-94bc-4992607f5e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402276804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.402276804
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3786242331
Short name T659
Test name
Test status
Simulation time 52153500398 ps
CPU time 90.42 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:50:48 PM PDT 24
Peak memory 200480 kb
Host smart-e4ed4fbe-c3bd-4ea9-8121-b45a1904cff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786242331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3786242331
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3325170215
Short name T452
Test name
Test status
Simulation time 26491093690 ps
CPU time 45.37 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:50:03 PM PDT 24
Peak memory 200444 kb
Host smart-1d81ea63-e2da-48ef-b305-a505689f1832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325170215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3325170215
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1734154925
Short name T1094
Test name
Test status
Simulation time 107427188839 ps
CPU time 46.68 seconds
Started May 28 01:49:14 PM PDT 24
Finished May 28 01:50:05 PM PDT 24
Peak memory 200568 kb
Host smart-9a5096f7-e1ab-482c-8ad1-c0b11997101c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734154925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1734154925
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1975617682
Short name T445
Test name
Test status
Simulation time 30249656807 ps
CPU time 30.43 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:49:48 PM PDT 24
Peak memory 200316 kb
Host smart-cede883e-fca6-4ecb-95df-39c91c0c56dc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975617682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1975617682
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3157989683
Short name T648
Test name
Test status
Simulation time 97334724706 ps
CPU time 494.26 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:57:31 PM PDT 24
Peak memory 200492 kb
Host smart-d022d898-8b48-4a30-978f-360adfc656fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157989683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3157989683
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2327213486
Short name T922
Test name
Test status
Simulation time 38203950860 ps
CPU time 32.33 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:49 PM PDT 24
Peak memory 200308 kb
Host smart-4cacb824-7cb0-4325-b0b7-7eb545abb6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327213486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2327213486
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3040495167
Short name T438
Test name
Test status
Simulation time 19674564026 ps
CPU time 183.99 seconds
Started May 28 01:49:15 PM PDT 24
Finished May 28 01:52:24 PM PDT 24
Peak memory 200472 kb
Host smart-c1d83e1a-c761-441b-b7e7-5579648246cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3040495167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3040495167
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2064580486
Short name T694
Test name
Test status
Simulation time 6177599940 ps
CPU time 51.85 seconds
Started May 28 01:49:09 PM PDT 24
Finished May 28 01:50:04 PM PDT 24
Peak memory 198512 kb
Host smart-e53b7ae1-d45e-42cd-8c07-900d79a86168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064580486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2064580486
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3535847701
Short name T269
Test name
Test status
Simulation time 21646522963 ps
CPU time 34.11 seconds
Started May 28 01:49:14 PM PDT 24
Finished May 28 01:49:53 PM PDT 24
Peak memory 200444 kb
Host smart-cc0bb4fc-d155-4a8a-8b9d-493c5be1d919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535847701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3535847701
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1228383037
Short name T795
Test name
Test status
Simulation time 40941815875 ps
CPU time 69.33 seconds
Started May 28 01:49:14 PM PDT 24
Finished May 28 01:50:28 PM PDT 24
Peak memory 196232 kb
Host smart-8959263f-0972-4c2b-9dd9-a145cc16a9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228383037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1228383037
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.455995775
Short name T360
Test name
Test status
Simulation time 307308615 ps
CPU time 1.66 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:49:19 PM PDT 24
Peak memory 198636 kb
Host smart-2f4c97e0-d413-406f-9440-069d4271048b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455995775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.455995775
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1992216796
Short name T552
Test name
Test status
Simulation time 341342415822 ps
CPU time 369.17 seconds
Started May 28 01:49:17 PM PDT 24
Finished May 28 01:55:30 PM PDT 24
Peak memory 200536 kb
Host smart-727f13d2-0b21-4e53-959d-8fff6000950f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992216796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1992216796
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1372015424
Short name T337
Test name
Test status
Simulation time 54773507161 ps
CPU time 572.31 seconds
Started May 28 01:49:17 PM PDT 24
Finished May 28 01:58:53 PM PDT 24
Peak memory 225356 kb
Host smart-37420b21-b33b-4e18-9266-8999bcd74db1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372015424 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1372015424
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.558389192
Short name T982
Test name
Test status
Simulation time 2364338791 ps
CPU time 2.36 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:19 PM PDT 24
Peak memory 199096 kb
Host smart-2aef6227-d90c-47d6-8089-e9d2fdb1d889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558389192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.558389192
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2730119755
Short name T433
Test name
Test status
Simulation time 40204576021 ps
CPU time 16.63 seconds
Started May 28 01:49:14 PM PDT 24
Finished May 28 01:49:36 PM PDT 24
Peak memory 200516 kb
Host smart-90faf34d-f63e-42f6-9aa8-f36ddeb13d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730119755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2730119755
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3499345959
Short name T669
Test name
Test status
Simulation time 39826849346 ps
CPU time 20.51 seconds
Started May 28 01:52:32 PM PDT 24
Finished May 28 01:52:55 PM PDT 24
Peak memory 200548 kb
Host smart-d59de3f5-45b5-43b9-b6b3-cf2bb7b568a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499345959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3499345959
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1344229342
Short name T985
Test name
Test status
Simulation time 63599885496 ps
CPU time 37.21 seconds
Started May 28 01:52:32 PM PDT 24
Finished May 28 01:53:11 PM PDT 24
Peak memory 200540 kb
Host smart-4770377b-1c2e-49b5-8720-adcf589699c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344229342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1344229342
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2878167130
Short name T132
Test name
Test status
Simulation time 37189536246 ps
CPU time 15.94 seconds
Started May 28 01:52:33 PM PDT 24
Finished May 28 01:52:52 PM PDT 24
Peak memory 200548 kb
Host smart-56d89382-01d1-4bc7-8070-ef7766ca8e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878167130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2878167130
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.519159866
Short name T170
Test name
Test status
Simulation time 19318676964 ps
CPU time 31.51 seconds
Started May 28 01:52:32 PM PDT 24
Finished May 28 01:53:06 PM PDT 24
Peak memory 200472 kb
Host smart-8460cc73-928c-44dd-a607-4a26ae4fcca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519159866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.519159866
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.997570671
Short name T941
Test name
Test status
Simulation time 26054341848 ps
CPU time 40.8 seconds
Started May 28 01:52:32 PM PDT 24
Finished May 28 01:53:15 PM PDT 24
Peak memory 200540 kb
Host smart-2c723238-9970-4e26-89e9-7b1af7154cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997570671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.997570671
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1147442610
Short name T546
Test name
Test status
Simulation time 79652205070 ps
CPU time 29.56 seconds
Started May 28 01:52:32 PM PDT 24
Finished May 28 01:53:04 PM PDT 24
Peak memory 200452 kb
Host smart-9614ca79-5636-4a0f-8f21-bc806558ac83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147442610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1147442610
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.947063845
Short name T222
Test name
Test status
Simulation time 118224040924 ps
CPU time 394.05 seconds
Started May 28 01:52:33 PM PDT 24
Finished May 28 01:59:11 PM PDT 24
Peak memory 200752 kb
Host smart-43a633c3-45b8-4083-b777-0d19acf5409e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947063845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.947063845
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1101543548
Short name T182
Test name
Test status
Simulation time 171414662444 ps
CPU time 102.88 seconds
Started May 28 01:52:32 PM PDT 24
Finished May 28 01:54:18 PM PDT 24
Peak memory 200520 kb
Host smart-d84f2282-1d50-4b15-811a-276f2f83f4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101543548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1101543548
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1537133819
Short name T823
Test name
Test status
Simulation time 110486887 ps
CPU time 0.54 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:17 PM PDT 24
Peak memory 195820 kb
Host smart-6c40fd6e-1558-499c-8c59-2ec93e2b957e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537133819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1537133819
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1393516903
Short name T939
Test name
Test status
Simulation time 66685807071 ps
CPU time 52.87 seconds
Started May 28 01:49:16 PM PDT 24
Finished May 28 01:50:13 PM PDT 24
Peak memory 200460 kb
Host smart-e810d153-843d-4745-bde5-49cae606cddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393516903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1393516903
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.175998326
Short name T481
Test name
Test status
Simulation time 26015687622 ps
CPU time 22.25 seconds
Started May 28 01:49:17 PM PDT 24
Finished May 28 01:49:43 PM PDT 24
Peak memory 200064 kb
Host smart-4aaf4e50-aafe-47d5-babd-74c5823e333f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175998326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.175998326
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.3312089235
Short name T378
Test name
Test status
Simulation time 8289758555 ps
CPU time 13.23 seconds
Started May 28 01:49:17 PM PDT 24
Finished May 28 01:49:34 PM PDT 24
Peak memory 199008 kb
Host smart-6a482b13-3f98-4054-9f0c-d4c91c13c357
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312089235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3312089235
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3040059675
Short name T1033
Test name
Test status
Simulation time 61207411416 ps
CPU time 189.19 seconds
Started May 28 01:49:20 PM PDT 24
Finished May 28 01:52:32 PM PDT 24
Peak memory 200548 kb
Host smart-3d349a5b-c790-4280-8f94-9a783d5bb5a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3040059675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3040059675
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.967105703
Short name T585
Test name
Test status
Simulation time 8409716658 ps
CPU time 3.4 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:49:21 PM PDT 24
Peak memory 199160 kb
Host smart-cdfd4d37-724a-42ba-b591-053ba00c8af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967105703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.967105703
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3740202632
Short name T484
Test name
Test status
Simulation time 42748142405 ps
CPU time 85.01 seconds
Started May 28 01:49:17 PM PDT 24
Finished May 28 01:50:45 PM PDT 24
Peak memory 200480 kb
Host smart-d18207a1-8044-4aa5-b4d2-74192a9207e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740202632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3740202632
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1870226006
Short name T467
Test name
Test status
Simulation time 9879025437 ps
CPU time 242.6 seconds
Started May 28 01:49:20 PM PDT 24
Finished May 28 01:53:25 PM PDT 24
Peak memory 200284 kb
Host smart-0455b3d4-d2f3-4840-a8b2-6f6981c09d01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1870226006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1870226006
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.777552287
Short name T878
Test name
Test status
Simulation time 6323329946 ps
CPU time 24.77 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:49:43 PM PDT 24
Peak memory 199688 kb
Host smart-d5ff0136-ae9e-4458-929e-6c2562317a2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=777552287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.777552287
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.499726997
Short name T1085
Test name
Test status
Simulation time 74664932976 ps
CPU time 116.01 seconds
Started May 28 01:49:17 PM PDT 24
Finished May 28 01:51:17 PM PDT 24
Peak memory 199928 kb
Host smart-e022b199-c9b5-4a33-aaf2-0bf7f0fe2cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499726997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.499726997
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1870664087
Short name T741
Test name
Test status
Simulation time 43007376544 ps
CPU time 77.84 seconds
Started May 28 01:49:16 PM PDT 24
Finished May 28 01:50:38 PM PDT 24
Peak memory 196520 kb
Host smart-c6e92334-0471-4e58-8879-ed99b4ececda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870664087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1870664087
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1162804070
Short name T997
Test name
Test status
Simulation time 513696528 ps
CPU time 1.63 seconds
Started May 28 01:49:16 PM PDT 24
Finished May 28 01:49:21 PM PDT 24
Peak memory 199376 kb
Host smart-4d757a58-738f-454b-81b0-18578c33d207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162804070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1162804070
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.2145926994
Short name T268
Test name
Test status
Simulation time 248390091825 ps
CPU time 280.46 seconds
Started May 28 01:49:19 PM PDT 24
Finished May 28 01:54:02 PM PDT 24
Peak memory 200916 kb
Host smart-29219180-c155-46d0-a07e-eb06ba9a3687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145926994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2145926994
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3339488402
Short name T725
Test name
Test status
Simulation time 93392774825 ps
CPU time 1858.99 seconds
Started May 28 01:49:20 PM PDT 24
Finished May 28 02:20:22 PM PDT 24
Peak memory 226688 kb
Host smart-59b495de-2eaa-4943-aca5-c405a3e84c6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339488402 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3339488402
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3633060976
Short name T1144
Test name
Test status
Simulation time 907658545 ps
CPU time 2.3 seconds
Started May 28 01:49:20 PM PDT 24
Finished May 28 01:49:25 PM PDT 24
Peak memory 200312 kb
Host smart-c9c918df-b639-4e16-9001-7ebd2959c9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633060976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3633060976
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1931744100
Short name T276
Test name
Test status
Simulation time 94524711894 ps
CPU time 159.97 seconds
Started May 28 01:49:10 PM PDT 24
Finished May 28 01:51:54 PM PDT 24
Peak memory 200472 kb
Host smart-434c4a5f-fa4d-4b82-b34f-3c0a7ad5665a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931744100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1931744100
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3349418237
Short name T402
Test name
Test status
Simulation time 124681285396 ps
CPU time 102.96 seconds
Started May 28 01:52:34 PM PDT 24
Finished May 28 01:54:20 PM PDT 24
Peak memory 200500 kb
Host smart-e0646bdd-a510-4fc7-a2bf-467da0ce3043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349418237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3349418237
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1436695516
Short name T528
Test name
Test status
Simulation time 97167176253 ps
CPU time 38.99 seconds
Started May 28 01:52:34 PM PDT 24
Finished May 28 01:53:16 PM PDT 24
Peak memory 200480 kb
Host smart-432db438-d5e4-4b9f-92d0-5f75d91e7a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436695516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1436695516
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3243608524
Short name T632
Test name
Test status
Simulation time 74358438575 ps
CPU time 30.46 seconds
Started May 28 01:52:34 PM PDT 24
Finished May 28 01:53:09 PM PDT 24
Peak memory 200456 kb
Host smart-cde41761-48f3-4fb1-8615-c00617f95d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243608524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3243608524
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2049457478
Short name T633
Test name
Test status
Simulation time 102055500892 ps
CPU time 569.22 seconds
Started May 28 01:52:31 PM PDT 24
Finished May 28 02:02:02 PM PDT 24
Peak memory 200556 kb
Host smart-4ccb8968-66a9-4d67-96ce-083b181f312f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049457478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2049457478
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.837246183
Short name T575
Test name
Test status
Simulation time 76619609845 ps
CPU time 110.75 seconds
Started May 28 01:52:32 PM PDT 24
Finished May 28 01:54:26 PM PDT 24
Peak memory 200548 kb
Host smart-8361cf1b-9572-482f-9ca5-e934e59bd213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837246183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.837246183
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.4202207236
Short name T661
Test name
Test status
Simulation time 31643643828 ps
CPU time 15.14 seconds
Started May 28 01:52:32 PM PDT 24
Finished May 28 01:52:48 PM PDT 24
Peak memory 200536 kb
Host smart-542a8a13-fffb-44a1-8229-a186b94a4538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202207236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.4202207236
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2689029733
Short name T1051
Test name
Test status
Simulation time 233120153263 ps
CPU time 85.53 seconds
Started May 28 01:52:36 PM PDT 24
Finished May 28 01:54:06 PM PDT 24
Peak memory 200536 kb
Host smart-d20369f2-bd1f-4e1d-b928-423d5b274598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689029733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2689029733
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3133253010
Short name T753
Test name
Test status
Simulation time 77199187538 ps
CPU time 11.52 seconds
Started May 28 01:52:34 PM PDT 24
Finished May 28 01:52:50 PM PDT 24
Peak memory 199356 kb
Host smart-c6adacf5-4ef6-4e3b-887f-b01c2eabd843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133253010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3133253010
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1142357057
Short name T173
Test name
Test status
Simulation time 169974252082 ps
CPU time 53.62 seconds
Started May 28 01:52:32 PM PDT 24
Finished May 28 01:53:27 PM PDT 24
Peak memory 200468 kb
Host smart-3d13aef8-24f9-46bc-b9d4-425e36c7de68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142357057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1142357057
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2541950691
Short name T547
Test name
Test status
Simulation time 49592209 ps
CPU time 0.58 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:49:17 PM PDT 24
Peak memory 195904 kb
Host smart-2deecad6-0a5c-41cf-be6f-00907ca901c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541950691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2541950691
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2597494721
Short name T815
Test name
Test status
Simulation time 27482583850 ps
CPU time 43.92 seconds
Started May 28 01:49:14 PM PDT 24
Finished May 28 01:50:03 PM PDT 24
Peak memory 200556 kb
Host smart-5e082e82-ee8c-4c92-862b-9742b6f06492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597494721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2597494721
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2781832147
Short name T14
Test name
Test status
Simulation time 108735612745 ps
CPU time 160.7 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:51:57 PM PDT 24
Peak memory 200512 kb
Host smart-aaaac8dd-4edc-44f7-85e4-8db3f839001e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781832147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2781832147
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.803132171
Short name T645
Test name
Test status
Simulation time 49811070409 ps
CPU time 20.68 seconds
Started May 28 01:49:20 PM PDT 24
Finished May 28 01:49:43 PM PDT 24
Peak memory 199796 kb
Host smart-169edd30-4b0d-45f7-8575-0371934b4733
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803132171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.803132171
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3492760260
Short name T1182
Test name
Test status
Simulation time 119211030381 ps
CPU time 340.69 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:54:58 PM PDT 24
Peak memory 200472 kb
Host smart-08a44a7e-3d46-4d3c-9790-d34712146458
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3492760260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3492760260
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1824031288
Short name T1160
Test name
Test status
Simulation time 8810911619 ps
CPU time 11.39 seconds
Started May 28 01:49:14 PM PDT 24
Finished May 28 01:49:30 PM PDT 24
Peak memory 200528 kb
Host smart-d8708611-d2e4-4c11-968e-a80cb3987027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824031288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1824031288
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.10980653
Short name T1175
Test name
Test status
Simulation time 26309279663 ps
CPU time 285.38 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:54:03 PM PDT 24
Peak memory 200528 kb
Host smart-260ea188-d88e-4b79-bfb4-11446bd8ad25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10980653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.10980653
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.260959523
Short name T384
Test name
Test status
Simulation time 5860248943 ps
CPU time 53.3 seconds
Started May 28 01:49:20 PM PDT 24
Finished May 28 01:50:16 PM PDT 24
Peak memory 199588 kb
Host smart-35fff3ca-a965-4b95-a2fa-05e0e793af71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=260959523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.260959523
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2594987658
Short name T26
Test name
Test status
Simulation time 18763250081 ps
CPU time 34.84 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:49:53 PM PDT 24
Peak memory 200536 kb
Host smart-9d04a8d0-7420-42bd-a4fa-838ff8813c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594987658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2594987658
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3685500482
Short name T608
Test name
Test status
Simulation time 22060255191 ps
CPU time 17.02 seconds
Started May 28 01:49:20 PM PDT 24
Finished May 28 01:49:39 PM PDT 24
Peak memory 196392 kb
Host smart-0fcb683c-c913-4ef4-93c0-be4ac865f38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685500482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3685500482
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3298112435
Short name T447
Test name
Test status
Simulation time 694420478 ps
CPU time 2.66 seconds
Started May 28 01:49:20 PM PDT 24
Finished May 28 01:49:25 PM PDT 24
Peak memory 199936 kb
Host smart-70650a22-bfd2-4571-8ef3-6acbf4117e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298112435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3298112435
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2276329516
Short name T731
Test name
Test status
Simulation time 199014888869 ps
CPU time 53.5 seconds
Started May 28 01:49:14 PM PDT 24
Finished May 28 01:50:12 PM PDT 24
Peak memory 200480 kb
Host smart-c529bc87-be7f-4173-8a0a-c50410394072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276329516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2276329516
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3791331708
Short name T532
Test name
Test status
Simulation time 25765689437 ps
CPU time 446.16 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:56:43 PM PDT 24
Peak memory 216688 kb
Host smart-e3f227df-72e5-4d55-9229-825fff24d580
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791331708 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3791331708
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.4149429672
Short name T930
Test name
Test status
Simulation time 967646928 ps
CPU time 2.03 seconds
Started May 28 01:49:21 PM PDT 24
Finished May 28 01:49:25 PM PDT 24
Peak memory 198748 kb
Host smart-074d6f90-4ac1-4436-8e18-8179f197b2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149429672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.4149429672
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3880241759
Short name T1021
Test name
Test status
Simulation time 45131727499 ps
CPU time 86.7 seconds
Started May 28 01:49:19 PM PDT 24
Finished May 28 01:50:49 PM PDT 24
Peak memory 200544 kb
Host smart-1627e532-772e-43ea-a402-1577ae968aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880241759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3880241759
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1785571953
Short name T216
Test name
Test status
Simulation time 170146851079 ps
CPU time 77.86 seconds
Started May 28 01:52:34 PM PDT 24
Finished May 28 01:53:56 PM PDT 24
Peak memory 200464 kb
Host smart-60ddc8f6-0e2c-43c5-b6d1-5b4a9bed997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785571953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1785571953
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2204120253
Short name T451
Test name
Test status
Simulation time 10206138913 ps
CPU time 18.84 seconds
Started May 28 01:52:31 PM PDT 24
Finished May 28 01:52:51 PM PDT 24
Peak memory 200404 kb
Host smart-d24c16f2-ac44-451b-b336-1dc1f754728d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204120253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2204120253
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2222295948
Short name T147
Test name
Test status
Simulation time 58665171129 ps
CPU time 64.6 seconds
Started May 28 01:52:31 PM PDT 24
Finished May 28 01:53:37 PM PDT 24
Peak memory 200408 kb
Host smart-47282404-a72b-48d8-84c2-97c5e9f7f236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222295948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2222295948
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3876812717
Short name T810
Test name
Test status
Simulation time 7383067641 ps
CPU time 14.88 seconds
Started May 28 01:52:36 PM PDT 24
Finished May 28 01:52:56 PM PDT 24
Peak memory 200488 kb
Host smart-41182a2f-a6ec-40a9-8c1d-d58079f26df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876812717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3876812717
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.4025829964
Short name T846
Test name
Test status
Simulation time 76248940209 ps
CPU time 413.74 seconds
Started May 28 01:52:36 PM PDT 24
Finished May 28 01:59:34 PM PDT 24
Peak memory 200508 kb
Host smart-2ba58cfb-ce2c-4d68-9e4a-201dd0c52d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025829964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4025829964
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1038392414
Short name T890
Test name
Test status
Simulation time 7560023432 ps
CPU time 25.88 seconds
Started May 28 01:52:32 PM PDT 24
Finished May 28 01:52:59 PM PDT 24
Peak memory 200548 kb
Host smart-6ccc5a9d-f6b8-47c3-b447-0f57ec2a4e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038392414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1038392414
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3406193070
Short name T197
Test name
Test status
Simulation time 90067234425 ps
CPU time 35.15 seconds
Started May 28 01:52:34 PM PDT 24
Finished May 28 01:53:14 PM PDT 24
Peak memory 200572 kb
Host smart-97c45663-3963-49bf-ae3f-5e20cda7a4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406193070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3406193070
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2418044567
Short name T1040
Test name
Test status
Simulation time 16677077762 ps
CPU time 20.18 seconds
Started May 28 01:52:34 PM PDT 24
Finished May 28 01:52:59 PM PDT 24
Peak memory 200536 kb
Host smart-ac281329-5ed9-4b4e-aca0-9655738248e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418044567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2418044567
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.230617116
Short name T805
Test name
Test status
Simulation time 63385094541 ps
CPU time 200.13 seconds
Started May 28 01:52:30 PM PDT 24
Finished May 28 01:55:51 PM PDT 24
Peak memory 200536 kb
Host smart-d526c224-8140-460c-a370-d6b4f6258a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230617116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.230617116
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3941177797
Short name T397
Test name
Test status
Simulation time 23601108 ps
CPU time 0.55 seconds
Started May 28 01:49:15 PM PDT 24
Finished May 28 01:49:20 PM PDT 24
Peak memory 195900 kb
Host smart-b7c3b5bd-a832-4f63-953a-e7fd3609121d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941177797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3941177797
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.297597329
Short name T1017
Test name
Test status
Simulation time 74980897856 ps
CPU time 69.64 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:50:27 PM PDT 24
Peak memory 200148 kb
Host smart-b13ec5bc-f656-4159-b3da-fad79c92abf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297597329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.297597329
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3293418861
Short name T636
Test name
Test status
Simulation time 36367902962 ps
CPU time 27.73 seconds
Started May 28 01:49:14 PM PDT 24
Finished May 28 01:49:46 PM PDT 24
Peak memory 200484 kb
Host smart-5888a497-339e-4b38-a562-19ca2a06ebfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293418861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3293418861
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3262328097
Short name T959
Test name
Test status
Simulation time 39453348875 ps
CPU time 22.89 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:39 PM PDT 24
Peak memory 200456 kb
Host smart-de4275d8-7516-4419-9817-922a35e9ea42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262328097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3262328097
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3616918459
Short name T118
Test name
Test status
Simulation time 35810205860 ps
CPU time 19.17 seconds
Started May 28 01:49:16 PM PDT 24
Finished May 28 01:49:39 PM PDT 24
Peak memory 200448 kb
Host smart-9df74a88-16f7-4934-8642-41b332ae6393
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616918459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3616918459
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.4139255343
Short name T1091
Test name
Test status
Simulation time 127323987874 ps
CPU time 837.58 seconds
Started May 28 01:49:17 PM PDT 24
Finished May 28 02:03:18 PM PDT 24
Peak memory 200468 kb
Host smart-0beaaaf4-5e42-4070-86ee-d8de9bac4e12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139255343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.4139255343
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3841193047
Short name T483
Test name
Test status
Simulation time 923414988 ps
CPU time 1.7 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:17 PM PDT 24
Peak memory 196592 kb
Host smart-86ae2fda-a265-4bc5-b1f9-5b512de42136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841193047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3841193047
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3586725834
Short name T915
Test name
Test status
Simulation time 34204428373 ps
CPU time 29.02 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:44 PM PDT 24
Peak memory 200848 kb
Host smart-03b8a806-0862-4a7c-b082-8770677a045d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586725834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3586725834
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.4056111023
Short name T538
Test name
Test status
Simulation time 22992119945 ps
CPU time 340.11 seconds
Started May 28 01:49:16 PM PDT 24
Finished May 28 01:55:00 PM PDT 24
Peak memory 200560 kb
Host smart-8911de6b-4d70-4c4a-89c6-96b314012fc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056111023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.4056111023
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3144360270
Short name T681
Test name
Test status
Simulation time 3071478847 ps
CPU time 12.12 seconds
Started May 28 01:49:14 PM PDT 24
Finished May 28 01:49:31 PM PDT 24
Peak memory 199776 kb
Host smart-b0117958-f617-415d-8d55-7dc5080884f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3144360270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3144360270
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3644812173
Short name T288
Test name
Test status
Simulation time 241955400657 ps
CPU time 165.38 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:52:03 PM PDT 24
Peak memory 200056 kb
Host smart-3abf8b54-7c8b-4deb-97bf-0c1579227018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644812173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3644812173
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1780934777
Short name T432
Test name
Test status
Simulation time 3634724016 ps
CPU time 1.17 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:49:18 PM PDT 24
Peak memory 196376 kb
Host smart-91c5c63b-12c4-491c-92f6-5547299ebc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780934777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1780934777
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3427049150
Short name T1139
Test name
Test status
Simulation time 947817018 ps
CPU time 2.32 seconds
Started May 28 01:49:16 PM PDT 24
Finished May 28 01:49:22 PM PDT 24
Peak memory 199184 kb
Host smart-96d6b0c9-b6e3-487c-b024-ebbcaf099ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427049150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3427049150
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3624657284
Short name T993
Test name
Test status
Simulation time 95552960584 ps
CPU time 326.7 seconds
Started May 28 01:49:14 PM PDT 24
Finished May 28 01:54:45 PM PDT 24
Peak memory 216212 kb
Host smart-6cbf67b8-4541-40a8-9b8f-3da33415e989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624657284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3624657284
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.4280996954
Short name T1168
Test name
Test status
Simulation time 1683735276 ps
CPU time 3.16 seconds
Started May 28 01:49:10 PM PDT 24
Finished May 28 01:49:18 PM PDT 24
Peak memory 199216 kb
Host smart-11a99fa0-7f99-4dcc-9d02-fba157922fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280996954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4280996954
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1244822923
Short name T319
Test name
Test status
Simulation time 66847331126 ps
CPU time 10.11 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:49:28 PM PDT 24
Peak memory 200508 kb
Host smart-c950692a-03f7-436e-9351-d63e73180020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244822923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1244822923
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2570306425
Short name T168
Test name
Test status
Simulation time 32483871284 ps
CPU time 29.46 seconds
Started May 28 01:52:33 PM PDT 24
Finished May 28 01:53:05 PM PDT 24
Peak memory 200468 kb
Host smart-a14502da-79af-43f3-95bf-62d1b2bda73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570306425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2570306425
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2013615159
Short name T972
Test name
Test status
Simulation time 44671182487 ps
CPU time 95.05 seconds
Started May 28 01:52:35 PM PDT 24
Finished May 28 01:54:15 PM PDT 24
Peak memory 200460 kb
Host smart-deb57055-240d-4abd-8c4e-a40aa4e39f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013615159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2013615159
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1739931643
Short name T900
Test name
Test status
Simulation time 78847078303 ps
CPU time 114.3 seconds
Started May 28 01:52:35 PM PDT 24
Finished May 28 01:54:33 PM PDT 24
Peak memory 200488 kb
Host smart-1c981745-a75f-4b85-9dbf-e82a50cf336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739931643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1739931643
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2724351604
Short name T156
Test name
Test status
Simulation time 62971070110 ps
CPU time 25.09 seconds
Started May 28 01:52:35 PM PDT 24
Finished May 28 01:53:05 PM PDT 24
Peak memory 200576 kb
Host smart-a1ca4a60-b4c2-47cf-a8e1-4f89ed76021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724351604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2724351604
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3671610633
Short name T291
Test name
Test status
Simulation time 157551594236 ps
CPU time 46.55 seconds
Started May 28 01:52:35 PM PDT 24
Finished May 28 01:53:26 PM PDT 24
Peak memory 200544 kb
Host smart-9c54347d-4841-4f58-9fe6-47743ec25b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671610633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3671610633
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1665287157
Short name T54
Test name
Test status
Simulation time 177294759615 ps
CPU time 83.23 seconds
Started May 28 01:52:35 PM PDT 24
Finished May 28 01:54:03 PM PDT 24
Peak memory 200528 kb
Host smart-7e9070b1-67dd-43ce-8418-0f224abd8215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665287157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1665287157
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.383270863
Short name T541
Test name
Test status
Simulation time 52764464755 ps
CPU time 63.27 seconds
Started May 28 01:52:36 PM PDT 24
Finished May 28 01:53:44 PM PDT 24
Peak memory 200560 kb
Host smart-5c1748d3-3489-4968-8e99-8244fb3e3a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383270863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.383270863
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3943501858
Short name T426
Test name
Test status
Simulation time 83759319624 ps
CPU time 196.64 seconds
Started May 28 01:52:35 PM PDT 24
Finished May 28 01:55:56 PM PDT 24
Peak memory 200476 kb
Host smart-43f5bf7b-8da0-4475-9b80-7bcf625b722c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943501858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3943501858
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2350430776
Short name T1016
Test name
Test status
Simulation time 22899840 ps
CPU time 0.55 seconds
Started May 28 01:49:23 PM PDT 24
Finished May 28 01:49:26 PM PDT 24
Peak memory 195908 kb
Host smart-e0f6e18f-0898-47a3-bbf5-9bba598671a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350430776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2350430776
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.707364360
Short name T1149
Test name
Test status
Simulation time 123503735684 ps
CPU time 100.5 seconds
Started May 28 01:49:22 PM PDT 24
Finished May 28 01:51:05 PM PDT 24
Peak memory 200480 kb
Host smart-2af43baf-5917-495f-827f-a38a5a886ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707364360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.707364360
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1073609535
Short name T186
Test name
Test status
Simulation time 30481535165 ps
CPU time 14.62 seconds
Started May 28 01:49:24 PM PDT 24
Finished May 28 01:49:41 PM PDT 24
Peak memory 200424 kb
Host smart-6efba7ab-5002-4b50-81a8-de7c010f157e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073609535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1073609535
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1992882101
Short name T229
Test name
Test status
Simulation time 29594853257 ps
CPU time 58.24 seconds
Started May 28 01:49:24 PM PDT 24
Finished May 28 01:50:24 PM PDT 24
Peak memory 200428 kb
Host smart-a2a4a4f0-0199-4820-a396-049f9b010ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992882101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1992882101
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2162098637
Short name T1036
Test name
Test status
Simulation time 19029671846 ps
CPU time 34.58 seconds
Started May 28 01:49:28 PM PDT 24
Finished May 28 01:50:07 PM PDT 24
Peak memory 199524 kb
Host smart-f27cd838-c47a-40c4-a23f-9d623e551525
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162098637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2162098637
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2250149100
Short name T468
Test name
Test status
Simulation time 130979143339 ps
CPU time 228.89 seconds
Started May 28 01:49:31 PM PDT 24
Finished May 28 01:53:22 PM PDT 24
Peak memory 200344 kb
Host smart-e9993c68-7239-4590-a6c6-50298e4b37e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2250149100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2250149100
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.523968879
Short name T1025
Test name
Test status
Simulation time 4218854133 ps
CPU time 9.5 seconds
Started May 28 01:49:23 PM PDT 24
Finished May 28 01:49:35 PM PDT 24
Peak memory 199252 kb
Host smart-3a6f85e3-1f4d-48ce-bf49-a64f1490ddaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523968879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.523968879
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.735350205
Short name T503
Test name
Test status
Simulation time 40902664434 ps
CPU time 17.54 seconds
Started May 28 01:49:26 PM PDT 24
Finished May 28 01:49:47 PM PDT 24
Peak memory 197584 kb
Host smart-7cf69c26-79d6-4fa5-9da0-5a01ad83943c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735350205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.735350205
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2689074786
Short name T1002
Test name
Test status
Simulation time 13088069624 ps
CPU time 633.99 seconds
Started May 28 01:49:27 PM PDT 24
Finished May 28 02:00:05 PM PDT 24
Peak memory 200536 kb
Host smart-f13f5c4e-10df-438a-b3d5-b543449e7fa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2689074786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2689074786
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3652999690
Short name T884
Test name
Test status
Simulation time 3916971934 ps
CPU time 8.16 seconds
Started May 28 01:49:26 PM PDT 24
Finished May 28 01:49:39 PM PDT 24
Peak memory 198676 kb
Host smart-7a50ca4b-a38c-4160-a080-2e41db778dc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652999690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3652999690
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3716313538
Short name T53
Test name
Test status
Simulation time 132724940439 ps
CPU time 64.09 seconds
Started May 28 01:49:24 PM PDT 24
Finished May 28 01:50:32 PM PDT 24
Peak memory 200468 kb
Host smart-6e87bf37-b1ed-423d-b85f-2910d5bc6683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716313538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3716313538
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.355770460
Short name T812
Test name
Test status
Simulation time 5366440032 ps
CPU time 9.72 seconds
Started May 28 01:49:24 PM PDT 24
Finished May 28 01:49:37 PM PDT 24
Peak memory 196784 kb
Host smart-da99fc21-84a7-48da-90a1-a2170ac5ed19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355770460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.355770460
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2593739035
Short name T366
Test name
Test status
Simulation time 483185132 ps
CPU time 1.84 seconds
Started May 28 01:49:14 PM PDT 24
Finished May 28 01:49:20 PM PDT 24
Peak memory 199364 kb
Host smart-e5f183c0-03f0-424a-b674-dc0b07a2c7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593739035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2593739035
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.571945986
Short name T765
Test name
Test status
Simulation time 490334116016 ps
CPU time 246.67 seconds
Started May 28 01:49:27 PM PDT 24
Finished May 28 01:53:37 PM PDT 24
Peak memory 208932 kb
Host smart-637335da-00cd-40ee-83fc-33486398da8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571945986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.571945986
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3449775231
Short name T63
Test name
Test status
Simulation time 162584004056 ps
CPU time 1116.98 seconds
Started May 28 01:49:23 PM PDT 24
Finished May 28 02:08:03 PM PDT 24
Peak memory 225132 kb
Host smart-7070ef53-575c-4a81-80da-83fa7f27701c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449775231 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3449775231
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2233022135
Short name T10
Test name
Test status
Simulation time 1072661519 ps
CPU time 4.75 seconds
Started May 28 01:49:28 PM PDT 24
Finished May 28 01:49:37 PM PDT 24
Peak memory 198788 kb
Host smart-b297db82-7645-4671-97c3-feb1f8f10dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233022135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2233022135
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2813432693
Short name T359
Test name
Test status
Simulation time 10675981906 ps
CPU time 18.41 seconds
Started May 28 01:49:20 PM PDT 24
Finished May 28 01:49:41 PM PDT 24
Peak memory 200256 kb
Host smart-35678f8b-fe0f-42b9-ba7c-2ff8b76690a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813432693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2813432693
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2814089591
Short name T888
Test name
Test status
Simulation time 134084307323 ps
CPU time 90.64 seconds
Started May 28 01:52:34 PM PDT 24
Finished May 28 01:54:09 PM PDT 24
Peak memory 200196 kb
Host smart-0bd4a2c1-47a8-4e00-ba66-9df1e2e4cea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814089591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2814089591
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2085206003
Short name T574
Test name
Test status
Simulation time 105694759465 ps
CPU time 46.03 seconds
Started May 28 01:52:37 PM PDT 24
Finished May 28 01:53:27 PM PDT 24
Peak memory 200544 kb
Host smart-7e21a049-1b46-48c7-90c4-0fd3f348ab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085206003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2085206003
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.4294617677
Short name T1118
Test name
Test status
Simulation time 129270411964 ps
CPU time 139.02 seconds
Started May 28 01:52:34 PM PDT 24
Finished May 28 01:54:57 PM PDT 24
Peak memory 200568 kb
Host smart-c7c257bf-7be5-421d-af86-93c25a33926b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294617677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.4294617677
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2342646398
Short name T494
Test name
Test status
Simulation time 67153005389 ps
CPU time 63.62 seconds
Started May 28 01:52:34 PM PDT 24
Finished May 28 01:53:42 PM PDT 24
Peak memory 200500 kb
Host smart-8a6c6e83-ad06-4f06-97d7-91850a1635ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342646398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2342646398
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2706085392
Short name T193
Test name
Test status
Simulation time 80646541662 ps
CPU time 217.9 seconds
Started May 28 01:52:36 PM PDT 24
Finished May 28 01:56:18 PM PDT 24
Peak memory 200516 kb
Host smart-50d46c6a-a523-4c38-b195-136a76019e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706085392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2706085392
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1962485677
Short name T1121
Test name
Test status
Simulation time 74030007386 ps
CPU time 31.32 seconds
Started May 28 01:52:50 PM PDT 24
Finished May 28 01:53:24 PM PDT 24
Peak memory 200464 kb
Host smart-a809cef3-21b6-42b9-ba3e-0f779fbfcf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962485677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1962485677
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.4047917548
Short name T1122
Test name
Test status
Simulation time 19410542579 ps
CPU time 42.82 seconds
Started May 28 01:52:49 PM PDT 24
Finished May 28 01:53:35 PM PDT 24
Peak memory 200544 kb
Host smart-58b50816-4669-4073-9c3b-6f9333db5aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047917548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.4047917548
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1298197704
Short name T724
Test name
Test status
Simulation time 47421137682 ps
CPU time 46.81 seconds
Started May 28 01:52:48 PM PDT 24
Finished May 28 01:53:36 PM PDT 24
Peak memory 200624 kb
Host smart-f23ef77a-fba5-4d7d-863d-5d4171c253f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298197704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1298197704
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3208605290
Short name T488
Test name
Test status
Simulation time 47911692 ps
CPU time 0.63 seconds
Started May 28 01:49:28 PM PDT 24
Finished May 28 01:49:33 PM PDT 24
Peak memory 195908 kb
Host smart-6b64a43a-aa3d-4a6e-a7a2-7a9fda6358a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208605290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3208605290
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.701355570
Short name T1028
Test name
Test status
Simulation time 142749075909 ps
CPU time 457.5 seconds
Started May 28 01:49:27 PM PDT 24
Finished May 28 01:57:09 PM PDT 24
Peak memory 200432 kb
Host smart-aad35072-8407-4d7f-bf28-1332e1f2200d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701355570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.701355570
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.4083718580
Short name T1098
Test name
Test status
Simulation time 51174577297 ps
CPU time 87.6 seconds
Started May 28 01:49:27 PM PDT 24
Finished May 28 01:50:59 PM PDT 24
Peak memory 200524 kb
Host smart-1d645274-7a4a-425d-bc59-e060aa104782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083718580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.4083718580
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2758725164
Short name T1159
Test name
Test status
Simulation time 5969900429 ps
CPU time 10.93 seconds
Started May 28 01:49:23 PM PDT 24
Finished May 28 01:49:37 PM PDT 24
Peak memory 200352 kb
Host smart-087fb4c0-684d-4c71-894d-c48d135b6ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758725164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2758725164
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1944516616
Short name T1154
Test name
Test status
Simulation time 54431293243 ps
CPU time 26.35 seconds
Started May 28 01:49:25 PM PDT 24
Finished May 28 01:49:55 PM PDT 24
Peak memory 200540 kb
Host smart-c4e43a79-2818-42bd-9983-0b3dc98c655f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944516616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1944516616
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3304931547
Short name T931
Test name
Test status
Simulation time 93959098644 ps
CPU time 506.86 seconds
Started May 28 01:49:22 PM PDT 24
Finished May 28 01:57:52 PM PDT 24
Peak memory 200544 kb
Host smart-b5dc2e01-9432-482f-8809-373deff687bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3304931547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3304931547
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2969891768
Short name T365
Test name
Test status
Simulation time 7778778743 ps
CPU time 5.47 seconds
Started May 28 01:49:22 PM PDT 24
Finished May 28 01:49:30 PM PDT 24
Peak memory 199324 kb
Host smart-6bcf6cb7-2ac3-427d-9aae-21d622cd41fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969891768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2969891768
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3533647112
Short name T562
Test name
Test status
Simulation time 57879036686 ps
CPU time 67.21 seconds
Started May 28 01:49:26 PM PDT 24
Finished May 28 01:50:36 PM PDT 24
Peak memory 200776 kb
Host smart-50d880b0-7ff3-41d4-a017-9f4507ef7072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533647112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3533647112
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.693579273
Short name T665
Test name
Test status
Simulation time 3593238144 ps
CPU time 26.22 seconds
Started May 28 01:49:24 PM PDT 24
Finished May 28 01:49:53 PM PDT 24
Peak memory 198640 kb
Host smart-b22dc4ce-b904-407c-8a0c-5e0ed8536897
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=693579273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.693579273
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2826549440
Short name T164
Test name
Test status
Simulation time 127626757912 ps
CPU time 224.93 seconds
Started May 28 01:49:28 PM PDT 24
Finished May 28 01:53:17 PM PDT 24
Peak memory 200528 kb
Host smart-a737f02e-60cc-4dd5-a865-3b3aa242f258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826549440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2826549440
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1981816352
Short name T300
Test name
Test status
Simulation time 2872119213 ps
CPU time 1.96 seconds
Started May 28 01:49:29 PM PDT 24
Finished May 28 01:49:34 PM PDT 24
Peak memory 195988 kb
Host smart-92983da9-6031-473f-9ec5-75be3c9128e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981816352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1981816352
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.4247626594
Short name T515
Test name
Test status
Simulation time 111606413 ps
CPU time 0.81 seconds
Started May 28 01:49:26 PM PDT 24
Finished May 28 01:49:30 PM PDT 24
Peak memory 197532 kb
Host smart-331c721b-5796-4776-9dfa-570457ab5a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247626594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.4247626594
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.806412175
Short name T881
Test name
Test status
Simulation time 614980682034 ps
CPU time 179.13 seconds
Started May 28 01:49:22 PM PDT 24
Finished May 28 01:52:24 PM PDT 24
Peak memory 200552 kb
Host smart-a12e109e-5b8c-4e77-a409-2d4aea199947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806412175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.806412175
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3181982816
Short name T969
Test name
Test status
Simulation time 140492015993 ps
CPU time 672.12 seconds
Started May 28 01:49:28 PM PDT 24
Finished May 28 02:00:44 PM PDT 24
Peak memory 216996 kb
Host smart-9ca20efa-dc7a-46b7-a9d3-df11f42cfb22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181982816 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3181982816
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1212958154
Short name T838
Test name
Test status
Simulation time 1003002144 ps
CPU time 2.78 seconds
Started May 28 01:49:27 PM PDT 24
Finished May 28 01:49:34 PM PDT 24
Peak memory 200404 kb
Host smart-2cd2815e-ab53-4d9d-a0d7-d7d234c28211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212958154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1212958154
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3733582662
Short name T782
Test name
Test status
Simulation time 59624006053 ps
CPU time 26.36 seconds
Started May 28 01:49:21 PM PDT 24
Finished May 28 01:49:50 PM PDT 24
Peak memory 200540 kb
Host smart-d23b8b7e-8c23-4a4e-b417-71243a05b52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733582662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3733582662
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1012314576
Short name T495
Test name
Test status
Simulation time 38002012114 ps
CPU time 16.3 seconds
Started May 28 01:52:47 PM PDT 24
Finished May 28 01:53:05 PM PDT 24
Peak memory 199604 kb
Host smart-acf7e256-2c24-4064-abf9-bfc5fab46153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012314576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1012314576
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.434581947
Short name T933
Test name
Test status
Simulation time 193599307330 ps
CPU time 312.05 seconds
Started May 28 01:52:48 PM PDT 24
Finished May 28 01:58:03 PM PDT 24
Peak memory 200564 kb
Host smart-8ee4b2bd-48ce-4240-b5f8-d19a967d7213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434581947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.434581947
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.580511037
Short name T1090
Test name
Test status
Simulation time 50794375037 ps
CPU time 24.5 seconds
Started May 28 01:52:49 PM PDT 24
Finished May 28 01:53:17 PM PDT 24
Peak memory 200484 kb
Host smart-bd8e8337-9ef5-49f6-a05c-6a7f2ae82d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580511037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.580511037
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.809323109
Short name T204
Test name
Test status
Simulation time 14969585869 ps
CPU time 24.2 seconds
Started May 28 01:52:54 PM PDT 24
Finished May 28 01:53:20 PM PDT 24
Peak memory 200556 kb
Host smart-02b2ba50-7ec6-4327-8a8b-fdccda1ee600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809323109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.809323109
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3519385231
Short name T230
Test name
Test status
Simulation time 98270451604 ps
CPU time 267.38 seconds
Started May 28 01:52:51 PM PDT 24
Finished May 28 01:57:21 PM PDT 24
Peak memory 200576 kb
Host smart-2ded2ee2-e550-4f43-bbdc-19554ba4582e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519385231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3519385231
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2537445400
Short name T1103
Test name
Test status
Simulation time 185417941637 ps
CPU time 272.84 seconds
Started May 28 01:52:45 PM PDT 24
Finished May 28 01:57:19 PM PDT 24
Peak memory 200548 kb
Host smart-e619cb8b-cff7-4fae-8d6c-7ca4cbd41f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537445400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2537445400
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2827871925
Short name T1108
Test name
Test status
Simulation time 72631259885 ps
CPU time 119.32 seconds
Started May 28 01:52:59 PM PDT 24
Finished May 28 01:55:01 PM PDT 24
Peak memory 200520 kb
Host smart-b5ac8409-51cc-45eb-b455-e94f29404f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827871925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2827871925
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.612909185
Short name T345
Test name
Test status
Simulation time 5764591538 ps
CPU time 16.61 seconds
Started May 28 01:52:51 PM PDT 24
Finished May 28 01:53:10 PM PDT 24
Peak memory 200524 kb
Host smart-4c0e4f24-6291-42b8-9554-1a02d2bef26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612909185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.612909185
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3927337408
Short name T136
Test name
Test status
Simulation time 62445536846 ps
CPU time 100.53 seconds
Started May 28 01:49:22 PM PDT 24
Finished May 28 01:51:06 PM PDT 24
Peak memory 200712 kb
Host smart-21d67e93-2f88-4016-b8a3-ec3905a23f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927337408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3927337408
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3936446454
Short name T643
Test name
Test status
Simulation time 22602257765 ps
CPU time 17.75 seconds
Started May 28 01:49:24 PM PDT 24
Finished May 28 01:49:44 PM PDT 24
Peak memory 199956 kb
Host smart-65fa64d7-0293-465a-b470-3c06491ffcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936446454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3936446454
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1459748934
Short name T153
Test name
Test status
Simulation time 260992324249 ps
CPU time 101.96 seconds
Started May 28 01:49:26 PM PDT 24
Finished May 28 01:51:12 PM PDT 24
Peak memory 200532 kb
Host smart-d32a6adc-ba0f-40d4-81e1-ada2f97a2dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459748934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1459748934
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1543926959
Short name T400
Test name
Test status
Simulation time 15366815895 ps
CPU time 12.38 seconds
Started May 28 01:49:27 PM PDT 24
Finished May 28 01:49:44 PM PDT 24
Peak memory 198048 kb
Host smart-10256479-8c41-4ed3-b276-15f5bdeaa552
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543926959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1543926959
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3455486599
Short name T840
Test name
Test status
Simulation time 137483731771 ps
CPU time 1340.98 seconds
Started May 28 01:49:27 PM PDT 24
Finished May 28 02:11:53 PM PDT 24
Peak memory 200484 kb
Host smart-cc29c843-704c-4283-9b8f-1f56662b9809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455486599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3455486599
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3901470525
Short name T911
Test name
Test status
Simulation time 8140100206 ps
CPU time 18.38 seconds
Started May 28 01:49:25 PM PDT 24
Finished May 28 01:49:47 PM PDT 24
Peak memory 199808 kb
Host smart-0e8d3773-9b6b-4db2-931d-9ce43a827b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901470525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3901470525
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3427187741
Short name T450
Test name
Test status
Simulation time 193060266805 ps
CPU time 48.56 seconds
Started May 28 01:49:26 PM PDT 24
Finished May 28 01:50:19 PM PDT 24
Peak memory 200636 kb
Host smart-3722c908-44d3-4755-a023-d41107cb0226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427187741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3427187741
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2300017120
Short name T729
Test name
Test status
Simulation time 14534373524 ps
CPU time 419.14 seconds
Started May 28 01:49:22 PM PDT 24
Finished May 28 01:56:24 PM PDT 24
Peak memory 200516 kb
Host smart-bf1b0ef2-afa9-4245-86b5-68c0eb3a5a73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2300017120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2300017120
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1150777303
Short name T602
Test name
Test status
Simulation time 2229890378 ps
CPU time 12.68 seconds
Started May 28 01:49:22 PM PDT 24
Finished May 28 01:49:37 PM PDT 24
Peak memory 198532 kb
Host smart-ca6267e2-c7e6-4fe8-a341-c40951d8c299
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150777303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1150777303
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1678459355
Short name T185
Test name
Test status
Simulation time 118330277653 ps
CPU time 33.13 seconds
Started May 28 01:49:30 PM PDT 24
Finished May 28 01:50:06 PM PDT 24
Peak memory 200372 kb
Host smart-c85e5b14-f7ac-4286-8142-9412240e573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678459355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1678459355
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.708973914
Short name T858
Test name
Test status
Simulation time 4243123293 ps
CPU time 7.17 seconds
Started May 28 01:49:28 PM PDT 24
Finished May 28 01:49:39 PM PDT 24
Peak memory 196812 kb
Host smart-bd8c8678-7d4a-46b9-8981-02d2ebe3e2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708973914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.708973914
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.764485493
Short name T352
Test name
Test status
Simulation time 90558741 ps
CPU time 1.08 seconds
Started May 28 01:49:27 PM PDT 24
Finished May 28 01:49:32 PM PDT 24
Peak memory 198928 kb
Host smart-af085c30-15f8-4921-b5c8-650325096d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764485493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.764485493
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1267688997
Short name T1029
Test name
Test status
Simulation time 231997703925 ps
CPU time 802.29 seconds
Started May 28 01:49:27 PM PDT 24
Finished May 28 02:02:53 PM PDT 24
Peak memory 200524 kb
Host smart-0df23f47-8e2e-4319-8281-addf4805ac7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267688997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1267688997
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.269103782
Short name T57
Test name
Test status
Simulation time 64088462744 ps
CPU time 1158.67 seconds
Started May 28 01:49:25 PM PDT 24
Finished May 28 02:08:47 PM PDT 24
Peak memory 216888 kb
Host smart-822693ae-18a7-4135-a9b5-917f115ff1ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269103782 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.269103782
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1869550980
Short name T683
Test name
Test status
Simulation time 1435526245 ps
CPU time 3.47 seconds
Started May 28 01:49:26 PM PDT 24
Finished May 28 01:49:33 PM PDT 24
Peak memory 200028 kb
Host smart-05673324-f900-49ec-a3ca-c93088c15e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869550980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1869550980
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3952684278
Short name T401
Test name
Test status
Simulation time 62585731578 ps
CPU time 27.96 seconds
Started May 28 01:49:22 PM PDT 24
Finished May 28 01:49:53 PM PDT 24
Peak memory 200488 kb
Host smart-f34f5128-41ac-43cc-a328-f63c4a897d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952684278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3952684278
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.295834585
Short name T1124
Test name
Test status
Simulation time 23083393397 ps
CPU time 45.42 seconds
Started May 28 01:52:47 PM PDT 24
Finished May 28 01:53:34 PM PDT 24
Peak memory 200452 kb
Host smart-e952550b-5543-4c20-b0d3-5b5093dc8326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295834585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.295834585
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1436880710
Short name T56
Test name
Test status
Simulation time 124720150086 ps
CPU time 157.91 seconds
Started May 28 01:52:50 PM PDT 24
Finished May 28 01:55:30 PM PDT 24
Peak memory 200536 kb
Host smart-49c238ee-4439-468a-bd8e-9254bb582520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436880710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1436880710
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1486278946
Short name T195
Test name
Test status
Simulation time 80984610404 ps
CPU time 149.9 seconds
Started May 28 01:52:52 PM PDT 24
Finished May 28 01:55:24 PM PDT 24
Peak memory 200532 kb
Host smart-5b863f98-9e48-43db-8002-1e437eb96e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486278946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1486278946
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1950410297
Short name T266
Test name
Test status
Simulation time 56647931616 ps
CPU time 23.18 seconds
Started May 28 01:52:57 PM PDT 24
Finished May 28 01:53:21 PM PDT 24
Peak memory 200160 kb
Host smart-4b67de50-b6fe-4b58-9541-37563da7e895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950410297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1950410297
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1628485388
Short name T210
Test name
Test status
Simulation time 102076876191 ps
CPU time 30.56 seconds
Started May 28 01:52:51 PM PDT 24
Finished May 28 01:53:24 PM PDT 24
Peak memory 200548 kb
Host smart-6afa3fc3-c922-4b70-9e88-3b7d8ada4e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628485388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1628485388
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3979994871
Short name T614
Test name
Test status
Simulation time 125043265396 ps
CPU time 105.34 seconds
Started May 28 01:52:49 PM PDT 24
Finished May 28 01:54:37 PM PDT 24
Peak memory 200432 kb
Host smart-7b0d0040-5dbc-42c5-998a-23ad90336930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979994871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3979994871
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3717475617
Short name T862
Test name
Test status
Simulation time 5215213334 ps
CPU time 9.01 seconds
Started May 28 01:52:56 PM PDT 24
Finished May 28 01:53:06 PM PDT 24
Peak memory 199664 kb
Host smart-21ab1d69-3b44-42f7-a398-60898574764a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717475617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3717475617
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1506778567
Short name T999
Test name
Test status
Simulation time 14347443847 ps
CPU time 29.98 seconds
Started May 28 01:52:50 PM PDT 24
Finished May 28 01:53:23 PM PDT 24
Peak memory 200460 kb
Host smart-b91a5d37-b0ba-4b46-ac0a-d9ddce3528c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506778567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1506778567
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.456728253
Short name T172
Test name
Test status
Simulation time 125474545463 ps
CPU time 74.94 seconds
Started May 28 01:52:58 PM PDT 24
Finished May 28 01:54:16 PM PDT 24
Peak memory 200564 kb
Host smart-4d86af99-ffcd-4ca9-a9e9-eec934615f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456728253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.456728253
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3305525809
Short name T367
Test name
Test status
Simulation time 17585164 ps
CPU time 0.56 seconds
Started May 28 01:49:34 PM PDT 24
Finished May 28 01:49:35 PM PDT 24
Peak memory 195616 kb
Host smart-8683c6c5-2b31-4363-83aa-8deb4ae57145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305525809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3305525809
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2437214591
Short name T1180
Test name
Test status
Simulation time 78255577512 ps
CPU time 68.86 seconds
Started May 28 01:49:29 PM PDT 24
Finished May 28 01:50:41 PM PDT 24
Peak memory 200348 kb
Host smart-9fae0bec-2812-4bd1-ae5e-22d815e1146c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437214591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2437214591
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3985664000
Short name T1166
Test name
Test status
Simulation time 102757925181 ps
CPU time 51.27 seconds
Started May 28 01:49:34 PM PDT 24
Finished May 28 01:50:26 PM PDT 24
Peak memory 200188 kb
Host smart-cde6c517-f92c-48ce-826b-34dfab542b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985664000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3985664000
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2082942498
Short name T259
Test name
Test status
Simulation time 121349794440 ps
CPU time 326.05 seconds
Started May 28 01:49:25 PM PDT 24
Finished May 28 01:54:55 PM PDT 24
Peak memory 200228 kb
Host smart-f8d41861-4469-4bbd-b9e4-a800b60b574c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082942498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2082942498
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3705543749
Short name T1063
Test name
Test status
Simulation time 15466860733 ps
CPU time 33.1 seconds
Started May 28 01:49:28 PM PDT 24
Finished May 28 01:50:05 PM PDT 24
Peak memory 200256 kb
Host smart-ea266159-5145-4019-925f-45dc918ca80d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705543749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3705543749
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2364681725
Short name T501
Test name
Test status
Simulation time 75890666098 ps
CPU time 197.67 seconds
Started May 28 01:49:24 PM PDT 24
Finished May 28 01:52:45 PM PDT 24
Peak memory 200496 kb
Host smart-b8ec248e-7f81-458f-8021-821a2f2d8bcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2364681725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2364681725
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2882296322
Short name T682
Test name
Test status
Simulation time 4252969853 ps
CPU time 4.48 seconds
Started May 28 01:49:24 PM PDT 24
Finished May 28 01:49:32 PM PDT 24
Peak memory 199692 kb
Host smart-061d341b-5e37-47a7-982c-c1a467f6b0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882296322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2882296322
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1753176703
Short name T905
Test name
Test status
Simulation time 590085471695 ps
CPU time 83.99 seconds
Started May 28 01:49:35 PM PDT 24
Finished May 28 01:51:00 PM PDT 24
Peak memory 201280 kb
Host smart-a1fc1155-9226-49e2-a9e2-253b6c62fb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753176703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1753176703
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1801183545
Short name T826
Test name
Test status
Simulation time 17445384551 ps
CPU time 238.05 seconds
Started May 28 01:49:34 PM PDT 24
Finished May 28 01:53:33 PM PDT 24
Peak memory 200496 kb
Host smart-0fedb12b-3494-4ebc-9775-55a99af7e7a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1801183545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1801183545
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1786829367
Short name T1075
Test name
Test status
Simulation time 3192855805 ps
CPU time 7.19 seconds
Started May 28 01:49:25 PM PDT 24
Finished May 28 01:49:36 PM PDT 24
Peak memory 199116 kb
Host smart-c5f49de2-51a4-4495-a543-daa12770cc14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1786829367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1786829367
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2670261128
Short name T537
Test name
Test status
Simulation time 95908126975 ps
CPU time 377.52 seconds
Started May 28 01:49:26 PM PDT 24
Finished May 28 01:55:48 PM PDT 24
Peak memory 200504 kb
Host smart-13d21ac0-33de-4bd3-91dd-3f9655eb65c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670261128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2670261128
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3902743931
Short name T589
Test name
Test status
Simulation time 1983534092 ps
CPU time 3.78 seconds
Started May 28 01:49:25 PM PDT 24
Finished May 28 01:49:33 PM PDT 24
Peak memory 195660 kb
Host smart-0a3f1306-9eb0-4e8d-8941-9e8f9caf2b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902743931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3902743931
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.668171923
Short name T766
Test name
Test status
Simulation time 268025861 ps
CPU time 1.53 seconds
Started May 28 01:49:25 PM PDT 24
Finished May 28 01:49:30 PM PDT 24
Peak memory 200416 kb
Host smart-454442fd-c05d-463a-89f1-e00b1f805226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668171923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.668171923
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.1480026295
Short name T425
Test name
Test status
Simulation time 364251768631 ps
CPU time 910.68 seconds
Started May 28 01:49:33 PM PDT 24
Finished May 28 02:04:45 PM PDT 24
Peak memory 200512 kb
Host smart-10852bdd-08b0-474b-bd50-fd7f430f283b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480026295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1480026295
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.943637073
Short name T1062
Test name
Test status
Simulation time 1040036206 ps
CPU time 3.27 seconds
Started May 28 01:49:34 PM PDT 24
Finished May 28 01:49:39 PM PDT 24
Peak memory 199028 kb
Host smart-0c4d68c1-a412-4713-862f-8325d45f8927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943637073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.943637073
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.926451123
Short name T743
Test name
Test status
Simulation time 73977119663 ps
CPU time 29.63 seconds
Started May 28 01:49:28 PM PDT 24
Finished May 28 01:50:02 PM PDT 24
Peak memory 197616 kb
Host smart-778ad83e-0b96-423d-bd10-4f192e5bb985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926451123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.926451123
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1015110221
Short name T473
Test name
Test status
Simulation time 38562394687 ps
CPU time 25.1 seconds
Started May 28 01:52:47 PM PDT 24
Finished May 28 01:53:14 PM PDT 24
Peak memory 200548 kb
Host smart-e14a4fe9-3746-411d-b34c-5349b9a7f777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015110221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1015110221
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2199914059
Short name T1015
Test name
Test status
Simulation time 19067094471 ps
CPU time 7.6 seconds
Started May 28 01:52:47 PM PDT 24
Finished May 28 01:52:56 PM PDT 24
Peak memory 200548 kb
Host smart-de9a3567-9b6f-4f2c-afa3-20afd3cd312b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199914059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2199914059
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.194561092
Short name T658
Test name
Test status
Simulation time 7497713470 ps
CPU time 13.19 seconds
Started May 28 01:52:49 PM PDT 24
Finished May 28 01:53:04 PM PDT 24
Peak memory 200508 kb
Host smart-82d2b059-c4ec-4873-b953-c89ff7e06c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194561092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.194561092
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.4258264172
Short name T77
Test name
Test status
Simulation time 45997392471 ps
CPU time 136.61 seconds
Started May 28 01:52:54 PM PDT 24
Finished May 28 01:55:12 PM PDT 24
Peak memory 200548 kb
Host smart-656af77d-591a-49c5-8f79-ff9ade6e1f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258264172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.4258264172
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3154494881
Short name T496
Test name
Test status
Simulation time 19772810436 ps
CPU time 11.29 seconds
Started May 28 01:52:54 PM PDT 24
Finished May 28 01:53:07 PM PDT 24
Peak memory 200492 kb
Host smart-5c6e702d-c305-4eb1-8137-05fc397f1d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154494881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3154494881
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2784977180
Short name T657
Test name
Test status
Simulation time 71871509589 ps
CPU time 70.02 seconds
Started May 28 01:52:49 PM PDT 24
Finished May 28 01:54:02 PM PDT 24
Peak memory 200488 kb
Host smart-a87b751a-02e8-43fd-bbfa-7694c3ad0aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784977180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2784977180
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.448625740
Short name T231
Test name
Test status
Simulation time 94035811630 ps
CPU time 183.98 seconds
Started May 28 01:52:47 PM PDT 24
Finished May 28 01:55:53 PM PDT 24
Peak memory 200440 kb
Host smart-fc707dbd-9cc5-4db0-9737-0afa7a72ac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448625740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.448625740
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1503787306
Short name T243
Test name
Test status
Simulation time 87745620805 ps
CPU time 120.26 seconds
Started May 28 01:52:54 PM PDT 24
Finished May 28 01:54:56 PM PDT 24
Peak memory 200540 kb
Host smart-bd37bc51-cb28-4ab7-8302-6f79f07a4d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503787306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1503787306
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3615391063
Short name T906
Test name
Test status
Simulation time 35461113062 ps
CPU time 70.36 seconds
Started May 28 01:52:56 PM PDT 24
Finished May 28 01:54:07 PM PDT 24
Peak memory 200424 kb
Host smart-c2585d55-a200-43a3-a90e-7062cacb1460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615391063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3615391063
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1113067129
Short name T752
Test name
Test status
Simulation time 43505801 ps
CPU time 0.55 seconds
Started May 28 01:49:37 PM PDT 24
Finished May 28 01:49:39 PM PDT 24
Peak memory 195908 kb
Host smart-b657c535-5762-4a69-9174-d9f755bc3252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113067129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1113067129
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1712806570
Short name T386
Test name
Test status
Simulation time 43055580404 ps
CPU time 15.95 seconds
Started May 28 01:49:26 PM PDT 24
Finished May 28 01:49:46 PM PDT 24
Peak memory 200576 kb
Host smart-a6d11bc0-be8b-45a8-9180-654d45381eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712806570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1712806570
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3228273588
Short name T693
Test name
Test status
Simulation time 134620181973 ps
CPU time 67.79 seconds
Started May 28 01:49:34 PM PDT 24
Finished May 28 01:50:43 PM PDT 24
Peak memory 200428 kb
Host smart-418feec7-7bc4-4ea1-8b7d-b51084cf4e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228273588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3228273588
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.230224468
Short name T313
Test name
Test status
Simulation time 55485197468 ps
CPU time 24.83 seconds
Started May 28 01:49:26 PM PDT 24
Finished May 28 01:49:55 PM PDT 24
Peak memory 200144 kb
Host smart-7978ee1d-8dad-4e58-bc66-6fa058ff1d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230224468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.230224468
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.607736419
Short name T510
Test name
Test status
Simulation time 42924518440 ps
CPU time 18.77 seconds
Started May 28 01:49:26 PM PDT 24
Finished May 28 01:49:49 PM PDT 24
Peak memory 200116 kb
Host smart-5c99013e-75f6-4123-bb09-4a35e9bf8718
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607736419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.607736419
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1339987492
Short name T436
Test name
Test status
Simulation time 293122901428 ps
CPU time 103.48 seconds
Started May 28 01:49:37 PM PDT 24
Finished May 28 01:51:22 PM PDT 24
Peak memory 200480 kb
Host smart-1e6111fb-5105-4478-a31d-fed9c7d38db2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1339987492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1339987492
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3026667619
Short name T387
Test name
Test status
Simulation time 6404766332 ps
CPU time 13.28 seconds
Started May 28 01:49:36 PM PDT 24
Finished May 28 01:49:51 PM PDT 24
Peak memory 200248 kb
Host smart-894e0853-1714-447b-96e3-92ee2e3d3d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026667619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3026667619
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.671522817
Short name T1167
Test name
Test status
Simulation time 40146047989 ps
CPU time 58.07 seconds
Started May 28 01:49:35 PM PDT 24
Finished May 28 01:50:34 PM PDT 24
Peak memory 200444 kb
Host smart-f3349557-0c94-4c9a-85e5-589f2132ef14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671522817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.671522817
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.637116306
Short name T410
Test name
Test status
Simulation time 17431166169 ps
CPU time 206.8 seconds
Started May 28 01:49:36 PM PDT 24
Finished May 28 01:53:04 PM PDT 24
Peak memory 200496 kb
Host smart-1eb929c6-4634-4584-bcd1-c642307fe9eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=637116306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.637116306
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3925482671
Short name T865
Test name
Test status
Simulation time 5691687762 ps
CPU time 51.32 seconds
Started May 28 01:49:26 PM PDT 24
Finished May 28 01:50:20 PM PDT 24
Peak memory 198708 kb
Host smart-088782d6-8be1-4e65-8258-5da7d1c2931d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925482671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3925482671
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1445257407
Short name T409
Test name
Test status
Simulation time 40825964145 ps
CPU time 87.92 seconds
Started May 28 01:49:41 PM PDT 24
Finished May 28 01:51:11 PM PDT 24
Peak memory 200496 kb
Host smart-1576a396-d36d-48a3-85f3-66cd5e48ca34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445257407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1445257407
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2649169128
Short name T883
Test name
Test status
Simulation time 3174049879 ps
CPU time 5.51 seconds
Started May 28 01:49:41 PM PDT 24
Finished May 28 01:49:49 PM PDT 24
Peak memory 196304 kb
Host smart-ac1dd2c9-39e0-4173-9527-483d3da24805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649169128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2649169128
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2525383144
Short name T699
Test name
Test status
Simulation time 671845477 ps
CPU time 2.46 seconds
Started May 28 01:49:34 PM PDT 24
Finished May 28 01:49:38 PM PDT 24
Peak memory 199964 kb
Host smart-2aede21f-87b8-43df-8390-bb5a48aa7048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525383144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2525383144
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1784864003
Short name T492
Test name
Test status
Simulation time 158697487332 ps
CPU time 304.06 seconds
Started May 28 01:49:38 PM PDT 24
Finished May 28 01:54:45 PM PDT 24
Peak memory 200568 kb
Host smart-0881bf15-8ab3-4c58-9e07-cbe2538e601a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784864003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1784864003
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1111035922
Short name T1041
Test name
Test status
Simulation time 1309557532 ps
CPU time 1.49 seconds
Started May 28 01:49:36 PM PDT 24
Finished May 28 01:49:39 PM PDT 24
Peak memory 198724 kb
Host smart-3be6e661-ee34-49cf-bcfb-03b05f896af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111035922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1111035922
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.4146519308
Short name T322
Test name
Test status
Simulation time 62018143079 ps
CPU time 27.9 seconds
Started May 28 01:49:34 PM PDT 24
Finished May 28 01:50:04 PM PDT 24
Peak memory 200500 kb
Host smart-bfac87b9-7071-4785-8f85-96d6367b1971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146519308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.4146519308
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3347974086
Short name T508
Test name
Test status
Simulation time 109893586503 ps
CPU time 49.14 seconds
Started May 28 01:52:51 PM PDT 24
Finished May 28 01:53:43 PM PDT 24
Peak memory 200400 kb
Host smart-f3a93ea2-42c1-4f96-a735-71ebc12a643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347974086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3347974086
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.4080931669
Short name T740
Test name
Test status
Simulation time 26898269222 ps
CPU time 10.98 seconds
Started May 28 01:52:51 PM PDT 24
Finished May 28 01:53:04 PM PDT 24
Peak memory 200468 kb
Host smart-820573b2-2600-4eac-8198-ddd0c96dc1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080931669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.4080931669
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1520367311
Short name T1112
Test name
Test status
Simulation time 16169357018 ps
CPU time 25.35 seconds
Started May 28 01:52:47 PM PDT 24
Finished May 28 01:53:14 PM PDT 24
Peak memory 200368 kb
Host smart-89bd3956-9dd9-4def-a553-83295b675522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520367311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1520367311
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1724242568
Short name T217
Test name
Test status
Simulation time 43277265521 ps
CPU time 19.4 seconds
Started May 28 01:52:47 PM PDT 24
Finished May 28 01:53:07 PM PDT 24
Peak memory 200576 kb
Host smart-7d2007d3-1f03-475b-ab32-ae9a6c595393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724242568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1724242568
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3328025850
Short name T719
Test name
Test status
Simulation time 134341874328 ps
CPU time 69.57 seconds
Started May 28 01:52:52 PM PDT 24
Finished May 28 01:54:03 PM PDT 24
Peak memory 200520 kb
Host smart-55bc2603-9cfd-4712-87e9-30610b88ed67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328025850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3328025850
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.501294524
Short name T205
Test name
Test status
Simulation time 26928460604 ps
CPU time 46.95 seconds
Started May 28 01:52:51 PM PDT 24
Finished May 28 01:53:40 PM PDT 24
Peak memory 200496 kb
Host smart-96a6ad3e-b365-4a4b-a953-bab54e82e100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501294524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.501294524
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.124348897
Short name T1004
Test name
Test status
Simulation time 9636134161 ps
CPU time 20.94 seconds
Started May 28 01:52:49 PM PDT 24
Finished May 28 01:53:13 PM PDT 24
Peak memory 200528 kb
Host smart-814b88d3-6e5c-4a0d-9a55-e4dad861ad4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124348897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.124348897
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2532847920
Short name T9
Test name
Test status
Simulation time 149431636256 ps
CPU time 14.03 seconds
Started May 28 01:52:59 PM PDT 24
Finished May 28 01:53:15 PM PDT 24
Peak memory 200492 kb
Host smart-371cf979-c34e-48a9-afa6-69e44f9708f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532847920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2532847920
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3435638026
Short name T246
Test name
Test status
Simulation time 58341772174 ps
CPU time 26.23 seconds
Started May 28 01:52:58 PM PDT 24
Finished May 28 01:53:26 PM PDT 24
Peak memory 200468 kb
Host smart-cf8c7102-8d5f-4202-bb46-77789d09b4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435638026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3435638026
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3618915260
Short name T789
Test name
Test status
Simulation time 15753386 ps
CPU time 0.55 seconds
Started May 28 01:48:51 PM PDT 24
Finished May 28 01:48:55 PM PDT 24
Peak memory 195904 kb
Host smart-62f535e1-08c8-40c8-a637-f780aa2ab4ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618915260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3618915260
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3431230853
Short name T1050
Test name
Test status
Simulation time 133498382118 ps
CPU time 43.57 seconds
Started May 28 01:48:47 PM PDT 24
Finished May 28 01:49:35 PM PDT 24
Peak memory 200484 kb
Host smart-ea9e9640-d072-4e84-b6a4-95b5e4f637a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431230853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3431230853
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.919258088
Short name T499
Test name
Test status
Simulation time 46122577511 ps
CPU time 20.98 seconds
Started May 28 01:48:45 PM PDT 24
Finished May 28 01:49:11 PM PDT 24
Peak memory 200488 kb
Host smart-fb5aaaae-8393-4928-89e4-6379d120dbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919258088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.919258088
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2153546606
Short name T652
Test name
Test status
Simulation time 86747284997 ps
CPU time 14.22 seconds
Started May 28 01:48:47 PM PDT 24
Finished May 28 01:49:06 PM PDT 24
Peak memory 200500 kb
Host smart-eb3fb5e2-dc01-489f-baad-549f8e0d163e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153546606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2153546606
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2855938299
Short name T671
Test name
Test status
Simulation time 19152571441 ps
CPU time 13.66 seconds
Started May 28 01:48:47 PM PDT 24
Finished May 28 01:49:06 PM PDT 24
Peak memory 198332 kb
Host smart-27256e2d-c70f-4d48-8a74-7c49ca00a1af
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855938299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2855938299
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.4139135035
Short name T722
Test name
Test status
Simulation time 352841858615 ps
CPU time 147.94 seconds
Started May 28 01:48:52 PM PDT 24
Finished May 28 01:51:22 PM PDT 24
Peak memory 200472 kb
Host smart-b9192168-36bb-4ea7-a4c2-14fc08536f71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139135035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4139135035
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.345168569
Short name T350
Test name
Test status
Simulation time 97876419 ps
CPU time 0.73 seconds
Started May 28 01:48:52 PM PDT 24
Finished May 28 01:48:55 PM PDT 24
Peak memory 196296 kb
Host smart-eb1c79a7-8167-46a0-b310-8c68d1a0fa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345168569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.345168569
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.81688730
Short name T284
Test name
Test status
Simulation time 27453833359 ps
CPU time 46.52 seconds
Started May 28 01:48:46 PM PDT 24
Finished May 28 01:49:38 PM PDT 24
Peak memory 199448 kb
Host smart-d932a3bf-c86e-4a9c-910a-a8723f2b7f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81688730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.81688730
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.230574111
Short name T78
Test name
Test status
Simulation time 5494677239 ps
CPU time 99.26 seconds
Started May 28 01:48:53 PM PDT 24
Finished May 28 01:50:34 PM PDT 24
Peak memory 200528 kb
Host smart-85b29ac5-5e4c-4e20-a113-2b554511272a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230574111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.230574111
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1485138067
Short name T570
Test name
Test status
Simulation time 4792261159 ps
CPU time 31.54 seconds
Started May 28 01:48:50 PM PDT 24
Finished May 28 01:49:25 PM PDT 24
Peak memory 198420 kb
Host smart-482becb8-7c17-4c12-93c7-6a75536c9f4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485138067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1485138067
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3493643379
Short name T835
Test name
Test status
Simulation time 213716868351 ps
CPU time 68.55 seconds
Started May 28 01:48:55 PM PDT 24
Finished May 28 01:50:04 PM PDT 24
Peak memory 200508 kb
Host smart-52d057ef-16b2-4f8c-8de5-0bd908287d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493643379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3493643379
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1348182741
Short name T1066
Test name
Test status
Simulation time 4203836059 ps
CPU time 7.5 seconds
Started May 28 01:48:54 PM PDT 24
Finished May 28 01:49:03 PM PDT 24
Peak memory 196788 kb
Host smart-a85c3a71-4181-4ed1-a62b-bafa39c12da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348182741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1348182741
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3822101501
Short name T34
Test name
Test status
Simulation time 67634512 ps
CPU time 0.78 seconds
Started May 28 01:48:51 PM PDT 24
Finished May 28 01:48:55 PM PDT 24
Peak memory 219028 kb
Host smart-8480ca4a-8280-4b5e-be8f-89c9265ad004
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822101501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3822101501
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3879434092
Short name T1151
Test name
Test status
Simulation time 733269053 ps
CPU time 1.64 seconds
Started May 28 01:48:45 PM PDT 24
Finished May 28 01:48:52 PM PDT 24
Peak memory 199220 kb
Host smart-93517d21-43c9-4fa4-b2d8-ed1beac71203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879434092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3879434092
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1763366190
Short name T1006
Test name
Test status
Simulation time 284033180455 ps
CPU time 561.73 seconds
Started May 28 01:48:51 PM PDT 24
Finished May 28 01:58:16 PM PDT 24
Peak memory 200536 kb
Host smart-c00ce291-399c-4c61-8064-fa748721e417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763366190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1763366190
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3880877351
Short name T19
Test name
Test status
Simulation time 7257201326 ps
CPU time 15.15 seconds
Started May 28 01:48:49 PM PDT 24
Finished May 28 01:49:08 PM PDT 24
Peak memory 200364 kb
Host smart-8f76cd8b-8f47-46fe-9771-2fbc3cc91dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880877351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3880877351
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.273222129
Short name T1150
Test name
Test status
Simulation time 133322125520 ps
CPU time 88.54 seconds
Started May 28 01:48:47 PM PDT 24
Finished May 28 01:50:20 PM PDT 24
Peak memory 200532 kb
Host smart-7cf7683f-2b2b-46eb-b4bc-80689e284025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273222129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.273222129
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2134312603
Short name T984
Test name
Test status
Simulation time 41193157 ps
CPU time 0.57 seconds
Started May 28 01:49:38 PM PDT 24
Finished May 28 01:49:41 PM PDT 24
Peak memory 195884 kb
Host smart-f8275f5d-b192-4991-a4f6-d5b72a40096c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134312603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2134312603
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3244828569
Short name T952
Test name
Test status
Simulation time 90918780685 ps
CPU time 144.88 seconds
Started May 28 01:49:36 PM PDT 24
Finished May 28 01:52:02 PM PDT 24
Peak memory 200508 kb
Host smart-8aab1e10-b3c4-4be6-9039-4112b6e5014c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244828569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3244828569
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2679607280
Short name T934
Test name
Test status
Simulation time 102445694672 ps
CPU time 42.29 seconds
Started May 28 01:49:37 PM PDT 24
Finished May 28 01:50:21 PM PDT 24
Peak memory 200520 kb
Host smart-697b0113-b120-4aee-ad67-88c045184e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679607280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2679607280
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2176780761
Short name T220
Test name
Test status
Simulation time 189984175913 ps
CPU time 73.31 seconds
Started May 28 01:49:36 PM PDT 24
Finished May 28 01:50:51 PM PDT 24
Peak memory 200688 kb
Host smart-a37da584-05be-494d-962a-974068ae6cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176780761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2176780761
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1020262246
Short name T51
Test name
Test status
Simulation time 57347204790 ps
CPU time 47.39 seconds
Started May 28 01:49:37 PM PDT 24
Finished May 28 01:50:26 PM PDT 24
Peak memory 200532 kb
Host smart-3eda04ae-11f3-49f5-8963-100f35d06389
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020262246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1020262246
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.990689783
Short name T986
Test name
Test status
Simulation time 117714077633 ps
CPU time 584.55 seconds
Started May 28 01:49:45 PM PDT 24
Finished May 28 01:59:32 PM PDT 24
Peak memory 200316 kb
Host smart-1485ba05-c110-4d82-b14a-943b26865d61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=990689783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.990689783
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2010049482
Short name T961
Test name
Test status
Simulation time 6981279724 ps
CPU time 15.68 seconds
Started May 28 01:49:38 PM PDT 24
Finished May 28 01:49:55 PM PDT 24
Peak memory 199136 kb
Host smart-97a50c28-61d9-45d9-946e-6065f6211d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010049482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2010049482
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3484750826
Short name T792
Test name
Test status
Simulation time 56363237922 ps
CPU time 97.69 seconds
Started May 28 01:49:41 PM PDT 24
Finished May 28 01:51:21 PM PDT 24
Peak memory 200692 kb
Host smart-28ff378c-5fe4-4ec5-9246-31dda8e7b694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484750826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3484750826
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.982917521
Short name T639
Test name
Test status
Simulation time 7752320715 ps
CPU time 307.14 seconds
Started May 28 01:49:39 PM PDT 24
Finished May 28 01:54:48 PM PDT 24
Peak memory 200140 kb
Host smart-c322deb1-d240-4649-a951-22c55862d80e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=982917521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.982917521
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.4185133352
Short name T1001
Test name
Test status
Simulation time 4341650970 ps
CPU time 15.1 seconds
Started May 28 01:49:38 PM PDT 24
Finished May 28 01:49:56 PM PDT 24
Peak memory 198700 kb
Host smart-9ee4fc0f-4a02-4dec-ad70-4fd164d24283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185133352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.4185133352
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1061603418
Short name T140
Test name
Test status
Simulation time 42477572807 ps
CPU time 17.13 seconds
Started May 28 01:49:42 PM PDT 24
Finished May 28 01:50:01 PM PDT 24
Peak memory 200440 kb
Host smart-c4a7f7fa-7f30-4fac-a658-99b1c1d0cd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061603418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1061603418
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.430999144
Short name T819
Test name
Test status
Simulation time 39145892373 ps
CPU time 11.2 seconds
Started May 28 01:49:37 PM PDT 24
Finished May 28 01:49:49 PM PDT 24
Peak memory 196488 kb
Host smart-003b8b37-442b-4560-9e93-6f60e95f2fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430999144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.430999144
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3537104161
Short name T50
Test name
Test status
Simulation time 757239811 ps
CPU time 1.07 seconds
Started May 28 01:49:39 PM PDT 24
Finished May 28 01:49:42 PM PDT 24
Peak memory 199528 kb
Host smart-9c502a07-5305-4f6a-8ef9-c140fd9503ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537104161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3537104161
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.511899249
Short name T1026
Test name
Test status
Simulation time 117820258179 ps
CPU time 338.16 seconds
Started May 28 01:49:37 PM PDT 24
Finished May 28 01:55:17 PM PDT 24
Peak memory 225256 kb
Host smart-bd7602b3-44a9-4167-82f6-897204cd726b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511899249 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.511899249
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3610504894
Short name T316
Test name
Test status
Simulation time 1369744619 ps
CPU time 2.68 seconds
Started May 28 01:49:40 PM PDT 24
Finished May 28 01:49:45 PM PDT 24
Peak memory 199332 kb
Host smart-857edadf-1626-40be-83b6-7e23f55d3890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610504894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3610504894
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.232051402
Short name T272
Test name
Test status
Simulation time 60642312817 ps
CPU time 32.87 seconds
Started May 28 01:49:38 PM PDT 24
Finished May 28 01:50:13 PM PDT 24
Peak memory 200468 kb
Host smart-ece477fd-b551-4d03-8b01-d10327654e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232051402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.232051402
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1755989040
Short name T794
Test name
Test status
Simulation time 59087023754 ps
CPU time 193.57 seconds
Started May 28 01:52:49 PM PDT 24
Finished May 28 01:56:05 PM PDT 24
Peak memory 200444 kb
Host smart-87dc3508-dcd9-4a3f-b154-2d7e7a29f4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755989040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1755989040
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3652913610
Short name T199
Test name
Test status
Simulation time 22386210089 ps
CPU time 38.05 seconds
Started May 28 01:52:56 PM PDT 24
Finished May 28 01:53:35 PM PDT 24
Peak memory 200364 kb
Host smart-1c230ad1-b0bb-420d-bb77-3d32e44d6c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652913610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3652913610
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2661992348
Short name T42
Test name
Test status
Simulation time 11764732610 ps
CPU time 10.92 seconds
Started May 28 01:52:55 PM PDT 24
Finished May 28 01:53:07 PM PDT 24
Peak memory 200356 kb
Host smart-2351832d-a150-4764-aa2b-c3a6c87ce02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661992348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2661992348
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3321346658
Short name T437
Test name
Test status
Simulation time 247555236731 ps
CPU time 104.21 seconds
Started May 28 01:52:46 PM PDT 24
Finished May 28 01:54:31 PM PDT 24
Peak memory 200380 kb
Host smart-915a7257-50ac-4698-bc5c-9e989e893713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321346658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3321346658
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.217593042
Short name T460
Test name
Test status
Simulation time 11752219623 ps
CPU time 18.2 seconds
Started May 28 01:52:51 PM PDT 24
Finished May 28 01:53:12 PM PDT 24
Peak memory 200296 kb
Host smart-40009347-2eb8-42be-b641-1e87e3f43f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217593042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.217593042
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3153016392
Short name T621
Test name
Test status
Simulation time 86690705799 ps
CPU time 152.11 seconds
Started May 28 01:52:49 PM PDT 24
Finished May 28 01:55:23 PM PDT 24
Peak memory 200528 kb
Host smart-88c85561-d8db-4d35-ba8a-f6f13575a532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153016392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3153016392
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1164316879
Short name T145
Test name
Test status
Simulation time 68545392466 ps
CPU time 31.35 seconds
Started May 28 01:52:49 PM PDT 24
Finished May 28 01:53:23 PM PDT 24
Peak memory 200464 kb
Host smart-a5cf1352-fff2-4cd7-9682-d9699d2a7b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164316879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1164316879
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1214587215
Short name T901
Test name
Test status
Simulation time 23695312403 ps
CPU time 12.75 seconds
Started May 28 01:52:59 PM PDT 24
Finished May 28 01:53:14 PM PDT 24
Peak memory 200276 kb
Host smart-a8919222-5f6e-4a9e-ad48-bad9f4523bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214587215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1214587215
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.474657806
Short name T413
Test name
Test status
Simulation time 42993029 ps
CPU time 0.56 seconds
Started May 28 01:49:39 PM PDT 24
Finished May 28 01:49:41 PM PDT 24
Peak memory 195876 kb
Host smart-2e31be90-09f8-4faa-8739-6060d283d460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474657806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.474657806
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1574588922
Short name T991
Test name
Test status
Simulation time 145453388733 ps
CPU time 176.85 seconds
Started May 28 01:49:43 PM PDT 24
Finished May 28 01:52:42 PM PDT 24
Peak memory 200388 kb
Host smart-b834f0de-5d29-48c0-9f12-a48531c0d3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574588922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1574588922
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.864331200
Short name T662
Test name
Test status
Simulation time 28510813843 ps
CPU time 11.41 seconds
Started May 28 01:49:43 PM PDT 24
Finished May 28 01:49:56 PM PDT 24
Peak memory 200468 kb
Host smart-3bfad2e3-f681-4299-8d73-cf584604dc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864331200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.864331200
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2172433346
Short name T779
Test name
Test status
Simulation time 213178248369 ps
CPU time 76.03 seconds
Started May 28 01:49:44 PM PDT 24
Finished May 28 01:51:01 PM PDT 24
Peak memory 199716 kb
Host smart-ae513f11-6bdc-4aea-81bf-4c5de68ee1e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172433346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2172433346
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1563309770
Short name T738
Test name
Test status
Simulation time 44364898775 ps
CPU time 225.6 seconds
Started May 28 01:49:39 PM PDT 24
Finished May 28 01:53:26 PM PDT 24
Peak memory 200576 kb
Host smart-d6bb488b-82a5-4e7f-a096-a03c9f6a2887
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1563309770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1563309770
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3140715650
Short name T381
Test name
Test status
Simulation time 5148400766 ps
CPU time 5 seconds
Started May 28 01:49:46 PM PDT 24
Finished May 28 01:49:54 PM PDT 24
Peak memory 198708 kb
Host smart-f81f462b-eba8-4479-a6e6-0cb71e1aa9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140715650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3140715650
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.2036736167
Short name T595
Test name
Test status
Simulation time 141336947510 ps
CPU time 279.89 seconds
Started May 28 01:49:41 PM PDT 24
Finished May 28 01:54:23 PM PDT 24
Peak memory 200576 kb
Host smart-1609a7f2-de39-4fed-9a13-b222fe7f2df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036736167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2036736167
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1222008366
Short name T945
Test name
Test status
Simulation time 22059894271 ps
CPU time 311.39 seconds
Started May 28 01:49:42 PM PDT 24
Finished May 28 01:54:55 PM PDT 24
Peak memory 200508 kb
Host smart-3c1900d4-47b2-4f0d-8329-1c2af3ef5e7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222008366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1222008366
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.933733273
Short name T493
Test name
Test status
Simulation time 3889483124 ps
CPU time 5.67 seconds
Started May 28 01:49:46 PM PDT 24
Finished May 28 01:49:54 PM PDT 24
Peak memory 198608 kb
Host smart-a4c22d69-2059-4b68-8f11-8ac35d50ed86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933733273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.933733273
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2540756026
Short name T287
Test name
Test status
Simulation time 47663048227 ps
CPU time 77.93 seconds
Started May 28 01:49:46 PM PDT 24
Finished May 28 01:51:07 PM PDT 24
Peak memory 200472 kb
Host smart-008ad522-5d26-48a7-b83a-8d70e1a02edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540756026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2540756026
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.4149167351
Short name T851
Test name
Test status
Simulation time 31177598089 ps
CPU time 26.48 seconds
Started May 28 01:49:46 PM PDT 24
Finished May 28 01:50:15 PM PDT 24
Peak memory 196216 kb
Host smart-afb1d702-64e7-44e5-9ca2-89ec5a8e1a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149167351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.4149167351
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1510377534
Short name T1084
Test name
Test status
Simulation time 11076022913 ps
CPU time 15.21 seconds
Started May 28 01:49:42 PM PDT 24
Finished May 28 01:49:59 PM PDT 24
Peak memory 200272 kb
Host smart-4e3f80a4-4849-4d5c-92e6-ff81b139ee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510377534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1510377534
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1594430790
Short name T323
Test name
Test status
Simulation time 224954366723 ps
CPU time 104.98 seconds
Started May 28 01:49:39 PM PDT 24
Finished May 28 01:51:26 PM PDT 24
Peak memory 200468 kb
Host smart-5f596348-62b0-4917-96cb-6f5f0a91b271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594430790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1594430790
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3364121888
Short name T797
Test name
Test status
Simulation time 257927259375 ps
CPU time 672.46 seconds
Started May 28 01:49:39 PM PDT 24
Finished May 28 02:00:54 PM PDT 24
Peak memory 225400 kb
Host smart-51898ce6-fe89-4d1c-8fa0-7842925f0a07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364121888 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3364121888
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.4124286453
Short name T416
Test name
Test status
Simulation time 7586970606 ps
CPU time 2.33 seconds
Started May 28 01:49:45 PM PDT 24
Finished May 28 01:49:49 PM PDT 24
Peak memory 200324 kb
Host smart-580ea347-09dc-4c89-8bd1-6c23b4a9e8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124286453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.4124286453
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1667572794
Short name T715
Test name
Test status
Simulation time 344865649975 ps
CPU time 47.8 seconds
Started May 28 01:49:42 PM PDT 24
Finished May 28 01:50:31 PM PDT 24
Peak memory 200460 kb
Host smart-ca178a0e-1595-4918-879e-e2357b35bd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667572794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1667572794
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2592552666
Short name T439
Test name
Test status
Simulation time 26332911731 ps
CPU time 67.55 seconds
Started May 28 01:52:48 PM PDT 24
Finished May 28 01:53:57 PM PDT 24
Peak memory 200484 kb
Host smart-9bc0b426-7149-4721-a4bf-13c3d7adf286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592552666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2592552666
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.151479364
Short name T989
Test name
Test status
Simulation time 131235151578 ps
CPU time 101.26 seconds
Started May 28 01:52:51 PM PDT 24
Finished May 28 01:54:35 PM PDT 24
Peak memory 200492 kb
Host smart-8a15b264-7e1f-442b-a9b6-d41a0d6faaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151479364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.151479364
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1251052115
Short name T615
Test name
Test status
Simulation time 22117419882 ps
CPU time 12.24 seconds
Started May 28 01:52:58 PM PDT 24
Finished May 28 01:53:13 PM PDT 24
Peak memory 200492 kb
Host smart-0b2eec2d-ce5d-40d8-bc3c-0de349218aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251052115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1251052115
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.4213179575
Short name T126
Test name
Test status
Simulation time 20844546808 ps
CPU time 40.62 seconds
Started May 28 01:52:57 PM PDT 24
Finished May 28 01:53:39 PM PDT 24
Peak memory 200340 kb
Host smart-3af0de95-1ec2-4c71-8bbf-f65fb6ec6ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213179575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.4213179575
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3329584419
Short name T787
Test name
Test status
Simulation time 55537163055 ps
CPU time 78.29 seconds
Started May 28 01:52:56 PM PDT 24
Finished May 28 01:54:15 PM PDT 24
Peak memory 200160 kb
Host smart-09f629fe-f4da-4128-b53e-82c17f8a1b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329584419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3329584419
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1937677609
Short name T1110
Test name
Test status
Simulation time 53810494125 ps
CPU time 85.02 seconds
Started May 28 01:52:48 PM PDT 24
Finished May 28 01:54:15 PM PDT 24
Peak memory 200312 kb
Host smart-85210305-8bdf-43ab-912b-57712c3ac655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937677609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1937677609
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1427843488
Short name T1008
Test name
Test status
Simulation time 36112213333 ps
CPU time 37 seconds
Started May 28 01:52:50 PM PDT 24
Finished May 28 01:53:30 PM PDT 24
Peak memory 200480 kb
Host smart-732e1181-7a79-460e-8995-f5f38ab8c6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427843488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1427843488
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.4004898198
Short name T716
Test name
Test status
Simulation time 73790079750 ps
CPU time 19.24 seconds
Started May 28 01:53:02 PM PDT 24
Finished May 28 01:53:23 PM PDT 24
Peak memory 200312 kb
Host smart-f08a6a08-0347-4191-8fbf-c31997175a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004898198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4004898198
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1991162293
Short name T824
Test name
Test status
Simulation time 52647189849 ps
CPU time 26.57 seconds
Started May 28 01:53:01 PM PDT 24
Finished May 28 01:53:30 PM PDT 24
Peak memory 200548 kb
Host smart-61ae56b4-e50e-4030-881d-e47e66dc7e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991162293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1991162293
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.220495179
Short name T758
Test name
Test status
Simulation time 21923345 ps
CPU time 0.56 seconds
Started May 28 01:49:40 PM PDT 24
Finished May 28 01:49:42 PM PDT 24
Peak memory 195908 kb
Host smart-3dcfc4b9-a77c-4533-8203-4139a158bcb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220495179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.220495179
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1266669732
Short name T831
Test name
Test status
Simulation time 140059312027 ps
CPU time 70.67 seconds
Started May 28 01:49:46 PM PDT 24
Finished May 28 01:50:59 PM PDT 24
Peak memory 200448 kb
Host smart-f897a2a7-1089-4b83-8fc2-8a443d9d8544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266669732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1266669732
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.4282519968
Short name T788
Test name
Test status
Simulation time 71571716525 ps
CPU time 22.06 seconds
Started May 28 01:49:38 PM PDT 24
Finished May 28 01:50:03 PM PDT 24
Peak memory 200512 kb
Host smart-1bc575e6-374d-4198-a582-c8b70f942b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282519968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.4282519968
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2906800387
Short name T586
Test name
Test status
Simulation time 24562099050 ps
CPU time 59.01 seconds
Started May 28 01:49:40 PM PDT 24
Finished May 28 01:50:41 PM PDT 24
Peak memory 200424 kb
Host smart-0119a9be-0bee-45b5-9153-6ae3ed49a33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906800387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2906800387
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.457787592
Short name T642
Test name
Test status
Simulation time 32542842342 ps
CPU time 31.81 seconds
Started May 28 01:49:40 PM PDT 24
Finished May 28 01:50:13 PM PDT 24
Peak memory 198912 kb
Host smart-8c67117a-d5a0-4ad9-8350-0811fdd82c46
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457787592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.457787592
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1841831291
Short name T702
Test name
Test status
Simulation time 39845343883 ps
CPU time 158.63 seconds
Started May 28 01:49:40 PM PDT 24
Finished May 28 01:52:21 PM PDT 24
Peak memory 200568 kb
Host smart-66f47dd3-e0cf-428d-bc49-efe05b15b482
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1841831291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1841831291
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.4270554165
Short name T687
Test name
Test status
Simulation time 2599261257 ps
CPU time 2.86 seconds
Started May 28 01:49:38 PM PDT 24
Finished May 28 01:49:43 PM PDT 24
Peak memory 196316 kb
Host smart-a7266855-3c8d-4528-9782-40792fbc2b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270554165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.4270554165
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1895796626
Short name T1116
Test name
Test status
Simulation time 78189968096 ps
CPU time 36.34 seconds
Started May 28 01:49:46 PM PDT 24
Finished May 28 01:50:25 PM PDT 24
Peak memory 200588 kb
Host smart-abe49e29-ade0-4602-9d8f-fbefdba78561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895796626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1895796626
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1001573040
Short name T955
Test name
Test status
Simulation time 21739406275 ps
CPU time 646.77 seconds
Started May 28 01:49:46 PM PDT 24
Finished May 28 02:00:35 PM PDT 24
Peak memory 200540 kb
Host smart-fa329c08-c60c-45d2-8717-fc770b2ab2b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1001573040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1001573040
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3486354601
Short name T679
Test name
Test status
Simulation time 3181573734 ps
CPU time 22.7 seconds
Started May 28 01:49:40 PM PDT 24
Finished May 28 01:50:04 PM PDT 24
Peak memory 198140 kb
Host smart-83259205-7614-4d4a-9e67-fe4471a2bffb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3486354601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3486354601
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1015223290
Short name T411
Test name
Test status
Simulation time 25505740556 ps
CPU time 11.84 seconds
Started May 28 01:49:42 PM PDT 24
Finished May 28 01:49:56 PM PDT 24
Peak memory 200256 kb
Host smart-5c386031-ed03-495a-ae0c-eed6f08b4671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015223290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1015223290
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2894015621
Short name T1117
Test name
Test status
Simulation time 53085170640 ps
CPU time 85.76 seconds
Started May 28 01:49:42 PM PDT 24
Finished May 28 01:51:10 PM PDT 24
Peak memory 196512 kb
Host smart-017ab2b2-4dd4-4e9a-a07f-f2e182786432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894015621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2894015621
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3719655407
Short name T361
Test name
Test status
Simulation time 268782817 ps
CPU time 2.17 seconds
Started May 28 01:49:38 PM PDT 24
Finished May 28 01:49:42 PM PDT 24
Peak memory 198808 kb
Host smart-7c3ecbf8-f25c-4eab-9b61-783ffe6a04ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719655407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3719655407
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1899671884
Short name T543
Test name
Test status
Simulation time 405847751417 ps
CPU time 132.99 seconds
Started May 28 01:49:40 PM PDT 24
Finished May 28 01:51:55 PM PDT 24
Peak memory 200596 kb
Host smart-5aea2da7-fe58-4041-9794-a985fa1e4a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899671884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1899671884
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1339937783
Short name T929
Test name
Test status
Simulation time 216417635658 ps
CPU time 287.38 seconds
Started May 28 01:49:46 PM PDT 24
Finished May 28 01:54:36 PM PDT 24
Peak memory 216916 kb
Host smart-0a7a5a8c-0d68-478d-a033-12dddd35e612
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339937783 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1339937783
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2224422830
Short name T973
Test name
Test status
Simulation time 1766039711 ps
CPU time 1.69 seconds
Started May 28 01:49:42 PM PDT 24
Finished May 28 01:49:46 PM PDT 24
Peak memory 199236 kb
Host smart-a725d069-ab6a-4603-a99a-f93a3a84ccd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224422830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2224422830
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1397822886
Short name T500
Test name
Test status
Simulation time 79600051520 ps
CPU time 130.32 seconds
Started May 28 01:49:40 PM PDT 24
Finished May 28 01:51:52 PM PDT 24
Peak memory 200536 kb
Host smart-47a49ac8-ab2d-4624-8147-733e51144e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397822886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1397822886
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3291792901
Short name T198
Test name
Test status
Simulation time 231339696296 ps
CPU time 94.47 seconds
Started May 28 01:53:02 PM PDT 24
Finished May 28 01:54:38 PM PDT 24
Peak memory 200520 kb
Host smart-a350e943-2e01-4aa3-ad99-f790cc49f248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291792901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3291792901
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.4109518178
Short name T47
Test name
Test status
Simulation time 22738971941 ps
CPU time 24.05 seconds
Started May 28 01:53:00 PM PDT 24
Finished May 28 01:53:26 PM PDT 24
Peak memory 200488 kb
Host smart-a7993fa7-82c9-4186-ae6a-b77d8d7e1199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109518178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4109518178
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.4088750156
Short name T344
Test name
Test status
Simulation time 138909964220 ps
CPU time 457.35 seconds
Started May 28 01:53:02 PM PDT 24
Finished May 28 02:00:42 PM PDT 24
Peak memory 200472 kb
Host smart-2dd6705d-823f-4c73-b446-fb7b6751fc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088750156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.4088750156
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.442648599
Short name T1179
Test name
Test status
Simulation time 9389011543 ps
CPU time 14.5 seconds
Started May 28 01:53:01 PM PDT 24
Finished May 28 01:53:18 PM PDT 24
Peak memory 200464 kb
Host smart-0b762841-1528-4cca-abbc-458ad97db5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442648599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.442648599
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2789523971
Short name T1176
Test name
Test status
Simulation time 6472822551 ps
CPU time 12.04 seconds
Started May 28 01:53:00 PM PDT 24
Finished May 28 01:53:14 PM PDT 24
Peak memory 200496 kb
Host smart-cd2f6220-2117-4df1-ac10-76973c8821c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789523971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2789523971
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3429132269
Short name T704
Test name
Test status
Simulation time 155418429939 ps
CPU time 50.62 seconds
Started May 28 01:53:02 PM PDT 24
Finished May 28 01:53:55 PM PDT 24
Peak memory 200444 kb
Host smart-eafd37be-5c33-42c2-870a-dd0badca55ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429132269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3429132269
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1816434608
Short name T326
Test name
Test status
Simulation time 38991653665 ps
CPU time 36.12 seconds
Started May 28 01:53:01 PM PDT 24
Finished May 28 01:53:39 PM PDT 24
Peak memory 200596 kb
Host smart-a4c1aa9c-1865-4dfc-89e3-736e0e24de64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816434608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1816434608
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3741029014
Short name T1054
Test name
Test status
Simulation time 109547773121 ps
CPU time 33.01 seconds
Started May 28 01:53:02 PM PDT 24
Finished May 28 01:53:37 PM PDT 24
Peak memory 200548 kb
Host smart-f828f807-105b-4133-899c-19370486d27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741029014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3741029014
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1329082351
Short name T1157
Test name
Test status
Simulation time 138924803042 ps
CPU time 98.69 seconds
Started May 28 01:53:03 PM PDT 24
Finished May 28 01:54:44 PM PDT 24
Peak memory 200548 kb
Host smart-fd5fe860-9e41-4270-b78c-66877150bc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329082351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1329082351
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1031260774
Short name T482
Test name
Test status
Simulation time 17427424 ps
CPU time 0.6 seconds
Started May 28 01:49:55 PM PDT 24
Finished May 28 01:49:58 PM PDT 24
Peak memory 195912 kb
Host smart-416e1201-a298-46c3-a9ed-be7f259c076e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031260774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1031260774
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3939862172
Short name T672
Test name
Test status
Simulation time 18669233588 ps
CPU time 27.77 seconds
Started May 28 01:49:56 PM PDT 24
Finished May 28 01:50:25 PM PDT 24
Peak memory 200524 kb
Host smart-187b3c21-1747-42fa-85c2-2352e637a9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939862172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3939862172
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2154273831
Short name T189
Test name
Test status
Simulation time 10915939194 ps
CPU time 18.48 seconds
Started May 28 01:49:52 PM PDT 24
Finished May 28 01:50:12 PM PDT 24
Peak memory 200524 kb
Host smart-ecabf768-569e-4219-8447-ac04549b4bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154273831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2154273831
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.4204884179
Short name T202
Test name
Test status
Simulation time 62004817189 ps
CPU time 49.39 seconds
Started May 28 01:49:56 PM PDT 24
Finished May 28 01:50:47 PM PDT 24
Peak memory 200568 kb
Host smart-c098fa92-d444-4ef1-9ffd-60e6f240b895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204884179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.4204884179
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2500477213
Short name T119
Test name
Test status
Simulation time 53113923934 ps
CPU time 92.04 seconds
Started May 28 01:49:54 PM PDT 24
Finished May 28 01:51:28 PM PDT 24
Peak memory 199488 kb
Host smart-1be40eea-81ef-4156-b184-6393a18425b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500477213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2500477213
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2290624004
Short name T407
Test name
Test status
Simulation time 91509934115 ps
CPU time 303.85 seconds
Started May 28 01:49:54 PM PDT 24
Finished May 28 01:54:59 PM PDT 24
Peak memory 200456 kb
Host smart-80ddc918-dcd5-4c2d-a0b3-0e159ceadc8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2290624004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2290624004
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1938697466
Short name T376
Test name
Test status
Simulation time 1699980662 ps
CPU time 1.42 seconds
Started May 28 01:49:55 PM PDT 24
Finished May 28 01:49:58 PM PDT 24
Peak memory 196488 kb
Host smart-e6f7d8ad-f788-4a29-8c8f-be285b25d0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938697466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1938697466
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.771479204
Short name T742
Test name
Test status
Simulation time 47595754456 ps
CPU time 33.65 seconds
Started May 28 01:49:54 PM PDT 24
Finished May 28 01:50:30 PM PDT 24
Peak memory 199940 kb
Host smart-4b8b2742-2e5d-4a92-bb37-183da49a548d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771479204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.771479204
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.4182298563
Short name T925
Test name
Test status
Simulation time 11469909218 ps
CPU time 133.1 seconds
Started May 28 01:49:54 PM PDT 24
Finished May 28 01:52:08 PM PDT 24
Peak memory 200456 kb
Host smart-21803eeb-cc01-48ef-9be0-1f02a29ef2ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182298563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.4182298563
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1767905174
Short name T584
Test name
Test status
Simulation time 4844191148 ps
CPU time 20.59 seconds
Started May 28 01:49:54 PM PDT 24
Finished May 28 01:50:16 PM PDT 24
Peak memory 199476 kb
Host smart-d2749e46-ac3d-4fd3-8022-630bed3e691c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767905174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1767905174
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3431451925
Short name T314
Test name
Test status
Simulation time 123841330576 ps
CPU time 31.66 seconds
Started May 28 01:49:54 PM PDT 24
Finished May 28 01:50:26 PM PDT 24
Peak memory 198876 kb
Host smart-b7e0e654-4b59-4b99-8366-712e2aeeb0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431451925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3431451925
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.830508235
Short name T773
Test name
Test status
Simulation time 3577440832 ps
CPU time 2.18 seconds
Started May 28 01:49:53 PM PDT 24
Finished May 28 01:49:56 PM PDT 24
Peak memory 196320 kb
Host smart-5ce0c0e2-af74-43ae-8cd9-62de2aa2b9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830508235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.830508235
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2977636245
Short name T318
Test name
Test status
Simulation time 661202746 ps
CPU time 3.04 seconds
Started May 28 01:49:46 PM PDT 24
Finished May 28 01:49:51 PM PDT 24
Peak memory 199012 kb
Host smart-85fec8c9-d73e-4892-b707-785b89419c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977636245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2977636245
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.4059215477
Short name T1052
Test name
Test status
Simulation time 61444997927 ps
CPU time 25.56 seconds
Started May 28 01:49:55 PM PDT 24
Finished May 28 01:50:22 PM PDT 24
Peak memory 200496 kb
Host smart-ca14b926-38ce-4668-8e22-de1f29e57ac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059215477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4059215477
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1924088178
Short name T110
Test name
Test status
Simulation time 43459306257 ps
CPU time 62.09 seconds
Started May 28 01:49:56 PM PDT 24
Finished May 28 01:51:00 PM PDT 24
Peak memory 216960 kb
Host smart-82f5ae17-98c2-4bc8-a9ca-8f561e258746
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924088178 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1924088178
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1615391251
Short name T705
Test name
Test status
Simulation time 7054306802 ps
CPU time 14.68 seconds
Started May 28 01:49:55 PM PDT 24
Finished May 28 01:50:12 PM PDT 24
Peak memory 199884 kb
Host smart-c70780c5-a1de-4411-b35c-9568273ec518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615391251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1615391251
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1081799028
Short name T686
Test name
Test status
Simulation time 132691624850 ps
CPU time 42.98 seconds
Started May 28 01:49:46 PM PDT 24
Finished May 28 01:50:31 PM PDT 24
Peak memory 200540 kb
Host smart-9c86b0f6-dfbd-4f54-880b-9edf1750f211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081799028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1081799028
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1406524022
Short name T845
Test name
Test status
Simulation time 72512789385 ps
CPU time 33.79 seconds
Started May 28 01:53:00 PM PDT 24
Finished May 28 01:53:36 PM PDT 24
Peak memory 200456 kb
Host smart-6057e9dd-fda7-4415-8ca6-3dab8f60b359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406524022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1406524022
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3479185766
Short name T667
Test name
Test status
Simulation time 127925996424 ps
CPU time 229.36 seconds
Started May 28 01:53:03 PM PDT 24
Finished May 28 01:56:55 PM PDT 24
Peak memory 200516 kb
Host smart-a4aea610-815b-4035-8488-ee4c0b8e7aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479185766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3479185766
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.4138246216
Short name T1134
Test name
Test status
Simulation time 44561296500 ps
CPU time 77.55 seconds
Started May 28 01:53:01 PM PDT 24
Finished May 28 01:54:21 PM PDT 24
Peak memory 200456 kb
Host smart-3956b016-b958-4e27-90bd-798c5354f9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138246216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.4138246216
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2436637429
Short name T1138
Test name
Test status
Simulation time 33794981339 ps
CPU time 30.73 seconds
Started May 28 01:53:02 PM PDT 24
Finished May 28 01:53:35 PM PDT 24
Peak memory 200516 kb
Host smart-9aac8648-9b5f-4c3c-92ba-e06ab31c92a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436637429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2436637429
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.746053180
Short name T489
Test name
Test status
Simulation time 14354270533 ps
CPU time 27.17 seconds
Started May 28 01:53:02 PM PDT 24
Finished May 28 01:53:31 PM PDT 24
Peak memory 200472 kb
Host smart-e1d7a008-7396-4f0f-8852-360124c363a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746053180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.746053180
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3715657403
Short name T209
Test name
Test status
Simulation time 96714905872 ps
CPU time 164.94 seconds
Started May 28 01:53:00 PM PDT 24
Finished May 28 01:55:48 PM PDT 24
Peak memory 200548 kb
Host smart-d0bf8f86-a176-4e5f-a104-d590e4b7c700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715657403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3715657403
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1298619739
Short name T521
Test name
Test status
Simulation time 99705788934 ps
CPU time 45.35 seconds
Started May 28 01:53:06 PM PDT 24
Finished May 28 01:53:53 PM PDT 24
Peak memory 200520 kb
Host smart-bec8f27b-a16b-4f8a-9a7c-286846112cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298619739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1298619739
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1108700044
Short name T904
Test name
Test status
Simulation time 36123479179 ps
CPU time 37.16 seconds
Started May 28 01:53:02 PM PDT 24
Finished May 28 01:53:41 PM PDT 24
Peak memory 200548 kb
Host smart-04cdbc21-5a09-4c2e-a128-9d3009fcc82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108700044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1108700044
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2551379364
Short name T629
Test name
Test status
Simulation time 57958458708 ps
CPU time 49.01 seconds
Started May 28 01:53:01 PM PDT 24
Finished May 28 01:53:52 PM PDT 24
Peak memory 200540 kb
Host smart-83275f48-9d0c-40bd-b00f-44a990377717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551379364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2551379364
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2239829981
Short name T203
Test name
Test status
Simulation time 90818656159 ps
CPU time 40.96 seconds
Started May 28 01:53:03 PM PDT 24
Finished May 28 01:53:46 PM PDT 24
Peak memory 200428 kb
Host smart-a5477a95-be8c-4ef0-a497-13323dea6780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239829981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2239829981
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1989320004
Short name T801
Test name
Test status
Simulation time 14015686 ps
CPU time 0.56 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:17 PM PDT 24
Peak memory 195360 kb
Host smart-01733c06-7b74-4d99-ada1-d17d1382d941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989320004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1989320004
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1297483451
Short name T271
Test name
Test status
Simulation time 79381508739 ps
CPU time 35.33 seconds
Started May 28 01:49:55 PM PDT 24
Finished May 28 01:50:32 PM PDT 24
Peak memory 200544 kb
Host smart-b79dad01-7956-4c2f-bbe6-a4e190a2f674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297483451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1297483451
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2567964732
Short name T891
Test name
Test status
Simulation time 15581180338 ps
CPU time 14.75 seconds
Started May 28 01:49:55 PM PDT 24
Finished May 28 01:50:12 PM PDT 24
Peak memory 200528 kb
Host smart-0d449252-254f-45eb-9ca2-dc98742799ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567964732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2567964732
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1801360744
Short name T745
Test name
Test status
Simulation time 14654061599 ps
CPU time 12.24 seconds
Started May 28 01:49:56 PM PDT 24
Finished May 28 01:50:10 PM PDT 24
Peak memory 200480 kb
Host smart-02cd77d7-c212-4c2d-b257-5d86b6c48557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801360744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1801360744
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.4211654537
Short name T408
Test name
Test status
Simulation time 50501527759 ps
CPU time 79.69 seconds
Started May 28 01:49:57 PM PDT 24
Finished May 28 01:51:18 PM PDT 24
Peak memory 199768 kb
Host smart-2679e834-7cf5-4f28-ba2d-4954bc85a25b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211654537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.4211654537
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.397494819
Short name T954
Test name
Test status
Simulation time 65975705230 ps
CPU time 83.62 seconds
Started May 28 01:49:57 PM PDT 24
Finished May 28 01:51:22 PM PDT 24
Peak memory 200556 kb
Host smart-99a3c82c-ff30-4a84-917a-69427323faab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=397494819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.397494819
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2538592466
Short name T806
Test name
Test status
Simulation time 10533394471 ps
CPU time 11.29 seconds
Started May 28 01:49:56 PM PDT 24
Finished May 28 01:50:09 PM PDT 24
Peak memory 199904 kb
Host smart-2ba5a056-cb84-45d0-b500-f66720ac2081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538592466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2538592466
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.286920258
Short name T828
Test name
Test status
Simulation time 64872001968 ps
CPU time 116.65 seconds
Started May 28 01:49:57 PM PDT 24
Finished May 28 01:51:55 PM PDT 24
Peak memory 200768 kb
Host smart-d013903a-b54e-4995-88d9-bca704eb480a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286920258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.286920258
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.4230695100
Short name T1060
Test name
Test status
Simulation time 10776157250 ps
CPU time 147.87 seconds
Started May 28 01:49:56 PM PDT 24
Finished May 28 01:52:25 PM PDT 24
Peak memory 200488 kb
Host smart-f25e32eb-c7f7-413f-9840-c7433b18ccee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4230695100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.4230695100
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.146969258
Short name T389
Test name
Test status
Simulation time 2018956244 ps
CPU time 2.92 seconds
Started May 28 01:49:57 PM PDT 24
Finished May 28 01:50:01 PM PDT 24
Peak memory 198460 kb
Host smart-6d4d1b40-b2d5-480d-a727-ff2c32057f22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=146969258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.146969258
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.4117271375
Short name T169
Test name
Test status
Simulation time 82542409818 ps
CPU time 64.25 seconds
Started May 28 01:49:55 PM PDT 24
Finished May 28 01:51:02 PM PDT 24
Peak memory 200524 kb
Host smart-17718cda-bdf1-449a-98ad-3dadb357d228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117271375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.4117271375
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.192030390
Short name T918
Test name
Test status
Simulation time 2156963533 ps
CPU time 1.61 seconds
Started May 28 01:49:54 PM PDT 24
Finished May 28 01:49:57 PM PDT 24
Peak memory 196232 kb
Host smart-134150dd-2771-4e24-93d2-96db8408b857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192030390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.192030390
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2935541997
Short name T994
Test name
Test status
Simulation time 898047794 ps
CPU time 2.55 seconds
Started May 28 01:49:55 PM PDT 24
Finished May 28 01:49:59 PM PDT 24
Peak memory 199236 kb
Host smart-7159d6f3-0774-40d4-93c9-b89a73994248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935541997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2935541997
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3401131312
Short name T476
Test name
Test status
Simulation time 334686515210 ps
CPU time 219.85 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:53:57 PM PDT 24
Peak memory 200476 kb
Host smart-47767e43-d91f-4c2e-b3fc-7e489fee3993
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401131312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3401131312
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2039014280
Short name T970
Test name
Test status
Simulation time 115065395110 ps
CPU time 761.33 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 02:02:59 PM PDT 24
Peak memory 217272 kb
Host smart-ed28072b-f143-4ee8-b08c-b18cb64a60a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039014280 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2039014280
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1196133162
Short name T1119
Test name
Test status
Simulation time 6810858495 ps
CPU time 24.86 seconds
Started May 28 01:49:55 PM PDT 24
Finished May 28 01:50:22 PM PDT 24
Peak memory 199756 kb
Host smart-fb1e37a7-0bbd-4e96-8860-3f3e05e2dc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196133162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1196133162
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2179551174
Short name T343
Test name
Test status
Simulation time 75267516489 ps
CPU time 164.23 seconds
Started May 28 01:49:55 PM PDT 24
Finished May 28 01:52:41 PM PDT 24
Peak memory 200536 kb
Host smart-940ce54b-6b9a-4d60-b88b-4293a22b98d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179551174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2179551174
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.4119952753
Short name T981
Test name
Test status
Simulation time 12821841158 ps
CPU time 22.2 seconds
Started May 28 01:53:04 PM PDT 24
Finished May 28 01:53:28 PM PDT 24
Peak memory 200548 kb
Host smart-b7a27261-6b83-405b-b786-70f0917f6ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119952753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.4119952753
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2989296129
Short name T393
Test name
Test status
Simulation time 37930380905 ps
CPU time 36.75 seconds
Started May 28 01:53:03 PM PDT 24
Finished May 28 01:53:43 PM PDT 24
Peak memory 200456 kb
Host smart-43916f09-7c10-46b0-9551-9bc128fce330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989296129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2989296129
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2406651914
Short name T935
Test name
Test status
Simulation time 33712479524 ps
CPU time 38.37 seconds
Started May 28 01:53:04 PM PDT 24
Finished May 28 01:53:45 PM PDT 24
Peak memory 200488 kb
Host smart-e0919ff5-c045-411b-9863-5f08379a53f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406651914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2406651914
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1580641068
Short name T1007
Test name
Test status
Simulation time 199730366850 ps
CPU time 32.4 seconds
Started May 28 01:53:05 PM PDT 24
Finished May 28 01:53:39 PM PDT 24
Peak memory 200164 kb
Host smart-6cc8cc7b-9851-4694-b3a6-50b3b2d5de5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580641068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1580641068
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3976130766
Short name T611
Test name
Test status
Simulation time 27371379262 ps
CPU time 31.05 seconds
Started May 28 01:53:02 PM PDT 24
Finished May 28 01:53:36 PM PDT 24
Peak memory 200580 kb
Host smart-dff5937f-b24b-4684-ae20-5a34c960a5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976130766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3976130766
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1168107334
Short name T876
Test name
Test status
Simulation time 23947571289 ps
CPU time 18.97 seconds
Started May 28 01:53:05 PM PDT 24
Finished May 28 01:53:26 PM PDT 24
Peak memory 200456 kb
Host smart-2ee97094-fd1f-4e71-a2fe-b20163d1f933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168107334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1168107334
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.720499837
Short name T388
Test name
Test status
Simulation time 32641759518 ps
CPU time 61.31 seconds
Started May 28 01:53:04 PM PDT 24
Finished May 28 01:54:08 PM PDT 24
Peak memory 200476 kb
Host smart-add64336-1f86-4d1f-a0e5-55a72d526fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720499837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.720499837
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2184978788
Short name T821
Test name
Test status
Simulation time 48110324482 ps
CPU time 18.92 seconds
Started May 28 01:53:19 PM PDT 24
Finished May 28 01:53:41 PM PDT 24
Peak memory 200460 kb
Host smart-97126e61-8944-4abd-9a88-c2b7adf87585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184978788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2184978788
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.976236195
Short name T977
Test name
Test status
Simulation time 52049073 ps
CPU time 0.55 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:18 PM PDT 24
Peak memory 195908 kb
Host smart-eedcea74-428b-4d1a-970d-2b8aca817029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976236195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.976236195
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.4109508885
Short name T166
Test name
Test status
Simulation time 121606648140 ps
CPU time 99.75 seconds
Started May 28 01:50:13 PM PDT 24
Finished May 28 01:51:58 PM PDT 24
Peak memory 200440 kb
Host smart-98ff0ebb-9c78-42ad-ad1e-f47a7792a7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109508885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.4109508885
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1994180313
Short name T593
Test name
Test status
Simulation time 149831534017 ps
CPU time 358.78 seconds
Started May 28 01:50:13 PM PDT 24
Finished May 28 01:56:17 PM PDT 24
Peak memory 200516 kb
Host smart-49e616af-e986-4e56-8112-2f9502c8e613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994180313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1994180313
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1048990354
Short name T887
Test name
Test status
Simulation time 21194034795 ps
CPU time 34.65 seconds
Started May 28 01:50:10 PM PDT 24
Finished May 28 01:50:47 PM PDT 24
Peak memory 198032 kb
Host smart-39c11e5b-db86-4cc4-866e-b25bdb01d6ac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048990354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1048990354
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3429013818
Short name T591
Test name
Test status
Simulation time 71844322058 ps
CPU time 559.64 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:59:36 PM PDT 24
Peak memory 200512 kb
Host smart-8eaab6d8-039c-4133-9336-9b878d62f613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3429013818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3429013818
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2625792330
Short name T1043
Test name
Test status
Simulation time 4872953970 ps
CPU time 3 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:50:18 PM PDT 24
Peak memory 198324 kb
Host smart-95b8aaa9-6910-45e2-a6e9-aef8eec6b2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625792330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2625792330
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3818190449
Short name T721
Test name
Test status
Simulation time 7680386744 ps
CPU time 13.63 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:30 PM PDT 24
Peak memory 200764 kb
Host smart-4c960464-0f5e-4bb1-852c-b92b257b22b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818190449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3818190449
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3958402576
Short name T1161
Test name
Test status
Simulation time 7044857423 ps
CPU time 212.98 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:53:50 PM PDT 24
Peak memory 200512 kb
Host smart-86100ea9-513e-4823-9c2e-ab0db444b6d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3958402576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3958402576
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3488359511
Short name T427
Test name
Test status
Simulation time 6084061132 ps
CPU time 25.49 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:42 PM PDT 24
Peak memory 199908 kb
Host smart-469c0277-9a17-4c05-b640-8a29f84f924a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488359511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3488359511
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3235707915
Short name T113
Test name
Test status
Simulation time 41615567856 ps
CPU time 63.01 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:51:20 PM PDT 24
Peak memory 200456 kb
Host smart-e11bdc11-a2c2-449f-9902-46517213317b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235707915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3235707915
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3840868802
Short name T1104
Test name
Test status
Simulation time 42475817226 ps
CPU time 69.37 seconds
Started May 28 01:50:10 PM PDT 24
Finished May 28 01:51:21 PM PDT 24
Peak memory 196528 kb
Host smart-44b25ba0-e632-4a02-a307-71ec4f84bf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840868802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3840868802
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3074581045
Short name T784
Test name
Test status
Simulation time 625338192 ps
CPU time 2.85 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:20 PM PDT 24
Peak memory 200188 kb
Host smart-8b4cf6d5-c66d-4722-8772-fd33c1ff6931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074581045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3074581045
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3033678228
Short name T1003
Test name
Test status
Simulation time 469768122388 ps
CPU time 275.52 seconds
Started May 28 01:50:09 PM PDT 24
Finished May 28 01:54:47 PM PDT 24
Peak memory 200540 kb
Host smart-a375e579-b146-4882-8fac-210247b2b912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033678228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3033678228
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2133502807
Short name T1011
Test name
Test status
Simulation time 46142916571 ps
CPU time 283.21 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:54:58 PM PDT 24
Peak memory 214232 kb
Host smart-0392746b-4fd0-45aa-ac02-11ddfb5b732a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133502807 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2133502807
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3827181086
Short name T377
Test name
Test status
Simulation time 576897738 ps
CPU time 2.16 seconds
Started May 28 01:50:10 PM PDT 24
Finished May 28 01:50:16 PM PDT 24
Peak memory 198860 kb
Host smart-fa6f4d19-2e17-40df-a2c9-cd1eff103ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827181086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3827181086
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.62763678
Short name T130
Test name
Test status
Simulation time 25294769521 ps
CPU time 12.08 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:50:27 PM PDT 24
Peak memory 198536 kb
Host smart-b8a77f8c-68c0-4a61-9498-fb4a053e4cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62763678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.62763678
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1989134861
Short name T234
Test name
Test status
Simulation time 200106322981 ps
CPU time 39.67 seconds
Started May 28 01:53:16 PM PDT 24
Finished May 28 01:53:57 PM PDT 24
Peak memory 200548 kb
Host smart-87b86724-0dd9-4164-88a6-d31ba75f7d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989134861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1989134861
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3045899206
Short name T1097
Test name
Test status
Simulation time 20131710724 ps
CPU time 33.86 seconds
Started May 28 01:53:16 PM PDT 24
Finished May 28 01:53:52 PM PDT 24
Peak memory 200460 kb
Host smart-827f286e-0ebe-4754-9dd5-6b5096f50c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045899206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3045899206
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3387566874
Short name T290
Test name
Test status
Simulation time 44544566734 ps
CPU time 22.44 seconds
Started May 28 01:53:14 PM PDT 24
Finished May 28 01:53:38 PM PDT 24
Peak memory 200524 kb
Host smart-ca4e035f-26a5-49ca-91a6-d70d88ef5e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387566874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3387566874
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1211123456
Short name T1082
Test name
Test status
Simulation time 49259932807 ps
CPU time 67.95 seconds
Started May 28 01:53:20 PM PDT 24
Finished May 28 01:54:31 PM PDT 24
Peak memory 200528 kb
Host smart-516e9c55-e2e7-4da9-8c0b-f75f44b4ed81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211123456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1211123456
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1716957781
Short name T453
Test name
Test status
Simulation time 179151518769 ps
CPU time 279.13 seconds
Started May 28 01:53:17 PM PDT 24
Finished May 28 01:57:58 PM PDT 24
Peak memory 200568 kb
Host smart-6b0e838c-f219-451f-bc0a-cdd27eddbb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716957781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1716957781
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.322253144
Short name T809
Test name
Test status
Simulation time 15525049757 ps
CPU time 33.97 seconds
Started May 28 01:53:15 PM PDT 24
Finished May 28 01:53:51 PM PDT 24
Peak memory 200536 kb
Host smart-15fd5742-a96e-425c-ba0a-36cd8b3badff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322253144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.322253144
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.978387682
Short name T995
Test name
Test status
Simulation time 68215832679 ps
CPU time 112.36 seconds
Started May 28 01:53:16 PM PDT 24
Finished May 28 01:55:11 PM PDT 24
Peak memory 200500 kb
Host smart-52b652d4-7de3-44b7-a417-b39f8b353035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978387682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.978387682
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2534120557
Short name T239
Test name
Test status
Simulation time 30128757453 ps
CPU time 19.03 seconds
Started May 28 01:53:17 PM PDT 24
Finished May 28 01:53:38 PM PDT 24
Peak memory 200756 kb
Host smart-13b9b5a9-6e29-47f0-93de-0013f5bf31e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534120557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2534120557
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3441118622
Short name T1092
Test name
Test status
Simulation time 42605211551 ps
CPU time 14.37 seconds
Started May 28 01:53:21 PM PDT 24
Finished May 28 01:53:39 PM PDT 24
Peak memory 200404 kb
Host smart-48437a53-2156-4c08-98d2-34ff0236b931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441118622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3441118622
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1328527782
Short name T207
Test name
Test status
Simulation time 119741999621 ps
CPU time 126.66 seconds
Started May 28 01:53:16 PM PDT 24
Finished May 28 01:55:25 PM PDT 24
Peak memory 200436 kb
Host smart-63e10f96-b2f6-4401-bdbd-bbb1f52b861e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328527782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1328527782
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3549362947
Short name T1147
Test name
Test status
Simulation time 39934828 ps
CPU time 0.55 seconds
Started May 28 01:50:14 PM PDT 24
Finished May 28 01:50:19 PM PDT 24
Peak memory 195884 kb
Host smart-e378b166-c30c-44b5-a091-3e1dc2533146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549362947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3549362947
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2608090185
Short name T131
Test name
Test status
Simulation time 44770941563 ps
CPU time 75.56 seconds
Started May 28 01:50:13 PM PDT 24
Finished May 28 01:51:34 PM PDT 24
Peak memory 200520 kb
Host smart-07d27ac7-61b2-48b4-b1df-7cedebdb71c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608090185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2608090185
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1238703460
Short name T1101
Test name
Test status
Simulation time 76223247223 ps
CPU time 155.98 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:52:51 PM PDT 24
Peak memory 200464 kb
Host smart-81716f48-eab4-46f0-9423-6cde34280174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238703460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1238703460
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.118757101
Short name T576
Test name
Test status
Simulation time 30451286292 ps
CPU time 15.73 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:50:32 PM PDT 24
Peak memory 200496 kb
Host smart-f743e256-6dc3-4ec2-bffd-7353ff3e7d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118757101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.118757101
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1308352007
Short name T1074
Test name
Test status
Simulation time 61278968555 ps
CPU time 100.65 seconds
Started May 28 01:50:13 PM PDT 24
Finished May 28 01:51:59 PM PDT 24
Peak memory 200332 kb
Host smart-ea539ab1-b259-4005-ae58-4c804fed1179
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308352007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1308352007
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1333184649
Short name T1125
Test name
Test status
Simulation time 86975092363 ps
CPU time 349.78 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:56:08 PM PDT 24
Peak memory 200192 kb
Host smart-06562f3c-cb84-49a8-ac1b-871f94413f3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1333184649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1333184649
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3895190639
Short name T1174
Test name
Test status
Simulation time 1631691367 ps
CPU time 3.49 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:50:19 PM PDT 24
Peak memory 199516 kb
Host smart-66d5a046-2995-4878-a92e-03b117148042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895190639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3895190639
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3857086931
Short name T698
Test name
Test status
Simulation time 178183808129 ps
CPU time 95.37 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:51:50 PM PDT 24
Peak memory 200740 kb
Host smart-1f0e8cb7-ff95-4083-8775-15141213b767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857086931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3857086931
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3051564354
Short name T592
Test name
Test status
Simulation time 18644816127 ps
CPU time 310.76 seconds
Started May 28 01:50:10 PM PDT 24
Finished May 28 01:55:24 PM PDT 24
Peak memory 200528 kb
Host smart-e8eccdcb-2027-466e-b813-c757f9cc1b44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3051564354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3051564354
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3719837633
Short name T678
Test name
Test status
Simulation time 6134516249 ps
CPU time 29.31 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:50:44 PM PDT 24
Peak memory 199612 kb
Host smart-2f0f8b44-0153-4c67-a974-e6ab98d63964
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3719837633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3719837633
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2371730214
Short name T1010
Test name
Test status
Simulation time 228759530174 ps
CPU time 199.69 seconds
Started May 28 01:50:09 PM PDT 24
Finished May 28 01:53:30 PM PDT 24
Peak memory 200368 kb
Host smart-febb9091-d132-4be1-b0dd-75926fcaed4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371730214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2371730214
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1706513466
Short name T624
Test name
Test status
Simulation time 2201259217 ps
CPU time 3.81 seconds
Started May 28 01:50:13 PM PDT 24
Finished May 28 01:50:22 PM PDT 24
Peak memory 196228 kb
Host smart-fedfda98-5c24-430d-b622-ef5dea233c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706513466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1706513466
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1629196349
Short name T2
Test name
Test status
Simulation time 687292391 ps
CPU time 3.88 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:50:19 PM PDT 24
Peak memory 199240 kb
Host smart-8ff630ff-b79d-4711-9e49-f4792613902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629196349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1629196349
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.1792859111
Short name T912
Test name
Test status
Simulation time 77197762321 ps
CPU time 31.33 seconds
Started May 28 01:50:10 PM PDT 24
Finished May 28 01:50:44 PM PDT 24
Peak memory 200484 kb
Host smart-889b9b2c-a026-4a9e-99c5-f5add6869a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792859111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1792859111
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.621273672
Short name T152
Test name
Test status
Simulation time 99657307663 ps
CPU time 2081.17 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 02:24:58 PM PDT 24
Peak memory 227832 kb
Host smart-c4a70db3-b3ad-4b0f-87b2-3cd59a453e19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621273672 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.621273672
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.4291258516
Short name T1070
Test name
Test status
Simulation time 6405830002 ps
CPU time 12.02 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:29 PM PDT 24
Peak memory 200216 kb
Host smart-bf645e00-2a9c-421c-9741-b3317b6d0764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291258516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4291258516
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3433098566
Short name T580
Test name
Test status
Simulation time 7805651723 ps
CPU time 14.4 seconds
Started May 28 01:50:13 PM PDT 24
Finished May 28 01:50:33 PM PDT 24
Peak memory 198804 kb
Host smart-94f214aa-5f78-479f-a75b-7c50bdad75b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433098566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3433098566
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1101488031
Short name T55
Test name
Test status
Simulation time 15839179489 ps
CPU time 26.86 seconds
Started May 28 01:53:14 PM PDT 24
Finished May 28 01:53:43 PM PDT 24
Peak memory 200516 kb
Host smart-302c574e-44ad-411e-8891-ff9ce49d0e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101488031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1101488031
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.380718296
Short name T364
Test name
Test status
Simulation time 15821121441 ps
CPU time 12.84 seconds
Started May 28 01:53:15 PM PDT 24
Finished May 28 01:53:30 PM PDT 24
Peak memory 200320 kb
Host smart-c4b8dfe5-fbf9-4c14-a71e-cb7c9d2c0cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380718296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.380718296
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1913777340
Short name T245
Test name
Test status
Simulation time 55478077288 ps
CPU time 26.88 seconds
Started May 28 01:53:14 PM PDT 24
Finished May 28 01:53:42 PM PDT 24
Peak memory 200472 kb
Host smart-13b3ed1a-f578-481c-ae32-a1c9df9f754a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913777340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1913777340
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3756183588
Short name T142
Test name
Test status
Simulation time 33755755172 ps
CPU time 66.5 seconds
Started May 28 01:53:17 PM PDT 24
Finished May 28 01:54:26 PM PDT 24
Peak memory 200512 kb
Host smart-22d38dcf-7933-4221-8f30-e183a21b7d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756183588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3756183588
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2820890501
Short name T832
Test name
Test status
Simulation time 39768411477 ps
CPU time 17.25 seconds
Started May 28 01:53:15 PM PDT 24
Finished May 28 01:53:34 PM PDT 24
Peak memory 200256 kb
Host smart-8af14bf3-c3dc-4bc1-aa4c-c21552cf74b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820890501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2820890501
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3417780279
Short name T255
Test name
Test status
Simulation time 67682121974 ps
CPU time 127.55 seconds
Started May 28 01:53:15 PM PDT 24
Finished May 28 01:55:25 PM PDT 24
Peak memory 200592 kb
Host smart-33b3d00a-dcdd-4efd-9bee-123b0b1043c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417780279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3417780279
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2642043976
Short name T157
Test name
Test status
Simulation time 171871761772 ps
CPU time 69.78 seconds
Started May 28 01:53:17 PM PDT 24
Finished May 28 01:54:29 PM PDT 24
Peak memory 200360 kb
Host smart-f2832741-272a-40a3-a02b-f25998c372ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642043976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2642043976
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2957001818
Short name T708
Test name
Test status
Simulation time 40149061 ps
CPU time 0.53 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:18 PM PDT 24
Peak memory 195888 kb
Host smart-324849bc-14fb-4e47-a89a-b30dcb6ea546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957001818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2957001818
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.881968717
Short name T548
Test name
Test status
Simulation time 129060739109 ps
CPU time 276.64 seconds
Started May 28 01:50:10 PM PDT 24
Finished May 28 01:54:51 PM PDT 24
Peak memory 200484 kb
Host smart-02fee93a-5262-429a-8a8d-ef86a70b46f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881968717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.881968717
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1218191450
Short name T798
Test name
Test status
Simulation time 76512559097 ps
CPU time 110.89 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:52:08 PM PDT 24
Peak memory 199924 kb
Host smart-af26a128-b67d-4fdf-ba48-4ed57c1b992b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218191450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1218191450
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1457034040
Short name T917
Test name
Test status
Simulation time 18482986337 ps
CPU time 36.56 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:50:52 PM PDT 24
Peak memory 200496 kb
Host smart-1001b310-c359-448e-9e85-861f02c8277b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457034040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1457034040
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1188548804
Short name T466
Test name
Test status
Simulation time 6252559826 ps
CPU time 3.29 seconds
Started May 28 01:50:10 PM PDT 24
Finished May 28 01:50:16 PM PDT 24
Peak memory 196992 kb
Host smart-70d3f839-cbeb-4516-8ef5-23d0d4ea0b4b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188548804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1188548804
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3219380619
Short name T275
Test name
Test status
Simulation time 52796738280 ps
CPU time 86.96 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:51:43 PM PDT 24
Peak memory 200544 kb
Host smart-94f8c158-0196-4750-81d9-53960ad45605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3219380619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3219380619
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3760656127
Short name T726
Test name
Test status
Simulation time 6996256986 ps
CPU time 6.25 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:23 PM PDT 24
Peak memory 200476 kb
Host smart-df7f2d97-1641-4e12-8b0b-d00108d73159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760656127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3760656127
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.874354804
Short name T399
Test name
Test status
Simulation time 173443407243 ps
CPU time 146.88 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:52:44 PM PDT 24
Peak memory 199832 kb
Host smart-9ec8d788-359a-4824-9270-ebf8d4d4ce87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874354804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.874354804
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1708279763
Short name T1061
Test name
Test status
Simulation time 7614332247 ps
CPU time 81.02 seconds
Started May 28 01:50:04 PM PDT 24
Finished May 28 01:51:26 PM PDT 24
Peak memory 200472 kb
Host smart-a5936f38-8b42-4f12-9a55-b7c001efb301
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1708279763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1708279763
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.2938059706
Short name T353
Test name
Test status
Simulation time 5010207970 ps
CPU time 3.71 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:50:18 PM PDT 24
Peak memory 199584 kb
Host smart-4b4603f1-e56c-43c2-b36a-a14d8c8c0ba0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2938059706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2938059706
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2575051215
Short name T176
Test name
Test status
Simulation time 44448038893 ps
CPU time 34.42 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:50:50 PM PDT 24
Peak memory 200408 kb
Host smart-83293fe7-abc6-4a3b-b183-6fbc4e252537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575051215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2575051215
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.529919542
Short name T957
Test name
Test status
Simulation time 102040574754 ps
CPU time 80.89 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:51:38 PM PDT 24
Peak memory 196252 kb
Host smart-56918b64-f22c-4161-be08-9d471766c05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529919542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.529919542
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3065519712
Short name T749
Test name
Test status
Simulation time 5908038924 ps
CPU time 10.58 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:28 PM PDT 24
Peak memory 199708 kb
Host smart-4e358ac9-43ed-4c32-be67-15b0d17651de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065519712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3065519712
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.385901105
Short name T616
Test name
Test status
Simulation time 125652000107 ps
CPU time 127.49 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:52:24 PM PDT 24
Peak memory 200480 kb
Host smart-0871140d-464f-4843-b860-96f7a09952b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385901105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.385901105
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1040961731
Short name T861
Test name
Test status
Simulation time 23877411771 ps
CPU time 228.58 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:54:05 PM PDT 24
Peak memory 216724 kb
Host smart-b45c26fc-7e86-48c5-b39a-cc663a34da0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040961731 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1040961731
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.144984878
Short name T375
Test name
Test status
Simulation time 1190139422 ps
CPU time 2.5 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:20 PM PDT 24
Peak memory 199040 kb
Host smart-f35db3de-4987-460b-a957-1119c39d6abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144984878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.144984878
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1102110181
Short name T511
Test name
Test status
Simulation time 13907641056 ps
CPU time 24.29 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:41 PM PDT 24
Peak memory 200544 kb
Host smart-45e60645-39e2-4bc8-870a-6d6a3da957b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102110181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1102110181
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3208862571
Short name T240
Test name
Test status
Simulation time 40543685300 ps
CPU time 25.39 seconds
Started May 28 01:53:15 PM PDT 24
Finished May 28 01:53:43 PM PDT 24
Peak memory 200548 kb
Host smart-02217f6b-db55-4b94-a6c9-5170d0f21df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208862571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3208862571
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2709839198
Short name T297
Test name
Test status
Simulation time 98814051647 ps
CPU time 50.96 seconds
Started May 28 01:53:18 PM PDT 24
Finished May 28 01:54:12 PM PDT 24
Peak memory 200544 kb
Host smart-8a78ae85-c3b6-4051-b033-b4fb1b57c431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709839198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2709839198
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.165057119
Short name T201
Test name
Test status
Simulation time 148214657551 ps
CPU time 46.08 seconds
Started May 28 01:53:15 PM PDT 24
Finished May 28 01:54:03 PM PDT 24
Peak memory 200496 kb
Host smart-30a1b86c-9cf3-4cc9-bb12-c41438576f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165057119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.165057119
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2680526241
Short name T807
Test name
Test status
Simulation time 118777229093 ps
CPU time 97.76 seconds
Started May 28 01:53:16 PM PDT 24
Finished May 28 01:54:56 PM PDT 24
Peak memory 200548 kb
Host smart-7b0ee8e4-e851-4a3c-b75a-c36fc52d9f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680526241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2680526241
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1821135008
Short name T896
Test name
Test status
Simulation time 31816524646 ps
CPU time 12.31 seconds
Started May 28 01:53:19 PM PDT 24
Finished May 28 01:53:34 PM PDT 24
Peak memory 200380 kb
Host smart-24aa6051-ddca-4dc4-9809-14fa1778ca90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821135008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1821135008
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1118587411
Short name T1111
Test name
Test status
Simulation time 115727452613 ps
CPU time 187.33 seconds
Started May 28 01:53:19 PM PDT 24
Finished May 28 01:56:29 PM PDT 24
Peak memory 200356 kb
Host smart-a647144c-d719-413c-a04b-a169d70ec1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118587411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1118587411
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1921995518
Short name T980
Test name
Test status
Simulation time 296459956658 ps
CPU time 47.74 seconds
Started May 28 01:53:15 PM PDT 24
Finished May 28 01:54:04 PM PDT 24
Peak memory 200452 kb
Host smart-f00e73cf-d1c4-43df-bfb3-fea0483701c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921995518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1921995518
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3097292965
Short name T191
Test name
Test status
Simulation time 32929672965 ps
CPU time 30.63 seconds
Started May 28 01:53:16 PM PDT 24
Finished May 28 01:53:49 PM PDT 24
Peak memory 200552 kb
Host smart-24fca5e9-0611-4189-a283-4cd81784e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097292965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3097292965
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2529843458
Short name T267
Test name
Test status
Simulation time 132916900576 ps
CPU time 41.29 seconds
Started May 28 01:53:18 PM PDT 24
Finished May 28 01:54:02 PM PDT 24
Peak memory 200484 kb
Host smart-7a9d80d6-0112-4941-9d5c-612463e74e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529843458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2529843458
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3350088025
Short name T358
Test name
Test status
Simulation time 36849176 ps
CPU time 0.56 seconds
Started May 28 01:50:13 PM PDT 24
Finished May 28 01:50:19 PM PDT 24
Peak memory 194868 kb
Host smart-991ae9d8-22ee-49dd-91c2-90991a7d3e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350088025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3350088025
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.175291701
Short name T162
Test name
Test status
Simulation time 229953896673 ps
CPU time 73.88 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:51:32 PM PDT 24
Peak memory 200448 kb
Host smart-ac195a79-dea9-4645-8372-020fe32658f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175291701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.175291701
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1146591659
Short name T301
Test name
Test status
Simulation time 174781294552 ps
CPU time 82.61 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:51:40 PM PDT 24
Peak memory 200480 kb
Host smart-3d809ea6-ee63-4550-9896-39d5d10f60d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146591659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1146591659
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_intr.864161112
Short name T625
Test name
Test status
Simulation time 29825971026 ps
CPU time 51.82 seconds
Started May 28 01:50:13 PM PDT 24
Finished May 28 01:51:10 PM PDT 24
Peak memory 200544 kb
Host smart-d687b024-b3be-4456-84fc-593d2ea7d654
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864161112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.864161112
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2500664999
Short name T76
Test name
Test status
Simulation time 99459133838 ps
CPU time 467.5 seconds
Started May 28 01:50:13 PM PDT 24
Finished May 28 01:58:06 PM PDT 24
Peak memory 200468 kb
Host smart-373c5eff-9e4d-4777-81d7-8379f0d07166
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2500664999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2500664999
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1597164806
Short name T703
Test name
Test status
Simulation time 7007730132 ps
CPU time 13.94 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:32 PM PDT 24
Peak memory 199168 kb
Host smart-34cafa15-3787-4019-b683-27275b1f65e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597164806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1597164806
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.997439771
Short name T487
Test name
Test status
Simulation time 32411104145 ps
CPU time 14.62 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:50:31 PM PDT 24
Peak memory 195792 kb
Host smart-71375aa4-67c6-469f-ba64-591483586500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997439771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.997439771
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2210978073
Short name T1069
Test name
Test status
Simulation time 14195273252 ps
CPU time 302.99 seconds
Started May 28 01:50:14 PM PDT 24
Finished May 28 01:55:22 PM PDT 24
Peak memory 200456 kb
Host smart-38c1abb4-f270-4dac-a344-3e4c88786f96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2210978073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2210978073
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3081223469
Short name T79
Test name
Test status
Simulation time 6482129343 ps
CPU time 14.1 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:32 PM PDT 24
Peak memory 200292 kb
Host smart-8b08756c-7abc-4822-bc7e-16dcc7badac4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081223469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3081223469
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.382789658
Short name T1132
Test name
Test status
Simulation time 40733765727 ps
CPU time 27.26 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:50:45 PM PDT 24
Peak memory 200276 kb
Host smart-3f1fa83b-2ef1-47ef-86ec-41b1fce6d58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382789658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.382789658
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2781023557
Short name T717
Test name
Test status
Simulation time 1719063118 ps
CPU time 3.46 seconds
Started May 28 01:50:13 PM PDT 24
Finished May 28 01:50:22 PM PDT 24
Peak memory 196152 kb
Host smart-68033683-8aff-4bb3-b55c-a12f6ed7e024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781023557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2781023557
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2420361573
Short name T852
Test name
Test status
Simulation time 660822733 ps
CPU time 1.43 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:50:18 PM PDT 24
Peak memory 198784 kb
Host smart-e1e3af99-15d7-4412-afbf-853782b8e922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420361573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2420361573
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3560292209
Short name T124
Test name
Test status
Simulation time 196422627146 ps
CPU time 34.1 seconds
Started May 28 01:50:13 PM PDT 24
Finished May 28 01:50:53 PM PDT 24
Peak memory 200524 kb
Host smart-0c67140e-7aa6-4116-8304-5dca646dc590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560292209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3560292209
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2566606409
Short name T988
Test name
Test status
Simulation time 620653765141 ps
CPU time 478.39 seconds
Started May 28 01:50:14 PM PDT 24
Finished May 28 01:58:17 PM PDT 24
Peak memory 216756 kb
Host smart-9ff527f8-213d-4404-ba0a-028b1888e80d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566606409 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2566606409
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3720349695
Short name T1099
Test name
Test status
Simulation time 7043996589 ps
CPU time 7.98 seconds
Started May 28 01:50:11 PM PDT 24
Finished May 28 01:50:25 PM PDT 24
Peak memory 200472 kb
Host smart-0dfe760c-7237-421e-9ef7-ac0fe2a99d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720349695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3720349695
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.363705263
Short name T1148
Test name
Test status
Simulation time 164574765298 ps
CPU time 15.36 seconds
Started May 28 01:50:13 PM PDT 24
Finished May 28 01:50:34 PM PDT 24
Peak memory 200488 kb
Host smart-4602f88f-fcd8-4aad-81ce-6aa0021ed65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363705263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.363705263
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.84413732
Short name T250
Test name
Test status
Simulation time 50427248983 ps
CPU time 23.5 seconds
Started May 28 01:53:36 PM PDT 24
Finished May 28 01:54:04 PM PDT 24
Peak memory 200416 kb
Host smart-58d7b474-3057-4c61-aeb1-d099bff2ee5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84413732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.84413732
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1828484995
Short name T1023
Test name
Test status
Simulation time 90454367698 ps
CPU time 41.89 seconds
Started May 28 01:53:32 PM PDT 24
Finished May 28 01:54:19 PM PDT 24
Peak memory 200568 kb
Host smart-9219fa29-10df-47aa-b89f-8f7ba04854cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828484995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1828484995
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1336326821
Short name T244
Test name
Test status
Simulation time 11746844668 ps
CPU time 11.42 seconds
Started May 28 01:53:32 PM PDT 24
Finished May 28 01:53:49 PM PDT 24
Peak memory 200312 kb
Host smart-f3da0ad6-7132-4baa-9667-11b5236cdff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336326821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1336326821
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.327301701
Short name T1088
Test name
Test status
Simulation time 92969927441 ps
CPU time 45.16 seconds
Started May 28 01:53:34 PM PDT 24
Finished May 28 01:54:24 PM PDT 24
Peak memory 200572 kb
Host smart-9180b50c-2728-4f0d-a93a-ec960d842342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327301701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.327301701
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3792728403
Short name T649
Test name
Test status
Simulation time 75543213653 ps
CPU time 12.21 seconds
Started May 28 01:53:32 PM PDT 24
Finished May 28 01:53:50 PM PDT 24
Peak memory 200344 kb
Host smart-f7377dad-62f4-4f8b-96b1-15e00f67a92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792728403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3792728403
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2513109832
Short name T160
Test name
Test status
Simulation time 35671092660 ps
CPU time 49.28 seconds
Started May 28 01:53:32 PM PDT 24
Finished May 28 01:54:26 PM PDT 24
Peak memory 200544 kb
Host smart-eb6d9763-5f60-4ad8-b40b-725d0271aa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513109832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2513109832
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2204760825
Short name T1045
Test name
Test status
Simulation time 253978611239 ps
CPU time 28.36 seconds
Started May 28 01:53:33 PM PDT 24
Finished May 28 01:54:06 PM PDT 24
Peak memory 200560 kb
Host smart-9101354d-5ac8-4c71-a514-abab0ed631aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204760825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2204760825
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.610039053
Short name T525
Test name
Test status
Simulation time 17145435126 ps
CPU time 30.07 seconds
Started May 28 01:53:34 PM PDT 24
Finished May 28 01:54:09 PM PDT 24
Peak memory 200500 kb
Host smart-906ee280-ca4b-42af-8189-5c9e436dba83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610039053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.610039053
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.4030280778
Short name T1135
Test name
Test status
Simulation time 64201612 ps
CPU time 0.56 seconds
Started May 28 01:50:26 PM PDT 24
Finished May 28 01:50:33 PM PDT 24
Peak memory 195904 kb
Host smart-7ca890a2-578d-455c-b37d-545d4b9a75eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030280778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.4030280778
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3337009354
Short name T106
Test name
Test status
Simulation time 331019113930 ps
CPU time 65.74 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:51:23 PM PDT 24
Peak memory 200504 kb
Host smart-69b59fa3-12b8-4509-bef5-4f8ecc64a1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337009354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3337009354
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3121351178
Short name T158
Test name
Test status
Simulation time 33952559815 ps
CPU time 59.92 seconds
Started May 28 01:50:27 PM PDT 24
Finished May 28 01:51:34 PM PDT 24
Peak memory 200456 kb
Host smart-2f7eb1e6-096b-4029-b3c4-28c4c92dd317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121351178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3121351178
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.524544261
Short name T522
Test name
Test status
Simulation time 231005829426 ps
CPU time 186.22 seconds
Started May 28 01:50:23 PM PDT 24
Finished May 28 01:53:32 PM PDT 24
Peak memory 200524 kb
Host smart-1b069fa3-779c-4ee7-8239-ce2d5bc07458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524544261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.524544261
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.4114133124
Short name T962
Test name
Test status
Simulation time 48242282757 ps
CPU time 35.19 seconds
Started May 28 01:50:27 PM PDT 24
Finished May 28 01:51:09 PM PDT 24
Peak memory 200532 kb
Host smart-afa6c172-2658-4b4b-901b-7d1b2709ad87
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114133124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.4114133124
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.391323809
Short name T817
Test name
Test status
Simulation time 280820125818 ps
CPU time 202.4 seconds
Started May 28 01:50:24 PM PDT 24
Finished May 28 01:53:51 PM PDT 24
Peak memory 200568 kb
Host smart-3d929a85-1b7f-40d1-9bae-0db10c9c658c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=391323809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.391323809
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.575848230
Short name T1014
Test name
Test status
Simulation time 1873929017 ps
CPU time 4 seconds
Started May 28 01:50:26 PM PDT 24
Finished May 28 01:50:37 PM PDT 24
Peak memory 195932 kb
Host smart-d34418f6-385f-4751-82ee-b78c8885aaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575848230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.575848230
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.4139318082
Short name T1105
Test name
Test status
Simulation time 57751203883 ps
CPU time 72.91 seconds
Started May 28 01:50:23 PM PDT 24
Finished May 28 01:51:39 PM PDT 24
Peak memory 200668 kb
Host smart-98e1f17a-50ec-44e1-9011-76131873b0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139318082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.4139318082
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2071338105
Short name T637
Test name
Test status
Simulation time 11264587800 ps
CPU time 558.49 seconds
Started May 28 01:50:22 PM PDT 24
Finished May 28 01:59:42 PM PDT 24
Peak memory 200528 kb
Host smart-5fc812b8-e235-4d2d-8ef1-83c4e09f3309
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2071338105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2071338105
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2319234604
Short name T480
Test name
Test status
Simulation time 6348360152 ps
CPU time 59.99 seconds
Started May 28 01:50:24 PM PDT 24
Finished May 28 01:51:28 PM PDT 24
Peak memory 200512 kb
Host smart-88ff4505-f634-4aae-a685-e9602dcb38fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2319234604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2319234604
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.4272837784
Short name T1024
Test name
Test status
Simulation time 100545629922 ps
CPU time 65.52 seconds
Started May 28 01:50:25 PM PDT 24
Finished May 28 01:51:36 PM PDT 24
Peak memory 200520 kb
Host smart-16919c23-60da-43d5-9bb4-f8dc01fd86f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272837784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.4272837784
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3320168699
Short name T748
Test name
Test status
Simulation time 2979781053 ps
CPU time 4.81 seconds
Started May 28 01:50:24 PM PDT 24
Finished May 28 01:50:34 PM PDT 24
Peak memory 196328 kb
Host smart-8d2368b5-c960-4e8d-ab72-d83d78d0ef61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320168699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3320168699
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1901619455
Short name T1163
Test name
Test status
Simulation time 5968527921 ps
CPU time 22.88 seconds
Started May 28 01:50:14 PM PDT 24
Finished May 28 01:50:42 PM PDT 24
Peak memory 200264 kb
Host smart-afe993d5-ac41-4381-b276-8aaa1346923c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901619455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1901619455
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1502382731
Short name T159
Test name
Test status
Simulation time 98736144317 ps
CPU time 1058.98 seconds
Started May 28 01:50:24 PM PDT 24
Finished May 28 02:08:07 PM PDT 24
Peak memory 216992 kb
Host smart-274dce06-c60e-4009-9c80-2184b5002cea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502382731 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1502382731
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1623405983
Short name T882
Test name
Test status
Simulation time 8348484587 ps
CPU time 11.17 seconds
Started May 28 01:50:22 PM PDT 24
Finished May 28 01:50:35 PM PDT 24
Peak memory 200392 kb
Host smart-62dff36f-b864-4786-beba-6b6bb6b15863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623405983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1623405983
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.4113149793
Short name T998
Test name
Test status
Simulation time 50309945732 ps
CPU time 91.98 seconds
Started May 28 01:50:12 PM PDT 24
Finished May 28 01:51:50 PM PDT 24
Peak memory 200464 kb
Host smart-16abf2ad-78d3-424a-8ec4-0e87594a9a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113149793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.4113149793
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1332644932
Short name T293
Test name
Test status
Simulation time 94241198837 ps
CPU time 105.98 seconds
Started May 28 01:53:32 PM PDT 24
Finished May 28 01:55:22 PM PDT 24
Peak memory 200528 kb
Host smart-e3e67445-68c8-41d6-ae37-54810a34b20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332644932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1332644932
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.384345296
Short name T342
Test name
Test status
Simulation time 79289103251 ps
CPU time 59.18 seconds
Started May 28 01:53:32 PM PDT 24
Finished May 28 01:54:37 PM PDT 24
Peak memory 200476 kb
Host smart-92af7065-417f-4cdd-87cb-5bffe4742218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384345296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.384345296
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1638276554
Short name T1093
Test name
Test status
Simulation time 138504882272 ps
CPU time 294.62 seconds
Started May 28 01:53:31 PM PDT 24
Finished May 28 01:58:30 PM PDT 24
Peak memory 200516 kb
Host smart-616ab3ab-fba6-4aea-8bf8-ced4307618eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638276554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1638276554
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1485928890
Short name T249
Test name
Test status
Simulation time 168205943883 ps
CPU time 30.54 seconds
Started May 28 01:53:32 PM PDT 24
Finished May 28 01:54:07 PM PDT 24
Peak memory 200484 kb
Host smart-1fda4194-59b7-483e-90bb-b82aa6a9f231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485928890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1485928890
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.903013425
Short name T992
Test name
Test status
Simulation time 32098419594 ps
CPU time 14.76 seconds
Started May 28 01:53:32 PM PDT 24
Finished May 28 01:53:52 PM PDT 24
Peak memory 199968 kb
Host smart-76418ab6-1714-4551-b988-e67f045bdbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903013425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.903013425
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2151793408
Short name T459
Test name
Test status
Simulation time 57947382434 ps
CPU time 58.95 seconds
Started May 28 01:53:32 PM PDT 24
Finished May 28 01:54:35 PM PDT 24
Peak memory 200500 kb
Host smart-d4666511-257a-44bf-a881-2a508290f203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151793408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2151793408
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.4167166228
Short name T539
Test name
Test status
Simulation time 173070094797 ps
CPU time 85.28 seconds
Started May 28 01:53:33 PM PDT 24
Finished May 28 01:55:03 PM PDT 24
Peak memory 200532 kb
Host smart-dbd5f27e-8a93-4486-9392-50f3c431529f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167166228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.4167166228
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3181128027
Short name T1034
Test name
Test status
Simulation time 91274858056 ps
CPU time 42.65 seconds
Started May 28 01:53:32 PM PDT 24
Finished May 28 01:54:19 PM PDT 24
Peak memory 200472 kb
Host smart-b983719a-addb-4d13-8627-0bfe1e4f1a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181128027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3181128027
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.422332261
Short name T836
Test name
Test status
Simulation time 61482887330 ps
CPU time 41.53 seconds
Started May 28 01:53:33 PM PDT 24
Finished May 28 01:54:20 PM PDT 24
Peak memory 200516 kb
Host smart-7d1451b6-f797-4080-bb6c-471a4998511e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422332261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.422332261
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1768029778
Short name T926
Test name
Test status
Simulation time 13394809 ps
CPU time 0.56 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:49:09 PM PDT 24
Peak memory 195900 kb
Host smart-50261856-5ba4-4723-bb4e-8ba82eaaf8e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768029778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1768029778
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1919555659
Short name T536
Test name
Test status
Simulation time 43756478494 ps
CPU time 21.41 seconds
Started May 28 01:48:46 PM PDT 24
Finished May 28 01:49:12 PM PDT 24
Peak memory 200568 kb
Host smart-8a73746d-d3a8-4139-bbb9-3e1893d80420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919555659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1919555659
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3255676520
Short name T825
Test name
Test status
Simulation time 57612986878 ps
CPU time 29.03 seconds
Started May 28 01:48:45 PM PDT 24
Finished May 28 01:49:19 PM PDT 24
Peak memory 200476 kb
Host smart-803267f7-dae4-450b-8be5-678439e52ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255676520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3255676520
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.759395230
Short name T224
Test name
Test status
Simulation time 98291167408 ps
CPU time 50.52 seconds
Started May 28 01:48:50 PM PDT 24
Finished May 28 01:49:44 PM PDT 24
Peak memory 200516 kb
Host smart-ffa0b074-6b29-4df7-ad8d-bbcd75f7c067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759395230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.759395230
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2937528966
Short name T581
Test name
Test status
Simulation time 4536618241 ps
CPU time 4.53 seconds
Started May 28 01:48:48 PM PDT 24
Finished May 28 01:48:57 PM PDT 24
Peak memory 200404 kb
Host smart-bd8d0419-e2d2-4672-8d53-466affc1c918
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937528966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2937528966
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.372016699
Short name T1049
Test name
Test status
Simulation time 150211529083 ps
CPU time 459.3 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:56:48 PM PDT 24
Peak memory 200532 kb
Host smart-b3a04473-fa49-4b95-b839-c6bbd58966da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=372016699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.372016699
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2017199645
Short name T23
Test name
Test status
Simulation time 3282288758 ps
CPU time 7.48 seconds
Started May 28 01:48:59 PM PDT 24
Finished May 28 01:49:10 PM PDT 24
Peak memory 199480 kb
Host smart-8c97c0c3-3f55-40a0-af0e-008b98799c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017199645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2017199645
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2461001627
Short name T924
Test name
Test status
Simulation time 51115658063 ps
CPU time 16.69 seconds
Started May 28 01:48:57 PM PDT 24
Finished May 28 01:49:15 PM PDT 24
Peak memory 200804 kb
Host smart-577c454b-9ae2-48a9-a042-3d2f896c5945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461001627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2461001627
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2041207608
Short name T650
Test name
Test status
Simulation time 12831639544 ps
CPU time 738 seconds
Started May 28 01:48:58 PM PDT 24
Finished May 28 02:01:20 PM PDT 24
Peak memory 200536 kb
Host smart-0c1f8431-215c-4e5f-bd78-441c7fa07b64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041207608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2041207608
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2150145017
Short name T368
Test name
Test status
Simulation time 4797682528 ps
CPU time 11.5 seconds
Started May 28 01:48:50 PM PDT 24
Finished May 28 01:49:05 PM PDT 24
Peak memory 198620 kb
Host smart-6c6bfe74-c2fd-4462-ba57-27ce0a83f53b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2150145017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2150145017
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1132799193
Short name T1013
Test name
Test status
Simulation time 158563193776 ps
CPU time 28.46 seconds
Started May 28 01:48:57 PM PDT 24
Finished May 28 01:49:27 PM PDT 24
Peak memory 200548 kb
Host smart-05983890-2fb2-4613-8495-0a5a159ee4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132799193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1132799193
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.473486299
Short name T534
Test name
Test status
Simulation time 30910541074 ps
CPU time 49.19 seconds
Started May 28 01:48:59 PM PDT 24
Finished May 28 01:49:54 PM PDT 24
Peak memory 196168 kb
Host smart-02a2767e-25e9-4aee-bdda-386bfc7e508c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473486299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.473486299
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2493383775
Short name T102
Test name
Test status
Simulation time 140141322 ps
CPU time 0.86 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:49:10 PM PDT 24
Peak memory 219024 kb
Host smart-8843ec8d-38af-43e2-ba6b-563ba871e0f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493383775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2493383775
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1032600243
Short name T854
Test name
Test status
Simulation time 5912378585 ps
CPU time 25.66 seconds
Started May 28 01:48:55 PM PDT 24
Finished May 28 01:49:21 PM PDT 24
Peak memory 199688 kb
Host smart-3dd7a253-4451-47cf-a3ff-cae22b9b501a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032600243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1032600243
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1866406080
Short name T527
Test name
Test status
Simulation time 8641151511 ps
CPU time 219.55 seconds
Started May 28 01:48:57 PM PDT 24
Finished May 28 01:52:37 PM PDT 24
Peak memory 200600 kb
Host smart-3576153b-3ed9-47e8-91a0-4fb6ff0a33ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866406080 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1866406080
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3354709274
Short name T579
Test name
Test status
Simulation time 6703225102 ps
CPU time 32.55 seconds
Started May 28 01:48:57 PM PDT 24
Finished May 28 01:49:30 PM PDT 24
Peak memory 200476 kb
Host smart-7f4f306c-0b76-4477-ac26-a2d88156f6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354709274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3354709274
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.263585583
Short name T390
Test name
Test status
Simulation time 4328132607 ps
CPU time 5.47 seconds
Started May 28 01:48:46 PM PDT 24
Finished May 28 01:48:57 PM PDT 24
Peak memory 200508 kb
Host smart-cba23ea6-e358-491f-940b-e355b848ba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263585583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.263585583
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3042257655
Short name T52
Test name
Test status
Simulation time 54732048 ps
CPU time 0.56 seconds
Started May 28 01:50:25 PM PDT 24
Finished May 28 01:50:31 PM PDT 24
Peak memory 195832 kb
Host smart-3683d4b3-84eb-4f67-99cf-4d38ecb7d26e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042257655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3042257655
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2285716213
Short name T830
Test name
Test status
Simulation time 34299572004 ps
CPU time 85.85 seconds
Started May 28 01:50:24 PM PDT 24
Finished May 28 01:51:54 PM PDT 24
Peak memory 200524 kb
Host smart-b3367cfc-936c-42e7-a571-56bdd9cd6377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285716213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2285716213
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1340529675
Short name T772
Test name
Test status
Simulation time 9013639022 ps
CPU time 16.85 seconds
Started May 28 01:50:26 PM PDT 24
Finished May 28 01:50:49 PM PDT 24
Peak memory 200548 kb
Host smart-847c6eaa-b8b2-4fec-8de1-d3e3e9f64515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340529675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1340529675
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3904056699
Short name T226
Test name
Test status
Simulation time 110382855464 ps
CPU time 182.4 seconds
Started May 28 01:50:27 PM PDT 24
Finished May 28 01:53:36 PM PDT 24
Peak memory 200532 kb
Host smart-c8bd9e6f-bee7-4e2b-ac23-f0c7d252a7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904056699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3904056699
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1006834384
Short name T309
Test name
Test status
Simulation time 42128384145 ps
CPU time 50.13 seconds
Started May 28 01:50:24 PM PDT 24
Finished May 28 01:51:18 PM PDT 24
Peak memory 200496 kb
Host smart-185cc622-c8f6-406c-ab5a-27c9e32ac7b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006834384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1006834384
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1768127019
Short name T486
Test name
Test status
Simulation time 102348322173 ps
CPU time 267.27 seconds
Started May 28 01:50:25 PM PDT 24
Finished May 28 01:54:57 PM PDT 24
Peak memory 200312 kb
Host smart-8e1832fb-62a8-45f9-a1af-ebb0a9c6434e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1768127019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1768127019
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3531521653
Short name T1079
Test name
Test status
Simulation time 8381047434 ps
CPU time 8.9 seconds
Started May 28 01:50:23 PM PDT 24
Finished May 28 01:50:36 PM PDT 24
Peak memory 200456 kb
Host smart-7dee4d21-d1ec-48fb-a858-38c858376c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531521653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3531521653
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1150129060
Short name T128
Test name
Test status
Simulation time 144807566286 ps
CPU time 24.39 seconds
Started May 28 01:50:23 PM PDT 24
Finished May 28 01:50:50 PM PDT 24
Peak memory 200780 kb
Host smart-899b4bb8-ad0d-439a-b7b2-8c0dbe4d192e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150129060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1150129060
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.67431819
Short name T45
Test name
Test status
Simulation time 8615763732 ps
CPU time 309.5 seconds
Started May 28 01:50:23 PM PDT 24
Finished May 28 01:55:36 PM PDT 24
Peak memory 200464 kb
Host smart-91a2452d-6b9b-46e3-84d6-eeed39d283ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67431819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.67431819
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1028636112
Short name T22
Test name
Test status
Simulation time 3914477369 ps
CPU time 17.6 seconds
Started May 28 01:50:25 PM PDT 24
Finished May 28 01:50:48 PM PDT 24
Peak memory 198756 kb
Host smart-21880352-f2ad-471b-a8a0-5383101f5d04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028636112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1028636112
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2786907234
Short name T444
Test name
Test status
Simulation time 25636502305 ps
CPU time 50.22 seconds
Started May 28 01:50:27 PM PDT 24
Finished May 28 01:51:23 PM PDT 24
Peak memory 200520 kb
Host smart-e6f35e66-26a6-4d43-9544-9b9b445a1bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786907234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2786907234
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1796916646
Short name T440
Test name
Test status
Simulation time 5875538163 ps
CPU time 8.98 seconds
Started May 28 01:50:27 PM PDT 24
Finished May 28 01:50:43 PM PDT 24
Peak memory 196508 kb
Host smart-81792fad-77f6-447b-ad8f-1e9e18852697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796916646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1796916646
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.13449485
Short name T864
Test name
Test status
Simulation time 5749778014 ps
CPU time 13.89 seconds
Started May 28 01:50:24 PM PDT 24
Finished May 28 01:50:43 PM PDT 24
Peak memory 200376 kb
Host smart-7afe5710-78bd-4843-ab19-1b71a79a4fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13449485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.13449485
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.2416687958
Short name T178
Test name
Test status
Simulation time 38118518814 ps
CPU time 62.2 seconds
Started May 28 01:50:27 PM PDT 24
Finished May 28 01:51:36 PM PDT 24
Peak memory 208760 kb
Host smart-c4649fc7-b02e-4d48-b7ce-0a9a359ee4e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416687958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2416687958
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3230405283
Short name T61
Test name
Test status
Simulation time 44206741358 ps
CPU time 523.24 seconds
Started May 28 01:50:26 PM PDT 24
Finished May 28 01:59:15 PM PDT 24
Peak memory 208832 kb
Host smart-0bcaadfb-f705-4861-a94c-08d4dde906dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230405283 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3230405283
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2937692218
Short name T863
Test name
Test status
Simulation time 6498184210 ps
CPU time 17.7 seconds
Started May 28 01:50:23 PM PDT 24
Finished May 28 01:50:44 PM PDT 24
Peak memory 200264 kb
Host smart-ab5f0013-2c85-4d68-9957-5ad5cb6646de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937692218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2937692218
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1645310543
Short name T1181
Test name
Test status
Simulation time 7956311888 ps
CPU time 12.45 seconds
Started May 28 01:50:22 PM PDT 24
Finished May 28 01:50:37 PM PDT 24
Peak memory 200472 kb
Host smart-0ab26a78-490c-4a90-ae19-043792f52834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645310543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1645310543
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3935600606
Short name T971
Test name
Test status
Simulation time 27842431 ps
CPU time 0.55 seconds
Started May 28 01:50:26 PM PDT 24
Finished May 28 01:50:32 PM PDT 24
Peak memory 195904 kb
Host smart-0fc73c99-97d8-434b-a3b4-f151563b1df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935600606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3935600606
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2807883112
Short name T455
Test name
Test status
Simulation time 108793551966 ps
CPU time 47.88 seconds
Started May 28 01:50:26 PM PDT 24
Finished May 28 01:51:19 PM PDT 24
Peak memory 200480 kb
Host smart-6b7d2d28-27ec-44c9-bd96-73e7c7ff6ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807883112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2807883112
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2260639984
Short name T566
Test name
Test status
Simulation time 47138209238 ps
CPU time 19.76 seconds
Started May 28 01:50:27 PM PDT 24
Finished May 28 01:50:54 PM PDT 24
Peak memory 200296 kb
Host smart-18cf83cb-0631-4628-a0c9-ea9b25776442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260639984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2260639984
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2656602055
Short name T513
Test name
Test status
Simulation time 13063378211 ps
CPU time 40.12 seconds
Started May 28 01:50:24 PM PDT 24
Finished May 28 01:51:09 PM PDT 24
Peak memory 200460 kb
Host smart-36e4ef5f-2b4d-442f-9665-7fa56b74cae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656602055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2656602055
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3237518918
Short name T822
Test name
Test status
Simulation time 37338824694 ps
CPU time 74.45 seconds
Started May 28 01:50:23 PM PDT 24
Finished May 28 01:51:41 PM PDT 24
Peak memory 200448 kb
Host smart-4696955b-de75-4807-9f22-5b867cfc1f32
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237518918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3237518918
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.432341274
Short name T11
Test name
Test status
Simulation time 198725191092 ps
CPU time 1072.63 seconds
Started May 28 01:50:24 PM PDT 24
Finished May 28 02:08:22 PM PDT 24
Peak memory 200524 kb
Host smart-329579f3-d567-4b26-97f7-6724d0c67064
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=432341274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.432341274
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1576094409
Short name T340
Test name
Test status
Simulation time 3889711396 ps
CPU time 3.45 seconds
Started May 28 01:50:27 PM PDT 24
Finished May 28 01:50:38 PM PDT 24
Peak memory 197804 kb
Host smart-46706da1-c357-49d8-8abd-c642011ee9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576094409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1576094409
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2850791508
Short name T1059
Test name
Test status
Simulation time 133172691580 ps
CPU time 199.07 seconds
Started May 28 01:50:24 PM PDT 24
Finished May 28 01:53:47 PM PDT 24
Peak memory 208788 kb
Host smart-4071c59e-738e-4cd0-9b78-986ae4094077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850791508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2850791508
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3261098838
Short name T641
Test name
Test status
Simulation time 36776771808 ps
CPU time 404.57 seconds
Started May 28 01:50:25 PM PDT 24
Finished May 28 01:57:15 PM PDT 24
Peak memory 200288 kb
Host smart-bce9bd69-bad1-44af-abe8-266a1c0d8724
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261098838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3261098838
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1669651650
Short name T1164
Test name
Test status
Simulation time 3901943111 ps
CPU time 8.51 seconds
Started May 28 01:50:25 PM PDT 24
Finished May 28 01:50:39 PM PDT 24
Peak memory 198588 kb
Host smart-a6d23bb7-1a4c-493e-91c2-e4cc11203f85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1669651650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1669651650
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3498047425
Short name T712
Test name
Test status
Simulation time 35200452839 ps
CPU time 17.11 seconds
Started May 28 01:50:23 PM PDT 24
Finished May 28 01:50:44 PM PDT 24
Peak memory 200060 kb
Host smart-c8478d13-89c1-4fb3-a262-ee1ea90bf6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498047425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3498047425
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1282288205
Short name T457
Test name
Test status
Simulation time 4668362462 ps
CPU time 2.64 seconds
Started May 28 01:50:23 PM PDT 24
Finished May 28 01:50:28 PM PDT 24
Peak memory 196516 kb
Host smart-df069d98-8608-4a91-8053-126c53b4fe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282288205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1282288205
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.938143628
Short name T747
Test name
Test status
Simulation time 717487236 ps
CPU time 1.94 seconds
Started May 28 01:50:23 PM PDT 24
Finished May 28 01:50:29 PM PDT 24
Peak memory 198996 kb
Host smart-d2dc9743-bc6d-4ef6-9d71-3dc635d00fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938143628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.938143628
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2067004120
Short name T472
Test name
Test status
Simulation time 175567204256 ps
CPU time 1159.14 seconds
Started May 28 01:50:25 PM PDT 24
Finished May 28 02:09:50 PM PDT 24
Peak memory 200256 kb
Host smart-1d7ba45d-f9cc-4a74-86ee-218ec1386697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067004120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2067004120
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.928199280
Short name T1087
Test name
Test status
Simulation time 120759593297 ps
CPU time 303.78 seconds
Started May 28 01:50:26 PM PDT 24
Finished May 28 01:55:36 PM PDT 24
Peak memory 217152 kb
Host smart-2d463612-cf97-4db9-be92-a5edd49dded0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928199280 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.928199280
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3283092418
Short name T280
Test name
Test status
Simulation time 1205569611 ps
CPU time 1.72 seconds
Started May 28 01:50:30 PM PDT 24
Finished May 28 01:50:37 PM PDT 24
Peak memory 198616 kb
Host smart-5c7f3ba2-ea40-4ec5-80c6-3634fc25d2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283092418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3283092418
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.516239717
Short name T551
Test name
Test status
Simulation time 102903332307 ps
CPU time 38.14 seconds
Started May 28 01:50:24 PM PDT 24
Finished May 28 01:51:06 PM PDT 24
Peak memory 200544 kb
Host smart-63adbca7-c876-4457-976c-26fe58ca8c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516239717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.516239717
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.535261897
Short name T709
Test name
Test status
Simulation time 12770641 ps
CPU time 0.54 seconds
Started May 28 01:50:27 PM PDT 24
Finished May 28 01:50:33 PM PDT 24
Peak memory 195868 kb
Host smart-25961f2d-9397-472c-8c41-aa2a860eda68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535261897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.535261897
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.298210819
Short name T1000
Test name
Test status
Simulation time 18200915809 ps
CPU time 10 seconds
Started May 28 01:50:27 PM PDT 24
Finished May 28 01:50:44 PM PDT 24
Peak memory 200444 kb
Host smart-c449f9fa-adce-431a-8a9d-3bf0f6bb1351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298210819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.298210819
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2591341049
Short name T860
Test name
Test status
Simulation time 14850835889 ps
CPU time 21.94 seconds
Started May 28 01:50:25 PM PDT 24
Finished May 28 01:50:53 PM PDT 24
Peak memory 200516 kb
Host smart-2d32c01d-6f90-4b1b-a69f-07d262ac3a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591341049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2591341049
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_intr.3826256969
Short name T559
Test name
Test status
Simulation time 6939481855 ps
CPU time 9.86 seconds
Started May 28 01:50:26 PM PDT 24
Finished May 28 01:50:41 PM PDT 24
Peak memory 196428 kb
Host smart-afef9703-2e6c-48e4-91dd-0ae90f291eaa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826256969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3826256969
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1425247640
Short name T454
Test name
Test status
Simulation time 222432585787 ps
CPU time 148.48 seconds
Started May 28 01:50:31 PM PDT 24
Finished May 28 01:53:04 PM PDT 24
Peak memory 200468 kb
Host smart-b0092ec5-2176-444b-af29-3ba04701b61b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1425247640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1425247640
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2020726514
Short name T1027
Test name
Test status
Simulation time 2535892405 ps
CPU time 2.86 seconds
Started May 28 01:50:31 PM PDT 24
Finished May 28 01:50:39 PM PDT 24
Peak memory 197896 kb
Host smart-d8300775-ae5d-4581-9b95-e28b13424470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020726514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2020726514
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2251165161
Short name T607
Test name
Test status
Simulation time 185640218137 ps
CPU time 86.56 seconds
Started May 28 01:50:25 PM PDT 24
Finished May 28 01:51:57 PM PDT 24
Peak memory 208728 kb
Host smart-ec336216-58ea-470c-a6bc-c70f19535535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251165161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2251165161
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1905355525
Short name T916
Test name
Test status
Simulation time 10418318368 ps
CPU time 584.8 seconds
Started May 28 01:50:31 PM PDT 24
Finished May 28 02:00:21 PM PDT 24
Peak memory 200520 kb
Host smart-bf5942f7-0922-48e2-90ed-150502d196d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1905355525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1905355525
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.757606158
Short name T951
Test name
Test status
Simulation time 2541016889 ps
CPU time 4.43 seconds
Started May 28 01:50:25 PM PDT 24
Finished May 28 01:50:34 PM PDT 24
Peak memory 198656 kb
Host smart-836d7039-0b82-41e0-a2c0-85671dd13adf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=757606158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.757606158
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.707681001
Short name T347
Test name
Test status
Simulation time 21006674692 ps
CPU time 33.24 seconds
Started May 28 01:50:30 PM PDT 24
Finished May 28 01:51:08 PM PDT 24
Peak memory 199760 kb
Host smart-c8a52596-a34c-4d4e-a4a0-3b1b4c0da6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707681001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.707681001
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3828087830
Short name T435
Test name
Test status
Simulation time 5362985086 ps
CPU time 1.24 seconds
Started May 28 01:50:25 PM PDT 24
Finished May 28 01:50:31 PM PDT 24
Peak memory 196456 kb
Host smart-814c711e-ffc8-4d4d-8d57-1ba697945999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828087830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3828087830
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3029316546
Short name T654
Test name
Test status
Simulation time 5281311806 ps
CPU time 13.06 seconds
Started May 28 01:50:24 PM PDT 24
Finished May 28 01:50:42 PM PDT 24
Peak memory 200236 kb
Host smart-045632dd-7984-48b9-98c7-7cc99a5f3a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029316546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3029316546
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.624145516
Short name T442
Test name
Test status
Simulation time 27643379150 ps
CPU time 44.57 seconds
Started May 28 01:50:30 PM PDT 24
Finished May 28 01:51:20 PM PDT 24
Peak memory 200544 kb
Host smart-02f31710-32a6-4a86-868c-02214a820a11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624145516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.624145516
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1149146946
Short name T27
Test name
Test status
Simulation time 37257940759 ps
CPU time 334.01 seconds
Started May 28 01:50:29 PM PDT 24
Finished May 28 01:56:09 PM PDT 24
Peak memory 217296 kb
Host smart-95add429-d40c-4943-a692-b6ac61c39da4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149146946 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1149146946
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2068026081
Short name T385
Test name
Test status
Simulation time 1036050849 ps
CPU time 4.72 seconds
Started May 28 01:50:29 PM PDT 24
Finished May 28 01:50:40 PM PDT 24
Peak memory 199432 kb
Host smart-746ca59a-6c8d-4f8f-bfa7-78ef28b19bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068026081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2068026081
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3888774679
Short name T612
Test name
Test status
Simulation time 41367500759 ps
CPU time 75.02 seconds
Started May 28 01:50:30 PM PDT 24
Finished May 28 01:51:50 PM PDT 24
Peak memory 200452 kb
Host smart-7581df60-2c70-4feb-b866-e8c81d2bc05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888774679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3888774679
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1661314028
Short name T1140
Test name
Test status
Simulation time 38668068 ps
CPU time 0.58 seconds
Started May 28 01:50:30 PM PDT 24
Finished May 28 01:50:36 PM PDT 24
Peak memory 195900 kb
Host smart-9a75f6a7-b659-4836-89d2-65ceee2aa941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661314028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1661314028
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1364696611
Short name T125
Test name
Test status
Simulation time 94659756444 ps
CPU time 27.09 seconds
Started May 28 01:50:31 PM PDT 24
Finished May 28 01:51:03 PM PDT 24
Peak memory 200508 kb
Host smart-2c42262a-18fb-400b-806d-dca105fa986c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364696611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1364696611
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3321980876
Short name T563
Test name
Test status
Simulation time 33389018625 ps
CPU time 17.45 seconds
Started May 28 01:50:31 PM PDT 24
Finished May 28 01:50:54 PM PDT 24
Peak memory 200412 kb
Host smart-79b298e8-19a7-40f2-8126-7182efc78c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321980876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3321980876
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1690312742
Short name T556
Test name
Test status
Simulation time 85404052750 ps
CPU time 11.36 seconds
Started May 28 01:50:31 PM PDT 24
Finished May 28 01:50:48 PM PDT 24
Peak memory 200332 kb
Host smart-19b6550c-6429-4684-9a0f-7e3b45f503ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690312742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1690312742
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2691606948
Short name T568
Test name
Test status
Simulation time 14115349881 ps
CPU time 11.74 seconds
Started May 28 01:50:32 PM PDT 24
Finished May 28 01:50:48 PM PDT 24
Peak memory 198252 kb
Host smart-529d3af7-5b05-484b-b663-85abcab8c2f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691606948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2691606948
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1194379724
Short name T640
Test name
Test status
Simulation time 44327200282 ps
CPU time 111.04 seconds
Started May 28 01:50:31 PM PDT 24
Finished May 28 01:52:27 PM PDT 24
Peak memory 200456 kb
Host smart-52c595a9-0772-4537-b535-08d44750b5b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1194379724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1194379724
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2175693973
Short name T746
Test name
Test status
Simulation time 9660913552 ps
CPU time 12.84 seconds
Started May 28 01:50:24 PM PDT 24
Finished May 28 01:50:42 PM PDT 24
Peak memory 199640 kb
Host smart-ef69a7a0-7744-4efd-b303-6a492fe2a55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175693973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2175693973
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.437740784
Short name T1106
Test name
Test status
Simulation time 19656379717 ps
CPU time 19.01 seconds
Started May 28 01:50:32 PM PDT 24
Finished May 28 01:50:55 PM PDT 24
Peak memory 200732 kb
Host smart-01ebdc35-d2ea-4019-bb8f-0cd8df4f9591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437740784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.437740784
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1612222546
Short name T850
Test name
Test status
Simulation time 23444752274 ps
CPU time 345.85 seconds
Started May 28 01:50:32 PM PDT 24
Finished May 28 01:56:22 PM PDT 24
Peak memory 200448 kb
Host smart-2d817f85-645a-4d47-ac61-4d38a9cb5494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1612222546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1612222546
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2537162048
Short name T873
Test name
Test status
Simulation time 2642607612 ps
CPU time 18.21 seconds
Started May 28 01:50:30 PM PDT 24
Finished May 28 01:50:53 PM PDT 24
Peak memory 198904 kb
Host smart-2bd23b46-2e63-4065-9f65-85b786ee1c10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2537162048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2537162048
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.818056554
Short name T944
Test name
Test status
Simulation time 22939656806 ps
CPU time 39.67 seconds
Started May 28 01:50:32 PM PDT 24
Finished May 28 01:51:16 PM PDT 24
Peak memory 200352 kb
Host smart-cd5315b9-3738-4d39-8ca9-e0d4ab0e07fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818056554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.818056554
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3510767704
Short name T943
Test name
Test status
Simulation time 631865489 ps
CPU time 1.65 seconds
Started May 28 01:50:30 PM PDT 24
Finished May 28 01:50:37 PM PDT 24
Peak memory 195892 kb
Host smart-09a840a6-2795-4281-8221-7b639243b766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510767704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3510767704
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1015235602
Short name T908
Test name
Test status
Simulation time 5992334828 ps
CPU time 9.48 seconds
Started May 28 01:50:27 PM PDT 24
Finished May 28 01:50:42 PM PDT 24
Peak memory 200244 kb
Host smart-83755831-78d9-4ea4-a867-2a78612fe817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015235602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1015235602
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2055915325
Short name T112
Test name
Test status
Simulation time 154994347649 ps
CPU time 246.72 seconds
Started May 28 01:50:32 PM PDT 24
Finished May 28 01:54:43 PM PDT 24
Peak memory 200524 kb
Host smart-5076738d-cd27-4230-bf55-a52b28d8c8dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055915325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2055915325
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1042417635
Short name T109
Test name
Test status
Simulation time 43461804003 ps
CPU time 405.13 seconds
Started May 28 01:50:30 PM PDT 24
Finished May 28 01:57:20 PM PDT 24
Peak memory 217012 kb
Host smart-5d356800-76da-460e-83a6-fd304bdb4b2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042417635 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1042417635
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2123760729
Short name T1153
Test name
Test status
Simulation time 7691099344 ps
CPU time 12.17 seconds
Started May 28 01:50:31 PM PDT 24
Finished May 28 01:50:48 PM PDT 24
Peak memory 200480 kb
Host smart-75d7c0ed-2b77-4ab5-9998-e40f41d2ca7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123760729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2123760729
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.576997058
Short name T305
Test name
Test status
Simulation time 40519382104 ps
CPU time 28.75 seconds
Started May 28 01:50:30 PM PDT 24
Finished May 28 01:51:04 PM PDT 24
Peak memory 200484 kb
Host smart-8a86ba2f-4fa7-4b5a-a9e6-6667c3093e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576997058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.576997058
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.138162963
Short name T804
Test name
Test status
Simulation time 13102232 ps
CPU time 0.55 seconds
Started May 28 01:50:50 PM PDT 24
Finished May 28 01:50:52 PM PDT 24
Peak memory 195832 kb
Host smart-b7b7172a-4175-4f9b-b7be-4e7aa00b06ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138162963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.138162963
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.618479744
Short name T780
Test name
Test status
Simulation time 21623284439 ps
CPU time 8.36 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:50:49 PM PDT 24
Peak memory 199916 kb
Host smart-d2688219-514a-425f-8406-a99a0c41c4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618479744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.618479744
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3979247197
Short name T774
Test name
Test status
Simulation time 154071046889 ps
CPU time 77.96 seconds
Started May 28 01:50:37 PM PDT 24
Finished May 28 01:51:57 PM PDT 24
Peak memory 200516 kb
Host smart-c43ff363-6f9b-4cf2-b711-41e2082dc90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979247197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3979247197
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_intr.1884807701
Short name T21
Test name
Test status
Simulation time 66721681001 ps
CPU time 28.1 seconds
Started May 28 01:50:42 PM PDT 24
Finished May 28 01:51:11 PM PDT 24
Peak memory 200516 kb
Host smart-ea9932e6-c4a5-4bdb-a609-52e6613c8d38
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884807701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1884807701
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1129178351
Short name T776
Test name
Test status
Simulation time 239710912472 ps
CPU time 286.71 seconds
Started May 28 01:50:43 PM PDT 24
Finished May 28 01:55:31 PM PDT 24
Peak memory 200508 kb
Host smart-b08122f3-6291-49dd-887c-b9e064d03d7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129178351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1129178351
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3158634538
Short name T799
Test name
Test status
Simulation time 1213775573 ps
CPU time 1.4 seconds
Started May 28 01:50:37 PM PDT 24
Finished May 28 01:50:41 PM PDT 24
Peak memory 197856 kb
Host smart-c3338b4c-e979-43e0-9a77-35e296623290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158634538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3158634538
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.324933465
Short name T430
Test name
Test status
Simulation time 64682859119 ps
CPU time 105.97 seconds
Started May 28 01:50:39 PM PDT 24
Finished May 28 01:52:27 PM PDT 24
Peak memory 208936 kb
Host smart-c4c32638-b0e8-4f3a-8bd5-5e767b39db28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324933465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.324933465
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1485577366
Short name T415
Test name
Test status
Simulation time 7203298929 ps
CPU time 427.83 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:57:48 PM PDT 24
Peak memory 200336 kb
Host smart-aed8caf6-b56e-4ef2-af18-3737cc5fc04f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485577366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1485577366
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3597917082
Short name T946
Test name
Test status
Simulation time 3694631560 ps
CPU time 26.52 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:51:07 PM PDT 24
Peak memory 199412 kb
Host smart-4463ee91-84ce-4177-a32c-b4fafcf284f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3597917082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3597917082
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1448783024
Short name T670
Test name
Test status
Simulation time 171976376246 ps
CPU time 108.26 seconds
Started May 28 01:50:36 PM PDT 24
Finished May 28 01:52:27 PM PDT 24
Peak memory 200540 kb
Host smart-11748d73-cfee-4f61-87bd-8f20e93c5bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448783024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1448783024
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3623298906
Short name T691
Test name
Test status
Simulation time 3462793188 ps
CPU time 1.23 seconds
Started May 28 01:50:37 PM PDT 24
Finished May 28 01:50:41 PM PDT 24
Peak memory 196520 kb
Host smart-b379117e-bd55-4b2b-ba5c-a23a4d0a358a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623298906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3623298906
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1496924239
Short name T1046
Test name
Test status
Simulation time 770029687 ps
CPU time 1.38 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:50:42 PM PDT 24
Peak memory 200204 kb
Host smart-8395c622-d6cd-4c80-a62b-d4336e05f078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496924239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1496924239
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3141877878
Short name T953
Test name
Test status
Simulation time 212087061652 ps
CPU time 663.5 seconds
Started May 28 01:50:50 PM PDT 24
Finished May 28 02:01:55 PM PDT 24
Peak memory 225352 kb
Host smart-3f223850-6dfc-4fcc-a2de-34fa84778b7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141877878 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3141877878
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.951304249
Short name T1030
Test name
Test status
Simulation time 4452319063 ps
CPU time 1.8 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:50:42 PM PDT 24
Peak memory 198968 kb
Host smart-61fdacc2-9ca3-4e3f-86b7-10f7e43fad3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951304249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.951304249
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3327511413
Short name T333
Test name
Test status
Simulation time 25020023733 ps
CPU time 38.75 seconds
Started May 28 01:50:36 PM PDT 24
Finished May 28 01:51:17 PM PDT 24
Peak memory 200472 kb
Host smart-051dc85f-4e84-41c8-b929-f56e5aad6e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327511413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3327511413
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2636698871
Short name T1035
Test name
Test status
Simulation time 42236527 ps
CPU time 0.54 seconds
Started May 28 01:50:50 PM PDT 24
Finished May 28 01:50:52 PM PDT 24
Peak memory 195828 kb
Host smart-ecb95eb7-7d5d-4dd3-a28d-18f24b918983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636698871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2636698871
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.843864597
Short name T306
Test name
Test status
Simulation time 81730759664 ps
CPU time 44.7 seconds
Started May 28 01:50:40 PM PDT 24
Finished May 28 01:51:27 PM PDT 24
Peak memory 200520 kb
Host smart-d14b0521-e107-48d3-acb9-972fbddb3727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843864597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.843864597
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.566109168
Short name T711
Test name
Test status
Simulation time 110553406372 ps
CPU time 557.82 seconds
Started May 28 01:50:49 PM PDT 24
Finished May 28 02:00:08 PM PDT 24
Peak memory 200364 kb
Host smart-09a029ce-4ee4-4882-b005-f9f624d7ec10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566109168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.566109168
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_intr.1808324453
Short name T518
Test name
Test status
Simulation time 21675111965 ps
CPU time 18.85 seconds
Started May 28 01:50:37 PM PDT 24
Finished May 28 01:50:58 PM PDT 24
Peak memory 198984 kb
Host smart-1eccde96-9d4a-4551-8074-1907ad980f23
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808324453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1808324453
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2993839256
Short name T714
Test name
Test status
Simulation time 74218757140 ps
CPU time 376.87 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:56:57 PM PDT 24
Peak memory 200556 kb
Host smart-b7737640-7fc2-4cb0-96ae-ecdbf9d95bf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2993839256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2993839256
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3665978312
Short name T1177
Test name
Test status
Simulation time 965707771 ps
CPU time 1.36 seconds
Started May 28 01:50:40 PM PDT 24
Finished May 28 01:50:43 PM PDT 24
Peak memory 196544 kb
Host smart-e74e76e7-afcb-47c6-b7f3-81dc364c0eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665978312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3665978312
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.4132617492
Short name T292
Test name
Test status
Simulation time 134537566391 ps
CPU time 204.32 seconds
Started May 28 01:50:44 PM PDT 24
Finished May 28 01:54:09 PM PDT 24
Peak memory 208980 kb
Host smart-d100ea3b-bdff-4140-8982-709e27cc52d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132617492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.4132617492
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3900403005
Short name T1009
Test name
Test status
Simulation time 16431979350 ps
CPU time 193.79 seconds
Started May 28 01:50:39 PM PDT 24
Finished May 28 01:53:55 PM PDT 24
Peak memory 200540 kb
Host smart-8b443733-d94a-4361-a7a3-78d8fedaa5f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3900403005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3900403005
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3839961247
Short name T942
Test name
Test status
Simulation time 3016266059 ps
CPU time 7.09 seconds
Started May 28 01:50:36 PM PDT 24
Finished May 28 01:50:46 PM PDT 24
Peak memory 198512 kb
Host smart-12d82361-c7e2-4e73-83f6-441d9f918417
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3839961247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3839961247
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3090355482
Short name T879
Test name
Test status
Simulation time 21563323075 ps
CPU time 21.63 seconds
Started May 28 01:50:40 PM PDT 24
Finished May 28 01:51:03 PM PDT 24
Peak memory 200508 kb
Host smart-f1f06faf-39cc-4ddf-ac81-17b9db790759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090355482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3090355482
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.715761653
Short name T406
Test name
Test status
Simulation time 3252327479 ps
CPU time 3.32 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:50:44 PM PDT 24
Peak memory 196508 kb
Host smart-c93f17ba-9132-42a8-b4c8-55d84e2ab516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715761653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.715761653
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3849927929
Short name T573
Test name
Test status
Simulation time 128409769 ps
CPU time 1.38 seconds
Started May 28 01:50:40 PM PDT 24
Finished May 28 01:50:44 PM PDT 24
Peak memory 199128 kb
Host smart-2936634a-6790-40b2-b1ed-8e0a7140c796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849927929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3849927929
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.112853253
Short name T720
Test name
Test status
Simulation time 199706571593 ps
CPU time 378.85 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:57:00 PM PDT 24
Peak memory 200540 kb
Host smart-a089c356-4c10-4375-8bcf-464e32eaa8f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112853253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.112853253
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2754615273
Short name T550
Test name
Test status
Simulation time 16648698575 ps
CPU time 194.88 seconds
Started May 28 01:50:43 PM PDT 24
Finished May 28 01:53:59 PM PDT 24
Peak memory 208712 kb
Host smart-a2c85e89-273d-4716-b52d-ddb6c9d4a8e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754615273 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2754615273
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3479949977
Short name T1165
Test name
Test status
Simulation time 771157445 ps
CPU time 2.92 seconds
Started May 28 01:50:50 PM PDT 24
Finished May 28 01:50:54 PM PDT 24
Peak memory 199320 kb
Host smart-e90a3e8f-95f3-4632-9b6f-9ab80b9618af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479949977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3479949977
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1700997145
Short name T504
Test name
Test status
Simulation time 52390393741 ps
CPU time 43.97 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:51:24 PM PDT 24
Peak memory 200504 kb
Host smart-f2cec6cd-f5da-4f84-9b43-f13887306cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700997145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1700997145
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1471438932
Short name T392
Test name
Test status
Simulation time 43053106 ps
CPU time 0.55 seconds
Started May 28 01:50:55 PM PDT 24
Finished May 28 01:50:56 PM PDT 24
Peak memory 195904 kb
Host smart-ae21fd42-e1af-449a-97fd-7e9600e59a92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471438932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1471438932
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2991137279
Short name T1155
Test name
Test status
Simulation time 42841857636 ps
CPU time 21.74 seconds
Started May 28 01:50:50 PM PDT 24
Finished May 28 01:51:13 PM PDT 24
Peak memory 200452 kb
Host smart-7b05cc15-ee8c-4558-be41-321cae51f9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991137279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2991137279
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2378349285
Short name T304
Test name
Test status
Simulation time 55114225650 ps
CPU time 77.69 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:51:58 PM PDT 24
Peak memory 200464 kb
Host smart-e421a67d-afac-4b40-9c9c-7c1132ceb9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378349285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2378349285
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_intr.402783327
Short name T847
Test name
Test status
Simulation time 113218353683 ps
CPU time 99.03 seconds
Started May 28 01:50:42 PM PDT 24
Finished May 28 01:52:23 PM PDT 24
Peak memory 200432 kb
Host smart-076da2f7-a9d7-4425-a87a-1153484061f4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402783327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.402783327
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.567104022
Short name T8
Test name
Test status
Simulation time 104858433409 ps
CPU time 371.56 seconds
Started May 28 01:50:50 PM PDT 24
Finished May 28 01:57:03 PM PDT 24
Peak memory 200420 kb
Host smart-5b2d82ba-6157-422e-b035-f83db2368a02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=567104022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.567104022
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2170443977
Short name T464
Test name
Test status
Simulation time 3933950755 ps
CPU time 9.42 seconds
Started May 28 01:50:52 PM PDT 24
Finished May 28 01:51:04 PM PDT 24
Peak memory 200540 kb
Host smart-5d7cdb12-c3d4-48ac-9712-790957ead861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170443977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2170443977
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2076706643
Short name T960
Test name
Test status
Simulation time 70284888131 ps
CPU time 34.45 seconds
Started May 28 01:50:40 PM PDT 24
Finished May 28 01:51:17 PM PDT 24
Peak memory 199504 kb
Host smart-c066d2dc-a6b4-42a0-9405-1a8f93c035d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076706643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2076706643
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.2449075309
Short name T1109
Test name
Test status
Simulation time 11812760615 ps
CPU time 313.3 seconds
Started May 28 01:50:39 PM PDT 24
Finished May 28 01:55:55 PM PDT 24
Peak memory 200540 kb
Host smart-ac859b5e-0437-488b-9235-cc10e2e4916a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2449075309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2449075309
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3751257214
Short name T356
Test name
Test status
Simulation time 3798910129 ps
CPU time 26.68 seconds
Started May 28 01:50:39 PM PDT 24
Finished May 28 01:51:08 PM PDT 24
Peak memory 200360 kb
Host smart-1e021b01-adc7-44f9-aa87-a76e41f2deb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3751257214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3751257214
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1271590843
Short name T1102
Test name
Test status
Simulation time 9995455030 ps
CPU time 18.58 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:50:59 PM PDT 24
Peak memory 200492 kb
Host smart-a1b24cbd-ab8f-4418-aea5-138e40c36806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271590843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1271590843
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3609591827
Short name T315
Test name
Test status
Simulation time 44268558898 ps
CPU time 36.85 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:51:17 PM PDT 24
Peak memory 196528 kb
Host smart-d50e9b12-1745-4c8e-84f2-b428721118dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609591827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3609591827
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.887025820
Short name T622
Test name
Test status
Simulation time 486160685 ps
CPU time 1.44 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:50:42 PM PDT 24
Peak memory 200408 kb
Host smart-6b4a5b01-08dc-4c66-a28f-5e81041dc7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887025820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.887025820
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.2998969141
Short name T849
Test name
Test status
Simulation time 161306646616 ps
CPU time 299.17 seconds
Started May 28 01:50:37 PM PDT 24
Finished May 28 01:55:39 PM PDT 24
Peak memory 200552 kb
Host smart-bf0dbddb-4302-4c82-8ef9-75a286ccd34d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998969141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2998969141
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1285078149
Short name T289
Test name
Test status
Simulation time 6916439906 ps
CPU time 19.61 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:51:00 PM PDT 24
Peak memory 200400 kb
Host smart-1260e8b4-fcf6-4a3f-924e-9f03eeaa0ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285078149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1285078149
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2595034262
Short name T707
Test name
Test status
Simulation time 59974454682 ps
CPU time 31.49 seconds
Started May 28 01:50:38 PM PDT 24
Finished May 28 01:51:11 PM PDT 24
Peak memory 200376 kb
Host smart-7547912b-a402-45dc-b6a4-8d671aa96ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595034262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2595034262
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2355693304
Short name T514
Test name
Test status
Simulation time 30794571 ps
CPU time 0.53 seconds
Started May 28 01:50:57 PM PDT 24
Finished May 28 01:50:59 PM PDT 24
Peak memory 194624 kb
Host smart-0fd6c591-112a-4229-b57d-b87e23af622a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355693304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2355693304
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1897584679
Short name T813
Test name
Test status
Simulation time 150183548021 ps
CPU time 55.53 seconds
Started May 28 01:50:52 PM PDT 24
Finished May 28 01:51:50 PM PDT 24
Peak memory 200536 kb
Host smart-f93b25cd-3086-4def-a419-bf6dbe7ee724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897584679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1897584679
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1110481490
Short name T610
Test name
Test status
Simulation time 183269613072 ps
CPU time 51.87 seconds
Started May 28 01:50:52 PM PDT 24
Finished May 28 01:51:46 PM PDT 24
Peak memory 200432 kb
Host smart-1a394ef2-aeb3-4231-a6c6-169ac46160f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110481490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1110481490
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3826337187
Short name T414
Test name
Test status
Simulation time 94589847894 ps
CPU time 134.17 seconds
Started May 28 01:50:51 PM PDT 24
Finished May 28 01:53:06 PM PDT 24
Peak memory 200540 kb
Host smart-922539df-dabc-4f8a-af5f-b33d187598a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826337187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3826337187
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2206219414
Short name T458
Test name
Test status
Simulation time 13024431800 ps
CPU time 19.86 seconds
Started May 28 01:50:52 PM PDT 24
Finished May 28 01:51:15 PM PDT 24
Peak memory 199264 kb
Host smart-262ad627-b62c-4c78-a792-e4d007cc703f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206219414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2206219414
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3374373205
Short name T1146
Test name
Test status
Simulation time 95935938690 ps
CPU time 533.41 seconds
Started May 28 01:50:51 PM PDT 24
Finished May 28 01:59:46 PM PDT 24
Peak memory 200460 kb
Host smart-c1204187-db03-42fe-8982-c5dd9884e675
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3374373205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3374373205
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.803259500
Short name T462
Test name
Test status
Simulation time 1704141227 ps
CPU time 1.92 seconds
Started May 28 01:50:53 PM PDT 24
Finished May 28 01:50:57 PM PDT 24
Peak memory 195964 kb
Host smart-d0bbfd7d-36e6-4b3d-a300-d38d104220ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803259500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.803259500
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.742624550
Short name T599
Test name
Test status
Simulation time 168268834109 ps
CPU time 241.23 seconds
Started May 28 01:50:51 PM PDT 24
Finished May 28 01:54:54 PM PDT 24
Peak memory 208592 kb
Host smart-b7b72fac-b51b-4645-96a7-9e0d88640b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742624550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.742624550
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.4184091078
Short name T303
Test name
Test status
Simulation time 17578342242 ps
CPU time 1036.53 seconds
Started May 28 01:50:51 PM PDT 24
Finished May 28 02:08:10 PM PDT 24
Peak memory 200444 kb
Host smart-bf5f302b-89e2-4158-8ee0-738aa01c7a17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4184091078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.4184091078
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1495806925
Short name T990
Test name
Test status
Simulation time 6655540515 ps
CPU time 8.75 seconds
Started May 28 01:50:51 PM PDT 24
Finished May 28 01:51:02 PM PDT 24
Peak memory 199320 kb
Host smart-66aaa85a-7f5e-49b6-ba3c-6db4b414e056
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1495806925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1495806925
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1625841264
Short name T762
Test name
Test status
Simulation time 132079434643 ps
CPU time 100.47 seconds
Started May 28 01:50:54 PM PDT 24
Finished May 28 01:52:36 PM PDT 24
Peak memory 200324 kb
Host smart-1e8ca9d3-c9b4-4b29-b05e-043b3546ce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625841264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1625841264
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.526542654
Short name T317
Test name
Test status
Simulation time 5122443320 ps
CPU time 4.12 seconds
Started May 28 01:50:50 PM PDT 24
Finished May 28 01:50:56 PM PDT 24
Peak memory 196808 kb
Host smart-9390b392-4fe3-4f10-adad-be6ce368f1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526542654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.526542654
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.655886487
Short name T834
Test name
Test status
Simulation time 1032024714 ps
CPU time 1.14 seconds
Started May 28 01:50:50 PM PDT 24
Finished May 28 01:50:53 PM PDT 24
Peak memory 199092 kb
Host smart-92815326-013f-4a28-96b5-0acc4794db81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655886487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.655886487
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1819191065
Short name T783
Test name
Test status
Simulation time 45246624479 ps
CPU time 89.73 seconds
Started May 28 01:50:53 PM PDT 24
Finished May 28 01:52:25 PM PDT 24
Peak memory 200548 kb
Host smart-b0934ebe-2a13-444f-9c6e-6761b2227b60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819191065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1819191065
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.588027936
Short name T1081
Test name
Test status
Simulation time 313186785196 ps
CPU time 356.84 seconds
Started May 28 01:50:52 PM PDT 24
Finished May 28 01:56:52 PM PDT 24
Peak memory 209812 kb
Host smart-6199fd49-53d8-447b-a016-1aae7b8a934c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588027936 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.588027936
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.658831570
Short name T295
Test name
Test status
Simulation time 872579311 ps
CPU time 3.07 seconds
Started May 28 01:50:52 PM PDT 24
Finished May 28 01:50:57 PM PDT 24
Peak memory 199044 kb
Host smart-466fa8f7-0bfe-45f7-a911-7f69595deae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658831570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.658831570
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1492708791
Short name T561
Test name
Test status
Simulation time 19641952013 ps
CPU time 10.3 seconds
Started May 28 01:50:57 PM PDT 24
Finished May 28 01:51:09 PM PDT 24
Peak memory 198128 kb
Host smart-4e6f7163-b871-4dff-b36a-9bc0180b5b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492708791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1492708791
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3891406978
Short name T461
Test name
Test status
Simulation time 15053433 ps
CPU time 0.58 seconds
Started May 28 01:50:50 PM PDT 24
Finished May 28 01:50:53 PM PDT 24
Peak memory 195820 kb
Host smart-90209208-91f8-4171-b406-33bdfe161211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891406978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3891406978
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.4071844278
Short name T618
Test name
Test status
Simulation time 65560162943 ps
CPU time 106.1 seconds
Started May 28 01:50:51 PM PDT 24
Finished May 28 01:52:39 PM PDT 24
Peak memory 200564 kb
Host smart-5dd9c2d6-3edb-4b59-9628-654f104663e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071844278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.4071844278
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.439211799
Short name T983
Test name
Test status
Simulation time 84873497648 ps
CPU time 37.08 seconds
Started May 28 01:50:57 PM PDT 24
Finished May 28 01:51:36 PM PDT 24
Peak memory 200180 kb
Host smart-7d154972-9059-4e9a-bbb7-55e408bf771b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439211799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.439211799
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_intr.4243738113
Short name T710
Test name
Test status
Simulation time 155297174459 ps
CPU time 103.24 seconds
Started May 28 01:50:53 PM PDT 24
Finished May 28 01:52:38 PM PDT 24
Peak memory 200416 kb
Host smart-1e48e256-8bc7-4f91-b787-f9e8d2f7dd38
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243738113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.4243738113
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2892419615
Short name T803
Test name
Test status
Simulation time 95432889313 ps
CPU time 735.95 seconds
Started May 28 01:50:57 PM PDT 24
Finished May 28 02:03:14 PM PDT 24
Peak memory 200488 kb
Host smart-3233f31c-547d-400c-af44-97b6cee8bb41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2892419615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2892419615
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1988679724
Short name T1133
Test name
Test status
Simulation time 5326804502 ps
CPU time 3.58 seconds
Started May 28 01:50:51 PM PDT 24
Finished May 28 01:50:57 PM PDT 24
Peak memory 197920 kb
Host smart-d541b431-905f-458a-af04-f142a70ece07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988679724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1988679724
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.328752185
Short name T324
Test name
Test status
Simulation time 41813452125 ps
CPU time 95.7 seconds
Started May 28 01:50:53 PM PDT 24
Finished May 28 01:52:31 PM PDT 24
Peak memory 208976 kb
Host smart-a38b3bde-c25a-45c8-93b2-4d886861fcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328752185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.328752185
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1268110038
Short name T485
Test name
Test status
Simulation time 7824045539 ps
CPU time 111.22 seconds
Started May 28 01:50:51 PM PDT 24
Finished May 28 01:52:44 PM PDT 24
Peak memory 200536 kb
Host smart-9f876187-122f-4222-9ebd-3c068f504bfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1268110038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1268110038
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1497919467
Short name T3
Test name
Test status
Simulation time 5831039337 ps
CPU time 51.12 seconds
Started May 28 01:50:57 PM PDT 24
Finished May 28 01:51:49 PM PDT 24
Peak memory 199628 kb
Host smart-543209d8-98b5-492c-8d9f-a8cac39c1e5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1497919467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1497919467
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1172031192
Short name T754
Test name
Test status
Simulation time 259270731901 ps
CPU time 97.2 seconds
Started May 28 01:50:51 PM PDT 24
Finished May 28 01:52:30 PM PDT 24
Peak memory 200468 kb
Host smart-ebc7247c-6daf-41c5-98ae-ea090de25db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172031192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1172031192
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1884280946
Short name T811
Test name
Test status
Simulation time 419922567 ps
CPU time 1.32 seconds
Started May 28 01:50:57 PM PDT 24
Finished May 28 01:51:00 PM PDT 24
Peak memory 195904 kb
Host smart-0a63f007-af5b-4364-a88f-1f3c04fd44bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884280946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1884280946
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.4282875348
Short name T422
Test name
Test status
Simulation time 868262292 ps
CPU time 2.08 seconds
Started May 28 01:50:52 PM PDT 24
Finished May 28 01:50:56 PM PDT 24
Peak memory 200144 kb
Host smart-034a6d0c-dac4-4c02-82a8-cd9f19161afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282875348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4282875348
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1798102258
Short name T35
Test name
Test status
Simulation time 16478761682 ps
CPU time 194.55 seconds
Started May 28 01:50:53 PM PDT 24
Finished May 28 01:54:10 PM PDT 24
Peak memory 216308 kb
Host smart-73f248e1-234d-4a71-834e-c33e6114bc72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798102258 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1798102258
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.798483998
Short name T558
Test name
Test status
Simulation time 2255123053 ps
CPU time 2.27 seconds
Started May 28 01:50:52 PM PDT 24
Finished May 28 01:50:56 PM PDT 24
Peak memory 199192 kb
Host smart-ce5d8f84-8c41-4228-851f-070fb3ff0422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798483998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.798483998
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3553036543
Short name T549
Test name
Test status
Simulation time 163009786698 ps
CPU time 112.23 seconds
Started May 28 01:50:57 PM PDT 24
Finished May 28 01:52:50 PM PDT 24
Peak memory 200464 kb
Host smart-d6ea876a-c6b4-4e3d-a530-aba3c217dfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553036543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3553036543
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2032249727
Short name T520
Test name
Test status
Simulation time 24965256 ps
CPU time 0.57 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 01:51:09 PM PDT 24
Peak memory 195888 kb
Host smart-ae9314a1-98d2-4bcf-82bd-a1540fcb6e2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032249727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2032249727
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.454351592
Short name T133
Test name
Test status
Simulation time 103808937989 ps
CPU time 297.05 seconds
Started May 28 01:50:57 PM PDT 24
Finished May 28 01:55:55 PM PDT 24
Peak memory 200540 kb
Host smart-a22456a5-f743-438e-870a-81d76d65b31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454351592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.454351592
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2203719343
Short name T844
Test name
Test status
Simulation time 171858483299 ps
CPU time 79.89 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 01:52:28 PM PDT 24
Peak memory 200440 kb
Host smart-48d5346e-d89d-4a1e-8bb8-981ed272afc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203719343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2203719343
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2606844853
Short name T181
Test name
Test status
Simulation time 27965778776 ps
CPU time 14.51 seconds
Started May 28 01:51:08 PM PDT 24
Finished May 28 01:51:25 PM PDT 24
Peak memory 200464 kb
Host smart-3642f7ed-d94f-4d21-82d5-bb9fbcb6d58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606844853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2606844853
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3618955689
Short name T751
Test name
Test status
Simulation time 44532681493 ps
CPU time 41.04 seconds
Started May 28 01:51:04 PM PDT 24
Finished May 28 01:51:48 PM PDT 24
Peak memory 200464 kb
Host smart-7bfa484a-9e5e-4709-9a06-e784e1cd8e8e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618955689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3618955689
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3847786065
Short name T540
Test name
Test status
Simulation time 181544105428 ps
CPU time 657 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 02:02:06 PM PDT 24
Peak memory 200468 kb
Host smart-be667542-8e7c-4b2b-9f3a-1f021412bcdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3847786065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3847786065
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1177672269
Short name T968
Test name
Test status
Simulation time 8570431843 ps
CPU time 4.99 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 01:51:14 PM PDT 24
Peak memory 198264 kb
Host smart-04541b68-7e70-4008-b97e-e70864eb98e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177672269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1177672269
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2026432990
Short name T839
Test name
Test status
Simulation time 23026983633 ps
CPU time 36.28 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 01:51:45 PM PDT 24
Peak memory 200272 kb
Host smart-1ae44a9c-d571-4faf-bf8b-1c81b9ac288a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026432990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2026432990
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.4267248902
Short name T1076
Test name
Test status
Simulation time 12607813632 ps
CPU time 772.52 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 02:04:01 PM PDT 24
Peak memory 200536 kb
Host smart-5003c2a3-4558-464c-9374-ccd83028e21e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267248902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.4267248902
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3388406832
Short name T339
Test name
Test status
Simulation time 3700803270 ps
CPU time 8.11 seconds
Started May 28 01:51:06 PM PDT 24
Finished May 28 01:51:18 PM PDT 24
Peak memory 198524 kb
Host smart-8853ea93-1c15-494d-b3e9-f95b9e16b49c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388406832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3388406832
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2456809675
Short name T456
Test name
Test status
Simulation time 16733224391 ps
CPU time 17.84 seconds
Started May 28 01:51:08 PM PDT 24
Finished May 28 01:51:28 PM PDT 24
Peak memory 200524 kb
Host smart-2ba049f7-b3b5-4fa6-8c95-1890dee437bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456809675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2456809675
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.613074999
Short name T299
Test name
Test status
Simulation time 5190494602 ps
CPU time 2.94 seconds
Started May 28 01:51:04 PM PDT 24
Finished May 28 01:51:09 PM PDT 24
Peak memory 196508 kb
Host smart-4d4bc405-3db4-4b8e-8791-468235014a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613074999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.613074999
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.4214235872
Short name T688
Test name
Test status
Simulation time 5682643559 ps
CPU time 29.33 seconds
Started May 28 01:50:57 PM PDT 24
Finished May 28 01:51:27 PM PDT 24
Peak memory 200456 kb
Host smart-3d3834b3-8102-4042-ae77-795f220373a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214235872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.4214235872
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3605544636
Short name T20
Test name
Test status
Simulation time 15215298871 ps
CPU time 27.86 seconds
Started May 28 01:51:04 PM PDT 24
Finished May 28 01:51:34 PM PDT 24
Peak memory 200524 kb
Host smart-93f26480-2043-4193-adb4-dbf81b5dfde6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605544636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3605544636
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3895373714
Short name T1173
Test name
Test status
Simulation time 124605306928 ps
CPU time 158.63 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 01:53:47 PM PDT 24
Peak memory 217020 kb
Host smart-f091421f-dd09-4243-bd57-50ce9e898b1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895373714 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3895373714
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.4195538438
Short name T298
Test name
Test status
Simulation time 2192244410 ps
CPU time 1.77 seconds
Started May 28 01:51:07 PM PDT 24
Finished May 28 01:51:12 PM PDT 24
Peak memory 198900 kb
Host smart-d972e2d8-e18e-49d0-ac18-45c5ddb1e39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195538438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.4195538438
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2006293357
Short name T936
Test name
Test status
Simulation time 189339668957 ps
CPU time 130.11 seconds
Started May 28 01:50:51 PM PDT 24
Finished May 28 01:53:03 PM PDT 24
Peak memory 200448 kb
Host smart-cd7760b0-6471-4439-85f1-f69dc7f6f9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006293357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2006293357
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1958254362
Short name T391
Test name
Test status
Simulation time 13195702 ps
CPU time 0.55 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:49:09 PM PDT 24
Peak memory 194876 kb
Host smart-90068898-6023-4e92-8197-6f87ca77f991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958254362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1958254362
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1047769303
Short name T1162
Test name
Test status
Simulation time 131113658093 ps
CPU time 61.69 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:50:10 PM PDT 24
Peak memory 200548 kb
Host smart-d377ad64-471f-4d40-9f6a-7bbfd741c8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047769303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1047769303
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2929413274
Short name T829
Test name
Test status
Simulation time 32045142744 ps
CPU time 13.28 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:49:23 PM PDT 24
Peak memory 198520 kb
Host smart-ff3a37e3-619c-409f-bd6c-12523c58cb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929413274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2929413274
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1864372033
Short name T419
Test name
Test status
Simulation time 24112989472 ps
CPU time 11.55 seconds
Started May 28 01:49:01 PM PDT 24
Finished May 28 01:49:19 PM PDT 24
Peak memory 200432 kb
Host smart-ccb47aec-cedf-4354-879c-57b556aee286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864372033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1864372033
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2856670740
Short name T555
Test name
Test status
Simulation time 15308331715 ps
CPU time 3.41 seconds
Started May 28 01:49:00 PM PDT 24
Finished May 28 01:49:09 PM PDT 24
Peak memory 200552 kb
Host smart-0bbbf974-4778-46ae-b04c-cee03f26b7ef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856670740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2856670740
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1149099269
Short name T921
Test name
Test status
Simulation time 65193908413 ps
CPU time 400.35 seconds
Started May 28 01:49:00 PM PDT 24
Finished May 28 01:55:45 PM PDT 24
Peak memory 200476 kb
Host smart-7f76f720-ebaf-4dd6-8231-0b7f37a6d587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149099269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1149099269
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3274793279
Short name T1018
Test name
Test status
Simulation time 3048125557 ps
CPU time 5.59 seconds
Started May 28 01:48:58 PM PDT 24
Finished May 28 01:49:05 PM PDT 24
Peak memory 198984 kb
Host smart-bbe61910-431d-4129-b60c-da5d5a7223b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274793279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3274793279
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.4029514407
Short name T770
Test name
Test status
Simulation time 63351054120 ps
CPU time 27.71 seconds
Started May 28 01:49:00 PM PDT 24
Finished May 28 01:49:32 PM PDT 24
Peak memory 200436 kb
Host smart-1c8f56dd-24fe-46f5-8332-807121099b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029514407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.4029514407
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3897551094
Short name T535
Test name
Test status
Simulation time 8301474426 ps
CPU time 96.5 seconds
Started May 28 01:48:59 PM PDT 24
Finished May 28 01:50:40 PM PDT 24
Peak memory 200456 kb
Host smart-f56fa92f-d6cc-4cd1-a34b-111e039debcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3897551094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3897551094
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2091459567
Short name T571
Test name
Test status
Simulation time 2952042511 ps
CPU time 3.54 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:49:13 PM PDT 24
Peak memory 198808 kb
Host smart-bc0101d4-2315-4e82-bf16-dab67df27151
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2091459567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2091459567
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.4115999620
Short name T1095
Test name
Test status
Simulation time 235654367921 ps
CPU time 262.38 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:53:32 PM PDT 24
Peak memory 200468 kb
Host smart-371ca94d-ccb8-476b-b7b8-41c5aa3f726b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115999620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.4115999620
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.4225592443
Short name T1057
Test name
Test status
Simulation time 4251208119 ps
CPU time 7.7 seconds
Started May 28 01:48:58 PM PDT 24
Finished May 28 01:49:09 PM PDT 24
Peak memory 196544 kb
Host smart-57c91093-8e47-4fb8-a00f-1035bfc4f343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225592443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.4225592443
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.767349694
Short name T101
Test name
Test status
Simulation time 108520649 ps
CPU time 0.83 seconds
Started May 28 01:48:58 PM PDT 24
Finished May 28 01:49:02 PM PDT 24
Peak memory 218944 kb
Host smart-dbee30b4-e34b-433e-8901-588c0b78db6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767349694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.767349694
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1234513156
Short name T470
Test name
Test status
Simulation time 6207379953 ps
CPU time 22.01 seconds
Started May 28 01:48:56 PM PDT 24
Finished May 28 01:49:19 PM PDT 24
Peak memory 200344 kb
Host smart-82a78108-d669-4bab-a247-54cb072e6a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234513156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1234513156
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2750687195
Short name T757
Test name
Test status
Simulation time 527351049023 ps
CPU time 124.92 seconds
Started May 28 01:49:00 PM PDT 24
Finished May 28 01:51:11 PM PDT 24
Peak memory 208884 kb
Host smart-8558aa88-8378-4afc-badf-c436b57effdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750687195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2750687195
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1915644451
Short name T144
Test name
Test status
Simulation time 38206936702 ps
CPU time 163.68 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:51:53 PM PDT 24
Peak memory 208724 kb
Host smart-8e6589ba-4cb0-47e2-80eb-93e71aef01c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915644451 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1915644451
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.44241620
Short name T398
Test name
Test status
Simulation time 1320792569 ps
CPU time 2.73 seconds
Started May 28 01:49:00 PM PDT 24
Finished May 28 01:49:09 PM PDT 24
Peak memory 198800 kb
Host smart-55e8b9af-1f25-4e1f-821b-f1e21263d6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44241620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.44241620
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1426452507
Short name T279
Test name
Test status
Simulation time 37947991661 ps
CPU time 31.61 seconds
Started May 28 01:48:58 PM PDT 24
Finished May 28 01:49:32 PM PDT 24
Peak memory 200460 kb
Host smart-25fc74ae-f430-4e7b-a23c-f70a98b25bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426452507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1426452507
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3712739231
Short name T31
Test name
Test status
Simulation time 21984436 ps
CPU time 0.56 seconds
Started May 28 01:51:08 PM PDT 24
Finished May 28 01:51:11 PM PDT 24
Peak memory 195904 kb
Host smart-2bf7542f-2e78-405b-82f2-614b28d482aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712739231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3712739231
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2472715378
Short name T588
Test name
Test status
Simulation time 108077203622 ps
CPU time 335.71 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 01:56:45 PM PDT 24
Peak memory 200472 kb
Host smart-517f3d4a-7dc1-4884-92fc-d31a499e8f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472715378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2472715378
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2473241782
Short name T103
Test name
Test status
Simulation time 35106031154 ps
CPU time 15.14 seconds
Started May 28 01:51:04 PM PDT 24
Finished May 28 01:51:23 PM PDT 24
Peak memory 200488 kb
Host smart-619e0cd8-1482-4dc7-a350-a30dc8317653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473241782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2473241782
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3231939323
Short name T429
Test name
Test status
Simulation time 7224477073 ps
CPU time 13.28 seconds
Started May 28 01:51:04 PM PDT 24
Finished May 28 01:51:19 PM PDT 24
Peak memory 197236 kb
Host smart-0c21bce9-c33a-492a-a6f3-0b66855b40c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231939323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3231939323
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2163199295
Short name T363
Test name
Test status
Simulation time 233068589365 ps
CPU time 273.33 seconds
Started May 28 01:51:06 PM PDT 24
Finished May 28 01:55:43 PM PDT 24
Peak memory 200520 kb
Host smart-463e733b-3ad7-40ad-a018-7891c5bb27af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2163199295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2163199295
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.373998396
Short name T978
Test name
Test status
Simulation time 4429422252 ps
CPU time 7.69 seconds
Started May 28 01:51:04 PM PDT 24
Finished May 28 01:51:15 PM PDT 24
Peak memory 196412 kb
Host smart-291e0cfa-98b6-4131-8342-6fafa21c31e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373998396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.373998396
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2180261464
Short name T689
Test name
Test status
Simulation time 62152352094 ps
CPU time 104.06 seconds
Started May 28 01:51:07 PM PDT 24
Finished May 28 01:52:54 PM PDT 24
Peak memory 200768 kb
Host smart-0f7465cd-e9df-4666-8716-cbda0fc5d94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180261464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2180261464
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3066016170
Short name T1158
Test name
Test status
Simulation time 20028673289 ps
CPU time 947.52 seconds
Started May 28 01:51:04 PM PDT 24
Finished May 28 02:06:55 PM PDT 24
Peak memory 200728 kb
Host smart-425abbf8-9bbb-47ce-99b5-7672ff93b01d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3066016170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3066016170
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1907609951
Short name T692
Test name
Test status
Simulation time 7194829299 ps
CPU time 33.95 seconds
Started May 28 01:51:04 PM PDT 24
Finished May 28 01:51:41 PM PDT 24
Peak memory 198768 kb
Host smart-aaddba63-2e15-4de2-998a-e6146fb7c47f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1907609951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1907609951
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.35318018
Short name T184
Test name
Test status
Simulation time 73839077891 ps
CPU time 21.44 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 01:51:29 PM PDT 24
Peak memory 200492 kb
Host smart-4ba20adb-6b27-49ca-b334-b17edc766af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35318018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.35318018
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.974548429
Short name T1077
Test name
Test status
Simulation time 3535332232 ps
CPU time 1.53 seconds
Started May 28 01:51:08 PM PDT 24
Finished May 28 01:51:12 PM PDT 24
Peak memory 196812 kb
Host smart-0c65c9b9-9c78-4c7e-861e-220d9996d8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974548429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.974548429
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2345690164
Short name T383
Test name
Test status
Simulation time 505675545 ps
CPU time 2.33 seconds
Started May 28 01:51:04 PM PDT 24
Finished May 28 01:51:10 PM PDT 24
Peak memory 198808 kb
Host smart-be8ff2c2-9a2e-4c27-bce3-748f58bc28b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345690164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2345690164
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1811611563
Short name T857
Test name
Test status
Simulation time 25661933103 ps
CPU time 46.02 seconds
Started May 28 01:51:07 PM PDT 24
Finished May 28 01:51:56 PM PDT 24
Peak memory 200468 kb
Host smart-6ef86cba-01c4-42c3-a376-e4f8a406d666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811611563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1811611563
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.829246184
Short name T64
Test name
Test status
Simulation time 83034355878 ps
CPU time 1120.66 seconds
Started May 28 01:51:04 PM PDT 24
Finished May 28 02:09:48 PM PDT 24
Peak memory 216956 kb
Host smart-f7058773-3b88-4993-95b0-6a636a0ae65f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829246184 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.829246184
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.222927272
Short name T567
Test name
Test status
Simulation time 327098134 ps
CPU time 1.42 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 01:51:10 PM PDT 24
Peak memory 200108 kb
Host smart-a1b4c24d-8ee6-47f1-bc56-a0438277c107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222927272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.222927272
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2058151414
Short name T603
Test name
Test status
Simulation time 44517131373 ps
CPU time 15.56 seconds
Started May 28 01:51:06 PM PDT 24
Finished May 28 01:51:25 PM PDT 24
Peak memory 200300 kb
Host smart-6a8236b3-4be4-4828-b033-8bba32f5ba0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058151414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2058151414
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.4131925077
Short name T1031
Test name
Test status
Simulation time 44200409 ps
CPU time 0.55 seconds
Started May 28 01:51:18 PM PDT 24
Finished May 28 01:51:22 PM PDT 24
Peak memory 195292 kb
Host smart-f66829af-b2f5-4209-b20e-600663f872e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131925077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.4131925077
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1783409758
Short name T282
Test name
Test status
Simulation time 41914828281 ps
CPU time 67.95 seconds
Started May 28 01:51:06 PM PDT 24
Finished May 28 01:52:17 PM PDT 24
Peak memory 200556 kb
Host smart-3aaa0020-9f4c-4c68-840d-174823415cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783409758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1783409758
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.588777394
Short name T1072
Test name
Test status
Simulation time 21828695712 ps
CPU time 52.91 seconds
Started May 28 01:51:09 PM PDT 24
Finished May 28 01:52:04 PM PDT 24
Peak memory 200440 kb
Host smart-013d4e0c-f1b3-4622-87b3-a372718dbedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588777394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.588777394
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1555852389
Short name T148
Test name
Test status
Simulation time 30126914890 ps
CPU time 14.03 seconds
Started May 28 01:51:06 PM PDT 24
Finished May 28 01:51:23 PM PDT 24
Peak memory 200472 kb
Host smart-787184c4-42e3-4463-87fc-e0524e2e3ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555852389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1555852389
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.4013439402
Short name T728
Test name
Test status
Simulation time 328833655091 ps
CPU time 123.37 seconds
Started May 28 01:51:04 PM PDT 24
Finished May 28 01:53:09 PM PDT 24
Peak memory 200480 kb
Host smart-457ae455-4102-4749-8e2a-6c7375afd90d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013439402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.4013439402
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.363402167
Short name T903
Test name
Test status
Simulation time 53944111625 ps
CPU time 161.78 seconds
Started May 28 01:51:17 PM PDT 24
Finished May 28 01:54:01 PM PDT 24
Peak memory 200500 kb
Host smart-8ba38749-adb5-4b9e-bc36-f4c6ac0131d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=363402167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.363402167
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1380869253
Short name T1042
Test name
Test status
Simulation time 3440513640 ps
CPU time 1.61 seconds
Started May 28 01:51:08 PM PDT 24
Finished May 28 01:51:12 PM PDT 24
Peak memory 199820 kb
Host smart-97dc6d68-3c57-4857-b15a-0e61f7e2306f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380869253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1380869253
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.694197876
Short name T791
Test name
Test status
Simulation time 11479251431 ps
CPU time 330.71 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 01:56:49 PM PDT 24
Peak memory 200472 kb
Host smart-eba572c4-d912-4029-ad69-c1efe050255b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=694197876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.694197876
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3570005515
Short name T478
Test name
Test status
Simulation time 3919506899 ps
CPU time 31.48 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 01:51:39 PM PDT 24
Peak memory 199432 kb
Host smart-3c97719a-8f61-4942-8367-1407f56df826
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3570005515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3570005515
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.372964801
Short name T149
Test name
Test status
Simulation time 47468848867 ps
CPU time 35.62 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 01:51:44 PM PDT 24
Peak memory 200444 kb
Host smart-7e4e82ec-538e-43bd-bdf5-4a41a2a20e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372964801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.372964801
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.515094117
Short name T947
Test name
Test status
Simulation time 6461836673 ps
CPU time 3 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 01:51:12 PM PDT 24
Peak memory 196804 kb
Host smart-7b3cf5cc-e5c1-4403-9a5c-c1ba34ef0bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515094117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.515094117
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3594925361
Short name T395
Test name
Test status
Simulation time 505607555 ps
CPU time 2.21 seconds
Started May 28 01:51:08 PM PDT 24
Finished May 28 01:51:13 PM PDT 24
Peak memory 200384 kb
Host smart-481a747e-cf21-48ad-a6a5-568460fc8515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594925361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3594925361
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1275282822
Short name T1107
Test name
Test status
Simulation time 217478004724 ps
CPU time 1039.9 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 02:08:37 PM PDT 24
Peak memory 200544 kb
Host smart-09fa38a1-42fa-434a-b9d1-a563e34d84d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275282822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1275282822
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3310397002
Short name T334
Test name
Test status
Simulation time 17584502727 ps
CPU time 151.67 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 01:53:49 PM PDT 24
Peak memory 215932 kb
Host smart-a4dbd6c6-a542-45c5-95de-820c0dcf29f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310397002 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3310397002
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2846687799
Short name T1071
Test name
Test status
Simulation time 7321411765 ps
CPU time 9.79 seconds
Started May 28 01:51:07 PM PDT 24
Finished May 28 01:51:20 PM PDT 24
Peak memory 200392 kb
Host smart-435d980a-3cf6-408f-aac9-94f2bbfc8aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846687799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2846687799
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.4201501395
Short name T820
Test name
Test status
Simulation time 58157408581 ps
CPU time 96.86 seconds
Started May 28 01:51:05 PM PDT 24
Finished May 28 01:52:45 PM PDT 24
Peak memory 200456 kb
Host smart-a6ad7021-68df-403b-b8f0-eb9bddadbd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201501395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.4201501395
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.970840041
Short name T1065
Test name
Test status
Simulation time 11117343 ps
CPU time 0.55 seconds
Started May 28 01:51:17 PM PDT 24
Finished May 28 01:51:21 PM PDT 24
Peak memory 195864 kb
Host smart-5652e0e8-13dd-4260-9464-13faa32cbce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970840041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.970840041
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2514256790
Short name T137
Test name
Test status
Simulation time 103701925928 ps
CPU time 33.74 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 01:51:52 PM PDT 24
Peak memory 200476 kb
Host smart-940dbc82-4cea-42a6-865f-19ebd2f6bf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514256790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2514256790
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3905076166
Short name T235
Test name
Test status
Simulation time 67333095971 ps
CPU time 88.86 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 01:52:48 PM PDT 24
Peak memory 200444 kb
Host smart-e9cae79b-e1eb-493a-ac1c-17a6529b989c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905076166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3905076166
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2827681668
Short name T524
Test name
Test status
Simulation time 37151476979 ps
CPU time 30.02 seconds
Started May 28 01:51:15 PM PDT 24
Finished May 28 01:51:46 PM PDT 24
Peak memory 200504 kb
Host smart-08a0a016-8b00-4633-b857-a3b0a28d8565
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827681668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2827681668
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.4283995484
Short name T666
Test name
Test status
Simulation time 133114682415 ps
CPU time 1446.62 seconds
Started May 28 01:51:15 PM PDT 24
Finished May 28 02:15:24 PM PDT 24
Peak memory 200548 kb
Host smart-3783d506-2827-4269-bb73-ad1bf3d0ac1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4283995484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4283995484
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1747890214
Short name T893
Test name
Test status
Simulation time 610460367 ps
CPU time 1.67 seconds
Started May 28 01:51:17 PM PDT 24
Finished May 28 01:51:22 PM PDT 24
Peak memory 198480 kb
Host smart-5a1b9543-0fcb-4a8e-a534-69556a5d332a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747890214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1747890214
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.207838671
Short name T348
Test name
Test status
Simulation time 7303052021 ps
CPU time 7.23 seconds
Started May 28 01:51:17 PM PDT 24
Finished May 28 01:51:27 PM PDT 24
Peak memory 200776 kb
Host smart-214a5853-60fa-4827-91e0-bbe11b837fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207838671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.207838671
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.787163773
Short name T465
Test name
Test status
Simulation time 5011808831 ps
CPU time 157.3 seconds
Started May 28 01:51:17 PM PDT 24
Finished May 28 01:53:58 PM PDT 24
Peak memory 200460 kb
Host smart-91886042-ed25-40a3-a9ca-2c48068dac0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787163773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.787163773
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2809401457
Short name T491
Test name
Test status
Simulation time 4968440206 ps
CPU time 38.52 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 01:51:56 PM PDT 24
Peak memory 199272 kb
Host smart-aecadf22-c664-477c-901f-590380cf8b15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809401457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2809401457
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3836696452
Short name T1089
Test name
Test status
Simulation time 19306589195 ps
CPU time 11.46 seconds
Started May 28 01:51:18 PM PDT 24
Finished May 28 01:51:33 PM PDT 24
Peak memory 200444 kb
Host smart-50c87f1e-5d43-4af1-94ed-59cbe56a089e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836696452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3836696452
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3169282522
Short name T963
Test name
Test status
Simulation time 1587776765 ps
CPU time 3.32 seconds
Started May 28 01:51:17 PM PDT 24
Finished May 28 01:51:24 PM PDT 24
Peak memory 196152 kb
Host smart-19f39707-248d-4175-85e2-cc41a1618fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169282522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3169282522
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.4094114663
Short name T736
Test name
Test status
Simulation time 6314746451 ps
CPU time 5.67 seconds
Started May 28 01:51:19 PM PDT 24
Finished May 28 01:51:28 PM PDT 24
Peak memory 200448 kb
Host smart-f38dad79-b21a-41cb-b50e-0190c818c75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094114663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.4094114663
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3355311581
Short name T735
Test name
Test status
Simulation time 225629678244 ps
CPU time 373.98 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 01:57:33 PM PDT 24
Peak memory 200520 kb
Host smart-cdb47fea-7ec8-4c1a-a622-b5d0b0d2559e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355311581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3355311581
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2369064604
Short name T338
Test name
Test status
Simulation time 21336293892 ps
CPU time 174.26 seconds
Started May 28 01:51:20 PM PDT 24
Finished May 28 01:54:17 PM PDT 24
Peak memory 216968 kb
Host smart-6bc62462-58c9-4938-8b6f-115983f09cc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369064604 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2369064604
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.854458154
Short name T542
Test name
Test status
Simulation time 1605628935 ps
CPU time 2.69 seconds
Started May 28 01:51:19 PM PDT 24
Finished May 28 01:51:25 PM PDT 24
Peak memory 199404 kb
Host smart-8082b319-50ad-4666-9bea-c1b2e5f4e954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854458154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.854458154
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.9454359
Short name T1067
Test name
Test status
Simulation time 21149129351 ps
CPU time 35.45 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 01:51:53 PM PDT 24
Peak memory 200576 kb
Host smart-abe3b0ad-ab91-4c96-a92f-63aa81856c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9454359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.9454359
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1927268054
Short name T1078
Test name
Test status
Simulation time 25112382 ps
CPU time 0.53 seconds
Started May 28 01:51:18 PM PDT 24
Finished May 28 01:51:22 PM PDT 24
Peak memory 194880 kb
Host smart-569ebe28-7387-4109-a4b2-cbb872927111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927268054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1927268054
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1725795974
Short name T572
Test name
Test status
Simulation time 34843476474 ps
CPU time 32.16 seconds
Started May 28 01:51:15 PM PDT 24
Finished May 28 01:51:48 PM PDT 24
Peak memory 200532 kb
Host smart-4c6a6922-2d75-4118-84ae-347fe791699e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725795974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1725795974
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2235234336
Short name T928
Test name
Test status
Simulation time 19812423860 ps
CPU time 30.4 seconds
Started May 28 01:51:18 PM PDT 24
Finished May 28 01:51:52 PM PDT 24
Peak memory 200448 kb
Host smart-ea176642-112e-476e-a27b-a5b1145cadba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235234336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2235234336
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.74433655
Short name T1113
Test name
Test status
Simulation time 111200385026 ps
CPU time 53.88 seconds
Started May 28 01:51:17 PM PDT 24
Finished May 28 01:52:15 PM PDT 24
Peak memory 200444 kb
Host smart-5a4521ec-a959-4787-b223-8966f60925f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74433655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.74433655
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3849076926
Short name T628
Test name
Test status
Simulation time 49187117895 ps
CPU time 117.11 seconds
Started May 28 01:51:17 PM PDT 24
Finished May 28 01:53:17 PM PDT 24
Peak memory 200472 kb
Host smart-1faa52ef-e83a-470b-9c6e-ae74aeddac19
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849076926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3849076926
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.4239947875
Short name T382
Test name
Test status
Simulation time 110775892826 ps
CPU time 254.96 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 01:55:33 PM PDT 24
Peak memory 200520 kb
Host smart-9fbdc1f5-4073-4206-8d15-2f1c68310493
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4239947875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.4239947875
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1495485940
Short name T403
Test name
Test status
Simulation time 3818594656 ps
CPU time 3.72 seconds
Started May 28 01:51:18 PM PDT 24
Finished May 28 01:51:25 PM PDT 24
Peak memory 198092 kb
Host smart-f754b019-71ce-4e16-ac41-e5766e7b88d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495485940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1495485940
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3580950005
Short name T907
Test name
Test status
Simulation time 33615004753 ps
CPU time 43.91 seconds
Started May 28 01:51:18 PM PDT 24
Finished May 28 01:52:06 PM PDT 24
Peak memory 200600 kb
Host smart-3f0751ca-fbfc-4b0a-864d-b2d056e7e6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580950005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3580950005
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3199649044
Short name T843
Test name
Test status
Simulation time 9873777125 ps
CPU time 519.7 seconds
Started May 28 01:51:20 PM PDT 24
Finished May 28 02:00:02 PM PDT 24
Peak memory 200536 kb
Host smart-5c645d6d-46cd-4a82-ba8f-1f221de26b5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3199649044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3199649044
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1654317812
Short name T357
Test name
Test status
Simulation time 1819333043 ps
CPU time 2.7 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 01:51:22 PM PDT 24
Peak memory 198412 kb
Host smart-fa4ef8aa-092d-4017-b2ee-45bf2faa394b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1654317812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1654317812
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3449528350
Short name T827
Test name
Test status
Simulation time 180654109888 ps
CPU time 97.67 seconds
Started May 28 01:51:20 PM PDT 24
Finished May 28 01:53:00 PM PDT 24
Peak memory 200432 kb
Host smart-5f149305-7560-46f5-8cab-4710f67c4909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449528350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3449528350
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.828601911
Short name T793
Test name
Test status
Simulation time 4472612097 ps
CPU time 2.17 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 01:51:21 PM PDT 24
Peak memory 196548 kb
Host smart-89b92f71-a795-4e18-92f6-52d181daae28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828601911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.828601911
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.6500768
Short name T601
Test name
Test status
Simulation time 636092984 ps
CPU time 3.25 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 01:51:22 PM PDT 24
Peak memory 199436 kb
Host smart-6046a554-7cfa-4b17-8170-0ea1d1a4952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6500768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.6500768
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2041968738
Short name T606
Test name
Test status
Simulation time 519107743698 ps
CPU time 572.87 seconds
Started May 28 01:51:17 PM PDT 24
Finished May 28 02:00:54 PM PDT 24
Peak memory 225468 kb
Host smart-118846a7-02d4-4a80-a191-74eefd50242e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041968738 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2041968738
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.777806468
Short name T1115
Test name
Test status
Simulation time 7325608956 ps
CPU time 8.55 seconds
Started May 28 01:51:18 PM PDT 24
Finished May 28 01:51:30 PM PDT 24
Peak memory 200372 kb
Host smart-70d1092c-0f8b-4bf2-9785-12f35d32d8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777806468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.777806468
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1599857649
Short name T531
Test name
Test status
Simulation time 22973517312 ps
CPU time 24.79 seconds
Started May 28 01:51:15 PM PDT 24
Finished May 28 01:51:41 PM PDT 24
Peak memory 200480 kb
Host smart-2c3e942e-95e5-4924-8e7f-f2588613957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599857649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1599857649
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2266454474
Short name T463
Test name
Test status
Simulation time 99706448 ps
CPU time 0.56 seconds
Started May 28 01:51:32 PM PDT 24
Finished May 28 01:51:35 PM PDT 24
Peak memory 195848 kb
Host smart-ca6cfc09-8acb-45f1-b57a-0ff2d19d4fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266454474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2266454474
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1645458554
Short name T505
Test name
Test status
Simulation time 55805720792 ps
CPU time 26.14 seconds
Started May 28 01:51:20 PM PDT 24
Finished May 28 01:51:49 PM PDT 24
Peak memory 200468 kb
Host smart-7ce98108-caee-464c-982a-81244c9c78c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645458554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1645458554
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.4165888939
Short name T1142
Test name
Test status
Simulation time 144141369977 ps
CPU time 70.12 seconds
Started May 28 01:51:18 PM PDT 24
Finished May 28 01:52:32 PM PDT 24
Peak memory 200528 kb
Host smart-5e2bb103-cdb3-4627-a010-dd9117647075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165888939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.4165888939
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1246611090
Short name T213
Test name
Test status
Simulation time 48576569448 ps
CPU time 48.21 seconds
Started May 28 01:51:17 PM PDT 24
Finished May 28 01:52:09 PM PDT 24
Peak memory 200508 kb
Host smart-16e5555b-b2f8-4347-91c7-a1344a8ef3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246611090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1246611090
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.434045443
Short name T1039
Test name
Test status
Simulation time 143351317075 ps
CPU time 158.92 seconds
Started May 28 01:51:17 PM PDT 24
Finished May 28 01:53:59 PM PDT 24
Peak memory 200480 kb
Host smart-f6d007f4-d1f0-4ddc-9c6a-c3d68f1d094c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434045443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.434045443
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2614285410
Short name T885
Test name
Test status
Simulation time 140788639747 ps
CPU time 396.89 seconds
Started May 28 01:51:29 PM PDT 24
Finished May 28 01:58:06 PM PDT 24
Peak memory 200548 kb
Host smart-60af0d9d-2283-44e0-98b4-7420def81ecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2614285410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2614285410
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.4046598244
Short name T664
Test name
Test status
Simulation time 321739420 ps
CPU time 0.75 seconds
Started May 28 01:51:16 PM PDT 24
Finished May 28 01:51:20 PM PDT 24
Peak memory 197504 kb
Host smart-5461a27a-0101-405a-8ed3-9a783a119000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046598244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.4046598244
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3632044013
Short name T371
Test name
Test status
Simulation time 177125995611 ps
CPU time 72.42 seconds
Started May 28 01:51:18 PM PDT 24
Finished May 28 01:52:34 PM PDT 24
Peak memory 216956 kb
Host smart-0b3847dd-95d7-45cf-8a58-b70c96931e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632044013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3632044013
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.947555148
Short name T790
Test name
Test status
Simulation time 27100955725 ps
CPU time 374.09 seconds
Started May 28 01:51:18 PM PDT 24
Finished May 28 01:57:36 PM PDT 24
Peak memory 200556 kb
Host smart-744f093f-db1b-4c0d-8931-df3a06a46560
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=947555148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.947555148
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3673113825
Short name T582
Test name
Test status
Simulation time 3945068640 ps
CPU time 6.82 seconds
Started May 28 01:51:18 PM PDT 24
Finished May 28 01:51:29 PM PDT 24
Peak memory 198844 kb
Host smart-e32f6522-7ae4-4e1b-847b-3ba25b1bdbdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3673113825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3673113825
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1832842615
Short name T1086
Test name
Test status
Simulation time 50572507604 ps
CPU time 16.41 seconds
Started May 28 01:51:18 PM PDT 24
Finished May 28 01:51:38 PM PDT 24
Peak memory 200436 kb
Host smart-fdfa484c-5a1b-46cf-8e1e-a516d1c03d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832842615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1832842615
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3555532771
Short name T923
Test name
Test status
Simulation time 3814189388 ps
CPU time 3.48 seconds
Started May 28 01:51:18 PM PDT 24
Finished May 28 01:51:25 PM PDT 24
Peak memory 196508 kb
Host smart-8be8c7f6-029d-485a-8522-186f36744ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555532771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3555532771
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.612165618
Short name T533
Test name
Test status
Simulation time 832492769 ps
CPU time 0.95 seconds
Started May 28 01:51:17 PM PDT 24
Finished May 28 01:51:21 PM PDT 24
Peak memory 198992 kb
Host smart-6bb67930-aa5d-44c6-b2ef-9373bba0a480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612165618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.612165618
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.589449282
Short name T165
Test name
Test status
Simulation time 144008138917 ps
CPU time 189.04 seconds
Started May 28 01:51:30 PM PDT 24
Finished May 28 01:54:42 PM PDT 24
Peak memory 200540 kb
Host smart-101e1467-12d5-4988-ad34-c79d1d65e622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589449282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.589449282
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3266437417
Short name T498
Test name
Test status
Simulation time 95786457763 ps
CPU time 533.03 seconds
Started May 28 01:51:30 PM PDT 24
Finished May 28 02:00:25 PM PDT 24
Peak memory 216984 kb
Host smart-a0ef64e6-231a-47bf-ba0f-15629447abd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266437417 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3266437417
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1586939005
Short name T919
Test name
Test status
Simulation time 1891748670 ps
CPU time 2.24 seconds
Started May 28 01:51:18 PM PDT 24
Finished May 28 01:51:23 PM PDT 24
Peak memory 199796 kb
Host smart-2b9c2253-d261-456a-ad56-63d7c554fad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586939005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1586939005
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3818681428
Short name T565
Test name
Test status
Simulation time 45544112750 ps
CPU time 40.86 seconds
Started May 28 01:51:20 PM PDT 24
Finished May 28 01:52:03 PM PDT 24
Peak memory 200540 kb
Host smart-a57313e8-8474-4f18-9fe2-ed84846dbacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818681428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3818681428
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.4174262625
Short name T1032
Test name
Test status
Simulation time 37058062 ps
CPU time 0.56 seconds
Started May 28 01:51:32 PM PDT 24
Finished May 28 01:51:35 PM PDT 24
Peak memory 195848 kb
Host smart-57aaae6b-6592-42cd-9a81-1a0105ff6e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174262625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.4174262625
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.652879946
Short name T1137
Test name
Test status
Simulation time 108381386654 ps
CPU time 175.67 seconds
Started May 28 01:51:31 PM PDT 24
Finished May 28 01:54:30 PM PDT 24
Peak memory 200544 kb
Host smart-e104b118-b46a-4a5e-84c8-3711efbefe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652879946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.652879946
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.4263826641
Short name T327
Test name
Test status
Simulation time 111581382523 ps
CPU time 208.44 seconds
Started May 28 01:51:32 PM PDT 24
Finished May 28 01:55:03 PM PDT 24
Peak memory 200452 kb
Host smart-a2e47c71-96b7-40a4-92bc-b863b4744448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263826641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.4263826641
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2194548136
Short name T237
Test name
Test status
Simulation time 197792491508 ps
CPU time 18.97 seconds
Started May 28 01:51:28 PM PDT 24
Finished May 28 01:51:48 PM PDT 24
Peak memory 200520 kb
Host smart-8017bdc2-823b-4a0a-8b12-cbd72f7ae005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194548136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2194548136
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2378050110
Short name T739
Test name
Test status
Simulation time 45951692382 ps
CPU time 11.44 seconds
Started May 28 01:51:29 PM PDT 24
Finished May 28 01:51:43 PM PDT 24
Peak memory 200484 kb
Host smart-e3422699-0333-4891-b9a4-92e02826d41f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378050110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2378050110
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1219312942
Short name T676
Test name
Test status
Simulation time 141168817932 ps
CPU time 1029.31 seconds
Started May 28 01:51:29 PM PDT 24
Finished May 28 02:08:40 PM PDT 24
Peak memory 200520 kb
Host smart-fea6112d-c86c-4bd3-9595-77949817a5b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1219312942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1219312942
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2876458571
Short name T428
Test name
Test status
Simulation time 8424977242 ps
CPU time 8.66 seconds
Started May 28 01:51:31 PM PDT 24
Finished May 28 01:51:42 PM PDT 24
Peak memory 200152 kb
Host smart-484adb00-a586-4bb6-876e-d7beae25e752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876458571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2876458571
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2331796933
Short name T899
Test name
Test status
Simulation time 198767652766 ps
CPU time 119.54 seconds
Started May 28 01:51:25 PM PDT 24
Finished May 28 01:53:25 PM PDT 24
Peak memory 200932 kb
Host smart-31b83fb0-de14-4201-8ee7-dbf4d85f009a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331796933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2331796933
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3470241750
Short name T958
Test name
Test status
Simulation time 22123666295 ps
CPU time 297.78 seconds
Started May 28 01:51:29 PM PDT 24
Finished May 28 01:56:29 PM PDT 24
Peak memory 200508 kb
Host smart-a10ce464-cd3c-436b-b45b-3fb1a2010007
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3470241750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3470241750
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1227304357
Short name T775
Test name
Test status
Simulation time 4693479780 ps
CPU time 10.44 seconds
Started May 28 01:51:30 PM PDT 24
Finished May 28 01:51:43 PM PDT 24
Peak memory 198736 kb
Host smart-4ab2caec-20eb-480f-9459-d0a7cfa170ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1227304357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1227304357
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.294771024
Short name T1129
Test name
Test status
Simulation time 34408729949 ps
CPU time 30.58 seconds
Started May 28 01:51:29 PM PDT 24
Finished May 28 01:52:02 PM PDT 24
Peak memory 200612 kb
Host smart-94c5b4c6-7f5d-4788-ba4e-d0ef25d5280b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294771024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.294771024
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.4289234252
Short name T872
Test name
Test status
Simulation time 41756288287 ps
CPU time 20.3 seconds
Started May 28 01:51:29 PM PDT 24
Finished May 28 01:51:52 PM PDT 24
Peak memory 196520 kb
Host smart-b3aa2892-9c36-44e0-9bf0-e1358a55ca74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289234252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.4289234252
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3110540126
Short name T469
Test name
Test status
Simulation time 6015594759 ps
CPU time 6.16 seconds
Started May 28 01:51:29 PM PDT 24
Finished May 28 01:51:38 PM PDT 24
Peak memory 200336 kb
Host smart-d4699951-ecf3-448c-ae99-852420269645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110540126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3110540126
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2119458365
Short name T15
Test name
Test status
Simulation time 66221939827 ps
CPU time 107.7 seconds
Started May 28 01:51:29 PM PDT 24
Finished May 28 01:53:19 PM PDT 24
Peak memory 200776 kb
Host smart-a49e038d-912b-4672-a9a9-cbf59e544f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119458365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2119458365
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1967096862
Short name T675
Test name
Test status
Simulation time 150787892764 ps
CPU time 283.09 seconds
Started May 28 01:51:31 PM PDT 24
Finished May 28 01:56:17 PM PDT 24
Peak memory 217224 kb
Host smart-0ede81e7-7ccc-4e47-8246-2b5234a257a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967096862 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1967096862
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.871002907
Short name T557
Test name
Test status
Simulation time 814468401 ps
CPU time 2.64 seconds
Started May 28 01:51:31 PM PDT 24
Finished May 28 01:51:37 PM PDT 24
Peak memory 198984 kb
Host smart-ffce794d-deb9-4e22-8970-bd357575a6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871002907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.871002907
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1524111227
Short name T431
Test name
Test status
Simulation time 42565256900 ps
CPU time 12.2 seconds
Started May 28 01:51:30 PM PDT 24
Finished May 28 01:51:44 PM PDT 24
Peak memory 199088 kb
Host smart-d5214f3d-6cf6-4bd4-9cc4-d597e0168c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524111227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1524111227
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2312481670
Short name T802
Test name
Test status
Simulation time 56076017 ps
CPU time 0.59 seconds
Started May 28 01:51:31 PM PDT 24
Finished May 28 01:51:35 PM PDT 24
Peak memory 195880 kb
Host smart-cdeb1367-bb6f-4cbf-b92b-8800d60dbd1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312481670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2312481670
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2478337619
Short name T373
Test name
Test status
Simulation time 9231078102 ps
CPU time 15.63 seconds
Started May 28 01:51:30 PM PDT 24
Finished May 28 01:51:48 PM PDT 24
Peak memory 199232 kb
Host smart-d8d05ef5-0885-44fd-a9fc-729b860169d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478337619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2478337619
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.464670091
Short name T859
Test name
Test status
Simulation time 90960826617 ps
CPU time 194.48 seconds
Started May 28 01:51:33 PM PDT 24
Finished May 28 01:54:50 PM PDT 24
Peak memory 200324 kb
Host smart-b074e739-bb0e-4ae8-8260-7e9ce73fa624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464670091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.464670091
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3415443912
Short name T697
Test name
Test status
Simulation time 10990422586 ps
CPU time 21.5 seconds
Started May 28 01:51:32 PM PDT 24
Finished May 28 01:51:57 PM PDT 24
Peak memory 200664 kb
Host smart-f7026a8a-6ae6-4e29-957d-9b64080b50ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415443912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3415443912
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.811062545
Short name T756
Test name
Test status
Simulation time 49983886785 ps
CPU time 10.26 seconds
Started May 28 01:51:30 PM PDT 24
Finished May 28 01:51:42 PM PDT 24
Peak memory 200476 kb
Host smart-33c8cae6-ac60-42c7-8910-9d827e934521
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811062545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.811062545
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1541855880
Short name T544
Test name
Test status
Simulation time 99776892506 ps
CPU time 286.36 seconds
Started May 28 01:51:32 PM PDT 24
Finished May 28 01:56:21 PM PDT 24
Peak memory 200428 kb
Host smart-5f7bf207-6cff-40fd-aa9f-31056f8c740c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541855880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1541855880
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2868335657
Short name T341
Test name
Test status
Simulation time 9888160664 ps
CPU time 5.87 seconds
Started May 28 01:51:29 PM PDT 24
Finished May 28 01:51:36 PM PDT 24
Peak memory 200248 kb
Host smart-7855b93f-2a03-4903-85c9-681c3c5f43e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868335657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2868335657
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3164019519
Short name T441
Test name
Test status
Simulation time 3504602552 ps
CPU time 1.89 seconds
Started May 28 01:51:34 PM PDT 24
Finished May 28 01:51:38 PM PDT 24
Peak memory 195424 kb
Host smart-54691151-8c9b-4ae1-acc7-5c9ebaf2a6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164019519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3164019519
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1421550704
Short name T396
Test name
Test status
Simulation time 28559344272 ps
CPU time 392.71 seconds
Started May 28 01:51:30 PM PDT 24
Finished May 28 01:58:06 PM PDT 24
Peak memory 200564 kb
Host smart-f0d6fa90-915f-490c-a85e-f9cd53f9ae84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1421550704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1421550704
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.693998885
Short name T889
Test name
Test status
Simulation time 3597882224 ps
CPU time 28.37 seconds
Started May 28 01:51:32 PM PDT 24
Finished May 28 01:52:03 PM PDT 24
Peak memory 199908 kb
Host smart-929a037f-545a-413d-bedc-ecb0fc718409
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=693998885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.693998885
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3716014854
Short name T553
Test name
Test status
Simulation time 29031809786 ps
CPU time 21.15 seconds
Started May 28 01:51:33 PM PDT 24
Finished May 28 01:51:57 PM PDT 24
Peak memory 200248 kb
Host smart-f5a3c607-5e4a-4f26-897c-174f56bee13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716014854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3716014854
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1651988433
Short name T307
Test name
Test status
Simulation time 31076123175 ps
CPU time 27.39 seconds
Started May 28 01:51:31 PM PDT 24
Finished May 28 01:52:01 PM PDT 24
Peak memory 196516 kb
Host smart-f7be896d-9450-45a0-b365-35c42970bcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651988433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1651988433
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1883468372
Short name T412
Test name
Test status
Simulation time 743453889 ps
CPU time 1.03 seconds
Started May 28 01:51:32 PM PDT 24
Finished May 28 01:51:36 PM PDT 24
Peak memory 198956 kb
Host smart-5bd1108d-ec81-4a00-92c9-6e7e6428644e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883468372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1883468372
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.971873616
Short name T509
Test name
Test status
Simulation time 335227056948 ps
CPU time 216.08 seconds
Started May 28 01:51:30 PM PDT 24
Finished May 28 01:55:08 PM PDT 24
Peak memory 200516 kb
Host smart-59bf290d-6e56-45b6-bdfd-7a93cd61b985
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971873616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.971873616
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.353890556
Short name T187
Test name
Test status
Simulation time 59662571147 ps
CPU time 342.74 seconds
Started May 28 01:51:32 PM PDT 24
Finished May 28 01:57:17 PM PDT 24
Peak memory 216992 kb
Host smart-38267f26-b736-4ac9-9ddb-4b1c1a3c49de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353890556 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.353890556
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1910100744
Short name T310
Test name
Test status
Simulation time 8047372947 ps
CPU time 14.15 seconds
Started May 28 01:51:31 PM PDT 24
Finished May 28 01:51:48 PM PDT 24
Peak memory 200168 kb
Host smart-a8edadf4-915c-48e7-b6bf-a589a6655c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910100744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1910100744
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1282007940
Short name T696
Test name
Test status
Simulation time 107909465281 ps
CPU time 44.76 seconds
Started May 28 01:51:31 PM PDT 24
Finished May 28 01:52:18 PM PDT 24
Peak memory 200448 kb
Host smart-9f4a9dc7-7026-4670-913f-59e2de456509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282007940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1282007940
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2463681656
Short name T868
Test name
Test status
Simulation time 21155933 ps
CPU time 0.54 seconds
Started May 28 01:51:41 PM PDT 24
Finished May 28 01:51:42 PM PDT 24
Peak memory 195908 kb
Host smart-f7269847-b0f3-4792-b436-0b7482fbeb91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463681656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2463681656
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1471448474
Short name T497
Test name
Test status
Simulation time 59368343831 ps
CPU time 30.37 seconds
Started May 28 01:51:30 PM PDT 24
Finished May 28 01:52:02 PM PDT 24
Peak memory 200540 kb
Host smart-c4d6dc41-1917-4377-adcd-c95267c7d43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471448474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1471448474
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.557002111
Short name T1169
Test name
Test status
Simulation time 226107255171 ps
CPU time 580.98 seconds
Started May 28 01:51:30 PM PDT 24
Finished May 28 02:01:14 PM PDT 24
Peak memory 200448 kb
Host smart-e739986a-5ae5-4344-81c0-d2b350a34263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557002111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.557002111
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3573659624
Short name T227
Test name
Test status
Simulation time 43441239502 ps
CPU time 38.96 seconds
Started May 28 01:51:31 PM PDT 24
Finished May 28 01:52:12 PM PDT 24
Peak memory 200508 kb
Host smart-4d81fa72-3adc-4490-b283-d71db724d639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573659624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3573659624
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1202356524
Short name T940
Test name
Test status
Simulation time 41752166352 ps
CPU time 18.42 seconds
Started May 28 01:51:32 PM PDT 24
Finished May 28 01:51:53 PM PDT 24
Peak memory 200472 kb
Host smart-94c5c3fd-993c-4742-9938-5210ca3b9708
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202356524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1202356524
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1525600329
Short name T545
Test name
Test status
Simulation time 281192973780 ps
CPU time 591.29 seconds
Started May 28 01:51:42 PM PDT 24
Finished May 28 02:01:36 PM PDT 24
Peak memory 200576 kb
Host smart-922d1824-ec0e-4c44-a4d4-e4bbf219084c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525600329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1525600329
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.224706605
Short name T1055
Test name
Test status
Simulation time 10281214833 ps
CPU time 22.31 seconds
Started May 28 01:51:44 PM PDT 24
Finished May 28 01:52:09 PM PDT 24
Peak memory 200516 kb
Host smart-af86a235-930d-4e85-af37-41f171783ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224706605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.224706605
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3770765288
Short name T277
Test name
Test status
Simulation time 45170353169 ps
CPU time 123.87 seconds
Started May 28 01:51:32 PM PDT 24
Finished May 28 01:53:39 PM PDT 24
Peak memory 209180 kb
Host smart-db8e79dc-ffd8-4392-8fb7-ed1347d354fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770765288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3770765288
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2742441613
Short name T871
Test name
Test status
Simulation time 15772945257 ps
CPU time 954.77 seconds
Started May 28 01:51:42 PM PDT 24
Finished May 28 02:07:38 PM PDT 24
Peak memory 200536 kb
Host smart-0af70c6f-3e0c-4989-806a-1df38671efe0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2742441613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2742441613
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3058681492
Short name T623
Test name
Test status
Simulation time 3616160618 ps
CPU time 6.43 seconds
Started May 28 01:51:31 PM PDT 24
Finished May 28 01:51:40 PM PDT 24
Peak memory 199308 kb
Host smart-7c214678-cbec-4692-9642-20bb7433193a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3058681492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3058681492
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.4213858139
Short name T653
Test name
Test status
Simulation time 52417247433 ps
CPU time 45.1 seconds
Started May 28 01:51:41 PM PDT 24
Finished May 28 01:52:27 PM PDT 24
Peak memory 200380 kb
Host smart-b8c978ee-7685-4597-9719-65d8740f5bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213858139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.4213858139
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2835738193
Short name T1123
Test name
Test status
Simulation time 6625802925 ps
CPU time 3.24 seconds
Started May 28 01:51:30 PM PDT 24
Finished May 28 01:51:35 PM PDT 24
Peak memory 196456 kb
Host smart-da404851-b2e5-4fe9-86f5-88bee30a6d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835738193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2835738193
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3643815075
Short name T554
Test name
Test status
Simulation time 484994379 ps
CPU time 2.42 seconds
Started May 28 01:51:29 PM PDT 24
Finished May 28 01:51:34 PM PDT 24
Peak memory 200136 kb
Host smart-0fad7968-0079-43a9-ae14-168cee860b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643815075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3643815075
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1055288151
Short name T325
Test name
Test status
Simulation time 177636797240 ps
CPU time 162.27 seconds
Started May 28 01:51:41 PM PDT 24
Finished May 28 01:54:25 PM PDT 24
Peak memory 200552 kb
Host smart-0ffb57be-20cc-44bb-acbb-6be2a97bc86a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055288151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1055288151
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2951714754
Short name T1047
Test name
Test status
Simulation time 61545308038 ps
CPU time 1060.15 seconds
Started May 28 01:51:39 PM PDT 24
Finished May 28 02:09:20 PM PDT 24
Peak memory 225396 kb
Host smart-f15b2650-b35f-46bf-be4d-7b54af903c3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951714754 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2951714754
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.962875769
Short name T104
Test name
Test status
Simulation time 518829516 ps
CPU time 2.16 seconds
Started May 28 01:51:44 PM PDT 24
Finished May 28 01:51:49 PM PDT 24
Peak memory 200136 kb
Host smart-59f53463-69d1-4900-af22-189352d1a5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962875769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.962875769
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3775267299
Short name T842
Test name
Test status
Simulation time 21807540708 ps
CPU time 34.3 seconds
Started May 28 01:51:31 PM PDT 24
Finished May 28 01:52:08 PM PDT 24
Peak memory 200400 kb
Host smart-48ec7967-96ef-4e72-b739-cbcc2d1a7b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775267299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3775267299
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3700632305
Short name T354
Test name
Test status
Simulation time 38793631 ps
CPU time 0.56 seconds
Started May 28 01:51:42 PM PDT 24
Finished May 28 01:51:45 PM PDT 24
Peak memory 195908 kb
Host smart-ba1e9049-3a50-47d3-adaf-0d79e44d4e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700632305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3700632305
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1621874665
Short name T379
Test name
Test status
Simulation time 44183885110 ps
CPU time 19.06 seconds
Started May 28 01:51:43 PM PDT 24
Finished May 28 01:52:05 PM PDT 24
Peak memory 200468 kb
Host smart-7c4aa2ec-384b-42bd-a43a-97365e632cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621874665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1621874665
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1710571669
Short name T281
Test name
Test status
Simulation time 105137468495 ps
CPU time 191.55 seconds
Started May 28 01:51:43 PM PDT 24
Finished May 28 01:54:57 PM PDT 24
Peak memory 200468 kb
Host smart-7b908b57-2f16-4d5a-9bb0-beb2b834ce39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710571669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1710571669
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.376505389
Short name T1114
Test name
Test status
Simulation time 8311166619 ps
CPU time 6.75 seconds
Started May 28 01:51:43 PM PDT 24
Finished May 28 01:51:52 PM PDT 24
Peak memory 200500 kb
Host smart-5b033920-3217-40aa-ab1c-7b83efdfa876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376505389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.376505389
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3077420175
Short name T598
Test name
Test status
Simulation time 10264168478 ps
CPU time 5.97 seconds
Started May 28 01:51:43 PM PDT 24
Finished May 28 01:51:52 PM PDT 24
Peak memory 200392 kb
Host smart-fcb0977b-65be-4c48-abb4-5fec56c9e5c5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077420175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3077420175
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.640103573
Short name T320
Test name
Test status
Simulation time 119472803538 ps
CPU time 1023.05 seconds
Started May 28 01:51:42 PM PDT 24
Finished May 28 02:08:47 PM PDT 24
Peak memory 200360 kb
Host smart-1e773ea2-49b5-425e-ba8d-5503d02b7636
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=640103573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.640103573
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2441963064
Short name T512
Test name
Test status
Simulation time 7726613986 ps
CPU time 10.36 seconds
Started May 28 01:51:44 PM PDT 24
Finished May 28 01:51:57 PM PDT 24
Peak memory 199712 kb
Host smart-6360aa72-9729-4aed-b16e-4971abb57ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441963064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2441963064
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1431556623
Short name T372
Test name
Test status
Simulation time 7073865304 ps
CPU time 6.27 seconds
Started May 28 01:51:42 PM PDT 24
Finished May 28 01:51:50 PM PDT 24
Peak memory 200544 kb
Host smart-a308381a-2100-411d-b1a3-1a360d34bd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431556623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1431556623
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2127287224
Short name T974
Test name
Test status
Simulation time 16605439698 ps
CPU time 432.58 seconds
Started May 28 01:51:41 PM PDT 24
Finished May 28 01:58:55 PM PDT 24
Peak memory 200448 kb
Host smart-0e55877b-4c9e-441d-ac77-506a29f36fe2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2127287224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2127287224
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2578740597
Short name T73
Test name
Test status
Simulation time 3369414076 ps
CPU time 29.71 seconds
Started May 28 01:51:41 PM PDT 24
Finished May 28 01:52:12 PM PDT 24
Peak memory 198672 kb
Host smart-e7b20ef3-5f5d-4cbd-abc9-50e0add38db4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2578740597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2578740597
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3780732860
Short name T1038
Test name
Test status
Simulation time 125816700260 ps
CPU time 51.4 seconds
Started May 28 01:51:44 PM PDT 24
Finished May 28 01:52:38 PM PDT 24
Peak memory 200528 kb
Host smart-18a48df7-0206-4dd6-bb8d-db1ebe64407d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780732860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3780732860
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.437430366
Short name T996
Test name
Test status
Simulation time 32144820499 ps
CPU time 7.57 seconds
Started May 28 01:51:44 PM PDT 24
Finished May 28 01:51:54 PM PDT 24
Peak memory 196524 kb
Host smart-fb6d80f5-dbcc-414e-ac65-6a1a2d65e4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437430366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.437430366
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1976664252
Short name T1044
Test name
Test status
Simulation time 569197603 ps
CPU time 1.34 seconds
Started May 28 01:51:44 PM PDT 24
Finished May 28 01:51:48 PM PDT 24
Peak memory 199032 kb
Host smart-880b4e79-1725-49db-9495-360abb70f1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976664252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1976664252
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1953693835
Short name T143
Test name
Test status
Simulation time 192981031414 ps
CPU time 638.98 seconds
Started May 28 01:51:44 PM PDT 24
Finished May 28 02:02:26 PM PDT 24
Peak memory 200560 kb
Host smart-c7abacbe-6e7e-43cb-a276-fafd2e849c4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953693835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1953693835
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1557326217
Short name T74
Test name
Test status
Simulation time 30302200312 ps
CPU time 379.78 seconds
Started May 28 01:51:42 PM PDT 24
Finished May 28 01:58:04 PM PDT 24
Peak memory 215976 kb
Host smart-22e1aea5-297f-4fcb-b52d-5a3978a2c097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557326217 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1557326217
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2772978854
Short name T913
Test name
Test status
Simulation time 535127809 ps
CPU time 1.69 seconds
Started May 28 01:51:43 PM PDT 24
Finished May 28 01:51:47 PM PDT 24
Peak memory 198772 kb
Host smart-50bada74-23dc-4565-8c93-20478a88edeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772978854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2772978854
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1261112891
Short name T768
Test name
Test status
Simulation time 162162616557 ps
CPU time 110.75 seconds
Started May 28 01:51:40 PM PDT 24
Finished May 28 01:53:32 PM PDT 24
Peak memory 200552 kb
Host smart-81a5fd81-e05f-41c6-8f57-af7f425f4284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261112891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1261112891
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1900293877
Short name T853
Test name
Test status
Simulation time 13875962 ps
CPU time 0.54 seconds
Started May 28 01:51:43 PM PDT 24
Finished May 28 01:51:45 PM PDT 24
Peak memory 195900 kb
Host smart-4ea47910-1116-468c-8434-85f8ad5830d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900293877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1900293877
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1264413065
Short name T646
Test name
Test status
Simulation time 69419276866 ps
CPU time 83.93 seconds
Started May 28 01:51:43 PM PDT 24
Finished May 28 01:53:10 PM PDT 24
Peak memory 200432 kb
Host smart-157b0bfd-a3ab-4989-a66b-51ef9d3aaf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264413065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1264413065
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2916662533
Short name T139
Test name
Test status
Simulation time 97337248170 ps
CPU time 41.11 seconds
Started May 28 01:51:44 PM PDT 24
Finished May 28 01:52:28 PM PDT 24
Peak memory 200020 kb
Host smart-529cd793-666b-44f8-8a36-dbe39c25221d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916662533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2916662533
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.41263941
Short name T167
Test name
Test status
Simulation time 27255346009 ps
CPU time 22.63 seconds
Started May 28 01:51:43 PM PDT 24
Finished May 28 01:52:08 PM PDT 24
Peak memory 200556 kb
Host smart-458c550c-c83b-461a-b593-5d9803960e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41263941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.41263941
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1142266704
Short name T786
Test name
Test status
Simulation time 337293878831 ps
CPU time 371.09 seconds
Started May 28 01:51:44 PM PDT 24
Finished May 28 01:57:58 PM PDT 24
Peak memory 200432 kb
Host smart-c8a1c79b-af9d-4ac9-8165-c25922ea71cf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142266704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1142266704
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1829224534
Short name T1022
Test name
Test status
Simulation time 151339096702 ps
CPU time 491.17 seconds
Started May 28 01:51:44 PM PDT 24
Finished May 28 01:59:58 PM PDT 24
Peak memory 200572 kb
Host smart-c4085dfc-761a-42ab-bff5-9a9fea4525b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1829224534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1829224534
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1850965570
Short name T370
Test name
Test status
Simulation time 4987339005 ps
CPU time 9.53 seconds
Started May 28 01:51:42 PM PDT 24
Finished May 28 01:51:54 PM PDT 24
Peak memory 198592 kb
Host smart-04daa9d2-6eb5-43c3-9635-c7aa6cc4035b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850965570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1850965570
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2399096269
Short name T1143
Test name
Test status
Simulation time 94349125672 ps
CPU time 190.11 seconds
Started May 28 01:51:42 PM PDT 24
Finished May 28 01:54:54 PM PDT 24
Peak memory 199444 kb
Host smart-fffa224c-dce9-4297-84b2-bb357cd171bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399096269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2399096269
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3493336315
Short name T449
Test name
Test status
Simulation time 9281653379 ps
CPU time 454.15 seconds
Started May 28 01:51:43 PM PDT 24
Finished May 28 01:59:20 PM PDT 24
Peak memory 200468 kb
Host smart-b7c47a6d-50c8-48ae-ad19-9ab8de8a461b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3493336315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3493336315
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1260520489
Short name T902
Test name
Test status
Simulation time 4997241743 ps
CPU time 20.93 seconds
Started May 28 01:51:43 PM PDT 24
Finished May 28 01:52:07 PM PDT 24
Peak memory 198560 kb
Host smart-66e2bbc9-0699-4824-87c5-d3276a59fdbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260520489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1260520489
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3200427224
Short name T174
Test name
Test status
Simulation time 136407879630 ps
CPU time 67.23 seconds
Started May 28 01:51:42 PM PDT 24
Finished May 28 01:52:50 PM PDT 24
Peak memory 200496 kb
Host smart-d1134dba-b83e-45a7-b5bd-33a928f6e9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200427224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3200427224
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1543532628
Short name T966
Test name
Test status
Simulation time 38740210933 ps
CPU time 16.38 seconds
Started May 28 01:51:44 PM PDT 24
Finished May 28 01:52:03 PM PDT 24
Peak memory 196264 kb
Host smart-68945101-ea4f-4a26-a148-61b53e59fbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543532628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1543532628
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3530598710
Short name T856
Test name
Test status
Simulation time 124852677 ps
CPU time 1.01 seconds
Started May 28 01:51:45 PM PDT 24
Finished May 28 01:51:48 PM PDT 24
Peak memory 198900 kb
Host smart-9fecff63-752f-4753-a689-752f55086922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530598710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3530598710
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3802597446
Short name T1053
Test name
Test status
Simulation time 107867064093 ps
CPU time 53.74 seconds
Started May 28 01:51:45 PM PDT 24
Finished May 28 01:52:41 PM PDT 24
Peak memory 200728 kb
Host smart-ff4f0e57-3ceb-4ece-9f16-3ac7203b160b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802597446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3802597446
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2985319764
Short name T631
Test name
Test status
Simulation time 84852999258 ps
CPU time 267.71 seconds
Started May 28 01:51:44 PM PDT 24
Finished May 28 01:56:14 PM PDT 24
Peak memory 214564 kb
Host smart-4cc78d2c-9861-4f55-bfc2-898f57012297
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985319764 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2985319764
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.437000868
Short name T796
Test name
Test status
Simulation time 1530270464 ps
CPU time 1.58 seconds
Started May 28 01:51:43 PM PDT 24
Finished May 28 01:51:47 PM PDT 24
Peak memory 198952 kb
Host smart-c109a624-2831-4685-8b6a-f7f2f40ecfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437000868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.437000868
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3516889282
Short name T330
Test name
Test status
Simulation time 56587375950 ps
CPU time 21.93 seconds
Started May 28 01:51:45 PM PDT 24
Finished May 28 01:52:09 PM PDT 24
Peak memory 200748 kb
Host smart-b4928a3b-ee69-42ef-854b-272706266df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516889282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3516889282
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2783588186
Short name T30
Test name
Test status
Simulation time 15923511 ps
CPU time 0.56 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:49:09 PM PDT 24
Peak memory 195804 kb
Host smart-5bcc7a17-06d8-4d9a-a4d2-eff773c54dcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783588186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2783588186
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1819920721
Short name T841
Test name
Test status
Simulation time 48693532857 ps
CPU time 20.4 seconds
Started May 28 01:49:00 PM PDT 24
Finished May 28 01:49:26 PM PDT 24
Peak memory 200500 kb
Host smart-5a81974d-b653-4316-9b2c-cec890a3627c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819920721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1819920721
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.4149757154
Short name T424
Test name
Test status
Simulation time 177322031640 ps
CPU time 54.3 seconds
Started May 28 01:49:01 PM PDT 24
Finished May 28 01:50:01 PM PDT 24
Peak memory 200480 kb
Host smart-79856c8f-ad5e-4403-8ae1-6c23501b71ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149757154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.4149757154
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_intr.432841455
Short name T909
Test name
Test status
Simulation time 227264476261 ps
CPU time 348.74 seconds
Started May 28 01:49:01 PM PDT 24
Finished May 28 01:54:56 PM PDT 24
Peak memory 198808 kb
Host smart-a4e52042-4c49-4482-a7bc-310dbabb69ce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432841455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.432841455
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.4204019623
Short name T895
Test name
Test status
Simulation time 117490125802 ps
CPU time 601.46 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:59:09 PM PDT 24
Peak memory 200536 kb
Host smart-c941e9aa-bb1b-4dfc-af86-5b825799ecc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204019623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.4204019623
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3505104669
Short name T673
Test name
Test status
Simulation time 9696826250 ps
CPU time 19.77 seconds
Started May 28 01:48:59 PM PDT 24
Finished May 28 01:49:23 PM PDT 24
Peak memory 199120 kb
Host smart-7ad814af-2f27-4c2a-bfb4-f25d5ba3c841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505104669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3505104669
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.1397069948
Short name T605
Test name
Test status
Simulation time 45716049215 ps
CPU time 41.94 seconds
Started May 28 01:48:59 PM PDT 24
Finished May 28 01:49:46 PM PDT 24
Peak memory 200016 kb
Host smart-30a58c5c-481e-401e-9eed-977d3f2a1264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397069948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1397069948
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.122336859
Short name T1130
Test name
Test status
Simulation time 8467039652 ps
CPU time 116.57 seconds
Started May 28 01:48:58 PM PDT 24
Finished May 28 01:50:58 PM PDT 24
Peak memory 200492 kb
Host smart-4851f90c-6a72-4ba4-826e-45cd0f790e48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=122336859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.122336859
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2384339181
Short name T380
Test name
Test status
Simulation time 3988868652 ps
CPU time 33.18 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:49:42 PM PDT 24
Peak memory 198636 kb
Host smart-15dc6237-19f1-4374-b2f6-1bc8f0bd1037
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384339181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2384339181
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3735366902
Short name T761
Test name
Test status
Simulation time 107121259019 ps
CPU time 184.37 seconds
Started May 28 01:49:01 PM PDT 24
Finished May 28 01:52:11 PM PDT 24
Peak memory 200444 kb
Host smart-ebc3291a-b7cb-4f74-8053-fb318f2a1b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735366902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3735366902
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.164889988
Short name T7
Test name
Test status
Simulation time 4740485086 ps
CPU time 2.7 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:49:12 PM PDT 24
Peak memory 196544 kb
Host smart-670f1e3b-e3b5-4fd3-bfe3-9e221bbaf14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164889988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.164889988
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3270322046
Short name T800
Test name
Test status
Simulation time 922131305 ps
CPU time 1.73 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:49:11 PM PDT 24
Peak memory 199128 kb
Host smart-0e64cc2e-fa5a-4f87-b280-d471fbd751dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270322046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3270322046
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2899731550
Short name T18
Test name
Test status
Simulation time 41498771246 ps
CPU time 77.85 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:50:26 PM PDT 24
Peak memory 200476 kb
Host smart-db44993e-0a7b-4b33-8a66-812e323b7ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899731550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2899731550
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.398156359
Short name T71
Test name
Test status
Simulation time 564676959468 ps
CPU time 269.79 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:53:39 PM PDT 24
Peak memory 216996 kb
Host smart-4f082782-5ed1-4869-a02e-7a162665bd8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398156359 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.398156359
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.536825349
Short name T744
Test name
Test status
Simulation time 1549344374 ps
CPU time 1.97 seconds
Started May 28 01:48:59 PM PDT 24
Finished May 28 01:49:05 PM PDT 24
Peak memory 198964 kb
Host smart-c851492e-1bc6-4cfd-9fef-e8d9d0f8440b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536825349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.536825349
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2872095659
Short name T43
Test name
Test status
Simulation time 21721993675 ps
CPU time 8.51 seconds
Started May 28 01:48:56 PM PDT 24
Finished May 28 01:49:05 PM PDT 24
Peak memory 200536 kb
Host smart-0562670e-7339-411b-9c8d-3f52d1179042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872095659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2872095659
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1505318567
Short name T261
Test name
Test status
Simulation time 25040924014 ps
CPU time 12.63 seconds
Started May 28 01:51:40 PM PDT 24
Finished May 28 01:51:53 PM PDT 24
Peak memory 200416 kb
Host smart-503328f2-e0ed-41a3-a338-08e458d6f302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505318567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1505318567
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1804984140
Short name T814
Test name
Test status
Simulation time 33573193281 ps
CPU time 28.07 seconds
Started May 28 01:51:55 PM PDT 24
Finished May 28 01:52:27 PM PDT 24
Peak memory 200512 kb
Host smart-50800f93-4cfe-4e62-943f-bf89dce5d623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804984140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1804984140
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.211499812
Short name T680
Test name
Test status
Simulation time 50168267339 ps
CPU time 476.83 seconds
Started May 28 01:51:53 PM PDT 24
Finished May 28 01:59:53 PM PDT 24
Peak memory 212544 kb
Host smart-bc14f2fb-755c-4f81-96d3-851c570c856c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211499812 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.211499812
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.366049207
Short name T964
Test name
Test status
Simulation time 151060601170 ps
CPU time 121.17 seconds
Started May 28 01:51:53 PM PDT 24
Finished May 28 01:53:57 PM PDT 24
Peak memory 200568 kb
Host smart-5e4e5b6d-968a-4d5e-91a2-1576739cbcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366049207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.366049207
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3299339703
Short name T635
Test name
Test status
Simulation time 12589317510 ps
CPU time 146.18 seconds
Started May 28 01:51:54 PM PDT 24
Finished May 28 01:54:24 PM PDT 24
Peak memory 208744 kb
Host smart-f399f11d-e2cd-43b4-bec7-9c8993608a57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299339703 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3299339703
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3482528809
Short name T700
Test name
Test status
Simulation time 68547385305 ps
CPU time 21.38 seconds
Started May 28 01:51:54 PM PDT 24
Finished May 28 01:52:19 PM PDT 24
Peak memory 200508 kb
Host smart-145c7f18-76fe-4f19-af68-d9b844b93cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482528809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3482528809
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1499253335
Short name T1178
Test name
Test status
Simulation time 21602925201 ps
CPU time 234.18 seconds
Started May 28 01:51:55 PM PDT 24
Finished May 28 01:55:53 PM PDT 24
Peak memory 216068 kb
Host smart-efab1d7c-0607-4798-9bdb-162f2a0be5a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499253335 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1499253335
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1405293793
Short name T530
Test name
Test status
Simulation time 211489815412 ps
CPU time 168.79 seconds
Started May 28 01:51:59 PM PDT 24
Finished May 28 01:54:50 PM PDT 24
Peak memory 200488 kb
Host smart-ab2869b7-29d4-46a5-833c-20f03bb826a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405293793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1405293793
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2554889228
Short name T569
Test name
Test status
Simulation time 98343284985 ps
CPU time 619.62 seconds
Started May 28 01:51:58 PM PDT 24
Finished May 28 02:02:20 PM PDT 24
Peak memory 217008 kb
Host smart-e744e3c2-8d48-4dfc-b1c9-3cb8fcb52e46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554889228 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2554889228
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3068187004
Short name T516
Test name
Test status
Simulation time 22464599175 ps
CPU time 227.88 seconds
Started May 28 01:51:57 PM PDT 24
Finished May 28 01:55:48 PM PDT 24
Peak memory 208744 kb
Host smart-6932b46c-10f6-4e3b-9cea-418fd24622d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068187004 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3068187004
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2851856044
Short name T218
Test name
Test status
Simulation time 48118797480 ps
CPU time 41.28 seconds
Started May 28 01:51:57 PM PDT 24
Finished May 28 01:52:42 PM PDT 24
Peak memory 200540 kb
Host smart-1b08a90c-9e80-4fbe-8882-f450b2bbbe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851856044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2851856044
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2532077768
Short name T66
Test name
Test status
Simulation time 88452339045 ps
CPU time 537.79 seconds
Started May 28 01:51:53 PM PDT 24
Finished May 28 02:00:54 PM PDT 24
Peak memory 217264 kb
Host smart-f3813026-c8df-4048-b8c4-63383d886a03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532077768 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2532077768
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3718811517
Short name T135
Test name
Test status
Simulation time 26134304880 ps
CPU time 45.42 seconds
Started May 28 01:51:55 PM PDT 24
Finished May 28 01:52:44 PM PDT 24
Peak memory 200540 kb
Host smart-920eeb4b-8c1b-437b-ba15-ab46d76db1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718811517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3718811517
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.3713963619
Short name T446
Test name
Test status
Simulation time 49964517239 ps
CPU time 548.68 seconds
Started May 28 01:51:55 PM PDT 24
Finished May 28 02:01:08 PM PDT 24
Peak memory 217264 kb
Host smart-372c4540-5dd0-4245-a04e-6da916d36749
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713963619 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3713963619
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.775425941
Short name T151
Test name
Test status
Simulation time 67163738075 ps
CPU time 36.07 seconds
Started May 28 01:51:56 PM PDT 24
Finished May 28 01:52:36 PM PDT 24
Peak memory 200472 kb
Host smart-7d088244-8aa7-494c-9668-38cae9cbfee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775425941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.775425941
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2489069773
Short name T1068
Test name
Test status
Simulation time 19993095294 ps
CPU time 45.19 seconds
Started May 28 01:51:53 PM PDT 24
Finished May 28 01:52:42 PM PDT 24
Peak memory 200536 kb
Host smart-10f58ded-e997-475b-884b-3f6e6df0836d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489069773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2489069773
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2018813201
Short name T894
Test name
Test status
Simulation time 16330688551 ps
CPU time 67.59 seconds
Started May 28 01:51:55 PM PDT 24
Finished May 28 01:53:07 PM PDT 24
Peak memory 217272 kb
Host smart-93f6923a-14e0-414a-ac2d-be6def8fe5c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018813201 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2018813201
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3287957142
Short name T351
Test name
Test status
Simulation time 28800990 ps
CPU time 0.57 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:49:10 PM PDT 24
Peak memory 194632 kb
Host smart-be638022-88b7-481a-b059-4e50be9d4cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287957142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3287957142
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.492151025
Short name T564
Test name
Test status
Simulation time 66095126862 ps
CPU time 53.49 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:50:03 PM PDT 24
Peak memory 199724 kb
Host smart-22c336a7-613f-433d-87bf-273202be8e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492151025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.492151025
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1992587423
Short name T855
Test name
Test status
Simulation time 20831235321 ps
CPU time 14.72 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:49:23 PM PDT 24
Peak memory 200472 kb
Host smart-e68b404d-b03f-4a8b-b1e9-fab73b223f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992587423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1992587423
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.3814191295
Short name T630
Test name
Test status
Simulation time 33636605037 ps
CPU time 70.77 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:50:19 PM PDT 24
Peak memory 200340 kb
Host smart-f03e91d9-6fba-4b9a-8fbf-9d838e9f3453
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814191295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3814191295
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.4231706601
Short name T421
Test name
Test status
Simulation time 65783971688 ps
CPU time 182.09 seconds
Started May 28 01:48:57 PM PDT 24
Finished May 28 01:52:00 PM PDT 24
Peak memory 200508 kb
Host smart-04c6b59b-8ccb-48dd-b236-2c10cdb27094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231706601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.4231706601
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2199399267
Short name T604
Test name
Test status
Simulation time 7523856857 ps
CPU time 14.93 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:49:23 PM PDT 24
Peak memory 199800 kb
Host smart-4ec05761-f294-481b-b1b5-ff37609b6741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199399267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2199399267
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.553453611
Short name T46
Test name
Test status
Simulation time 113738273561 ps
CPU time 86.8 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:50:36 PM PDT 24
Peak memory 200780 kb
Host smart-1063190c-1990-4cad-89fa-09459a911489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553453611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.553453611
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2993984611
Short name T502
Test name
Test status
Simulation time 25158693350 ps
CPU time 298.79 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:54:08 PM PDT 24
Peak memory 200536 kb
Host smart-56149267-6150-47af-9df4-a3d11b37ac82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2993984611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2993984611
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.4143160896
Short name T16
Test name
Test status
Simulation time 6184528413 ps
CPU time 4.82 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:49:14 PM PDT 24
Peak memory 199704 kb
Host smart-d0596e0e-9ad3-447a-9e2d-c0a1df5e6993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4143160896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.4143160896
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1723435939
Short name T80
Test name
Test status
Simulation time 29236743325 ps
CPU time 51.99 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:50:01 PM PDT 24
Peak memory 200532 kb
Host smart-fefaa5fd-b512-4f9b-87f7-5bc1926863c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723435939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1723435939
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1962280592
Short name T1145
Test name
Test status
Simulation time 3674833041 ps
CPU time 2.41 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:49:12 PM PDT 24
Peak memory 196816 kb
Host smart-220ecbf9-1780-4b4c-b222-c551bfda8386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962280592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1962280592
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1608417196
Short name T423
Test name
Test status
Simulation time 5887374902 ps
CPU time 7.96 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:49:16 PM PDT 24
Peak memory 200452 kb
Host smart-1e87db43-7d79-41f9-b668-a6188c727160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608417196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1608417196
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2429522905
Short name T644
Test name
Test status
Simulation time 110778727817 ps
CPU time 40.99 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:49:49 PM PDT 24
Peak memory 200728 kb
Host smart-c0e57fcf-adc9-473d-99d4-818e1eadc842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429522905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2429522905
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2781952843
Short name T75
Test name
Test status
Simulation time 8916555197 ps
CPU time 8.88 seconds
Started May 28 01:49:00 PM PDT 24
Finished May 28 01:49:15 PM PDT 24
Peak memory 200432 kb
Host smart-c1a90540-dc1e-409a-8bc8-d7af401805b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781952843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2781952843
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1290531536
Short name T1172
Test name
Test status
Simulation time 222353525023 ps
CPU time 49.05 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:49:58 PM PDT 24
Peak memory 200484 kb
Host smart-df862888-f838-481f-9c4a-ce09fa8c8a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290531536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1290531536
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1052844668
Short name T785
Test name
Test status
Simulation time 35974903664 ps
CPU time 15.55 seconds
Started May 28 01:51:56 PM PDT 24
Finished May 28 01:52:15 PM PDT 24
Peak memory 199132 kb
Host smart-e7680f11-02fa-4a48-8612-f089d8eb6402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052844668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1052844668
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.4188796176
Short name T336
Test name
Test status
Simulation time 73744833646 ps
CPU time 66.21 seconds
Started May 28 01:51:55 PM PDT 24
Finished May 28 01:53:05 PM PDT 24
Peak memory 208828 kb
Host smart-7934279b-563b-4dc0-b200-47ea83d537a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188796176 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.4188796176
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.4190124730
Short name T1126
Test name
Test status
Simulation time 29328263557 ps
CPU time 12.17 seconds
Started May 28 01:51:55 PM PDT 24
Finished May 28 01:52:12 PM PDT 24
Peak memory 200248 kb
Host smart-4f64bd58-b123-40d4-979b-da9a8c01a53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190124730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.4190124730
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.12524103
Short name T587
Test name
Test status
Simulation time 278982962597 ps
CPU time 828.86 seconds
Started May 28 01:51:57 PM PDT 24
Finished May 28 02:05:49 PM PDT 24
Peak memory 214908 kb
Host smart-8cd8bce8-0071-4773-b689-5bdabac0342f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12524103 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.12524103
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.928595104
Short name T767
Test name
Test status
Simulation time 34020848224 ps
CPU time 62.06 seconds
Started May 28 01:51:53 PM PDT 24
Finished May 28 01:52:59 PM PDT 24
Peak memory 200252 kb
Host smart-136ce574-51a8-4952-b8cf-473a25617c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928595104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.928595104
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.954155073
Short name T920
Test name
Test status
Simulation time 157854752697 ps
CPU time 449.26 seconds
Started May 28 01:51:55 PM PDT 24
Finished May 28 01:59:28 PM PDT 24
Peak memory 225504 kb
Host smart-9314cbc9-20ba-4917-8fa2-55f8ad74bf9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954155073 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.954155073
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2656149182
Short name T760
Test name
Test status
Simulation time 148085135299 ps
CPU time 108.76 seconds
Started May 28 01:51:57 PM PDT 24
Finished May 28 01:53:49 PM PDT 24
Peak memory 200376 kb
Host smart-da686f9e-7b6f-445e-b4ad-fe5b0290b70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656149182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2656149182
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3678888862
Short name T755
Test name
Test status
Simulation time 54161173321 ps
CPU time 1369.94 seconds
Started May 28 01:51:55 PM PDT 24
Finished May 28 02:14:49 PM PDT 24
Peak memory 216952 kb
Host smart-1aac304a-fe2e-4c93-9d57-7f06acfa4e1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678888862 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3678888862
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.4129792437
Short name T674
Test name
Test status
Simulation time 90153002330 ps
CPU time 448.38 seconds
Started May 28 01:51:55 PM PDT 24
Finished May 28 01:59:28 PM PDT 24
Peak memory 200464 kb
Host smart-2410aa1c-8c50-419e-b414-c4e2d18e9582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129792437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.4129792437
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1214781255
Short name T677
Test name
Test status
Simulation time 84172418674 ps
CPU time 659.46 seconds
Started May 28 01:51:54 PM PDT 24
Finished May 28 02:02:57 PM PDT 24
Peak memory 217248 kb
Host smart-3f7136e2-6e4f-4c0e-a55b-0d81f0d2f17d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214781255 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1214781255
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2375229111
Short name T242
Test name
Test status
Simulation time 155807675407 ps
CPU time 56.74 seconds
Started May 28 01:51:56 PM PDT 24
Finished May 28 01:52:57 PM PDT 24
Peak memory 200520 kb
Host smart-a407b4a9-143d-407f-9ba0-5568bba39b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375229111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2375229111
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3627976715
Short name T651
Test name
Test status
Simulation time 19416762252 ps
CPU time 174.2 seconds
Started May 28 01:51:55 PM PDT 24
Finished May 28 01:54:53 PM PDT 24
Peak memory 217248 kb
Host smart-3f298247-c5d0-4d62-8295-0d543530581f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627976715 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3627976715
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3486470407
Short name T713
Test name
Test status
Simulation time 24914052936 ps
CPU time 37.54 seconds
Started May 28 01:51:53 PM PDT 24
Finished May 28 01:52:33 PM PDT 24
Peak memory 200484 kb
Host smart-a0c54e20-74bf-4495-983b-b0b9eec89f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486470407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3486470407
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1698845113
Short name T1141
Test name
Test status
Simulation time 12656359581 ps
CPU time 23.25 seconds
Started May 28 01:51:53 PM PDT 24
Finished May 28 01:52:19 PM PDT 24
Peak memory 200456 kb
Host smart-8cca2a57-4836-44ae-9951-bd521b530a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698845113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1698845113
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3233559781
Short name T233
Test name
Test status
Simulation time 36131113204 ps
CPU time 56.48 seconds
Started May 28 01:51:53 PM PDT 24
Finished May 28 01:52:53 PM PDT 24
Peak memory 200596 kb
Host smart-e3ec1d35-f1dd-4bed-aceb-a37c2b9042bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233559781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3233559781
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.281725954
Short name T764
Test name
Test status
Simulation time 138652264709 ps
CPU time 677.73 seconds
Started May 28 01:51:53 PM PDT 24
Finished May 28 02:03:14 PM PDT 24
Peak memory 217284 kb
Host smart-eff05452-352f-45b7-b547-fd6a72374ba8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281725954 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.281725954
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2833215889
Short name T937
Test name
Test status
Simulation time 11682173055 ps
CPU time 18.59 seconds
Started May 28 01:51:58 PM PDT 24
Finished May 28 01:52:19 PM PDT 24
Peak memory 200352 kb
Host smart-87178347-3165-4f43-906b-6109fb91b527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833215889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2833215889
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3295020784
Short name T479
Test name
Test status
Simulation time 34322357127 ps
CPU time 275.15 seconds
Started May 28 01:51:58 PM PDT 24
Finished May 28 01:56:36 PM PDT 24
Peak memory 216168 kb
Host smart-bd181634-20cd-4d6e-9652-485cf5e4d73d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295020784 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3295020784
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3892179850
Short name T737
Test name
Test status
Simulation time 94079233 ps
CPU time 0.56 seconds
Started May 28 01:49:00 PM PDT 24
Finished May 28 01:49:07 PM PDT 24
Peak memory 195920 kb
Host smart-3a7ca7ef-da75-466a-bd28-f38101c04bf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892179850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3892179850
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2226828120
Short name T273
Test name
Test status
Simulation time 98537304025 ps
CPU time 156.03 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:51:44 PM PDT 24
Peak memory 200568 kb
Host smart-d8d61fbe-2b1b-4ef4-83b5-0173a4e779a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226828120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2226828120
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2249662243
Short name T1127
Test name
Test status
Simulation time 52901367678 ps
CPU time 39.69 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:49:48 PM PDT 24
Peak memory 200144 kb
Host smart-d5c8db4d-4cda-48f0-9b77-eb268f8cd9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249662243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2249662243
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3199243019
Short name T808
Test name
Test status
Simulation time 96848342096 ps
CPU time 73.59 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:50:21 PM PDT 24
Peak memory 200496 kb
Host smart-063af989-b3f2-4d8b-8b95-afd8ddbcba40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199243019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3199243019
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3484881556
Short name T1056
Test name
Test status
Simulation time 19387522212 ps
CPU time 9.65 seconds
Started May 28 01:48:58 PM PDT 24
Finished May 28 01:49:11 PM PDT 24
Peak memory 200004 kb
Host smart-74f91728-c7fd-42ce-9650-3fc84c09a35d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484881556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3484881556
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.489240412
Short name T638
Test name
Test status
Simulation time 117822266882 ps
CPU time 455.26 seconds
Started May 28 01:49:05 PM PDT 24
Finished May 28 01:56:45 PM PDT 24
Peak memory 200460 kb
Host smart-b6008ddd-db87-4442-b9f4-7467e7065ef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=489240412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.489240412
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2677525990
Short name T634
Test name
Test status
Simulation time 10764155971 ps
CPU time 2.34 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:49:10 PM PDT 24
Peak memory 200524 kb
Host smart-298dcd0d-fc26-4074-baf2-465d33f6cf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677525990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2677525990
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.3483519414
Short name T474
Test name
Test status
Simulation time 42871936161 ps
CPU time 21.04 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:49:29 PM PDT 24
Peak memory 200800 kb
Host smart-c9ea2261-9b24-4c05-93c1-f56a1bf07489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483519414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3483519414
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1531707659
Short name T590
Test name
Test status
Simulation time 31307117628 ps
CPU time 934.88 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 02:04:44 PM PDT 24
Peak memory 200476 kb
Host smart-1eddbc26-6ab3-4101-aca9-702a0a0e8c56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531707659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1531707659
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1575947412
Short name T927
Test name
Test status
Simulation time 1295458405 ps
CPU time 1.08 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:49:10 PM PDT 24
Peak memory 196072 kb
Host smart-698abd4e-7eaa-468d-b8f5-7c6520e6d747
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1575947412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1575947412
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1238567041
Short name T490
Test name
Test status
Simulation time 25789010645 ps
CPU time 22.46 seconds
Started May 28 01:48:59 PM PDT 24
Finished May 28 01:49:25 PM PDT 24
Peak memory 200512 kb
Host smart-f829d71d-f351-43be-954a-7fa2cc4a80ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238567041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1238567041
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1011534242
Short name T434
Test name
Test status
Simulation time 681762961 ps
CPU time 1.76 seconds
Started May 28 01:49:05 PM PDT 24
Finished May 28 01:49:12 PM PDT 24
Peak memory 195408 kb
Host smart-601e30ed-a719-4bf5-b448-7c54f060bf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011534242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1011534242
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1540578039
Short name T1152
Test name
Test status
Simulation time 6326864907 ps
CPU time 6.94 seconds
Started May 28 01:48:59 PM PDT 24
Finished May 28 01:49:12 PM PDT 24
Peak memory 199676 kb
Host smart-84ef34e1-f498-493a-83a8-8dab1d6e4813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540578039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1540578039
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2799601657
Short name T471
Test name
Test status
Simulation time 5091726556 ps
CPU time 4.75 seconds
Started May 28 01:49:05 PM PDT 24
Finished May 28 01:49:15 PM PDT 24
Peak memory 199976 kb
Host smart-90663bc5-2c90-4362-8b95-140fa106aef2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799601657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2799601657
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3153739208
Short name T420
Test name
Test status
Simulation time 16036362566 ps
CPU time 188.62 seconds
Started May 28 01:49:01 PM PDT 24
Finished May 28 01:52:16 PM PDT 24
Peak memory 217008 kb
Host smart-bf75a178-bffe-439b-97df-fc62053df57b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153739208 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3153739208
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3899235002
Short name T405
Test name
Test status
Simulation time 599615788 ps
CPU time 3.06 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:49:12 PM PDT 24
Peak memory 199376 kb
Host smart-fcd978b0-0fc5-4dc9-9db2-51247b41b2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899235002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3899235002
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1033813298
Short name T332
Test name
Test status
Simulation time 174499221328 ps
CPU time 90.34 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:50:40 PM PDT 24
Peak memory 199392 kb
Host smart-1f17982d-3f04-4347-a50f-240a849153d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033813298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1033813298
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.720272335
Short name T257
Test name
Test status
Simulation time 436962025158 ps
CPU time 40.58 seconds
Started May 28 01:51:55 PM PDT 24
Finished May 28 01:52:39 PM PDT 24
Peak memory 200472 kb
Host smart-c2471812-0f25-469b-8b53-680083f07e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720272335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.720272335
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.4264131907
Short name T596
Test name
Test status
Simulation time 53651303048 ps
CPU time 139.49 seconds
Started May 28 01:51:54 PM PDT 24
Finished May 28 01:54:17 PM PDT 24
Peak memory 212292 kb
Host smart-d0fbb276-df6e-4793-8c49-d217bb7dea47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264131907 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.4264131907
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1274640941
Short name T219
Test name
Test status
Simulation time 23240530442 ps
CPU time 44.49 seconds
Started May 28 01:51:56 PM PDT 24
Finished May 28 01:52:44 PM PDT 24
Peak memory 200536 kb
Host smart-86a3c4dc-8df0-4850-8ae7-4a9f056fecf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274640941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1274640941
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.935151961
Short name T1083
Test name
Test status
Simulation time 59287436759 ps
CPU time 40.66 seconds
Started May 28 01:52:02 PM PDT 24
Finished May 28 01:52:43 PM PDT 24
Peak memory 200500 kb
Host smart-7da3da5c-2d14-4e85-9508-c3d218b106db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935151961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.935151961
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.2547499515
Short name T1171
Test name
Test status
Simulation time 116025779338 ps
CPU time 525.41 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 02:01:01 PM PDT 24
Peak memory 217316 kb
Host smart-6022e89e-6b35-46f1-962c-5f87114863ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547499515 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2547499515
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1283664452
Short name T577
Test name
Test status
Simulation time 181361759847 ps
CPU time 70.37 seconds
Started May 28 01:52:15 PM PDT 24
Finished May 28 01:53:27 PM PDT 24
Peak memory 200052 kb
Host smart-18e3f5b1-4746-46a3-99ac-a6d5d54c2059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283664452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1283664452
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3323399209
Short name T663
Test name
Test status
Simulation time 81119365217 ps
CPU time 432.14 seconds
Started May 28 01:52:12 PM PDT 24
Finished May 28 01:59:25 PM PDT 24
Peak memory 216780 kb
Host smart-595c8e41-8172-4b1e-a6f2-dfe53d232806
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323399209 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3323399209
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.947268683
Short name T750
Test name
Test status
Simulation time 47853708611 ps
CPU time 6 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 01:52:21 PM PDT 24
Peak memory 200304 kb
Host smart-d9723d82-2a60-4e06-bc38-2fa859d8ab88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947268683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.947268683
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1847897727
Short name T62
Test name
Test status
Simulation time 94848765927 ps
CPU time 369.52 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 01:58:26 PM PDT 24
Peak memory 226696 kb
Host smart-c3249429-7e0f-45fb-be28-ad553b6a3a9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847897727 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1847897727
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.27686492
Short name T107
Test name
Test status
Simulation time 124585067345 ps
CPU time 187.89 seconds
Started May 28 01:52:13 PM PDT 24
Finished May 28 01:55:22 PM PDT 24
Peak memory 200584 kb
Host smart-c8ebefa7-c237-42aa-a2f3-316e0f81b9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27686492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.27686492
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2810816459
Short name T837
Test name
Test status
Simulation time 92264774372 ps
CPU time 244.37 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 01:56:20 PM PDT 24
Peak memory 216408 kb
Host smart-a2c37dab-cc36-4c2c-b16e-65c8be766352
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810816459 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2810816459
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.680046395
Short name T1128
Test name
Test status
Simulation time 29223599465 ps
CPU time 49.17 seconds
Started May 28 01:52:12 PM PDT 24
Finished May 28 01:53:02 PM PDT 24
Peak memory 200532 kb
Host smart-c11e5a92-e28c-4041-9cf1-5ea0ebe48ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680046395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.680046395
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.943191669
Short name T529
Test name
Test status
Simulation time 49761949856 ps
CPU time 698.53 seconds
Started May 28 01:52:15 PM PDT 24
Finished May 28 02:03:55 PM PDT 24
Peak memory 226800 kb
Host smart-1255158a-d32c-4d13-99f9-6a66280da9cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943191669 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.943191669
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1886868840
Short name T294
Test name
Test status
Simulation time 70928405573 ps
CPU time 69.32 seconds
Started May 28 01:52:12 PM PDT 24
Finished May 28 01:53:22 PM PDT 24
Peak memory 200452 kb
Host smart-8b16df5c-7db9-407e-a5be-ef1f0061801d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886868840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1886868840
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.4043939675
Short name T39
Test name
Test status
Simulation time 51427800520 ps
CPU time 936.45 seconds
Started May 28 01:52:15 PM PDT 24
Finished May 28 02:07:53 PM PDT 24
Peak memory 225492 kb
Host smart-94b67c5b-d240-4b0b-be9d-0777dda11174
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043939675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.4043939675
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3407059191
Short name T40
Test name
Test status
Simulation time 12690252068 ps
CPU time 200.7 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 01:55:37 PM PDT 24
Peak memory 216784 kb
Host smart-14f268ec-c3a0-4c8b-9cf3-1d7cee2354d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407059191 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3407059191
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1886522855
Short name T620
Test name
Test status
Simulation time 31629633096 ps
CPU time 13.73 seconds
Started May 28 01:52:12 PM PDT 24
Finished May 28 01:52:27 PM PDT 24
Peak memory 198716 kb
Host smart-c2700582-3b20-4743-84c8-c7a90fb48637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886522855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1886522855
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1199755519
Short name T1073
Test name
Test status
Simulation time 243620081669 ps
CPU time 764.38 seconds
Started May 28 01:52:12 PM PDT 24
Finished May 28 02:04:57 PM PDT 24
Peak memory 217012 kb
Host smart-42b6f7b4-4159-42a1-8a01-1ba776cd26f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199755519 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1199755519
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1321303849
Short name T1048
Test name
Test status
Simulation time 13193460 ps
CPU time 0.55 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:16 PM PDT 24
Peak memory 195344 kb
Host smart-10cb7012-a099-4b9b-a3cd-67189038c0a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321303849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1321303849
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1225885699
Short name T898
Test name
Test status
Simulation time 68447343826 ps
CPU time 59.45 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:50:09 PM PDT 24
Peak memory 200520 kb
Host smart-b22fc74a-beea-4a64-9e53-3d496acaecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225885699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1225885699
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1333908640
Short name T732
Test name
Test status
Simulation time 174348866141 ps
CPU time 129.08 seconds
Started May 28 01:49:05 PM PDT 24
Finished May 28 01:51:19 PM PDT 24
Peak memory 200504 kb
Host smart-99bef060-f249-43ba-8cbf-600f813086d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333908640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1333908640
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.571107049
Short name T816
Test name
Test status
Simulation time 133051478320 ps
CPU time 263.98 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:53:32 PM PDT 24
Peak memory 200584 kb
Host smart-87d027cc-ff8d-4dd3-8814-fafcac9ff0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571107049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.571107049
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.4146213511
Short name T733
Test name
Test status
Simulation time 40092020093 ps
CPU time 55.43 seconds
Started May 28 01:49:03 PM PDT 24
Finished May 28 01:50:04 PM PDT 24
Peak memory 199484 kb
Host smart-a35e6cfd-78f8-46d3-a967-837cda158246
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146213511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.4146213511
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3392751791
Short name T949
Test name
Test status
Simulation time 79684534641 ps
CPU time 174.22 seconds
Started May 28 01:49:08 PM PDT 24
Finished May 28 01:52:06 PM PDT 24
Peak memory 200532 kb
Host smart-6872f20f-ae59-463a-8408-b32de417a50a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3392751791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3392751791
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.581928107
Short name T769
Test name
Test status
Simulation time 5929944301 ps
CPU time 2.2 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:49:20 PM PDT 24
Peak memory 199704 kb
Host smart-8b5d8cd5-03d5-4372-a579-64b84543484f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581928107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.581928107
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.573563788
Short name T278
Test name
Test status
Simulation time 57310448653 ps
CPU time 52.01 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:50:09 PM PDT 24
Peak memory 199856 kb
Host smart-a971a6d5-bb24-4774-9b60-487ae5f56848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573563788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.573563788
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3791898289
Short name T818
Test name
Test status
Simulation time 30500382043 ps
CPU time 1721.89 seconds
Started May 28 01:49:08 PM PDT 24
Finished May 28 02:17:54 PM PDT 24
Peak memory 200540 kb
Host smart-43f74a36-0fbc-4d67-9764-8ec1a1f51022
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3791898289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3791898289
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3057032401
Short name T519
Test name
Test status
Simulation time 4709937942 ps
CPU time 38.48 seconds
Started May 28 01:49:02 PM PDT 24
Finished May 28 01:49:46 PM PDT 24
Peak memory 198700 kb
Host smart-3f39eaac-2e48-45cd-93df-74b565ec7707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3057032401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3057032401
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1582132275
Short name T1012
Test name
Test status
Simulation time 120377595507 ps
CPU time 58.21 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:50:14 PM PDT 24
Peak memory 200520 kb
Host smart-48788a6b-b74a-4c14-84f5-6f04a0f5bf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582132275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1582132275
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3316624865
Short name T369
Test name
Test status
Simulation time 4889841762 ps
CPU time 2.09 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:17 PM PDT 24
Peak memory 196784 kb
Host smart-fb4d86d7-8ee6-4166-bcb8-aa00239ed547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316624865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3316624865
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3181762352
Short name T833
Test name
Test status
Simulation time 249822218 ps
CPU time 1.34 seconds
Started May 28 01:48:59 PM PDT 24
Finished May 28 01:49:04 PM PDT 24
Peak memory 198928 kb
Host smart-0110c265-8c65-4d7a-8db0-0c213c7390fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181762352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3181762352
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.266438359
Short name T778
Test name
Test status
Simulation time 130809998260 ps
CPU time 144.12 seconds
Started May 28 01:49:08 PM PDT 24
Finished May 28 01:51:36 PM PDT 24
Peak memory 200456 kb
Host smart-42738272-2554-4d18-9d07-0e486855e289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266438359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.266438359
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2380029719
Short name T660
Test name
Test status
Simulation time 36871261311 ps
CPU time 715.66 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 02:01:11 PM PDT 24
Peak memory 216388 kb
Host smart-6f9b7a59-3763-46e1-a006-46fa12a786ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380029719 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2380029719
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1252989336
Short name T296
Test name
Test status
Simulation time 7916946802 ps
CPU time 13.88 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:49:30 PM PDT 24
Peak memory 199860 kb
Host smart-82ac1bae-ce05-4538-af4d-7b560d2ec93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252989336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1252989336
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.4193563625
Short name T979
Test name
Test status
Simulation time 15383413571 ps
CPU time 26.19 seconds
Started May 28 01:48:57 PM PDT 24
Finished May 28 01:49:25 PM PDT 24
Peak memory 200452 kb
Host smart-1ddaf455-9d71-4629-89bb-1a0f67218959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193563625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.4193563625
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2349314208
Short name T346
Test name
Test status
Simulation time 21852530723 ps
CPU time 38.4 seconds
Started May 28 01:52:12 PM PDT 24
Finished May 28 01:52:51 PM PDT 24
Peak memory 200504 kb
Host smart-fec2989c-7bc4-4ae1-a3ac-bc019b84f5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349314208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2349314208
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1606455940
Short name T932
Test name
Test status
Simulation time 39897787836 ps
CPU time 201.22 seconds
Started May 28 01:52:18 PM PDT 24
Finished May 28 01:55:40 PM PDT 24
Peak memory 217212 kb
Host smart-ad5ce41c-880a-4e0b-b1ff-9e5d934cdb35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606455940 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1606455940
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3106436093
Short name T404
Test name
Test status
Simulation time 97062565014 ps
CPU time 143.4 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 01:54:39 PM PDT 24
Peak memory 200464 kb
Host smart-1e2f6a3c-cb16-4209-bc2f-12d72ad7e4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106436093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3106436093
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1726474078
Short name T1131
Test name
Test status
Simulation time 155835411516 ps
CPU time 434.57 seconds
Started May 28 01:52:16 PM PDT 24
Finished May 28 01:59:33 PM PDT 24
Peak memory 225216 kb
Host smart-57f71426-45e2-427a-964d-fb48f36837c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726474078 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1726474078
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.957952784
Short name T848
Test name
Test status
Simulation time 136209247412 ps
CPU time 492.87 seconds
Started May 28 01:52:16 PM PDT 24
Finished May 28 02:00:31 PM PDT 24
Peak memory 200360 kb
Host smart-84f6f7a8-dec2-484a-8464-5acbe698a0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957952784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.957952784
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1413833992
Short name T247
Test name
Test status
Simulation time 17229083150 ps
CPU time 14.42 seconds
Started May 28 01:52:10 PM PDT 24
Finished May 28 01:52:26 PM PDT 24
Peak memory 200304 kb
Host smart-daaa31cf-99b8-46c5-bb84-ad695f01bfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413833992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1413833992
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3774515434
Short name T967
Test name
Test status
Simulation time 198774577435 ps
CPU time 1415.11 seconds
Started May 28 01:52:12 PM PDT 24
Finished May 28 02:15:48 PM PDT 24
Peak memory 233656 kb
Host smart-99d1c3ac-2030-4010-be03-4dd68229b22d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774515434 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3774515434
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.969806672
Short name T718
Test name
Test status
Simulation time 19593289841 ps
CPU time 35.65 seconds
Started May 28 01:52:13 PM PDT 24
Finished May 28 01:52:50 PM PDT 24
Peak memory 200500 kb
Host smart-e3b3f80d-eab2-4cb0-8dc4-891c8ae3ba6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969806672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.969806672
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3309588762
Short name T938
Test name
Test status
Simulation time 49841192195 ps
CPU time 780.05 seconds
Started May 28 01:52:12 PM PDT 24
Finished May 28 02:05:14 PM PDT 24
Peak memory 216996 kb
Host smart-0a343af4-1ad8-4589-9d6e-c29572dd5b07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309588762 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3309588762
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.803263793
Short name T897
Test name
Test status
Simulation time 21739540970 ps
CPU time 7.74 seconds
Started May 28 01:52:15 PM PDT 24
Finished May 28 01:52:25 PM PDT 24
Peak memory 200532 kb
Host smart-dda91d63-d8a8-4b9f-be15-487933657c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803263793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.803263793
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.4046979829
Short name T869
Test name
Test status
Simulation time 289361360978 ps
CPU time 737.11 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 02:04:34 PM PDT 24
Peak memory 217004 kb
Host smart-08eaf41d-f508-4c8d-8887-f506d91b6241
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046979829 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.4046979829
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1442447171
Short name T116
Test name
Test status
Simulation time 50756879753 ps
CPU time 47.75 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 01:53:04 PM PDT 24
Peak memory 200396 kb
Host smart-cc46d4f3-0a49-4ef3-91ae-134d961962c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442447171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1442447171
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.4256061043
Short name T41
Test name
Test status
Simulation time 100510787271 ps
CPU time 882.14 seconds
Started May 28 01:52:13 PM PDT 24
Finished May 28 02:06:57 PM PDT 24
Peak memory 225388 kb
Host smart-52d2b796-f464-4569-b9db-02a77655843e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256061043 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.4256061043
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3564886008
Short name T867
Test name
Test status
Simulation time 24273742261 ps
CPU time 9.47 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 01:52:25 PM PDT 24
Peak memory 200540 kb
Host smart-b4905558-fc6e-4530-a862-8dd4de1c981d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564886008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3564886008
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1421163549
Short name T59
Test name
Test status
Simulation time 34140341644 ps
CPU time 266.46 seconds
Started May 28 01:52:13 PM PDT 24
Finished May 28 01:56:41 PM PDT 24
Peak memory 216692 kb
Host smart-c7fc3648-ba94-416d-9899-a2445bc4af70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421163549 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1421163549
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3512741998
Short name T417
Test name
Test status
Simulation time 57194754761 ps
CPU time 24.41 seconds
Started May 28 01:52:12 PM PDT 24
Finished May 28 01:52:38 PM PDT 24
Peak memory 200448 kb
Host smart-04db8774-36f9-45ab-9b68-fb0ddeeacb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512741998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3512741998
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3404038840
Short name T777
Test name
Test status
Simulation time 77208020776 ps
CPU time 373.35 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 01:58:29 PM PDT 24
Peak memory 217264 kb
Host smart-e4cd878c-7230-455f-86ec-a0fb8d13920e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404038840 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3404038840
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1227126903
Short name T238
Test name
Test status
Simulation time 29434680734 ps
CPU time 26.11 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 01:52:42 PM PDT 24
Peak memory 200292 kb
Host smart-d406e2ac-0a49-481b-85ae-08a7bf3bdb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227126903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1227126903
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1008439250
Short name T1156
Test name
Test status
Simulation time 196795109044 ps
CPU time 657.72 seconds
Started May 28 01:52:13 PM PDT 24
Finished May 28 02:03:12 PM PDT 24
Peak memory 217200 kb
Host smart-0c416249-1101-408e-b412-2b2c15e92048
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008439250 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1008439250
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3025462309
Short name T29
Test name
Test status
Simulation time 37683718 ps
CPU time 0.6 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:15 PM PDT 24
Peak memory 195904 kb
Host smart-df07e571-4966-4679-952b-1729abc137e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025462309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3025462309
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3343479994
Short name T163
Test name
Test status
Simulation time 40466094217 ps
CPU time 66.73 seconds
Started May 28 01:49:12 PM PDT 24
Finished May 28 01:50:24 PM PDT 24
Peak memory 200508 kb
Host smart-f341aef9-c6ce-4851-89e2-47b53639e48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343479994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3343479994
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.956462706
Short name T115
Test name
Test status
Simulation time 21698177797 ps
CPU time 35.2 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:51 PM PDT 24
Peak memory 200524 kb
Host smart-d40c65dd-ee3d-4d34-ab83-a6208d4fd984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956462706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.956462706
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2566099206
Short name T619
Test name
Test status
Simulation time 17386642707 ps
CPU time 33 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:49 PM PDT 24
Peak memory 200556 kb
Host smart-c1bdefb7-ccec-4bb0-8efa-18494446a056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566099206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2566099206
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2574651410
Short name T328
Test name
Test status
Simulation time 14887115891 ps
CPU time 7.12 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:49:25 PM PDT 24
Peak memory 200108 kb
Host smart-915a1896-34ba-460a-bf73-2bb5fd37f03e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574651410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2574651410
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2615208660
Short name T329
Test name
Test status
Simulation time 140115034329 ps
CPU time 314.97 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:54:30 PM PDT 24
Peak memory 200520 kb
Host smart-7c000409-8f31-482a-a93d-ca6c67cc8c67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2615208660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2615208660
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1592913512
Short name T25
Test name
Test status
Simulation time 115638191 ps
CPU time 0.7 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:15 PM PDT 24
Peak memory 196436 kb
Host smart-705cd681-1a2f-4e43-9e76-3cbb681c9047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592913512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1592913512
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1651835979
Short name T1120
Test name
Test status
Simulation time 57318476506 ps
CPU time 113.86 seconds
Started May 28 01:49:14 PM PDT 24
Finished May 28 01:51:13 PM PDT 24
Peak memory 200124 kb
Host smart-bfd20e9f-6f42-495d-b38b-552edd623c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651835979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1651835979
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.527745893
Short name T870
Test name
Test status
Simulation time 7563417477 ps
CPU time 443.3 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:56:40 PM PDT 24
Peak memory 200464 kb
Host smart-f600ca39-e4d2-4672-bf0d-28c1fc6e99c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=527745893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.527745893
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.96805045
Short name T727
Test name
Test status
Simulation time 4514156056 ps
CPU time 40.48 seconds
Started May 28 01:49:09 PM PDT 24
Finished May 28 01:49:53 PM PDT 24
Peak memory 198700 kb
Host smart-5689e91d-71e0-4e2c-9e91-957ee7880813
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96805045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.96805045
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2849258476
Short name T583
Test name
Test status
Simulation time 34684135615 ps
CPU time 55.25 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:50:11 PM PDT 24
Peak memory 200516 kb
Host smart-6d54f00b-90e8-4b86-810b-08f5f624f6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849258476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2849258476
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2965874029
Short name T730
Test name
Test status
Simulation time 770525421 ps
CPU time 1.34 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:18 PM PDT 24
Peak memory 195896 kb
Host smart-afb280b0-3420-4975-b0db-1a79ff77ca06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965874029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2965874029
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2875006116
Short name T701
Test name
Test status
Simulation time 5536595413 ps
CPU time 17.51 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 01:49:34 PM PDT 24
Peak memory 200436 kb
Host smart-e05d3ddb-015c-4545-8fc2-8a4e9f073b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875006116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2875006116
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.198816544
Short name T655
Test name
Test status
Simulation time 93483182272 ps
CPU time 979.83 seconds
Started May 28 01:49:11 PM PDT 24
Finished May 28 02:05:35 PM PDT 24
Peak memory 200724 kb
Host smart-da7087dd-e247-426c-b4da-37126ba4da86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198816544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.198816544
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2427024243
Short name T6
Test name
Test status
Simulation time 17006426312 ps
CPU time 164.51 seconds
Started May 28 01:49:13 PM PDT 24
Finished May 28 01:52:03 PM PDT 24
Peak memory 210416 kb
Host smart-d4bde876-7f7e-47a6-b186-a3c18dce2fc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427024243 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2427024243
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.22055040
Short name T771
Test name
Test status
Simulation time 6694626445 ps
CPU time 13.83 seconds
Started May 28 01:49:10 PM PDT 24
Finished May 28 01:49:28 PM PDT 24
Peak memory 200680 kb
Host smart-6da83cee-3ca9-407e-9f99-a655c8d77ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22055040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.22055040
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2955691974
Short name T1136
Test name
Test status
Simulation time 61261814713 ps
CPU time 107.51 seconds
Started May 28 01:49:09 PM PDT 24
Finished May 28 01:51:00 PM PDT 24
Peak memory 200540 kb
Host smart-597ab081-5077-40ec-962e-3c205f9f5473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955691974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2955691974
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1575813856
Short name T690
Test name
Test status
Simulation time 22729304708 ps
CPU time 9.82 seconds
Started May 28 01:52:15 PM PDT 24
Finished May 28 01:52:27 PM PDT 24
Peak memory 200452 kb
Host smart-da177e86-ccdc-453f-8d74-24624dc0238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575813856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1575813856
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2351028868
Short name T65
Test name
Test status
Simulation time 103350056260 ps
CPU time 1802.79 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 02:22:19 PM PDT 24
Peak memory 227912 kb
Host smart-a92aa1e2-444f-42a5-9031-26c21238c75c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351028868 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2351028868
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.77733757
Short name T1005
Test name
Test status
Simulation time 92630986554 ps
CPU time 42.02 seconds
Started May 28 01:52:15 PM PDT 24
Finished May 28 01:52:59 PM PDT 24
Peak memory 200524 kb
Host smart-bf67b437-bdfe-43f3-a9c4-961311025d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77733757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.77733757
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1311892065
Short name T684
Test name
Test status
Simulation time 76576359818 ps
CPU time 677.27 seconds
Started May 28 01:52:16 PM PDT 24
Finished May 28 02:03:35 PM PDT 24
Peak memory 217196 kb
Host smart-1e140d61-6ac7-4c68-9e58-a1e178761522
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311892065 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1311892065
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4019863466
Short name T1037
Test name
Test status
Simulation time 69207596846 ps
CPU time 37.49 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 01:52:53 PM PDT 24
Peak memory 200540 kb
Host smart-c256ec2e-a0d7-4c45-b392-c38da4ebf03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019863466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4019863466
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2392052043
Short name T28
Test name
Test status
Simulation time 32766768086 ps
CPU time 198.15 seconds
Started May 28 01:52:16 PM PDT 24
Finished May 28 01:55:36 PM PDT 24
Peak memory 216960 kb
Host smart-c938f941-730f-404b-be26-ee57233f9ad2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392052043 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2392052043
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3458025791
Short name T48
Test name
Test status
Simulation time 130942659404 ps
CPU time 117.29 seconds
Started May 28 01:52:17 PM PDT 24
Finished May 28 01:54:15 PM PDT 24
Peak memory 200484 kb
Host smart-62f7ec2b-5d65-4d2d-a10e-ba04ab9642ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458025791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3458025791
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3998226373
Short name T196
Test name
Test status
Simulation time 42792319682 ps
CPU time 647.47 seconds
Started May 28 01:52:15 PM PDT 24
Finished May 28 02:03:04 PM PDT 24
Peak memory 216988 kb
Host smart-b6522d27-57fc-43f6-8d60-4ef9b26b56c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998226373 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3998226373
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2787440555
Short name T892
Test name
Test status
Simulation time 115363942260 ps
CPU time 51.41 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 01:53:07 PM PDT 24
Peak memory 200464 kb
Host smart-7e1c5aaf-6f85-41e3-a788-c93782e4b77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787440555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2787440555
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1063359635
Short name T180
Test name
Test status
Simulation time 72044594249 ps
CPU time 222.89 seconds
Started May 28 01:52:16 PM PDT 24
Finished May 28 01:56:01 PM PDT 24
Peak memory 209520 kb
Host smart-a1c3abfb-8058-417a-b1e1-41d95eec71b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063359635 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1063359635
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3127013306
Short name T523
Test name
Test status
Simulation time 75297156098 ps
CPU time 63.15 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 01:53:20 PM PDT 24
Peak memory 200524 kb
Host smart-c79c9e05-350f-4adc-9f6c-d1003068ec3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127013306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3127013306
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1267015534
Short name T418
Test name
Test status
Simulation time 24385848571 ps
CPU time 76.8 seconds
Started May 28 01:52:17 PM PDT 24
Finished May 28 01:53:35 PM PDT 24
Peak memory 216032 kb
Host smart-ee752150-c0ff-434b-9aae-a110e9086c46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267015534 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1267015534
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3326959210
Short name T886
Test name
Test status
Simulation time 45282084566 ps
CPU time 40.29 seconds
Started May 28 01:52:17 PM PDT 24
Finished May 28 01:52:58 PM PDT 24
Peak memory 200560 kb
Host smart-715ad5d0-3ba9-48b7-b27f-21ccd8e89d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326959210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3326959210
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.545540550
Short name T1080
Test name
Test status
Simulation time 132192168209 ps
CPU time 443.63 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 01:59:40 PM PDT 24
Peak memory 217264 kb
Host smart-16558082-a3ab-44d1-9918-cc4a1b40120b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545540550 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.545540550
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.4283865642
Short name T270
Test name
Test status
Simulation time 152005313389 ps
CPU time 151.03 seconds
Started May 28 01:52:14 PM PDT 24
Finished May 28 01:54:47 PM PDT 24
Peak memory 200464 kb
Host smart-4bf383b4-a0b2-4910-8506-829880e754c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283865642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.4283865642
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3457131595
Short name T1058
Test name
Test status
Simulation time 33742635514 ps
CPU time 988.46 seconds
Started May 28 01:52:16 PM PDT 24
Finished May 28 02:08:47 PM PDT 24
Peak memory 216220 kb
Host smart-afe3737f-27a2-4054-914d-faf5dee81269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457131595 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3457131595
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3741256404
Short name T759
Test name
Test status
Simulation time 20959278448 ps
CPU time 18.7 seconds
Started May 28 01:52:17 PM PDT 24
Finished May 28 01:52:37 PM PDT 24
Peak memory 200444 kb
Host smart-3bdafb60-0fa0-452b-beee-30968469c78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741256404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3741256404
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3907180566
Short name T517
Test name
Test status
Simulation time 47220505945 ps
CPU time 28.7 seconds
Started May 28 01:52:16 PM PDT 24
Finished May 28 01:52:47 PM PDT 24
Peak memory 200468 kb
Host smart-25bccc2b-50ae-46d1-bc00-b77140c68047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907180566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3907180566
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1424138110
Short name T763
Test name
Test status
Simulation time 135231955598 ps
CPU time 176.52 seconds
Started May 28 01:52:37 PM PDT 24
Finished May 28 01:55:37 PM PDT 24
Peak memory 216936 kb
Host smart-e565be8d-c7cc-4018-87bf-0458568ac445
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424138110 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1424138110
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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