Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	110039	1			T1	2		T2	60		T3	16
all_values[1]	110039	1			T1	2		T2	60		T3	16
all_values[2]	110039	1			T1	2		T2	60		T3	16
all_values[3]	110039	1			T1	2		T2	60		T3	16
all_values[4]	110039	1			T1	2		T2	60		T3	16
all_values[5]	110039	1			T1	2		T2	60		T3	16
all_values[6]	110039	1			T1	2		T2	60		T3	16
all_values[7]	110039	1			T1	2		T2	60		T3	16

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

430222

1

T1

16

T2

213

T3

76

auto[1]

450090

1

T2

267

T3

52

T4

93

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

822503

1

T1

13

T2

440

T3

122

auto[1]

57809

1

T1

3

T2

40

T3

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	32789	1			T3	13		T4	4		T5	8
all_values[0]	auto[0]	auto[1]	22016	1			T1	2		T3	3		T4	7
all_values[0]	auto[1]	auto[0]	30946	1			T2	31		T5	2		T8	9
all_values[0]	auto[1]	auto[1]	24288	1			T2	29		T4	5		T5	5
all_values[1]	auto[0]	auto[0]	51209	1			T1	2		T2	20		T3	2
all_values[1]	auto[0]	auto[1]	1660	1			T10	6		T21	1		T11	2
all_values[1]	auto[1]	auto[0]	55585	1			T2	40		T3	14		T4	11
all_values[1]	auto[1]	auto[1]	1585	1			T117	27		T11	6		T13	6
all_values[2]	auto[0]	auto[0]	50082	1			T1	1		T2	11		T3	11
all_values[2]	auto[0]	auto[1]	2724	1			T1	1		T2	2		T3	3
all_values[2]	auto[1]	auto[0]	54681	1			T2	38		T3	2		T4	11
all_values[2]	auto[1]	auto[1]	2552	1			T2	9		T4	2		T5	1
all_values[3]	auto[0]	auto[0]	55757	1			T1	2		T2	46		T3	16
all_values[3]	auto[0]	auto[1]	321	1			T11	2		T13	2		T12	2
all_values[3]	auto[1]	auto[0]	53637	1			T2	14		T4	14		T5	7
all_values[3]	auto[1]	auto[1]	324	1			T10	1		T11	1		T13	4
all_values[4]	auto[0]	auto[0]	53234	1			T1	2		T2	20		T3	14
all_values[4]	auto[0]	auto[1]	440	1			T11	7		T13	5		T12	2
all_values[4]	auto[1]	auto[0]	55921	1			T2	40		T3	2		T4	2
all_values[4]	auto[1]	auto[1]	444	1			T13	4		T12	1		T16	7
all_values[5]	auto[0]	auto[0]	52308	1			T1	2		T2	44		T3	14
all_values[5]	auto[0]	auto[1]	178	1			T12	4		T30	5		T129	2
all_values[5]	auto[1]	auto[0]	57371	1			T2	16		T3	2		T4	16
all_values[5]	auto[1]	auto[1]	182	1			T13	2		T12	3		T30	1
all_values[6]	auto[0]	auto[0]	51612	1			T1	2		T2	25		T5	14
all_values[6]	auto[0]	auto[1]	191	1			T13	4		T12	4		T34	2
all_values[6]	auto[1]	auto[0]	58058	1			T2	35		T3	16		T4	16
all_values[6]	auto[1]	auto[1]	178	1			T11	2		T13	3		T12	1
all_values[7]	auto[0]	auto[0]	55341	1			T1	2		T2	45		T5	10
all_values[7]	auto[0]	auto[1]	360	1			T10	4		T11	2		T12	2
all_values[7]	auto[1]	auto[0]	53972	1			T2	15		T3	16		T4	16
all_values[7]	auto[1]	auto[1]	366	1			T11	2		T13	2		T12	1