Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2481	1			T2	3		T3	1		T4	1
auto[BaudRate115200]	2086	1			T2	1		T3	1		T4	1
auto[BaudRate230400]	2095	1			T3	1		T5	3		T6	2
auto[BaudRate128Kbps]	2296	1			T1	1		T2	1		T3	1
auto[BaudRate256Kbps]	2404	1			T3	1		T4	3		T5	3
auto[BaudRate1Mbps]	1883	1			T1	1		T4	1		T10	1
auto[BaudRate1p5Mbps]	1353	1			T2	1		T8	1		T10	5

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1576	1			T14	5		T46	6		T266	6
freqs[25]	1723	1			T4	9		T5	8		T90	5
freqs[48]	472	1			T39	7		T132	7		T120	4
freqs[50]	598	1			T13	28		T19	18		T30	32
freqs[100]	1206	1			T331	1		T17	4		T118	6

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	265	1			T266	2		T334	3		T139	2
auto[BaudRate9600]	freqs[25]	301	1			T4	1		T5	2		T90	1
auto[BaudRate9600]	freqs[48]	96	1			T132	1		T235	1		T335	9
auto[BaudRate9600]	freqs[50]	105	1			T13	4		T30	5		T336	15
auto[BaudRate9600]	freqs[100]	188	1			T331	1		T329	1		T284	1
auto[BaudRate115200]	freqs[24]	204	1			T14	1		T266	1		T16	1
auto[BaudRate115200]	freqs[25]	256	1			T4	1		T22	2		T130	2
auto[BaudRate115200]	freqs[48]	42	1			T39	1		T296	1		T235	1
auto[BaudRate115200]	freqs[50]	97	1			T13	3		T19	3		T30	5
auto[BaudRate115200]	freqs[100]	147	1			T17	1		T118	2		T284	1
auto[BaudRate230400]	freqs[24]	205	1			T266	2		T273	2		T139	2
auto[BaudRate230400]	freqs[25]	232	1			T5	3		T130	1		T47	1
auto[BaudRate230400]	freqs[48]	58	1			T39	2		T132	3		T120	1
auto[BaudRate230400]	freqs[50]	90	1			T13	6		T30	7		T336	3
auto[BaudRate230400]	freqs[100]	150	1			T17	1		T329	1		T288	1
auto[BaudRate128Kbps]	freqs[24]	251	1			T266	1		T16	2		T139	1
auto[BaudRate128Kbps]	freqs[25]	271	1			T4	3		T90	1		T22	1
auto[BaudRate128Kbps]	freqs[48]	57	1			T39	1		T120	3		T337	1
auto[BaudRate128Kbps]	freqs[50]	70	1			T13	2		T19	3		T30	5
auto[BaudRate128Kbps]	freqs[100]	180	1			T17	2		T329	1		T288	2
auto[BaudRate256Kbps]	freqs[24]	235	1			T14	2		T46	2		T273	1
auto[BaudRate256Kbps]	freqs[25]	283	1			T4	3		T5	3		T90	2
auto[BaudRate256Kbps]	freqs[48]	86	1			T39	2		T132	1		T263	2
auto[BaudRate256Kbps]	freqs[50]	77	1			T13	5		T19	9		T30	3
auto[BaudRate256Kbps]	freqs[100]	183	1			T118	1		T291	4		T124	3
auto[BaudRate1Mbps]	freqs[24]	258	1			T14	1		T46	2		T139	1
auto[BaudRate1Mbps]	freqs[25]	256	1			T4	1		T90	1		T22	3
auto[BaudRate1Mbps]	freqs[48]	70	1			T132	1		T263	5		T258	1
auto[BaudRate1Mbps]	freqs[50]	74	1			T13	2		T30	3		T336	12
auto[BaudRate1Mbps]	freqs[100]	166	1			T118	2		T329	1		T288	3
auto[BaudRate1p5Mbps]	freqs[25]	124	1			T22	2		T130	1		T338	3
auto[BaudRate1p5Mbps]	freqs[48]	63	1			T39	1		T132	1		T263	3
auto[BaudRate1p5Mbps]	freqs[50]	85	1			T13	6		T19	3		T30	4
auto[BaudRate1p5Mbps]	freqs[100]	192	1			T118	1		T329	1		T288	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded