Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg
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Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
93.91 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 67 0 67 100.00
Crosses 130 12 118 90.77


Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_lvl 65 0 65 100.00 100 1 1 0
cp_rst 2 0 2 100.00 100 1 1 2


Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
rx_fifo_level_cg_cc 130 12 118 90.77 100 1 1 0


Summary for Variable cp_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 65 0 65 100.00


User Defined Bins for cp_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 31042627 1 T2 57 T3 23 T4 65
all_levels[1] 204671 1 T2 1 T3 5 T5 9
all_levels[2] 2521 1 T3 2 T5 1 T10 1
all_levels[3] 1050 1 T3 1 T8 1 T10 2
all_levels[4] 688 1 T3 2 T10 1 T117 5
all_levels[5] 519 1 T8 2 T10 1 T90 1
all_levels[6] 425 1 T3 1 T5 1 T10 1
all_levels[7] 344 1 T2 2 T10 1 T20 1
all_levels[8] 290 1 T10 3 T20 1 T22 1
all_levels[9] 263 1 T10 1 T22 1 T117 3
all_levels[10] 257 1 T3 1 T13 2 T42 2
all_levels[11] 199 1 T3 1 T13 1 T118 1
all_levels[12] 183 1 T2 1 T22 1 T13 3
all_levels[13] 138 1 T3 1 T130 1 T131 2
all_levels[14] 136 1 T6 1 T10 1 T13 1
all_levels[15] 145 1 T2 1 T10 1 T22 3
all_levels[16] 99 1 T132 1 T133 2 T134 1
all_levels[17] 88 1 T135 1 T136 1 T131 1
all_levels[18] 96 1 T22 1 T13 1 T12 1
all_levels[19] 86 1 T6 1 T130 1 T30 1
all_levels[20] 71 1 T4 2 T8 1 T12 1
all_levels[21] 67 1 T5 1 T43 1 T12 1
all_levels[22] 64 1 T5 1 T14 2 T22 1
all_levels[23] 53 1 T22 1 T117 1 T137 2
all_levels[24] 56 1 T13 1 T131 1 T138 2
all_levels[25] 46 1 T22 1 T11 1 T13 1
all_levels[26] 41 1 T22 1 T137 1 T133 1
all_levels[27] 48 1 T12 1 T139 1 T138 1
all_levels[28] 53 1 T10 1 T138 1 T140 1
all_levels[29] 45 1 T10 1 T13 1 T12 1
all_levels[30] 22 1 T124 1 T141 1 T35 1
all_levels[31] 41 1 T142 2 T143 1 T144 1
all_levels[32] 21 1 T137 1 T145 1 T146 2
all_levels[33] 36 1 T43 1 T147 1 T148 1
all_levels[34] 24 1 T10 1 T118 1 T149 1
all_levels[35] 21 1 T22 1 T150 1 T151 2
all_levels[36] 24 1 T37 1 T13 1 T152 1
all_levels[37] 19 1 T37 1 T107 1 T153 1
all_levels[38] 22 1 T147 1 T30 2 T154 1
all_levels[39] 13 1 T22 1 T155 1 T156 1
all_levels[40] 27 1 T157 1 T158 1 T144 2
all_levels[41] 21 1 T20 1 T22 1 T149 1
all_levels[42] 19 1 T12 1 T159 1 T160 1
all_levels[43] 16 1 T149 1 T148 1 T161 1
all_levels[44] 9 1 T159 1 T162 1 T161 1
all_levels[45] 13 1 T135 1 T159 2 T55 1
all_levels[46] 5 1 T163 1 T164 1 T165 1
all_levels[47] 12 1 T149 1 T166 1 T167 1
all_levels[48] 14 1 T168 1 T144 1 T169 1
all_levels[49] 17 1 T117 1 T170 1 T144 1
all_levels[50] 8 1 T130 1 T171 1 T172 2
all_levels[51] 11 1 T173 1 T174 1 T175 1
all_levels[52] 12 1 T12 1 T157 1 T170 1
all_levels[53] 9 1 T159 2 T176 2 T177 3
all_levels[54] 9 1 T149 1 T50 1 T178 1
all_levels[55] 7 1 T139 1 T179 1 T180 1
all_levels[56] 11 1 T162 1 T181 1 T182 1
all_levels[57] 11 1 T50 1 T180 3 T174 1
all_levels[58] 7 1 T183 1 T184 1 T185 1
all_levels[59] 14 1 T186 1 T179 1 T180 1
all_levels[60] 10 1 T170 2 T154 1 T187 1
all_levels[61] 3 1 T135 1 T116 1 T188 1
all_levels[62] 4 1 T150 1 T174 1 T164 1
all_levels[63] 8 1 T12 1 T185 1 T189 2
all_levels[64] 116 1 T10 2 T12 3 T138 3



Summary for Variable cp_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rst

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31251267 1 T2 56 T3 37 T4 58
auto[1] 4738 1 T2 6 T4 9 T6 3



Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 130 12 118 90.77 12


Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins
cp_lvlcp_rstCOUNTAT LEASTNUMBERSTATUS
[all_levels[30]] [auto[1]] 0 1 1
[all_levels[37]] [auto[1]] 0 1 1
[all_levels[39]] [auto[1]] 0 1 1
[all_levels[44] , all_levels[45] , all_levels[46]] [auto[1]] -- -- 3
[all_levels[52]] [auto[1]] 0 1 1
[all_levels[54] , all_levels[55]] [auto[1]] -- -- 2
[all_levels[58]] [auto[1]] 0 1 1
[all_levels[61] , all_levels[62]] [auto[1]] -- -- 2


Covered bins
cp_lvlcp_rstCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] auto[0] 31038334 1 T2 52 T3 23 T4 57
all_levels[0] auto[1] 4293 1 T2 5 T4 8 T6 3
all_levels[1] auto[0] 204599 1 T2 1 T3 5 T5 9
all_levels[1] auto[1] 72 1 T190 1 T30 1 T134 1
all_levels[2] auto[0] 2497 1 T3 2 T5 1 T10 1
all_levels[2] auto[1] 24 1 T191 1 T192 2 T193 3
all_levels[3] auto[0] 1030 1 T3 1 T8 1 T10 2
all_levels[3] auto[1] 20 1 T124 1 T141 1 T194 1
all_levels[4] auto[0] 669 1 T3 2 T10 1 T117 5
all_levels[4] auto[1] 19 1 T42 1 T105 1 T195 1
all_levels[5] auto[0] 506 1 T8 1 T10 1 T90 1
all_levels[5] auto[1] 13 1 T8 1 T142 1 T196 1
all_levels[6] auto[0] 412 1 T3 1 T5 1 T10 1
all_levels[6] auto[1] 13 1 T183 3 T197 1 T198 1
all_levels[7] auto[0] 331 1 T2 1 T10 1 T20 1
all_levels[7] auto[1] 13 1 T2 1 T160 1 T199 1
all_levels[8] auto[0] 280 1 T10 3 T20 1 T22 1
all_levels[8] auto[1] 10 1 T200 1 T201 1 T202 2
all_levels[9] auto[0] 239 1 T10 1 T22 1 T117 3
all_levels[9] auto[1] 24 1 T42 1 T138 2 T203 1
all_levels[10] auto[0] 244 1 T3 1 T13 2 T42 2
all_levels[10] auto[1] 13 1 T204 1 T205 1 T180 1
all_levels[11] auto[0] 190 1 T3 1 T13 1 T118 1
all_levels[11] auto[1] 9 1 T134 1 T205 1 T206 1
all_levels[12] auto[0] 171 1 T2 1 T22 1 T13 3
all_levels[12] auto[1] 12 1 T135 1 T145 2 T207 3
all_levels[13] auto[0] 124 1 T3 1 T130 1 T131 2
all_levels[13] auto[1] 14 1 T208 1 T159 1 T50 2
all_levels[14] auto[0] 127 1 T6 1 T10 1 T13 1
all_levels[14] auto[1] 9 1 T42 1 T184 1 T209 1
all_levels[15] auto[0] 131 1 T2 1 T10 1 T22 2
all_levels[15] auto[1] 14 1 T22 1 T37 1 T121 2
all_levels[16] auto[0] 87 1 T132 1 T133 2 T134 1
all_levels[16] auto[1] 12 1 T159 1 T210 1 T211 2
all_levels[17] auto[0] 85 1 T135 1 T136 1 T131 1
all_levels[17] auto[1] 3 1 T54 1 T212 1 T213 1
all_levels[18] auto[0] 87 1 T22 1 T13 1 T12 1
all_levels[18] auto[1] 9 1 T170 2 T214 1 T215 1
all_levels[19] auto[0] 73 1 T6 1 T130 1 T30 1
all_levels[19] auto[1] 13 1 T143 1 T216 2 T217 3
all_levels[20] auto[0] 61 1 T4 1 T8 1 T12 1
all_levels[20] auto[1] 10 1 T4 1 T191 2 T207 1
all_levels[21] auto[0] 58 1 T5 1 T43 1 T12 1
all_levels[21] auto[1] 9 1 T218 1 T219 1 T220 3
all_levels[22] auto[0] 56 1 T5 1 T14 1 T22 1
all_levels[22] auto[1] 8 1 T14 1 T191 1 T221 1
all_levels[23] auto[0] 48 1 T22 1 T117 1 T137 1
all_levels[23] auto[1] 5 1 T137 1 T222 1 T54 1
all_levels[24] auto[0] 51 1 T13 1 T131 1 T138 2
all_levels[24] auto[1] 5 1 T223 1 T224 1 T63 1
all_levels[25] auto[0] 43 1 T22 1 T11 1 T13 1
all_levels[25] auto[1] 3 1 T124 1 T225 1 T33 1
all_levels[26] auto[0] 40 1 T22 1 T137 1 T133 1
all_levels[26] auto[1] 1 1 T181 1 - - - -
all_levels[27] auto[0] 47 1 T12 1 T139 1 T138 1
all_levels[27] auto[1] 1 1 T226 1 - - - -
all_levels[28] auto[0] 47 1 T10 1 T138 1 T140 1
all_levels[28] auto[1] 6 1 T160 2 T227 1 T228 2
all_levels[29] auto[0] 38 1 T10 1 T13 1 T12 1
all_levels[29] auto[1] 7 1 T229 1 T214 1 T230 1
all_levels[30] auto[0] 22 1 T124 1 T141 1 T35 1
all_levels[31] auto[0] 37 1 T142 2 T143 1 T144 1
all_levels[31] auto[1] 4 1 T231 1 T232 2 T233 1
all_levels[32] auto[0] 19 1 T137 1 T145 1 T146 1
all_levels[32] auto[1] 2 1 T146 1 T234 1 - -
all_levels[33] auto[0] 29 1 T43 1 T147 1 T148 1
all_levels[33] auto[1] 7 1 T199 1 T235 2 T236 1
all_levels[34] auto[0] 23 1 T10 1 T118 1 T149 1
all_levels[34] auto[1] 1 1 T237 1 - - - -
all_levels[35] auto[0] 19 1 T22 1 T150 1 T151 2
all_levels[35] auto[1] 2 1 T238 1 T239 1 - -
all_levels[36] auto[0] 23 1 T37 1 T13 1 T152 1
all_levels[36] auto[1] 1 1 T240 1 - - - -
all_levels[37] auto[0] 19 1 T37 1 T107 1 T153 1
all_levels[38] auto[0] 21 1 T147 1 T30 1 T154 1
all_levels[38] auto[1] 1 1 T30 1 - - - -
all_levels[39] auto[0] 13 1 T22 1 T155 1 T156 1
all_levels[40] auto[0] 24 1 T157 1 T158 1 T144 2
all_levels[40] auto[1] 3 1 T214 2 T241 1 - -
all_levels[41] auto[0] 14 1 T20 1 T22 1 T149 1
all_levels[41] auto[1] 7 1 T242 3 T243 4 - -
all_levels[42] auto[0] 17 1 T12 1 T159 1 T160 1
all_levels[42] auto[1] 2 1 T209 1 T244 1 - -
all_levels[43] auto[0] 15 1 T149 1 T148 1 T161 1
all_levels[43] auto[1] 1 1 T245 1 - - - -
all_levels[44] auto[0] 9 1 T159 1 T162 1 T161 1
all_levels[45] auto[0] 13 1 T135 1 T159 2 T55 1
all_levels[46] auto[0] 5 1 T163 1 T164 1 T165 1
all_levels[47] auto[0] 11 1 T149 1 T166 1 T167 1
all_levels[47] auto[1] 1 1 T246 1 - - - -
all_levels[48] auto[0] 13 1 T168 1 T144 1 T169 1
all_levels[48] auto[1] 1 1 T247 1 - - - -
all_levels[49] auto[0] 16 1 T117 1 T170 1 T144 1
all_levels[49] auto[1] 1 1 T248 1 - - - -
all_levels[50] auto[0] 7 1 T130 1 T171 1 T172 1
all_levels[50] auto[1] 1 1 T172 1 - - - -
all_levels[51] auto[0] 9 1 T173 1 T174 1 T175 1
all_levels[51] auto[1] 2 1 T249 1 T250 1 - -
all_levels[52] auto[0] 12 1 T12 1 T157 1 T170 1
all_levels[53] auto[0] 4 1 T159 1 T176 1 T177 1
all_levels[53] auto[1] 5 1 T159 1 T176 1 T177 2
all_levels[54] auto[0] 9 1 T149 1 T50 1 T178 1
all_levels[55] auto[0] 7 1 T139 1 T179 1 T180 1
all_levels[56] auto[0] 7 1 T162 1 T181 1 T182 1
all_levels[56] auto[1] 4 1 T251 1 T252 3 - -
all_levels[57] auto[0] 8 1 T50 1 T180 1 T174 1
all_levels[57] auto[1] 3 1 T180 2 T253 1 - -
all_levels[58] auto[0] 7 1 T183 1 T184 1 T185 1
all_levels[59] auto[0] 9 1 T186 1 T179 1 T180 1
all_levels[59] auto[1] 5 1 T254 1 T253 4 - -
all_levels[60] auto[0] 7 1 T170 1 T154 1 T187 1
all_levels[60] auto[1] 3 1 T170 1 T255 2 - -
all_levels[61] auto[0] 3 1 T135 1 T116 1 T188 1
all_levels[62] auto[0] 4 1 T150 1 T174 1 T164 1
all_levels[63] auto[0] 7 1 T12 1 T185 1 T189 1
all_levels[63] auto[1] 1 1 T189 1 - - - -
all_levels[64] auto[0] 100 1 T10 2 T12 3 T138 1
all_levels[64] auto[1] 16 1 T138 2 T196 1 T50 2

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