Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	110039	1			T1	2		T2	60		T3	16
all_pins[1]	110039	1			T1	2		T2	60		T3	16
all_pins[2]	110039	1			T1	2		T2	60		T3	16
all_pins[3]	110039	1			T1	2		T2	60		T3	16
all_pins[4]	110039	1			T1	2		T2	60		T3	16
all_pins[5]	110039	1			T1	2		T2	60		T3	16
all_pins[6]	110039	1			T1	2		T2	60		T3	16
all_pins[7]	110039	1			T1	2		T2	60		T3	16

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	849512	1			T1	16		T2	442		T3	128
values[0x1]	30800	1			T2	38		T4	7		T5	6
transitions[0x0=>0x1]	29740	1			T2	38		T4	7		T5	6
transitions[0x1=>0x0]	29304	1			T2	37		T4	6		T5	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	85664	1			T1	2		T2	31		T3	16
all_pins[0]	values[0x1]	24375	1			T2	29		T4	5		T5	5
all_pins[0]	transitions[0x0=>0x1]	23866	1			T2	29		T4	5		T5	5
all_pins[0]	transitions[0x1=>0x0]	1080	1			T117	27		T13	4		T46	3
all_pins[1]	values[0x0]	108450	1			T1	2		T2	60		T3	16
all_pins[1]	values[0x1]	1589	1			T117	27		T11	6		T13	6
all_pins[1]	transitions[0x0=>0x1]	1490	1			T117	27		T11	6		T13	6
all_pins[1]	transitions[0x1=>0x0]	2522	1			T2	9		T4	2		T5	1
all_pins[2]	values[0x0]	107418	1			T1	2		T2	51		T3	16
all_pins[2]	values[0x1]	2621	1			T2	9		T4	2		T5	1
all_pins[2]	transitions[0x0=>0x1]	2549	1			T2	9		T4	2		T5	1
all_pins[2]	transitions[0x1=>0x0]	252	1			T10	1		T11	1		T13	2
all_pins[3]	values[0x0]	109715	1			T1	2		T2	60		T3	16
all_pins[3]	values[0x1]	324	1			T10	1		T11	1		T13	4
all_pins[3]	transitions[0x0=>0x1]	279	1			T10	1		T11	1		T13	3
all_pins[3]	transitions[0x1=>0x0]	399	1			T13	3		T12	1		T16	7
all_pins[4]	values[0x0]	109595	1			T1	2		T2	60		T3	16
all_pins[4]	values[0x1]	444	1			T13	4		T12	1		T16	7
all_pins[4]	transitions[0x0=>0x1]	363	1			T13	3		T16	5		T17	8
all_pins[4]	transitions[0x1=>0x0]	163	1			T11	1		T13	1		T12	2
all_pins[5]	values[0x0]	109795	1			T1	2		T2	60		T3	16
all_pins[5]	values[0x1]	244	1			T11	1		T13	2		T12	3
all_pins[5]	transitions[0x0=>0x1]	201	1			T11	1		T13	2		T12	2
all_pins[5]	transitions[0x1=>0x0]	794	1			T10	1		T14	5		T22	1
all_pins[6]	values[0x0]	109202	1			T1	2		T2	60		T3	16
all_pins[6]	values[0x1]	837	1			T10	1		T14	5		T22	1
all_pins[6]	transitions[0x0=>0x1]	792	1			T10	1		T14	5		T22	1
all_pins[6]	transitions[0x1=>0x0]	321	1			T11	2		T13	2		T12	1
all_pins[7]	values[0x0]	109673	1			T1	2		T2	60		T3	16
all_pins[7]	values[0x1]	366	1			T11	2		T13	2		T12	1
all_pins[7]	transitions[0x0=>0x1]	200	1			T11	1		T120	1		T30	4
all_pins[7]	transitions[0x1=>0x0]	23773	1			T2	28		T4	4		T5	4