Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8358864	1			T2	9		T3	5		T4	11
all_levels[1]	1563279	1			T2	5		T3	1		T4	40
all_levels[2]	332083	1			T3	2		T8	2		T10	2
all_levels[3]	229537	1			T2	4		T10	1		T21	268
all_levels[4]	444070	1			T2	3		T10	1		T21	275
all_levels[5]	294632	1			T21	270		T90	1		T22	2
all_levels[6]	352374	1			T2	1		T4	2		T10	2
all_levels[7]	224255	1			T2	2		T5	2		T8	1
all_levels[8]	268755	1			T2	6		T10	2		T21	272
all_levels[9]	284969	1			T21	281		T190	1		T11	18
all_levels[10]	207692	1			T21	246		T117	2		T11	23
all_levels[11]	384281	1			T21	280		T117	2		T11	25
all_levels[12]	219527	1			T21	264		T11	30		T38	37
all_levels[13]	267039	1			T2	1		T21	247		T11	18
all_levels[14]	205802	1			T2	1		T4	2		T5	2
all_levels[15]	288051	1			T8	1		T21	268		T190	2
all_levels[16]	497189	1			T2	1		T4	3		T21	272
all_levels[17]	191618	1			T5	5		T21	282		T190	3
all_levels[18]	194250	1			T5	5		T21	266		T117	3
all_levels[19]	389480	1			T2	2		T5	9		T8	2
all_levels[20]	190492	1			T4	1		T5	6		T21	245
all_levels[21]	250315	1			T5	15		T8	8		T10	2
all_levels[22]	426549	1			T5	5		T21	266		T190	2
all_levels[23]	265681	1			T2	7		T21	264		T11	20
all_levels[24]	190607	1			T4	3		T20	3		T21	277
all_levels[25]	311617	1			T3	2		T21	277		T190	2
all_levels[26]	214605	1			T2	4		T21	276		T117	6
all_levels[27]	397438	1			T2	4		T20	4		T21	297
all_levels[28]	523906	1			T2	1		T21	254		T22	7
all_levels[29]	175996	1			T2	1		T5	6		T21	257
all_levels[30]	166498	1			T2	2		T5	7		T21	273
all_levels[31]	842399	1			T2	2		T5	7		T20	2
all_levels[32]	12101651	1			T2	7		T3	28		T4	3

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31251267

1

T2

56

T3

37

T4

58

auto[1]

4234

1

T2

7

T3

1

T4

7

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8356703	1			T2	8		T3	5		T4	7
all_levels[0]	auto[1]	2161	1			T2	1		T4	4		T6	3
all_levels[1]	auto[0]	1562840	1			T2	5		T3	1		T4	40
all_levels[1]	auto[1]	439	1			T6	2		T8	1		T264	10
all_levels[2]	auto[0]	332047	1			T3	2		T8	2		T10	2
all_levels[2]	auto[1]	36	1			T107	1		T181	1		T340	10
all_levels[3]	auto[0]	229403	1			T2	4		T10	1		T21	268
all_levels[3]	auto[1]	134	1			T11	5		T148	1		T275	1
all_levels[4]	auto[0]	444036	1			T2	2		T10	1		T21	275
all_levels[4]	auto[1]	34	1			T2	1		T296	1		T124	1
all_levels[5]	auto[0]	294601	1			T21	270		T90	1		T22	2
all_levels[5]	auto[1]	31	1			T37	3		T266	2		T136	4
all_levels[6]	auto[0]	352344	1			T2	1		T4	1		T10	2
all_levels[6]	auto[1]	30	1			T4	1		T261	1		T216	2
all_levels[7]	auto[0]	224120	1			T2	1		T5	2		T8	1
all_levels[7]	auto[1]	135	1			T2	1		T17	19		T143	2
all_levels[8]	auto[0]	268725	1			T2	6		T10	2		T21	272
all_levels[8]	auto[1]	30	1			T135	1		T207	1		T112	1
all_levels[9]	auto[0]	284936	1			T21	281		T190	1		T11	18
all_levels[9]	auto[1]	33	1			T285	1		T131	1		T124	1
all_levels[10]	auto[0]	207676	1			T21	246		T117	2		T11	23
all_levels[10]	auto[1]	16	1			T148	1		T105	2		T341	2
all_levels[11]	auto[0]	384253	1			T21	280		T117	2		T11	25
all_levels[11]	auto[1]	28	1			T44	1		T135	2		T142	1
all_levels[12]	auto[0]	219503	1			T21	264		T11	30		T38	37
all_levels[12]	auto[1]	24	1			T260	1		T288	1		T342	1
all_levels[13]	auto[0]	267017	1			T2	1		T21	247		T11	18
all_levels[13]	auto[1]	22	1			T257	1		T210	1		T54	1
all_levels[14]	auto[0]	205766	1			T2	1		T4	2		T5	2
all_levels[14]	auto[1]	36	1			T20	1		T135	3		T208	1
all_levels[15]	auto[0]	287887	1			T8	1		T21	268		T190	2
all_levels[15]	auto[1]	164	1			T120	24		T129	1		T31	4
all_levels[16]	auto[0]	497160	1			T2	1		T4	3		T21	272
all_levels[16]	auto[1]	29	1			T11	2		T285	2		T142	1
all_levels[17]	auto[0]	191591	1			T5	5		T21	282		T190	3
all_levels[17]	auto[1]	27	1			T30	1		T138	2		T327	1
all_levels[18]	auto[0]	194234	1			T5	5		T21	266		T117	3
all_levels[18]	auto[1]	16	1			T343	1		T344	1		T345	1
all_levels[19]	auto[0]	389461	1			T2	2		T5	9		T8	2
all_levels[19]	auto[1]	19	1			T42	1		T141	1		T346	4
all_levels[20]	auto[0]	190470	1			T4	1		T5	6		T21	245
all_levels[20]	auto[1]	22	1			T48	6		T347	1		T223	3
all_levels[21]	auto[0]	250294	1			T5	15		T8	7		T10	2
all_levels[21]	auto[1]	21	1			T8	1		T135	1		T152	2
all_levels[22]	auto[0]	426523	1			T5	5		T21	266		T190	2
all_levels[22]	auto[1]	26	1			T136	2		T291	1		T159	2
all_levels[23]	auto[0]	265658	1			T2	4		T21	264		T11	20
all_levels[23]	auto[1]	23	1			T2	3		T42	1		T50	3
all_levels[24]	auto[0]	190590	1			T4	2		T20	3		T21	277
all_levels[24]	auto[1]	17	1			T4	1		T208	2		T270	1
all_levels[25]	auto[0]	311604	1			T3	2		T21	277		T190	2
all_levels[25]	auto[1]	13	1			T196	2		T105	1		T348	1
all_levels[26]	auto[0]	214580	1			T2	4		T21	276		T117	6
all_levels[26]	auto[1]	25	1			T137	1		T272	2		T183	1
all_levels[27]	auto[0]	397414	1			T2	4		T20	2		T21	297
all_levels[27]	auto[1]	24	1			T20	2		T326	1		T192	1
all_levels[28]	auto[0]	523879	1			T2	1		T21	254		T22	6
all_levels[28]	auto[1]	27	1			T22	1		T222	1		T283	1
all_levels[29]	auto[0]	175980	1			T2	1		T5	6		T21	257
all_levels[29]	auto[1]	16	1			T349	2		T221	1		T169	1
all_levels[30]	auto[0]	166468	1			T2	2		T5	7		T21	273
all_levels[30]	auto[1]	30	1			T47	2		T121	3		T216	2
all_levels[31]	auto[0]	842370	1			T2	2		T5	7		T20	1
all_levels[31]	auto[1]	29	1			T20	1		T22	1		T142	2
all_levels[32]	auto[0]	12101134	1			T2	6		T3	27		T4	2
all_levels[32]	auto[1]	517	1			T2	1		T3	1		T4	1