Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	815	1			T11	4		T13	11		T12	7
all_values[1]	815	1			T11	4		T13	11		T12	7
all_values[2]	815	1			T11	4		T13	11		T12	7
all_values[3]	815	1			T11	4		T13	11		T12	7
all_values[4]	815	1			T11	4		T13	11		T12	7
all_values[5]	815	1			T11	4		T13	11		T12	7
all_values[6]	815	1			T11	4		T13	11		T12	7
all_values[7]	815	1			T11	4		T13	11		T12	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3489

1

T11

19

T13

44

T12

33

auto[1]

3031

1

T11

13

T13

44

T12

23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2417

1

T11

15

T13

30

T12

20

auto[1]

4103

1

T11

17

T13

58

T12

36

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3862

1

T11

20

T13

53

T12

30

auto[1]

2658

1

T11

12

T13

35

T12

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	252	1			T11	1		T13	3		T12	1
all_values[0]	auto[0]	auto[1]	auto[1]	233	1			T11	1		T13	3		T12	1
all_values[0]	auto[1]	auto[0]	auto[1]	189	1			T11	1		T13	3		T12	1
all_values[0]	auto[1]	auto[1]	auto[1]	141	1			T11	1		T13	2		T12	4
all_values[1]	auto[0]	auto[0]	auto[0]	242	1			T11	1		T13	4		T12	1
all_values[1]	auto[0]	auto[1]	auto[0]	232	1			T11	1		T13	3		T12	3
all_values[1]	auto[1]	auto[0]	auto[1]	171	1			T11	2		T13	2		T12	1
all_values[1]	auto[1]	auto[1]	auto[1]	170	1			T13	2		T12	2		T30	3
all_values[2]	auto[0]	auto[0]	auto[0]	175	1			T11	1		T13	2		T12	4
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T13	1		T30	3		T34	2
all_values[2]	auto[0]	auto[1]	auto[0]	148	1			T11	1		T30	1		T32	3
all_values[2]	auto[0]	auto[1]	auto[1]	86	1			T13	3		T129	3		T32	1
all_values[2]	auto[1]	auto[0]	auto[1]	186	1			T11	2		T13	3		T12	3
all_values[2]	auto[1]	auto[1]	auto[1]	150	1			T13	2		T30	3		T129	1
all_values[3]	auto[0]	auto[0]	auto[0]	165	1			T11	1		T13	2		T12	3
all_values[3]	auto[0]	auto[0]	auto[1]	89	1			T11	1		T13	1		T30	1
all_values[3]	auto[0]	auto[1]	auto[0]	135	1			T30	3		T32	4		T35	1
all_values[3]	auto[0]	auto[1]	auto[1]	89	1			T13	3		T12	1		T129	2
all_values[3]	auto[1]	auto[0]	auto[1]	198	1			T13	2		T12	2		T30	2
all_values[3]	auto[1]	auto[1]	auto[1]	139	1			T11	2		T13	3		T12	1
all_values[4]	auto[0]	auto[0]	auto[0]	176	1			T11	2		T12	1		T30	6
all_values[4]	auto[0]	auto[0]	auto[1]	81	1			T13	4		T12	2		T30	1
all_values[4]	auto[0]	auto[1]	auto[0]	137	1			T13	2		T12	2		T30	1
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T13	1		T35	1		T122	1
all_values[4]	auto[1]	auto[0]	auto[1]	199	1			T11	2		T12	2		T30	2
all_values[4]	auto[1]	auto[1]	auto[1]	144	1			T13	4		T30	1		T32	2
all_values[5]	auto[0]	auto[0]	auto[0]	194	1			T11	1		T13	6		T30	3
all_values[5]	auto[0]	auto[0]	auto[1]	78	1			T12	2		T30	3		T129	1
all_values[5]	auto[0]	auto[1]	auto[0]	142	1			T11	2		T30	1		T32	1
all_values[5]	auto[0]	auto[1]	auto[1]	76	1			T32	2		T35	1		T111	3
all_values[5]	auto[1]	auto[0]	auto[1]	176	1			T11	1		T13	1		T12	2
all_values[5]	auto[1]	auto[1]	auto[1]	149	1			T13	4		T12	3		T32	1
all_values[6]	auto[0]	auto[0]	auto[0]	171	1			T11	1		T13	1		T12	1
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T13	1		T12	2		T34	1
all_values[6]	auto[0]	auto[1]	auto[0]	169	1			T13	2		T12	1		T30	3
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T11	2		T13	1		T32	1
all_values[6]	auto[1]	auto[0]	auto[1]	165	1			T13	4		T12	2		T30	1
all_values[6]	auto[1]	auto[1]	auto[1]	157	1			T11	1		T13	2		T12	1
all_values[7]	auto[0]	auto[0]	auto[0]	183	1			T11	2		T13	4		T12	1
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T12	1		T32	1		T35	1
all_values[7]	auto[0]	auto[1]	auto[0]	148	1			T11	2		T13	4		T12	3
all_values[7]	auto[0]	auto[1]	auto[1]	84	1			T13	2		T30	1		T32	1
all_values[7]	auto[1]	auto[0]	auto[1]	175	1			T12	1		T30	4		T32	3
all_values[7]	auto[1]	auto[1]	auto[1]	149	1			T13	1		T12	1		T30	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal