Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.27	97.95	100.00		98.80	100.00	99.55

Total test records in report: 1318

T1253	/workspace/coverage/cover_reg_top/2.uart_tl_errors.2522966825	May 30 12:48:00 PM PDT 24	May 30 12:48:02 PM PDT 24	36104320 ps
T128	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3587746450	May 30 12:47:59 PM PDT 24	May 30 12:48:00 PM PDT 24	89661273 ps
T1254	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.873108534	May 30 12:48:14 PM PDT 24	May 30 12:48:16 PM PDT 24	75945692 ps
T1255	/workspace/coverage/cover_reg_top/2.uart_intr_test.1016271692	May 30 12:48:06 PM PDT 24	May 30 12:48:08 PM PDT 24	44472895 ps
T1256	/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1915446683	May 30 12:48:26 PM PDT 24	May 30 12:48:28 PM PDT 24	19157707 ps
T1257	/workspace/coverage/cover_reg_top/36.uart_intr_test.3597387626	May 30 12:48:26 PM PDT 24	May 30 12:48:28 PM PDT 24	18731247 ps
T1258	/workspace/coverage/cover_reg_top/14.uart_tl_errors.531941984	May 30 12:48:13 PM PDT 24	May 30 12:48:17 PM PDT 24	182663452 ps
T1259	/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3179130956	May 30 12:48:03 PM PDT 24	May 30 12:48:04 PM PDT 24	95649351 ps
T1260	/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3785178898	May 30 12:48:13 PM PDT 24	May 30 12:48:15 PM PDT 24	27498020 ps
T1261	/workspace/coverage/cover_reg_top/0.uart_tl_errors.3048960529	May 30 12:47:51 PM PDT 24	May 30 12:47:53 PM PDT 24	47145715 ps
T1262	/workspace/coverage/cover_reg_top/8.uart_tl_errors.1534226219	May 30 12:48:00 PM PDT 24	May 30 12:48:04 PM PDT 24	110213540 ps
T1263	/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1848940172	May 30 12:48:03 PM PDT 24	May 30 12:48:07 PM PDT 24	176959034 ps
T1264	/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2105331473	May 30 12:48:04 PM PDT 24	May 30 12:48:06 PM PDT 24	73551340 ps
T1265	/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1848855631	May 30 12:47:58 PM PDT 24	May 30 12:47:59 PM PDT 24	42403053 ps
T1266	/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.35461127	May 30 12:48:01 PM PDT 24	May 30 12:48:03 PM PDT 24	21974053 ps
T1267	/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1874337263	May 30 12:48:00 PM PDT 24	May 30 12:48:03 PM PDT 24	1125992838 ps
T1268	/workspace/coverage/cover_reg_top/13.uart_tl_errors.487026750	May 30 12:48:15 PM PDT 24	May 30 12:48:18 PM PDT 24	72048191 ps
T1269	/workspace/coverage/cover_reg_top/41.uart_intr_test.1892932505	May 30 12:48:32 PM PDT 24	May 30 12:48:34 PM PDT 24	33080239 ps
T1270	/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2713043826	May 30 12:48:15 PM PDT 24	May 30 12:48:18 PM PDT 24	105549848 ps
T1271	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2711314712	May 30 12:48:10 PM PDT 24	May 30 12:48:12 PM PDT 24	555380762 ps
T1272	/workspace/coverage/cover_reg_top/1.uart_intr_test.2199379395	May 30 12:48:02 PM PDT 24	May 30 12:48:04 PM PDT 24	116437329 ps
T1273	/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.273710019	May 30 12:48:32 PM PDT 24	May 30 12:48:35 PM PDT 24	434564099 ps
T1274	/workspace/coverage/cover_reg_top/16.uart_intr_test.3251547618	May 30 12:48:14 PM PDT 24	May 30 12:48:16 PM PDT 24	57833873 ps
T1275	/workspace/coverage/cover_reg_top/6.uart_intr_test.1192060980	May 30 12:48:11 PM PDT 24	May 30 12:48:13 PM PDT 24	21264386 ps
T1276	/workspace/coverage/cover_reg_top/34.uart_intr_test.31454889	May 30 12:48:28 PM PDT 24	May 30 12:48:30 PM PDT 24	49213420 ps
T1277	/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1576955666	May 30 12:48:15 PM PDT 24	May 30 12:48:18 PM PDT 24	26833284 ps
T1278	/workspace/coverage/cover_reg_top/43.uart_intr_test.2773458963	May 30 12:48:31 PM PDT 24	May 30 12:48:33 PM PDT 24	12545547 ps
T1279	/workspace/coverage/cover_reg_top/11.uart_tl_errors.3062077778	May 30 12:48:14 PM PDT 24	May 30 12:48:17 PM PDT 24	213368300 ps
T1280	/workspace/coverage/cover_reg_top/17.uart_intr_test.494439088	May 30 12:48:14 PM PDT 24	May 30 12:48:16 PM PDT 24	15915657 ps
T1281	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1479936923	May 30 12:48:26 PM PDT 24	May 30 12:48:27 PM PDT 24	97594692 ps
T1282	/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.831718835	May 30 12:48:27 PM PDT 24	May 30 12:48:29 PM PDT 24	28126533 ps
T1283	/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4005565177	May 30 12:47:58 PM PDT 24	May 30 12:48:00 PM PDT 24	49537846 ps
T1284	/workspace/coverage/cover_reg_top/29.uart_intr_test.491665929	May 30 12:48:30 PM PDT 24	May 30 12:48:32 PM PDT 24	12846202 ps
T1285	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.736942361	May 30 12:48:12 PM PDT 24	May 30 12:48:14 PM PDT 24	84910272 ps
T1286	/workspace/coverage/cover_reg_top/12.uart_csr_rw.3223771993	May 30 12:48:15 PM PDT 24	May 30 12:48:17 PM PDT 24	27997552 ps
T1287	/workspace/coverage/cover_reg_top/19.uart_tl_errors.1490716346	May 30 12:48:28 PM PDT 24	May 30 12:48:30 PM PDT 24	65047099 ps
T1288	/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3491532109	May 30 12:48:12 PM PDT 24	May 30 12:48:14 PM PDT 24	63727944 ps
T1289	/workspace/coverage/cover_reg_top/27.uart_intr_test.815921439	May 30 12:48:30 PM PDT 24	May 30 12:48:32 PM PDT 24	27034733 ps
T1290	/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.727330927	May 30 12:48:15 PM PDT 24	May 30 12:48:18 PM PDT 24	48948052 ps
T1291	/workspace/coverage/cover_reg_top/11.uart_intr_test.2818113297	May 30 12:48:13 PM PDT 24	May 30 12:48:15 PM PDT 24	39109584 ps
T1292	/workspace/coverage/cover_reg_top/4.uart_tl_errors.139583938	May 30 12:48:04 PM PDT 24	May 30 12:48:06 PM PDT 24	150764741 ps
T75	/workspace/coverage/cover_reg_top/3.uart_csr_rw.2200103940	May 30 12:48:05 PM PDT 24	May 30 12:48:06 PM PDT 24	67420603 ps
T1293	/workspace/coverage/cover_reg_top/0.uart_intr_test.1693281524	May 30 12:47:54 PM PDT 24	May 30 12:47:55 PM PDT 24	54794991 ps
T1294	/workspace/coverage/cover_reg_top/28.uart_intr_test.1546705179	May 30 12:48:26 PM PDT 24	May 30 12:48:28 PM PDT 24	34680162 ps
T1295	/workspace/coverage/cover_reg_top/16.uart_tl_errors.4006878087	May 30 12:48:17 PM PDT 24	May 30 12:48:21 PM PDT 24	116823523 ps
T1296	/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.318435679	May 30 12:48:00 PM PDT 24	May 30 12:48:02 PM PDT 24	105464002 ps
T1297	/workspace/coverage/cover_reg_top/5.uart_tl_errors.588214374	May 30 12:48:05 PM PDT 24	May 30 12:48:08 PM PDT 24	103863682 ps
T1298	/workspace/coverage/cover_reg_top/1.uart_tl_errors.2780576306	May 30 12:47:59 PM PDT 24	May 30 12:48:01 PM PDT 24	207544345 ps
T1299	/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1893051266	May 30 12:48:12 PM PDT 24	May 30 12:48:15 PM PDT 24	330192259 ps
T1300	/workspace/coverage/cover_reg_top/25.uart_intr_test.1162988323	May 30 12:48:29 PM PDT 24	May 30 12:48:31 PM PDT 24	14729475 ps
T1301	/workspace/coverage/cover_reg_top/44.uart_intr_test.3974120978	May 30 12:48:27 PM PDT 24	May 30 12:48:29 PM PDT 24	25724033 ps
T1302	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3216348206	May 30 12:48:04 PM PDT 24	May 30 12:48:06 PM PDT 24	98395916 ps
T1303	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1418170543	May 30 12:48:13 PM PDT 24	May 30 12:48:15 PM PDT 24	60354278 ps
T1304	/workspace/coverage/cover_reg_top/18.uart_intr_test.3526864990	May 30 12:48:30 PM PDT 24	May 30 12:48:32 PM PDT 24	42383426 ps
T1305	/workspace/coverage/cover_reg_top/20.uart_intr_test.2069540938	May 30 12:48:33 PM PDT 24	May 30 12:48:34 PM PDT 24	144839548 ps
T1306	/workspace/coverage/cover_reg_top/22.uart_intr_test.797559611	May 30 12:48:27 PM PDT 24	May 30 12:48:28 PM PDT 24	12335029 ps
T1307	/workspace/coverage/cover_reg_top/32.uart_intr_test.1012481145	May 30 12:48:30 PM PDT 24	May 30 12:48:32 PM PDT 24	10372145 ps
T1308	/workspace/coverage/cover_reg_top/40.uart_intr_test.204103396	May 30 12:48:31 PM PDT 24	May 30 12:48:33 PM PDT 24	41963925 ps
T1309	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3392025222	May 30 12:48:16 PM PDT 24	May 30 12:48:19 PM PDT 24	18011377 ps
T1310	/workspace/coverage/cover_reg_top/8.uart_intr_test.2659473804	May 30 12:48:10 PM PDT 24	May 30 12:48:11 PM PDT 24	113113884 ps
T1311	/workspace/coverage/cover_reg_top/31.uart_intr_test.1147877120	May 30 12:48:27 PM PDT 24	May 30 12:48:29 PM PDT 24	12949722 ps
T1312	/workspace/coverage/cover_reg_top/2.uart_csr_rw.1320856281	May 30 12:48:01 PM PDT 24	May 30 12:48:03 PM PDT 24	10980791 ps
T1313	/workspace/coverage/cover_reg_top/9.uart_csr_rw.769531032	May 30 12:48:01 PM PDT 24	May 30 12:48:03 PM PDT 24	66546599 ps
T1314	/workspace/coverage/cover_reg_top/7.uart_csr_rw.4133205568	May 30 12:47:59 PM PDT 24	May 30 12:48:01 PM PDT 24	40226288 ps
T1315	/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1573250624	May 30 12:48:17 PM PDT 24	May 30 12:48:19 PM PDT 24	18311765 ps
T1316	/workspace/coverage/cover_reg_top/4.uart_intr_test.2961164734	May 30 12:48:04 PM PDT 24	May 30 12:48:06 PM PDT 24	12749673 ps
T1317	/workspace/coverage/cover_reg_top/15.uart_tl_errors.2911958554	May 30 12:48:15 PM PDT 24	May 30 12:48:19 PM PDT 24	491357255 ps
T1318	/workspace/coverage/cover_reg_top/1.uart_csr_rw.3978081490	May 30 12:48:01 PM PDT 24	May 30 12:48:03 PM PDT 24	38092248 ps

Test location	/workspace/coverage/default/172.uart_fifo_reset.656329452
Short name	T4
Test name
Test status
Simulation time	64516204153 ps
CPU time	26.15 seconds
Started	May 30 12:54:02 PM PDT 24
Finished	May 30 12:54:29 PM PDT 24
Peak memory	200336 kb
Host	smart-f08ccf28-0293-474f-9d10-b559f0136606
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=656329452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.656329452
Directory	/workspace/172.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_stress_all_with_rand_reset.1818865255
Short name	T11
Test name
Test status
Simulation time	549406474226 ps
CPU time	1169.96 seconds
Started	May 30 12:51:40 PM PDT 24
Finished	May 30 01:11:11 PM PDT 24
Peak memory	228012 kb
Host	smart-48111bb9-942b-44df-a798-1b6d36034b1e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818865255 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1818865255
Directory	/workspace/29.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/77.uart_stress_all_with_rand_reset.300937968
Short name	T12
Test name
Test status
Simulation time	347208380728 ps
CPU time	458.9 seconds
Started	May 30 12:53:33 PM PDT 24
Finished	May 30 01:01:13 PM PDT 24
Peak memory	216852 kb
Host	smart-bad4d48c-8b51-4047-8806-05804e0cefaf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300937968 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.300937968
Directory	/workspace/77.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.uart_long_xfer_wo_dly.3135907426
Short name	T21
Test name
Test status
Simulation time	164517376900 ps
CPU time	1355.01 seconds
Started	May 30 12:53:10 PM PDT 24
Finished	May 30 01:15:47 PM PDT 24
Peak memory	200352 kb
Host	smart-e1d4698b-ef43-4dac-9dca-d59de6de7652
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3135907426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3135907426
Directory	/workspace/49.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/30.uart_stress_all.2106415937
Short name	T149
Test name
Test status
Simulation time	773907763523 ps
CPU time	443.57 seconds
Started	May 30 12:51:49 PM PDT 24
Finished	May 30 12:59:14 PM PDT 24
Peak memory	200328 kb
Host	smart-84bb0a68-d5d1-4b11-b813-00e2ad16c4a7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106415937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2106415937
Directory	/workspace/30.uart_stress_all/latest

Test location	/workspace/coverage/default/8.uart_long_xfer_wo_dly.4142204487
Short name	T258
Test name
Test status
Simulation time	81398505584 ps
CPU time	290.78 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 12:55:17 PM PDT 24
Peak memory	200312 kb
Host	smart-3b836c06-d93b-46f3-9b30-f467ec3d1bf0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4142204487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.4142204487
Directory	/workspace/8.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/38.uart_stress_all.898825675
Short name	T124
Test name
Test status
Simulation time	188497846436 ps
CPU time	300.69 seconds
Started	May 30 12:52:31 PM PDT 24
Finished	May 30 12:57:32 PM PDT 24
Peak memory	200312 kb
Host	smart-aa7dcfb1-83cc-444d-a7d0-60b683d71f17
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898825675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.898825675
Directory	/workspace/38.uart_stress_all/latest

Test location	/workspace/coverage/default/4.uart_sec_cm.3070190312
Short name	T27
Test name
Test status
Simulation time	55142844 ps
CPU time	0.86 seconds
Started	May 30 12:50:21 PM PDT 24
Finished	May 30 12:50:23 PM PDT 24
Peak memory	218528 kb
Host	smart-e3dac8d7-3dce-4ba3-9031-649b223ca85a
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070190312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3070190312
Directory	/workspace/4.uart_sec_cm/latest

Test location	/workspace/coverage/default/68.uart_stress_all_with_rand_reset.3203501049
Short name	T13
Test name
Test status
Simulation time	120632477646 ps
CPU time	842.36 seconds
Started	May 30 12:53:24 PM PDT 24
Finished	May 30 01:07:28 PM PDT 24
Peak memory	216888 kb
Host	smart-4becc818-e01b-4ade-a96f-b8912d16cb82
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203501049 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3203501049
Directory	/workspace/68.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.uart_stress_all_with_rand_reset.4131448380
Short name	T402
Test name
Test status
Simulation time	276732154584 ps
CPU time	1276.72 seconds
Started	May 30 12:52:47 PM PDT 24
Finished	May 30 01:14:04 PM PDT 24
Peak memory	226144 kb
Host	smart-3abe2bac-f73f-4534-b43d-e60258ee8b42
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131448380 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.4131448380
Directory	/workspace/42.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/231.uart_fifo_reset.180421745
Short name	T148
Test name
Test status
Simulation time	102121486450 ps
CPU time	197.95 seconds
Started	May 30 12:54:33 PM PDT 24
Finished	May 30 12:57:51 PM PDT 24
Peak memory	200396 kb
Host	smart-2fdfba31-7d3d-45e7-9a2c-21f37d16c293
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=180421745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.180421745
Directory	/workspace/231.uart_fifo_reset/latest

Test location	/workspace/coverage/default/93.uart_stress_all_with_rand_reset.262120457
Short name	T58
Test name
Test status
Simulation time	119005513944 ps
CPU time	1335.2 seconds
Started	May 30 12:53:39 PM PDT 24
Finished	May 30 01:15:55 PM PDT 24
Peak memory	228560 kb
Host	smart-a3840f27-cceb-4129-8ef0-e3aee98a6c65
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262120457 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.262120457
Directory	/workspace/93.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/52.uart_stress_all_with_rand_reset.1219143914
Short name	T326
Test name
Test status
Simulation time	941033450169 ps
CPU time	904.56 seconds
Started	May 30 12:53:08 PM PDT 24
Finished	May 30 01:08:14 PM PDT 24
Peak memory	225192 kb
Host	smart-4add2ac7-7332-41b2-9228-4f0866ef03eb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219143914 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1219143914
Directory	/workspace/52.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.uart_fifo_full.2852146289
Short name	T5
Test name
Test status
Simulation time	84970895256 ps
CPU time	31.6 seconds
Started	May 30 12:50:33 PM PDT 24
Finished	May 30 12:51:06 PM PDT 24
Peak memory	200328 kb
Host	smart-8a9ddfaf-ab66-47eb-9b2a-3ddf34713806
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852146289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2852146289
Directory	/workspace/11.uart_fifo_full/latest

Test location	/workspace/coverage/default/14.uart_fifo_overflow.1225790777
Short name	T162
Test name
Test status
Simulation time	29670582430 ps
CPU time	44.3 seconds
Started	May 30 12:50:43 PM PDT 24
Finished	May 30 12:51:28 PM PDT 24
Peak memory	199756 kb
Host	smart-74bdc678-2ca0-4b3d-9317-e34d1de5473f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1225790777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1225790777
Directory	/workspace/14.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/35.uart_stress_all.1393504300
Short name	T183
Test name
Test status
Simulation time	223376984982 ps
CPU time	136.62 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:54:33 PM PDT 24
Peak memory	200400 kb
Host	smart-50db992d-369d-4a00-98a1-420aa3de3ddf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393504300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1393504300
Directory	/workspace/35.uart_stress_all/latest

Test location	/workspace/coverage/default/94.uart_stress_all_with_rand_reset.3058080517
Short name	T30
Test name
Test status
Simulation time	109798339622 ps
CPU time	644.75 seconds
Started	May 30 12:53:41 PM PDT 24
Finished	May 30 01:04:26 PM PDT 24
Peak memory	216772 kb
Host	smart-3e4e1dac-397b-4cca-a4f5-15b9f062c7d7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058080517 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3058080517
Directory	/workspace/94.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2339674545
Short name	T96
Test name
Test status
Simulation time	369137671 ps
CPU time	1.32 seconds
Started	May 30 12:48:05 PM PDT 24
Finished	May 30 12:48:07 PM PDT 24
Peak memory	199636 kb
Host	smart-27f13e4b-898e-4aff-a8f7-317b1e230a14
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339674545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2339674545
Directory	/workspace/10.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/9.uart_stress_all_with_rand_reset.2675831922
Short name	T210
Test name
Test status
Simulation time	58726609641 ps
CPU time	785.65 seconds
Started	May 30 12:50:31 PM PDT 24
Finished	May 30 01:03:37 PM PDT 24
Peak memory	216972 kb
Host	smart-d6ce4b8f-14af-492a-9453-241f7cdbd084
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675831922 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2675831922
Directory	/workspace/9.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.uart_alert_test.3555261332
Short name	T369
Test name
Test status
Simulation time	13865638 ps
CPU time	0.61 seconds
Started	May 30 12:50:07 PM PDT 24
Finished	May 30 12:50:09 PM PDT 24
Peak memory	195064 kb
Host	smart-ed6eb28c-38b1-4233-b1ca-62a28f511a94
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555261332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3555261332
Directory	/workspace/1.uart_alert_test/latest

Test location	/workspace/coverage/default/37.uart_stress_all.382893656
Short name	T283
Test name
Test status
Simulation time	241266362560 ps
CPU time	174.69 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:55:29 PM PDT 24
Peak memory	208844 kb
Host	smart-ebb95d11-5683-4fa6-9f20-7ffe81247dcf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382893656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.382893656
Directory	/workspace/37.uart_stress_all/latest

Test location	/workspace/coverage/default/145.uart_fifo_reset.2622406401
Short name	T208
Test name
Test status
Simulation time	195063707301 ps
CPU time	62.22 seconds
Started	May 30 12:53:51 PM PDT 24
Finished	May 30 12:54:54 PM PDT 24
Peak memory	200388 kb
Host	smart-dbe73d9a-2c3e-4f7d-ad40-df85ccc38ce8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622406401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2622406401
Directory	/workspace/145.uart_fifo_reset/latest

Test location	/workspace/coverage/default/42.uart_fifo_full.2206243362
Short name	T144
Test name
Test status
Simulation time	179297344197 ps
CPU time	122.81 seconds
Started	May 30 12:52:32 PM PDT 24
Finished	May 30 12:54:36 PM PDT 24
Peak memory	200340 kb
Host	smart-b6820bdf-742a-4c0a-a901-52c910f1ea23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2206243362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2206243362
Directory	/workspace/42.uart_fifo_full/latest

Test location	/workspace/coverage/default/175.uart_fifo_reset.2685235621
Short name	T42
Test name
Test status
Simulation time	41830929554 ps
CPU time	83.14 seconds
Started	May 30 12:54:00 PM PDT 24
Finished	May 30 12:55:24 PM PDT 24
Peak memory	200340 kb
Host	smart-f9db4452-29fd-469a-b47e-6db288d0b3b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685235621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2685235621
Directory	/workspace/175.uart_fifo_reset/latest

Test location	/workspace/coverage/default/147.uart_fifo_reset.3450689212
Short name	T275
Test name
Test status
Simulation time	258006819821 ps
CPU time	23.53 seconds
Started	May 30 12:53:51 PM PDT 24
Finished	May 30 12:54:16 PM PDT 24
Peak memory	200356 kb
Host	smart-37f69d14-1fad-4e03-b293-a9c41b52a4df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450689212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3450689212
Directory	/workspace/147.uart_fifo_reset/latest

Test location	/workspace/coverage/default/242.uart_fifo_reset.2092879658
Short name	T137
Test name
Test status
Simulation time	130716647418 ps
CPU time	219.43 seconds
Started	May 30 12:54:35 PM PDT 24
Finished	May 30 12:58:15 PM PDT 24
Peak memory	200376 kb
Host	smart-7adaaa4d-2c23-480c-9791-d3e7d464f466
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2092879658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2092879658
Directory	/workspace/242.uart_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3734753327
Short name	T69
Test name
Test status
Simulation time	79624209 ps
CPU time	0.59 seconds
Started	May 30 12:47:55 PM PDT 24
Finished	May 30 12:47:56 PM PDT 24
Peak memory	195640 kb
Host	smart-dc88f916-7dc9-4b4f-b436-b67ef00010ec
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734753327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3734753327
Directory	/workspace/0.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_rw.3140744974
Short name	T87
Test name
Test status
Simulation time	59391432 ps
CPU time	0.58 seconds
Started	May 30 12:48:15 PM PDT 24
Finished	May 30 12:48:18 PM PDT 24
Peak memory	195768 kb
Host	smart-fe678fc7-10e9-4128-850f-7b7d1bef172f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140744974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3140744974
Directory	/workspace/10.uart_csr_rw/latest

Test location	/workspace/coverage/default/75.uart_stress_all_with_rand_reset.2509998330
Short name	T174
Test name
Test status
Simulation time	430173609989 ps
CPU time	1057.07 seconds
Started	May 30 12:53:38 PM PDT 24
Finished	May 30 01:11:16 PM PDT 24
Peak memory	225168 kb
Host	smart-2e270b74-4bc1-49fa-93e1-d3caa1ea0d25
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509998330 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2509998330
Directory	/workspace/75.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.uart_stress_all.3780127737
Short name	T129
Test name
Test status
Simulation time	133757983186 ps
CPU time	248.33 seconds
Started	May 30 12:51:40 PM PDT 24
Finished	May 30 12:55:49 PM PDT 24
Peak memory	208792 kb
Host	smart-cc4e2bde-8c34-4459-891d-960a85cb9b39
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780127737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3780127737
Directory	/workspace/28.uart_stress_all/latest

Test location	/workspace/coverage/default/5.uart_stress_all.3920759960
Short name	T169
Test name
Test status
Simulation time	473306304545 ps
CPU time	226.43 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 12:54:14 PM PDT 24
Peak memory	208684 kb
Host	smart-389da531-77eb-4b2c-9793-2d57e49a782d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920759960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3920759960
Directory	/workspace/5.uart_stress_all/latest

Test location	/workspace/coverage/default/204.uart_fifo_reset.2353611190
Short name	T136
Test name
Test status
Simulation time	80601406446 ps
CPU time	193.88 seconds
Started	May 30 12:54:15 PM PDT 24
Finished	May 30 12:57:30 PM PDT 24
Peak memory	200368 kb
Host	smart-36323de1-8200-4438-97f8-597f77628a15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2353611190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2353611190
Directory	/workspace/204.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_fifo_full.283261757
Short name	T130
Test name
Test status
Simulation time	118974123082 ps
CPU time	57.73 seconds
Started	May 30 12:50:47 PM PDT 24
Finished	May 30 12:51:46 PM PDT 24
Peak memory	200316 kb
Host	smart-3601828e-fe04-4034-a82a-1e5d6785fe69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283261757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.283261757
Directory	/workspace/16.uart_fifo_full/latest

Test location	/workspace/coverage/default/194.uart_fifo_reset.467493401
Short name	T22
Test name
Test status
Simulation time	74138274012 ps
CPU time	46.1 seconds
Started	May 30 12:54:14 PM PDT 24
Finished	May 30 12:55:00 PM PDT 24
Peak memory	200312 kb
Host	smart-ff8f2fc9-15ce-4393-9667-1d1b8a05cb84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=467493401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.467493401
Directory	/workspace/194.uart_fifo_reset/latest

Test location	/workspace/coverage/default/228.uart_fifo_reset.2276080691
Short name	T214
Test name
Test status
Simulation time	66257289649 ps
CPU time	47.84 seconds
Started	May 30 12:54:35 PM PDT 24
Finished	May 30 12:55:24 PM PDT 24
Peak memory	200312 kb
Host	smart-7e0cf82a-27e6-4a2a-8de1-9c06e5d8351f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276080691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2276080691
Directory	/workspace/228.uart_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3807981324
Short name	T91
Test name
Test status
Simulation time	67176566 ps
CPU time	1.26 seconds
Started	May 30 12:47:52 PM PDT 24
Finished	May 30 12:47:54 PM PDT 24
Peak memory	199440 kb
Host	smart-5dc2ff9c-961d-4b0d-b2dd-04914e3c6820
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807981324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3807981324
Directory	/workspace/0.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/232.uart_fifo_reset.1639201033
Short name	T180
Test name
Test status
Simulation time	124606562694 ps
CPU time	39.31 seconds
Started	May 30 12:54:36 PM PDT 24
Finished	May 30 12:55:16 PM PDT 24
Peak memory	200328 kb
Host	smart-27ad751b-7b15-476d-8bf2-c983e8baecf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639201033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1639201033
Directory	/workspace/232.uart_fifo_reset/latest

Test location	/workspace/coverage/default/267.uart_fifo_reset.2542540664
Short name	T152
Test name
Test status
Simulation time	116172673806 ps
CPU time	92.12 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 12:56:21 PM PDT 24
Peak memory	200348 kb
Host	smart-805c83f5-a45e-4a43-863d-33affd57cff0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542540664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2542540664
Directory	/workspace/267.uart_fifo_reset/latest

Test location	/workspace/coverage/default/20.uart_fifo_full.1771678488
Short name	T281
Test name
Test status
Simulation time	104188257133 ps
CPU time	53.93 seconds
Started	May 30 12:51:02 PM PDT 24
Finished	May 30 12:51:57 PM PDT 24
Peak memory	200256 kb
Host	smart-b6a30757-0309-4302-ada6-3ecb5804a652
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1771678488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1771678488
Directory	/workspace/20.uart_fifo_full/latest

Test location	/workspace/coverage/default/288.uart_fifo_reset.3562048444
Short name	T207
Test name
Test status
Simulation time	12044054110 ps
CPU time	19.51 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 12:55:08 PM PDT 24
Peak memory	200388 kb
Host	smart-0e9c1c2a-3802-4f38-8a89-52d89a25a385
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3562048444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3562048444
Directory	/workspace/288.uart_fifo_reset/latest

Test location	/workspace/coverage/default/107.uart_fifo_reset.236525470
Short name	T244
Test name
Test status
Simulation time	58871287855 ps
CPU time	59.42 seconds
Started	May 30 12:53:47 PM PDT 24
Finished	May 30 12:54:48 PM PDT 24
Peak memory	200052 kb
Host	smart-14390a19-a687-46ff-9036-582497ed8fe3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=236525470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.236525470
Directory	/workspace/107.uart_fifo_reset/latest

Test location	/workspace/coverage/default/159.uart_fifo_reset.1315395324
Short name	T163
Test name
Test status
Simulation time	54906986828 ps
CPU time	117.14 seconds
Started	May 30 12:54:04 PM PDT 24
Finished	May 30 12:56:03 PM PDT 24
Peak memory	200224 kb
Host	smart-3d5cc910-b823-4f62-9dbb-6b5285948d28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315395324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1315395324
Directory	/workspace/159.uart_fifo_reset/latest

Test location	/workspace/coverage/default/48.uart_stress_all.3361603153
Short name	T193
Test name
Test status
Simulation time	81318629843 ps
CPU time	105.72 seconds
Started	May 30 12:53:09 PM PDT 24
Finished	May 30 12:54:56 PM PDT 24
Peak memory	200708 kb
Host	smart-55b2446d-da17-4ed9-b614-20351616607d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361603153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3361603153
Directory	/workspace/48.uart_stress_all/latest

Test location	/workspace/coverage/default/96.uart_stress_all_with_rand_reset.4014013260
Short name	T116
Test name
Test status
Simulation time	148881435993 ps
CPU time	370.89 seconds
Started	May 30 12:53:38 PM PDT 24
Finished	May 30 12:59:50 PM PDT 24
Peak memory	225136 kb
Host	smart-12c77052-67bd-4f29-ac97-db62fe046bf5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014013260 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.4014013260
Directory	/workspace/96.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/210.uart_fifo_reset.92103492
Short name	T341
Test name
Test status
Simulation time	94452359905 ps
CPU time	245.3 seconds
Started	May 30 12:54:22 PM PDT 24
Finished	May 30 12:58:28 PM PDT 24
Peak memory	200252 kb
Host	smart-cf736919-433d-4a37-b37c-a07cf7aeb49a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92103492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.92103492
Directory	/workspace/210.uart_fifo_reset/latest

Test location	/workspace/coverage/default/49.uart_fifo_reset.4159082371
Short name	T196
Test name
Test status
Simulation time	55070255091 ps
CPU time	12.91 seconds
Started	May 30 12:53:10 PM PDT 24
Finished	May 30 12:53:24 PM PDT 24
Peak memory	200388 kb
Host	smart-213730f7-c19f-404a-8275-97a9f241b5bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4159082371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.4159082371
Directory	/workspace/49.uart_fifo_reset/latest

Test location	/workspace/coverage/default/76.uart_stress_all_with_rand_reset.4013917928
Short name	T255
Test name
Test status
Simulation time	119842208334 ps
CPU time	540.38 seconds
Started	May 30 12:53:35 PM PDT 24
Finished	May 30 01:02:36 PM PDT 24
Peak memory	216764 kb
Host	smart-92470860-495d-4528-a734-ecc1fd4e4bac
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013917928 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.4013917928
Directory	/workspace/76.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/109.uart_fifo_reset.2024546674
Short name	T199
Test name
Test status
Simulation time	173328376086 ps
CPU time	40.18 seconds
Started	May 30 12:53:49 PM PDT 24
Finished	May 30 12:54:30 PM PDT 24
Peak memory	200304 kb
Host	smart-1cb1fed4-1f5d-48f2-9970-f9405b5f17ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2024546674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2024546674
Directory	/workspace/109.uart_fifo_reset/latest

Test location	/workspace/coverage/default/115.uart_fifo_reset.1145562620
Short name	T223
Test name
Test status
Simulation time	48963668599 ps
CPU time	51.14 seconds
Started	May 30 12:53:47 PM PDT 24
Finished	May 30 12:54:39 PM PDT 24
Peak memory	200356 kb
Host	smart-34da2a35-f4e9-4f35-bd76-fdadeb339099
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145562620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1145562620
Directory	/workspace/115.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_long_xfer_wo_dly.3908027317
Short name	T268
Test name
Test status
Simulation time	96615739389 ps
CPU time	324.7 seconds
Started	May 30 12:50:37 PM PDT 24
Finished	May 30 12:56:02 PM PDT 24
Peak memory	200472 kb
Host	smart-c5c145e8-07d3-499f-8121-be49ab44f675
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3908027317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3908027317
Directory	/workspace/13.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/169.uart_fifo_reset.2519524752
Short name	T220
Test name
Test status
Simulation time	99983727479 ps
CPU time	18.97 seconds
Started	May 30 12:54:01 PM PDT 24
Finished	May 30 12:54:22 PM PDT 24
Peak memory	200396 kb
Host	smart-4f68913e-ad62-43b8-81d1-142e828aab41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2519524752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2519524752
Directory	/workspace/169.uart_fifo_reset/latest

Test location	/workspace/coverage/default/201.uart_fifo_reset.1739885247
Short name	T213
Test name
Test status
Simulation time	36897324051 ps
CPU time	99.25 seconds
Started	May 30 12:54:13 PM PDT 24
Finished	May 30 12:55:53 PM PDT 24
Peak memory	200376 kb
Host	smart-9d1749a7-1b61-4a40-a3d2-d76f4568253b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1739885247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1739885247
Directory	/workspace/201.uart_fifo_reset/latest

Test location	/workspace/coverage/default/207.uart_fifo_reset.3098206615
Short name	T216
Test name
Test status
Simulation time	29315283382 ps
CPU time	27.39 seconds
Started	May 30 12:54:13 PM PDT 24
Finished	May 30 12:54:41 PM PDT 24
Peak memory	200428 kb
Host	smart-e851c90c-d2a7-4ed9-95cd-7de9650d6eec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3098206615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3098206615
Directory	/workspace/207.uart_fifo_reset/latest

Test location	/workspace/coverage/default/279.uart_fifo_reset.394106363
Short name	T226
Test name
Test status
Simulation time	197255777328 ps
CPU time	95.06 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 12:56:24 PM PDT 24
Peak memory	200328 kb
Host	smart-b2f1fb89-f11f-47e1-9005-81946ecc6d1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394106363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.394106363
Directory	/workspace/279.uart_fifo_reset/latest

Test location	/workspace/coverage/default/287.uart_fifo_reset.622207666
Short name	T181
Test name
Test status
Simulation time	71647354633 ps
CPU time	50.6 seconds
Started	May 30 12:54:46 PM PDT 24
Finished	May 30 12:55:38 PM PDT 24
Peak memory	200320 kb
Host	smart-77959931-02cf-44b6-be9f-27d9377b2a69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622207666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.622207666
Directory	/workspace/287.uart_fifo_reset/latest

Test location	/workspace/coverage/default/38.uart_tx_rx.2861852846
Short name	T260
Test name
Test status
Simulation time	163351928609 ps
CPU time	65.82 seconds
Started	May 30 12:52:34 PM PDT 24
Finished	May 30 12:53:41 PM PDT 24
Peak memory	200360 kb
Host	smart-6343153b-fd3c-47c1-9d1a-c851d7cbec53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2861852846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2861852846
Directory	/workspace/38.uart_tx_rx/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1833135806
Short name	T93
Test name
Test status
Simulation time	44321001 ps
CPU time	0.93 seconds
Started	May 30 12:48:19 PM PDT 24
Finished	May 30 12:48:20 PM PDT 24
Peak memory	198864 kb
Host	smart-b97fceec-2f0e-4ac9-a19d-7b5bc31fa2db
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833135806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1833135806
Directory	/workspace/12.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/0.uart_fifo_reset.2347569267
Short name	T251
Test name
Test status
Simulation time	66837572519 ps
CPU time	189.03 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:53:23 PM PDT 24
Peak memory	199788 kb
Host	smart-8799e8b5-ed1f-44eb-a751-e10434a118a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2347569267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2347569267
Directory	/workspace/0.uart_fifo_reset/latest

Test location	/workspace/coverage/default/10.uart_stress_all.3266591800
Short name	T759
Test name
Test status
Simulation time	196582745511 ps
CPU time	61.19 seconds
Started	May 30 12:50:31 PM PDT 24
Finished	May 30 12:51:33 PM PDT 24
Peak memory	200376 kb
Host	smart-51b16f5a-0040-4e0b-9ddb-9e1eb66e435b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266591800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3266591800
Directory	/workspace/10.uart_stress_all/latest

Test location	/workspace/coverage/default/100.uart_fifo_reset.3487846245
Short name	T248
Test name
Test status
Simulation time	58621183506 ps
CPU time	27.58 seconds
Started	May 30 12:53:36 PM PDT 24
Finished	May 30 12:54:05 PM PDT 24
Peak memory	200328 kb
Host	smart-e9e832c2-4840-4534-a7e9-ccb2001614fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3487846245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3487846245
Directory	/workspace/100.uart_fifo_reset/latest

Test location	/workspace/coverage/default/131.uart_fifo_reset.1860517948
Short name	T250
Test name
Test status
Simulation time	91382655723 ps
CPU time	39.63 seconds
Started	May 30 12:53:47 PM PDT 24
Finished	May 30 12:54:27 PM PDT 24
Peak memory	200248 kb
Host	smart-e0a29b05-5fc1-4375-bb23-3519841bb887
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1860517948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1860517948
Directory	/workspace/131.uart_fifo_reset/latest

Test location	/workspace/coverage/default/132.uart_fifo_reset.1097115439
Short name	T172
Test name
Test status
Simulation time	161783429960 ps
CPU time	203.92 seconds
Started	May 30 12:53:54 PM PDT 24
Finished	May 30 12:57:19 PM PDT 24
Peak memory	200308 kb
Host	smart-5b6b181b-bc44-4d5c-b836-9353253048da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1097115439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1097115439
Directory	/workspace/132.uart_fifo_reset/latest

Test location	/workspace/coverage/default/134.uart_fifo_reset.3152996832
Short name	T237
Test name
Test status
Simulation time	49693293800 ps
CPU time	87.38 seconds
Started	May 30 12:53:48 PM PDT 24
Finished	May 30 12:55:16 PM PDT 24
Peak memory	200408 kb
Host	smart-8db3a738-2254-4e29-8e60-0393e23ba72e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152996832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3152996832
Directory	/workspace/134.uart_fifo_reset/latest

Test location	/workspace/coverage/default/155.uart_fifo_reset.2623258368
Short name	T238
Test name
Test status
Simulation time	29470864029 ps
CPU time	57.31 seconds
Started	May 30 12:54:00 PM PDT 24
Finished	May 30 12:54:58 PM PDT 24
Peak memory	200308 kb
Host	smart-c8336e13-aa95-4938-90ec-5204895785c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623258368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2623258368
Directory	/workspace/155.uart_fifo_reset/latest

Test location	/workspace/coverage/default/170.uart_fifo_reset.1123380816
Short name	T215
Test name
Test status
Simulation time	76206566218 ps
CPU time	42.88 seconds
Started	May 30 12:54:00 PM PDT 24
Finished	May 30 12:54:44 PM PDT 24
Peak memory	200396 kb
Host	smart-e5616b3a-6677-4ebe-b2bd-ca174f1e0525
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123380816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1123380816
Directory	/workspace/170.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_fifo_reset.120416321
Short name	T189
Test name
Test status
Simulation time	6483229507 ps
CPU time	9.87 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 12:51:13 PM PDT 24
Peak memory	200344 kb
Host	smart-ff4a6e79-6cb7-40a5-aba2-8ac8e84c6256
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=120416321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.120416321
Directory	/workspace/18.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_rx_parity_err.3873501448
Short name	T186
Test name
Test status
Simulation time	28420464045 ps
CPU time	48.78 seconds
Started	May 30 12:51:01 PM PDT 24
Finished	May 30 12:51:51 PM PDT 24
Peak memory	200336 kb
Host	smart-1392a343-9530-4377-acec-f34459fed1a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3873501448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3873501448
Directory	/workspace/18.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/205.uart_fifo_reset.2313838640
Short name	T139
Test name
Test status
Simulation time	167810762905 ps
CPU time	86.62 seconds
Started	May 30 12:54:14 PM PDT 24
Finished	May 30 12:55:41 PM PDT 24
Peak memory	200280 kb
Host	smart-af91a2f9-f0d3-4335-b6ff-ef650a90366e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313838640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2313838640
Directory	/workspace/205.uart_fifo_reset/latest

Test location	/workspace/coverage/default/217.uart_fifo_reset.1297301691
Short name	T254
Test name
Test status
Simulation time	171061608432 ps
CPU time	258.25 seconds
Started	May 30 12:54:17 PM PDT 24
Finished	May 30 12:58:36 PM PDT 24
Peak memory	200340 kb
Host	smart-5dd9afb4-3e86-411c-b6b0-50cd8f520570
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1297301691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1297301691
Directory	/workspace/217.uart_fifo_reset/latest

Test location	/workspace/coverage/default/220.uart_fifo_reset.1417326074
Short name	T242
Test name
Test status
Simulation time	32496533208 ps
CPU time	44.64 seconds
Started	May 30 12:54:13 PM PDT 24
Finished	May 30 12:54:58 PM PDT 24
Peak memory	200408 kb
Host	smart-22f627d1-1669-459c-b4e0-918727d7ff2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1417326074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1417326074
Directory	/workspace/220.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_stress_all_with_rand_reset.1405415688
Short name	T234
Test name
Test status
Simulation time	221347936747 ps
CPU time	415.09 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 12:58:24 PM PDT 24
Peak memory	208856 kb
Host	smart-d17a0a3e-ea0d-4fa8-9d7b-23afedd66936
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405415688 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1405415688
Directory	/workspace/24.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/250.uart_fifo_reset.1629253190
Short name	T247
Test name
Test status
Simulation time	57462916650 ps
CPU time	18.65 seconds
Started	May 30 12:54:33 PM PDT 24
Finished	May 30 12:54:52 PM PDT 24
Peak memory	200360 kb
Host	smart-3ebb52c7-765a-4a86-a867-4951637020ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629253190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1629253190
Directory	/workspace/250.uart_fifo_reset/latest

Test location	/workspace/coverage/default/258.uart_fifo_reset.36550557
Short name	T232
Test name
Test status
Simulation time	120141207001 ps
CPU time	372.06 seconds
Started	May 30 12:54:46 PM PDT 24
Finished	May 30 01:00:59 PM PDT 24
Peak memory	200300 kb
Host	smart-23ef454d-8e3f-4c25-9b7e-bfeb4e20ea2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36550557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.36550557
Directory	/workspace/258.uart_fifo_reset/latest

Test location	/workspace/coverage/default/42.uart_fifo_reset.3773069387
Short name	T246
Test name
Test status
Simulation time	133743482458 ps
CPU time	65.27 seconds
Started	May 30 12:52:44 PM PDT 24
Finished	May 30 12:53:50 PM PDT 24
Peak memory	200320 kb
Host	smart-8fad80a5-0156-4194-bfa1-f38582b8d890
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3773069387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3773069387
Directory	/workspace/42.uart_fifo_reset/latest

Test location	/workspace/coverage/default/57.uart_fifo_reset.1144282360
Short name	T245
Test name
Test status
Simulation time	100204257634 ps
CPU time	88.46 seconds
Started	May 30 12:53:21 PM PDT 24
Finished	May 30 12:54:50 PM PDT 24
Peak memory	200276 kb
Host	smart-f2048f8e-f6c7-4a72-b74e-2a16671f1930
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1144282360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1144282360
Directory	/workspace/57.uart_fifo_reset/latest

Test location	/workspace/coverage/default/9.uart_fifo_reset.908676768
Short name	T240
Test name
Test status
Simulation time	36991656483 ps
CPU time	60.77 seconds
Started	May 30 12:50:34 PM PDT 24
Finished	May 30 12:51:36 PM PDT 24
Peak memory	200380 kb
Host	smart-d247b19c-c49d-4613-8b3e-209bb11a6443
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=908676768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.908676768
Directory	/workspace/9.uart_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2227774154
Short name	T1214
Test name
Test status
Simulation time	15938631 ps
CPU time	0.65 seconds
Started	May 30 12:48:06 PM PDT 24
Finished	May 30 12:48:07 PM PDT 24
Peak memory	195636 kb
Host	smart-890fd348-f8d1-4ce7-b964-0649ed4ce304
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227774154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2227774154
Directory	/workspace/0.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.612968154
Short name	T1192
Test name
Test status
Simulation time	171476436 ps
CPU time	2.32 seconds
Started	May 30 12:47:55 PM PDT 24
Finished	May 30 12:47:58 PM PDT 24
Peak memory	197888 kb
Host	smart-69cf1a9d-a8ed-44e5-9a3d-7fd949dc3626
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612968154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.612968154
Directory	/workspace/0.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.636488760
Short name	T1198
Test name
Test status
Simulation time	103043597 ps
CPU time	0.89 seconds
Started	May 30 12:48:00 PM PDT 24
Finished	May 30 12:48:02 PM PDT 24
Peak memory	199932 kb
Host	smart-9674221c-e5c6-4d41-8688-bccd330ce2bb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636488760 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.636488760
Directory	/workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_rw.1029427841
Short name	T1245
Test name
Test status
Simulation time	13141361 ps
CPU time	0.57 seconds
Started	May 30 12:47:55 PM PDT 24
Finished	May 30 12:47:56 PM PDT 24
Peak memory	195636 kb
Host	smart-b43180a8-f3d4-4c82-a600-368ea7ca636b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029427841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1029427841
Directory	/workspace/0.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_intr_test.1693281524
Short name	T1293
Test name
Test status
Simulation time	54794991 ps
CPU time	0.56 seconds
Started	May 30 12:47:54 PM PDT 24
Finished	May 30 12:47:55 PM PDT 24
Peak memory	194488 kb
Host	smart-22682bf5-eb97-4c9e-8156-0bb9dbca003c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693281524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1693281524
Directory	/workspace/0.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1663835771
Short name	T1227
Test name
Test status
Simulation time	30476474 ps
CPU time	0.76 seconds
Started	May 30 12:47:59 PM PDT 24
Finished	May 30 12:48:00 PM PDT 24
Peak memory	197252 kb
Host	smart-4329bb2e-212b-4e68-b3a9-a5e86f8b60b4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663835771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr _outstanding.1663835771
Directory	/workspace/0.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_errors.3048960529
Short name	T1261
Test name
Test status
Simulation time	47145715 ps
CPU time	2.21 seconds
Started	May 30 12:47:51 PM PDT 24
Finished	May 30 12:47:53 PM PDT 24
Peak memory	200256 kb
Host	smart-6d99a81e-3326-4f38-93c2-d16afe4b8bf9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048960529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3048960529
Directory	/workspace/0.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.296145767
Short name	T74
Test name
Test status
Simulation time	21763822 ps
CPU time	0.71 seconds
Started	May 30 12:48:00 PM PDT 24
Finished	May 30 12:48:02 PM PDT 24
Peak memory	195516 kb
Host	smart-8e8d480d-8aaf-4c52-990f-50958cff0e5d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296145767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.296145767
Directory	/workspace/1.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.632239061
Short name	T68
Test name
Test status
Simulation time	221615033 ps
CPU time	2.19 seconds
Started	May 30 12:48:01 PM PDT 24
Finished	May 30 12:48:04 PM PDT 24
Peak memory	197812 kb
Host	smart-5bda7f89-5d68-499c-b493-44baed63ca41
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632239061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.632239061
Directory	/workspace/1.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1848855631
Short name	T1265
Test name
Test status
Simulation time	42403053 ps
CPU time	0.58 seconds
Started	May 30 12:47:58 PM PDT 24
Finished	May 30 12:47:59 PM PDT 24
Peak memory	195540 kb
Host	smart-986b4057-72e7-4128-833b-c50a63c52802
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848855631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1848855631
Directory	/workspace/1.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2112116532
Short name	T1247
Test name
Test status
Simulation time	34084724 ps
CPU time	0.82 seconds
Started	May 30 12:48:10 PM PDT 24
Finished	May 30 12:48:12 PM PDT 24
Peak memory	199932 kb
Host	smart-b40add1b-398f-47b5-95b1-7be8657711b2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112116532 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2112116532
Directory	/workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_rw.3978081490
Short name	T1318
Test name
Test status
Simulation time	38092248 ps
CPU time	0.64 seconds
Started	May 30 12:48:01 PM PDT 24
Finished	May 30 12:48:03 PM PDT 24
Peak memory	195628 kb
Host	smart-92967d16-db1f-4a10-b1c7-3e2490ce6269
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978081490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3978081490
Directory	/workspace/1.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_intr_test.2199379395
Short name	T1272
Test name
Test status
Simulation time	116437329 ps
CPU time	0.57 seconds
Started	May 30 12:48:02 PM PDT 24
Finished	May 30 12:48:04 PM PDT 24
Peak memory	194584 kb
Host	smart-93c21c2c-da8d-4101-ad51-fece1ccd26ae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199379395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2199379395
Directory	/workspace/1.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3179130956
Short name	T1259
Test name
Test status
Simulation time	95649351 ps
CPU time	0.77 seconds
Started	May 30 12:48:03 PM PDT 24
Finished	May 30 12:48:04 PM PDT 24
Peak memory	196096 kb
Host	smart-d342f592-1bf3-4235-ac9e-3d85603a448e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179130956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr _outstanding.3179130956
Directory	/workspace/1.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_errors.2780576306
Short name	T1298
Test name
Test status
Simulation time	207544345 ps
CPU time	1.32 seconds
Started	May 30 12:47:59 PM PDT 24
Finished	May 30 12:48:01 PM PDT 24
Peak memory	200196 kb
Host	smart-2c1f2bde-80c3-4655-99ca-7e8b88c4c2a4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780576306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2780576306
Directory	/workspace/1.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1482955452
Short name	T1249
Test name
Test status
Simulation time	50232718 ps
CPU time	0.88 seconds
Started	May 30 12:47:58 PM PDT 24
Finished	May 30 12:48:00 PM PDT 24
Peak memory	198888 kb
Host	smart-bde976f4-a4fa-4894-b89f-18c661ff0819
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482955452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1482955452
Directory	/workspace/1.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3785178898
Short name	T1260
Test name
Test status
Simulation time	27498020 ps
CPU time	0.77 seconds
Started	May 30 12:48:13 PM PDT 24
Finished	May 30 12:48:15 PM PDT 24
Peak memory	198900 kb
Host	smart-4aee786c-a06a-42c6-a0e3-1fe9077bdb8c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785178898 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3785178898
Directory	/workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_intr_test.1867732196
Short name	T1193
Test name
Test status
Simulation time	15494166 ps
CPU time	0.53 seconds
Started	May 30 12:48:12 PM PDT 24
Finished	May 30 12:48:14 PM PDT 24
Peak memory	194496 kb
Host	smart-683f366e-30cc-41d1-a18e-fbbf64e3bb6c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867732196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1867732196
Directory	/workspace/10.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3114071618
Short name	T85
Test name
Test status
Simulation time	15755641 ps
CPU time	0.68 seconds
Started	May 30 12:48:16 PM PDT 24
Finished	May 30 12:48:19 PM PDT 24
Peak memory	197104 kb
Host	smart-3c36c492-bc8f-4e92-b0f4-5c6773ff12f9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114071618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs r_outstanding.3114071618
Directory	/workspace/10.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_errors.3219911640
Short name	T1188
Test name
Test status
Simulation time	184963815 ps
CPU time	1.77 seconds
Started	May 30 12:48:03 PM PDT 24
Finished	May 30 12:48:05 PM PDT 24
Peak memory	200188 kb
Host	smart-f014f2ac-fc6d-4410-acd8-c67b7b0fe0c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219911640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3219911640
Directory	/workspace/10.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1576955666
Short name	T1277
Test name
Test status
Simulation time	26833284 ps
CPU time	0.82 seconds
Started	May 30 12:48:15 PM PDT 24
Finished	May 30 12:48:18 PM PDT 24
Peak memory	199832 kb
Host	smart-e16dc33b-f7fa-41ff-bc1a-da8e5bd2b1b5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576955666 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1576955666
Directory	/workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_rw.859691718
Short name	T81
Test name
Test status
Simulation time	44867336 ps
CPU time	0.61 seconds
Started	May 30 12:48:12 PM PDT 24
Finished	May 30 12:48:13 PM PDT 24
Peak memory	195716 kb
Host	smart-3c20e069-c65f-43a1-9b20-ff902cce6fcb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859691718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.859691718
Directory	/workspace/11.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_intr_test.2818113297
Short name	T1291
Test name
Test status
Simulation time	39109584 ps
CPU time	0.55 seconds
Started	May 30 12:48:13 PM PDT 24
Finished	May 30 12:48:15 PM PDT 24
Peak memory	194512 kb
Host	smart-74d017c6-6bac-4d30-98bb-1bc461f2e614
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818113297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2818113297
Directory	/workspace/11.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.727330927
Short name	T1290
Test name
Test status
Simulation time	48948052 ps
CPU time	0.79 seconds
Started	May 30 12:48:15 PM PDT 24
Finished	May 30 12:48:18 PM PDT 24
Peak memory	197248 kb
Host	smart-052bfa48-b23e-44fe-b07f-a6382ef233eb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727330927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr _outstanding.727330927
Directory	/workspace/11.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_errors.3062077778
Short name	T1279
Test name
Test status
Simulation time	213368300 ps
CPU time	1.45 seconds
Started	May 30 12:48:14 PM PDT 24
Finished	May 30 12:48:17 PM PDT 24
Peak memory	200304 kb
Host	smart-26eba659-05e5-447d-91cf-f927361f6d7d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062077778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3062077778
Directory	/workspace/11.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1893051266
Short name	T1299
Test name
Test status
Simulation time	330192259 ps
CPU time	1.4 seconds
Started	May 30 12:48:12 PM PDT 24
Finished	May 30 12:48:15 PM PDT 24
Peak memory	199496 kb
Host	smart-f338c715-5d3c-4b32-81b7-c0d7684ebd95
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893051266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1893051266
Directory	/workspace/11.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1984241501
Short name	T1190
Test name
Test status
Simulation time	211838390 ps
CPU time	1.14 seconds
Started	May 30 12:48:17 PM PDT 24
Finished	May 30 12:48:20 PM PDT 24
Peak memory	199988 kb
Host	smart-df339bd4-c358-429a-8fd3-57f72435c32d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984241501 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1984241501
Directory	/workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_rw.3223771993
Short name	T1286
Test name
Test status
Simulation time	27997552 ps
CPU time	0.6 seconds
Started	May 30 12:48:15 PM PDT 24
Finished	May 30 12:48:17 PM PDT 24
Peak memory	195652 kb
Host	smart-27bbc859-11e6-4481-a3e9-8b1167b34dca
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223771993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3223771993
Directory	/workspace/12.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_intr_test.1817014456
Short name	T1234
Test name
Test status
Simulation time	68387548 ps
CPU time	0.58 seconds
Started	May 30 12:48:16 PM PDT 24
Finished	May 30 12:48:18 PM PDT 24
Peak memory	194468 kb
Host	smart-36009c59-b483-4268-a15a-36e96709bf4a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817014456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1817014456
Directory	/workspace/12.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1804252471
Short name	T89
Test name
Test status
Simulation time	105308528 ps
CPU time	0.66 seconds
Started	May 30 12:48:14 PM PDT 24
Finished	May 30 12:48:15 PM PDT 24
Peak memory	194672 kb
Host	smart-4eca05e2-c7bd-454a-816a-d4ec7e48207f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804252471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs r_outstanding.1804252471
Directory	/workspace/12.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_errors.2378474556
Short name	T1248
Test name
Test status
Simulation time	168105827 ps
CPU time	1.65 seconds
Started	May 30 12:48:14 PM PDT 24
Finished	May 30 12:48:18 PM PDT 24
Peak memory	200304 kb
Host	smart-61e90de5-8ce2-40c7-80f1-5f9dc174db80
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378474556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2378474556
Directory	/workspace/12.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1573250624
Short name	T1315
Test name
Test status
Simulation time	18311765 ps
CPU time	0.66 seconds
Started	May 30 12:48:17 PM PDT 24
Finished	May 30 12:48:19 PM PDT 24
Peak memory	197904 kb
Host	smart-e89619de-808e-4bb9-8393-d743f370328b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573250624 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1573250624
Directory	/workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_rw.3966810113
Short name	T1251
Test name
Test status
Simulation time	14256012 ps
CPU time	0.59 seconds
Started	May 30 12:48:13 PM PDT 24
Finished	May 30 12:48:15 PM PDT 24
Peak memory	195596 kb
Host	smart-3cd67eef-3446-4c7e-a86b-8952a9d52a05
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966810113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3966810113
Directory	/workspace/13.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_intr_test.1702566864
Short name	T1196
Test name
Test status
Simulation time	25478663 ps
CPU time	0.56 seconds
Started	May 30 12:48:11 PM PDT 24
Finished	May 30 12:48:13 PM PDT 24
Peak memory	194516 kb
Host	smart-10269713-9bfa-4df2-b19e-fee80a788862
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702566864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1702566864
Directory	/workspace/13.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3799186698
Short name	T82
Test name
Test status
Simulation time	47355991 ps
CPU time	0.63 seconds
Started	May 30 12:48:14 PM PDT 24
Finished	May 30 12:48:16 PM PDT 24
Peak memory	194732 kb
Host	smart-4917b857-a88d-4005-b276-0c175b321611
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799186698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs r_outstanding.3799186698
Directory	/workspace/13.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_errors.487026750
Short name	T1268
Test name
Test status
Simulation time	72048191 ps
CPU time	1.3 seconds
Started	May 30 12:48:15 PM PDT 24
Finished	May 30 12:48:18 PM PDT 24
Peak memory	200180 kb
Host	smart-8438f94e-0812-4102-8b35-7a0d1346da01
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487026750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.487026750
Directory	/workspace/13.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2095802651
Short name	T100
Test name
Test status
Simulation time	979336387 ps
CPU time	1.26 seconds
Started	May 30 12:48:14 PM PDT 24
Finished	May 30 12:48:16 PM PDT 24
Peak memory	199468 kb
Host	smart-5e08fef9-a987-4cde-81ed-33fe4e1c4dbb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095802651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2095802651
Directory	/workspace/13.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3392025222
Short name	T1309
Test name
Test status
Simulation time	18011377 ps
CPU time	0.92 seconds
Started	May 30 12:48:16 PM PDT 24
Finished	May 30 12:48:19 PM PDT 24
Peak memory	200144 kb
Host	smart-8311b086-c23f-435a-9bc4-17205731b5cd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392025222 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3392025222
Directory	/workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_rw.3324159439
Short name	T80
Test name
Test status
Simulation time	18059448 ps
CPU time	0.61 seconds
Started	May 30 12:48:15 PM PDT 24
Finished	May 30 12:48:17 PM PDT 24
Peak memory	195668 kb
Host	smart-910257f6-d2fa-4bca-b492-97e6de0959ab
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324159439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3324159439
Directory	/workspace/14.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_intr_test.2275006177
Short name	T1201
Test name
Test status
Simulation time	111284933 ps
CPU time	0.57 seconds
Started	May 30 12:48:13 PM PDT 24
Finished	May 30 12:48:15 PM PDT 24
Peak memory	194572 kb
Host	smart-3233f4be-3adf-4e05-a044-d957611d0aad
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275006177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2275006177
Directory	/workspace/14.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1418170543
Short name	T1303
Test name
Test status
Simulation time	60354278 ps
CPU time	0.78 seconds
Started	May 30 12:48:13 PM PDT 24
Finished	May 30 12:48:15 PM PDT 24
Peak memory	196308 kb
Host	smart-dd0387f8-ed63-426a-8032-8f8eff6a8319
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418170543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs r_outstanding.1418170543
Directory	/workspace/14.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_errors.531941984
Short name	T1258
Test name
Test status
Simulation time	182663452 ps
CPU time	2.15 seconds
Started	May 30 12:48:13 PM PDT 24
Finished	May 30 12:48:17 PM PDT 24
Peak memory	200304 kb
Host	smart-2bd9da1e-96bb-4aad-b11c-75b794e672ac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531941984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.531941984
Directory	/workspace/14.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4160933951
Short name	T92
Test name
Test status
Simulation time	650514796 ps
CPU time	1.23 seconds
Started	May 30 12:48:11 PM PDT 24
Finished	May 30 12:48:13 PM PDT 24
Peak memory	199540 kb
Host	smart-f2a417b9-bff4-4901-9f34-d706aa805753
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160933951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4160933951
Directory	/workspace/14.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.375175233
Short name	T1205
Test name
Test status
Simulation time	52247561 ps
CPU time	0.81 seconds
Started	May 30 12:48:15 PM PDT 24
Finished	May 30 12:48:18 PM PDT 24
Peak memory	200012 kb
Host	smart-98456336-03d0-41fb-93e6-d714c424735b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375175233 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.375175233
Directory	/workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_rw.3855533454
Short name	T86
Test name
Test status
Simulation time	32377995 ps
CPU time	0.63 seconds
Started	May 30 12:48:15 PM PDT 24
Finished	May 30 12:48:17 PM PDT 24
Peak memory	195580 kb
Host	smart-1ea0c5a7-f5a7-49d7-b9f5-b2d75c726de7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855533454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3855533454
Directory	/workspace/15.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_intr_test.2121685391
Short name	T1237
Test name
Test status
Simulation time	68657426 ps
CPU time	0.57 seconds
Started	May 30 12:48:19 PM PDT 24
Finished	May 30 12:48:20 PM PDT 24
Peak memory	194620 kb
Host	smart-438c77f1-2cdb-4800-a86d-b08be9512186
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121685391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2121685391
Directory	/workspace/15.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2239921412
Short name	T84
Test name
Test status
Simulation time	16708688 ps
CPU time	0.71 seconds
Started	May 30 12:48:13 PM PDT 24
Finished	May 30 12:48:15 PM PDT 24
Peak memory	196240 kb
Host	smart-c648ae01-26e3-490a-bad0-805844d2628e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239921412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs r_outstanding.2239921412
Directory	/workspace/15.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_errors.2911958554
Short name	T1317
Test name
Test status
Simulation time	491357255 ps
CPU time	2.25 seconds
Started	May 30 12:48:15 PM PDT 24
Finished	May 30 12:48:19 PM PDT 24
Peak memory	200192 kb
Host	smart-a0f5a67c-2898-46b4-8b20-72edb70ce00c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911958554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2911958554
Directory	/workspace/15.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3683134545
Short name	T98
Test name
Test status
Simulation time	81869423 ps
CPU time	0.98 seconds
Started	May 30 12:48:19 PM PDT 24
Finished	May 30 12:48:21 PM PDT 24
Peak memory	198768 kb
Host	smart-a36e501a-007b-477b-98b8-379ac5e05784
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683134545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3683134545
Directory	/workspace/15.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.991207801
Short name	T1244
Test name
Test status
Simulation time	29415675 ps
CPU time	0.63 seconds
Started	May 30 12:48:15 PM PDT 24
Finished	May 30 12:48:18 PM PDT 24
Peak memory	197684 kb
Host	smart-2be06ee2-cec6-4c4d-9acd-732e5596d4e3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991207801 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.991207801
Directory	/workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_rw.626160234
Short name	T1242
Test name
Test status
Simulation time	15894927 ps
CPU time	0.61 seconds
Started	May 30 12:48:15 PM PDT 24
Finished	May 30 12:48:17 PM PDT 24
Peak memory	195596 kb
Host	smart-349272bc-d437-4cef-91f4-b0b0cc1b55dd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626160234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.626160234
Directory	/workspace/16.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_intr_test.3251547618
Short name	T1274
Test name
Test status
Simulation time	57833873 ps
CPU time	0.58 seconds
Started	May 30 12:48:14 PM PDT 24
Finished	May 30 12:48:16 PM PDT 24
Peak memory	194612 kb
Host	smart-c25360f5-a43c-4afa-aafa-7f8075c92d53
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251547618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3251547618
Directory	/workspace/16.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.796842331
Short name	T83
Test name
Test status
Simulation time	28429494 ps
CPU time	0.74 seconds
Started	May 30 12:48:15 PM PDT 24
Finished	May 30 12:48:18 PM PDT 24
Peak memory	197160 kb
Host	smart-a6d9494e-b4fe-44f2-9e47-3bb9ba530775
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796842331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr _outstanding.796842331
Directory	/workspace/16.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_errors.4006878087
Short name	T1295
Test name
Test status
Simulation time	116823523 ps
CPU time	2.53 seconds
Started	May 30 12:48:17 PM PDT 24
Finished	May 30 12:48:21 PM PDT 24
Peak memory	200164 kb
Host	smart-51fd3a68-bfa6-4bfa-848e-9bb53ad65c33
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006878087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.4006878087
Directory	/workspace/16.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.873108534
Short name	T1254
Test name
Test status
Simulation time	75945692 ps
CPU time	0.99 seconds
Started	May 30 12:48:14 PM PDT 24
Finished	May 30 12:48:16 PM PDT 24
Peak memory	199336 kb
Host	smart-c969a41a-c0ac-4f13-b190-123c7128ecd2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873108534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.873108534
Directory	/workspace/16.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1479936923
Short name	T1281
Test name
Test status
Simulation time	97594692 ps
CPU time	0.87 seconds
Started	May 30 12:48:26 PM PDT 24
Finished	May 30 12:48:27 PM PDT 24
Peak memory	200148 kb
Host	smart-48e2b50a-e4b9-443b-a460-4a255d2d76da
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479936923 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1479936923
Directory	/workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_rw.3938905922
Short name	T71
Test name
Test status
Simulation time	17054120 ps
CPU time	0.66 seconds
Started	May 30 12:48:27 PM PDT 24
Finished	May 30 12:48:29 PM PDT 24
Peak memory	195648 kb
Host	smart-188cf500-74b2-4c79-9e1c-1337bbb6c55f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938905922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3938905922
Directory	/workspace/17.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_intr_test.494439088
Short name	T1280
Test name
Test status
Simulation time	15915657 ps
CPU time	0.59 seconds
Started	May 30 12:48:14 PM PDT 24
Finished	May 30 12:48:16 PM PDT 24
Peak memory	194504 kb
Host	smart-da74fcdd-187d-4d5a-93de-200703eb98a3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494439088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.494439088
Directory	/workspace/17.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.831718835
Short name	T1282
Test name
Test status
Simulation time	28126533 ps
CPU time	0.74 seconds
Started	May 30 12:48:27 PM PDT 24
Finished	May 30 12:48:29 PM PDT 24
Peak memory	197128 kb
Host	smart-f73ef139-3600-400a-99e1-fc59bd6144fe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831718835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr _outstanding.831718835
Directory	/workspace/17.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_errors.1665327470
Short name	T1194
Test name
Test status
Simulation time	150191584 ps
CPU time	1.85 seconds
Started	May 30 12:48:17 PM PDT 24
Finished	May 30 12:48:21 PM PDT 24
Peak memory	200220 kb
Host	smart-ed1a524e-dbf7-4e75-a096-9124378301f4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665327470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1665327470
Directory	/workspace/17.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.760651345
Short name	T126
Test name
Test status
Simulation time	87253942 ps
CPU time	1.35 seconds
Started	May 30 12:48:14 PM PDT 24
Finished	May 30 12:48:17 PM PDT 24
Peak memory	199488 kb
Host	smart-7387bc04-fb17-4db6-a9d0-28e709c72983
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760651345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.760651345
Directory	/workspace/17.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2567130677
Short name	T1239
Test name
Test status
Simulation time	19238748 ps
CPU time	0.72 seconds
Started	May 30 12:48:28 PM PDT 24
Finished	May 30 12:48:30 PM PDT 24
Peak memory	197756 kb
Host	smart-08be5657-7ab3-4c8a-bc68-8cf3743359e8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567130677 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2567130677
Directory	/workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_rw.3444558462
Short name	T73
Test name
Test status
Simulation time	36787970 ps
CPU time	0.58 seconds
Started	May 30 12:48:26 PM PDT 24
Finished	May 30 12:48:27 PM PDT 24
Peak memory	195624 kb
Host	smart-016f61b3-8b92-41c9-8af2-f716a105821d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444558462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3444558462
Directory	/workspace/18.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_intr_test.3526864990
Short name	T1304
Test name
Test status
Simulation time	42383426 ps
CPU time	0.58 seconds
Started	May 30 12:48:30 PM PDT 24
Finished	May 30 12:48:32 PM PDT 24
Peak memory	194640 kb
Host	smart-acc33a03-30da-4855-9ddc-9afebdf18723
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526864990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3526864990
Directory	/workspace/18.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1764457247
Short name	T1219
Test name
Test status
Simulation time	105961106 ps
CPU time	0.7 seconds
Started	May 30 12:48:23 PM PDT 24
Finished	May 30 12:48:24 PM PDT 24
Peak memory	197040 kb
Host	smart-2e966dc3-edf4-43d8-ad7a-558ed053eef2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764457247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs r_outstanding.1764457247
Directory	/workspace/18.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_errors.84531104
Short name	T1236
Test name
Test status
Simulation time	294952901 ps
CPU time	1.29 seconds
Started	May 30 12:48:26 PM PDT 24
Finished	May 30 12:48:28 PM PDT 24
Peak memory	200276 kb
Host	smart-8ff64f74-aa09-4e31-b3fd-2eba02e09c41
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84531104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.84531104
Directory	/workspace/18.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.273710019
Short name	T1273
Test name
Test status
Simulation time	434564099 ps
CPU time	1.3 seconds
Started	May 30 12:48:32 PM PDT 24
Finished	May 30 12:48:35 PM PDT 24
Peak memory	199388 kb
Host	smart-7b547b2e-8ea0-4990-9b2c-4fb57e3663fb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273710019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.273710019
Directory	/workspace/18.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2575747317
Short name	T1220
Test name
Test status
Simulation time	108841523 ps
CPU time	1.42 seconds
Started	May 30 12:48:31 PM PDT 24
Finished	May 30 12:48:33 PM PDT 24
Peak memory	200180 kb
Host	smart-7bd527aa-71c4-4aae-91b7-974aef63ba52
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575747317 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2575747317
Directory	/workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_rw.843394833
Short name	T1224
Test name
Test status
Simulation time	12515235 ps
CPU time	0.59 seconds
Started	May 30 12:48:29 PM PDT 24
Finished	May 30 12:48:32 PM PDT 24
Peak memory	195640 kb
Host	smart-689a0f8e-cf7a-4219-83d3-70be5f60fa42
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843394833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.843394833
Directory	/workspace/19.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_intr_test.3917967378
Short name	T1191
Test name
Test status
Simulation time	13216457 ps
CPU time	0.56 seconds
Started	May 30 12:48:29 PM PDT 24
Finished	May 30 12:48:31 PM PDT 24
Peak memory	194648 kb
Host	smart-26c3bcdd-0641-45e5-bb35-077b228b7cd4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917967378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3917967378
Directory	/workspace/19.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1915446683
Short name	T1256
Test name
Test status
Simulation time	19157707 ps
CPU time	0.69 seconds
Started	May 30 12:48:26 PM PDT 24
Finished	May 30 12:48:28 PM PDT 24
Peak memory	196176 kb
Host	smart-d95856f6-d168-4c6d-a1cb-8764cc49b386
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915446683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs r_outstanding.1915446683
Directory	/workspace/19.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_errors.1490716346
Short name	T1287
Test name
Test status
Simulation time	65047099 ps
CPU time	1.42 seconds
Started	May 30 12:48:28 PM PDT 24
Finished	May 30 12:48:30 PM PDT 24
Peak memory	200172 kb
Host	smart-d12037cf-9b38-4797-80a0-cfd32e7c96d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490716346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1490716346
Directory	/workspace/19.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.4189990268
Short name	T99
Test name
Test status
Simulation time	276729458 ps
CPU time	1.35 seconds
Started	May 30 12:48:27 PM PDT 24
Finished	May 30 12:48:30 PM PDT 24
Peak memory	199516 kb
Host	smart-d60274af-46ab-4670-99e9-a4f82544bde5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189990268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.4189990268
Directory	/workspace/19.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.4173617876
Short name	T79
Test name
Test status
Simulation time	25593569 ps
CPU time	0.81 seconds
Started	May 30 12:48:10 PM PDT 24
Finished	May 30 12:48:12 PM PDT 24
Peak memory	196404 kb
Host	smart-c054d15d-0d1f-4658-b3cc-54d08ed6090d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173617876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.4173617876
Directory	/workspace/2.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2976450109
Short name	T1186
Test name
Test status
Simulation time	511253374 ps
CPU time	1.65 seconds
Started	May 30 12:48:01 PM PDT 24
Finished	May 30 12:48:04 PM PDT 24
Peak memory	198212 kb
Host	smart-c536e8eb-3c74-4402-a4d3-a3f1e9ef8cd1
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976450109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2976450109
Directory	/workspace/2.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.110113185
Short name	T1230
Test name
Test status
Simulation time	54907077 ps
CPU time	0.64 seconds
Started	May 30 12:48:02 PM PDT 24
Finished	May 30 12:48:04 PM PDT 24
Peak memory	195632 kb
Host	smart-e94ef165-bc91-48f1-a21c-b43674d8a8c1
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110113185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.110113185
Directory	/workspace/2.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2549278102
Short name	T1189
Test name
Test status
Simulation time	57458120 ps
CPU time	1.37 seconds
Started	May 30 12:48:10 PM PDT 24
Finished	May 30 12:48:12 PM PDT 24
Peak memory	200272 kb
Host	smart-89bb9877-eb27-4a04-aa60-d32a88bfafb3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549278102 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2549278102
Directory	/workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_rw.1320856281
Short name	T1312
Test name
Test status
Simulation time	10980791 ps
CPU time	0.59 seconds
Started	May 30 12:48:01 PM PDT 24
Finished	May 30 12:48:03 PM PDT 24
Peak memory	195632 kb
Host	smart-ba4a5c83-b0ca-45e9-a74e-ee213797a803
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320856281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1320856281
Directory	/workspace/2.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_intr_test.1016271692
Short name	T1255
Test name
Test status
Simulation time	44472895 ps
CPU time	0.54 seconds
Started	May 30 12:48:06 PM PDT 24
Finished	May 30 12:48:08 PM PDT 24
Peak memory	194592 kb
Host	smart-f7d0e337-ecb9-4712-801f-94a4261eb80c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016271692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1016271692
Directory	/workspace/2.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2934645747
Short name	T1210
Test name
Test status
Simulation time	56386521 ps
CPU time	0.61 seconds
Started	May 30 12:48:06 PM PDT 24
Finished	May 30 12:48:07 PM PDT 24
Peak memory	195848 kb
Host	smart-d4177141-5b26-4418-aa78-f837beae52cb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934645747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr _outstanding.2934645747
Directory	/workspace/2.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_errors.2522966825
Short name	T1253
Test name
Test status
Simulation time	36104320 ps
CPU time	0.93 seconds
Started	May 30 12:48:00 PM PDT 24
Finished	May 30 12:48:02 PM PDT 24
Peak memory	199720 kb
Host	smart-1f5352e8-bb98-4da5-bdc7-14c7baed38c2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522966825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2522966825
Directory	/workspace/2.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2711314712
Short name	T1271
Test name
Test status
Simulation time	555380762 ps
CPU time	0.86 seconds
Started	May 30 12:48:10 PM PDT 24
Finished	May 30 12:48:12 PM PDT 24
Peak memory	199220 kb
Host	smart-32a51c67-238a-4aa0-b314-3d77488c7828
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711314712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2711314712
Directory	/workspace/2.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.uart_intr_test.2069540938
Short name	T1305
Test name
Test status
Simulation time	144839548 ps
CPU time	0.62 seconds
Started	May 30 12:48:33 PM PDT 24
Finished	May 30 12:48:34 PM PDT 24
Peak memory	194604 kb
Host	smart-347baf21-b771-479d-baaa-8d5a2d2cd5fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069540938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2069540938
Directory	/workspace/20.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.uart_intr_test.3539827576
Short name	T1238
Test name
Test status
Simulation time	13605050 ps
CPU time	0.56 seconds
Started	May 30 12:48:28 PM PDT 24
Finished	May 30 12:48:30 PM PDT 24
Peak memory	194664 kb
Host	smart-db9604af-d0fb-4128-bcfc-5e226aba48fe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539827576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3539827576
Directory	/workspace/21.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.uart_intr_test.797559611
Short name	T1306
Test name
Test status
Simulation time	12335029 ps
CPU time	0.57 seconds
Started	May 30 12:48:27 PM PDT 24
Finished	May 30 12:48:28 PM PDT 24
Peak memory	194600 kb
Host	smart-a1b1bfda-d3bc-4192-bcec-44589021b54d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797559611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.797559611
Directory	/workspace/22.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.uart_intr_test.4040744021
Short name	T1223
Test name
Test status
Simulation time	16196631 ps
CPU time	0.58 seconds
Started	May 30 12:48:31 PM PDT 24
Finished	May 30 12:48:33 PM PDT 24
Peak memory	194476 kb
Host	smart-0dcfa4f4-7769-4fea-ace1-d7ec6f0c328f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040744021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.4040744021
Directory	/workspace/23.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.uart_intr_test.3298215700
Short name	T1216
Test name
Test status
Simulation time	46126417 ps
CPU time	0.61 seconds
Started	May 30 12:48:26 PM PDT 24
Finished	May 30 12:48:27 PM PDT 24
Peak memory	194500 kb
Host	smart-b98c3c4d-214e-4d4b-bd2e-8db2c95ae041
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298215700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3298215700
Directory	/workspace/24.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.uart_intr_test.1162988323
Short name	T1300
Test name
Test status
Simulation time	14729475 ps
CPU time	0.6 seconds
Started	May 30 12:48:29 PM PDT 24
Finished	May 30 12:48:31 PM PDT 24
Peak memory	194600 kb
Host	smart-1543151a-c530-46fc-a5ae-a13bf6a223c3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162988323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1162988323
Directory	/workspace/25.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.uart_intr_test.3708083982
Short name	T1200
Test name
Test status
Simulation time	26894036 ps
CPU time	0.61 seconds
Started	May 30 12:48:28 PM PDT 24
Finished	May 30 12:48:30 PM PDT 24
Peak memory	194564 kb
Host	smart-f9820e33-5528-4b72-ac73-f04996132c4a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708083982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3708083982
Directory	/workspace/26.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.uart_intr_test.815921439
Short name	T1289
Test name
Test status
Simulation time	27034733 ps
CPU time	0.63 seconds
Started	May 30 12:48:30 PM PDT 24
Finished	May 30 12:48:32 PM PDT 24
Peak memory	194500 kb
Host	smart-5c62b55e-1c7a-4876-a1eb-600758cd41bc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815921439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.815921439
Directory	/workspace/27.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.uart_intr_test.1546705179
Short name	T1294
Test name
Test status
Simulation time	34680162 ps
CPU time	0.6 seconds
Started	May 30 12:48:26 PM PDT 24
Finished	May 30 12:48:28 PM PDT 24
Peak memory	194416 kb
Host	smart-1a32794b-eb9c-4efd-96db-686e409dee50
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546705179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1546705179
Directory	/workspace/28.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.uart_intr_test.491665929
Short name	T1284
Test name
Test status
Simulation time	12846202 ps
CPU time	0.57 seconds
Started	May 30 12:48:30 PM PDT 24
Finished	May 30 12:48:32 PM PDT 24
Peak memory	194536 kb
Host	smart-6853194e-348c-43d3-8c08-af4a01e9a48e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491665929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.491665929
Directory	/workspace/29.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1478927195
Short name	T72
Test name
Test status
Simulation time	40613479 ps
CPU time	0.63 seconds
Started	May 30 12:48:04 PM PDT 24
Finished	May 30 12:48:06 PM PDT 24
Peak memory	195176 kb
Host	smart-4fe5cfd9-c5ab-401a-a922-cca22d58143d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478927195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1478927195
Directory	/workspace/3.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1848940172
Short name	T1263
Test name
Test status
Simulation time	176959034 ps
CPU time	2.4 seconds
Started	May 30 12:48:03 PM PDT 24
Finished	May 30 12:48:07 PM PDT 24
Peak memory	197900 kb
Host	smart-4ea034b0-2884-43f6-ac72-ad1f7757f073
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848940172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1848940172
Directory	/workspace/3.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1751360626
Short name	T1221
Test name
Test status
Simulation time	12591406 ps
CPU time	0.58 seconds
Started	May 30 12:48:04 PM PDT 24
Finished	May 30 12:48:05 PM PDT 24
Peak memory	195648 kb
Host	smart-4abf5aa5-b8cb-43e2-b6ca-579381c69648
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751360626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1751360626
Directory	/workspace/3.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.35461127
Short name	T1266
Test name
Test status
Simulation time	21974053 ps
CPU time	0.72 seconds
Started	May 30 12:48:01 PM PDT 24
Finished	May 30 12:48:03 PM PDT 24
Peak memory	198672 kb
Host	smart-5dbfd9df-5348-41b8-8aa3-2cf8366b2cc6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35461127 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.35461127
Directory	/workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_rw.2200103940
Short name	T75
Test name
Test status
Simulation time	67420603 ps
CPU time	0.61 seconds
Started	May 30 12:48:05 PM PDT 24
Finished	May 30 12:48:06 PM PDT 24
Peak memory	195740 kb
Host	smart-149e471e-fdd9-4607-b999-19474b1e4969
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200103940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2200103940
Directory	/workspace/3.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_intr_test.2907732831
Short name	T1203
Test name
Test status
Simulation time	17230561 ps
CPU time	0.59 seconds
Started	May 30 12:48:03 PM PDT 24
Finished	May 30 12:48:05 PM PDT 24
Peak memory	194604 kb
Host	smart-3729a373-cd43-48c9-b3dc-4f1f0be25cbc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907732831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2907732831
Directory	/workspace/3.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2281492773
Short name	T1222
Test name
Test status
Simulation time	17814351 ps
CPU time	0.77 seconds
Started	May 30 12:48:06 PM PDT 24
Finished	May 30 12:48:07 PM PDT 24
Peak memory	197940 kb
Host	smart-69cae752-9a3e-4d9b-8241-0dd9591b0043
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281492773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr _outstanding.2281492773
Directory	/workspace/3.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_errors.1697392938
Short name	T1229
Test name
Test status
Simulation time	109544876 ps
CPU time	1.44 seconds
Started	May 30 12:48:00 PM PDT 24
Finished	May 30 12:48:03 PM PDT 24
Peak memory	200196 kb
Host	smart-9f04d008-f6d1-4cb0-9553-a55326e55d74
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697392938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1697392938
Directory	/workspace/3.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.208503201
Short name	T1243
Test name
Test status
Simulation time	141110916 ps
CPU time	0.93 seconds
Started	May 30 12:48:04 PM PDT 24
Finished	May 30 12:48:06 PM PDT 24
Peak memory	199272 kb
Host	smart-1753e2c1-86c4-426c-a684-3d353fc5111d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208503201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.208503201
Directory	/workspace/3.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.uart_intr_test.3148911268
Short name	T1231
Test name
Test status
Simulation time	13114001 ps
CPU time	0.63 seconds
Started	May 30 12:48:30 PM PDT 24
Finished	May 30 12:48:32 PM PDT 24
Peak memory	194496 kb
Host	smart-4912ee0c-86a1-43e8-b5d7-d1d2c135dafd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148911268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3148911268
Directory	/workspace/30.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.uart_intr_test.1147877120
Short name	T1311
Test name
Test status
Simulation time	12949722 ps
CPU time	0.58 seconds
Started	May 30 12:48:27 PM PDT 24
Finished	May 30 12:48:29 PM PDT 24
Peak memory	194520 kb
Host	smart-2cb58b9b-cb8d-4805-8372-1e4db3471210
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147877120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1147877120
Directory	/workspace/31.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.uart_intr_test.1012481145
Short name	T1307
Test name
Test status
Simulation time	10372145 ps
CPU time	0.56 seconds
Started	May 30 12:48:30 PM PDT 24
Finished	May 30 12:48:32 PM PDT 24
Peak memory	194572 kb
Host	smart-e9b57342-8325-4353-857e-cf3614bb2b25
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012481145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1012481145
Directory	/workspace/32.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.uart_intr_test.1184877586
Short name	T1195
Test name
Test status
Simulation time	13928338 ps
CPU time	0.63 seconds
Started	May 30 12:48:27 PM PDT 24
Finished	May 30 12:48:28 PM PDT 24
Peak memory	194588 kb
Host	smart-bd71f5a2-702a-480e-85f0-40c24d1ddeba
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184877586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1184877586
Directory	/workspace/33.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.uart_intr_test.31454889
Short name	T1276
Test name
Test status
Simulation time	49213420 ps
CPU time	0.55 seconds
Started	May 30 12:48:28 PM PDT 24
Finished	May 30 12:48:30 PM PDT 24
Peak memory	194596 kb
Host	smart-504da5ec-e919-4f55-803f-8aa278d73c05
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31454889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.31454889
Directory	/workspace/34.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.uart_intr_test.3723230028
Short name	T1232
Test name
Test status
Simulation time	15098714 ps
CPU time	0.56 seconds
Started	May 30 12:48:29 PM PDT 24
Finished	May 30 12:48:31 PM PDT 24
Peak memory	194600 kb
Host	smart-ccc7dca1-cdb1-480a-9137-f5603191e239
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723230028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3723230028
Directory	/workspace/35.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.uart_intr_test.3597387626
Short name	T1257
Test name
Test status
Simulation time	18731247 ps
CPU time	0.63 seconds
Started	May 30 12:48:26 PM PDT 24
Finished	May 30 12:48:28 PM PDT 24
Peak memory	194372 kb
Host	smart-ad54616a-2c80-422e-833c-f89efe93e317
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597387626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3597387626
Directory	/workspace/36.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.uart_intr_test.1275108767
Short name	T1246
Test name
Test status
Simulation time	17521783 ps
CPU time	0.6 seconds
Started	May 30 12:48:27 PM PDT 24
Finished	May 30 12:48:29 PM PDT 24
Peak memory	194608 kb
Host	smart-5f46e042-077a-4196-9192-dd2e5c348f83
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275108767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1275108767
Directory	/workspace/37.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.uart_intr_test.1640664042
Short name	T1225
Test name
Test status
Simulation time	36607074 ps
CPU time	0.61 seconds
Started	May 30 12:48:30 PM PDT 24
Finished	May 30 12:48:32 PM PDT 24
Peak memory	194576 kb
Host	smart-60704f87-c53d-4f4f-8464-2e8ea1676a2b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640664042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1640664042
Directory	/workspace/38.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.uart_intr_test.3965533941
Short name	T1217
Test name
Test status
Simulation time	64966004 ps
CPU time	0.59 seconds
Started	May 30 12:48:31 PM PDT 24
Finished	May 30 12:48:33 PM PDT 24
Peak memory	194496 kb
Host	smart-d7a21605-f47e-44a5-90a3-fb30a67e0231
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965533941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3965533941
Directory	/workspace/39.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2105331473
Short name	T1264
Test name
Test status
Simulation time	73551340 ps
CPU time	0.66 seconds
Started	May 30 12:48:04 PM PDT 24
Finished	May 30 12:48:06 PM PDT 24
Peak memory	195020 kb
Host	smart-8e78319a-91b9-4980-ab1b-904a7f503a1f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105331473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2105331473
Directory	/workspace/4.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.950996871
Short name	T1228
Test name
Test status
Simulation time	89720896 ps
CPU time	1.57 seconds
Started	May 30 12:48:02 PM PDT 24
Finished	May 30 12:48:05 PM PDT 24
Peak memory	198084 kb
Host	smart-6699c650-1cc8-4c06-b9ff-df06aa79edde
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950996871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.950996871
Directory	/workspace/4.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2426715903
Short name	T1252
Test name
Test status
Simulation time	23656533 ps
CPU time	0.58 seconds
Started	May 30 12:48:04 PM PDT 24
Finished	May 30 12:48:05 PM PDT 24
Peak memory	195544 kb
Host	smart-a5ffd949-ade3-41e5-8674-2c6fac95eb18
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426715903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2426715903
Directory	/workspace/4.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3216348206
Short name	T1302
Test name
Test status
Simulation time	98395916 ps
CPU time	0.79 seconds
Started	May 30 12:48:04 PM PDT 24
Finished	May 30 12:48:06 PM PDT 24
Peak memory	199804 kb
Host	smart-06f0aada-b0fb-46b9-9ca4-40b65ecc4e3d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216348206 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3216348206
Directory	/workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_rw.1309714981
Short name	T88
Test name
Test status
Simulation time	56302973 ps
CPU time	0.62 seconds
Started	May 30 12:48:06 PM PDT 24
Finished	May 30 12:48:07 PM PDT 24
Peak memory	195748 kb
Host	smart-9bb6e7df-4758-4332-8c7f-4f1428a64228
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309714981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1309714981
Directory	/workspace/4.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_intr_test.2961164734
Short name	T1316
Test name
Test status
Simulation time	12749673 ps
CPU time	0.56 seconds
Started	May 30 12:48:04 PM PDT 24
Finished	May 30 12:48:06 PM PDT 24
Peak memory	194596 kb
Host	smart-1d76b259-5d77-466c-aace-82ac72bdde14
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961164734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2961164734
Directory	/workspace/4.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.174728495
Short name	T1218
Test name
Test status
Simulation time	85521798 ps
CPU time	0.73 seconds
Started	May 30 12:48:04 PM PDT 24
Finished	May 30 12:48:06 PM PDT 24
Peak memory	196272 kb
Host	smart-046fa243-4046-4094-bdb9-56cba41dbac7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174728495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_ outstanding.174728495
Directory	/workspace/4.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_errors.139583938
Short name	T1292
Test name
Test status
Simulation time	150764741 ps
CPU time	1.31 seconds
Started	May 30 12:48:04 PM PDT 24
Finished	May 30 12:48:06 PM PDT 24
Peak memory	200212 kb
Host	smart-e0263353-b589-46e2-8b6a-8f65b22545bd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139583938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.139583938
Directory	/workspace/4.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1874337263
Short name	T1267
Test name
Test status
Simulation time	1125992838 ps
CPU time	1.32 seconds
Started	May 30 12:48:00 PM PDT 24
Finished	May 30 12:48:03 PM PDT 24
Peak memory	199396 kb
Host	smart-6e21af4d-0886-4ffa-bf9b-8f4c26f2bb54
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874337263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1874337263
Directory	/workspace/4.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.uart_intr_test.204103396
Short name	T1308
Test name
Test status
Simulation time	41963925 ps
CPU time	0.56 seconds
Started	May 30 12:48:31 PM PDT 24
Finished	May 30 12:48:33 PM PDT 24
Peak memory	194476 kb
Host	smart-c6e69a6b-0e10-4c01-b466-cd2f75b02795
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204103396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.204103396
Directory	/workspace/40.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.uart_intr_test.1892932505
Short name	T1269
Test name
Test status
Simulation time	33080239 ps
CPU time	0.57 seconds
Started	May 30 12:48:32 PM PDT 24
Finished	May 30 12:48:34 PM PDT 24
Peak memory	194548 kb
Host	smart-cdcdba0f-dab7-4baa-836c-bf8deaf44860
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892932505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1892932505
Directory	/workspace/41.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.uart_intr_test.2639443194
Short name	T1202
Test name
Test status
Simulation time	54366133 ps
CPU time	0.59 seconds
Started	May 30 12:48:28 PM PDT 24
Finished	May 30 12:48:30 PM PDT 24
Peak memory	194604 kb
Host	smart-b49f93e1-cb6e-4ec9-bca8-047bb2be2a6a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639443194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2639443194
Directory	/workspace/42.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.uart_intr_test.2773458963
Short name	T1278
Test name
Test status
Simulation time	12545547 ps
CPU time	0.56 seconds
Started	May 30 12:48:31 PM PDT 24
Finished	May 30 12:48:33 PM PDT 24
Peak memory	194624 kb
Host	smart-5fb72f4d-ab2a-4f5c-ab2a-2b06f944c29b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773458963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2773458963
Directory	/workspace/43.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.uart_intr_test.3974120978
Short name	T1301
Test name
Test status
Simulation time	25724033 ps
CPU time	0.62 seconds
Started	May 30 12:48:27 PM PDT 24
Finished	May 30 12:48:29 PM PDT 24
Peak memory	194520 kb
Host	smart-0341a790-7ac7-4b89-8ed3-c0da3d03d2a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974120978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3974120978
Directory	/workspace/44.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.uart_intr_test.3194718780
Short name	T1187
Test name
Test status
Simulation time	44064821 ps
CPU time	0.57 seconds
Started	May 30 12:48:30 PM PDT 24
Finished	May 30 12:48:32 PM PDT 24
Peak memory	194560 kb
Host	smart-7cbda1bf-555a-44ae-b6f9-c72bcf55d9a1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194718780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3194718780
Directory	/workspace/45.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.uart_intr_test.4215482658
Short name	T1215
Test name
Test status
Simulation time	15906794 ps
CPU time	0.59 seconds
Started	May 30 12:48:31 PM PDT 24
Finished	May 30 12:48:33 PM PDT 24
Peak memory	194492 kb
Host	smart-0253b0ea-d180-477c-8f35-7638770d4443
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215482658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.4215482658
Directory	/workspace/46.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.uart_intr_test.3960240285
Short name	T1206
Test name
Test status
Simulation time	25007499 ps
CPU time	0.58 seconds
Started	May 30 12:48:29 PM PDT 24
Finished	May 30 12:48:31 PM PDT 24
Peak memory	194592 kb
Host	smart-3e280d7a-2aae-4c72-b906-0c389c65ff42
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960240285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3960240285
Directory	/workspace/47.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.uart_intr_test.2354693615
Short name	T1233
Test name
Test status
Simulation time	14164019 ps
CPU time	0.59 seconds
Started	May 30 12:48:27 PM PDT 24
Finished	May 30 12:48:29 PM PDT 24
Peak memory	194580 kb
Host	smart-3e2f7aaa-bb4a-4398-ab2d-677c8a2edb95
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354693615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2354693615
Directory	/workspace/48.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.uart_intr_test.1071614033
Short name	T1185
Test name
Test status
Simulation time	42330681 ps
CPU time	0.59 seconds
Started	May 30 12:48:27 PM PDT 24
Finished	May 30 12:48:29 PM PDT 24
Peak memory	194584 kb
Host	smart-d398b8b1-d562-46f3-b031-f4ae4472ef05
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071614033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1071614033
Directory	/workspace/49.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3491532109
Short name	T1288
Test name
Test status
Simulation time	63727944 ps
CPU time	0.74 seconds
Started	May 30 12:48:12 PM PDT 24
Finished	May 30 12:48:14 PM PDT 24
Peak memory	199076 kb
Host	smart-cb41eb35-ffae-4124-a254-de0cbb20150b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491532109 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3491532109
Directory	/workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_rw.963698678
Short name	T70
Test name
Test status
Simulation time	27368544 ps
CPU time	0.6 seconds
Started	May 30 12:48:12 PM PDT 24
Finished	May 30 12:48:14 PM PDT 24
Peak memory	196020 kb
Host	smart-dca8e636-aa34-41c5-89dc-e8c57802f301
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963698678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.963698678
Directory	/workspace/5.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_intr_test.74808515
Short name	T1204
Test name
Test status
Simulation time	31307149 ps
CPU time	0.64 seconds
Started	May 30 12:48:00 PM PDT 24
Finished	May 30 12:48:02 PM PDT 24
Peak memory	194620 kb
Host	smart-f60e5e68-6f93-47c3-9262-d6df4ed057e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74808515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.74808515
Directory	/workspace/5.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.318435679
Short name	T1296
Test name
Test status
Simulation time	105464002 ps
CPU time	0.76 seconds
Started	May 30 12:48:00 PM PDT 24
Finished	May 30 12:48:02 PM PDT 24
Peak memory	196732 kb
Host	smart-128d6774-194c-4210-90e3-7fcecf623235
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318435679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_ outstanding.318435679
Directory	/workspace/5.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_errors.588214374
Short name	T1297
Test name
Test status
Simulation time	103863682 ps
CPU time	2.14 seconds
Started	May 30 12:48:05 PM PDT 24
Finished	May 30 12:48:08 PM PDT 24
Peak memory	200324 kb
Host	smart-99a8700b-6050-4a91-9b24-3d50b3a710e3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588214374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.588214374
Directory	/workspace/5.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.736942361
Short name	T1285
Test name
Test status
Simulation time	84910272 ps
CPU time	1.32 seconds
Started	May 30 12:48:12 PM PDT 24
Finished	May 30 12:48:14 PM PDT 24
Peak memory	199524 kb
Host	smart-41d340de-4c3d-48d2-b8d8-ab25d3878fe4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736942361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.736942361
Directory	/workspace/5.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.533788709
Short name	T1226
Test name
Test status
Simulation time	24554828 ps
CPU time	0.84 seconds
Started	May 30 12:48:00 PM PDT 24
Finished	May 30 12:48:02 PM PDT 24
Peak memory	198740 kb
Host	smart-fd65308c-8d4a-49d9-a7a9-a6f3e511de75
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533788709 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.533788709
Directory	/workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_rw.2218008571
Short name	T1250
Test name
Test status
Simulation time	11099112 ps
CPU time	0.6 seconds
Started	May 30 12:48:03 PM PDT 24
Finished	May 30 12:48:04 PM PDT 24
Peak memory	195656 kb
Host	smart-a10c88e7-b33a-46fc-b7cb-d5e7f509afc0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218008571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2218008571
Directory	/workspace/6.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_intr_test.1192060980
Short name	T1275
Test name
Test status
Simulation time	21264386 ps
CPU time	0.56 seconds
Started	May 30 12:48:11 PM PDT 24
Finished	May 30 12:48:13 PM PDT 24
Peak memory	194476 kb
Host	smart-d5c11ed1-0ca3-43cb-9092-e8c5c8386128
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192060980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1192060980
Directory	/workspace/6.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2713043826
Short name	T1270
Test name
Test status
Simulation time	105549848 ps
CPU time	0.77 seconds
Started	May 30 12:48:15 PM PDT 24
Finished	May 30 12:48:18 PM PDT 24
Peak memory	197288 kb
Host	smart-bcc0a9aa-2382-40af-9095-2cae5423951f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713043826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr _outstanding.2713043826
Directory	/workspace/6.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_errors.1026961555
Short name	T1211
Test name
Test status
Simulation time	83307831 ps
CPU time	1.3 seconds
Started	May 30 12:48:11 PM PDT 24
Finished	May 30 12:48:14 PM PDT 24
Peak memory	200100 kb
Host	smart-37d89242-087f-497b-bbf1-810371032e58
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026961555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1026961555
Directory	/workspace/6.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.247656363
Short name	T127
Test name
Test status
Simulation time	142727963 ps
CPU time	0.9 seconds
Started	May 30 12:48:11 PM PDT 24
Finished	May 30 12:48:14 PM PDT 24
Peak memory	199000 kb
Host	smart-9e9e88a9-d4b9-4b9e-811d-c9112d15fd00
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247656363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.247656363
Directory	/workspace/6.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2423498187
Short name	T1197
Test name
Test status
Simulation time	66232691 ps
CPU time	1.04 seconds
Started	May 30 12:47:58 PM PDT 24
Finished	May 30 12:48:00 PM PDT 24
Peak memory	200092 kb
Host	smart-ec299127-8931-46b8-9ee3-a04a575b215e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423498187 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2423498187
Directory	/workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_rw.4133205568
Short name	T1314
Test name
Test status
Simulation time	40226288 ps
CPU time	0.61 seconds
Started	May 30 12:47:59 PM PDT 24
Finished	May 30 12:48:01 PM PDT 24
Peak memory	195692 kb
Host	smart-f818ee6d-d07b-4b71-92d1-e4fabec88b15
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133205568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4133205568
Directory	/workspace/7.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_intr_test.2179588141
Short name	T1199
Test name
Test status
Simulation time	18116327 ps
CPU time	0.55 seconds
Started	May 30 12:48:00 PM PDT 24
Finished	May 30 12:48:02 PM PDT 24
Peak memory	194496 kb
Host	smart-e237b188-c84a-45f4-8b9f-56d0a1279263
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179588141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2179588141
Directory	/workspace/7.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1062873263
Short name	T1213
Test name
Test status
Simulation time	23373042 ps
CPU time	0.68 seconds
Started	May 30 12:48:02 PM PDT 24
Finished	May 30 12:48:03 PM PDT 24
Peak memory	195884 kb
Host	smart-22eb53bf-2998-409f-91ea-05b9bc9167ca
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062873263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr _outstanding.1062873263
Directory	/workspace/7.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_errors.3320192749
Short name	T1209
Test name
Test status
Simulation time	85285251 ps
CPU time	0.95 seconds
Started	May 30 12:48:00 PM PDT 24
Finished	May 30 12:48:01 PM PDT 24
Peak memory	199996 kb
Host	smart-183aea36-b5dd-429d-929c-0d71353de954
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320192749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3320192749
Directory	/workspace/7.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.193897005
Short name	T97
Test name
Test status
Simulation time	315019839 ps
CPU time	1.28 seconds
Started	May 30 12:47:59 PM PDT 24
Finished	May 30 12:48:01 PM PDT 24
Peak memory	199596 kb
Host	smart-d942cfec-c128-4743-b255-b8fd090acd92
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193897005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.193897005
Directory	/workspace/7.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3405022571
Short name	T1235
Test name
Test status
Simulation time	120344749 ps
CPU time	0.87 seconds
Started	May 30 12:48:01 PM PDT 24
Finished	May 30 12:48:03 PM PDT 24
Peak memory	200104 kb
Host	smart-b5e743a0-1017-484a-93d9-8420e572adfc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405022571 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3405022571
Directory	/workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_rw.897505642
Short name	T1240
Test name
Test status
Simulation time	23509889 ps
CPU time	0.66 seconds
Started	May 30 12:48:03 PM PDT 24
Finished	May 30 12:48:04 PM PDT 24
Peak memory	195728 kb
Host	smart-d333a569-f087-45d8-8795-9711be7f4a4c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897505642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.897505642
Directory	/workspace/8.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_intr_test.2659473804
Short name	T1310
Test name
Test status
Simulation time	113113884 ps
CPU time	0.55 seconds
Started	May 30 12:48:10 PM PDT 24
Finished	May 30 12:48:11 PM PDT 24
Peak memory	194652 kb
Host	smart-155f14dd-c557-4758-84bb-72aefdda1029
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659473804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2659473804
Directory	/workspace/8.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4005565177
Short name	T1283
Test name
Test status
Simulation time	49537846 ps
CPU time	0.64 seconds
Started	May 30 12:47:58 PM PDT 24
Finished	May 30 12:48:00 PM PDT 24
Peak memory	196896 kb
Host	smart-6265de5f-70db-4575-93af-3f0407639edb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005565177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr _outstanding.4005565177
Directory	/workspace/8.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_errors.1534226219
Short name	T1262
Test name
Test status
Simulation time	110213540 ps
CPU time	2.28 seconds
Started	May 30 12:48:00 PM PDT 24
Finished	May 30 12:48:04 PM PDT 24
Peak memory	200140 kb
Host	smart-e75febaa-a10e-4c2e-9c35-52b289949a98
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534226219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1534226219
Directory	/workspace/8.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.239909687
Short name	T95
Test name
Test status
Simulation time	293177186 ps
CPU time	1.34 seconds
Started	May 30 12:48:01 PM PDT 24
Finished	May 30 12:48:03 PM PDT 24
Peak memory	199456 kb
Host	smart-cb095424-5e49-4932-af34-3f0b314a2551
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239909687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.239909687
Directory	/workspace/8.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3124803224
Short name	T1207
Test name
Test status
Simulation time	59615513 ps
CPU time	0.91 seconds
Started	May 30 12:48:01 PM PDT 24
Finished	May 30 12:48:03 PM PDT 24
Peak memory	200080 kb
Host	smart-121316dc-0aca-44c2-b4a3-78d09afc841e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124803224 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3124803224
Directory	/workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_rw.769531032
Short name	T1313
Test name
Test status
Simulation time	66546599 ps
CPU time	0.61 seconds
Started	May 30 12:48:01 PM PDT 24
Finished	May 30 12:48:03 PM PDT 24
Peak memory	195620 kb
Host	smart-108d9411-dcad-4137-9464-92a4e035a4f4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769531032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.769531032
Directory	/workspace/9.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_intr_test.3461281044
Short name	T1212
Test name
Test status
Simulation time	12695573 ps
CPU time	0.63 seconds
Started	May 30 12:48:02 PM PDT 24
Finished	May 30 12:48:04 PM PDT 24
Peak memory	194448 kb
Host	smart-d126cac2-4346-404a-aaf2-d10baf7f54cd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461281044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3461281044
Directory	/workspace/9.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1517570206
Short name	T1241
Test name
Test status
Simulation time	39272449 ps
CPU time	0.69 seconds
Started	May 30 12:48:01 PM PDT 24
Finished	May 30 12:48:03 PM PDT 24
Peak memory	195840 kb
Host	smart-0ff18e05-8dc4-477f-b940-02bdce84da4a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517570206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.1517570206
Directory	/workspace/9.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_errors.1274150953
Short name	T1208
Test name
Test status
Simulation time	111551714 ps
CPU time	1.4 seconds
Started	May 30 12:48:01 PM PDT 24
Finished	May 30 12:48:03 PM PDT 24
Peak memory	200212 kb
Host	smart-81e1d134-230f-4d03-9a13-87eb1a00d30f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274150953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1274150953
Directory	/workspace/9.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3587746450
Short name	T128
Test name
Test status
Simulation time	89661273 ps
CPU time	0.93 seconds
Started	May 30 12:47:59 PM PDT 24
Finished	May 30 12:48:00 PM PDT 24
Peak memory	199248 kb
Host	smart-5e5d7575-3dfd-4899-8b4c-f4876c68874d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587746450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3587746450
Directory	/workspace/9.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/0.uart_alert_test.2227583095
Short name	T1101
Test name
Test status
Simulation time	42378870 ps
CPU time	0.55 seconds
Started	May 30 12:50:08 PM PDT 24
Finished	May 30 12:50:11 PM PDT 24
Peak memory	194908 kb
Host	smart-dc4a5c31-5502-42bf-9cf9-606788e755ae
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227583095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2227583095
Directory	/workspace/0.uart_alert_test/latest

Test location	/workspace/coverage/default/0.uart_fifo_full.2665584748
Short name	T914
Test name
Test status
Simulation time	34892390471 ps
CPU time	57.18 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:51:10 PM PDT 24
Peak memory	200376 kb
Host	smart-baf4130a-a64f-46c0-9f34-981abb289aa5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2665584748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2665584748
Directory	/workspace/0.uart_fifo_full/latest

Test location	/workspace/coverage/default/0.uart_fifo_overflow.1055507246
Short name	T1065
Test name
Test status
Simulation time	74958452365 ps
CPU time	105.2 seconds
Started	May 30 12:50:08 PM PDT 24
Finished	May 30 12:51:55 PM PDT 24
Peak memory	200308 kb
Host	smart-9e5d9d70-1f3a-4f2d-9d4d-8e58bbdc20b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1055507246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1055507246
Directory	/workspace/0.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/0.uart_intr.1795556821
Short name	T737
Test name
Test status
Simulation time	13730043000 ps
CPU time	8.72 seconds
Started	May 30 12:50:09 PM PDT 24
Finished	May 30 12:50:20 PM PDT 24
Peak memory	200364 kb
Host	smart-2a033ff2-50e6-40e2-880c-a9ff66b567d6
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795556821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1795556821
Directory	/workspace/0.uart_intr/latest

Test location	/workspace/coverage/default/0.uart_long_xfer_wo_dly.1161863085
Short name	T371
Test name
Test status
Simulation time	119173722165 ps
CPU time	368.39 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:56:21 PM PDT 24
Peak memory	200012 kb
Host	smart-9c9b9efe-3c57-4416-a797-a0aebb88a9f8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1161863085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1161863085
Directory	/workspace/0.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/0.uart_loopback.1863237256
Short name	T862
Test name
Test status
Simulation time	3368207845 ps
CPU time	6.42 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:50:19 PM PDT 24
Peak memory	199448 kb
Host	smart-09ec207d-8372-4098-bdc7-9342d0369059
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1863237256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1863237256
Directory	/workspace/0.uart_loopback/latest

Test location	/workspace/coverage/default/0.uart_noise_filter.3644748531
Short name	T642
Test name
Test status
Simulation time	133052251602 ps
CPU time	110.66 seconds
Started	May 30 12:50:12 PM PDT 24
Finished	May 30 12:52:05 PM PDT 24
Peak memory	199536 kb
Host	smart-ff476b9b-c9ac-43f8-8c80-6506ae06f59e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3644748531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3644748531
Directory	/workspace/0.uart_noise_filter/latest

Test location	/workspace/coverage/default/0.uart_perf.4175975938
Short name	T466
Test name
Test status
Simulation time	10996384716 ps
CPU time	530.48 seconds
Started	May 30 12:50:09 PM PDT 24
Finished	May 30 12:59:01 PM PDT 24
Peak memory	200356 kb
Host	smart-7c07f21c-6680-4029-8584-3c2fedd34f56
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4175975938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.4175975938
Directory	/workspace/0.uart_perf/latest

Test location	/workspace/coverage/default/0.uart_rx_oversample.2214565887
Short name	T880
Test name
Test status
Simulation time	3062521758 ps
CPU time	5.97 seconds
Started	May 30 12:50:08 PM PDT 24
Finished	May 30 12:50:16 PM PDT 24
Peak memory	198376 kb
Host	smart-4deff3ef-be53-486a-b9ce-917d149a22df
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2214565887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2214565887
Directory	/workspace/0.uart_rx_oversample/latest

Test location	/workspace/coverage/default/0.uart_rx_parity_err.2986895463
Short name	T844
Test name
Test status
Simulation time	16497123864 ps
CPU time	7.5 seconds
Started	May 30 12:50:08 PM PDT 24
Finished	May 30 12:50:18 PM PDT 24
Peak memory	199112 kb
Host	smart-b0048b52-a6df-4b0e-8e15-a476864331a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986895463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2986895463
Directory	/workspace/0.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/0.uart_rx_start_bit_filter.2390915132
Short name	T421
Test name
Test status
Simulation time	6044132475 ps
CPU time	2.81 seconds
Started	May 30 12:50:09 PM PDT 24
Finished	May 30 12:50:13 PM PDT 24
Peak memory	196632 kb
Host	smart-4320dd5b-ae2d-4d13-8241-8fc10817bb5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2390915132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2390915132
Directory	/workspace/0.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/0.uart_sec_cm.3796714821
Short name	T102
Test name
Test status
Simulation time	50299658 ps
CPU time	0.78 seconds
Started	May 30 12:50:06 PM PDT 24
Finished	May 30 12:50:08 PM PDT 24
Peak memory	218584 kb
Host	smart-452d8b89-2f11-4e4b-b777-57e6594f4d16
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796714821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3796714821
Directory	/workspace/0.uart_sec_cm/latest

Test location	/workspace/coverage/default/0.uart_smoke.2522680200
Short name	T362
Test name
Test status
Simulation time	6326878592 ps
CPU time	9.12 seconds
Started	May 30 12:50:15 PM PDT 24
Finished	May 30 12:50:25 PM PDT 24
Peak memory	200228 kb
Host	smart-310f892b-1fed-493f-a977-5d97c2428758
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2522680200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2522680200
Directory	/workspace/0.uart_smoke/latest

Test location	/workspace/coverage/default/0.uart_stress_all.3792537425
Short name	T1045
Test name
Test status
Simulation time	127213530199 ps
CPU time	212.44 seconds
Started	May 30 12:50:15 PM PDT 24
Finished	May 30 12:53:48 PM PDT 24
Peak memory	200328 kb
Host	smart-0fae6ee8-51bf-4feb-bb9d-20f2f5899c82
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792537425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3792537425
Directory	/workspace/0.uart_stress_all/latest

Test location	/workspace/coverage/default/0.uart_stress_all_with_rand_reset.2802287990
Short name	T575
Test name
Test status
Simulation time	31738493589 ps
CPU time	274.16 seconds
Started	May 30 12:50:06 PM PDT 24
Finished	May 30 12:54:42 PM PDT 24
Peak memory	217076 kb
Host	smart-269f2630-7651-4071-a18c-394ba0ef19b3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802287990 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2802287990
Directory	/workspace/0.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.uart_tx_ovrd.1006287023
Short name	T445
Test name
Test status
Simulation time	629220623 ps
CPU time	2.15 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:50:15 PM PDT 24
Peak memory	198624 kb
Host	smart-3cd70d88-1730-4e03-9a69-b6f47d1d4083
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1006287023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1006287023
Directory	/workspace/0.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/0.uart_tx_rx.2595034536
Short name	T551
Test name
Test status
Simulation time	40572670283 ps
CPU time	9.6 seconds
Started	May 30 12:50:06 PM PDT 24
Finished	May 30 12:50:17 PM PDT 24
Peak memory	197964 kb
Host	smart-ff7ecc22-da9f-4f2f-ae1d-1245dfbcdc46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2595034536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2595034536
Directory	/workspace/0.uart_tx_rx/latest

Test location	/workspace/coverage/default/1.uart_fifo_full.3839839250
Short name	T753
Test name
Test status
Simulation time	97143016490 ps
CPU time	38.14 seconds
Started	May 30 12:50:12 PM PDT 24
Finished	May 30 12:50:53 PM PDT 24
Peak memory	200312 kb
Host	smart-b1780b83-921d-4828-96e1-f6c1a040c0d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839839250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3839839250
Directory	/workspace/1.uart_fifo_full/latest

Test location	/workspace/coverage/default/1.uart_fifo_overflow.3625031960
Short name	T931
Test name
Test status
Simulation time	82093168910 ps
CPU time	229.32 seconds
Started	May 30 12:50:14 PM PDT 24
Finished	May 30 12:54:05 PM PDT 24
Peak memory	200288 kb
Host	smart-eb5c5397-cf97-4451-b07d-1c8cc5b6d1ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3625031960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3625031960
Directory	/workspace/1.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/1.uart_fifo_reset.1518991114
Short name	T1005
Test name
Test status
Simulation time	25689806793 ps
CPU time	108.81 seconds
Started	May 30 12:50:08 PM PDT 24
Finished	May 30 12:51:58 PM PDT 24
Peak memory	200388 kb
Host	smart-9c9754b3-9c43-4c99-a391-da08dd1e5d6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1518991114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1518991114
Directory	/workspace/1.uart_fifo_reset/latest

Test location	/workspace/coverage/default/1.uart_intr.2639166414
Short name	T823
Test name
Test status
Simulation time	28589935637 ps
CPU time	48.11 seconds
Started	May 30 12:50:09 PM PDT 24
Finished	May 30 12:51:00 PM PDT 24
Peak memory	200248 kb
Host	smart-dfdb774a-b250-47b9-9414-16abf2384e1b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639166414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2639166414
Directory	/workspace/1.uart_intr/latest

Test location	/workspace/coverage/default/1.uart_long_xfer_wo_dly.3079901127
Short name	T540
Test name
Test status
Simulation time	145378914100 ps
CPU time	251.46 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:54:24 PM PDT 24
Peak memory	200268 kb
Host	smart-d05453d6-9aba-4735-bf63-760ec73cd56b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3079901127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3079901127
Directory	/workspace/1.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/1.uart_loopback.2792262468
Short name	T822
Test name
Test status
Simulation time	8718814193 ps
CPU time	8.86 seconds
Started	May 30 12:50:12 PM PDT 24
Finished	May 30 12:50:23 PM PDT 24
Peak memory	200148 kb
Host	smart-03813fa2-384b-466e-8f7e-2ac911d1914f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2792262468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2792262468
Directory	/workspace/1.uart_loopback/latest

Test location	/workspace/coverage/default/1.uart_noise_filter.735811932
Short name	T296
Test name
Test status
Simulation time	19875119549 ps
CPU time	20.09 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:50:33 PM PDT 24
Peak memory	199960 kb
Host	smart-f108b6f9-a259-43d6-90fe-0341feb421d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=735811932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.735811932
Directory	/workspace/1.uart_noise_filter/latest

Test location	/workspace/coverage/default/1.uart_perf.1909755982
Short name	T1033
Test name
Test status
Simulation time	34287778313 ps
CPU time	721.67 seconds
Started	May 30 12:50:08 PM PDT 24
Finished	May 30 01:02:11 PM PDT 24
Peak memory	200208 kb
Host	smart-c9dd8e19-b04e-4cea-ae3c-eb0697fba1bd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1909755982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1909755982
Directory	/workspace/1.uart_perf/latest

Test location	/workspace/coverage/default/1.uart_rx_oversample.789104557
Short name	T424
Test name
Test status
Simulation time	3532411498 ps
CPU time	25.1 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:50:38 PM PDT 24
Peak memory	198260 kb
Host	smart-0c446541-fc5e-4b54-b556-fed1f98a1954
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=789104557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.789104557
Directory	/workspace/1.uart_rx_oversample/latest

Test location	/workspace/coverage/default/1.uart_rx_parity_err.2877265995
Short name	T157
Test name
Test status
Simulation time	58677961585 ps
CPU time	21.79 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:50:35 PM PDT 24
Peak memory	200108 kb
Host	smart-ec589b9a-a22d-47a4-8b16-75d0100114d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877265995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2877265995
Directory	/workspace/1.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/1.uart_rx_start_bit_filter.3274514642
Short name	T576
Test name
Test status
Simulation time	3602628069 ps
CPU time	7.04 seconds
Started	May 30 12:50:07 PM PDT 24
Finished	May 30 12:50:16 PM PDT 24
Peak memory	196164 kb
Host	smart-f838065a-21ea-462f-ab0b-a8eeb848dccf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3274514642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3274514642
Directory	/workspace/1.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/1.uart_sec_cm.60411418
Short name	T29
Test name
Test status
Simulation time	372666609 ps
CPU time	0.85 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:50:13 PM PDT 24
Peak memory	218632 kb
Host	smart-f6e4920d-8a7b-4c85-8e62-10ae3ea66c53
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60411418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.60411418
Directory	/workspace/1.uart_sec_cm/latest

Test location	/workspace/coverage/default/1.uart_smoke.2256801843
Short name	T1114
Test name
Test status
Simulation time	5359729122 ps
CPU time	10.9 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:50:25 PM PDT 24
Peak memory	199796 kb
Host	smart-1699cc1c-a358-45d2-874b-0d81cab229f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2256801843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2256801843
Directory	/workspace/1.uart_smoke/latest

Test location	/workspace/coverage/default/1.uart_stress_all.3259196299
Short name	T1111
Test name
Test status
Simulation time	56226739006 ps
CPU time	93.71 seconds
Started	May 30 12:50:12 PM PDT 24
Finished	May 30 12:51:48 PM PDT 24
Peak memory	216668 kb
Host	smart-8c2c2228-ce5f-4064-9134-a115aa5978aa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259196299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3259196299
Directory	/workspace/1.uart_stress_all/latest

Test location	/workspace/coverage/default/1.uart_stress_all_with_rand_reset.108850109
Short name	T48
Test name
Test status
Simulation time	27529016028 ps
CPU time	215.71 seconds
Started	May 30 12:50:07 PM PDT 24
Finished	May 30 12:53:43 PM PDT 24
Peak memory	216884 kb
Host	smart-2890ced5-467c-44b6-a185-fb9aba1ec4b1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108850109 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.108850109
Directory	/workspace/1.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.uart_tx_ovrd.2033416310
Short name	T815
Test name
Test status
Simulation time	637893208 ps
CPU time	2.87 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:50:15 PM PDT 24
Peak memory	200128 kb
Host	smart-37244eed-dabd-487f-a0bf-78ce1fc820a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2033416310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2033416310
Directory	/workspace/1.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/1.uart_tx_rx.2431488091
Short name	T810
Test name
Test status
Simulation time	118725737086 ps
CPU time	79.14 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:51:31 PM PDT 24
Peak memory	200360 kb
Host	smart-76267bb6-fee5-465b-8691-6fe1eda29d7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431488091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2431488091
Directory	/workspace/1.uart_tx_rx/latest

Test location	/workspace/coverage/default/10.uart_alert_test.1668904161
Short name	T1073
Test name
Test status
Simulation time	69498123 ps
CPU time	0.52 seconds
Started	May 30 12:50:38 PM PDT 24
Finished	May 30 12:50:40 PM PDT 24
Peak memory	195060 kb
Host	smart-507d362c-4f4f-4927-aa8e-61708ce0e7cb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668904161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1668904161
Directory	/workspace/10.uart_alert_test/latest

Test location	/workspace/coverage/default/10.uart_fifo_full.1089075115
Short name	T529
Test name
Test status
Simulation time	66546327329 ps
CPU time	115.92 seconds
Started	May 30 12:50:31 PM PDT 24
Finished	May 30 12:52:27 PM PDT 24
Peak memory	200392 kb
Host	smart-acfea112-9a81-4d71-a55d-347665763dc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1089075115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1089075115
Directory	/workspace/10.uart_fifo_full/latest

Test location	/workspace/coverage/default/10.uart_fifo_overflow.3125298024
Short name	T615
Test name
Test status
Simulation time	108799510140 ps
CPU time	159.04 seconds
Started	May 30 12:50:36 PM PDT 24
Finished	May 30 12:53:16 PM PDT 24
Peak memory	200368 kb
Host	smart-69943cd6-409e-4262-907f-a81bc296937b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3125298024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3125298024
Directory	/workspace/10.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/10.uart_fifo_reset.2583963432
Short name	T236
Test name
Test status
Simulation time	27148344655 ps
CPU time	47.96 seconds
Started	May 30 12:50:39 PM PDT 24
Finished	May 30 12:51:28 PM PDT 24
Peak memory	200396 kb
Host	smart-6d5d4c30-8858-4954-9e90-8bd4932e78a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2583963432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2583963432
Directory	/workspace/10.uart_fifo_reset/latest

Test location	/workspace/coverage/default/10.uart_intr.212723942
Short name	T621
Test name
Test status
Simulation time	45617159193 ps
CPU time	38.62 seconds
Started	May 30 12:50:37 PM PDT 24
Finished	May 30 12:51:17 PM PDT 24
Peak memory	200232 kb
Host	smart-5446a3d7-134e-4ab2-992e-19d3c4ee24ad
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212723942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.212723942
Directory	/workspace/10.uart_intr/latest

Test location	/workspace/coverage/default/10.uart_long_xfer_wo_dly.3575614436
Short name	T624
Test name
Test status
Simulation time	68506415329 ps
CPU time	370.86 seconds
Started	May 30 12:50:33 PM PDT 24
Finished	May 30 12:56:45 PM PDT 24
Peak memory	200324 kb
Host	smart-1068a1c8-abad-4ef4-9214-1e2441a177c8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3575614436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3575614436
Directory	/workspace/10.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/10.uart_loopback.4072813409
Short name	T401
Test name
Test status
Simulation time	11107230031 ps
CPU time	6.58 seconds
Started	May 30 12:50:31 PM PDT 24
Finished	May 30 12:50:39 PM PDT 24
Peak memory	200008 kb
Host	smart-637711ac-3b14-40e2-b2e5-604f7d73f995
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4072813409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.4072813409
Directory	/workspace/10.uart_loopback/latest

Test location	/workspace/coverage/default/10.uart_noise_filter.1904273074
Short name	T891
Test name
Test status
Simulation time	37769365942 ps
CPU time	31.53 seconds
Started	May 30 12:50:39 PM PDT 24
Finished	May 30 12:51:12 PM PDT 24
Peak memory	198952 kb
Host	smart-49e8e316-730c-4e86-89e9-149b8f286d07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1904273074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1904273074
Directory	/workspace/10.uart_noise_filter/latest

Test location	/workspace/coverage/default/10.uart_perf.170966750
Short name	T888
Test name
Test status
Simulation time	14893621454 ps
CPU time	903.88 seconds
Started	May 30 12:50:32 PM PDT 24
Finished	May 30 01:05:37 PM PDT 24
Peak memory	200392 kb
Host	smart-96305226-d8b9-4d9b-9c12-d03387b6647d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=170966750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.170966750
Directory	/workspace/10.uart_perf/latest

Test location	/workspace/coverage/default/10.uart_rx_oversample.3905892641
Short name	T966
Test name
Test status
Simulation time	1409126590 ps
CPU time	1.39 seconds
Started	May 30 12:50:33 PM PDT 24
Finished	May 30 12:50:36 PM PDT 24
Peak memory	198364 kb
Host	smart-53445c4e-0576-4677-8e34-2f765a1d9653
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3905892641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3905892641
Directory	/workspace/10.uart_rx_oversample/latest

Test location	/workspace/coverage/default/10.uart_rx_parity_err.611875890
Short name	T182
Test name
Test status
Simulation time	225588532693 ps
CPU time	89.58 seconds
Started	May 30 12:50:32 PM PDT 24
Finished	May 30 12:52:03 PM PDT 24
Peak memory	200336 kb
Host	smart-64e51545-163e-4028-a90e-6ba49dd21da6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=611875890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.611875890
Directory	/workspace/10.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/10.uart_rx_start_bit_filter.3255740008
Short name	T868
Test name
Test status
Simulation time	40822315714 ps
CPU time	69.72 seconds
Started	May 30 12:50:31 PM PDT 24
Finished	May 30 12:51:42 PM PDT 24
Peak memory	196348 kb
Host	smart-fa655134-16da-4a7c-b737-3777e3883b80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3255740008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3255740008
Directory	/workspace/10.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/10.uart_smoke.2861376287
Short name	T300
Test name
Test status
Simulation time	464035172 ps
CPU time	1.88 seconds
Started	May 30 12:50:40 PM PDT 24
Finished	May 30 12:50:43 PM PDT 24
Peak memory	200072 kb
Host	smart-786885b1-045b-470f-b326-efb65e2835e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2861376287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2861376287
Directory	/workspace/10.uart_smoke/latest

Test location	/workspace/coverage/default/10.uart_stress_all_with_rand_reset.2165981027
Short name	T963
Test name
Test status
Simulation time	67517447322 ps
CPU time	1395.91 seconds
Started	May 30 12:50:38 PM PDT 24
Finished	May 30 01:13:55 PM PDT 24
Peak memory	216932 kb
Host	smart-7da8f7d8-7b11-4206-9c82-3c6a8aea07a9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165981027 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2165981027
Directory	/workspace/10.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.uart_tx_ovrd.3794511990
Short name	T1156
Test name
Test status
Simulation time	1554908773 ps
CPU time	2.13 seconds
Started	May 30 12:50:39 PM PDT 24
Finished	May 30 12:50:43 PM PDT 24
Peak memory	199068 kb
Host	smart-7902cc1e-dceb-4f57-8508-cec38190473e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3794511990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3794511990
Directory	/workspace/10.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/10.uart_tx_rx.724019133
Short name	T90
Test name
Test status
Simulation time	34200481837 ps
CPU time	19.51 seconds
Started	May 30 12:50:32 PM PDT 24
Finished	May 30 12:50:53 PM PDT 24
Peak memory	200376 kb
Host	smart-4cf50545-7be9-418c-a7d1-cbda0e7c75ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724019133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.724019133
Directory	/workspace/10.uart_tx_rx/latest

Test location	/workspace/coverage/default/101.uart_fifo_reset.2163652831
Short name	T940
Test name
Test status
Simulation time	197408768918 ps
CPU time	162.92 seconds
Started	May 30 12:53:37 PM PDT 24
Finished	May 30 12:56:21 PM PDT 24
Peak memory	200260 kb
Host	smart-95d7871c-a818-4e99-b2e0-155acc275840
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163652831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2163652831
Directory	/workspace/101.uart_fifo_reset/latest

Test location	/workspace/coverage/default/102.uart_fifo_reset.1098419730
Short name	T972
Test name
Test status
Simulation time	64384719460 ps
CPU time	102.07 seconds
Started	May 30 12:53:38 PM PDT 24
Finished	May 30 12:55:21 PM PDT 24
Peak memory	200292 kb
Host	smart-5b43cb3e-19a2-4f11-a257-83c2694002ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1098419730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1098419730
Directory	/workspace/102.uart_fifo_reset/latest

Test location	/workspace/coverage/default/103.uart_fifo_reset.3369645850
Short name	T562
Test name
Test status
Simulation time	135689278825 ps
CPU time	19.18 seconds
Started	May 30 12:53:48 PM PDT 24
Finished	May 30 12:54:08 PM PDT 24
Peak memory	200380 kb
Host	smart-7a433809-91e3-4bc3-b75e-962caa1301ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3369645850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3369645850
Directory	/workspace/103.uart_fifo_reset/latest

Test location	/workspace/coverage/default/104.uart_fifo_reset.2285985641
Short name	T952
Test name
Test status
Simulation time	176257905902 ps
CPU time	76.02 seconds
Started	May 30 12:53:55 PM PDT 24
Finished	May 30 12:55:12 PM PDT 24
Peak memory	200320 kb
Host	smart-c1ce0517-105d-4e0c-8431-4278a5081b16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2285985641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2285985641
Directory	/workspace/104.uart_fifo_reset/latest

Test location	/workspace/coverage/default/105.uart_fifo_reset.3017031523
Short name	T802
Test name
Test status
Simulation time	38214720572 ps
CPU time	15.36 seconds
Started	May 30 12:53:47 PM PDT 24
Finished	May 30 12:54:03 PM PDT 24
Peak memory	200220 kb
Host	smart-c869f419-77b6-44ce-b211-7725de90fa0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017031523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3017031523
Directory	/workspace/105.uart_fifo_reset/latest

Test location	/workspace/coverage/default/106.uart_fifo_reset.2040888081
Short name	T1166
Test name
Test status
Simulation time	98444608938 ps
CPU time	168.39 seconds
Started	May 30 12:53:47 PM PDT 24
Finished	May 30 12:56:36 PM PDT 24
Peak memory	200372 kb
Host	smart-73e39660-5769-4c90-8f87-3191c4c2cae9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040888081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2040888081
Directory	/workspace/106.uart_fifo_reset/latest

Test location	/workspace/coverage/default/108.uart_fifo_reset.3555428465
Short name	T1131
Test name
Test status
Simulation time	32023006994 ps
CPU time	45.8 seconds
Started	May 30 12:53:48 PM PDT 24
Finished	May 30 12:54:35 PM PDT 24
Peak memory	200120 kb
Host	smart-695bf2a6-e75f-4033-bc21-c5be5729ec02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3555428465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3555428465
Directory	/workspace/108.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_alert_test.3496325975
Short name	T373
Test name
Test status
Simulation time	50555499 ps
CPU time	0.56 seconds
Started	May 30 12:50:34 PM PDT 24
Finished	May 30 12:50:36 PM PDT 24
Peak memory	195760 kb
Host	smart-c44a1370-f2e8-4865-8957-3725d5c5d198
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496325975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3496325975
Directory	/workspace/11.uart_alert_test/latest

Test location	/workspace/coverage/default/11.uart_fifo_overflow.1275685689
Short name	T700
Test name
Test status
Simulation time	82611156563 ps
CPU time	12.08 seconds
Started	May 30 12:50:39 PM PDT 24
Finished	May 30 12:50:52 PM PDT 24
Peak memory	200420 kb
Host	smart-99c986c3-5c37-43f7-8154-dcc05329a6e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275685689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1275685689
Directory	/workspace/11.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/11.uart_fifo_reset.2220026251
Short name	T589
Test name
Test status
Simulation time	35946136035 ps
CPU time	17.86 seconds
Started	May 30 12:50:32 PM PDT 24
Finished	May 30 12:50:51 PM PDT 24
Peak memory	200240 kb
Host	smart-d58689c8-f63c-497c-a11b-2f5b1b2184b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2220026251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2220026251
Directory	/workspace/11.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_intr.163371147
Short name	T339
Test name
Test status
Simulation time	39716542751 ps
CPU time	65.95 seconds
Started	May 30 12:50:31 PM PDT 24
Finished	May 30 12:51:38 PM PDT 24
Peak memory	199384 kb
Host	smart-afbbabe8-bd40-4f75-871f-385abf19c29c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163371147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.163371147
Directory	/workspace/11.uart_intr/latest

Test location	/workspace/coverage/default/11.uart_long_xfer_wo_dly.2543483926
Short name	T849
Test name
Test status
Simulation time	58336284178 ps
CPU time	111.63 seconds
Started	May 30 12:50:34 PM PDT 24
Finished	May 30 12:52:27 PM PDT 24
Peak memory	200332 kb
Host	smart-7b2ecb46-5aca-4613-8fb4-85ab9c271ff7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2543483926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2543483926
Directory	/workspace/11.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/11.uart_loopback.3147200686
Short name	T693
Test name
Test status
Simulation time	2558657587 ps
CPU time	2.61 seconds
Started	May 30 12:50:31 PM PDT 24
Finished	May 30 12:50:34 PM PDT 24
Peak memory	199076 kb
Host	smart-fbc198e7-96b4-4ad6-ac72-e5a5700cc312
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3147200686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3147200686
Directory	/workspace/11.uart_loopback/latest

Test location	/workspace/coverage/default/11.uart_noise_filter.755346418
Short name	T760
Test name
Test status
Simulation time	155793429721 ps
CPU time	96.95 seconds
Started	May 30 12:50:33 PM PDT 24
Finished	May 30 12:52:11 PM PDT 24
Peak memory	208592 kb
Host	smart-6df6349f-2cf5-46c0-a3b0-08dd22deac6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755346418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.755346418
Directory	/workspace/11.uart_noise_filter/latest

Test location	/workspace/coverage/default/11.uart_perf.2951359358
Short name	T956
Test name
Test status
Simulation time	12361557962 ps
CPU time	660.76 seconds
Started	May 30 12:50:33 PM PDT 24
Finished	May 30 01:01:35 PM PDT 24
Peak memory	200408 kb
Host	smart-8d6e64a4-9776-43a4-b42d-8be5564f7ed6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2951359358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2951359358
Directory	/workspace/11.uart_perf/latest

Test location	/workspace/coverage/default/11.uart_rx_oversample.1221456423
Short name	T878
Test name
Test status
Simulation time	7498813990 ps
CPU time	17.04 seconds
Started	May 30 12:50:34 PM PDT 24
Finished	May 30 12:50:52 PM PDT 24
Peak memory	199140 kb
Host	smart-c1e1b57a-6b92-4b63-8c96-01fb1552ec8b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1221456423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1221456423
Directory	/workspace/11.uart_rx_oversample/latest

Test location	/workspace/coverage/default/11.uart_rx_parity_err.523819822
Short name	T329
Test name
Test status
Simulation time	107781780665 ps
CPU time	179.13 seconds
Started	May 30 12:50:31 PM PDT 24
Finished	May 30 12:53:31 PM PDT 24
Peak memory	200076 kb
Host	smart-88abb73c-7127-45d6-9cea-1d150bb38187
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=523819822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.523819822
Directory	/workspace/11.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/11.uart_rx_start_bit_filter.512419505
Short name	T916
Test name
Test status
Simulation time	48470661045 ps
CPU time	37.93 seconds
Started	May 30 12:50:37 PM PDT 24
Finished	May 30 12:51:16 PM PDT 24
Peak memory	195996 kb
Host	smart-50631132-e116-49a2-ac6e-4fe298091d99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=512419505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.512419505
Directory	/workspace/11.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/11.uart_smoke.3298977639
Short name	T305
Test name
Test status
Simulation time	904889281 ps
CPU time	2.18 seconds
Started	May 30 12:50:31 PM PDT 24
Finished	May 30 12:50:34 PM PDT 24
Peak memory	199324 kb
Host	smart-3952c7d1-05a2-4397-9e0d-1d1b0415eefe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3298977639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3298977639
Directory	/workspace/11.uart_smoke/latest

Test location	/workspace/coverage/default/11.uart_stress_all.1486505219
Short name	T405
Test name
Test status
Simulation time	105205808905 ps
CPU time	213.5 seconds
Started	May 30 12:50:38 PM PDT 24
Finished	May 30 12:54:13 PM PDT 24
Peak memory	208748 kb
Host	smart-3c0ed581-72d3-4a1b-a290-18ffd6cb3e5a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486505219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1486505219
Directory	/workspace/11.uart_stress_all/latest

Test location	/workspace/coverage/default/11.uart_stress_all_with_rand_reset.2972297054
Short name	T1125
Test name
Test status
Simulation time	56470140747 ps
CPU time	429.54 seconds
Started	May 30 12:50:39 PM PDT 24
Finished	May 30 12:57:50 PM PDT 24
Peak memory	208744 kb
Host	smart-af16fc8d-0298-468c-8ad7-62b37c69b393
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972297054 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2972297054
Directory	/workspace/11.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.uart_tx_ovrd.3381107756
Short name	T1144
Test name
Test status
Simulation time	3628275193 ps
CPU time	1.44 seconds
Started	May 30 12:50:31 PM PDT 24
Finished	May 30 12:50:33 PM PDT 24
Peak memory	200316 kb
Host	smart-182d12b1-7e15-48cd-8a6f-abe13b8ee79a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3381107756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3381107756
Directory	/workspace/11.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/11.uart_tx_rx.1584527903
Short name	T807
Test name
Test status
Simulation time	80450402257 ps
CPU time	32.29 seconds
Started	May 30 12:50:38 PM PDT 24
Finished	May 30 12:51:12 PM PDT 24
Peak memory	200224 kb
Host	smart-30e4bd7e-7a1a-44e1-8094-52e3ad007bd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584527903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1584527903
Directory	/workspace/11.uart_tx_rx/latest

Test location	/workspace/coverage/default/110.uart_fifo_reset.2342044539
Short name	T813
Test name
Test status
Simulation time	18462967396 ps
CPU time	18.33 seconds
Started	May 30 12:53:49 PM PDT 24
Finished	May 30 12:54:08 PM PDT 24
Peak memory	200316 kb
Host	smart-4ee9efcf-e9dd-49b1-98a1-41dc18d51231
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2342044539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2342044539
Directory	/workspace/110.uart_fifo_reset/latest

Test location	/workspace/coverage/default/111.uart_fifo_reset.1251476789
Short name	T1146
Test name
Test status
Simulation time	20399182643 ps
CPU time	26.69 seconds
Started	May 30 12:53:49 PM PDT 24
Finished	May 30 12:54:16 PM PDT 24
Peak memory	200400 kb
Host	smart-0b33ae24-0c55-4f1f-8d2a-c9836efb8314
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1251476789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1251476789
Directory	/workspace/111.uart_fifo_reset/latest

Test location	/workspace/coverage/default/112.uart_fifo_reset.369540257
Short name	T456
Test name
Test status
Simulation time	65961952798 ps
CPU time	133.26 seconds
Started	May 30 12:53:48 PM PDT 24
Finished	May 30 12:56:02 PM PDT 24
Peak memory	200380 kb
Host	smart-d06522d2-26da-4840-9f75-ba5ed860d34e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=369540257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.369540257
Directory	/workspace/112.uart_fifo_reset/latest

Test location	/workspace/coverage/default/113.uart_fifo_reset.2330907173
Short name	T920
Test name
Test status
Simulation time	158560666480 ps
CPU time	156.33 seconds
Started	May 30 12:53:47 PM PDT 24
Finished	May 30 12:56:24 PM PDT 24
Peak memory	200388 kb
Host	smart-e8b0d2af-0555-45ce-b9b3-bef1fd8d7d0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2330907173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2330907173
Directory	/workspace/113.uart_fifo_reset/latest

Test location	/workspace/coverage/default/114.uart_fifo_reset.2799184896
Short name	T50
Test name
Test status
Simulation time	26447797139 ps
CPU time	15.07 seconds
Started	May 30 12:53:49 PM PDT 24
Finished	May 30 12:54:04 PM PDT 24
Peak memory	200332 kb
Host	smart-3926c2a1-5357-490a-a7a3-a077b0eea1f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2799184896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2799184896
Directory	/workspace/114.uart_fifo_reset/latest

Test location	/workspace/coverage/default/116.uart_fifo_reset.1676750368
Short name	T141
Test name
Test status
Simulation time	183306203010 ps
CPU time	93.6 seconds
Started	May 30 12:53:47 PM PDT 24
Finished	May 30 12:55:21 PM PDT 24
Peak memory	200340 kb
Host	smart-a4415fb9-f6a4-4977-bab4-2adfca677c1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1676750368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1676750368
Directory	/workspace/116.uart_fifo_reset/latest

Test location	/workspace/coverage/default/117.uart_fifo_reset.3436435707
Short name	T1078
Test name
Test status
Simulation time	75937601774 ps
CPU time	28.14 seconds
Started	May 30 12:53:50 PM PDT 24
Finished	May 30 12:54:19 PM PDT 24
Peak memory	200336 kb
Host	smart-ddb1c9e7-0982-43f6-8438-713eabe783b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3436435707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3436435707
Directory	/workspace/117.uart_fifo_reset/latest

Test location	/workspace/coverage/default/118.uart_fifo_reset.1587852949
Short name	T493
Test name
Test status
Simulation time	116864557859 ps
CPU time	47.93 seconds
Started	May 30 12:53:48 PM PDT 24
Finished	May 30 12:54:36 PM PDT 24
Peak memory	200376 kb
Host	smart-3a9b2469-86b6-4768-9c82-f2adedaffb56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1587852949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1587852949
Directory	/workspace/118.uart_fifo_reset/latest

Test location	/workspace/coverage/default/119.uart_fifo_reset.1933749252
Short name	T788
Test name
Test status
Simulation time	96658989753 ps
CPU time	168.99 seconds
Started	May 30 12:53:49 PM PDT 24
Finished	May 30 12:56:39 PM PDT 24
Peak memory	200336 kb
Host	smart-b2a3f000-0c56-4df0-b6d5-dc44ebd8e1c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1933749252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1933749252
Directory	/workspace/119.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_alert_test.2397729260
Short name	T588
Test name
Test status
Simulation time	14975221 ps
CPU time	0.57 seconds
Started	May 30 12:50:37 PM PDT 24
Finished	May 30 12:50:38 PM PDT 24
Peak memory	195664 kb
Host	smart-202e72fe-93b6-45e2-9f59-87970e5199f2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397729260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2397729260
Directory	/workspace/12.uart_alert_test/latest

Test location	/workspace/coverage/default/12.uart_fifo_full.1085953418
Short name	T1135
Test name
Test status
Simulation time	42726887084 ps
CPU time	30.65 seconds
Started	May 30 12:50:38 PM PDT 24
Finished	May 30 12:51:10 PM PDT 24
Peak memory	199796 kb
Host	smart-a201f5e8-4ece-4bd6-835f-9ee7250e3c5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1085953418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1085953418
Directory	/workspace/12.uart_fifo_full/latest

Test location	/workspace/coverage/default/12.uart_fifo_overflow.975350053
Short name	T801
Test name
Test status
Simulation time	21853758279 ps
CPU time	15.37 seconds
Started	May 30 12:50:38 PM PDT 24
Finished	May 30 12:50:55 PM PDT 24
Peak memory	200240 kb
Host	smart-5ec20722-3655-4978-ab2e-839406867e5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=975350053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.975350053
Directory	/workspace/12.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/12.uart_fifo_reset.3275180540
Short name	T535
Test name
Test status
Simulation time	172998333633 ps
CPU time	195.59 seconds
Started	May 30 12:50:34 PM PDT 24
Finished	May 30 12:53:51 PM PDT 24
Peak memory	200276 kb
Host	smart-55bbb65d-0958-444b-b2bd-61c6848e5a06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3275180540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3275180540
Directory	/workspace/12.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_intr.107171030
Short name	T1026
Test name
Test status
Simulation time	346483190453 ps
CPU time	146.2 seconds
Started	May 30 12:50:32 PM PDT 24
Finished	May 30 12:53:00 PM PDT 24
Peak memory	200032 kb
Host	smart-3000e61c-0b1c-4bea-8e95-1cd6d68043e1
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107171030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.107171030
Directory	/workspace/12.uart_intr/latest

Test location	/workspace/coverage/default/12.uart_long_xfer_wo_dly.2149512257
Short name	T378
Test name
Test status
Simulation time	165938672149 ps
CPU time	415.32 seconds
Started	May 30 12:50:40 PM PDT 24
Finished	May 30 12:57:36 PM PDT 24
Peak memory	199992 kb
Host	smart-21d3148c-77f6-4648-9c47-8019c2d5a5db
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2149512257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2149512257
Directory	/workspace/12.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/12.uart_loopback.973280983
Short name	T556
Test name
Test status
Simulation time	3517471620 ps
CPU time	2.32 seconds
Started	May 30 12:50:38 PM PDT 24
Finished	May 30 12:50:42 PM PDT 24
Peak memory	197168 kb
Host	smart-9176a378-2efe-47a5-bfb8-0f56f231b685
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=973280983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.973280983
Directory	/workspace/12.uart_loopback/latest

Test location	/workspace/coverage/default/12.uart_noise_filter.728858259
Short name	T463
Test name
Test status
Simulation time	82872581621 ps
CPU time	15.27 seconds
Started	May 30 12:50:34 PM PDT 24
Finished	May 30 12:50:51 PM PDT 24
Peak memory	200580 kb
Host	smart-587a1cb8-d89c-4360-a142-e200204e120b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=728858259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.728858259
Directory	/workspace/12.uart_noise_filter/latest

Test location	/workspace/coverage/default/12.uart_perf.3296408000
Short name	T979
Test name
Test status
Simulation time	26631615414 ps
CPU time	1471.34 seconds
Started	May 30 12:50:35 PM PDT 24
Finished	May 30 01:15:07 PM PDT 24
Peak memory	200324 kb
Host	smart-8e265fe3-0543-434a-a057-47cb79baf99e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3296408000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3296408000
Directory	/workspace/12.uart_perf/latest

Test location	/workspace/coverage/default/12.uart_rx_oversample.1119478885
Short name	T351
Test name
Test status
Simulation time	1500687809 ps
CPU time	2.81 seconds
Started	May 30 12:50:38 PM PDT 24
Finished	May 30 12:50:43 PM PDT 24
Peak memory	198352 kb
Host	smart-25921a76-975f-4768-acff-23af801e57d8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1119478885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1119478885
Directory	/workspace/12.uart_rx_oversample/latest

Test location	/workspace/coverage/default/12.uart_rx_parity_err.1140072902
Short name	T1012
Test name
Test status
Simulation time	208981920884 ps
CPU time	81.41 seconds
Started	May 30 12:50:39 PM PDT 24
Finished	May 30 12:52:01 PM PDT 24
Peak memory	200020 kb
Host	smart-b9e33d44-43be-42c1-a67d-7aa4f038b94a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1140072902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1140072902
Directory	/workspace/12.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/12.uart_rx_start_bit_filter.810999088
Short name	T660
Test name
Test status
Simulation time	2730683530 ps
CPU time	2.61 seconds
Started	May 30 12:50:40 PM PDT 24
Finished	May 30 12:50:43 PM PDT 24
Peak memory	196192 kb
Host	smart-bd59ce77-09fd-4c0c-8bc3-a9a0e519fc70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=810999088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.810999088
Directory	/workspace/12.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/12.uart_smoke.2871714607
Short name	T1049
Test name
Test status
Simulation time	114943002 ps
CPU time	0.85 seconds
Started	May 30 12:50:34 PM PDT 24
Finished	May 30 12:50:36 PM PDT 24
Peak memory	197312 kb
Host	smart-254b628c-5fa4-4c27-856c-aceb74b2e4d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2871714607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2871714607
Directory	/workspace/12.uart_smoke/latest

Test location	/workspace/coverage/default/12.uart_stress_all.2849299999
Short name	T934
Test name
Test status
Simulation time	86263234912 ps
CPU time	509.51 seconds
Started	May 30 12:50:33 PM PDT 24
Finished	May 30 12:59:04 PM PDT 24
Peak memory	200284 kb
Host	smart-e3d1c22d-7e3b-4f4f-b21b-6df37502a2f0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849299999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2849299999
Directory	/workspace/12.uart_stress_all/latest

Test location	/workspace/coverage/default/12.uart_stress_all_with_rand_reset.3592274366
Short name	T897
Test name
Test status
Simulation time	97517893973 ps
CPU time	212.67 seconds
Started	May 30 12:50:34 PM PDT 24
Finished	May 30 12:54:08 PM PDT 24
Peak memory	215032 kb
Host	smart-01dc584d-7377-40e9-add6-250929b56c7c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592274366 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3592274366
Directory	/workspace/12.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.uart_tx_ovrd.2104963036
Short name	T1083
Test name
Test status
Simulation time	558739738 ps
CPU time	1.94 seconds
Started	May 30 12:50:39 PM PDT 24
Finished	May 30 12:50:42 PM PDT 24
Peak memory	199016 kb
Host	smart-2b3beb7d-c242-4857-96d9-e5707edd3f37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2104963036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2104963036
Directory	/workspace/12.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/12.uart_tx_rx.3817820315
Short name	T257
Test name
Test status
Simulation time	80721570201 ps
CPU time	39.78 seconds
Started	May 30 12:50:35 PM PDT 24
Finished	May 30 12:51:16 PM PDT 24
Peak memory	200248 kb
Host	smart-9bb1eefb-8875-40b7-9b44-18fb044af747
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817820315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3817820315
Directory	/workspace/12.uart_tx_rx/latest

Test location	/workspace/coverage/default/120.uart_fifo_reset.398669272
Short name	T904
Test name
Test status
Simulation time	23680177073 ps
CPU time	24.29 seconds
Started	May 30 12:53:47 PM PDT 24
Finished	May 30 12:54:12 PM PDT 24
Peak memory	200396 kb
Host	smart-ac01db9e-5ea3-4863-b329-2de929c4eaab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398669272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.398669272
Directory	/workspace/120.uart_fifo_reset/latest

Test location	/workspace/coverage/default/121.uart_fifo_reset.2844334816
Short name	T710
Test name
Test status
Simulation time	52045726078 ps
CPU time	82.66 seconds
Started	May 30 12:53:49 PM PDT 24
Finished	May 30 12:55:13 PM PDT 24
Peak memory	200292 kb
Host	smart-7f74830b-04f3-4f0f-a36b-ef639ceb941d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2844334816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2844334816
Directory	/workspace/121.uart_fifo_reset/latest

Test location	/workspace/coverage/default/122.uart_fifo_reset.1907170994
Short name	T709
Test name
Test status
Simulation time	97918742854 ps
CPU time	115.18 seconds
Started	May 30 12:53:51 PM PDT 24
Finished	May 30 12:55:46 PM PDT 24
Peak memory	200252 kb
Host	smart-4f444750-7605-4172-9e99-132c17221ca8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1907170994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1907170994
Directory	/workspace/122.uart_fifo_reset/latest

Test location	/workspace/coverage/default/123.uart_fifo_reset.301430858
Short name	T550
Test name
Test status
Simulation time	32876495405 ps
CPU time	35.81 seconds
Started	May 30 12:53:51 PM PDT 24
Finished	May 30 12:54:27 PM PDT 24
Peak memory	200452 kb
Host	smart-42def640-e454-432f-9c33-bac3a058d484
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=301430858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.301430858
Directory	/workspace/123.uart_fifo_reset/latest

Test location	/workspace/coverage/default/124.uart_fifo_reset.986592297
Short name	T873
Test name
Test status
Simulation time	106307326788 ps
CPU time	246.9 seconds
Started	May 30 12:53:49 PM PDT 24
Finished	May 30 12:57:56 PM PDT 24
Peak memory	200372 kb
Host	smart-0ca95026-c30e-40ce-901e-f80ba28e85d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=986592297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.986592297
Directory	/workspace/124.uart_fifo_reset/latest

Test location	/workspace/coverage/default/125.uart_fifo_reset.1109932086
Short name	T1056
Test name
Test status
Simulation time	55170925828 ps
CPU time	64.76 seconds
Started	May 30 12:53:52 PM PDT 24
Finished	May 30 12:54:57 PM PDT 24
Peak memory	200320 kb
Host	smart-041559cd-b367-4ab5-a239-3378716f5b08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1109932086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1109932086
Directory	/workspace/125.uart_fifo_reset/latest

Test location	/workspace/coverage/default/126.uart_fifo_reset.2248596931
Short name	T783
Test name
Test status
Simulation time	233655140024 ps
CPU time	102.73 seconds
Started	May 30 12:53:49 PM PDT 24
Finished	May 30 12:55:33 PM PDT 24
Peak memory	200316 kb
Host	smart-448caa3f-a6b1-44f6-b775-3009cd4b0b14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2248596931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2248596931
Directory	/workspace/126.uart_fifo_reset/latest

Test location	/workspace/coverage/default/127.uart_fifo_reset.2012306394
Short name	T194
Test name
Test status
Simulation time	86422043570 ps
CPU time	34.09 seconds
Started	May 30 12:53:48 PM PDT 24
Finished	May 30 12:54:23 PM PDT 24
Peak memory	200224 kb
Host	smart-f251bbaf-9a8d-43d0-9664-da02ec9c9491
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012306394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2012306394
Directory	/workspace/127.uart_fifo_reset/latest

Test location	/workspace/coverage/default/128.uart_fifo_reset.1404556301
Short name	T1042
Test name
Test status
Simulation time	81211765139 ps
CPU time	45.19 seconds
Started	May 30 12:53:56 PM PDT 24
Finished	May 30 12:54:41 PM PDT 24
Peak memory	200400 kb
Host	smart-4f0f9245-a33e-428f-835a-292a0457b5ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1404556301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1404556301
Directory	/workspace/128.uart_fifo_reset/latest

Test location	/workspace/coverage/default/129.uart_fifo_reset.3314443246
Short name	T633
Test name
Test status
Simulation time	106627475879 ps
CPU time	189.74 seconds
Started	May 30 12:53:48 PM PDT 24
Finished	May 30 12:56:59 PM PDT 24
Peak memory	200356 kb
Host	smart-8f04b1a7-4354-4804-8563-3b2fabe820f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3314443246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3314443246
Directory	/workspace/129.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_alert_test.1208583140
Short name	T94
Test name
Test status
Simulation time	10082458 ps
CPU time	0.55 seconds
Started	May 30 12:50:45 PM PDT 24
Finished	May 30 12:50:46 PM PDT 24
Peak memory	194732 kb
Host	smart-74832fb5-d27e-4fcb-b495-6482e7491ef6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208583140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1208583140
Directory	/workspace/13.uart_alert_test/latest

Test location	/workspace/coverage/default/13.uart_fifo_full.709523841
Short name	T175
Test name
Test status
Simulation time	75107678861 ps
CPU time	9.54 seconds
Started	May 30 12:50:38 PM PDT 24
Finished	May 30 12:50:49 PM PDT 24
Peak memory	200300 kb
Host	smart-bd0d14b9-92ba-4b5d-99d9-7429411ad104
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=709523841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.709523841
Directory	/workspace/13.uart_fifo_full/latest

Test location	/workspace/coverage/default/13.uart_fifo_overflow.3739524713
Short name	T328
Test name
Test status
Simulation time	189602349990 ps
CPU time	63.83 seconds
Started	May 30 12:50:37 PM PDT 24
Finished	May 30 12:51:42 PM PDT 24
Peak memory	200280 kb
Host	smart-c35f8b75-c8d8-457c-bb78-3f521a22413e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739524713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3739524713
Directory	/workspace/13.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/13.uart_fifo_reset.1570291184
Short name	T984
Test name
Test status
Simulation time	66889805497 ps
CPU time	28.5 seconds
Started	May 30 12:50:38 PM PDT 24
Finished	May 30 12:51:08 PM PDT 24
Peak memory	200364 kb
Host	smart-38b955b5-7f6e-46e4-9ba9-835957478c8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570291184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1570291184
Directory	/workspace/13.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_intr.1750963671
Short name	T901
Test name
Test status
Simulation time	311439570427 ps
CPU time	102.28 seconds
Started	May 30 12:50:39 PM PDT 24
Finished	May 30 12:52:22 PM PDT 24
Peak memory	197660 kb
Host	smart-b1e34c35-fd5b-4d2e-87be-1db5bdc33f2a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750963671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1750963671
Directory	/workspace/13.uart_intr/latest

Test location	/workspace/coverage/default/13.uart_loopback.3281968746
Short name	T568
Test name
Test status
Simulation time	7853086604 ps
CPU time	5.24 seconds
Started	May 30 12:50:39 PM PDT 24
Finished	May 30 12:50:45 PM PDT 24
Peak memory	199804 kb
Host	smart-6f9b34d0-f330-4bd1-83f7-844febc54638
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281968746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3281968746
Directory	/workspace/13.uart_loopback/latest

Test location	/workspace/coverage/default/13.uart_noise_filter.2680967998
Short name	T921
Test name
Test status
Simulation time	56005984450 ps
CPU time	28.3 seconds
Started	May 30 12:50:38 PM PDT 24
Finished	May 30 12:51:08 PM PDT 24
Peak memory	199448 kb
Host	smart-21acfdc7-8b69-4c0c-a638-404fa821b1ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2680967998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2680967998
Directory	/workspace/13.uart_noise_filter/latest

Test location	/workspace/coverage/default/13.uart_perf.617808713
Short name	T498
Test name
Test status
Simulation time	6956500424 ps
CPU time	389.72 seconds
Started	May 30 12:50:39 PM PDT 24
Finished	May 30 12:57:10 PM PDT 24
Peak memory	200324 kb
Host	smart-623612e1-e93e-43d9-9039-7ab50bcb12ee
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=617808713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.617808713
Directory	/workspace/13.uart_perf/latest

Test location	/workspace/coverage/default/13.uart_rx_oversample.4080408520
Short name	T793
Test name
Test status
Simulation time	3050016893 ps
CPU time	12.45 seconds
Started	May 30 12:50:40 PM PDT 24
Finished	May 30 12:50:53 PM PDT 24
Peak memory	198892 kb
Host	smart-e7d64a09-eab5-4769-ba3d-7492362abd25
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4080408520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.4080408520
Directory	/workspace/13.uart_rx_oversample/latest

Test location	/workspace/coverage/default/13.uart_rx_parity_err.621271492
Short name	T483
Test name
Test status
Simulation time	115240622576 ps
CPU time	205.35 seconds
Started	May 30 12:50:38 PM PDT 24
Finished	May 30 12:54:05 PM PDT 24
Peak memory	200336 kb
Host	smart-9024851b-0485-4e18-a751-a5281c0bfc7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=621271492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.621271492
Directory	/workspace/13.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/13.uart_rx_start_bit_filter.244913933
Short name	T736
Test name
Test status
Simulation time	5134541520 ps
CPU time	1.51 seconds
Started	May 30 12:50:33 PM PDT 24
Finished	May 30 12:50:36 PM PDT 24
Peak memory	196352 kb
Host	smart-ffb14b4e-78ca-4671-ad98-d253f65ec388
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=244913933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.244913933
Directory	/workspace/13.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/13.uart_smoke.1323548464
Short name	T705
Test name
Test status
Simulation time	675341208 ps
CPU time	2.14 seconds
Started	May 30 12:50:35 PM PDT 24
Finished	May 30 12:50:38 PM PDT 24
Peak memory	200308 kb
Host	smart-c885d6ad-2f67-42e6-b627-e89174b7918a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1323548464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1323548464
Directory	/workspace/13.uart_smoke/latest

Test location	/workspace/coverage/default/13.uart_stress_all.165189121
Short name	T836
Test name
Test status
Simulation time	104061233671 ps
CPU time	111.1 seconds
Started	May 30 12:50:46 PM PDT 24
Finished	May 30 12:52:38 PM PDT 24
Peak memory	200408 kb
Host	smart-62d68284-c03a-49ea-ad04-94c13f2cf8fd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165189121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.165189121
Directory	/workspace/13.uart_stress_all/latest

Test location	/workspace/coverage/default/13.uart_stress_all_with_rand_reset.4266035098
Short name	T1143
Test name
Test status
Simulation time	22802878505 ps
CPU time	131.44 seconds
Started	May 30 12:50:44 PM PDT 24
Finished	May 30 12:52:56 PM PDT 24
Peak memory	216668 kb
Host	smart-1271593b-2996-4965-8360-31687e0a4005
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266035098 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.4266035098
Directory	/workspace/13.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.uart_tx_ovrd.686753382
Short name	T356
Test name
Test status
Simulation time	6459465178 ps
CPU time	31.46 seconds
Started	May 30 12:50:37 PM PDT 24
Finished	May 30 12:51:10 PM PDT 24
Peak memory	199856 kb
Host	smart-163774f8-f981-4444-8bd5-b98805b79067
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=686753382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.686753382
Directory	/workspace/13.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/13.uart_tx_rx.1830450262
Short name	T325
Test name
Test status
Simulation time	29317083720 ps
CPU time	11.24 seconds
Started	May 30 12:50:39 PM PDT 24
Finished	May 30 12:50:51 PM PDT 24
Peak memory	200236 kb
Host	smart-01e2f8de-c49b-4fb9-90f9-dcb6c7c8bc92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1830450262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1830450262
Directory	/workspace/13.uart_tx_rx/latest

Test location	/workspace/coverage/default/130.uart_fifo_reset.2758560717
Short name	T974
Test name
Test status
Simulation time	10009427435 ps
CPU time	17.63 seconds
Started	May 30 12:53:48 PM PDT 24
Finished	May 30 12:54:07 PM PDT 24
Peak memory	200392 kb
Host	smart-e31e8924-f293-460b-88f4-168b4b68db99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758560717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2758560717
Directory	/workspace/130.uart_fifo_reset/latest

Test location	/workspace/coverage/default/133.uart_fifo_reset.1488866362
Short name	T775
Test name
Test status
Simulation time	285022822611 ps
CPU time	412.35 seconds
Started	May 30 12:53:49 PM PDT 24
Finished	May 30 01:00:43 PM PDT 24
Peak memory	200396 kb
Host	smart-97e539e2-8e16-4b75-b151-2ea04fd3f9ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1488866362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1488866362
Directory	/workspace/133.uart_fifo_reset/latest

Test location	/workspace/coverage/default/135.uart_fifo_reset.3827484413
Short name	T1142
Test name
Test status
Simulation time	81184465177 ps
CPU time	189.24 seconds
Started	May 30 12:53:48 PM PDT 24
Finished	May 30 12:56:58 PM PDT 24
Peak memory	200312 kb
Host	smart-c0e14cef-a835-4f3a-a126-f9f26cc5c6e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3827484413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3827484413
Directory	/workspace/135.uart_fifo_reset/latest

Test location	/workspace/coverage/default/136.uart_fifo_reset.768911884
Short name	T225
Test name
Test status
Simulation time	111948652642 ps
CPU time	25.9 seconds
Started	May 30 12:53:50 PM PDT 24
Finished	May 30 12:54:17 PM PDT 24
Peak memory	200396 kb
Host	smart-6ada0ac2-1af4-4acc-8857-7dd66fc52c54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768911884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.768911884
Directory	/workspace/136.uart_fifo_reset/latest

Test location	/workspace/coverage/default/137.uart_fifo_reset.687966508
Short name	T252
Test name
Test status
Simulation time	77624135355 ps
CPU time	22.13 seconds
Started	May 30 12:53:52 PM PDT 24
Finished	May 30 12:54:15 PM PDT 24
Peak memory	200228 kb
Host	smart-01b8914d-6f7e-4e95-bf92-b0ed632a2bec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687966508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.687966508
Directory	/workspace/137.uart_fifo_reset/latest

Test location	/workspace/coverage/default/138.uart_fifo_reset.1376389814
Short name	T997
Test name
Test status
Simulation time	31320330445 ps
CPU time	51.11 seconds
Started	May 30 12:53:51 PM PDT 24
Finished	May 30 12:54:43 PM PDT 24
Peak memory	199900 kb
Host	smart-c61c7de2-b9e9-4ef0-95f8-f98634c17a7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1376389814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1376389814
Directory	/workspace/138.uart_fifo_reset/latest

Test location	/workspace/coverage/default/139.uart_fifo_reset.1980890418
Short name	T724
Test name
Test status
Simulation time	134298314415 ps
CPU time	210.71 seconds
Started	May 30 12:53:52 PM PDT 24
Finished	May 30 12:57:23 PM PDT 24
Peak memory	200152 kb
Host	smart-49a39edf-41a5-47ea-aeea-1e5d85ea2ef3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1980890418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1980890418
Directory	/workspace/139.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_alert_test.4207319705
Short name	T360
Test name
Test status
Simulation time	50773009 ps
CPU time	0.58 seconds
Started	May 30 12:50:44 PM PDT 24
Finished	May 30 12:50:45 PM PDT 24
Peak memory	194716 kb
Host	smart-58419b04-116e-447e-b5f7-fb637e6cd3e2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207319705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.4207319705
Directory	/workspace/14.uart_alert_test/latest

Test location	/workspace/coverage/default/14.uart_fifo_full.184038400
Short name	T507
Test name
Test status
Simulation time	102155825829 ps
CPU time	87.87 seconds
Started	May 30 12:50:48 PM PDT 24
Finished	May 30 12:52:16 PM PDT 24
Peak memory	200372 kb
Host	smart-91892963-85e4-4ac0-be9c-b4698e07c334
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184038400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.184038400
Directory	/workspace/14.uart_fifo_full/latest

Test location	/workspace/coverage/default/14.uart_fifo_reset.1607086371
Short name	T361
Test name
Test status
Simulation time	19469852055 ps
CPU time	10.43 seconds
Started	May 30 12:50:54 PM PDT 24
Finished	May 30 12:51:05 PM PDT 24
Peak memory	200044 kb
Host	smart-da4cb66f-ca74-4d7a-b523-7faab11c5c55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1607086371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1607086371
Directory	/workspace/14.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_intr.2775685531
Short name	T929
Test name
Test status
Simulation time	22846445929 ps
CPU time	25.98 seconds
Started	May 30 12:50:56 PM PDT 24
Finished	May 30 12:51:22 PM PDT 24
Peak memory	200208 kb
Host	smart-cd0fda8c-9eb3-4715-9c8a-3b4f39a61b59
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775685531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2775685531
Directory	/workspace/14.uart_intr/latest

Test location	/workspace/coverage/default/14.uart_long_xfer_wo_dly.1908388749
Short name	T978
Test name
Test status
Simulation time	233840441049 ps
CPU time	385.48 seconds
Started	May 30 12:50:45 PM PDT 24
Finished	May 30 12:57:12 PM PDT 24
Peak memory	200244 kb
Host	smart-7d9bd999-e31d-4f97-b2db-2f44b57e8d42
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1908388749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1908388749
Directory	/workspace/14.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/14.uart_loopback.868709691
Short name	T350
Test name
Test status
Simulation time	8013722255 ps
CPU time	28.84 seconds
Started	May 30 12:50:55 PM PDT 24
Finished	May 30 12:51:25 PM PDT 24
Peak memory	199864 kb
Host	smart-fd1521a2-d959-4097-9f98-246761bfd764
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=868709691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.868709691
Directory	/workspace/14.uart_loopback/latest

Test location	/workspace/coverage/default/14.uart_noise_filter.2494041529
Short name	T779
Test name
Test status
Simulation time	33298387836 ps
CPU time	29.07 seconds
Started	May 30 12:50:47 PM PDT 24
Finished	May 30 12:51:17 PM PDT 24
Peak memory	200564 kb
Host	smart-306a5157-6ec9-4ec1-96fa-5b51a5cd3d64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2494041529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2494041529
Directory	/workspace/14.uart_noise_filter/latest

Test location	/workspace/coverage/default/14.uart_perf.1225862270
Short name	T382
Test name
Test status
Simulation time	17423470691 ps
CPU time	218.9 seconds
Started	May 30 12:50:43 PM PDT 24
Finished	May 30 12:54:22 PM PDT 24
Peak memory	200368 kb
Host	smart-f30dfa57-a3ec-4577-9acd-4c915fa96476
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1225862270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1225862270
Directory	/workspace/14.uart_perf/latest

Test location	/workspace/coverage/default/14.uart_rx_oversample.852529033
Short name	T108
Test name
Test status
Simulation time	6643046722 ps
CPU time	28.91 seconds
Started	May 30 12:50:46 PM PDT 24
Finished	May 30 12:51:16 PM PDT 24
Peak memory	199528 kb
Host	smart-3b5fdc9d-f54a-4050-bca0-64745f4634dc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=852529033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.852529033
Directory	/workspace/14.uart_rx_oversample/latest

Test location	/workspace/coverage/default/14.uart_rx_parity_err.1845326970
Short name	T484
Test name
Test status
Simulation time	143649106982 ps
CPU time	30.4 seconds
Started	May 30 12:50:44 PM PDT 24
Finished	May 30 12:51:15 PM PDT 24
Peak memory	199936 kb
Host	smart-900cf2ad-aab0-44f8-8bc0-aefa1378ba46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1845326970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1845326970
Directory	/workspace/14.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/14.uart_rx_start_bit_filter.1751210866
Short name	T387
Test name
Test status
Simulation time	38166115143 ps
CPU time	65.93 seconds
Started	May 30 12:50:43 PM PDT 24
Finished	May 30 12:51:50 PM PDT 24
Peak memory	196028 kb
Host	smart-91b37c7b-d84f-4510-933f-df0f0c7e3916
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1751210866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1751210866
Directory	/workspace/14.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/14.uart_smoke.2345110577
Short name	T398
Test name
Test status
Simulation time	548731001 ps
CPU time	2.66 seconds
Started	May 30 12:50:47 PM PDT 24
Finished	May 30 12:50:51 PM PDT 24
Peak memory	199008 kb
Host	smart-8a87fdc0-ce2c-490c-90d1-ba1aa42ce877
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2345110577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2345110577
Directory	/workspace/14.uart_smoke/latest

Test location	/workspace/coverage/default/14.uart_stress_all.120557392
Short name	T685
Test name
Test status
Simulation time	115079636233 ps
CPU time	240.59 seconds
Started	May 30 12:50:45 PM PDT 24
Finished	May 30 12:54:46 PM PDT 24
Peak memory	200304 kb
Host	smart-67bdd494-8318-4fca-b6f9-0b5a8ccdd33a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120557392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.120557392
Directory	/workspace/14.uart_stress_all/latest

Test location	/workspace/coverage/default/14.uart_stress_all_with_rand_reset.1269823180
Short name	T59
Test name
Test status
Simulation time	653758219854 ps
CPU time	1316.64 seconds
Started	May 30 12:50:44 PM PDT 24
Finished	May 30 01:12:42 PM PDT 24
Peak memory	217808 kb
Host	smart-eef8cb4c-5ace-4296-b986-362110aa3195
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269823180 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1269823180
Directory	/workspace/14.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.uart_tx_ovrd.2727286345
Short name	T45
Test name
Test status
Simulation time	1752954996 ps
CPU time	4.31 seconds
Started	May 30 12:50:46 PM PDT 24
Finished	May 30 12:50:51 PM PDT 24
Peak memory	199404 kb
Host	smart-858a1f27-576d-49b4-bfcb-cfc1e5062e3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2727286345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2727286345
Directory	/workspace/14.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/14.uart_tx_rx.2410067086
Short name	T311
Test name
Test status
Simulation time	26213931782 ps
CPU time	54.95 seconds
Started	May 30 12:50:44 PM PDT 24
Finished	May 30 12:51:40 PM PDT 24
Peak memory	200316 kb
Host	smart-1aba2939-4694-41ec-8e76-0369cfbda593
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2410067086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2410067086
Directory	/workspace/14.uart_tx_rx/latest

Test location	/workspace/coverage/default/140.uart_fifo_reset.1672367307
Short name	T176
Test name
Test status
Simulation time	119297845684 ps
CPU time	32.05 seconds
Started	May 30 12:53:50 PM PDT 24
Finished	May 30 12:54:23 PM PDT 24
Peak memory	200304 kb
Host	smart-1ab997e3-7919-46fb-aaab-6978137a131a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672367307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1672367307
Directory	/workspace/140.uart_fifo_reset/latest

Test location	/workspace/coverage/default/141.uart_fifo_reset.1277861142
Short name	T652
Test name
Test status
Simulation time	29368711872 ps
CPU time	12.6 seconds
Started	May 30 12:53:51 PM PDT 24
Finished	May 30 12:54:04 PM PDT 24
Peak memory	199956 kb
Host	smart-cb1f2bd3-cffc-49d8-a750-0a721b7b93f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1277861142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1277861142
Directory	/workspace/141.uart_fifo_reset/latest

Test location	/workspace/coverage/default/142.uart_fifo_reset.2410773824
Short name	T706
Test name
Test status
Simulation time	123591821794 ps
CPU time	212.48 seconds
Started	May 30 12:53:49 PM PDT 24
Finished	May 30 12:57:22 PM PDT 24
Peak memory	200384 kb
Host	smart-319ae273-3249-4ef9-bb21-c1161b727f9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2410773824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2410773824
Directory	/workspace/142.uart_fifo_reset/latest

Test location	/workspace/coverage/default/143.uart_fifo_reset.163626732
Short name	T1122
Test name
Test status
Simulation time	112081297442 ps
CPU time	132.2 seconds
Started	May 30 12:53:55 PM PDT 24
Finished	May 30 12:56:08 PM PDT 24
Peak memory	200332 kb
Host	smart-3407c8e7-7f53-428b-82c5-59a533d2985f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=163626732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.163626732
Directory	/workspace/143.uart_fifo_reset/latest

Test location	/workspace/coverage/default/144.uart_fifo_reset.3721773935
Short name	T670
Test name
Test status
Simulation time	74436583245 ps
CPU time	36.45 seconds
Started	May 30 12:53:54 PM PDT 24
Finished	May 30 12:54:31 PM PDT 24
Peak memory	200268 kb
Host	smart-9b2ab4d0-ab24-4b01-a1c4-773aea37c036
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3721773935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3721773935
Directory	/workspace/144.uart_fifo_reset/latest

Test location	/workspace/coverage/default/146.uart_fifo_reset.3636643776
Short name	T601
Test name
Test status
Simulation time	140716884206 ps
CPU time	72.47 seconds
Started	May 30 12:53:54 PM PDT 24
Finished	May 30 12:55:07 PM PDT 24
Peak memory	200296 kb
Host	smart-8bf04cb5-7a35-4930-b289-228f12df9a50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3636643776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3636643776
Directory	/workspace/146.uart_fifo_reset/latest

Test location	/workspace/coverage/default/148.uart_fifo_reset.3622400972
Short name	T786
Test name
Test status
Simulation time	25388679984 ps
CPU time	40.61 seconds
Started	May 30 12:53:53 PM PDT 24
Finished	May 30 12:54:34 PM PDT 24
Peak memory	200220 kb
Host	smart-5f79e8cc-4a15-4ade-93ba-ecbf98fe4b86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3622400972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3622400972
Directory	/workspace/148.uart_fifo_reset/latest

Test location	/workspace/coverage/default/149.uart_fifo_reset.3098051865
Short name	T105
Test name
Test status
Simulation time	18823525461 ps
CPU time	28.83 seconds
Started	May 30 12:54:05 PM PDT 24
Finished	May 30 12:54:35 PM PDT 24
Peak memory	200256 kb
Host	smart-57fba169-cc63-462b-94b8-b2a12f952bbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3098051865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3098051865
Directory	/workspace/149.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_alert_test.1558903419
Short name	T358
Test name
Test status
Simulation time	43322465 ps
CPU time	0.55 seconds
Started	May 30 12:50:45 PM PDT 24
Finished	May 30 12:50:47 PM PDT 24
Peak memory	195768 kb
Host	smart-9c2bfd6c-aa6a-43a5-8a4d-89dac5105060
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558903419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1558903419
Directory	/workspace/15.uart_alert_test/latest

Test location	/workspace/coverage/default/15.uart_fifo_full.272532881
Short name	T680
Test name
Test status
Simulation time	216937973625 ps
CPU time	464.77 seconds
Started	May 30 12:50:52 PM PDT 24
Finished	May 30 12:58:37 PM PDT 24
Peak memory	200456 kb
Host	smart-c186fa01-dbb9-4786-a21a-a1e58c0f07f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272532881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.272532881
Directory	/workspace/15.uart_fifo_full/latest

Test location	/workspace/coverage/default/15.uart_fifo_overflow.3186866058
Short name	T1118
Test name
Test status
Simulation time	27671500915 ps
CPU time	23.4 seconds
Started	May 30 12:50:46 PM PDT 24
Finished	May 30 12:51:10 PM PDT 24
Peak memory	200220 kb
Host	smart-354a3a12-ee1b-4073-ad0a-a3946ccae928
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3186866058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3186866058
Directory	/workspace/15.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/15.uart_fifo_reset.638334178
Short name	T228
Test name
Test status
Simulation time	101351053787 ps
CPU time	32.1 seconds
Started	May 30 12:50:47 PM PDT 24
Finished	May 30 12:51:20 PM PDT 24
Peak memory	200152 kb
Host	smart-b5c62575-c663-4c9a-9350-484d899b8a71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=638334178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.638334178
Directory	/workspace/15.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_intr.1065455312
Short name	T16
Test name
Test status
Simulation time	41030371070 ps
CPU time	21.12 seconds
Started	May 30 12:50:44 PM PDT 24
Finished	May 30 12:51:06 PM PDT 24
Peak memory	200288 kb
Host	smart-c3b13b15-bf83-49ea-bb90-e30ac34de69c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065455312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1065455312
Directory	/workspace/15.uart_intr/latest

Test location	/workspace/coverage/default/15.uart_long_xfer_wo_dly.2613456931
Short name	T814
Test name
Test status
Simulation time	96626031238 ps
CPU time	420.41 seconds
Started	May 30 12:50:44 PM PDT 24
Finished	May 30 12:57:45 PM PDT 24
Peak memory	200272 kb
Host	smart-a0865b40-1d3b-417e-947e-bf7d022af174
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2613456931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2613456931
Directory	/workspace/15.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/15.uart_loopback.2164139906
Short name	T447
Test name
Test status
Simulation time	8505708951 ps
CPU time	15.9 seconds
Started	May 30 12:50:55 PM PDT 24
Finished	May 30 12:51:11 PM PDT 24
Peak memory	200232 kb
Host	smart-97cafde5-7d42-40de-b742-db9ac2dd512f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2164139906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2164139906
Directory	/workspace/15.uart_loopback/latest

Test location	/workspace/coverage/default/15.uart_noise_filter.3149953913
Short name	T782
Test name
Test status
Simulation time	193772620332 ps
CPU time	58.24 seconds
Started	May 30 12:50:56 PM PDT 24
Finished	May 30 12:51:55 PM PDT 24
Peak memory	200412 kb
Host	smart-88bbdeed-8fa6-4e87-bb46-f13c20be586a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3149953913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3149953913
Directory	/workspace/15.uart_noise_filter/latest

Test location	/workspace/coverage/default/15.uart_perf.2546242641
Short name	T426
Test name
Test status
Simulation time	16177304707 ps
CPU time	161.54 seconds
Started	May 30 12:50:45 PM PDT 24
Finished	May 30 12:53:28 PM PDT 24
Peak memory	200392 kb
Host	smart-f1aa0ad1-a21c-4d03-904b-e3204a885bc7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2546242641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2546242641
Directory	/workspace/15.uart_perf/latest

Test location	/workspace/coverage/default/15.uart_rx_oversample.3808126984
Short name	T630
Test name
Test status
Simulation time	5776833388 ps
CPU time	16.94 seconds
Started	May 30 12:50:45 PM PDT 24
Finished	May 30 12:51:02 PM PDT 24
Peak memory	200324 kb
Host	smart-74749cc8-e727-4fd0-be9d-90ce4e17d290
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3808126984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3808126984
Directory	/workspace/15.uart_rx_oversample/latest

Test location	/workspace/coverage/default/15.uart_rx_parity_err.49503571
Short name	T276
Test name
Test status
Simulation time	119438904504 ps
CPU time	95.48 seconds
Started	May 30 12:50:47 PM PDT 24
Finished	May 30 12:52:23 PM PDT 24
Peak memory	200352 kb
Host	smart-a426daee-ef8d-4182-ace6-8ee2ac1c0fff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49503571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.49503571
Directory	/workspace/15.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/15.uart_rx_start_bit_filter.2685511871
Short name	T390
Test name
Test status
Simulation time	2701818989 ps
CPU time	1.81 seconds
Started	May 30 12:50:47 PM PDT 24
Finished	May 30 12:50:50 PM PDT 24
Peak memory	196096 kb
Host	smart-c653d311-bb65-4a00-b73e-d751cb8cbb05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685511871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2685511871
Directory	/workspace/15.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/15.uart_smoke.4023099873
Short name	T503
Test name
Test status
Simulation time	136134125 ps
CPU time	0.83 seconds
Started	May 30 12:50:45 PM PDT 24
Finished	May 30 12:50:47 PM PDT 24
Peak memory	198336 kb
Host	smart-9e2758df-6b7d-435f-a7ba-c89df50333af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023099873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.4023099873
Directory	/workspace/15.uart_smoke/latest

Test location	/workspace/coverage/default/15.uart_stress_all.281246084
Short name	T1015
Test name
Test status
Simulation time	250636992196 ps
CPU time	641.86 seconds
Started	May 30 12:50:53 PM PDT 24
Finished	May 30 01:01:36 PM PDT 24
Peak memory	200348 kb
Host	smart-9473d395-e389-4390-81b0-65d96859a555
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281246084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.281246084
Directory	/workspace/15.uart_stress_all/latest

Test location	/workspace/coverage/default/15.uart_stress_all_with_rand_reset.1686860513
Short name	T122
Test name
Test status
Simulation time	183121863834 ps
CPU time	694.53 seconds
Started	May 30 12:50:55 PM PDT 24
Finished	May 30 01:02:30 PM PDT 24
Peak memory	212436 kb
Host	smart-b143ac44-145e-461d-b847-18d508380582
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686860513 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1686860513
Directory	/workspace/15.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.uart_tx_ovrd.1844222163
Short name	T376
Test name
Test status
Simulation time	729572815 ps
CPU time	2.33 seconds
Started	May 30 12:50:45 PM PDT 24
Finished	May 30 12:50:48 PM PDT 24
Peak memory	198976 kb
Host	smart-d1aab089-e6ea-40de-96be-ca3bc7ad34a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1844222163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1844222163
Directory	/workspace/15.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/15.uart_tx_rx.3010010791
Short name	T526
Test name
Test status
Simulation time	77751177859 ps
CPU time	33.56 seconds
Started	May 30 12:50:46 PM PDT 24
Finished	May 30 12:51:21 PM PDT 24
Peak memory	200136 kb
Host	smart-74139307-413d-4716-9a89-75d7680432ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3010010791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3010010791
Directory	/workspace/15.uart_tx_rx/latest

Test location	/workspace/coverage/default/150.uart_fifo_reset.3760030102
Short name	T935
Test name
Test status
Simulation time	172380988793 ps
CPU time	267.8 seconds
Started	May 30 12:54:03 PM PDT 24
Finished	May 30 12:58:33 PM PDT 24
Peak memory	200332 kb
Host	smart-4bd8ef37-936a-4994-9a29-9593bdb2e540
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760030102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3760030102
Directory	/workspace/150.uart_fifo_reset/latest

Test location	/workspace/coverage/default/151.uart_fifo_reset.537319861
Short name	T833
Test name
Test status
Simulation time	101390779635 ps
CPU time	94.82 seconds
Started	May 30 12:54:08 PM PDT 24
Finished	May 30 12:55:43 PM PDT 24
Peak memory	200284 kb
Host	smart-f4e8dedc-b40a-45d1-9e82-f9e729bdbb9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537319861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.537319861
Directory	/workspace/151.uart_fifo_reset/latest

Test location	/workspace/coverage/default/152.uart_fifo_reset.3883290016
Short name	T1004
Test name
Test status
Simulation time	39109071530 ps
CPU time	15.35 seconds
Started	May 30 12:54:01 PM PDT 24
Finished	May 30 12:54:18 PM PDT 24
Peak memory	199688 kb
Host	smart-215f1ff4-913a-41b9-a3ad-679bfa5ce546
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883290016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3883290016
Directory	/workspace/152.uart_fifo_reset/latest

Test location	/workspace/coverage/default/153.uart_fifo_reset.987605479
Short name	T145
Test name
Test status
Simulation time	36781361529 ps
CPU time	17.56 seconds
Started	May 30 12:54:04 PM PDT 24
Finished	May 30 12:54:23 PM PDT 24
Peak memory	199944 kb
Host	smart-2b05b25a-d620-4751-9d67-ea04444c6a0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=987605479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.987605479
Directory	/workspace/153.uart_fifo_reset/latest

Test location	/workspace/coverage/default/154.uart_fifo_reset.1352697105
Short name	T465
Test name
Test status
Simulation time	28563692701 ps
CPU time	47.86 seconds
Started	May 30 12:53:59 PM PDT 24
Finished	May 30 12:54:48 PM PDT 24
Peak memory	200316 kb
Host	smart-4a439cdb-ec0f-4676-b44e-62dbdb43848a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1352697105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1352697105
Directory	/workspace/154.uart_fifo_reset/latest

Test location	/workspace/coverage/default/156.uart_fifo_reset.3266423288
Short name	T887
Test name
Test status
Simulation time	26130283106 ps
CPU time	63.04 seconds
Started	May 30 12:54:02 PM PDT 24
Finished	May 30 12:55:07 PM PDT 24
Peak memory	200372 kb
Host	smart-2d72430c-cdf0-4d9c-a324-a33ccbe3c793
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3266423288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3266423288
Directory	/workspace/156.uart_fifo_reset/latest

Test location	/workspace/coverage/default/157.uart_fifo_reset.159292471
Short name	T866
Test name
Test status
Simulation time	161506970209 ps
CPU time	45.44 seconds
Started	May 30 12:54:03 PM PDT 24
Finished	May 30 12:54:50 PM PDT 24
Peak memory	200404 kb
Host	smart-dec401c2-756b-434a-b9cc-661b8fc63e34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159292471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.159292471
Directory	/workspace/157.uart_fifo_reset/latest

Test location	/workspace/coverage/default/158.uart_fifo_reset.2843172021
Short name	T647
Test name
Test status
Simulation time	28280109291 ps
CPU time	12.64 seconds
Started	May 30 12:54:00 PM PDT 24
Finished	May 30 12:54:15 PM PDT 24
Peak memory	200424 kb
Host	smart-1a66a19d-34d2-4042-87d7-3765f381886e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2843172021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2843172021
Directory	/workspace/158.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_alert_test.3345479519
Short name	T444
Test name
Test status
Simulation time	22477498 ps
CPU time	0.55 seconds
Started	May 30 12:50:48 PM PDT 24
Finished	May 30 12:50:49 PM PDT 24
Peak memory	194728 kb
Host	smart-87829ded-d11b-4630-a310-9dfda5d11535
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345479519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3345479519
Directory	/workspace/16.uart_alert_test/latest

Test location	/workspace/coverage/default/16.uart_fifo_overflow.2134754693
Short name	T1036
Test name
Test status
Simulation time	186658501045 ps
CPU time	196.82 seconds
Started	May 30 12:50:44 PM PDT 24
Finished	May 30 12:54:02 PM PDT 24
Peak memory	200224 kb
Host	smart-61d196d5-ed9b-454f-83c6-5440efddd38e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2134754693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2134754693
Directory	/workspace/16.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/16.uart_fifo_reset.2971710256
Short name	T653
Test name
Test status
Simulation time	113704242423 ps
CPU time	78.42 seconds
Started	May 30 12:50:45 PM PDT 24
Finished	May 30 12:52:05 PM PDT 24
Peak memory	200216 kb
Host	smart-83b86208-3511-4702-9428-69c917fe5b0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2971710256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2971710256
Directory	/workspace/16.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_intr.2775438706
Short name	T948
Test name
Test status
Simulation time	19557685606 ps
CPU time	39.06 seconds
Started	May 30 12:50:45 PM PDT 24
Finished	May 30 12:51:25 PM PDT 24
Peak memory	200260 kb
Host	smart-7596c650-6faf-426e-9682-230a56b5b563
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775438706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2775438706
Directory	/workspace/16.uart_intr/latest

Test location	/workspace/coverage/default/16.uart_long_xfer_wo_dly.621266324
Short name	T454
Test name
Test status
Simulation time	222151167715 ps
CPU time	1482.23 seconds
Started	May 30 12:50:48 PM PDT 24
Finished	May 30 01:15:31 PM PDT 24
Peak memory	200404 kb
Host	smart-c817384a-7b4c-49a4-bace-54b637e9052b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=621266324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.621266324
Directory	/workspace/16.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/16.uart_loopback.1756152732
Short name	T336
Test name
Test status
Simulation time	12277596056 ps
CPU time	14.26 seconds
Started	May 30 12:50:47 PM PDT 24
Finished	May 30 12:51:02 PM PDT 24
Peak memory	200352 kb
Host	smart-14eea4f7-dfb6-4355-8908-3f180d20900b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1756152732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1756152732
Directory	/workspace/16.uart_loopback/latest

Test location	/workspace/coverage/default/16.uart_noise_filter.1021380191
Short name	T918
Test name
Test status
Simulation time	60992585508 ps
CPU time	105.93 seconds
Started	May 30 12:50:52 PM PDT 24
Finished	May 30 12:52:38 PM PDT 24
Peak memory	200488 kb
Host	smart-d048501b-a2a2-43cd-bd51-47854e9275ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1021380191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1021380191
Directory	/workspace/16.uart_noise_filter/latest

Test location	/workspace/coverage/default/16.uart_perf.70654137
Short name	T292
Test name
Test status
Simulation time	18021933892 ps
CPU time	976.92 seconds
Started	May 30 12:50:47 PM PDT 24
Finished	May 30 01:07:05 PM PDT 24
Peak memory	200328 kb
Host	smart-7bfdf2e2-0db6-4354-a0a3-65414099a4cb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=70654137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.70654137
Directory	/workspace/16.uart_perf/latest

Test location	/workspace/coverage/default/16.uart_rx_oversample.3984401714
Short name	T547
Test name
Test status
Simulation time	2105758257 ps
CPU time	6.75 seconds
Started	May 30 12:50:55 PM PDT 24
Finished	May 30 12:51:02 PM PDT 24
Peak memory	199576 kb
Host	smart-b3a1bc3c-222d-415a-a32c-69d1af96645b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3984401714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3984401714
Directory	/workspace/16.uart_rx_oversample/latest

Test location	/workspace/coverage/default/16.uart_rx_parity_err.3769719916
Short name	T519
Test name
Test status
Simulation time	16651553819 ps
CPU time	30.31 seconds
Started	May 30 12:50:45 PM PDT 24
Finished	May 30 12:51:17 PM PDT 24
Peak memory	200292 kb
Host	smart-4afb7c3d-12d8-475e-ba76-baa7de566c28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3769719916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3769719916
Directory	/workspace/16.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/16.uart_rx_start_bit_filter.356855710
Short name	T52
Test name
Test status
Simulation time	1241821492 ps
CPU time	2.81 seconds
Started	May 30 12:50:50 PM PDT 24
Finished	May 30 12:50:54 PM PDT 24
Peak memory	195648 kb
Host	smart-e6f23a13-8bb2-4f4f-997f-e1ce81c9b246
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=356855710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.356855710
Directory	/workspace/16.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/16.uart_smoke.357921928
Short name	T485
Test name
Test status
Simulation time	126177596 ps
CPU time	0.93 seconds
Started	May 30 12:50:55 PM PDT 24
Finished	May 30 12:50:57 PM PDT 24
Peak memory	197324 kb
Host	smart-74ae6c46-8c56-4cd5-bea3-867a54fcd3be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357921928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.357921928
Directory	/workspace/16.uart_smoke/latest

Test location	/workspace/coverage/default/16.uart_stress_all.1547068245
Short name	T309
Test name
Test status
Simulation time	242370505232 ps
CPU time	2282.28 seconds
Started	May 30 12:50:48 PM PDT 24
Finished	May 30 01:28:51 PM PDT 24
Peak memory	208736 kb
Host	smart-92187a10-c8a8-4caf-8d74-8ffbe2141e52
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547068245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1547068245
Directory	/workspace/16.uart_stress_all/latest

Test location	/workspace/coverage/default/16.uart_stress_all_with_rand_reset.4268028944
Short name	T928
Test name
Test status
Simulation time	27857910683 ps
CPU time	276.08 seconds
Started	May 30 12:50:46 PM PDT 24
Finished	May 30 12:55:23 PM PDT 24
Peak memory	212636 kb
Host	smart-f9446b59-5329-42a9-86a4-a2018833c4e4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268028944 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.4268028944
Directory	/workspace/16.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.uart_tx_ovrd.3157916348
Short name	T534
Test name
Test status
Simulation time	577710468 ps
CPU time	1.86 seconds
Started	May 30 12:50:50 PM PDT 24
Finished	May 30 12:50:53 PM PDT 24
Peak memory	199796 kb
Host	smart-d5a732f6-2677-4302-a5d2-79c9e76f1bec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3157916348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3157916348
Directory	/workspace/16.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/16.uart_tx_rx.3541833512
Short name	T846
Test name
Test status
Simulation time	68484092256 ps
CPU time	297.15 seconds
Started	May 30 12:50:45 PM PDT 24
Finished	May 30 12:55:44 PM PDT 24
Peak memory	200404 kb
Host	smart-62c7337b-6f1f-4574-9a9d-52b7152c106d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3541833512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3541833512
Directory	/workspace/16.uart_tx_rx/latest

Test location	/workspace/coverage/default/160.uart_fifo_reset.3850129489
Short name	T578
Test name
Test status
Simulation time	314097162044 ps
CPU time	34.02 seconds
Started	May 30 12:53:58 PM PDT 24
Finished	May 30 12:54:33 PM PDT 24
Peak memory	200252 kb
Host	smart-7c44853e-f984-4086-ac6c-129839de63f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3850129489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3850129489
Directory	/workspace/160.uart_fifo_reset/latest

Test location	/workspace/coverage/default/161.uart_fifo_reset.1581607776
Short name	T811
Test name
Test status
Simulation time	32097893180 ps
CPU time	41.09 seconds
Started	May 30 12:54:02 PM PDT 24
Finished	May 30 12:54:44 PM PDT 24
Peak memory	200304 kb
Host	smart-a4229c76-fbe6-4334-bc4d-722031a7cb7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1581607776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1581607776
Directory	/workspace/161.uart_fifo_reset/latest

Test location	/workspace/coverage/default/162.uart_fifo_reset.3267480642
Short name	T6
Test name
Test status
Simulation time	14472353208 ps
CPU time	7.37 seconds
Started	May 30 12:54:02 PM PDT 24
Finished	May 30 12:54:11 PM PDT 24
Peak memory	200352 kb
Host	smart-94f11abf-9132-44a2-94c8-99901a4ec4a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3267480642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3267480642
Directory	/workspace/162.uart_fifo_reset/latest

Test location	/workspace/coverage/default/163.uart_fifo_reset.1790067737
Short name	T627
Test name
Test status
Simulation time	176258019760 ps
CPU time	266.25 seconds
Started	May 30 12:54:04 PM PDT 24
Finished	May 30 12:58:32 PM PDT 24
Peak memory	200248 kb
Host	smart-4f75961b-6acc-448d-87ae-cb2380c6f7aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1790067737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1790067737
Directory	/workspace/163.uart_fifo_reset/latest

Test location	/workspace/coverage/default/164.uart_fifo_reset.2481830985
Short name	T349
Test name
Test status
Simulation time	14219777178 ps
CPU time	6.66 seconds
Started	May 30 12:54:07 PM PDT 24
Finished	May 30 12:54:15 PM PDT 24
Peak memory	200148 kb
Host	smart-5b95832e-9d8b-46f2-b32f-9cb67add6c18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2481830985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2481830985
Directory	/workspace/164.uart_fifo_reset/latest

Test location	/workspace/coverage/default/165.uart_fifo_reset.487556657
Short name	T295
Test name
Test status
Simulation time	126218511004 ps
CPU time	262.68 seconds
Started	May 30 12:54:01 PM PDT 24
Finished	May 30 12:58:25 PM PDT 24
Peak memory	200368 kb
Host	smart-003017a8-9271-41d7-bc4d-a137bd1913c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=487556657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.487556657
Directory	/workspace/165.uart_fifo_reset/latest

Test location	/workspace/coverage/default/166.uart_fifo_reset.1727425214
Short name	T212
Test name
Test status
Simulation time	76519470147 ps
CPU time	33.19 seconds
Started	May 30 12:54:01 PM PDT 24
Finished	May 30 12:54:36 PM PDT 24
Peak memory	200396 kb
Host	smart-818514c3-1f96-42fc-b5a2-36957da2b515
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1727425214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1727425214
Directory	/workspace/166.uart_fifo_reset/latest

Test location	/workspace/coverage/default/167.uart_fifo_reset.1934132227
Short name	T631
Test name
Test status
Simulation time	101443591525 ps
CPU time	41.64 seconds
Started	May 30 12:54:04 PM PDT 24
Finished	May 30 12:54:47 PM PDT 24
Peak memory	199860 kb
Host	smart-7dec35e3-a949-4a1f-b931-7f7b2e53f6bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1934132227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1934132227
Directory	/workspace/167.uart_fifo_reset/latest

Test location	/workspace/coverage/default/168.uart_fifo_reset.3933245241
Short name	T804
Test name
Test status
Simulation time	11726935245 ps
CPU time	19.78 seconds
Started	May 30 12:54:01 PM PDT 24
Finished	May 30 12:54:22 PM PDT 24
Peak memory	200368 kb
Host	smart-d9a4c8e8-9d56-4a5a-a364-46b90382a6ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3933245241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3933245241
Directory	/workspace/168.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_alert_test.350080689
Short name	T1140
Test name
Test status
Simulation time	21519982 ps
CPU time	0.55 seconds
Started	May 30 12:50:59 PM PDT 24
Finished	May 30 12:51:01 PM PDT 24
Peak memory	195660 kb
Host	smart-de0f6847-c56c-4096-86e3-d221bd106f5a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350080689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.350080689
Directory	/workspace/17.uart_alert_test/latest

Test location	/workspace/coverage/default/17.uart_fifo_full.1798528910
Short name	T304
Test name
Test status
Simulation time	248480495102 ps
CPU time	410.12 seconds
Started	May 30 12:50:45 PM PDT 24
Finished	May 30 12:57:37 PM PDT 24
Peak memory	200288 kb
Host	smart-e3466d7d-a347-4a11-8c2b-cdfc4fee17c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798528910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1798528910
Directory	/workspace/17.uart_fifo_full/latest

Test location	/workspace/coverage/default/17.uart_fifo_overflow.137459687
Short name	T561
Test name
Test status
Simulation time	86217864891 ps
CPU time	35.66 seconds
Started	May 30 12:51:00 PM PDT 24
Finished	May 30 12:51:36 PM PDT 24
Peak memory	200376 kb
Host	smart-2da2617d-f719-4120-9b0d-12e1f3ce56a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=137459687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.137459687
Directory	/workspace/17.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/17.uart_fifo_reset.2739906329
Short name	T996
Test name
Test status
Simulation time	70951011354 ps
CPU time	115.13 seconds
Started	May 30 12:51:01 PM PDT 24
Finished	May 30 12:52:57 PM PDT 24
Peak memory	200332 kb
Host	smart-ed8e4156-5750-4667-b129-9a311f781fa0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2739906329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2739906329
Directory	/workspace/17.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_intr.1838362359
Short name	T1100
Test name
Test status
Simulation time	265632094993 ps
CPU time	432.2 seconds
Started	May 30 12:50:59 PM PDT 24
Finished	May 30 12:58:12 PM PDT 24
Peak memory	199668 kb
Host	smart-82b6e690-cc1a-4c8f-8f44-8f56c2276366
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838362359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1838362359
Directory	/workspace/17.uart_intr/latest

Test location	/workspace/coverage/default/17.uart_long_xfer_wo_dly.3659615135
Short name	T730
Test name
Test status
Simulation time	122209024538 ps
CPU time	1142.66 seconds
Started	May 30 12:51:00 PM PDT 24
Finished	May 30 01:10:04 PM PDT 24
Peak memory	200404 kb
Host	smart-ffdc28b8-7d8e-4d5e-b1b7-2335ebe13098
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3659615135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3659615135
Directory	/workspace/17.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/17.uart_loopback.1591173747
Short name	T848
Test name
Test status
Simulation time	5827262964 ps
CPU time	18.65 seconds
Started	May 30 12:51:00 PM PDT 24
Finished	May 30 12:51:19 PM PDT 24
Peak memory	199528 kb
Host	smart-c5f4b52f-9bfb-4088-9716-a59ca5d0c47c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1591173747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1591173747
Directory	/workspace/17.uart_loopback/latest

Test location	/workspace/coverage/default/17.uart_noise_filter.2635909985
Short name	T482
Test name
Test status
Simulation time	55353576699 ps
CPU time	19.27 seconds
Started	May 30 12:50:58 PM PDT 24
Finished	May 30 12:51:18 PM PDT 24
Peak memory	200420 kb
Host	smart-ef12d46d-9173-4b08-935f-0f0b72b8f7a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2635909985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2635909985
Directory	/workspace/17.uart_noise_filter/latest

Test location	/workspace/coverage/default/17.uart_perf.756952880
Short name	T1069
Test name
Test status
Simulation time	21980160084 ps
CPU time	1198.09 seconds
Started	May 30 12:51:01 PM PDT 24
Finished	May 30 01:11:00 PM PDT 24
Peak memory	200264 kb
Host	smart-c25825f8-aeac-44b8-aa82-47aeb9f61d87
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=756952880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.756952880
Directory	/workspace/17.uart_perf/latest

Test location	/workspace/coverage/default/17.uart_rx_oversample.1713587713
Short name	T919
Test name
Test status
Simulation time	7004068302 ps
CPU time	29.64 seconds
Started	May 30 12:50:59 PM PDT 24
Finished	May 30 12:51:30 PM PDT 24
Peak memory	199600 kb
Host	smart-3320f535-32c9-4981-97af-fa95d734dd18
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1713587713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1713587713
Directory	/workspace/17.uart_rx_oversample/latest

Test location	/workspace/coverage/default/17.uart_rx_parity_err.1204329810
Short name	T439
Test name
Test status
Simulation time	66103403342 ps
CPU time	60.09 seconds
Started	May 30 12:51:02 PM PDT 24
Finished	May 30 12:52:03 PM PDT 24
Peak memory	200352 kb
Host	smart-8d3d4b7a-2e02-4b77-9731-8fe84590a380
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204329810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1204329810
Directory	/workspace/17.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/17.uart_rx_start_bit_filter.3912819304
Short name	T937
Test name
Test status
Simulation time	4314100775 ps
CPU time	0.97 seconds
Started	May 30 12:51:02 PM PDT 24
Finished	May 30 12:51:04 PM PDT 24
Peak memory	196648 kb
Host	smart-7235df2e-7651-4477-952f-d4d5166eedac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3912819304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3912819304
Directory	/workspace/17.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/17.uart_smoke.1561377410
Short name	T715
Test name
Test status
Simulation time	649350565 ps
CPU time	3.48 seconds
Started	May 30 12:50:45 PM PDT 24
Finished	May 30 12:50:50 PM PDT 24
Peak memory	198640 kb
Host	smart-11ecdedf-4d45-4d80-9fc2-cbee5a9c58e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1561377410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1561377410
Directory	/workspace/17.uart_smoke/latest

Test location	/workspace/coverage/default/17.uart_stress_all.531869863
Short name	T249
Test name
Test status
Simulation time	489310370286 ps
CPU time	201 seconds
Started	May 30 12:50:59 PM PDT 24
Finished	May 30 12:54:21 PM PDT 24
Peak memory	201084 kb
Host	smart-6361574c-a6c0-4fe8-8ea5-7eff587b557b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531869863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.531869863
Directory	/workspace/17.uart_stress_all/latest

Test location	/workspace/coverage/default/17.uart_stress_all_with_rand_reset.2657885684
Short name	T77
Test name
Test status
Simulation time	25681691493 ps
CPU time	706.61 seconds
Started	May 30 12:51:00 PM PDT 24
Finished	May 30 01:02:48 PM PDT 24
Peak memory	208896 kb
Host	smart-81ac3323-9f10-42c2-b740-d6a7fb2eebd4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657885684 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2657885684
Directory	/workspace/17.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.uart_tx_ovrd.1435673102
Short name	T7
Test name
Test status
Simulation time	878275378 ps
CPU time	2.98 seconds
Started	May 30 12:50:59 PM PDT 24
Finished	May 30 12:51:03 PM PDT 24
Peak memory	200212 kb
Host	smart-066321b3-c107-444e-8233-c30d49271a31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1435673102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1435673102
Directory	/workspace/17.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/17.uart_tx_rx.2119444488
Short name	T651
Test name
Test status
Simulation time	9786776678 ps
CPU time	16.77 seconds
Started	May 30 12:50:48 PM PDT 24
Finished	May 30 12:51:06 PM PDT 24
Peak memory	200136 kb
Host	smart-fa269d7f-e938-4d62-9607-6764d36e2bae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2119444488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2119444488
Directory	/workspace/17.uart_tx_rx/latest

Test location	/workspace/coverage/default/171.uart_fifo_reset.2715709637
Short name	T720
Test name
Test status
Simulation time	60209059839 ps
CPU time	17.13 seconds
Started	May 30 12:54:07 PM PDT 24
Finished	May 30 12:54:25 PM PDT 24
Peak memory	200208 kb
Host	smart-cce8c875-797e-4821-b3cf-fd2948c327ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2715709637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2715709637
Directory	/workspace/171.uart_fifo_reset/latest

Test location	/workspace/coverage/default/173.uart_fifo_reset.2605610856
Short name	T177
Test name
Test status
Simulation time	74856734051 ps
CPU time	23.25 seconds
Started	May 30 12:54:02 PM PDT 24
Finished	May 30 12:54:26 PM PDT 24
Peak memory	200412 kb
Host	smart-cb7387f3-bcbc-41d0-9b87-bbc94a3ef88f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2605610856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2605610856
Directory	/workspace/173.uart_fifo_reset/latest

Test location	/workspace/coverage/default/174.uart_fifo_reset.457802637
Short name	T227
Test name
Test status
Simulation time	92199264957 ps
CPU time	46.98 seconds
Started	May 30 12:54:00 PM PDT 24
Finished	May 30 12:54:48 PM PDT 24
Peak memory	200400 kb
Host	smart-fa822197-cb34-4750-83f8-b3dd5f3f3f8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=457802637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.457802637
Directory	/workspace/174.uart_fifo_reset/latest

Test location	/workspace/coverage/default/176.uart_fifo_reset.1600553418
Short name	T883
Test name
Test status
Simulation time	100338507119 ps
CPU time	39.09 seconds
Started	May 30 12:54:02 PM PDT 24
Finished	May 30 12:54:42 PM PDT 24
Peak memory	200312 kb
Host	smart-2b6dbb52-feae-4183-b13a-e57820832c9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1600553418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1600553418
Directory	/workspace/176.uart_fifo_reset/latest

Test location	/workspace/coverage/default/177.uart_fifo_reset.3896802521
Short name	T754
Test name
Test status
Simulation time	146047870899 ps
CPU time	117.22 seconds
Started	May 30 12:54:05 PM PDT 24
Finished	May 30 12:56:04 PM PDT 24
Peak memory	200124 kb
Host	smart-d9fd4319-3ede-4ead-a816-7e9adf1a9711
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896802521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3896802521
Directory	/workspace/177.uart_fifo_reset/latest

Test location	/workspace/coverage/default/178.uart_fifo_reset.484961340
Short name	T1116
Test name
Test status
Simulation time	176833500531 ps
CPU time	83.81 seconds
Started	May 30 12:54:03 PM PDT 24
Finished	May 30 12:55:29 PM PDT 24
Peak memory	200260 kb
Host	smart-f6fa8eea-e0f7-48e9-bf02-83a37c8b18a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=484961340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.484961340
Directory	/workspace/178.uart_fifo_reset/latest

Test location	/workspace/coverage/default/179.uart_fifo_reset.1793912852
Short name	T1080
Test name
Test status
Simulation time	92581419808 ps
CPU time	152.01 seconds
Started	May 30 12:54:04 PM PDT 24
Finished	May 30 12:56:37 PM PDT 24
Peak memory	200244 kb
Host	smart-cca4bca4-2cf6-4ce8-b282-84b435992f38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1793912852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1793912852
Directory	/workspace/179.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_alert_test.1814685809
Short name	T1027
Test name
Test status
Simulation time	34056680 ps
CPU time	0.56 seconds
Started	May 30 12:51:01 PM PDT 24
Finished	May 30 12:51:02 PM PDT 24
Peak memory	195756 kb
Host	smart-8a8f5e03-ba8b-48aa-bc54-60fa80c1fafe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814685809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1814685809
Directory	/workspace/18.uart_alert_test/latest

Test location	/workspace/coverage/default/18.uart_fifo_full.904661642
Short name	T43
Test name
Test status
Simulation time	87498953294 ps
CPU time	223.89 seconds
Started	May 30 12:51:02 PM PDT 24
Finished	May 30 12:54:47 PM PDT 24
Peak memory	200320 kb
Host	smart-b35c62e4-4ba3-47e9-a224-bcc2bdfd3fdf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=904661642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.904661642
Directory	/workspace/18.uart_fifo_full/latest

Test location	/workspace/coverage/default/18.uart_fifo_overflow.974338584
Short name	T409
Test name
Test status
Simulation time	36384899106 ps
CPU time	39.45 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 12:51:44 PM PDT 24
Peak memory	200400 kb
Host	smart-875ab59f-2492-491b-9374-c9452b5878ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=974338584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.974338584
Directory	/workspace/18.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/18.uart_intr.3186018567
Short name	T1025
Test name
Test status
Simulation time	18168130143 ps
CPU time	16.26 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 12:51:20 PM PDT 24
Peak memory	200244 kb
Host	smart-b80ec59e-ce52-481f-b94d-937fde4f9800
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186018567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3186018567
Directory	/workspace/18.uart_intr/latest

Test location	/workspace/coverage/default/18.uart_long_xfer_wo_dly.1196972174
Short name	T654
Test name
Test status
Simulation time	84553574752 ps
CPU time	298.63 seconds
Started	May 30 12:51:05 PM PDT 24
Finished	May 30 12:56:04 PM PDT 24
Peak memory	200336 kb
Host	smart-ef576529-ffbb-42bd-9dd3-9b14987ff84d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1196972174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1196972174
Directory	/workspace/18.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/18.uart_loopback.2655485094
Short name	T662
Test name
Test status
Simulation time	4227335078 ps
CPU time	8.71 seconds
Started	May 30 12:51:02 PM PDT 24
Finished	May 30 12:51:11 PM PDT 24
Peak memory	198844 kb
Host	smart-38409e7a-afa1-4221-b0f6-84e0e1540dee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2655485094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2655485094
Directory	/workspace/18.uart_loopback/latest

Test location	/workspace/coverage/default/18.uart_noise_filter.3209645190
Short name	T1038
Test name
Test status
Simulation time	63774186041 ps
CPU time	26.92 seconds
Started	May 30 12:51:02 PM PDT 24
Finished	May 30 12:51:30 PM PDT 24
Peak memory	200528 kb
Host	smart-a6e85289-5bb1-4ae9-bae6-42dfa6261ef0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3209645190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3209645190
Directory	/workspace/18.uart_noise_filter/latest

Test location	/workspace/coverage/default/18.uart_perf.3686363275
Short name	T1182
Test name
Test status
Simulation time	14150246315 ps
CPU time	189.84 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 12:54:14 PM PDT 24
Peak memory	200300 kb
Host	smart-33d9f1e0-42ab-445b-9b81-dc96833ad395
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3686363275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3686363275
Directory	/workspace/18.uart_perf/latest

Test location	/workspace/coverage/default/18.uart_rx_oversample.263683188
Short name	T381
Test name
Test status
Simulation time	3584268594 ps
CPU time	26.6 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 12:51:30 PM PDT 24
Peak memory	198464 kb
Host	smart-d524ea78-169e-4930-89e8-bb4ed1577bd9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=263683188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.263683188
Directory	/workspace/18.uart_rx_oversample/latest

Test location	/workspace/coverage/default/18.uart_rx_start_bit_filter.2327001829
Short name	T663
Test name
Test status
Simulation time	3111449004 ps
CPU time	0.89 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 12:51:05 PM PDT 24
Peak memory	196060 kb
Host	smart-b73672b5-299a-4ff0-904f-1a860109b0cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2327001829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2327001829
Directory	/workspace/18.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/18.uart_smoke.1274355897
Short name	T284
Test name
Test status
Simulation time	6257282522 ps
CPU time	24.23 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 12:51:28 PM PDT 24
Peak memory	200116 kb
Host	smart-0ed57975-d1a9-4db6-bd12-fea599d1014a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1274355897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1274355897
Directory	/workspace/18.uart_smoke/latest

Test location	/workspace/coverage/default/18.uart_stress_all.2618463984
Short name	T200
Test name
Test status
Simulation time	38542830686 ps
CPU time	67.15 seconds
Started	May 30 12:51:02 PM PDT 24
Finished	May 30 12:52:10 PM PDT 24
Peak memory	200348 kb
Host	smart-77c4062e-2aae-4c10-9f74-72c988fe91b7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618463984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2618463984
Directory	/workspace/18.uart_stress_all/latest

Test location	/workspace/coverage/default/18.uart_stress_all_with_rand_reset.1773614803
Short name	T333
Test name
Test status
Simulation time	97781940876 ps
CPU time	523.02 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 12:59:47 PM PDT 24
Peak memory	208604 kb
Host	smart-a87c14a6-4451-4160-85fa-3628338d063a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773614803 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1773614803
Directory	/workspace/18.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.uart_tx_ovrd.2051060449
Short name	T1178
Test name
Test status
Simulation time	3512168387 ps
CPU time	2.58 seconds
Started	May 30 12:51:08 PM PDT 24
Finished	May 30 12:51:11 PM PDT 24
Peak memory	200388 kb
Host	smart-dc10d52f-357e-4198-8005-4a3368f38c01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2051060449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2051060449
Directory	/workspace/18.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/18.uart_tx_rx.2142144627
Short name	T1019
Test name
Test status
Simulation time	12219425167 ps
CPU time	22.54 seconds
Started	May 30 12:51:00 PM PDT 24
Finished	May 30 12:51:23 PM PDT 24
Peak memory	200328 kb
Host	smart-538ec298-60d8-4f7e-a76c-b5944cf67fc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2142144627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2142144627
Directory	/workspace/18.uart_tx_rx/latest

Test location	/workspace/coverage/default/180.uart_fifo_reset.3549981018
Short name	T47
Test name
Test status
Simulation time	78692608033 ps
CPU time	86.13 seconds
Started	May 30 12:54:04 PM PDT 24
Finished	May 30 12:55:32 PM PDT 24
Peak memory	200404 kb
Host	smart-ab497147-c81d-4c75-8d90-582a8a32f62f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3549981018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3549981018
Directory	/workspace/180.uart_fifo_reset/latest

Test location	/workspace/coverage/default/181.uart_fifo_reset.1809492432
Short name	T860
Test name
Test status
Simulation time	59977599374 ps
CPU time	22.54 seconds
Started	May 30 12:53:59 PM PDT 24
Finished	May 30 12:54:22 PM PDT 24
Peak memory	200224 kb
Host	smart-6b5bbd10-f3a1-4d9d-9a00-1da68f4fd03e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809492432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1809492432
Directory	/workspace/181.uart_fifo_reset/latest

Test location	/workspace/coverage/default/182.uart_fifo_reset.2768602267
Short name	T634
Test name
Test status
Simulation time	52965428320 ps
CPU time	19.26 seconds
Started	May 30 12:54:04 PM PDT 24
Finished	May 30 12:54:25 PM PDT 24
Peak memory	200332 kb
Host	smart-f575c155-db35-4eb6-ae59-a5355fa0e132
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2768602267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2768602267
Directory	/workspace/182.uart_fifo_reset/latest

Test location	/workspace/coverage/default/183.uart_fifo_reset.3911790978
Short name	T229
Test name
Test status
Simulation time	39594807427 ps
CPU time	16.69 seconds
Started	May 30 12:54:03 PM PDT 24
Finished	May 30 12:54:22 PM PDT 24
Peak memory	200320 kb
Host	smart-7fb07e4a-0971-49ef-a816-a94340852f1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3911790978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3911790978
Directory	/workspace/183.uart_fifo_reset/latest

Test location	/workspace/coverage/default/184.uart_fifo_reset.2679556791
Short name	T345
Test name
Test status
Simulation time	37559943922 ps
CPU time	63.18 seconds
Started	May 30 12:54:03 PM PDT 24
Finished	May 30 12:55:08 PM PDT 24
Peak memory	200388 kb
Host	smart-9c1b45dc-3a71-4f28-b4df-2c2059b3d219
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2679556791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2679556791
Directory	/workspace/184.uart_fifo_reset/latest

Test location	/workspace/coverage/default/185.uart_fifo_reset.2597026883
Short name	T286
Test name
Test status
Simulation time	56032493296 ps
CPU time	28.9 seconds
Started	May 30 12:54:05 PM PDT 24
Finished	May 30 12:54:35 PM PDT 24
Peak memory	200344 kb
Host	smart-c0554812-d8b8-4396-b1da-0b5f52c10b06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597026883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2597026883
Directory	/workspace/185.uart_fifo_reset/latest

Test location	/workspace/coverage/default/186.uart_fifo_reset.1480719108
Short name	T103
Test name
Test status
Simulation time	45527757998 ps
CPU time	21.2 seconds
Started	May 30 12:54:03 PM PDT 24
Finished	May 30 12:54:26 PM PDT 24
Peak memory	200404 kb
Host	smart-4548c43b-64ce-4117-8ac3-e5ab92713df7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1480719108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1480719108
Directory	/workspace/186.uart_fifo_reset/latest

Test location	/workspace/coverage/default/187.uart_fifo_reset.1217835605
Short name	T686
Test name
Test status
Simulation time	78738795575 ps
CPU time	38.34 seconds
Started	May 30 12:54:02 PM PDT 24
Finished	May 30 12:54:42 PM PDT 24
Peak memory	200340 kb
Host	smart-bebbe05a-47de-4992-814c-d74c12aa8cc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217835605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1217835605
Directory	/workspace/187.uart_fifo_reset/latest

Test location	/workspace/coverage/default/188.uart_fifo_reset.3584734510
Short name	T1107
Test name
Test status
Simulation time	47474005462 ps
CPU time	20.92 seconds
Started	May 30 12:54:03 PM PDT 24
Finished	May 30 12:54:26 PM PDT 24
Peak memory	200392 kb
Host	smart-228cf0eb-6c9e-4258-9852-995be79d0c0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584734510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3584734510
Directory	/workspace/188.uart_fifo_reset/latest

Test location	/workspace/coverage/default/189.uart_fifo_reset.3957872654
Short name	T222
Test name
Test status
Simulation time	41224496031 ps
CPU time	33.97 seconds
Started	May 30 12:54:02 PM PDT 24
Finished	May 30 12:54:37 PM PDT 24
Peak memory	200396 kb
Host	smart-4389e726-0c51-4c58-8955-c19bfd291046
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3957872654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3957872654
Directory	/workspace/189.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_alert_test.1269986204
Short name	T1155
Test name
Test status
Simulation time	28905780 ps
CPU time	0.55 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 12:51:05 PM PDT 24
Peak memory	195752 kb
Host	smart-ac476d7f-bf9a-4aed-94b1-bf843c63b842
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269986204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1269986204
Directory	/workspace/19.uart_alert_test/latest

Test location	/workspace/coverage/default/19.uart_fifo_full.3680188713
Short name	T132
Test name
Test status
Simulation time	62616305334 ps
CPU time	48.93 seconds
Started	May 30 12:51:02 PM PDT 24
Finished	May 30 12:51:52 PM PDT 24
Peak memory	200328 kb
Host	smart-0b975551-e804-4a96-8661-29006bad44ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3680188713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3680188713
Directory	/workspace/19.uart_fifo_full/latest

Test location	/workspace/coverage/default/19.uart_fifo_overflow.982553611
Short name	T394
Test name
Test status
Simulation time	78816106339 ps
CPU time	112.53 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 12:52:57 PM PDT 24
Peak memory	200020 kb
Host	smart-f4ecbdb8-7dd6-44cc-a330-5886cc8648d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=982553611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.982553611
Directory	/workspace/19.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/19.uart_fifo_reset.1205369318
Short name	T722
Test name
Test status
Simulation time	15667068682 ps
CPU time	25.19 seconds
Started	May 30 12:51:05 PM PDT 24
Finished	May 30 12:51:31 PM PDT 24
Peak memory	200368 kb
Host	smart-04da1346-06c5-47ba-ae1b-1abd58f93471
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1205369318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1205369318
Directory	/workspace/19.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_intr.425425308
Short name	T518
Test name
Test status
Simulation time	29206446003 ps
CPU time	15.8 seconds
Started	May 30 12:51:04 PM PDT 24
Finished	May 30 12:51:20 PM PDT 24
Peak memory	200368 kb
Host	smart-9f8a29cc-57c8-4a6d-9737-264f3c77f71d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425425308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.425425308
Directory	/workspace/19.uart_intr/latest

Test location	/workspace/coverage/default/19.uart_long_xfer_wo_dly.510565827
Short name	T38
Test name
Test status
Simulation time	258887201660 ps
CPU time	267.93 seconds
Started	May 30 12:51:04 PM PDT 24
Finished	May 30 12:55:33 PM PDT 24
Peak memory	200312 kb
Host	smart-3299cec6-6fcd-4459-8f5f-0b9bbc063186
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=510565827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.510565827
Directory	/workspace/19.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/19.uart_loopback.4105670978
Short name	T597
Test name
Test status
Simulation time	7702444484 ps
CPU time	17.7 seconds
Started	May 30 12:51:04 PM PDT 24
Finished	May 30 12:51:23 PM PDT 24
Peak memory	200208 kb
Host	smart-6fecc855-4a15-48a0-955f-7b05f417426b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4105670978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.4105670978
Directory	/workspace/19.uart_loopback/latest

Test location	/workspace/coverage/default/19.uart_noise_filter.1932143042
Short name	T626
Test name
Test status
Simulation time	31923263637 ps
CPU time	55.12 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 12:51:59 PM PDT 24
Peak memory	197472 kb
Host	smart-a6346aaf-a168-4971-9e1b-c8f327db5bff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932143042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1932143042
Directory	/workspace/19.uart_noise_filter/latest

Test location	/workspace/coverage/default/19.uart_perf.3217087745
Short name	T408
Test name
Test status
Simulation time	11999081304 ps
CPU time	127.52 seconds
Started	May 30 12:51:04 PM PDT 24
Finished	May 30 12:53:12 PM PDT 24
Peak memory	200392 kb
Host	smart-99a91f8c-d09a-4d6d-bc30-f77f25e4570b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3217087745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3217087745
Directory	/workspace/19.uart_perf/latest

Test location	/workspace/coverage/default/19.uart_rx_oversample.1866524575
Short name	T450
Test name
Test status
Simulation time	5225376241 ps
CPU time	10.71 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 12:51:15 PM PDT 24
Peak memory	198504 kb
Host	smart-6ab9f172-8db7-46aa-8660-4d251b1617be
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1866524575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1866524575
Directory	/workspace/19.uart_rx_oversample/latest

Test location	/workspace/coverage/default/19.uart_rx_parity_err.3554041206
Short name	T153
Test name
Test status
Simulation time	44237317556 ps
CPU time	19.97 seconds
Started	May 30 12:51:02 PM PDT 24
Finished	May 30 12:51:23 PM PDT 24
Peak memory	200320 kb
Host	smart-1c42b11b-6bf8-40d4-8dbb-99e9ebc23f45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3554041206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3554041206
Directory	/workspace/19.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/19.uart_rx_start_bit_filter.2023922532
Short name	T1109
Test name
Test status
Simulation time	50477461033 ps
CPU time	27.89 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 12:51:32 PM PDT 24
Peak memory	196356 kb
Host	smart-3c6a11ce-5a8b-4b44-9c71-5916391cc687
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2023922532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2023922532
Directory	/workspace/19.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/19.uart_smoke.3610205309
Short name	T602
Test name
Test status
Simulation time	114257286 ps
CPU time	0.94 seconds
Started	May 30 12:51:02 PM PDT 24
Finished	May 30 12:51:04 PM PDT 24
Peak memory	199856 kb
Host	smart-a84beede-265f-4193-b9d5-fdbe6e8c0a78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3610205309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3610205309
Directory	/workspace/19.uart_smoke/latest

Test location	/workspace/coverage/default/19.uart_stress_all.3744354243
Short name	T1023
Test name
Test status
Simulation time	210051966398 ps
CPU time	696.84 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 01:02:41 PM PDT 24
Peak memory	200416 kb
Host	smart-8b5a59f6-aa50-4b8a-95bd-d6bb57be6673
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744354243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3744354243
Directory	/workspace/19.uart_stress_all/latest

Test location	/workspace/coverage/default/19.uart_stress_all_with_rand_reset.74467358
Short name	T1028
Test name
Test status
Simulation time	165597515152 ps
CPU time	275.2 seconds
Started	May 30 12:51:03 PM PDT 24
Finished	May 30 12:55:39 PM PDT 24
Peak memory	217028 kb
Host	smart-07adaa92-733e-47eb-b6c9-bfc838c4bba5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74467358 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.74467358
Directory	/workspace/19.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.uart_tx_ovrd.547195472
Short name	T490
Test name
Test status
Simulation time	1178033354 ps
CPU time	5.23 seconds
Started	May 30 12:51:04 PM PDT 24
Finished	May 30 12:51:10 PM PDT 24
Peak memory	200240 kb
Host	smart-1fdfd291-3a06-4209-8652-b0d5158ac754
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547195472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.547195472
Directory	/workspace/19.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/19.uart_tx_rx.1122142816
Short name	T1106
Test name
Test status
Simulation time	28597888894 ps
CPU time	76.06 seconds
Started	May 30 12:51:02 PM PDT 24
Finished	May 30 12:52:19 PM PDT 24
Peak memory	200344 kb
Host	smart-e97901ec-cd29-4d91-86b0-5925211ced4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1122142816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1122142816
Directory	/workspace/19.uart_tx_rx/latest

Test location	/workspace/coverage/default/190.uart_fifo_reset.3020514009
Short name	T308
Test name
Test status
Simulation time	177636051305 ps
CPU time	68.25 seconds
Started	May 30 12:54:04 PM PDT 24
Finished	May 30 12:55:14 PM PDT 24
Peak memory	199708 kb
Host	smart-3a8f4c98-b3fb-4164-a578-4209b63ffaac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3020514009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3020514009
Directory	/workspace/190.uart_fifo_reset/latest

Test location	/workspace/coverage/default/191.uart_fifo_reset.639155794
Short name	T241
Test name
Test status
Simulation time	39412319787 ps
CPU time	64.26 seconds
Started	May 30 12:54:17 PM PDT 24
Finished	May 30 12:55:22 PM PDT 24
Peak memory	200340 kb
Host	smart-f14e1727-a89e-4519-b3f7-4102531616d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=639155794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.639155794
Directory	/workspace/191.uart_fifo_reset/latest

Test location	/workspace/coverage/default/192.uart_fifo_reset.2451469210
Short name	T410
Test name
Test status
Simulation time	9959508495 ps
CPU time	15.74 seconds
Started	May 30 12:54:15 PM PDT 24
Finished	May 30 12:54:32 PM PDT 24
Peak memory	200380 kb
Host	smart-7ba8f2e6-bd23-4de1-a93b-012e6240be7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2451469210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2451469210
Directory	/workspace/192.uart_fifo_reset/latest

Test location	/workspace/coverage/default/193.uart_fifo_reset.1231348129
Short name	T224
Test name
Test status
Simulation time	158807548910 ps
CPU time	502.36 seconds
Started	May 30 12:54:15 PM PDT 24
Finished	May 30 01:02:38 PM PDT 24
Peak memory	200332 kb
Host	smart-905d43da-28fe-4a5e-ae51-9f30bffb9b34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231348129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1231348129
Directory	/workspace/193.uart_fifo_reset/latest

Test location	/workspace/coverage/default/195.uart_fifo_reset.652584894
Short name	T138
Test name
Test status
Simulation time	33504777575 ps
CPU time	16.05 seconds
Started	May 30 12:54:12 PM PDT 24
Finished	May 30 12:54:29 PM PDT 24
Peak memory	200220 kb
Host	smart-fa74fcca-7a72-4862-8217-8edf065dd31c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=652584894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.652584894
Directory	/workspace/195.uart_fifo_reset/latest

Test location	/workspace/coverage/default/196.uart_fifo_reset.3232272512
Short name	T553
Test name
Test status
Simulation time	120621589571 ps
CPU time	39.34 seconds
Started	May 30 12:54:14 PM PDT 24
Finished	May 30 12:54:54 PM PDT 24
Peak memory	200308 kb
Host	smart-bb4f17dd-eb0a-4b96-af8d-59ead91ca59a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3232272512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3232272512
Directory	/workspace/196.uart_fifo_reset/latest

Test location	/workspace/coverage/default/197.uart_fifo_reset.2093816186
Short name	T400
Test name
Test status
Simulation time	13604859202 ps
CPU time	40.39 seconds
Started	May 30 12:54:14 PM PDT 24
Finished	May 30 12:54:55 PM PDT 24
Peak memory	200308 kb
Host	smart-55ab7d92-e097-4061-b997-3be840d78a33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2093816186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2093816186
Directory	/workspace/197.uart_fifo_reset/latest

Test location	/workspace/coverage/default/198.uart_fifo_reset.2686130764
Short name	T156
Test name
Test status
Simulation time	39935392561 ps
CPU time	19.98 seconds
Started	May 30 12:54:14 PM PDT 24
Finished	May 30 12:54:35 PM PDT 24
Peak memory	200396 kb
Host	smart-7d889dbd-2721-4efb-b118-dddfb380fea2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2686130764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2686130764
Directory	/workspace/198.uart_fifo_reset/latest

Test location	/workspace/coverage/default/199.uart_fifo_reset.3506566357
Short name	T1147
Test name
Test status
Simulation time	25382720116 ps
CPU time	31.17 seconds
Started	May 30 12:54:22 PM PDT 24
Finished	May 30 12:54:54 PM PDT 24
Peak memory	200200 kb
Host	smart-fbad6c5d-71e4-4b06-9161-87eb6fa1bb3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3506566357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3506566357
Directory	/workspace/199.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_alert_test.86448590
Short name	T397
Test name
Test status
Simulation time	23418839 ps
CPU time	0.55 seconds
Started	May 30 12:50:12 PM PDT 24
Finished	May 30 12:50:15 PM PDT 24
Peak memory	195628 kb
Host	smart-4e39ee09-0995-433e-9846-69617276738f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86448590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.86448590
Directory	/workspace/2.uart_alert_test/latest

Test location	/workspace/coverage/default/2.uart_fifo_full.446174410
Short name	T1170
Test name
Test status
Simulation time	38503974135 ps
CPU time	30.68 seconds
Started	May 30 12:50:07 PM PDT 24
Finished	May 30 12:50:38 PM PDT 24
Peak memory	200396 kb
Host	smart-a74e6340-27a1-44ec-bde0-6031526fd20b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=446174410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.446174410
Directory	/workspace/2.uart_fifo_full/latest

Test location	/workspace/coverage/default/2.uart_fifo_overflow.3101258116
Short name	T557
Test name
Test status
Simulation time	46841809960 ps
CPU time	26.13 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:50:39 PM PDT 24
Peak memory	200144 kb
Host	smart-2da8378c-0b3b-4429-ba72-4c2d43c7651c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3101258116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3101258116
Directory	/workspace/2.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/2.uart_fifo_reset.1131796845
Short name	T142
Test name
Test status
Simulation time	55836839685 ps
CPU time	26.91 seconds
Started	May 30 12:50:12 PM PDT 24
Finished	May 30 12:50:41 PM PDT 24
Peak memory	200348 kb
Host	smart-22fc671e-da54-44c9-a416-546336e1a7c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1131796845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1131796845
Directory	/workspace/2.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_intr.959101568
Short name	T742
Test name
Test status
Simulation time	13536549115 ps
CPU time	20.21 seconds
Started	May 30 12:50:08 PM PDT 24
Finished	May 30 12:50:30 PM PDT 24
Peak memory	199232 kb
Host	smart-d189ccce-3549-4b3a-9aa3-040404b4ead7
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959101568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.959101568
Directory	/workspace/2.uart_intr/latest

Test location	/workspace/coverage/default/2.uart_long_xfer_wo_dly.222967065
Short name	T46
Test name
Test status
Simulation time	86677791581 ps
CPU time	319.08 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:55:31 PM PDT 24
Peak memory	200392 kb
Host	smart-9e0f4207-df77-41ee-a6a1-406d0218ca40
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=222967065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.222967065
Directory	/workspace/2.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/2.uart_loopback.2157952994
Short name	T554
Test name
Test status
Simulation time	10146850376 ps
CPU time	9.85 seconds
Started	May 30 12:50:08 PM PDT 24
Finished	May 30 12:50:19 PM PDT 24
Peak memory	200248 kb
Host	smart-6c5a0729-b48c-4d6e-af15-3b2e71f330af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2157952994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2157952994
Directory	/workspace/2.uart_loopback/latest

Test location	/workspace/coverage/default/2.uart_noise_filter.3066510318
Short name	T818
Test name
Test status
Simulation time	120490633163 ps
CPU time	55.03 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:51:07 PM PDT 24
Peak memory	200568 kb
Host	smart-247b82fc-ea2f-4f9e-a43a-f9822c5e51a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066510318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3066510318
Directory	/workspace/2.uart_noise_filter/latest

Test location	/workspace/coverage/default/2.uart_perf.369257289
Short name	T1103
Test name
Test status
Simulation time	10308998300 ps
CPU time	231.95 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:54:06 PM PDT 24
Peak memory	200352 kb
Host	smart-d3d1ee9d-7536-4d87-b81b-3beb6fcc42bf
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=369257289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.369257289
Directory	/workspace/2.uart_perf/latest

Test location	/workspace/coverage/default/2.uart_rx_oversample.1445176551
Short name	T501
Test name
Test status
Simulation time	6243071421 ps
CPU time	5.33 seconds
Started	May 30 12:50:06 PM PDT 24
Finished	May 30 12:50:13 PM PDT 24
Peak memory	199012 kb
Host	smart-7a11125a-5a95-468a-8b89-005b8fb9d49d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1445176551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1445176551
Directory	/workspace/2.uart_rx_oversample/latest

Test location	/workspace/coverage/default/2.uart_rx_parity_err.1830840026
Short name	T133
Test name
Test status
Simulation time	105459129962 ps
CPU time	181.44 seconds
Started	May 30 12:50:12 PM PDT 24
Finished	May 30 12:53:16 PM PDT 24
Peak memory	200220 kb
Host	smart-385b765c-e9dc-474d-9c2e-5c04f9ef32a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1830840026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1830840026
Directory	/workspace/2.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/2.uart_rx_start_bit_filter.1428995844
Short name	T1129
Test name
Test status
Simulation time	58064307851 ps
CPU time	22.27 seconds
Started	May 30 12:50:07 PM PDT 24
Finished	May 30 12:50:31 PM PDT 24
Peak memory	196280 kb
Host	smart-a6dae999-d9b3-4ae5-9ef3-e9e9a1288f72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1428995844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1428995844
Directory	/workspace/2.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/2.uart_sec_cm.2932903235
Short name	T28
Test name
Test status
Simulation time	224816076 ps
CPU time	0.83 seconds
Started	May 30 12:50:12 PM PDT 24
Finished	May 30 12:50:15 PM PDT 24
Peak memory	218592 kb
Host	smart-5a14938f-3217-4c01-94bb-9537b54f9642
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932903235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2932903235
Directory	/workspace/2.uart_sec_cm/latest

Test location	/workspace/coverage/default/2.uart_smoke.1374843944
Short name	T875
Test name
Test status
Simulation time	6246236846 ps
CPU time	23.12 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:50:36 PM PDT 24
Peak memory	200140 kb
Host	smart-37caa913-e658-4ebc-8a04-de9595df33fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1374843944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1374843944
Directory	/workspace/2.uart_smoke/latest

Test location	/workspace/coverage/default/2.uart_stress_all.1867166810
Short name	T665
Test name
Test status
Simulation time	288429102569 ps
CPU time	157.07 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:52:49 PM PDT 24
Peak memory	200232 kb
Host	smart-5705dd33-3a06-41d7-973c-62c0b5181005
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867166810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1867166810
Directory	/workspace/2.uart_stress_all/latest

Test location	/workspace/coverage/default/2.uart_stress_all_with_rand_reset.659422304
Short name	T1075
Test name
Test status
Simulation time	24164930369 ps
CPU time	68.42 seconds
Started	May 30 12:50:08 PM PDT 24
Finished	May 30 12:51:18 PM PDT 24
Peak memory	216360 kb
Host	smart-9624da41-01c6-4be8-b94c-f3733b268382
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659422304 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.659422304
Directory	/workspace/2.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.uart_tx_ovrd.2294858499
Short name	T870
Test name
Test status
Simulation time	792297971 ps
CPU time	1.69 seconds
Started	May 30 12:50:09 PM PDT 24
Finished	May 30 12:50:13 PM PDT 24
Peak memory	198548 kb
Host	smart-f3ab54b9-2371-4662-a503-3f79c39af900
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2294858499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2294858499
Directory	/workspace/2.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/2.uart_tx_rx.2158349212
Short name	T324
Test name
Test status
Simulation time	54386579717 ps
CPU time	33.36 seconds
Started	May 30 12:50:09 PM PDT 24
Finished	May 30 12:50:45 PM PDT 24
Peak memory	200252 kb
Host	smart-9bbc1466-405b-47d2-b129-3f06d482104a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2158349212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2158349212
Directory	/workspace/2.uart_tx_rx/latest

Test location	/workspace/coverage/default/20.uart_alert_test.3876165338
Short name	T365
Test name
Test status
Simulation time	168350292 ps
CPU time	0.53 seconds
Started	May 30 12:51:11 PM PDT 24
Finished	May 30 12:51:12 PM PDT 24
Peak memory	195756 kb
Host	smart-a56bc8d6-9616-4fa3-9fff-ab9a5da10205
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876165338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3876165338
Directory	/workspace/20.uart_alert_test/latest

Test location	/workspace/coverage/default/20.uart_fifo_overflow.2396147994
Short name	T1137
Test name
Test status
Simulation time	24620208899 ps
CPU time	11.41 seconds
Started	May 30 12:51:00 PM PDT 24
Finished	May 30 12:51:12 PM PDT 24
Peak memory	199784 kb
Host	smart-3665dd17-8482-4915-94b8-29fad26fbfc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396147994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2396147994
Directory	/workspace/20.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/20.uart_fifo_reset.1356323136
Short name	T37
Test name
Test status
Simulation time	27308306570 ps
CPU time	20.11 seconds
Started	May 30 12:51:00 PM PDT 24
Finished	May 30 12:51:21 PM PDT 24
Peak memory	200404 kb
Host	smart-702ba9e5-8803-498c-8694-7a7651c88758
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356323136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1356323136
Directory	/workspace/20.uart_fifo_reset/latest

Test location	/workspace/coverage/default/20.uart_intr.321331811
Short name	T1067
Test name
Test status
Simulation time	12720703247 ps
CPU time	12.25 seconds
Started	May 30 12:51:00 PM PDT 24
Finished	May 30 12:51:13 PM PDT 24
Peak memory	197056 kb
Host	smart-4d0e6aa6-0457-4fdc-afd7-0bfb82e25449
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321331811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.321331811
Directory	/workspace/20.uart_intr/latest

Test location	/workspace/coverage/default/20.uart_long_xfer_wo_dly.911365555
Short name	T1159
Test name
Test status
Simulation time	119572964125 ps
CPU time	312 seconds
Started	May 30 12:51:14 PM PDT 24
Finished	May 30 12:56:27 PM PDT 24
Peak memory	200368 kb
Host	smart-f3dea45a-ab30-4a1a-ad99-68cebbc338fe
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=911365555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.911365555
Directory	/workspace/20.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/20.uart_loopback.3001155256
Short name	T738
Test name
Test status
Simulation time	7884055312 ps
CPU time	16.45 seconds
Started	May 30 12:51:12 PM PDT 24
Finished	May 30 12:51:30 PM PDT 24
Peak memory	198912 kb
Host	smart-fe18ba49-8992-46b1-b694-3ed573619d72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3001155256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3001155256
Directory	/workspace/20.uart_loopback/latest

Test location	/workspace/coverage/default/20.uart_noise_filter.958874000
Short name	T906
Test name
Test status
Simulation time	65479841405 ps
CPU time	28.49 seconds
Started	May 30 12:51:00 PM PDT 24
Finished	May 30 12:51:29 PM PDT 24
Peak memory	198812 kb
Host	smart-04b978a0-c96f-4d84-bfbc-912b57bbf895
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958874000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.958874000
Directory	/workspace/20.uart_noise_filter/latest

Test location	/workspace/coverage/default/20.uart_perf.3263343048
Short name	T607
Test name
Test status
Simulation time	19447682348 ps
CPU time	287.31 seconds
Started	May 30 12:51:15 PM PDT 24
Finished	May 30 12:56:04 PM PDT 24
Peak memory	200340 kb
Host	smart-b0c9b4ba-c3a5-4e0c-85b3-5a80ac7f01de
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3263343048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3263343048
Directory	/workspace/20.uart_perf/latest

Test location	/workspace/coverage/default/20.uart_rx_oversample.239164003
Short name	T1063
Test name
Test status
Simulation time	3409514239 ps
CPU time	6.62 seconds
Started	May 30 12:51:01 PM PDT 24
Finished	May 30 12:51:08 PM PDT 24
Peak memory	200332 kb
Host	smart-64667cc5-d87f-4bf6-9269-ce97dcf8ecf2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=239164003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.239164003
Directory	/workspace/20.uart_rx_oversample/latest

Test location	/workspace/coverage/default/20.uart_rx_parity_err.2233683979
Short name	T446
Test name
Test status
Simulation time	21258345105 ps
CPU time	32.52 seconds
Started	May 30 12:51:00 PM PDT 24
Finished	May 30 12:51:33 PM PDT 24
Peak memory	200200 kb
Host	smart-a5fc1e48-d7fe-49e8-a352-32cd28553b46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2233683979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2233683979
Directory	/workspace/20.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/20.uart_rx_start_bit_filter.3781284859
Short name	T1093
Test name
Test status
Simulation time	44577071785 ps
CPU time	29.89 seconds
Started	May 30 12:51:01 PM PDT 24
Finished	May 30 12:51:32 PM PDT 24
Peak memory	196372 kb
Host	smart-7df187da-925a-4e10-85a2-e4d267bb883b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3781284859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3781284859
Directory	/workspace/20.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/20.uart_smoke.397505737
Short name	T903
Test name
Test status
Simulation time	624658590 ps
CPU time	1.51 seconds
Started	May 30 12:51:04 PM PDT 24
Finished	May 30 12:51:06 PM PDT 24
Peak memory	198840 kb
Host	smart-3f467df8-798c-4362-9f12-cd4b4095864a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=397505737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.397505737
Directory	/workspace/20.uart_smoke/latest

Test location	/workspace/coverage/default/20.uart_stress_all.1742348688
Short name	T682
Test name
Test status
Simulation time	154006097741 ps
CPU time	123.21 seconds
Started	May 30 12:51:17 PM PDT 24
Finished	May 30 12:53:22 PM PDT 24
Peak memory	200408 kb
Host	smart-596573d9-ee1d-487c-8baf-41d2de8c4f1b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742348688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1742348688
Directory	/workspace/20.uart_stress_all/latest

Test location	/workspace/coverage/default/20.uart_stress_all_with_rand_reset.931464319
Short name	T592
Test name
Test status
Simulation time	180866146143 ps
CPU time	500.04 seconds
Started	May 30 12:51:13 PM PDT 24
Finished	May 30 12:59:34 PM PDT 24
Peak memory	217128 kb
Host	smart-f0174f5c-122d-4aa5-a05b-fffcb4a5e875
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931464319 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.931464319
Directory	/workspace/20.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.uart_tx_ovrd.3972375979
Short name	T330
Test name
Test status
Simulation time	1675438124 ps
CPU time	1.79 seconds
Started	May 30 12:51:12 PM PDT 24
Finished	May 30 12:51:15 PM PDT 24
Peak memory	198928 kb
Host	smart-f5041384-892c-44e5-b80e-7c28c2ef6469
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3972375979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3972375979
Directory	/workspace/20.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/20.uart_tx_rx.2207093587
Short name	T671
Test name
Test status
Simulation time	74918480016 ps
CPU time	114.07 seconds
Started	May 30 12:51:00 PM PDT 24
Finished	May 30 12:52:55 PM PDT 24
Peak memory	200388 kb
Host	smart-c7c525ef-5b00-4225-8beb-6d562958deff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2207093587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2207093587
Directory	/workspace/20.uart_tx_rx/latest

Test location	/workspace/coverage/default/200.uart_fifo_reset.907849638
Short name	T604
Test name
Test status
Simulation time	136011409991 ps
CPU time	213 seconds
Started	May 30 12:54:17 PM PDT 24
Finished	May 30 12:57:51 PM PDT 24
Peak memory	200320 kb
Host	smart-587ce6b5-9a73-4f24-9592-2628539b92ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=907849638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.907849638
Directory	/workspace/200.uart_fifo_reset/latest

Test location	/workspace/coverage/default/202.uart_fifo_reset.2641978148
Short name	T1061
Test name
Test status
Simulation time	26595475357 ps
CPU time	42.22 seconds
Started	May 30 12:54:16 PM PDT 24
Finished	May 30 12:54:59 PM PDT 24
Peak memory	200368 kb
Host	smart-1c4d51a2-260c-4469-8e14-260490f15e24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2641978148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2641978148
Directory	/workspace/202.uart_fifo_reset/latest

Test location	/workspace/coverage/default/203.uart_fifo_reset.2232682112
Short name	T787
Test name
Test status
Simulation time	93481944259 ps
CPU time	49.11 seconds
Started	May 30 12:54:15 PM PDT 24
Finished	May 30 12:55:05 PM PDT 24
Peak memory	200352 kb
Host	smart-b8db7278-f1f6-4f22-afc4-3da3c169d27c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2232682112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2232682112
Directory	/workspace/203.uart_fifo_reset/latest

Test location	/workspace/coverage/default/206.uart_fifo_reset.3074875299
Short name	T969
Test name
Test status
Simulation time	19187280403 ps
CPU time	27.99 seconds
Started	May 30 12:54:16 PM PDT 24
Finished	May 30 12:54:45 PM PDT 24
Peak memory	199884 kb
Host	smart-bb0a0673-7f49-4e31-ab79-84bd2945091d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3074875299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3074875299
Directory	/workspace/206.uart_fifo_reset/latest

Test location	/workspace/coverage/default/208.uart_fifo_reset.3312652411
Short name	T1112
Test name
Test status
Simulation time	22868062278 ps
CPU time	53.78 seconds
Started	May 30 12:54:22 PM PDT 24
Finished	May 30 12:55:17 PM PDT 24
Peak memory	200240 kb
Host	smart-27c137ed-5bd0-4da9-a7c8-b6fbbe3492fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3312652411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3312652411
Directory	/workspace/208.uart_fifo_reset/latest

Test location	/workspace/coverage/default/209.uart_fifo_reset.2349897574
Short name	T54
Test name
Test status
Simulation time	37314333498 ps
CPU time	58.73 seconds
Started	May 30 12:54:15 PM PDT 24
Finished	May 30 12:55:14 PM PDT 24
Peak memory	200348 kb
Host	smart-7e3b64ae-f366-4e74-8c9a-075d286896fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349897574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2349897574
Directory	/workspace/209.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_alert_test.2281702099
Short name	T981
Test name
Test status
Simulation time	21220578 ps
CPU time	0.54 seconds
Started	May 30 12:51:13 PM PDT 24
Finished	May 30 12:51:15 PM PDT 24
Peak memory	195672 kb
Host	smart-8f8ce009-90be-4273-9216-c2d0e9fcd03f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281702099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2281702099
Directory	/workspace/21.uart_alert_test/latest

Test location	/workspace/coverage/default/21.uart_fifo_full.3135070114
Short name	T559
Test name
Test status
Simulation time	55692139203 ps
CPU time	62.02 seconds
Started	May 30 12:51:14 PM PDT 24
Finished	May 30 12:52:18 PM PDT 24
Peak memory	200388 kb
Host	smart-f37877db-50b3-4f4a-adf8-2c44fd45bc22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3135070114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3135070114
Directory	/workspace/21.uart_fifo_full/latest

Test location	/workspace/coverage/default/21.uart_fifo_overflow.2242039219
Short name	T867
Test name
Test status
Simulation time	179139436493 ps
CPU time	163.72 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:54:01 PM PDT 24
Peak memory	200364 kb
Host	smart-28ffc9ce-8626-4dc4-8702-a290ee30293d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2242039219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2242039219
Directory	/workspace/21.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/21.uart_fifo_reset.3275914135
Short name	T1163
Test name
Test status
Simulation time	23820833500 ps
CPU time	49.45 seconds
Started	May 30 12:51:12 PM PDT 24
Finished	May 30 12:52:03 PM PDT 24
Peak memory	200324 kb
Host	smart-84beb594-84b6-408f-b792-f59102f0303b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3275914135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3275914135
Directory	/workspace/21.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_intr.2548351059
Short name	T293
Test name
Test status
Simulation time	19526209156 ps
CPU time	34.64 seconds
Started	May 30 12:51:12 PM PDT 24
Finished	May 30 12:51:48 PM PDT 24
Peak memory	199736 kb
Host	smart-325d18df-060d-4af0-8da0-8c5ca07633d9
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548351059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2548351059
Directory	/workspace/21.uart_intr/latest

Test location	/workspace/coverage/default/21.uart_long_xfer_wo_dly.728825694
Short name	T546
Test name
Test status
Simulation time	112134849121 ps
CPU time	297.19 seconds
Started	May 30 12:51:13 PM PDT 24
Finished	May 30 12:56:12 PM PDT 24
Peak memory	200280 kb
Host	smart-68f64617-4441-463b-b2d9-d076e729a107
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=728825694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.728825694
Directory	/workspace/21.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/21.uart_loopback.3604525416
Short name	T717
Test name
Test status
Simulation time	9648082167 ps
CPU time	10.94 seconds
Started	May 30 12:51:13 PM PDT 24
Finished	May 30 12:51:25 PM PDT 24
Peak memory	200320 kb
Host	smart-8c06e5e1-a979-4331-a8c2-619a2a6fe6a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3604525416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3604525416
Directory	/workspace/21.uart_loopback/latest

Test location	/workspace/coverage/default/21.uart_noise_filter.4200340861
Short name	T471
Test name
Test status
Simulation time	228943213523 ps
CPU time	116.21 seconds
Started	May 30 12:51:14 PM PDT 24
Finished	May 30 12:53:12 PM PDT 24
Peak memory	200272 kb
Host	smart-10ed34f2-4540-4b9a-a08a-23673809102e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4200340861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.4200340861
Directory	/workspace/21.uart_noise_filter/latest

Test location	/workspace/coverage/default/21.uart_perf.1643529895
Short name	T871
Test name
Test status
Simulation time	9295300472 ps
CPU time	41.09 seconds
Started	May 30 12:51:14 PM PDT 24
Finished	May 30 12:51:57 PM PDT 24
Peak memory	200396 kb
Host	smart-2cfe022d-5710-48e9-ab58-71db55db705e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1643529895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1643529895
Directory	/workspace/21.uart_perf/latest

Test location	/workspace/coverage/default/21.uart_rx_oversample.1828720249
Short name	T1068
Test name
Test status
Simulation time	2611552697 ps
CPU time	4.51 seconds
Started	May 30 12:51:12 PM PDT 24
Finished	May 30 12:51:18 PM PDT 24
Peak memory	198304 kb
Host	smart-6f3b5925-6fa8-4c30-b4d7-e135357233ff
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1828720249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1828720249
Directory	/workspace/21.uart_rx_oversample/latest

Test location	/workspace/coverage/default/21.uart_rx_parity_err.3602924971
Short name	T894
Test name
Test status
Simulation time	98966577158 ps
CPU time	38.76 seconds
Started	May 30 12:51:14 PM PDT 24
Finished	May 30 12:51:54 PM PDT 24
Peak memory	200304 kb
Host	smart-eda3e43e-be3c-4603-a8be-8762cb3dc6aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3602924971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3602924971
Directory	/workspace/21.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/21.uart_rx_start_bit_filter.1786761207
Short name	T1183
Test name
Test status
Simulation time	1336378215 ps
CPU time	2.83 seconds
Started	May 30 12:51:11 PM PDT 24
Finished	May 30 12:51:14 PM PDT 24
Peak memory	195644 kb
Host	smart-ff73e217-4507-46be-bb4a-f1f81bb8dcd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786761207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1786761207
Directory	/workspace/21.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/21.uart_smoke.3264623771
Short name	T392
Test name
Test status
Simulation time	665963289 ps
CPU time	2.84 seconds
Started	May 30 12:51:13 PM PDT 24
Finished	May 30 12:51:17 PM PDT 24
Peak memory	199104 kb
Host	smart-d52a58d3-80ea-4a73-9030-6e5ec421af07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3264623771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3264623771
Directory	/workspace/21.uart_smoke/latest

Test location	/workspace/coverage/default/21.uart_tx_ovrd.2556077448
Short name	T988
Test name
Test status
Simulation time	6350221334 ps
CPU time	15.8 seconds
Started	May 30 12:51:15 PM PDT 24
Finished	May 30 12:51:33 PM PDT 24
Peak memory	200336 kb
Host	smart-5440ddf2-2dd7-45a5-9adf-f758614bbda5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2556077448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2556077448
Directory	/workspace/21.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/21.uart_tx_rx.2561046480
Short name	T701
Test name
Test status
Simulation time	3785035452 ps
CPU time	3.61 seconds
Started	May 30 12:51:15 PM PDT 24
Finished	May 30 12:51:21 PM PDT 24
Peak memory	197852 kb
Host	smart-b9fe0f85-501b-41b6-8bfa-5c8a8af31bfe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2561046480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2561046480
Directory	/workspace/21.uart_tx_rx/latest

Test location	/workspace/coverage/default/211.uart_fifo_reset.3261361449
Short name	T441
Test name
Test status
Simulation time	20488381736 ps
CPU time	10.88 seconds
Started	May 30 12:54:13 PM PDT 24
Finished	May 30 12:54:25 PM PDT 24
Peak memory	200064 kb
Host	smart-a34549fa-ec3b-4df8-bc6e-33c73dbed012
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3261361449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3261361449
Directory	/workspace/211.uart_fifo_reset/latest

Test location	/workspace/coverage/default/212.uart_fifo_reset.2647818210
Short name	T678
Test name
Test status
Simulation time	29628016603 ps
CPU time	13.81 seconds
Started	May 30 12:54:15 PM PDT 24
Finished	May 30 12:54:30 PM PDT 24
Peak memory	200308 kb
Host	smart-cd279936-7bd4-44c7-a8b5-1e976ba182a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2647818210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2647818210
Directory	/workspace/212.uart_fifo_reset/latest

Test location	/workspace/coverage/default/213.uart_fifo_reset.2730333627
Short name	T317
Test name
Test status
Simulation time	13400925122 ps
CPU time	23.17 seconds
Started	May 30 12:54:16 PM PDT 24
Finished	May 30 12:54:40 PM PDT 24
Peak memory	200380 kb
Host	smart-d600cf70-03b3-4c37-a37b-4fb88259a914
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2730333627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2730333627
Directory	/workspace/213.uart_fifo_reset/latest

Test location	/workspace/coverage/default/214.uart_fifo_reset.1373358600
Short name	T201
Test name
Test status
Simulation time	68345552150 ps
CPU time	28.15 seconds
Started	May 30 12:54:15 PM PDT 24
Finished	May 30 12:54:44 PM PDT 24
Peak memory	200268 kb
Host	smart-835c7bf6-5293-45b1-b514-ce3535e5088c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1373358600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1373358600
Directory	/workspace/214.uart_fifo_reset/latest

Test location	/workspace/coverage/default/215.uart_fifo_reset.1703994585
Short name	T617
Test name
Test status
Simulation time	23000127280 ps
CPU time	32.04 seconds
Started	May 30 12:54:14 PM PDT 24
Finished	May 30 12:54:47 PM PDT 24
Peak memory	200220 kb
Host	smart-ea103108-36f8-4f43-9dc7-b0770a85156a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1703994585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1703994585
Directory	/workspace/215.uart_fifo_reset/latest

Test location	/workspace/coverage/default/216.uart_fifo_reset.2839623189
Short name	T1064
Test name
Test status
Simulation time	44302051722 ps
CPU time	26.58 seconds
Started	May 30 12:54:15 PM PDT 24
Finished	May 30 12:54:43 PM PDT 24
Peak memory	200400 kb
Host	smart-23fbd0dd-4a98-4b62-91e8-bb2ee5a9c4e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2839623189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2839623189
Directory	/workspace/216.uart_fifo_reset/latest

Test location	/workspace/coverage/default/218.uart_fifo_reset.1291361288
Short name	T159
Test name
Test status
Simulation time	38931525496 ps
CPU time	166.81 seconds
Started	May 30 12:54:16 PM PDT 24
Finished	May 30 12:57:04 PM PDT 24
Peak memory	200348 kb
Host	smart-cc601d63-eace-4e45-89df-3504b20e6585
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291361288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1291361288
Directory	/workspace/218.uart_fifo_reset/latest

Test location	/workspace/coverage/default/219.uart_fifo_reset.2822925285
Short name	T191
Test name
Test status
Simulation time	83259642070 ps
CPU time	52.77 seconds
Started	May 30 12:54:14 PM PDT 24
Finished	May 30 12:55:08 PM PDT 24
Peak memory	200392 kb
Host	smart-d4f03624-88cf-445f-a89e-29a1af0b0ef8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822925285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2822925285
Directory	/workspace/219.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_alert_test.46713299
Short name	T467
Test name
Test status
Simulation time	16986245 ps
CPU time	0.53 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:51:19 PM PDT 24
Peak memory	195732 kb
Host	smart-1b8249f8-16c3-4905-a7e2-56d32485f088
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46713299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.46713299
Directory	/workspace/22.uart_alert_test/latest

Test location	/workspace/coverage/default/22.uart_fifo_full.3388142592
Short name	T765
Test name
Test status
Simulation time	54291497946 ps
CPU time	45.8 seconds
Started	May 30 12:51:14 PM PDT 24
Finished	May 30 12:52:01 PM PDT 24
Peak memory	200380 kb
Host	smart-5c646a72-9d2f-4632-902a-071413b6657d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388142592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3388142592
Directory	/workspace/22.uart_fifo_full/latest

Test location	/workspace/coverage/default/22.uart_fifo_overflow.4218218719
Short name	T513
Test name
Test status
Simulation time	34184101846 ps
CPU time	15.67 seconds
Started	May 30 12:51:12 PM PDT 24
Finished	May 30 12:51:28 PM PDT 24
Peak memory	200308 kb
Host	smart-96af2d0e-560f-48a3-afcd-4d4dd1f66f05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4218218719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.4218218719
Directory	/workspace/22.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/22.uart_fifo_reset.3998509175
Short name	T217
Test name
Test status
Simulation time	18456876635 ps
CPU time	36.81 seconds
Started	May 30 12:51:14 PM PDT 24
Finished	May 30 12:51:53 PM PDT 24
Peak memory	200364 kb
Host	smart-4dbdc0fb-dfc4-4bf6-a245-17084d1361be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3998509175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3998509175
Directory	/workspace/22.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_intr.3227201928
Short name	T635
Test name
Test status
Simulation time	20326577266 ps
CPU time	29.03 seconds
Started	May 30 12:51:15 PM PDT 24
Finished	May 30 12:51:46 PM PDT 24
Peak memory	197508 kb
Host	smart-1d757cc8-4023-4ce9-952a-7b77719e3ad2
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227201928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3227201928
Directory	/workspace/22.uart_intr/latest

Test location	/workspace/coverage/default/22.uart_long_xfer_wo_dly.2662061802
Short name	T473
Test name
Test status
Simulation time	141537028941 ps
CPU time	370.66 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:57:29 PM PDT 24
Peak memory	200356 kb
Host	smart-6e9de73e-5381-4d08-8034-68a05d7f2d0e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2662061802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2662061802
Directory	/workspace/22.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/22.uart_loopback.2394553678
Short name	T494
Test name
Test status
Simulation time	7781161987 ps
CPU time	16.07 seconds
Started	May 30 12:51:15 PM PDT 24
Finished	May 30 12:51:33 PM PDT 24
Peak memory	200280 kb
Host	smart-8b82ff89-36ec-4943-af52-f072a5c27c6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2394553678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2394553678
Directory	/workspace/22.uart_loopback/latest

Test location	/workspace/coverage/default/22.uart_noise_filter.181512874
Short name	T427
Test name
Test status
Simulation time	207359894336 ps
CPU time	77.17 seconds
Started	May 30 12:51:15 PM PDT 24
Finished	May 30 12:52:34 PM PDT 24
Peak memory	199312 kb
Host	smart-09cb58a3-bf24-4fb5-8380-2947b8f2410b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=181512874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.181512874
Directory	/workspace/22.uart_noise_filter/latest

Test location	/workspace/coverage/default/22.uart_perf.4163789862
Short name	T1039
Test name
Test status
Simulation time	11534452969 ps
CPU time	605.22 seconds
Started	May 30 12:51:14 PM PDT 24
Finished	May 30 01:01:21 PM PDT 24
Peak memory	200344 kb
Host	smart-d2ec3c07-bc73-4686-a4aa-3e0c2d04cda3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4163789862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.4163789862
Directory	/workspace/22.uart_perf/latest

Test location	/workspace/coverage/default/22.uart_rx_oversample.4061161796
Short name	T640
Test name
Test status
Simulation time	5152505693 ps
CPU time	41.94 seconds
Started	May 30 12:51:14 PM PDT 24
Finished	May 30 12:51:57 PM PDT 24
Peak memory	199588 kb
Host	smart-11d7b69c-490b-475e-9c05-b10710c54633
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4061161796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.4061161796
Directory	/workspace/22.uart_rx_oversample/latest

Test location	/workspace/coverage/default/22.uart_rx_parity_err.2136393638
Short name	T150
Test name
Test status
Simulation time	104114885123 ps
CPU time	55.16 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:52:13 PM PDT 24
Peak memory	200220 kb
Host	smart-45f19842-df49-4bc9-981b-6080fa41b5bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136393638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2136393638
Directory	/workspace/22.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/22.uart_rx_start_bit_filter.1754900601
Short name	T495
Test name
Test status
Simulation time	3950512139 ps
CPU time	7.39 seconds
Started	May 30 12:51:14 PM PDT 24
Finished	May 30 12:51:23 PM PDT 24
Peak memory	196352 kb
Host	smart-4be9adf4-32e1-45ac-9384-63a581c8dcc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1754900601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1754900601
Directory	/workspace/22.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/22.uart_smoke.3721472391
Short name	T269
Test name
Test status
Simulation time	724456717 ps
CPU time	2.34 seconds
Started	May 30 12:51:12 PM PDT 24
Finished	May 30 12:51:16 PM PDT 24
Peak memory	200112 kb
Host	smart-2a05b6d8-9cdd-48e1-8129-396061a06517
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3721472391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3721472391
Directory	/workspace/22.uart_smoke/latest

Test location	/workspace/coverage/default/22.uart_stress_all.1680419599
Short name	T669
Test name
Test status
Simulation time	119765372456 ps
CPU time	93.41 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:52:51 PM PDT 24
Peak memory	200392 kb
Host	smart-ead89575-538a-44cc-bb68-02d2fa49adbb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680419599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1680419599
Directory	/workspace/22.uart_stress_all/latest

Test location	/workspace/coverage/default/22.uart_stress_all_with_rand_reset.3910907577
Short name	T60
Test name
Test status
Simulation time	41404515131 ps
CPU time	576.81 seconds
Started	May 30 12:51:14 PM PDT 24
Finished	May 30 01:00:52 PM PDT 24
Peak memory	208672 kb
Host	smart-b207c093-428c-4401-86a1-0d60bfddda73
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910907577 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3910907577
Directory	/workspace/22.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.uart_tx_ovrd.2245934669
Short name	T762
Test name
Test status
Simulation time	1546650212 ps
CPU time	1.79 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:51:20 PM PDT 24
Peak memory	199156 kb
Host	smart-f7654e68-fb91-4abd-887b-8728c09ad7ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2245934669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2245934669
Directory	/workspace/22.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/22.uart_tx_rx.2709752501
Short name	T515
Test name
Test status
Simulation time	30935516060 ps
CPU time	16.92 seconds
Started	May 30 12:51:15 PM PDT 24
Finished	May 30 12:51:34 PM PDT 24
Peak memory	200392 kb
Host	smart-eb26a61d-50fc-450f-8216-581b3f480cc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709752501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2709752501
Directory	/workspace/22.uart_tx_rx/latest

Test location	/workspace/coverage/default/221.uart_fifo_reset.3791693639
Short name	T632
Test name
Test status
Simulation time	109732062754 ps
CPU time	176.69 seconds
Started	May 30 12:54:14 PM PDT 24
Finished	May 30 12:57:11 PM PDT 24
Peak memory	200396 kb
Host	smart-7dbc2c32-8a3c-40b6-9e75-e0cec538671b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3791693639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3791693639
Directory	/workspace/221.uart_fifo_reset/latest

Test location	/workspace/coverage/default/222.uart_fifo_reset.3313820887
Short name	T695
Test name
Test status
Simulation time	62257331853 ps
CPU time	49.4 seconds
Started	May 30 12:54:22 PM PDT 24
Finished	May 30 12:55:13 PM PDT 24
Peak memory	200264 kb
Host	smart-d4a67e21-bc2a-4f8b-aaab-e3efe086d94a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3313820887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3313820887
Directory	/workspace/222.uart_fifo_reset/latest

Test location	/workspace/coverage/default/223.uart_fifo_reset.2866682135
Short name	T1089
Test name
Test status
Simulation time	35912959540 ps
CPU time	27.59 seconds
Started	May 30 12:54:15 PM PDT 24
Finished	May 30 12:54:44 PM PDT 24
Peak memory	200352 kb
Host	smart-0ec2d1a9-4ca2-4d21-a285-4c2e6377aae4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2866682135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2866682135
Directory	/workspace/223.uart_fifo_reset/latest

Test location	/workspace/coverage/default/224.uart_fifo_reset.1749559183
Short name	T211
Test name
Test status
Simulation time	27442869272 ps
CPU time	50.35 seconds
Started	May 30 12:54:15 PM PDT 24
Finished	May 30 12:55:07 PM PDT 24
Peak memory	200372 kb
Host	smart-9a095dd4-3b74-49f6-963c-4327307fd37a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1749559183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1749559183
Directory	/workspace/224.uart_fifo_reset/latest

Test location	/workspace/coverage/default/225.uart_fifo_reset.1283740483
Short name	T253
Test name
Test status
Simulation time	43073723683 ps
CPU time	19.4 seconds
Started	May 30 12:54:14 PM PDT 24
Finished	May 30 12:54:35 PM PDT 24
Peak memory	200312 kb
Host	smart-f35dc48d-d673-4214-8d46-240fef8b5240
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283740483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1283740483
Directory	/workspace/225.uart_fifo_reset/latest

Test location	/workspace/coverage/default/226.uart_fifo_reset.2815949277
Short name	T606
Test name
Test status
Simulation time	89326036056 ps
CPU time	169.08 seconds
Started	May 30 12:54:15 PM PDT 24
Finished	May 30 12:57:05 PM PDT 24
Peak memory	200392 kb
Host	smart-ac5a7998-11eb-4f20-a828-b0f36f5406d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815949277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2815949277
Directory	/workspace/226.uart_fifo_reset/latest

Test location	/workspace/coverage/default/227.uart_fifo_reset.971238335
Short name	T749
Test name
Test status
Simulation time	12121523668 ps
CPU time	18.99 seconds
Started	May 30 12:54:34 PM PDT 24
Finished	May 30 12:54:53 PM PDT 24
Peak memory	200236 kb
Host	smart-162b30c6-66cc-4015-8f10-d70f0410d072
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=971238335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.971238335
Directory	/workspace/227.uart_fifo_reset/latest

Test location	/workspace/coverage/default/229.uart_fifo_reset.3985133319
Short name	T1134
Test name
Test status
Simulation time	115504315903 ps
CPU time	48.99 seconds
Started	May 30 12:54:37 PM PDT 24
Finished	May 30 12:55:27 PM PDT 24
Peak memory	200364 kb
Host	smart-c78e7973-2fe5-433b-a8c6-beeb49675c14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3985133319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3985133319
Directory	/workspace/229.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_alert_test.91351497
Short name	T999
Test name
Test status
Simulation time	14107612 ps
CPU time	0.55 seconds
Started	May 30 12:51:15 PM PDT 24
Finished	May 30 12:51:18 PM PDT 24
Peak memory	195092 kb
Host	smart-7682d471-ce38-4f99-9337-60421ced5080
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91351497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.91351497
Directory	/workspace/23.uart_alert_test/latest

Test location	/workspace/coverage/default/23.uart_fifo_full.273424101
Short name	T1087
Test name
Test status
Simulation time	305324541756 ps
CPU time	55.25 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:52:14 PM PDT 24
Peak memory	200372 kb
Host	smart-d58731ea-6d33-41e2-a7da-fff701d009ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=273424101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.273424101
Directory	/workspace/23.uart_fifo_full/latest

Test location	/workspace/coverage/default/23.uart_fifo_overflow.4228525293
Short name	T179
Test name
Test status
Simulation time	156325505096 ps
CPU time	203.17 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:54:41 PM PDT 24
Peak memory	200248 kb
Host	smart-546298c6-0dc4-46d7-b086-8fe7ba69df61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4228525293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4228525293
Directory	/workspace/23.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/23.uart_fifo_reset.3085601951
Short name	T198
Test name
Test status
Simulation time	34054278709 ps
CPU time	17.71 seconds
Started	May 30 12:51:13 PM PDT 24
Finished	May 30 12:51:32 PM PDT 24
Peak memory	200384 kb
Host	smart-95121f42-9ef2-42ee-b4fd-1bec58e93f4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085601951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3085601951
Directory	/workspace/23.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_intr.109042375
Short name	T532
Test name
Test status
Simulation time	240321339263 ps
CPU time	353.27 seconds
Started	May 30 12:51:17 PM PDT 24
Finished	May 30 12:57:12 PM PDT 24
Peak memory	200168 kb
Host	smart-6775e5d4-273d-4481-9768-566b613059d7
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109042375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.109042375
Directory	/workspace/23.uart_intr/latest

Test location	/workspace/coverage/default/23.uart_long_xfer_wo_dly.3305337284
Short name	T961
Test name
Test status
Simulation time	137232631292 ps
CPU time	1054.66 seconds
Started	May 30 12:51:17 PM PDT 24
Finished	May 30 01:08:53 PM PDT 24
Peak memory	200384 kb
Host	smart-e70bfefe-c49e-4531-b340-0184a6819604
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3305337284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3305337284
Directory	/workspace/23.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/23.uart_loopback.2789753086
Short name	T808
Test name
Test status
Simulation time	8398418911 ps
CPU time	6.58 seconds
Started	May 30 12:51:18 PM PDT 24
Finished	May 30 12:51:26 PM PDT 24
Peak memory	199156 kb
Host	smart-303e8500-9579-4a56-b967-7b9690634980
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789753086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2789753086
Directory	/workspace/23.uart_loopback/latest

Test location	/workspace/coverage/default/23.uart_noise_filter.1138480665
Short name	T44
Test name
Test status
Simulation time	116712079891 ps
CPU time	105.78 seconds
Started	May 30 12:51:13 PM PDT 24
Finished	May 30 12:53:00 PM PDT 24
Peak memory	200440 kb
Host	smart-199ed818-ad24-419f-8950-212de8cb57e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1138480665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1138480665
Directory	/workspace/23.uart_noise_filter/latest

Test location	/workspace/coverage/default/23.uart_perf.1042960751
Short name	T1057
Test name
Test status
Simulation time	19700155625 ps
CPU time	1222.75 seconds
Started	May 30 12:51:14 PM PDT 24
Finished	May 30 01:11:38 PM PDT 24
Peak memory	200396 kb
Host	smart-d216ca6a-822e-470f-8d2c-374e0f4ffd2d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1042960751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1042960751
Directory	/workspace/23.uart_perf/latest

Test location	/workspace/coverage/default/23.uart_rx_oversample.3813255710
Short name	T896
Test name
Test status
Simulation time	7054050519 ps
CPU time	65.87 seconds
Started	May 30 12:51:13 PM PDT 24
Finished	May 30 12:52:21 PM PDT 24
Peak memory	198412 kb
Host	smart-ec487333-4f52-4382-a2b0-c65564347b2c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3813255710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3813255710
Directory	/workspace/23.uart_rx_oversample/latest

Test location	/workspace/coverage/default/23.uart_rx_parity_err.849865977
Short name	T1000
Test name
Test status
Simulation time	99663300406 ps
CPU time	167.83 seconds
Started	May 30 12:51:17 PM PDT 24
Finished	May 30 12:54:07 PM PDT 24
Peak memory	200236 kb
Host	smart-ded2d5cb-4415-484b-b208-04e887a654e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=849865977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.849865977
Directory	/workspace/23.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/23.uart_rx_start_bit_filter.3826452705
Short name	T764
Test name
Test status
Simulation time	4208608394 ps
CPU time	4.03 seconds
Started	May 30 12:51:18 PM PDT 24
Finished	May 30 12:51:23 PM PDT 24
Peak memory	196292 kb
Host	smart-725c0ae4-8a49-4171-b0b9-a07329df737b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3826452705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3826452705
Directory	/workspace/23.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/23.uart_smoke.3686368831
Short name	T500
Test name
Test status
Simulation time	841452097 ps
CPU time	3.12 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:51:21 PM PDT 24
Peak memory	198656 kb
Host	smart-072ce970-aae0-464c-8515-c8e8d9d2f6bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3686368831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3686368831
Directory	/workspace/23.uart_smoke/latest

Test location	/workspace/coverage/default/23.uart_stress_all.1473556491
Short name	T612
Test name
Test status
Simulation time	222839873504 ps
CPU time	1270.93 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 01:12:29 PM PDT 24
Peak memory	200276 kb
Host	smart-d34d78f5-ac8f-40f2-8ab0-9bf83ed106c1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473556491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1473556491
Directory	/workspace/23.uart_stress_all/latest

Test location	/workspace/coverage/default/23.uart_stress_all_with_rand_reset.3489904397
Short name	T673
Test name
Test status
Simulation time	36068038046 ps
CPU time	303.14 seconds
Started	May 30 12:51:15 PM PDT 24
Finished	May 30 12:56:20 PM PDT 24
Peak memory	216736 kb
Host	smart-32fdf4e0-feef-4765-bb74-10345d53a9dc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489904397 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3489904397
Directory	/workspace/23.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.uart_tx_ovrd.3507652997
Short name	T1060
Test name
Test status
Simulation time	1050039143 ps
CPU time	1.41 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:51:19 PM PDT 24
Peak memory	199476 kb
Host	smart-1be9a6ab-3d2c-4f6d-ae8b-ae9ab5b9396c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3507652997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3507652997
Directory	/workspace/23.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/23.uart_tx_rx.3204211934
Short name	T472
Test name
Test status
Simulation time	38216804185 ps
CPU time	22.49 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:51:40 PM PDT 24
Peak memory	200320 kb
Host	smart-a24a0e1d-1cfa-45f2-9604-5c1bf5fd557b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3204211934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3204211934
Directory	/workspace/23.uart_tx_rx/latest

Test location	/workspace/coverage/default/230.uart_fifo_reset.3211487622
Short name	T1102
Test name
Test status
Simulation time	28544864293 ps
CPU time	24.38 seconds
Started	May 30 12:54:33 PM PDT 24
Finished	May 30 12:54:58 PM PDT 24
Peak memory	200368 kb
Host	smart-5ce18453-8721-44a4-8393-12bc536aa21a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3211487622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3211487622
Directory	/workspace/230.uart_fifo_reset/latest

Test location	/workspace/coverage/default/233.uart_fifo_reset.4003406103
Short name	T776
Test name
Test status
Simulation time	29471392633 ps
CPU time	26.35 seconds
Started	May 30 12:54:34 PM PDT 24
Finished	May 30 12:55:01 PM PDT 24
Peak memory	200284 kb
Host	smart-c930f48a-9386-4bef-9fa8-7d5ce422c34c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003406103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.4003406103
Directory	/workspace/233.uart_fifo_reset/latest

Test location	/workspace/coverage/default/234.uart_fifo_reset.1400126508
Short name	T395
Test name
Test status
Simulation time	24423812347 ps
CPU time	41.61 seconds
Started	May 30 12:54:33 PM PDT 24
Finished	May 30 12:55:15 PM PDT 24
Peak memory	200332 kb
Host	smart-818d7dee-ef0f-49a7-be7f-d0f0a0025e9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1400126508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1400126508
Directory	/workspace/234.uart_fifo_reset/latest

Test location	/workspace/coverage/default/235.uart_fifo_reset.2675167399
Short name	T143
Test name
Test status
Simulation time	50147486949 ps
CPU time	61.29 seconds
Started	May 30 12:54:35 PM PDT 24
Finished	May 30 12:55:37 PM PDT 24
Peak memory	200392 kb
Host	smart-9c12d17e-54e7-42f2-b6ac-37c1189b2c3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2675167399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2675167399
Directory	/workspace/235.uart_fifo_reset/latest

Test location	/workspace/coverage/default/236.uart_fifo_reset.1950529031
Short name	T455
Test name
Test status
Simulation time	84814899780 ps
CPU time	30.88 seconds
Started	May 30 12:54:35 PM PDT 24
Finished	May 30 12:55:07 PM PDT 24
Peak memory	200272 kb
Host	smart-c903d365-6e52-4251-a0ef-38770af561ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1950529031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1950529031
Directory	/workspace/236.uart_fifo_reset/latest

Test location	/workspace/coverage/default/237.uart_fifo_reset.1505978100
Short name	T785
Test name
Test status
Simulation time	41011572088 ps
CPU time	20.52 seconds
Started	May 30 12:54:36 PM PDT 24
Finished	May 30 12:54:58 PM PDT 24
Peak memory	199872 kb
Host	smart-add0d50b-6114-4186-9dd9-0340d9544501
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505978100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1505978100
Directory	/workspace/237.uart_fifo_reset/latest

Test location	/workspace/coverage/default/238.uart_fifo_reset.832576304
Short name	T791
Test name
Test status
Simulation time	229303732285 ps
CPU time	91.05 seconds
Started	May 30 12:54:34 PM PDT 24
Finished	May 30 12:56:06 PM PDT 24
Peak memory	200400 kb
Host	smart-a67c59ca-1c2a-4a6f-ba08-de6472077d57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832576304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.832576304
Directory	/workspace/238.uart_fifo_reset/latest

Test location	/workspace/coverage/default/239.uart_fifo_reset.1345529281
Short name	T221
Test name
Test status
Simulation time	16882376524 ps
CPU time	24.59 seconds
Started	May 30 12:54:37 PM PDT 24
Finished	May 30 12:55:03 PM PDT 24
Peak memory	200084 kb
Host	smart-51019463-266c-4f9d-b8fb-cc15db3c3924
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345529281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1345529281
Directory	/workspace/239.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_alert_test.205386456
Short name	T1052
Test name
Test status
Simulation time	15950267 ps
CPU time	0.57 seconds
Started	May 30 12:51:27 PM PDT 24
Finished	May 30 12:51:29 PM PDT 24
Peak memory	195768 kb
Host	smart-c5b1905b-57ac-4ee4-8227-fe24741d47ac
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205386456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.205386456
Directory	/workspace/24.uart_alert_test/latest

Test location	/workspace/coverage/default/24.uart_fifo_full.2514333926
Short name	T982
Test name
Test status
Simulation time	49109579609 ps
CPU time	26.67 seconds
Started	May 30 12:51:18 PM PDT 24
Finished	May 30 12:51:46 PM PDT 24
Peak memory	200340 kb
Host	smart-ffa320ee-5280-4293-8a75-5ab92927d64b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2514333926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2514333926
Directory	/workspace/24.uart_fifo_full/latest

Test location	/workspace/coverage/default/24.uart_fifo_overflow.887771521
Short name	T289
Test name
Test status
Simulation time	69236767189 ps
CPU time	7.8 seconds
Started	May 30 12:51:12 PM PDT 24
Finished	May 30 12:51:21 PM PDT 24
Peak memory	200312 kb
Host	smart-edb4066c-9b0a-43de-b166-12446a1753c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=887771521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.887771521
Directory	/workspace/24.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/24.uart_fifo_reset.1950997271
Short name	T832
Test name
Test status
Simulation time	170816484648 ps
CPU time	18.41 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:51:37 PM PDT 24
Peak memory	200356 kb
Host	smart-06251393-344f-49f2-8dde-59e97a5292d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1950997271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1950997271
Directory	/workspace/24.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_intr.2350295955
Short name	T17
Test name
Test status
Simulation time	52996877639 ps
CPU time	94.32 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:52:53 PM PDT 24
Peak memory	200380 kb
Host	smart-427f61f0-98ae-4c2c-8c42-15ac2d825810
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350295955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2350295955
Directory	/workspace/24.uart_intr/latest

Test location	/workspace/coverage/default/24.uart_long_xfer_wo_dly.109755996
Short name	T1167
Test name
Test status
Simulation time	89541399317 ps
CPU time	293.28 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 12:56:23 PM PDT 24
Peak memory	200320 kb
Host	smart-8f226d04-385f-49bc-9c69-8cd8388b30ef
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=109755996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.109755996
Directory	/workspace/24.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/24.uart_loopback.2075345851
Short name	T388
Test name
Test status
Simulation time	7027800010 ps
CPU time	12.37 seconds
Started	May 30 12:51:27 PM PDT 24
Finished	May 30 12:51:41 PM PDT 24
Peak memory	200212 kb
Host	smart-d07ff511-4e88-478c-8702-67e0128f2a89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075345851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2075345851
Directory	/workspace/24.uart_loopback/latest

Test location	/workspace/coverage/default/24.uart_noise_filter.57212288
Short name	T267
Test name
Test status
Simulation time	49332844840 ps
CPU time	21.43 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:51:39 PM PDT 24
Peak memory	199768 kb
Host	smart-9df5ce2c-e5f1-4dd0-9f55-6ac4ba1b2af3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=57212288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.57212288
Directory	/workspace/24.uart_noise_filter/latest

Test location	/workspace/coverage/default/24.uart_perf.1073930868
Short name	T372
Test name
Test status
Simulation time	6709535758 ps
CPU time	178.99 seconds
Started	May 30 12:51:26 PM PDT 24
Finished	May 30 12:54:25 PM PDT 24
Peak memory	200376 kb
Host	smart-2ea6bd3a-b665-4411-a939-b7f58dcb898c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1073930868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1073930868
Directory	/workspace/24.uart_perf/latest

Test location	/workspace/coverage/default/24.uart_rx_oversample.2916452861
Short name	T853
Test name
Test status
Simulation time	2981270059 ps
CPU time	5.67 seconds
Started	May 30 12:51:16 PM PDT 24
Finished	May 30 12:51:24 PM PDT 24
Peak memory	199468 kb
Host	smart-b9a09b67-546a-41f3-91b8-5f257cf8650e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2916452861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2916452861
Directory	/workspace/24.uart_rx_oversample/latest

Test location	/workspace/coverage/default/24.uart_rx_parity_err.795078032
Short name	T536
Test name
Test status
Simulation time	181564539595 ps
CPU time	87.81 seconds
Started	May 30 12:51:25 PM PDT 24
Finished	May 30 12:52:54 PM PDT 24
Peak memory	200196 kb
Host	smart-7eee96af-d851-4cef-9de0-53e1dfed6b96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=795078032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.795078032
Directory	/workspace/24.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/24.uart_rx_start_bit_filter.3513158676
Short name	T761
Test name
Test status
Simulation time	4411276607 ps
CPU time	2.16 seconds
Started	May 30 12:51:15 PM PDT 24
Finished	May 30 12:51:20 PM PDT 24
Peak memory	196652 kb
Host	smart-afb52f12-3a4b-45a5-b026-f6d23336cef9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513158676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3513158676
Directory	/workspace/24.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/24.uart_smoke.2752794196
Short name	T406
Test name
Test status
Simulation time	290872104 ps
CPU time	1.51 seconds
Started	May 30 12:51:14 PM PDT 24
Finished	May 30 12:51:18 PM PDT 24
Peak memory	199212 kb
Host	smart-37f9b972-dc76-455d-8756-bb51de9cde3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2752794196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2752794196
Directory	/workspace/24.uart_smoke/latest

Test location	/workspace/coverage/default/24.uart_stress_all.65575713
Short name	T461
Test name
Test status
Simulation time	513216590778 ps
CPU time	658.71 seconds
Started	May 30 12:51:30 PM PDT 24
Finished	May 30 01:02:30 PM PDT 24
Peak memory	200332 kb
Host	smart-f0da9214-a86d-41ec-8b30-25575e9f2bd2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65575713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.65575713
Directory	/workspace/24.uart_stress_all/latest

Test location	/workspace/coverage/default/24.uart_tx_ovrd.1560403912
Short name	T684
Test name
Test status
Simulation time	752188571 ps
CPU time	2.4 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 12:51:32 PM PDT 24
Peak memory	199168 kb
Host	smart-5289ba98-7a48-46f3-8d49-24410550f920
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1560403912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1560403912
Directory	/workspace/24.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/24.uart_tx_rx.2882373493
Short name	T614
Test name
Test status
Simulation time	56671435214 ps
CPU time	90.35 seconds
Started	May 30 12:51:17 PM PDT 24
Finished	May 30 12:52:49 PM PDT 24
Peak memory	200356 kb
Host	smart-fc1811d9-97f4-498c-a8a5-a9a1f5b61b02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2882373493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2882373493
Directory	/workspace/24.uart_tx_rx/latest

Test location	/workspace/coverage/default/240.uart_fifo_reset.3147098056
Short name	T774
Test name
Test status
Simulation time	40483087787 ps
CPU time	13.15 seconds
Started	May 30 12:54:34 PM PDT 24
Finished	May 30 12:54:47 PM PDT 24
Peak memory	200244 kb
Host	smart-d72a4c2a-c26b-41a2-94d5-5e12d98bf921
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3147098056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3147098056
Directory	/workspace/240.uart_fifo_reset/latest

Test location	/workspace/coverage/default/241.uart_fifo_reset.1983743713
Short name	T895
Test name
Test status
Simulation time	335923805061 ps
CPU time	34.7 seconds
Started	May 30 12:54:34 PM PDT 24
Finished	May 30 12:55:09 PM PDT 24
Peak memory	200224 kb
Host	smart-0ef4b572-87e9-42a7-8709-9845f75467b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1983743713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1983743713
Directory	/workspace/241.uart_fifo_reset/latest

Test location	/workspace/coverage/default/243.uart_fifo_reset.1870331884
Short name	T1154
Test name
Test status
Simulation time	28692898154 ps
CPU time	15.43 seconds
Started	May 30 12:54:33 PM PDT 24
Finished	May 30 12:54:49 PM PDT 24
Peak memory	200284 kb
Host	smart-d577901f-1289-4bc3-8dd2-cda677b8ffe8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1870331884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1870331884
Directory	/workspace/243.uart_fifo_reset/latest

Test location	/workspace/coverage/default/244.uart_fifo_reset.1936689965
Short name	T757
Test name
Test status
Simulation time	189415123168 ps
CPU time	21.55 seconds
Started	May 30 12:54:33 PM PDT 24
Finished	May 30 12:54:56 PM PDT 24
Peak memory	200376 kb
Host	smart-97c769bb-7c50-412d-bd1d-5fefe3749886
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936689965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1936689965
Directory	/workspace/244.uart_fifo_reset/latest

Test location	/workspace/coverage/default/245.uart_fifo_reset.4122850608
Short name	T285
Test name
Test status
Simulation time	6317447525 ps
CPU time	22.48 seconds
Started	May 30 12:54:34 PM PDT 24
Finished	May 30 12:54:57 PM PDT 24
Peak memory	200388 kb
Host	smart-7bf9de70-6738-4502-939c-31c0d9e156f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4122850608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.4122850608
Directory	/workspace/245.uart_fifo_reset/latest

Test location	/workspace/coverage/default/246.uart_fifo_reset.2567635695
Short name	T239
Test name
Test status
Simulation time	86948536817 ps
CPU time	21.02 seconds
Started	May 30 12:54:34 PM PDT 24
Finished	May 30 12:54:56 PM PDT 24
Peak memory	200336 kb
Host	smart-6397d546-7548-4a2c-8248-39852b7859ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2567635695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2567635695
Directory	/workspace/246.uart_fifo_reset/latest

Test location	/workspace/coverage/default/247.uart_fifo_reset.2890044988
Short name	T185
Test name
Test status
Simulation time	45074351073 ps
CPU time	16.91 seconds
Started	May 30 12:54:33 PM PDT 24
Finished	May 30 12:54:51 PM PDT 24
Peak memory	200408 kb
Host	smart-d6dd434d-5caf-4606-b5cd-f5522d1da357
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2890044988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2890044988
Directory	/workspace/247.uart_fifo_reset/latest

Test location	/workspace/coverage/default/248.uart_fifo_reset.513429333
Short name	T1020
Test name
Test status
Simulation time	14189719288 ps
CPU time	36.1 seconds
Started	May 30 12:54:35 PM PDT 24
Finished	May 30 12:55:12 PM PDT 24
Peak memory	200356 kb
Host	smart-9f02a3ef-c5f5-4589-a851-f3d9e2935d6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513429333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.513429333
Directory	/workspace/248.uart_fifo_reset/latest

Test location	/workspace/coverage/default/249.uart_fifo_reset.618403346
Short name	T745
Test name
Test status
Simulation time	18284176654 ps
CPU time	14.25 seconds
Started	May 30 12:54:35 PM PDT 24
Finished	May 30 12:54:50 PM PDT 24
Peak memory	199988 kb
Host	smart-a1277a6d-880d-4e78-8ff4-827b10b41237
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=618403346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.618403346
Directory	/workspace/249.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_alert_test.2533391600
Short name	T694
Test name
Test status
Simulation time	26002868 ps
CPU time	0.57 seconds
Started	May 30 12:51:27 PM PDT 24
Finished	May 30 12:51:28 PM PDT 24
Peak memory	195672 kb
Host	smart-4a4a6adc-5059-4db4-aea2-f238732c8d3f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533391600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2533391600
Directory	/workspace/25.uart_alert_test/latest

Test location	/workspace/coverage/default/25.uart_fifo_full.2922392362
Short name	T723
Test name
Test status
Simulation time	12195044179 ps
CPU time	12.88 seconds
Started	May 30 12:51:27 PM PDT 24
Finished	May 30 12:51:40 PM PDT 24
Peak memory	200352 kb
Host	smart-43c42304-dea1-4a93-a6ac-6a31b81ed9bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2922392362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2922392362
Directory	/workspace/25.uart_fifo_full/latest

Test location	/workspace/coverage/default/25.uart_fifo_overflow.2376385199
Short name	T53
Test name
Test status
Simulation time	87168003592 ps
CPU time	74.53 seconds
Started	May 30 12:51:26 PM PDT 24
Finished	May 30 12:52:41 PM PDT 24
Peak memory	200320 kb
Host	smart-2b1f9ec7-6d91-4bb6-a460-f4dcd6199e25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2376385199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2376385199
Directory	/workspace/25.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/25.uart_fifo_reset.2164429357
Short name	T837
Test name
Test status
Simulation time	13101896806 ps
CPU time	11.14 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 12:51:40 PM PDT 24
Peak memory	200296 kb
Host	smart-9c381e53-27b1-4dc9-ab12-3797da43e93d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2164429357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2164429357
Directory	/workspace/25.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_intr.2104026295
Short name	T120
Test name
Test status
Simulation time	42247055340 ps
CPU time	41.92 seconds
Started	May 30 12:51:30 PM PDT 24
Finished	May 30 12:52:13 PM PDT 24
Peak memory	200304 kb
Host	smart-6afac387-9ca1-4e35-97e7-f88eb6191cd2
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104026295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2104026295
Directory	/workspace/25.uart_intr/latest

Test location	/workspace/coverage/default/25.uart_long_xfer_wo_dly.3133992982
Short name	T263
Test name
Test status
Simulation time	95782803009 ps
CPU time	209.2 seconds
Started	May 30 12:51:27 PM PDT 24
Finished	May 30 12:54:58 PM PDT 24
Peak memory	200380 kb
Host	smart-5ff78129-1b78-4f11-9fc6-5edd088f533d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3133992982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3133992982
Directory	/workspace/25.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/25.uart_loopback.1556213860
Short name	T335
Test name
Test status
Simulation time	8114193666 ps
CPU time	9.01 seconds
Started	May 30 12:51:29 PM PDT 24
Finished	May 30 12:51:40 PM PDT 24
Peak memory	200340 kb
Host	smart-5b9dee08-2d3b-46e1-9806-4cdc7bb23a16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1556213860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1556213860
Directory	/workspace/25.uart_loopback/latest

Test location	/workspace/coverage/default/25.uart_noise_filter.965913583
Short name	T452
Test name
Test status
Simulation time	40239379172 ps
CPU time	79.5 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 12:52:49 PM PDT 24
Peak memory	200448 kb
Host	smart-3c71f642-fafc-48de-88f7-4b3981e58519
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=965913583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.965913583
Directory	/workspace/25.uart_noise_filter/latest

Test location	/workspace/coverage/default/25.uart_perf.1783567998
Short name	T1165
Test name
Test status
Simulation time	8785874871 ps
CPU time	132.48 seconds
Started	May 30 12:51:31 PM PDT 24
Finished	May 30 12:53:44 PM PDT 24
Peak memory	200272 kb
Host	smart-2aa4601a-9b2a-4560-822c-f88eb7809f04
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1783567998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1783567998
Directory	/workspace/25.uart_perf/latest

Test location	/workspace/coverage/default/25.uart_rx_oversample.640782807
Short name	T520
Test name
Test status
Simulation time	3492907723 ps
CPU time	27.05 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 12:51:56 PM PDT 24
Peak memory	198352 kb
Host	smart-d8f230b4-e823-49a2-b6f7-c76365d3ae5c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=640782807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.640782807
Directory	/workspace/25.uart_rx_oversample/latest

Test location	/workspace/coverage/default/25.uart_rx_parity_err.1222833908
Short name	T462
Test name
Test status
Simulation time	19327094901 ps
CPU time	31.53 seconds
Started	May 30 12:51:27 PM PDT 24
Finished	May 30 12:52:00 PM PDT 24
Peak memory	200276 kb
Host	smart-d0ef220a-c764-489f-8fd6-a8b41294d93b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222833908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1222833908
Directory	/workspace/25.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/25.uart_rx_start_bit_filter.2328413433
Short name	T946
Test name
Test status
Simulation time	42952766444 ps
CPU time	34.35 seconds
Started	May 30 12:51:27 PM PDT 24
Finished	May 30 12:52:02 PM PDT 24
Peak memory	196088 kb
Host	smart-b2334735-1f44-4132-ae98-249280d33c21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2328413433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2328413433
Directory	/workspace/25.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/25.uart_smoke.541454213
Short name	T303
Test name
Test status
Simulation time	752472609 ps
CPU time	2.1 seconds
Started	May 30 12:51:27 PM PDT 24
Finished	May 30 12:51:31 PM PDT 24
Peak memory	199992 kb
Host	smart-e77d11cc-1963-4e31-93f8-915568aa7f39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=541454213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.541454213
Directory	/workspace/25.uart_smoke/latest

Test location	/workspace/coverage/default/25.uart_stress_all.2131765075
Short name	T123
Test name
Test status
Simulation time	290918920984 ps
CPU time	533.37 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 01:00:22 PM PDT 24
Peak memory	200720 kb
Host	smart-bae667ba-da50-47e9-96e4-a2e9b7ade22f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131765075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2131765075
Directory	/workspace/25.uart_stress_all/latest

Test location	/workspace/coverage/default/25.uart_stress_all_with_rand_reset.3479808960
Short name	T187
Test name
Test status
Simulation time	174895001536 ps
CPU time	760.24 seconds
Started	May 30 12:51:27 PM PDT 24
Finished	May 30 01:04:09 PM PDT 24
Peak memory	225276 kb
Host	smart-a9a584a7-ffa0-4629-b59f-b42cc8d0536b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479808960 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3479808960
Directory	/workspace/25.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.uart_tx_ovrd.3536080588
Short name	T265
Test name
Test status
Simulation time	13570301261 ps
CPU time	17.36 seconds
Started	May 30 12:51:29 PM PDT 24
Finished	May 30 12:51:48 PM PDT 24
Peak memory	200252 kb
Host	smart-103466b3-dd62-4b33-a255-adf4677ae424
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3536080588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3536080588
Directory	/workspace/25.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/25.uart_tx_rx.981831944
Short name	T970
Test name
Test status
Simulation time	79915929793 ps
CPU time	16.46 seconds
Started	May 30 12:51:27 PM PDT 24
Finished	May 30 12:51:45 PM PDT 24
Peak memory	200376 kb
Host	smart-d0859b63-2124-421d-89ce-a35301e44bc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=981831944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.981831944
Directory	/workspace/25.uart_tx_rx/latest

Test location	/workspace/coverage/default/251.uart_fifo_reset.2016357073
Short name	T1071
Test name
Test status
Simulation time	76596784286 ps
CPU time	120.98 seconds
Started	May 30 12:54:35 PM PDT 24
Finished	May 30 12:56:37 PM PDT 24
Peak memory	200436 kb
Host	smart-0511c0a9-6864-460c-8844-e05f6f7c9577
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016357073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2016357073
Directory	/workspace/251.uart_fifo_reset/latest

Test location	/workspace/coverage/default/252.uart_fifo_reset.1843215934
Short name	T879
Test name
Test status
Simulation time	100829778263 ps
CPU time	174.57 seconds
Started	May 30 12:54:32 PM PDT 24
Finished	May 30 12:57:27 PM PDT 24
Peak memory	200300 kb
Host	smart-52192957-6500-426d-9b7a-61d8a978dcb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1843215934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1843215934
Directory	/workspace/252.uart_fifo_reset/latest

Test location	/workspace/coverage/default/253.uart_fifo_reset.1831045848
Short name	T892
Test name
Test status
Simulation time	86502916696 ps
CPU time	37.68 seconds
Started	May 30 12:54:34 PM PDT 24
Finished	May 30 12:55:13 PM PDT 24
Peak memory	200008 kb
Host	smart-878d6c56-bfa6-4058-9920-5f1d1df0ca9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831045848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1831045848
Directory	/workspace/253.uart_fifo_reset/latest

Test location	/workspace/coverage/default/254.uart_fifo_reset.855943272
Short name	T885
Test name
Test status
Simulation time	22867083217 ps
CPU time	38.88 seconds
Started	May 30 12:54:33 PM PDT 24
Finished	May 30 12:55:13 PM PDT 24
Peak memory	200116 kb
Host	smart-355ffb31-0d0a-430b-bcbc-90c29b6ad9eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=855943272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.855943272
Directory	/workspace/254.uart_fifo_reset/latest

Test location	/workspace/coverage/default/255.uart_fifo_reset.3221227559
Short name	T677
Test name
Test status
Simulation time	209552532942 ps
CPU time	428.91 seconds
Started	May 30 12:54:34 PM PDT 24
Finished	May 30 01:01:43 PM PDT 24
Peak memory	200300 kb
Host	smart-eda9c75a-4164-4d25-bba4-72babfa5e72b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3221227559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3221227559
Directory	/workspace/255.uart_fifo_reset/latest

Test location	/workspace/coverage/default/256.uart_fifo_reset.4078200064
Short name	T1096
Test name
Test status
Simulation time	129531758353 ps
CPU time	646.27 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 01:05:36 PM PDT 24
Peak memory	200228 kb
Host	smart-8b930933-152a-4e78-a964-2e9c1720c187
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078200064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.4078200064
Directory	/workspace/256.uart_fifo_reset/latest

Test location	/workspace/coverage/default/257.uart_fifo_reset.1231443039
Short name	T734
Test name
Test status
Simulation time	127138779161 ps
CPU time	259.52 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 12:59:09 PM PDT 24
Peak memory	200344 kb
Host	smart-37e35335-ba8b-4779-9fec-baac62becdb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231443039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1231443039
Directory	/workspace/257.uart_fifo_reset/latest

Test location	/workspace/coverage/default/259.uart_fifo_reset.492629524
Short name	T1138
Test name
Test status
Simulation time	28874176758 ps
CPU time	28.53 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 12:55:18 PM PDT 24
Peak memory	199364 kb
Host	smart-bf5cf7e1-dec8-48fa-9167-0de4f3216c4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=492629524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.492629524
Directory	/workspace/259.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_alert_test.942679975
Short name	T418
Test name
Test status
Simulation time	26891678 ps
CPU time	0.56 seconds
Started	May 30 12:51:31 PM PDT 24
Finished	May 30 12:51:32 PM PDT 24
Peak memory	195668 kb
Host	smart-427122ce-3f9e-4f2b-9f97-783476d04e97
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942679975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.942679975
Directory	/workspace/26.uart_alert_test/latest

Test location	/workspace/coverage/default/26.uart_fifo_full.798584696
Short name	T690
Test name
Test status
Simulation time	158511840216 ps
CPU time	44.71 seconds
Started	May 30 12:51:26 PM PDT 24
Finished	May 30 12:52:11 PM PDT 24
Peak memory	200332 kb
Host	smart-d541a155-0b71-4372-9694-eee4714ae3f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=798584696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.798584696
Directory	/workspace/26.uart_fifo_full/latest

Test location	/workspace/coverage/default/26.uart_fifo_overflow.4178750884
Short name	T831
Test name
Test status
Simulation time	126029739162 ps
CPU time	103.44 seconds
Started	May 30 12:51:27 PM PDT 24
Finished	May 30 12:53:12 PM PDT 24
Peak memory	200312 kb
Host	smart-6d26b8de-58cf-4edc-a7ac-ed5306f31ad7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4178750884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.4178750884
Directory	/workspace/26.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/26.uart_fifo_reset.1809907706
Short name	T404
Test name
Test status
Simulation time	17415132566 ps
CPU time	26.27 seconds
Started	May 30 12:51:29 PM PDT 24
Finished	May 30 12:51:57 PM PDT 24
Peak memory	200312 kb
Host	smart-b8e46c14-fd96-4b82-bf21-9c6032a45067
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809907706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1809907706
Directory	/workspace/26.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_intr.2112595763
Short name	T610
Test name
Test status
Simulation time	31176692784 ps
CPU time	37.73 seconds
Started	May 30 12:51:29 PM PDT 24
Finished	May 30 12:52:08 PM PDT 24
Peak memory	200304 kb
Host	smart-66273294-36fd-43e2-9edc-59340e2ec7f4
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112595763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2112595763
Directory	/workspace/26.uart_intr/latest

Test location	/workspace/coverage/default/26.uart_long_xfer_wo_dly.3303461416
Short name	T40
Test name
Test status
Simulation time	127071454066 ps
CPU time	253.12 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 12:55:43 PM PDT 24
Peak memory	200392 kb
Host	smart-79cd79e0-fbd3-4c6d-93a4-2a00dfea7e3a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3303461416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3303461416
Directory	/workspace/26.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/26.uart_loopback.1264937387
Short name	T1153
Test name
Test status
Simulation time	278613545 ps
CPU time	0.89 seconds
Started	May 30 12:51:31 PM PDT 24
Finished	May 30 12:51:32 PM PDT 24
Peak memory	197388 kb
Host	smart-f6594386-7dc5-4eee-8462-d22550f5fc73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1264937387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1264937387
Directory	/workspace/26.uart_loopback/latest

Test location	/workspace/coverage/default/26.uart_noise_filter.132831132
Short name	T104
Test name
Test status
Simulation time	58880135337 ps
CPU time	86.3 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 12:52:56 PM PDT 24
Peak memory	199568 kb
Host	smart-b92213ac-0d9a-4254-8acf-7bd8105414bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=132831132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.132831132
Directory	/workspace/26.uart_noise_filter/latest

Test location	/workspace/coverage/default/26.uart_perf.473328658
Short name	T820
Test name
Test status
Simulation time	1506640643 ps
CPU time	41.01 seconds
Started	May 30 12:51:25 PM PDT 24
Finished	May 30 12:52:07 PM PDT 24
Peak memory	200304 kb
Host	smart-f1c678b7-cb1c-4b52-af22-ad42beb457a9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=473328658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.473328658
Directory	/workspace/26.uart_perf/latest

Test location	/workspace/coverage/default/26.uart_rx_oversample.1312941501
Short name	T599
Test name
Test status
Simulation time	1902932040 ps
CPU time	9.92 seconds
Started	May 30 12:51:32 PM PDT 24
Finished	May 30 12:51:42 PM PDT 24
Peak memory	199036 kb
Host	smart-13f6ff61-83f3-48c7-800a-84ad7219b2a6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1312941501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1312941501
Directory	/workspace/26.uart_rx_oversample/latest

Test location	/workspace/coverage/default/26.uart_rx_parity_err.2983779698
Short name	T277
Test name
Test status
Simulation time	124189578264 ps
CPU time	82.31 seconds
Started	May 30 12:51:30 PM PDT 24
Finished	May 30 12:52:53 PM PDT 24
Peak memory	200368 kb
Host	smart-ec2d550d-e5fc-4502-8b23-fd415534bf99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2983779698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2983779698
Directory	/workspace/26.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/26.uart_rx_start_bit_filter.3950355831
Short name	T854
Test name
Test status
Simulation time	2636549555 ps
CPU time	1.43 seconds
Started	May 30 12:51:26 PM PDT 24
Finished	May 30 12:51:28 PM PDT 24
Peak memory	195964 kb
Host	smart-2ba8085e-4af4-421e-84bf-68673e6134f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3950355831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3950355831
Directory	/workspace/26.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/26.uart_smoke.564268946
Short name	T403
Test name
Test status
Simulation time	447709032 ps
CPU time	1.92 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 12:51:32 PM PDT 24
Peak memory	198904 kb
Host	smart-2217688a-12d0-4761-b646-ac0f677ee624
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=564268946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.564268946
Directory	/workspace/26.uart_smoke/latest

Test location	/workspace/coverage/default/26.uart_stress_all.2518076105
Short name	T533
Test name
Test status
Simulation time	268783513530 ps
CPU time	491.53 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 12:59:41 PM PDT 24
Peak memory	208704 kb
Host	smart-8403dc89-b297-4d75-b962-86fe0e2f1d7a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518076105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2518076105
Directory	/workspace/26.uart_stress_all/latest

Test location	/workspace/coverage/default/26.uart_stress_all_with_rand_reset.2680652860
Short name	T36
Test name
Test status
Simulation time	175122542284 ps
CPU time	671.24 seconds
Started	May 30 12:51:27 PM PDT 24
Finished	May 30 01:02:40 PM PDT 24
Peak memory	216764 kb
Host	smart-8d4692ac-4871-4857-862e-f314989c3276
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680652860 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2680652860
Directory	/workspace/26.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.uart_tx_ovrd.4109558366
Short name	T453
Test name
Test status
Simulation time	1985028532 ps
CPU time	3.09 seconds
Started	May 30 12:51:30 PM PDT 24
Finished	May 30 12:51:34 PM PDT 24
Peak memory	199976 kb
Host	smart-5a58b3f1-5fa1-42d8-b49e-5341ff75e73e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4109558366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4109558366
Directory	/workspace/26.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/26.uart_tx_rx.3839712348
Short name	T731
Test name
Test status
Simulation time	6904247964 ps
CPU time	6.83 seconds
Started	May 30 12:51:25 PM PDT 24
Finished	May 30 12:51:33 PM PDT 24
Peak memory	198084 kb
Host	smart-bc4c75f8-c0e6-4abf-b99c-3fd2d6828c7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839712348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3839712348
Directory	/workspace/26.uart_tx_rx/latest

Test location	/workspace/coverage/default/260.uart_fifo_reset.3351549662
Short name	T2
Test name
Test status
Simulation time	51591210693 ps
CPU time	115.27 seconds
Started	May 30 12:54:47 PM PDT 24
Finished	May 30 12:56:43 PM PDT 24
Peak memory	200320 kb
Host	smart-6784464c-f5e3-41bb-bc92-219d33604252
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3351549662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3351549662
Directory	/workspace/260.uart_fifo_reset/latest

Test location	/workspace/coverage/default/261.uart_fifo_reset.4058302414
Short name	T884
Test name
Test status
Simulation time	73134013590 ps
CPU time	170.22 seconds
Started	May 30 12:54:47 PM PDT 24
Finished	May 30 12:57:39 PM PDT 24
Peak memory	200300 kb
Host	smart-d6bb5215-783f-4dd1-83ec-89be91d755a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4058302414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.4058302414
Directory	/workspace/261.uart_fifo_reset/latest

Test location	/workspace/coverage/default/262.uart_fifo_reset.635160178
Short name	T364
Test name
Test status
Simulation time	36424994699 ps
CPU time	13.53 seconds
Started	May 30 12:54:52 PM PDT 24
Finished	May 30 12:55:06 PM PDT 24
Peak memory	199204 kb
Host	smart-d041adb3-82a6-4126-8d50-6b8aacd17d32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=635160178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.635160178
Directory	/workspace/262.uart_fifo_reset/latest

Test location	/workspace/coverage/default/263.uart_fifo_reset.3977003655
Short name	T121
Test name
Test status
Simulation time	289946253455 ps
CPU time	25.86 seconds
Started	May 30 12:54:46 PM PDT 24
Finished	May 30 12:55:13 PM PDT 24
Peak memory	200384 kb
Host	smart-f75d5c9b-e72f-443a-99fa-2c9853eb8116
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3977003655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3977003655
Directory	/workspace/263.uart_fifo_reset/latest

Test location	/workspace/coverage/default/264.uart_fifo_reset.672542147
Short name	T824
Test name
Test status
Simulation time	63405967624 ps
CPU time	23.34 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 12:55:12 PM PDT 24
Peak memory	200316 kb
Host	smart-d53c7ddb-c234-469f-be1d-0c899db47359
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=672542147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.672542147
Directory	/workspace/264.uart_fifo_reset/latest

Test location	/workspace/coverage/default/265.uart_fifo_reset.3521397793
Short name	T766
Test name
Test status
Simulation time	79529818222 ps
CPU time	60.97 seconds
Started	May 30 12:54:47 PM PDT 24
Finished	May 30 12:55:49 PM PDT 24
Peak memory	200340 kb
Host	smart-31e27bd5-94df-4b9e-aa53-c40ebf395ec2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521397793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3521397793
Directory	/workspace/265.uart_fifo_reset/latest

Test location	/workspace/coverage/default/266.uart_fifo_reset.2068474394
Short name	T893
Test name
Test status
Simulation time	81828000299 ps
CPU time	262.03 seconds
Started	May 30 12:54:45 PM PDT 24
Finished	May 30 12:59:08 PM PDT 24
Peak memory	200404 kb
Host	smart-b9a3e295-8fdc-4bb0-8607-ad8edb6586e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2068474394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2068474394
Directory	/workspace/266.uart_fifo_reset/latest

Test location	/workspace/coverage/default/268.uart_fifo_reset.4164038417
Short name	T1174
Test name
Test status
Simulation time	45685445715 ps
CPU time	22.17 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 12:55:11 PM PDT 24
Peak memory	200380 kb
Host	smart-1d1a4694-c303-4b04-b96b-31b431287428
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4164038417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.4164038417
Directory	/workspace/268.uart_fifo_reset/latest

Test location	/workspace/coverage/default/269.uart_fifo_reset.2807033951
Short name	T235
Test name
Test status
Simulation time	97147882885 ps
CPU time	83.2 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 12:56:12 PM PDT 24
Peak memory	200300 kb
Host	smart-4dde592f-07d6-430e-bbc7-0894bd541725
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2807033951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2807033951
Directory	/workspace/269.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_alert_test.1447180126
Short name	T586
Test name
Test status
Simulation time	15323778 ps
CPU time	0.54 seconds
Started	May 30 12:51:39 PM PDT 24
Finished	May 30 12:51:41 PM PDT 24
Peak memory	195736 kb
Host	smart-fbf3c9c8-9a95-42e6-9ce0-2c506a9c14ef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447180126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1447180126
Directory	/workspace/27.uart_alert_test/latest

Test location	/workspace/coverage/default/27.uart_fifo_full.1974177840
Short name	T261
Test name
Test status
Simulation time	69635951873 ps
CPU time	106.74 seconds
Started	May 30 12:51:27 PM PDT 24
Finished	May 30 12:53:15 PM PDT 24
Peak memory	200380 kb
Host	smart-01f14295-2ca5-4e90-8227-945e5ed0e08d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1974177840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1974177840
Directory	/workspace/27.uart_fifo_full/latest

Test location	/workspace/coverage/default/27.uart_fifo_overflow.240094798
Short name	T278
Test name
Test status
Simulation time	135751894301 ps
CPU time	59.63 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 12:52:30 PM PDT 24
Peak memory	200156 kb
Host	smart-bbdb76d5-6b3f-46f2-87f2-a517b1781e65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240094798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.240094798
Directory	/workspace/27.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/27.uart_fifo_reset.1970704466
Short name	T852
Test name
Test status
Simulation time	144249275431 ps
CPU time	120.38 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 12:53:30 PM PDT 24
Peak memory	200464 kb
Host	smart-3d8e0450-6474-4696-bc2a-52f0f8df2e77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1970704466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1970704466
Directory	/workspace/27.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_intr.980889572
Short name	T636
Test name
Test status
Simulation time	122204207229 ps
CPU time	134.7 seconds
Started	May 30 12:51:29 PM PDT 24
Finished	May 30 12:53:45 PM PDT 24
Peak memory	198460 kb
Host	smart-ec063973-4656-4bf8-867c-59ab736f2271
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980889572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.980889572
Directory	/workspace/27.uart_intr/latest

Test location	/workspace/coverage/default/27.uart_long_xfer_wo_dly.504319600
Short name	T522
Test name
Test status
Simulation time	176702964009 ps
CPU time	259.09 seconds
Started	May 30 12:51:40 PM PDT 24
Finished	May 30 12:56:00 PM PDT 24
Peak memory	200340 kb
Host	smart-521e4f58-2187-48fd-8870-797561136546
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=504319600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.504319600
Directory	/workspace/27.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/27.uart_loopback.1763881836
Short name	T645
Test name
Test status
Simulation time	1495970255 ps
CPU time	3.93 seconds
Started	May 30 12:51:26 PM PDT 24
Finished	May 30 12:51:31 PM PDT 24
Peak memory	199180 kb
Host	smart-4d2534b5-b604-4eba-b428-6424fe62c530
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1763881836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1763881836
Directory	/workspace/27.uart_loopback/latest

Test location	/workspace/coverage/default/27.uart_noise_filter.265319791
Short name	T768
Test name
Test status
Simulation time	45717039364 ps
CPU time	15.95 seconds
Started	May 30 12:51:29 PM PDT 24
Finished	May 30 12:51:47 PM PDT 24
Peak memory	195116 kb
Host	smart-ef465732-046b-43f9-b770-12af37fc4f62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265319791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.265319791
Directory	/workspace/27.uart_noise_filter/latest

Test location	/workspace/coverage/default/27.uart_perf.3334640738
Short name	T499
Test name
Test status
Simulation time	9783143332 ps
CPU time	81.66 seconds
Started	May 30 12:51:41 PM PDT 24
Finished	May 30 12:53:04 PM PDT 24
Peak memory	200368 kb
Host	smart-ab9d0a76-694b-4825-8c08-e52719c94eb1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3334640738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3334640738
Directory	/workspace/27.uart_perf/latest

Test location	/workspace/coverage/default/27.uart_rx_oversample.3439244076
Short name	T510
Test name
Test status
Simulation time	5903829771 ps
CPU time	15.09 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 12:51:44 PM PDT 24
Peak memory	200220 kb
Host	smart-ac639a77-bdb6-4434-a913-a50a59dca5d0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3439244076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3439244076
Directory	/workspace/27.uart_rx_oversample/latest

Test location	/workspace/coverage/default/27.uart_rx_parity_err.4185516962
Short name	T119
Test name
Test status
Simulation time	67358810691 ps
CPU time	26.31 seconds
Started	May 30 12:51:32 PM PDT 24
Finished	May 30 12:51:59 PM PDT 24
Peak memory	200300 kb
Host	smart-b6e49da4-a9ef-4431-a299-35557ac18fcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4185516962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.4185516962
Directory	/workspace/27.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/27.uart_rx_start_bit_filter.713202088
Short name	T1046
Test name
Test status
Simulation time	5096464236 ps
CPU time	1.52 seconds
Started	May 30 12:51:29 PM PDT 24
Finished	May 30 12:51:32 PM PDT 24
Peak memory	196384 kb
Host	smart-95a3aa2d-6392-4aa4-850f-2de4132ec41d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=713202088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.713202088
Directory	/workspace/27.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/27.uart_smoke.693163588
Short name	T1043
Test name
Test status
Simulation time	5490729475 ps
CPU time	21.08 seconds
Started	May 30 12:51:25 PM PDT 24
Finished	May 30 12:51:46 PM PDT 24
Peak memory	200036 kb
Host	smart-bbab12e5-286d-45c6-8f81-4dbfd2080bd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=693163588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.693163588
Directory	/workspace/27.uart_smoke/latest

Test location	/workspace/coverage/default/27.uart_stress_all.209509696
Short name	T858
Test name
Test status
Simulation time	730172510908 ps
CPU time	1052.69 seconds
Started	May 30 12:51:39 PM PDT 24
Finished	May 30 01:09:13 PM PDT 24
Peak memory	200360 kb
Host	smart-96bd3403-4ad6-4aab-956b-7694b54f3380
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209509696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.209509696
Directory	/workspace/27.uart_stress_all/latest

Test location	/workspace/coverage/default/27.uart_stress_all_with_rand_reset.2451610289
Short name	T115
Test name
Test status
Simulation time	92290137132 ps
CPU time	532.14 seconds
Started	May 30 12:51:40 PM PDT 24
Finished	May 30 01:00:33 PM PDT 24
Peak memory	216964 kb
Host	smart-99a819bf-8e47-4265-b57b-bc8364e8d31e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451610289 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2451610289
Directory	/workspace/27.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.uart_tx_ovrd.2883988351
Short name	T923
Test name
Test status
Simulation time	10381960994 ps
CPU time	5.87 seconds
Started	May 30 12:51:28 PM PDT 24
Finished	May 30 12:51:35 PM PDT 24
Peak memory	200316 kb
Host	smart-4125dffd-4666-4b18-aaa8-e11aec3e43be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2883988351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2883988351
Directory	/workspace/27.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/27.uart_tx_rx.1060487436
Short name	T527
Test name
Test status
Simulation time	146633516006 ps
CPU time	65.13 seconds
Started	May 30 12:51:30 PM PDT 24
Finished	May 30 12:52:36 PM PDT 24
Peak memory	200388 kb
Host	smart-098bdf8d-7a5c-4897-8d47-3a57eec052e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1060487436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1060487436
Directory	/workspace/27.uart_tx_rx/latest

Test location	/workspace/coverage/default/270.uart_fifo_reset.3018782500
Short name	T936
Test name
Test status
Simulation time	91479103477 ps
CPU time	382.58 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 01:01:12 PM PDT 24
Peak memory	200392 kb
Host	smart-8a44e4a8-d8cd-46dd-8b76-eb3f2361dafc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018782500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3018782500
Directory	/workspace/270.uart_fifo_reset/latest

Test location	/workspace/coverage/default/271.uart_fifo_reset.3785805800
Short name	T569
Test name
Test status
Simulation time	17249307950 ps
CPU time	31.85 seconds
Started	May 30 12:54:47 PM PDT 24
Finished	May 30 12:55:20 PM PDT 24
Peak memory	200412 kb
Host	smart-a6378eb6-1bad-4934-bde9-e1b7f34aea94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3785805800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3785805800
Directory	/workspace/271.uart_fifo_reset/latest

Test location	/workspace/coverage/default/272.uart_fifo_reset.1734290038
Short name	T41
Test name
Test status
Simulation time	9711292312 ps
CPU time	16.41 seconds
Started	May 30 12:54:46 PM PDT 24
Finished	May 30 12:55:04 PM PDT 24
Peak memory	199672 kb
Host	smart-3ac517c0-e298-45fe-bb77-9840a4adf230
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1734290038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1734290038
Directory	/workspace/272.uart_fifo_reset/latest

Test location	/workspace/coverage/default/273.uart_fifo_reset.2415576237
Short name	T1090
Test name
Test status
Simulation time	16961453576 ps
CPU time	12.98 seconds
Started	May 30 12:54:47 PM PDT 24
Finished	May 30 12:55:01 PM PDT 24
Peak memory	200376 kb
Host	smart-1587f152-09f6-4e34-9e84-19910d3ab765
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415576237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2415576237
Directory	/workspace/273.uart_fifo_reset/latest

Test location	/workspace/coverage/default/274.uart_fifo_reset.1305123221
Short name	T192
Test name
Test status
Simulation time	165061643392 ps
CPU time	45.85 seconds
Started	May 30 12:54:47 PM PDT 24
Finished	May 30 12:55:34 PM PDT 24
Peak memory	200188 kb
Host	smart-3b08b1a5-2b9c-46e9-8a55-91dd1be92b18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1305123221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1305123221
Directory	/workspace/274.uart_fifo_reset/latest

Test location	/workspace/coverage/default/275.uart_fifo_reset.602785416
Short name	T230
Test name
Test status
Simulation time	85366500701 ps
CPU time	120.85 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 12:56:50 PM PDT 24
Peak memory	200348 kb
Host	smart-6029158e-800f-486a-9df7-fbdec9b8809b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=602785416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.602785416
Directory	/workspace/275.uart_fifo_reset/latest

Test location	/workspace/coverage/default/276.uart_fifo_reset.889293255
Short name	T769
Test name
Test status
Simulation time	111071840882 ps
CPU time	158.64 seconds
Started	May 30 12:54:49 PM PDT 24
Finished	May 30 12:57:29 PM PDT 24
Peak memory	200300 kb
Host	smart-1c418995-4262-478c-949b-ecf0901960df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=889293255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.889293255
Directory	/workspace/276.uart_fifo_reset/latest

Test location	/workspace/coverage/default/277.uart_fifo_reset.1971206017
Short name	T195
Test name
Test status
Simulation time	40541422869 ps
CPU time	17.57 seconds
Started	May 30 12:54:46 PM PDT 24
Finished	May 30 12:55:04 PM PDT 24
Peak memory	199984 kb
Host	smart-22ce09d2-10fc-4410-8d76-a222ce6ada1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1971206017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1971206017
Directory	/workspace/277.uart_fifo_reset/latest

Test location	/workspace/coverage/default/278.uart_fifo_reset.4125075697
Short name	T1149
Test name
Test status
Simulation time	85263511588 ps
CPU time	18.02 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 12:55:07 PM PDT 24
Peak memory	200388 kb
Host	smart-8fab2271-31e7-4a1e-bd1e-8d6ce1e03151
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4125075697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.4125075697
Directory	/workspace/278.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_alert_test.3096512014
Short name	T24
Test name
Test status
Simulation time	15358316 ps
CPU time	0.55 seconds
Started	May 30 12:51:38 PM PDT 24
Finished	May 30 12:51:40 PM PDT 24
Peak memory	195760 kb
Host	smart-ca7fb50a-73ac-454a-a39f-162ab1418f2c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096512014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3096512014
Directory	/workspace/28.uart_alert_test/latest

Test location	/workspace/coverage/default/28.uart_fifo_full.839814261
Short name	T318
Test name
Test status
Simulation time	116008533028 ps
CPU time	112.69 seconds
Started	May 30 12:51:38 PM PDT 24
Finished	May 30 12:53:32 PM PDT 24
Peak memory	200380 kb
Host	smart-e56c0c14-613f-44f4-b891-7d6c3c287ea4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=839814261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.839814261
Directory	/workspace/28.uart_fifo_full/latest

Test location	/workspace/coverage/default/28.uart_fifo_overflow.1086090500
Short name	T543
Test name
Test status
Simulation time	30399694529 ps
CPU time	45.72 seconds
Started	May 30 12:51:44 PM PDT 24
Finished	May 30 12:52:30 PM PDT 24
Peak memory	200356 kb
Host	smart-35c89ad8-7b87-4003-a268-253f0bcf2c95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1086090500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1086090500
Directory	/workspace/28.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/28.uart_fifo_reset.2112608050
Short name	T1017
Test name
Test status
Simulation time	184264063744 ps
CPU time	56.18 seconds
Started	May 30 12:51:38 PM PDT 24
Finished	May 30 12:52:36 PM PDT 24
Peak memory	200288 kb
Host	smart-ed6e04c1-8615-4155-a4ae-12405b43a09a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2112608050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2112608050
Directory	/workspace/28.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_intr.1035618183
Short name	T924
Test name
Test status
Simulation time	57016837490 ps
CPU time	11.87 seconds
Started	May 30 12:51:38 PM PDT 24
Finished	May 30 12:51:51 PM PDT 24
Peak memory	200312 kb
Host	smart-75951724-5574-4b5d-8cc5-d15620d7f899
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035618183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1035618183
Directory	/workspace/28.uart_intr/latest

Test location	/workspace/coverage/default/28.uart_long_xfer_wo_dly.1441997789
Short name	T1081
Test name
Test status
Simulation time	149696469063 ps
CPU time	223.9 seconds
Started	May 30 12:51:38 PM PDT 24
Finished	May 30 12:55:23 PM PDT 24
Peak memory	200292 kb
Host	smart-20d3e225-2790-4742-9efe-9932436a8c5c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1441997789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1441997789
Directory	/workspace/28.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/28.uart_loopback.1944255193
Short name	T1133
Test name
Test status
Simulation time	5217319077 ps
CPU time	6.4 seconds
Started	May 30 12:51:45 PM PDT 24
Finished	May 30 12:51:52 PM PDT 24
Peak memory	200340 kb
Host	smart-caa20af3-b8bb-4fc1-8fda-b3dc3b4291b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1944255193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1944255193
Directory	/workspace/28.uart_loopback/latest

Test location	/workspace/coverage/default/28.uart_noise_filter.4277543682
Short name	T312
Test name
Test status
Simulation time	61206691142 ps
CPU time	94.81 seconds
Started	May 30 12:51:39 PM PDT 24
Finished	May 30 12:53:15 PM PDT 24
Peak memory	200544 kb
Host	smart-3398cb56-49e4-4ad6-8be0-6970f8062efe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4277543682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.4277543682
Directory	/workspace/28.uart_noise_filter/latest

Test location	/workspace/coverage/default/28.uart_perf.367371144
Short name	T1032
Test name
Test status
Simulation time	4991410072 ps
CPU time	132.49 seconds
Started	May 30 12:51:41 PM PDT 24
Finished	May 30 12:53:54 PM PDT 24
Peak memory	200316 kb
Host	smart-e813365b-fc3b-4e19-9e7a-6ccce88b358f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=367371144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.367371144
Directory	/workspace/28.uart_perf/latest

Test location	/workspace/coverage/default/28.uart_rx_oversample.723545516
Short name	T650
Test name
Test status
Simulation time	5842581022 ps
CPU time	4.58 seconds
Started	May 30 12:51:38 PM PDT 24
Finished	May 30 12:51:43 PM PDT 24
Peak memory	199328 kb
Host	smart-09ba5ab7-871c-4a3d-ad05-2e22d036523e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=723545516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.723545516
Directory	/workspace/28.uart_rx_oversample/latest

Test location	/workspace/coverage/default/28.uart_rx_parity_err.3145013310
Short name	T118
Test name
Test status
Simulation time	11165028953 ps
CPU time	20.31 seconds
Started	May 30 12:51:41 PM PDT 24
Finished	May 30 12:52:02 PM PDT 24
Peak memory	200140 kb
Host	smart-085dc1dc-846a-4304-bf4d-8e387ec4a5c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3145013310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3145013310
Directory	/workspace/28.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/28.uart_rx_start_bit_filter.83369391
Short name	T301
Test name
Test status
Simulation time	38908638133 ps
CPU time	62.1 seconds
Started	May 30 12:51:40 PM PDT 24
Finished	May 30 12:52:43 PM PDT 24
Peak memory	196436 kb
Host	smart-16d89974-2738-4f11-8fe1-71e5ae55e1c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83369391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.83369391
Directory	/workspace/28.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/28.uart_smoke.3082606402
Short name	T681
Test name
Test status
Simulation time	452626606 ps
CPU time	1.18 seconds
Started	May 30 12:51:37 PM PDT 24
Finished	May 30 12:51:39 PM PDT 24
Peak memory	200312 kb
Host	smart-c0712bd3-6c4f-46bb-b05c-d51984242434
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082606402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3082606402
Directory	/workspace/28.uart_smoke/latest

Test location	/workspace/coverage/default/28.uart_stress_all_with_rand_reset.3379956363
Short name	T62
Test name
Test status
Simulation time	473202102105 ps
CPU time	581.45 seconds
Started	May 30 12:51:39 PM PDT 24
Finished	May 30 01:01:22 PM PDT 24
Peak memory	216808 kb
Host	smart-75e52767-4b67-46d7-8794-9a5d3a7a9a24
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379956363 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3379956363
Directory	/workspace/28.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.uart_tx_ovrd.1727754931
Short name	T368
Test name
Test status
Simulation time	761089170 ps
CPU time	1.41 seconds
Started	May 30 12:51:41 PM PDT 24
Finished	May 30 12:51:43 PM PDT 24
Peak memory	198888 kb
Host	smart-3c4d52b8-015d-4af3-b36d-b9d860cf8531
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1727754931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1727754931
Directory	/workspace/28.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/28.uart_tx_rx.3959572127
Short name	T821
Test name
Test status
Simulation time	80851110606 ps
CPU time	130.63 seconds
Started	May 30 12:51:38 PM PDT 24
Finished	May 30 12:53:50 PM PDT 24
Peak memory	200340 kb
Host	smart-22a24a58-a0ce-44c5-9d71-2108408ff4b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3959572127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3959572127
Directory	/workspace/28.uart_tx_rx/latest

Test location	/workspace/coverage/default/280.uart_fifo_reset.1982260072
Short name	T590
Test name
Test status
Simulation time	73717151171 ps
CPU time	22.81 seconds
Started	May 30 12:54:50 PM PDT 24
Finished	May 30 12:55:13 PM PDT 24
Peak memory	200024 kb
Host	smart-389a12f9-189d-424d-bcbf-7fa7d7782dd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982260072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1982260072
Directory	/workspace/280.uart_fifo_reset/latest

Test location	/workspace/coverage/default/281.uart_fifo_reset.1839338522
Short name	T545
Test name
Test status
Simulation time	130868720871 ps
CPU time	81 seconds
Started	May 30 12:54:52 PM PDT 24
Finished	May 30 12:56:13 PM PDT 24
Peak memory	200400 kb
Host	smart-97529afc-5fc7-4a06-981e-5a748aea94e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1839338522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1839338522
Directory	/workspace/281.uart_fifo_reset/latest

Test location	/workspace/coverage/default/282.uart_fifo_reset.1820160643
Short name	T563
Test name
Test status
Simulation time	85538440622 ps
CPU time	37.22 seconds
Started	May 30 12:54:49 PM PDT 24
Finished	May 30 12:55:27 PM PDT 24
Peak memory	200304 kb
Host	smart-6e61e348-fe16-491c-a468-9ff9ffe539f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820160643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1820160643
Directory	/workspace/282.uart_fifo_reset/latest

Test location	/workspace/coverage/default/283.uart_fifo_reset.3717927581
Short name	T155
Test name
Test status
Simulation time	49560931531 ps
CPU time	40.06 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 12:55:29 PM PDT 24
Peak memory	200392 kb
Host	smart-75336d6a-a621-4a67-9402-7d445497c582
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3717927581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3717927581
Directory	/workspace/283.uart_fifo_reset/latest

Test location	/workspace/coverage/default/284.uart_fifo_reset.3582446300
Short name	T1092
Test name
Test status
Simulation time	48127340578 ps
CPU time	44.16 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 12:55:33 PM PDT 24
Peak memory	200388 kb
Host	smart-98fadae5-b9e0-40cc-8f94-59ad5b123dc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582446300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3582446300
Directory	/workspace/284.uart_fifo_reset/latest

Test location	/workspace/coverage/default/285.uart_fifo_reset.927331571
Short name	T190
Test name
Test status
Simulation time	47443708886 ps
CPU time	83.55 seconds
Started	May 30 12:54:44 PM PDT 24
Finished	May 30 12:56:08 PM PDT 24
Peak memory	200336 kb
Host	smart-510e2462-ec85-4beb-8f86-53c4426d2ed6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927331571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.927331571
Directory	/workspace/285.uart_fifo_reset/latest

Test location	/workspace/coverage/default/286.uart_fifo_reset.1846948748
Short name	T1175
Test name
Test status
Simulation time	73908420643 ps
CPU time	115.05 seconds
Started	May 30 12:54:50 PM PDT 24
Finished	May 30 12:56:45 PM PDT 24
Peak memory	200436 kb
Host	smart-9862b28d-8042-4e21-99e1-3c30b85f38ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846948748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1846948748
Directory	/workspace/286.uart_fifo_reset/latest

Test location	/workspace/coverage/default/289.uart_fifo_reset.2527519350
Short name	T816
Test name
Test status
Simulation time	137029000910 ps
CPU time	38.63 seconds
Started	May 30 12:54:50 PM PDT 24
Finished	May 30 12:55:29 PM PDT 24
Peak memory	200408 kb
Host	smart-127835a7-ded9-4629-9562-91bdd923fcc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527519350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2527519350
Directory	/workspace/289.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_alert_test.2485606950
Short name	T508
Test name
Test status
Simulation time	29807407 ps
CPU time	0.58 seconds
Started	May 30 12:51:39 PM PDT 24
Finished	May 30 12:51:41 PM PDT 24
Peak memory	195652 kb
Host	smart-22523822-9c88-4a43-870c-3fb5501fe950
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485606950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2485606950
Directory	/workspace/29.uart_alert_test/latest

Test location	/workspace/coverage/default/29.uart_fifo_full.1201514775
Short name	T511
Test name
Test status
Simulation time	141387235146 ps
CPU time	185.43 seconds
Started	May 30 12:51:40 PM PDT 24
Finished	May 30 12:54:46 PM PDT 24
Peak memory	200300 kb
Host	smart-21cc7594-35b5-4a06-8ff1-207669f624d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201514775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1201514775
Directory	/workspace/29.uart_fifo_full/latest

Test location	/workspace/coverage/default/29.uart_fifo_overflow.493647094
Short name	T558
Test name
Test status
Simulation time	306094994976 ps
CPU time	30.23 seconds
Started	May 30 12:51:46 PM PDT 24
Finished	May 30 12:52:17 PM PDT 24
Peak memory	200300 kb
Host	smart-aaf438a2-234d-4db2-9090-e7e5d7834c7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=493647094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.493647094
Directory	/workspace/29.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/29.uart_fifo_reset.3652759951
Short name	T51
Test name
Test status
Simulation time	20321943839 ps
CPU time	19.97 seconds
Started	May 30 12:51:38 PM PDT 24
Finished	May 30 12:51:59 PM PDT 24
Peak memory	200300 kb
Host	smart-20706538-3d2f-4873-b811-cc53e347d1c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3652759951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3652759951
Directory	/workspace/29.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_intr.1055302018
Short name	T780
Test name
Test status
Simulation time	195020910038 ps
CPU time	305.47 seconds
Started	May 30 12:51:40 PM PDT 24
Finished	May 30 12:56:46 PM PDT 24
Peak memory	198204 kb
Host	smart-5d48d922-6303-4b5d-aad6-872ee2361fc4
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055302018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1055302018
Directory	/workspace/29.uart_intr/latest

Test location	/workspace/coverage/default/29.uart_long_xfer_wo_dly.2004266381
Short name	T411
Test name
Test status
Simulation time	52643023471 ps
CPU time	466.01 seconds
Started	May 30 12:51:41 PM PDT 24
Finished	May 30 12:59:28 PM PDT 24
Peak memory	200232 kb
Host	smart-7ed00125-353e-463b-921f-8dfbe287d7a6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2004266381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2004266381
Directory	/workspace/29.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/29.uart_loopback.3810372326
Short name	T993
Test name
Test status
Simulation time	114458101 ps
CPU time	0.78 seconds
Started	May 30 12:51:43 PM PDT 24
Finished	May 30 12:51:44 PM PDT 24
Peak memory	196432 kb
Host	smart-bfc70f59-2023-446f-922d-9ae7fc7b7361
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3810372326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3810372326
Directory	/workspace/29.uart_loopback/latest

Test location	/workspace/coverage/default/29.uart_noise_filter.2355453210
Short name	T288
Test name
Test status
Simulation time	10107050001 ps
CPU time	17.06 seconds
Started	May 30 12:51:38 PM PDT 24
Finished	May 30 12:51:56 PM PDT 24
Peak memory	200564 kb
Host	smart-bc43f4ac-fd6a-406d-b89f-11231435fab9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2355453210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2355453210
Directory	/workspace/29.uart_noise_filter/latest

Test location	/workspace/coverage/default/29.uart_perf.1459498533
Short name	T798
Test name
Test status
Simulation time	12030099888 ps
CPU time	677.28 seconds
Started	May 30 12:51:39 PM PDT 24
Finished	May 30 01:02:58 PM PDT 24
Peak memory	200268 kb
Host	smart-13202088-1a34-4c76-964a-0b7f1f1336f9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1459498533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1459498533
Directory	/workspace/29.uart_perf/latest

Test location	/workspace/coverage/default/29.uart_rx_oversample.1368606432
Short name	T1040
Test name
Test status
Simulation time	2209380399 ps
CPU time	3.31 seconds
Started	May 30 12:51:37 PM PDT 24
Finished	May 30 12:51:41 PM PDT 24
Peak memory	198472 kb
Host	smart-085f7a9e-78ab-43e8-b7be-07a4c5dd8f3c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1368606432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1368606432
Directory	/workspace/29.uart_rx_oversample/latest

Test location	/workspace/coverage/default/29.uart_rx_parity_err.1148362983
Short name	T413
Test name
Test status
Simulation time	40022210634 ps
CPU time	64.23 seconds
Started	May 30 12:51:40 PM PDT 24
Finished	May 30 12:52:46 PM PDT 24
Peak memory	200192 kb
Host	smart-a794cce5-d6a4-46dc-be2d-3478e7f411c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148362983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1148362983
Directory	/workspace/29.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/29.uart_rx_start_bit_filter.3992276931
Short name	T313
Test name
Test status
Simulation time	2947315371 ps
CPU time	3.14 seconds
Started	May 30 12:51:38 PM PDT 24
Finished	May 30 12:51:43 PM PDT 24
Peak memory	196364 kb
Host	smart-cab44641-e5bb-42f3-bf91-3582b719e93d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3992276931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3992276931
Directory	/workspace/29.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/29.uart_smoke.3010553609
Short name	T306
Test name
Test status
Simulation time	507468361 ps
CPU time	2.3 seconds
Started	May 30 12:51:37 PM PDT 24
Finished	May 30 12:51:40 PM PDT 24
Peak memory	200180 kb
Host	smart-fe00998d-6999-41a1-bed1-f978177271eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3010553609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3010553609
Directory	/workspace/29.uart_smoke/latest

Test location	/workspace/coverage/default/29.uart_stress_all.3081476586
Short name	T1041
Test name
Test status
Simulation time	212477783193 ps
CPU time	193.47 seconds
Started	May 30 12:51:45 PM PDT 24
Finished	May 30 12:54:59 PM PDT 24
Peak memory	200324 kb
Host	smart-73c855f8-672f-4aa4-836a-b9ea9346cfca
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081476586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3081476586
Directory	/workspace/29.uart_stress_all/latest

Test location	/workspace/coverage/default/29.uart_tx_ovrd.3998695910
Short name	T688
Test name
Test status
Simulation time	1107330056 ps
CPU time	1.29 seconds
Started	May 30 12:51:39 PM PDT 24
Finished	May 30 12:51:42 PM PDT 24
Peak memory	199164 kb
Host	smart-f8b94c14-4afb-4719-bbbd-253ae45ccecf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3998695910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3998695910
Directory	/workspace/29.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/29.uart_tx_rx.3031444452
Short name	T847
Test name
Test status
Simulation time	294533834167 ps
CPU time	35.68 seconds
Started	May 30 12:51:37 PM PDT 24
Finished	May 30 12:52:13 PM PDT 24
Peak memory	200376 kb
Host	smart-7185bdc5-3911-40e2-bf75-1b12f02db709
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031444452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3031444452
Directory	/workspace/29.uart_tx_rx/latest

Test location	/workspace/coverage/default/290.uart_fifo_reset.1322797985
Short name	T243
Test name
Test status
Simulation time	28522072414 ps
CPU time	13.42 seconds
Started	May 30 12:54:50 PM PDT 24
Finished	May 30 12:55:04 PM PDT 24
Peak memory	200352 kb
Host	smart-5c9ef441-fd8e-40ce-9900-2048151c4aff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1322797985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1322797985
Directory	/workspace/290.uart_fifo_reset/latest

Test location	/workspace/coverage/default/291.uart_fifo_reset.2943390973
Short name	T307
Test name
Test status
Simulation time	92314569710 ps
CPU time	463.84 seconds
Started	May 30 12:54:52 PM PDT 24
Finished	May 30 01:02:36 PM PDT 24
Peak memory	199748 kb
Host	smart-362d30ce-932c-4b99-8607-af22544bd08d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2943390973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2943390973
Directory	/workspace/291.uart_fifo_reset/latest

Test location	/workspace/coverage/default/292.uart_fifo_reset.705099246
Short name	T942
Test name
Test status
Simulation time	160325496099 ps
CPU time	147.38 seconds
Started	May 30 12:54:52 PM PDT 24
Finished	May 30 12:57:20 PM PDT 24
Peak memory	199732 kb
Host	smart-feedb62c-7b0b-486f-9acf-0675c5e08beb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=705099246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.705099246
Directory	/workspace/292.uart_fifo_reset/latest

Test location	/workspace/coverage/default/293.uart_fifo_reset.3604417592
Short name	T218
Test name
Test status
Simulation time	214791694402 ps
CPU time	61.82 seconds
Started	May 30 12:54:52 PM PDT 24
Finished	May 30 12:55:54 PM PDT 24
Peak memory	200336 kb
Host	smart-cd6e72b9-3152-4b37-83d0-e219511f32a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3604417592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3604417592
Directory	/workspace/293.uart_fifo_reset/latest

Test location	/workspace/coverage/default/294.uart_fifo_reset.269148826
Short name	T735
Test name
Test status
Simulation time	27659353753 ps
CPU time	10.33 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 12:55:00 PM PDT 24
Peak memory	200372 kb
Host	smart-824e0e82-963a-44f9-9f74-13d4b72fa33c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=269148826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.269148826
Directory	/workspace/294.uart_fifo_reset/latest

Test location	/workspace/coverage/default/295.uart_fifo_reset.2100629432
Short name	T203
Test name
Test status
Simulation time	110456678233 ps
CPU time	396.55 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 01:01:26 PM PDT 24
Peak memory	200336 kb
Host	smart-b6e3ec38-d50c-4f31-ab08-46604be656a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2100629432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2100629432
Directory	/workspace/295.uart_fifo_reset/latest

Test location	/workspace/coverage/default/296.uart_fifo_reset.679009254
Short name	T197
Test name
Test status
Simulation time	22402738716 ps
CPU time	41.06 seconds
Started	May 30 12:54:52 PM PDT 24
Finished	May 30 12:55:34 PM PDT 24
Peak memory	200344 kb
Host	smart-0bc686c6-66fb-44ad-a8cc-713f3f1a5799
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=679009254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.679009254
Directory	/workspace/296.uart_fifo_reset/latest

Test location	/workspace/coverage/default/297.uart_fifo_reset.1310716877
Short name	T146
Test name
Test status
Simulation time	206589748794 ps
CPU time	381.11 seconds
Started	May 30 12:54:48 PM PDT 24
Finished	May 30 01:01:10 PM PDT 24
Peak memory	200376 kb
Host	smart-b5d94c51-53c5-4000-8042-1fadf0791683
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1310716877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1310716877
Directory	/workspace/297.uart_fifo_reset/latest

Test location	/workspace/coverage/default/298.uart_fifo_reset.1695751985
Short name	T938
Test name
Test status
Simulation time	137932283861 ps
CPU time	55.03 seconds
Started	May 30 12:54:50 PM PDT 24
Finished	May 30 12:55:45 PM PDT 24
Peak memory	200240 kb
Host	smart-40058a3b-66ab-498f-acfa-9f13794e714d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1695751985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1695751985
Directory	/workspace/298.uart_fifo_reset/latest

Test location	/workspace/coverage/default/299.uart_fifo_reset.660604714
Short name	T321
Test name
Test status
Simulation time	4404637876 ps
CPU time	17.99 seconds
Started	May 30 12:54:51 PM PDT 24
Finished	May 30 12:55:10 PM PDT 24
Peak memory	200240 kb
Host	smart-7824ece3-4c6b-4df8-a7be-1c3b788c56b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660604714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.660604714
Directory	/workspace/299.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_alert_test.2506081389
Short name	T913
Test name
Test status
Simulation time	22004172 ps
CPU time	0.59 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:50:12 PM PDT 24
Peak memory	195768 kb
Host	smart-df1fda70-0b6e-4c6f-ac23-e994bbc1edcf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506081389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2506081389
Directory	/workspace/3.uart_alert_test/latest

Test location	/workspace/coverage/default/3.uart_fifo_full.241851461
Short name	T164
Test name
Test status
Simulation time	88379661369 ps
CPU time	37.97 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:50:51 PM PDT 24
Peak memory	200376 kb
Host	smart-7f6a097b-3919-48b8-82ba-21244fb92b5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=241851461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.241851461
Directory	/workspace/3.uart_fifo_full/latest

Test location	/workspace/coverage/default/3.uart_fifo_overflow.2777850891
Short name	T168
Test name
Test status
Simulation time	150215099738 ps
CPU time	75.7 seconds
Started	May 30 12:50:12 PM PDT 24
Finished	May 30 12:51:30 PM PDT 24
Peak memory	200196 kb
Host	smart-13318b21-1148-4485-9ab0-95a3e538c475
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777850891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2777850891
Directory	/workspace/3.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/3.uart_fifo_reset.1933816538
Short name	T925
Test name
Test status
Simulation time	56448605826 ps
CPU time	64.12 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:51:18 PM PDT 24
Peak memory	200372 kb
Host	smart-47d96311-3a8a-40de-8870-4a4a84abda44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1933816538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1933816538
Directory	/workspace/3.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_intr.1890197393
Short name	T264
Test name
Test status
Simulation time	380023823296 ps
CPU time	474.44 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:58:08 PM PDT 24
Peak memory	200140 kb
Host	smart-7479d710-1b13-4654-b599-86f4165092db
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890197393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1890197393
Directory	/workspace/3.uart_intr/latest

Test location	/workspace/coverage/default/3.uart_long_xfer_wo_dly.1081049747
Short name	T521
Test name
Test status
Simulation time	61658904037 ps
CPU time	499.62 seconds
Started	May 30 12:50:12 PM PDT 24
Finished	May 30 12:58:33 PM PDT 24
Peak memory	200372 kb
Host	smart-a4929761-4a9a-4534-bb63-fd2a0910d1ff
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1081049747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1081049747
Directory	/workspace/3.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/3.uart_loopback.849443659
Short name	T987
Test name
Test status
Simulation time	4817600211 ps
CPU time	12.49 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:50:26 PM PDT 24
Peak memory	199132 kb
Host	smart-3fd048cd-9bcf-417e-9eac-0af312f9adc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=849443659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.849443659
Directory	/workspace/3.uart_loopback/latest

Test location	/workspace/coverage/default/3.uart_noise_filter.1505039826
Short name	T332
Test name
Test status
Simulation time	100328683698 ps
CPU time	180.62 seconds
Started	May 30 12:50:12 PM PDT 24
Finished	May 30 12:53:15 PM PDT 24
Peak memory	200440 kb
Host	smart-951c9a2d-c192-45e9-9a51-f4b4de9246fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505039826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1505039826
Directory	/workspace/3.uart_noise_filter/latest

Test location	/workspace/coverage/default/3.uart_perf.2532761183
Short name	T799
Test name
Test status
Simulation time	6821371703 ps
CPU time	68.95 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:51:21 PM PDT 24
Peak memory	200248 kb
Host	smart-723d1da8-8177-4578-bf91-295fe9cfc45f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2532761183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2532761183
Directory	/workspace/3.uart_perf/latest

Test location	/workspace/coverage/default/3.uart_rx_oversample.3796383084
Short name	T829
Test name
Test status
Simulation time	2020851759 ps
CPU time	3.66 seconds
Started	May 30 12:50:08 PM PDT 24
Finished	May 30 12:50:13 PM PDT 24
Peak memory	198404 kb
Host	smart-bcb4497e-2f9b-404d-9eba-791441145067
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3796383084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3796383084
Directory	/workspace/3.uart_rx_oversample/latest

Test location	/workspace/coverage/default/3.uart_rx_parity_err.2015924133
Short name	T464
Test name
Test status
Simulation time	16876065735 ps
CPU time	11.88 seconds
Started	May 30 12:50:08 PM PDT 24
Finished	May 30 12:50:22 PM PDT 24
Peak memory	200296 kb
Host	smart-40c73430-80c9-4e9c-947f-86a59824d7dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2015924133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2015924133
Directory	/workspace/3.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/3.uart_rx_start_bit_filter.405423991
Short name	T359
Test name
Test status
Simulation time	439426489 ps
CPU time	1.39 seconds
Started	May 30 12:50:09 PM PDT 24
Finished	May 30 12:50:13 PM PDT 24
Peak memory	195732 kb
Host	smart-273ed59f-b505-41de-83ce-9ccf332208e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=405423991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.405423991
Directory	/workspace/3.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/3.uart_sec_cm.88596081
Short name	T101
Test name
Test status
Simulation time	34201197 ps
CPU time	0.82 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:50:13 PM PDT 24
Peak memory	218400 kb
Host	smart-7c710455-ee3a-4dd5-9eae-0d6441ad6f06
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88596081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.88596081
Directory	/workspace/3.uart_sec_cm/latest

Test location	/workspace/coverage/default/3.uart_smoke.3579253234
Short name	T9
Test name
Test status
Simulation time	5755127823 ps
CPU time	15.94 seconds
Started	May 30 12:50:15 PM PDT 24
Finished	May 30 12:50:32 PM PDT 24
Peak memory	200200 kb
Host	smart-51746682-6fd7-44a6-8ae0-0e6084748cf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579253234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3579253234
Directory	/workspace/3.uart_smoke/latest

Test location	/workspace/coverage/default/3.uart_stress_all.1617915321
Short name	T1136
Test name
Test status
Simulation time	155789665910 ps
CPU time	178.36 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:53:10 PM PDT 24
Peak memory	200228 kb
Host	smart-d9029315-f911-4fff-93b7-0729786a0921
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617915321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1617915321
Directory	/workspace/3.uart_stress_all/latest

Test location	/workspace/coverage/default/3.uart_stress_all_with_rand_reset.103428296
Short name	T976
Test name
Test status
Simulation time	22559076033 ps
CPU time	283.92 seconds
Started	May 30 12:50:12 PM PDT 24
Finished	May 30 12:54:58 PM PDT 24
Peak memory	216928 kb
Host	smart-21f19f76-f341-42fe-92e4-7c28843dc9a9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103428296 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.103428296
Directory	/workspace/3.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.uart_tx_ovrd.44028315
Short name	T1184
Test name
Test status
Simulation time	984008376 ps
CPU time	2.84 seconds
Started	May 30 12:50:12 PM PDT 24
Finished	May 30 12:50:17 PM PDT 24
Peak memory	199152 kb
Host	smart-1e75380b-b4d0-414e-9fff-fad2f77d39a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44028315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.44028315
Directory	/workspace/3.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/3.uart_tx_rx.1296475030
Short name	T975
Test name
Test status
Simulation time	13666434906 ps
CPU time	5.46 seconds
Started	May 30 12:50:12 PM PDT 24
Finished	May 30 12:50:20 PM PDT 24
Peak memory	196900 kb
Host	smart-0ee51fef-cbe8-47e9-b20f-99276792f062
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296475030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1296475030
Directory	/workspace/3.uart_tx_rx/latest

Test location	/workspace/coverage/default/30.uart_alert_test.2009006782
Short name	T1169
Test name
Test status
Simulation time	20905118 ps
CPU time	0.56 seconds
Started	May 30 12:51:52 PM PDT 24
Finished	May 30 12:51:53 PM PDT 24
Peak memory	195692 kb
Host	smart-043e70fa-e379-49cf-bae3-6b236ed2c06b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009006782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2009006782
Directory	/workspace/30.uart_alert_test/latest

Test location	/workspace/coverage/default/30.uart_fifo_full.3644280316
Short name	T1001
Test name
Test status
Simulation time	110237156021 ps
CPU time	60.67 seconds
Started	May 30 12:51:40 PM PDT 24
Finished	May 30 12:52:41 PM PDT 24
Peak memory	200412 kb
Host	smart-64e4deb3-7993-45b4-bccc-011dd5ee519f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3644280316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3644280316
Directory	/workspace/30.uart_fifo_full/latest

Test location	/workspace/coverage/default/30.uart_fifo_overflow.2609873195
Short name	T1164
Test name
Test status
Simulation time	88634664673 ps
CPU time	129.48 seconds
Started	May 30 12:51:42 PM PDT 24
Finished	May 30 12:53:52 PM PDT 24
Peak memory	200268 kb
Host	smart-cf0bf2ca-cee8-4c7c-8942-fbf1bf3260ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2609873195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2609873195
Directory	/workspace/30.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/30.uart_fifo_reset.1180842278
Short name	T863
Test name
Test status
Simulation time	127328817145 ps
CPU time	14.81 seconds
Started	May 30 12:51:41 PM PDT 24
Finished	May 30 12:51:57 PM PDT 24
Peak memory	200276 kb
Host	smart-80d0b7c4-ed31-4e64-9f16-b2d944e59095
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1180842278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1180842278
Directory	/workspace/30.uart_fifo_reset/latest

Test location	/workspace/coverage/default/30.uart_intr.633193620
Short name	T1128
Test name
Test status
Simulation time	12777666995 ps
CPU time	23.98 seconds
Started	May 30 12:51:42 PM PDT 24
Finished	May 30 12:52:07 PM PDT 24
Peak memory	200252 kb
Host	smart-7b1c8b94-23d8-4c90-8225-71d2ec9187f5
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633193620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.633193620
Directory	/workspace/30.uart_intr/latest

Test location	/workspace/coverage/default/30.uart_long_xfer_wo_dly.1775866149
Short name	T542
Test name
Test status
Simulation time	92394801226 ps
CPU time	384.18 seconds
Started	May 30 12:51:50 PM PDT 24
Finished	May 30 12:58:16 PM PDT 24
Peak memory	200384 kb
Host	smart-f835fd13-e3bc-4b8e-a28a-05e5578969b5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1775866149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1775866149
Directory	/workspace/30.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/30.uart_loopback.3315344059
Short name	T504
Test name
Test status
Simulation time	484376194 ps
CPU time	1.29 seconds
Started	May 30 12:51:49 PM PDT 24
Finished	May 30 12:51:52 PM PDT 24
Peak memory	196240 kb
Host	smart-f0e45226-3ed6-4b42-beb5-2659e047027a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3315344059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3315344059
Directory	/workspace/30.uart_loopback/latest

Test location	/workspace/coverage/default/30.uart_noise_filter.1326564215
Short name	T344
Test name
Test status
Simulation time	32248610809 ps
CPU time	27.07 seconds
Started	May 30 12:51:39 PM PDT 24
Finished	May 30 12:52:07 PM PDT 24
Peak memory	200568 kb
Host	smart-34635b56-1c26-4527-89a0-cf10e66876f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1326564215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1326564215
Directory	/workspace/30.uart_noise_filter/latest

Test location	/workspace/coverage/default/30.uart_perf.3206690467
Short name	T619
Test name
Test status
Simulation time	16012154005 ps
CPU time	235.13 seconds
Started	May 30 12:51:51 PM PDT 24
Finished	May 30 12:55:47 PM PDT 24
Peak memory	200300 kb
Host	smart-ba94bc88-087c-43bb-9ba7-8413c7d66b3c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3206690467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3206690467
Directory	/workspace/30.uart_perf/latest

Test location	/workspace/coverage/default/30.uart_rx_oversample.10114622
Short name	T353
Test name
Test status
Simulation time	3818326247 ps
CPU time	15.97 seconds
Started	May 30 12:51:42 PM PDT 24
Finished	May 30 12:51:59 PM PDT 24
Peak memory	198532 kb
Host	smart-8b48fa3b-eb5e-43d4-a769-695118107a5a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=10114622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.10114622
Directory	/workspace/30.uart_rx_oversample/latest

Test location	/workspace/coverage/default/30.uart_rx_parity_err.2751401598
Short name	T560
Test name
Test status
Simulation time	113104507058 ps
CPU time	36.29 seconds
Started	May 30 12:51:50 PM PDT 24
Finished	May 30 12:52:27 PM PDT 24
Peak memory	200380 kb
Host	smart-3fc5c103-c7b5-44cb-8db7-def9fe4b8803
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2751401598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2751401598
Directory	/workspace/30.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/30.uart_rx_start_bit_filter.2552532840
Short name	T605
Test name
Test status
Simulation time	35503584191 ps
CPU time	53.46 seconds
Started	May 30 12:51:49 PM PDT 24
Finished	May 30 12:52:44 PM PDT 24
Peak memory	196068 kb
Host	smart-f6727287-267c-4f6e-9a14-0389ef5addec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2552532840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2552532840
Directory	/workspace/30.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/30.uart_smoke.1523015404
Short name	T819
Test name
Test status
Simulation time	283015573 ps
CPU time	1.54 seconds
Started	May 30 12:51:43 PM PDT 24
Finished	May 30 12:51:45 PM PDT 24
Peak memory	198632 kb
Host	smart-5228cfaa-9aed-4611-bc93-16d1fb8f8cc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1523015404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1523015404
Directory	/workspace/30.uart_smoke/latest

Test location	/workspace/coverage/default/30.uart_stress_all_with_rand_reset.4084742869
Short name	T1173
Test name
Test status
Simulation time	94904511642 ps
CPU time	446.89 seconds
Started	May 30 12:51:50 PM PDT 24
Finished	May 30 12:59:18 PM PDT 24
Peak memory	208648 kb
Host	smart-d09b2d57-ba30-41c6-970a-94ec44d62bf4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084742869 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.4084742869
Directory	/workspace/30.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.uart_tx_ovrd.3514354744
Short name	T475
Test name
Test status
Simulation time	7283490570 ps
CPU time	14.32 seconds
Started	May 30 12:51:51 PM PDT 24
Finished	May 30 12:52:06 PM PDT 24
Peak memory	199692 kb
Host	smart-b37d4290-46c3-4bfe-b6cd-d3f93f81318c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3514354744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3514354744
Directory	/workspace/30.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/30.uart_tx_rx.908451460
Short name	T425
Test name
Test status
Simulation time	47237999728 ps
CPU time	85.21 seconds
Started	May 30 12:51:45 PM PDT 24
Finished	May 30 12:53:11 PM PDT 24
Peak memory	200376 kb
Host	smart-b91b7b81-41ea-4871-8f5a-54013edf670a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=908451460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.908451460
Directory	/workspace/30.uart_tx_rx/latest

Test location	/workspace/coverage/default/31.uart_alert_test.859999382
Short name	T911
Test name
Test status
Simulation time	12258878 ps
CPU time	0.56 seconds
Started	May 30 12:51:51 PM PDT 24
Finished	May 30 12:51:53 PM PDT 24
Peak memory	195660 kb
Host	smart-8e9b8fff-dc0d-48a7-b410-77266fd62a1e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859999382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.859999382
Directory	/workspace/31.uart_alert_test/latest

Test location	/workspace/coverage/default/31.uart_fifo_full.3034434286
Short name	T664
Test name
Test status
Simulation time	37391063022 ps
CPU time	32.56 seconds
Started	May 30 12:51:50 PM PDT 24
Finished	May 30 12:52:23 PM PDT 24
Peak memory	200348 kb
Host	smart-8cae12f7-8a13-45f5-8bc9-2574d4701582
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3034434286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3034434286
Directory	/workspace/31.uart_fifo_full/latest

Test location	/workspace/coverage/default/31.uart_fifo_overflow.3315244346
Short name	T856
Test name
Test status
Simulation time	181421618535 ps
CPU time	45.06 seconds
Started	May 30 12:51:54 PM PDT 24
Finished	May 30 12:52:40 PM PDT 24
Peak memory	200108 kb
Host	smart-23c12cdc-c0db-475c-b7e5-4fa2bbc0e82f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3315244346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3315244346
Directory	/workspace/31.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/31.uart_fifo_reset.364896946
Short name	T433
Test name
Test status
Simulation time	49084617097 ps
CPU time	33.09 seconds
Started	May 30 12:51:50 PM PDT 24
Finished	May 30 12:52:24 PM PDT 24
Peak memory	200420 kb
Host	smart-183dd271-d2b8-4362-9f87-97fa319d7677
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=364896946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.364896946
Directory	/workspace/31.uart_fifo_reset/latest

Test location	/workspace/coverage/default/31.uart_intr.2758549881
Short name	T49
Test name
Test status
Simulation time	27260912504 ps
CPU time	10.8 seconds
Started	May 30 12:51:51 PM PDT 24
Finished	May 30 12:52:03 PM PDT 24
Peak memory	198400 kb
Host	smart-ce78730b-0b45-49fc-8ab0-009b1ac6909e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758549881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2758549881
Directory	/workspace/31.uart_intr/latest

Test location	/workspace/coverage/default/31.uart_long_xfer_wo_dly.2003910363
Short name	T746
Test name
Test status
Simulation time	102068192579 ps
CPU time	297.55 seconds
Started	May 30 12:51:56 PM PDT 24
Finished	May 30 12:56:54 PM PDT 24
Peak memory	199888 kb
Host	smart-1d157676-726c-4069-ae6b-228a644474db
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2003910363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2003910363
Directory	/workspace/31.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/31.uart_loopback.106361479
Short name	T994
Test name
Test status
Simulation time	96575175 ps
CPU time	0.59 seconds
Started	May 30 12:51:55 PM PDT 24
Finished	May 30 12:51:56 PM PDT 24
Peak memory	196252 kb
Host	smart-387c33ae-6cbd-4d87-82a4-d7cd86cf5cc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=106361479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.106361479
Directory	/workspace/31.uart_loopback/latest

Test location	/workspace/coverage/default/31.uart_noise_filter.2574735153
Short name	T438
Test name
Test status
Simulation time	42970637120 ps
CPU time	332.77 seconds
Started	May 30 12:51:56 PM PDT 24
Finished	May 30 12:57:29 PM PDT 24
Peak memory	200060 kb
Host	smart-162639b2-79ce-4f58-8802-df2fbe02e02a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574735153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2574735153
Directory	/workspace/31.uart_noise_filter/latest

Test location	/workspace/coverage/default/31.uart_perf.1908749604
Short name	T1105
Test name
Test status
Simulation time	18778764572 ps
CPU time	272.01 seconds
Started	May 30 12:51:51 PM PDT 24
Finished	May 30 12:56:24 PM PDT 24
Peak memory	200388 kb
Host	smart-51726452-af13-4869-968c-6969491c2fda
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1908749604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1908749604
Directory	/workspace/31.uart_perf/latest

Test location	/workspace/coverage/default/31.uart_rx_oversample.921553275
Short name	T1176
Test name
Test status
Simulation time	3161213892 ps
CPU time	24.73 seconds
Started	May 30 12:51:50 PM PDT 24
Finished	May 30 12:52:15 PM PDT 24
Peak memory	198488 kb
Host	smart-47405a00-a060-4e17-ba1e-2711f27c1848
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=921553275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.921553275
Directory	/workspace/31.uart_rx_oversample/latest

Test location	/workspace/coverage/default/31.uart_rx_parity_err.1717936071
Short name	T161
Test name
Test status
Simulation time	72690537293 ps
CPU time	100.1 seconds
Started	May 30 12:51:50 PM PDT 24
Finished	May 30 12:53:31 PM PDT 24
Peak memory	200220 kb
Host	smart-1c265cc5-f909-405e-bafb-a7bc73746839
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1717936071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1717936071
Directory	/workspace/31.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/31.uart_rx_start_bit_filter.1719553020
Short name	T795
Test name
Test status
Simulation time	44251515849 ps
CPU time	70.13 seconds
Started	May 30 12:51:51 PM PDT 24
Finished	May 30 12:53:02 PM PDT 24
Peak memory	196376 kb
Host	smart-df0dd28d-465a-45ab-b496-f4138f0e087e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719553020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1719553020
Directory	/workspace/31.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/31.uart_smoke.650921400
Short name	T367
Test name
Test status
Simulation time	692316451 ps
CPU time	1.54 seconds
Started	May 30 12:51:49 PM PDT 24
Finished	May 30 12:51:51 PM PDT 24
Peak memory	200008 kb
Host	smart-254ba92c-f824-4e64-a6bc-cd036aa707e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=650921400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.650921400
Directory	/workspace/31.uart_smoke/latest

Test location	/workspace/coverage/default/31.uart_stress_all.2476356748
Short name	T383
Test name
Test status
Simulation time	36914507614 ps
CPU time	16.29 seconds
Started	May 30 12:51:54 PM PDT 24
Finished	May 30 12:52:11 PM PDT 24
Peak memory	200308 kb
Host	smart-b79f4319-a6b5-4fb8-9b66-52c316e9a5fa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476356748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2476356748
Directory	/workspace/31.uart_stress_all/latest

Test location	/workspace/coverage/default/31.uart_stress_all_with_rand_reset.3891380308
Short name	T64
Test name
Test status
Simulation time	180739912376 ps
CPU time	771.55 seconds
Started	May 30 12:51:52 PM PDT 24
Finished	May 30 01:04:45 PM PDT 24
Peak memory	228112 kb
Host	smart-399732c9-1683-4c2d-8e82-aba3bd0857e4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891380308 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3891380308
Directory	/workspace/31.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.uart_tx_ovrd.1781883839
Short name	T951
Test name
Test status
Simulation time	1210128501 ps
CPU time	1.9 seconds
Started	May 30 12:51:51 PM PDT 24
Finished	May 30 12:51:54 PM PDT 24
Peak memory	198956 kb
Host	smart-a421bf5f-a092-473e-bf10-de81e00c7080
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1781883839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1781883839
Directory	/workspace/31.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/31.uart_tx_rx.420269248
Short name	T566
Test name
Test status
Simulation time	58172762655 ps
CPU time	98.22 seconds
Started	May 30 12:51:54 PM PDT 24
Finished	May 30 12:53:32 PM PDT 24
Peak memory	200388 kb
Host	smart-8e6045b4-d78a-4a71-bbc5-5449f5367cf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=420269248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.420269248
Directory	/workspace/31.uart_tx_rx/latest

Test location	/workspace/coverage/default/32.uart_alert_test.3959818246
Short name	T943
Test name
Test status
Simulation time	102221198 ps
CPU time	0.53 seconds
Started	May 30 12:51:51 PM PDT 24
Finished	May 30 12:51:53 PM PDT 24
Peak memory	195764 kb
Host	smart-9bc90381-34c1-472c-af2b-ae03bf23b7de
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959818246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3959818246
Directory	/workspace/32.uart_alert_test/latest

Test location	/workspace/coverage/default/32.uart_fifo_full.1824379696
Short name	T548
Test name
Test status
Simulation time	47706410087 ps
CPU time	21.03 seconds
Started	May 30 12:51:57 PM PDT 24
Finished	May 30 12:52:18 PM PDT 24
Peak memory	200400 kb
Host	smart-9255f60f-f581-4b33-91e0-7016c361afab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1824379696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1824379696
Directory	/workspace/32.uart_fifo_full/latest

Test location	/workspace/coverage/default/32.uart_fifo_overflow.3283679473
Short name	T703
Test name
Test status
Simulation time	53647153982 ps
CPU time	89.69 seconds
Started	May 30 12:51:53 PM PDT 24
Finished	May 30 12:53:23 PM PDT 24
Peak memory	200280 kb
Host	smart-238dc40f-f29a-4ce0-b316-e414f0ba26c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3283679473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3283679473
Directory	/workspace/32.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/32.uart_fifo_reset.2431869412
Short name	T648
Test name
Test status
Simulation time	61457317516 ps
CPU time	100.78 seconds
Started	May 30 12:51:50 PM PDT 24
Finished	May 30 12:53:32 PM PDT 24
Peak memory	200336 kb
Host	smart-b0af6c21-29dc-4915-8156-9a70fb911784
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431869412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2431869412
Directory	/workspace/32.uart_fifo_reset/latest

Test location	/workspace/coverage/default/32.uart_intr.3519418297
Short name	T491
Test name
Test status
Simulation time	29868097207 ps
CPU time	11.78 seconds
Started	May 30 12:51:50 PM PDT 24
Finished	May 30 12:52:03 PM PDT 24
Peak memory	200212 kb
Host	smart-56fe5e54-9aed-49b8-9ef7-d42c343436d5
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519418297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3519418297
Directory	/workspace/32.uart_intr/latest

Test location	/workspace/coverage/default/32.uart_long_xfer_wo_dly.2566722177
Short name	T432
Test name
Test status
Simulation time	135527214299 ps
CPU time	269.96 seconds
Started	May 30 12:51:56 PM PDT 24
Finished	May 30 12:56:27 PM PDT 24
Peak memory	200380 kb
Host	smart-4a73200c-e6e0-405a-a614-261e92e52bd8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2566722177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2566722177
Directory	/workspace/32.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/32.uart_loopback.507386749
Short name	T1115
Test name
Test status
Simulation time	11981909608 ps
CPU time	4.6 seconds
Started	May 30 12:51:52 PM PDT 24
Finished	May 30 12:51:57 PM PDT 24
Peak memory	200396 kb
Host	smart-94f8908e-7ce7-4ae8-90e7-e273a9566491
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507386749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.507386749
Directory	/workspace/32.uart_loopback/latest

Test location	/workspace/coverage/default/32.uart_noise_filter.3974969734
Short name	T1066
Test name
Test status
Simulation time	57802239441 ps
CPU time	120.93 seconds
Started	May 30 12:51:52 PM PDT 24
Finished	May 30 12:53:54 PM PDT 24
Peak memory	199500 kb
Host	smart-26ba5867-d6d9-493a-8535-55f1f153266a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974969734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3974969734
Directory	/workspace/32.uart_noise_filter/latest

Test location	/workspace/coverage/default/32.uart_perf.63094694
Short name	T825
Test name
Test status
Simulation time	14931092430 ps
CPU time	348.31 seconds
Started	May 30 12:51:52 PM PDT 24
Finished	May 30 12:57:41 PM PDT 24
Peak memory	200316 kb
Host	smart-877d4b50-09e4-4993-b3cd-976dd7c2eaa5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=63094694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.63094694
Directory	/workspace/32.uart_perf/latest

Test location	/workspace/coverage/default/32.uart_rx_oversample.2035460726
Short name	T733
Test name
Test status
Simulation time	5282680314 ps
CPU time	20.91 seconds
Started	May 30 12:51:55 PM PDT 24
Finished	May 30 12:52:17 PM PDT 24
Peak memory	199624 kb
Host	smart-70480f8f-3004-48d5-b14f-afa38cd51bfa
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2035460726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2035460726
Directory	/workspace/32.uart_rx_oversample/latest

Test location	/workspace/coverage/default/32.uart_rx_parity_err.322424963
Short name	T620
Test name
Test status
Simulation time	121798693176 ps
CPU time	64.67 seconds
Started	May 30 12:51:51 PM PDT 24
Finished	May 30 12:52:56 PM PDT 24
Peak memory	200384 kb
Host	smart-e57c23a4-9637-486d-9e02-a14f0cad34e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322424963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.322424963
Directory	/workspace/32.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/32.uart_rx_start_bit_filter.3956852310
Short name	T968
Test name
Test status
Simulation time	843318489 ps
CPU time	2.09 seconds
Started	May 30 12:51:56 PM PDT 24
Finished	May 30 12:51:58 PM PDT 24
Peak memory	195648 kb
Host	smart-8ac8d08a-57af-49b8-9836-3ca40f0db286
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956852310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3956852310
Directory	/workspace/32.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/32.uart_smoke.3174450496
Short name	T1
Test name
Test status
Simulation time	478402719 ps
CPU time	2.5 seconds
Started	May 30 12:51:50 PM PDT 24
Finished	May 30 12:51:53 PM PDT 24
Peak memory	200000 kb
Host	smart-189ba376-25f3-4911-a423-a1018d766182
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3174450496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3174450496
Directory	/workspace/32.uart_smoke/latest

Test location	/workspace/coverage/default/32.uart_stress_all.2036050641
Short name	T845
Test name
Test status
Simulation time	228996841545 ps
CPU time	2701.53 seconds
Started	May 30 12:51:52 PM PDT 24
Finished	May 30 01:36:55 PM PDT 24
Peak memory	200380 kb
Host	smart-1b962c5c-cc32-40af-82e7-87d2e060b8d7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036050641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2036050641
Directory	/workspace/32.uart_stress_all/latest

Test location	/workspace/coverage/default/32.uart_stress_all_with_rand_reset.756756878
Short name	T603
Test name
Test status
Simulation time	420633523770 ps
CPU time	604.28 seconds
Started	May 30 12:51:51 PM PDT 24
Finished	May 30 01:01:57 PM PDT 24
Peak memory	225312 kb
Host	smart-e795dc52-a808-4c71-9e4e-cfe46da331e6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756756878 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.756756878
Directory	/workspace/32.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.uart_tx_ovrd.2109350104
Short name	T587
Test name
Test status
Simulation time	1516931568 ps
CPU time	1.88 seconds
Started	May 30 12:51:51 PM PDT 24
Finished	May 30 12:51:54 PM PDT 24
Peak memory	199088 kb
Host	smart-b9d79d4a-e98a-4c35-96b1-9a8b4de0120e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2109350104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2109350104
Directory	/workspace/32.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/32.uart_tx_rx.833119577
Short name	T1119
Test name
Test status
Simulation time	70818265624 ps
CPU time	40.02 seconds
Started	May 30 12:51:50 PM PDT 24
Finished	May 30 12:52:31 PM PDT 24
Peak memory	200304 kb
Host	smart-b33fc48f-a8bc-4ff1-8e84-e03b3162bbd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=833119577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.833119577
Directory	/workspace/32.uart_tx_rx/latest

Test location	/workspace/coverage/default/33.uart_alert_test.526939625
Short name	T1126
Test name
Test status
Simulation time	20133158 ps
CPU time	0.55 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:52:17 PM PDT 24
Peak memory	195644 kb
Host	smart-4b096716-056d-49a2-b7c8-89613fa370b0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526939625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.526939625
Directory	/workspace/33.uart_alert_test/latest

Test location	/workspace/coverage/default/33.uart_fifo_full.835032761
Short name	T1031
Test name
Test status
Simulation time	40141615808 ps
CPU time	21.59 seconds
Started	May 30 12:51:50 PM PDT 24
Finished	May 30 12:52:13 PM PDT 24
Peak memory	200276 kb
Host	smart-5c9350e1-16fe-4a3c-bec1-fc34685acd16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=835032761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.835032761
Directory	/workspace/33.uart_fifo_full/latest

Test location	/workspace/coverage/default/33.uart_fifo_overflow.4187714538
Short name	T582
Test name
Test status
Simulation time	198747406486 ps
CPU time	128.53 seconds
Started	May 30 12:51:51 PM PDT 24
Finished	May 30 12:54:01 PM PDT 24
Peak memory	200236 kb
Host	smart-7be54359-7f3b-4e0e-86d8-846b4f1753df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187714538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4187714538
Directory	/workspace/33.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/33.uart_fifo_reset.1796688836
Short name	T797
Test name
Test status
Simulation time	30251383101 ps
CPU time	53 seconds
Started	May 30 12:51:54 PM PDT 24
Finished	May 30 12:52:47 PM PDT 24
Peak memory	200288 kb
Host	smart-9ee5f1f8-f0a6-48a0-a9de-318df9cfee71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796688836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1796688836
Directory	/workspace/33.uart_fifo_reset/latest

Test location	/workspace/coverage/default/33.uart_intr.1698549183
Short name	T877
Test name
Test status
Simulation time	11588547235 ps
CPU time	22.69 seconds
Started	May 30 12:52:13 PM PDT 24
Finished	May 30 12:52:37 PM PDT 24
Peak memory	200284 kb
Host	smart-084bffe5-894e-4632-8a2c-1e7c085c2493
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698549183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1698549183
Directory	/workspace/33.uart_intr/latest

Test location	/workspace/coverage/default/33.uart_long_xfer_wo_dly.1874243764
Short name	T457
Test name
Test status
Simulation time	104523894541 ps
CPU time	630 seconds
Started	May 30 12:52:15 PM PDT 24
Finished	May 30 01:02:45 PM PDT 24
Peak memory	200208 kb
Host	smart-8ed1d399-6a0f-4409-8530-a1e8ecd189d7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1874243764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1874243764
Directory	/workspace/33.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/33.uart_loopback.1225322887
Short name	T699
Test name
Test status
Simulation time	4222592997 ps
CPU time	4.3 seconds
Started	May 30 12:52:14 PM PDT 24
Finished	May 30 12:52:19 PM PDT 24
Peak memory	200144 kb
Host	smart-1339b662-bf42-4735-b4e2-eabab0ea2270
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1225322887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1225322887
Directory	/workspace/33.uart_loopback/latest

Test location	/workspace/coverage/default/33.uart_noise_filter.1575384494
Short name	T1029
Test name
Test status
Simulation time	113857543316 ps
CPU time	51.83 seconds
Started	May 30 12:52:13 PM PDT 24
Finished	May 30 12:53:05 PM PDT 24
Peak memory	208548 kb
Host	smart-32c06a44-c559-4ac7-b7a7-ea4de201671e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575384494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1575384494
Directory	/workspace/33.uart_noise_filter/latest

Test location	/workspace/coverage/default/33.uart_perf.1636295705
Short name	T702
Test name
Test status
Simulation time	15136391683 ps
CPU time	280.92 seconds
Started	May 30 12:52:19 PM PDT 24
Finished	May 30 12:57:01 PM PDT 24
Peak memory	200328 kb
Host	smart-3d8751b8-2e44-497b-8356-14715eb5e90a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1636295705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1636295705
Directory	/workspace/33.uart_perf/latest

Test location	/workspace/coverage/default/33.uart_rx_oversample.955619092
Short name	T380
Test name
Test status
Simulation time	2216886897 ps
CPU time	12.24 seconds
Started	May 30 12:52:18 PM PDT 24
Finished	May 30 12:52:31 PM PDT 24
Peak memory	198556 kb
Host	smart-d6da01fc-df32-4278-9f68-ffe1b255068a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=955619092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.955619092
Directory	/workspace/33.uart_rx_oversample/latest

Test location	/workspace/coverage/default/33.uart_rx_parity_err.2802953
Short name	T1179
Test name
Test status
Simulation time	127658818279 ps
CPU time	109.34 seconds
Started	May 30 12:52:15 PM PDT 24
Finished	May 30 12:54:05 PM PDT 24
Peak memory	200296 kb
Host	smart-ee00e25e-91f5-4033-a7f7-b4cdb8712c06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2802953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2802953
Directory	/workspace/33.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/33.uart_rx_start_bit_filter.234363465
Short name	T298
Test name
Test status
Simulation time	1715620982 ps
CPU time	2.19 seconds
Started	May 30 12:52:13 PM PDT 24
Finished	May 30 12:52:15 PM PDT 24
Peak memory	195716 kb
Host	smart-a6d7ed45-c464-4b81-b497-df6b4cd7dd3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=234363465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.234363465
Directory	/workspace/33.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/33.uart_smoke.2758849507
Short name	T1047
Test name
Test status
Simulation time	5705698466 ps
CPU time	11.14 seconds
Started	May 30 12:51:52 PM PDT 24
Finished	May 30 12:52:04 PM PDT 24
Peak memory	199532 kb
Host	smart-58d1c315-949c-4fb5-9fac-720912f349e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758849507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2758849507
Directory	/workspace/33.uart_smoke/latest

Test location	/workspace/coverage/default/33.uart_stress_all.2629829910
Short name	T712
Test name
Test status
Simulation time	91904368646 ps
CPU time	82.44 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:53:39 PM PDT 24
Peak memory	200412 kb
Host	smart-1ea7ed47-646a-465e-b370-7c0d498292e1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629829910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2629829910
Directory	/workspace/33.uart_stress_all/latest

Test location	/workspace/coverage/default/33.uart_stress_all_with_rand_reset.3307245547
Short name	T716
Test name
Test status
Simulation time	75774248751 ps
CPU time	129.49 seconds
Started	May 30 12:52:14 PM PDT 24
Finished	May 30 12:54:24 PM PDT 24
Peak memory	208708 kb
Host	smart-9ab1ecf7-43b3-4138-bc83-f53959511a24
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307245547 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3307245547
Directory	/workspace/33.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.uart_tx_ovrd.577955145
Short name	T375
Test name
Test status
Simulation time	1031796775 ps
CPU time	3.33 seconds
Started	May 30 12:52:14 PM PDT 24
Finished	May 30 12:52:18 PM PDT 24
Peak memory	199020 kb
Host	smart-a8422de4-ea69-4e5f-8e30-2c1f902dbb49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=577955145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.577955145
Directory	/workspace/33.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/33.uart_tx_rx.720217075
Short name	T672
Test name
Test status
Simulation time	87349964789 ps
CPU time	35.41 seconds
Started	May 30 12:51:51 PM PDT 24
Finished	May 30 12:52:28 PM PDT 24
Peak memory	200424 kb
Host	smart-2e44f144-95a2-42b1-bd3c-79dd108d470b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=720217075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.720217075
Directory	/workspace/33.uart_tx_rx/latest

Test location	/workspace/coverage/default/34.uart_alert_test.4014669127
Short name	T639
Test name
Test status
Simulation time	16960653 ps
CPU time	0.55 seconds
Started	May 30 12:52:14 PM PDT 24
Finished	May 30 12:52:16 PM PDT 24
Peak memory	195028 kb
Host	smart-9acafd24-1d4b-4294-9419-36df4575c695
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014669127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.4014669127
Directory	/workspace/34.uart_alert_test/latest

Test location	/workspace/coverage/default/34.uart_fifo_full.1746648515
Short name	T3
Test name
Test status
Simulation time	53843225395 ps
CPU time	20.14 seconds
Started	May 30 12:52:18 PM PDT 24
Finished	May 30 12:52:39 PM PDT 24
Peak memory	200224 kb
Host	smart-e6a54864-d5c3-484d-9ec2-7c3aad958041
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1746648515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1746648515
Directory	/workspace/34.uart_fifo_full/latest

Test location	/workspace/coverage/default/34.uart_fifo_overflow.2873718442
Short name	T523
Test name
Test status
Simulation time	176550590311 ps
CPU time	298.36 seconds
Started	May 30 12:52:14 PM PDT 24
Finished	May 30 12:57:13 PM PDT 24
Peak memory	200288 kb
Host	smart-023e1fdd-d4ee-4036-a680-1b76cf3d9b01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2873718442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2873718442
Directory	/workspace/34.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/34.uart_fifo_reset.187737011
Short name	T524
Test name
Test status
Simulation time	71312278320 ps
CPU time	49.8 seconds
Started	May 30 12:52:14 PM PDT 24
Finished	May 30 12:53:05 PM PDT 24
Peak memory	200380 kb
Host	smart-19718d5a-8231-4458-bc78-14d0bc0ac9df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187737011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.187737011
Directory	/workspace/34.uart_fifo_reset/latest

Test location	/workspace/coverage/default/34.uart_intr.1611558610
Short name	T855
Test name
Test status
Simulation time	20605581602 ps
CPU time	7.51 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:52:25 PM PDT 24
Peak memory	197328 kb
Host	smart-520cce9d-c4fb-41f9-9415-d35625cf24a3
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611558610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1611558610
Directory	/workspace/34.uart_intr/latest

Test location	/workspace/coverage/default/34.uart_long_xfer_wo_dly.2775925695
Short name	T995
Test name
Test status
Simulation time	369691700459 ps
CPU time	272.73 seconds
Started	May 30 12:52:13 PM PDT 24
Finished	May 30 12:56:47 PM PDT 24
Peak memory	200212 kb
Host	smart-da0ec468-eec3-45c0-86ee-53a0be98340d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2775925695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2775925695
Directory	/workspace/34.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/34.uart_loopback.1838257897
Short name	T750
Test name
Test status
Simulation time	7524924113 ps
CPU time	7.66 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:52:24 PM PDT 24
Peak memory	200288 kb
Host	smart-7a257935-bcf8-494b-b255-f3c49c70303e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1838257897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1838257897
Directory	/workspace/34.uart_loopback/latest

Test location	/workspace/coverage/default/34.uart_noise_filter.224704939
Short name	T637
Test name
Test status
Simulation time	345527137725 ps
CPU time	125.31 seconds
Started	May 30 12:52:19 PM PDT 24
Finished	May 30 12:54:25 PM PDT 24
Peak memory	200560 kb
Host	smart-fc15c8a9-0b13-4013-9e0b-4dbc6339998f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=224704939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.224704939
Directory	/workspace/34.uart_noise_filter/latest

Test location	/workspace/coverage/default/34.uart_perf.3735264685
Short name	T763
Test name
Test status
Simulation time	22512960899 ps
CPU time	167.49 seconds
Started	May 30 12:52:17 PM PDT 24
Finished	May 30 12:55:06 PM PDT 24
Peak memory	200324 kb
Host	smart-c6f74c12-cab4-4a93-b532-4a389499a2bb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3735264685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3735264685
Directory	/workspace/34.uart_perf/latest

Test location	/workspace/coverage/default/34.uart_rx_oversample.2087817986
Short name	T363
Test name
Test status
Simulation time	1296441833 ps
CPU time	1.4 seconds
Started	May 30 12:52:13 PM PDT 24
Finished	May 30 12:52:15 PM PDT 24
Peak memory	198516 kb
Host	smart-e831ba7e-cd17-4523-8cf6-79c164ea9694
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2087817986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2087817986
Directory	/workspace/34.uart_rx_oversample/latest

Test location	/workspace/coverage/default/34.uart_rx_parity_err.1386740766
Short name	T1181
Test name
Test status
Simulation time	208804538583 ps
CPU time	31.04 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:52:48 PM PDT 24
Peak memory	200284 kb
Host	smart-d7e5df0b-81bb-4570-8847-d70d2cd9145c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1386740766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1386740766
Directory	/workspace/34.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/34.uart_rx_start_bit_filter.3748552055
Short name	T1086
Test name
Test status
Simulation time	26785879540 ps
CPU time	36.8 seconds
Started	May 30 12:52:15 PM PDT 24
Finished	May 30 12:52:53 PM PDT 24
Peak memory	196068 kb
Host	smart-6ce39ae2-b0e2-49d7-ba6d-5bffedb22a71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748552055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3748552055
Directory	/workspace/34.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/34.uart_smoke.4047172739
Short name	T741
Test name
Test status
Simulation time	534726962 ps
CPU time	1.29 seconds
Started	May 30 12:52:15 PM PDT 24
Finished	May 30 12:52:17 PM PDT 24
Peak memory	198596 kb
Host	smart-cfa80f3f-ee43-43b8-adde-7ff5b6195f7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4047172739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.4047172739
Directory	/workspace/34.uart_smoke/latest

Test location	/workspace/coverage/default/34.uart_stress_all.1438979416
Short name	T154
Test name
Test status
Simulation time	176747245594 ps
CPU time	54.91 seconds
Started	May 30 12:52:17 PM PDT 24
Finished	May 30 12:53:14 PM PDT 24
Peak memory	200316 kb
Host	smart-79cc8c9f-83d1-450f-92c2-cde3623f92a2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438979416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1438979416
Directory	/workspace/34.uart_stress_all/latest

Test location	/workspace/coverage/default/34.uart_stress_all_with_rand_reset.2095319605
Short name	T704
Test name
Test status
Simulation time	349491235681 ps
CPU time	949.52 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 01:08:07 PM PDT 24
Peak memory	216856 kb
Host	smart-f0727a74-cd2d-4ae8-b113-12a8e916394b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095319605 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2095319605
Directory	/workspace/34.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.uart_tx_ovrd.2464437939
Short name	T1113
Test name
Test status
Simulation time	1581248959 ps
CPU time	1.48 seconds
Started	May 30 12:52:13 PM PDT 24
Finished	May 30 12:52:16 PM PDT 24
Peak memory	199084 kb
Host	smart-b72e4eff-3fd5-45f8-ba71-9970fd35c752
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2464437939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2464437939
Directory	/workspace/34.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/34.uart_tx_rx.2025855576
Short name	T598
Test name
Test status
Simulation time	190336855045 ps
CPU time	52.49 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:53:10 PM PDT 24
Peak memory	200304 kb
Host	smart-368c1eda-5d06-4476-ab5a-12cc46c8ba7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025855576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2025855576
Directory	/workspace/34.uart_tx_rx/latest

Test location	/workspace/coverage/default/35.uart_alert_test.1827429167
Short name	T506
Test name
Test status
Simulation time	26216206 ps
CPU time	0.62 seconds
Started	May 30 12:52:17 PM PDT 24
Finished	May 30 12:52:19 PM PDT 24
Peak memory	195744 kb
Host	smart-3e5cef1e-76be-4b82-93aa-57cd1aac232c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827429167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1827429167
Directory	/workspace/35.uart_alert_test/latest

Test location	/workspace/coverage/default/35.uart_fifo_full.3348437036
Short name	T147
Test name
Test status
Simulation time	87726429674 ps
CPU time	122.74 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:54:20 PM PDT 24
Peak memory	200304 kb
Host	smart-50399496-1fcd-4c5d-9cf5-677e2092f402
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348437036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3348437036
Directory	/workspace/35.uart_fifo_full/latest

Test location	/workspace/coverage/default/35.uart_fifo_overflow.1457099565
Short name	T623
Test name
Test status
Simulation time	107173370934 ps
CPU time	278.28 seconds
Started	May 30 12:52:17 PM PDT 24
Finished	May 30 12:56:57 PM PDT 24
Peak memory	200188 kb
Host	smart-2928d1c1-d6a8-4947-8aa6-33a09bbd16db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457099565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1457099565
Directory	/workspace/35.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/35.uart_fifo_reset.1004016250
Short name	T983
Test name
Test status
Simulation time	37601333099 ps
CPU time	23.45 seconds
Started	May 30 12:52:15 PM PDT 24
Finished	May 30 12:52:40 PM PDT 24
Peak memory	200192 kb
Host	smart-eeb0d097-a9e4-4902-930a-a7078028a0bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004016250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1004016250
Directory	/workspace/35.uart_fifo_reset/latest

Test location	/workspace/coverage/default/35.uart_intr.750988046
Short name	T986
Test name
Test status
Simulation time	53178892967 ps
CPU time	20.69 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:52:37 PM PDT 24
Peak memory	200368 kb
Host	smart-20e074b0-585f-4309-8de5-107aedc2d200
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750988046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.750988046
Directory	/workspace/35.uart_intr/latest

Test location	/workspace/coverage/default/35.uart_long_xfer_wo_dly.565490762
Short name	T728
Test name
Test status
Simulation time	59255516173 ps
CPU time	343.17 seconds
Started	May 30 12:52:14 PM PDT 24
Finished	May 30 12:57:58 PM PDT 24
Peak memory	200312 kb
Host	smart-0d71b3a7-7cb0-4a29-ac2f-fd440c6b3208
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=565490762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.565490762
Directory	/workspace/35.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/35.uart_loopback.2707995803
Short name	T370
Test name
Test status
Simulation time	1190861170 ps
CPU time	1.15 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:52:19 PM PDT 24
Peak memory	196308 kb
Host	smart-3b839247-02d6-49a3-927e-b50d5f1508cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2707995803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2707995803
Directory	/workspace/35.uart_loopback/latest

Test location	/workspace/coverage/default/35.uart_noise_filter.1011856651
Short name	T625
Test name
Test status
Simulation time	82319663673 ps
CPU time	70.88 seconds
Started	May 30 12:52:17 PM PDT 24
Finished	May 30 12:53:29 PM PDT 24
Peak memory	200076 kb
Host	smart-913043aa-6ec6-4786-9538-4deb4cbdf103
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1011856651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1011856651
Directory	/workspace/35.uart_noise_filter/latest

Test location	/workspace/coverage/default/35.uart_perf.2937192595
Short name	T805
Test name
Test status
Simulation time	16891931756 ps
CPU time	963.83 seconds
Started	May 30 12:52:15 PM PDT 24
Finished	May 30 01:08:20 PM PDT 24
Peak memory	200360 kb
Host	smart-6f31f73e-30fb-4b91-a38c-bfbd674f44c5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2937192595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2937192595
Directory	/workspace/35.uart_perf/latest

Test location	/workspace/coverage/default/35.uart_rx_oversample.1320339492
Short name	T581
Test name
Test status
Simulation time	5548044226 ps
CPU time	46.24 seconds
Started	May 30 12:52:18 PM PDT 24
Finished	May 30 12:53:06 PM PDT 24
Peak memory	200248 kb
Host	smart-d6ebd3f1-5a2d-408f-b0e1-f81bd762afa8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1320339492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1320339492
Directory	/workspace/35.uart_rx_oversample/latest

Test location	/workspace/coverage/default/35.uart_rx_parity_err.394853377
Short name	T851
Test name
Test status
Simulation time	48512957881 ps
CPU time	74.12 seconds
Started	May 30 12:52:17 PM PDT 24
Finished	May 30 12:53:33 PM PDT 24
Peak memory	200280 kb
Host	smart-a1a009bc-ff82-4766-87e2-2a823cfa1e22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394853377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.394853377
Directory	/workspace/35.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/35.uart_rx_start_bit_filter.2984648000
Short name	T889
Test name
Test status
Simulation time	2695774106 ps
CPU time	1.81 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:52:19 PM PDT 24
Peak memory	196052 kb
Host	smart-e3c91eaa-5356-4f6b-94bd-b4bf5f9a59e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984648000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2984648000
Directory	/workspace/35.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/35.uart_smoke.724738766
Short name	T469
Test name
Test status
Simulation time	6190751170 ps
CPU time	15.14 seconds
Started	May 30 12:52:14 PM PDT 24
Finished	May 30 12:52:30 PM PDT 24
Peak memory	200048 kb
Host	smart-fbcda97d-f73b-415e-ac45-97304966bc74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724738766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.724738766
Directory	/workspace/35.uart_smoke/latest

Test location	/workspace/coverage/default/35.uart_stress_all_with_rand_reset.205458945
Short name	T990
Test name
Test status
Simulation time	66585991816 ps
CPU time	215.36 seconds
Started	May 30 12:52:14 PM PDT 24
Finished	May 30 12:55:50 PM PDT 24
Peak memory	208556 kb
Host	smart-a3df85bd-493e-48b3-9e3d-6ad43fa3f475
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205458945 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.205458945
Directory	/workspace/35.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.uart_tx_ovrd.3245332699
Short name	T806
Test name
Test status
Simulation time	648708207 ps
CPU time	2.31 seconds
Started	May 30 12:52:14 PM PDT 24
Finished	May 30 12:52:17 PM PDT 24
Peak memory	198764 kb
Host	smart-ead88f9d-f0f0-4ed0-86f1-44d0e0e5e6d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3245332699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3245332699
Directory	/workspace/35.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/35.uart_tx_rx.3845727241
Short name	T989
Test name
Test status
Simulation time	31518105777 ps
CPU time	17.33 seconds
Started	May 30 12:52:12 PM PDT 24
Finished	May 30 12:52:30 PM PDT 24
Peak memory	199808 kb
Host	smart-9e0ca52e-3451-4df4-8bfd-89f60c2d390e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3845727241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3845727241
Directory	/workspace/35.uart_tx_rx/latest

Test location	/workspace/coverage/default/36.uart_alert_test.1084920964
Short name	T509
Test name
Test status
Simulation time	12497332 ps
CPU time	0.52 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:52:18 PM PDT 24
Peak memory	194644 kb
Host	smart-de380519-bc29-479b-be72-6253a0de7809
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084920964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1084920964
Directory	/workspace/36.uart_alert_test/latest

Test location	/workspace/coverage/default/36.uart_fifo_full.937493677
Short name	T323
Test name
Test status
Simulation time	56013642971 ps
CPU time	97.16 seconds
Started	May 30 12:52:14 PM PDT 24
Finished	May 30 12:53:52 PM PDT 24
Peak memory	200332 kb
Host	smart-20233e20-5c27-4821-a561-7206f0f88033
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=937493677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.937493677
Directory	/workspace/36.uart_fifo_full/latest

Test location	/workspace/coverage/default/36.uart_fifo_overflow.920611619
Short name	T898
Test name
Test status
Simulation time	97455506159 ps
CPU time	56.38 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:53:14 PM PDT 24
Peak memory	200364 kb
Host	smart-c824d73c-ccbe-4dc4-be8f-48a04f84b9a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920611619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.920611619
Directory	/workspace/36.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/36.uart_fifo_reset.3673014560
Short name	T732
Test name
Test status
Simulation time	124755034895 ps
CPU time	67.89 seconds
Started	May 30 12:52:17 PM PDT 24
Finished	May 30 12:53:26 PM PDT 24
Peak memory	200320 kb
Host	smart-51dd7933-f0b6-46f9-9acb-4e79f6a532ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673014560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3673014560
Directory	/workspace/36.uart_fifo_reset/latest

Test location	/workspace/coverage/default/36.uart_intr.4230803640
Short name	T1088
Test name
Test status
Simulation time	50288508172 ps
CPU time	10.14 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:52:27 PM PDT 24
Peak memory	200284 kb
Host	smart-fcc6c5ab-e49d-4e3e-990e-1236823176a8
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230803640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.4230803640
Directory	/workspace/36.uart_intr/latest

Test location	/workspace/coverage/default/36.uart_long_xfer_wo_dly.212609552
Short name	T488
Test name
Test status
Simulation time	111199873958 ps
CPU time	506.57 seconds
Started	May 30 12:52:19 PM PDT 24
Finished	May 30 01:00:46 PM PDT 24
Peak memory	200388 kb
Host	smart-e2b6bb38-ffc9-4ffe-b6f8-d71363e779a0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=212609552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.212609552
Directory	/workspace/36.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/36.uart_loopback.2785271591
Short name	T19
Test name
Test status
Simulation time	1331289428 ps
CPU time	1.81 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:52:18 PM PDT 24
Peak memory	197656 kb
Host	smart-31d140ee-a343-46e4-9a54-33efafcb1cff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785271591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2785271591
Directory	/workspace/36.uart_loopback/latest

Test location	/workspace/coverage/default/36.uart_noise_filter.1119238536
Short name	T595
Test name
Test status
Simulation time	18304945105 ps
CPU time	31.69 seconds
Started	May 30 12:52:18 PM PDT 24
Finished	May 30 12:52:51 PM PDT 24
Peak memory	198652 kb
Host	smart-23190207-db53-47b6-baa8-697cc6443023
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1119238536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1119238536
Directory	/workspace/36.uart_noise_filter/latest

Test location	/workspace/coverage/default/36.uart_perf.2550722675
Short name	T957
Test name
Test status
Simulation time	13763608749 ps
CPU time	616.07 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 01:02:33 PM PDT 24
Peak memory	200340 kb
Host	smart-62f93608-ee6c-42ff-87a2-4ce537fa7130
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2550722675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2550722675
Directory	/workspace/36.uart_perf/latest

Test location	/workspace/coverage/default/36.uart_rx_oversample.3454098867
Short name	T890
Test name
Test status
Simulation time	1281430998 ps
CPU time	1.74 seconds
Started	May 30 12:52:17 PM PDT 24
Finished	May 30 12:52:20 PM PDT 24
Peak memory	196628 kb
Host	smart-2ac8608e-ad01-491d-ac60-00f9bc37b985
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3454098867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3454098867
Directory	/workspace/36.uart_rx_oversample/latest

Test location	/workspace/coverage/default/36.uart_rx_parity_err.2216949709
Short name	T748
Test name
Test status
Simulation time	152952761068 ps
CPU time	34.23 seconds
Started	May 30 12:52:17 PM PDT 24
Finished	May 30 12:52:52 PM PDT 24
Peak memory	200368 kb
Host	smart-20ac3553-44c5-4748-8375-9c751b092d54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2216949709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2216949709
Directory	/workspace/36.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/36.uart_rx_start_bit_filter.2447192594
Short name	T1014
Test name
Test status
Simulation time	45792746625 ps
CPU time	4.94 seconds
Started	May 30 12:52:18 PM PDT 24
Finished	May 30 12:52:24 PM PDT 24
Peak memory	196080 kb
Host	smart-c17a80be-5fac-4106-b662-e7689a8edacb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447192594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2447192594
Directory	/workspace/36.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/36.uart_smoke.1809821399
Short name	T687
Test name
Test status
Simulation time	584193171 ps
CPU time	0.85 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:52:18 PM PDT 24
Peak memory	198536 kb
Host	smart-73a20fa2-6736-4a73-84ea-c2bb17c7b0cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809821399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1809821399
Directory	/workspace/36.uart_smoke/latest

Test location	/workspace/coverage/default/36.uart_stress_all.3189369416
Short name	T420
Test name
Test status
Simulation time	113597660025 ps
CPU time	231.67 seconds
Started	May 30 12:52:21 PM PDT 24
Finished	May 30 12:56:13 PM PDT 24
Peak memory	200316 kb
Host	smart-af35069b-d4ba-44bb-bc60-3d7274e0f9a4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189369416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3189369416
Directory	/workspace/36.uart_stress_all/latest

Test location	/workspace/coverage/default/36.uart_stress_all_with_rand_reset.1858581203
Short name	T638
Test name
Test status
Simulation time	46248915565 ps
CPU time	458.64 seconds
Started	May 30 12:52:15 PM PDT 24
Finished	May 30 12:59:55 PM PDT 24
Peak memory	225244 kb
Host	smart-7e2fde6e-1299-42e5-8e10-0950f48f11d8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858581203 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1858581203
Directory	/workspace/36.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.uart_tx_ovrd.2970880937
Short name	T973
Test name
Test status
Simulation time	1093225470 ps
CPU time	4.64 seconds
Started	May 30 12:52:15 PM PDT 24
Finished	May 30 12:52:21 PM PDT 24
Peak memory	199228 kb
Host	smart-17be78c1-679d-4253-ad94-dfa43abe3f18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2970880937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2970880937
Directory	/workspace/36.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/36.uart_tx_rx.3313960562
Short name	T1150
Test name
Test status
Simulation time	25711818082 ps
CPU time	42.29 seconds
Started	May 30 12:52:19 PM PDT 24
Finished	May 30 12:53:02 PM PDT 24
Peak memory	200384 kb
Host	smart-9a36cff2-f21b-4255-8b67-9d8cfcc309ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3313960562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3313960562
Directory	/workspace/36.uart_tx_rx/latest

Test location	/workspace/coverage/default/37.uart_alert_test.2004295792
Short name	T512
Test name
Test status
Simulation time	61824515 ps
CPU time	0.55 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:52:34 PM PDT 24
Peak memory	195652 kb
Host	smart-02292c57-c705-44e3-9617-0ac82fd2094d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004295792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2004295792
Directory	/workspace/37.uart_alert_test/latest

Test location	/workspace/coverage/default/37.uart_fifo_full.3612854442
Short name	T337
Test name
Test status
Simulation time	86272953827 ps
CPU time	66.81 seconds
Started	May 30 12:52:16 PM PDT 24
Finished	May 30 12:53:24 PM PDT 24
Peak memory	200372 kb
Host	smart-07c227b9-71d8-4ba0-91ce-02f68b7d0f01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3612854442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3612854442
Directory	/workspace/37.uart_fifo_full/latest

Test location	/workspace/coverage/default/37.uart_fifo_overflow.4173502618
Short name	T778
Test name
Test status
Simulation time	161521002754 ps
CPU time	293.57 seconds
Started	May 30 12:52:17 PM PDT 24
Finished	May 30 12:57:12 PM PDT 24
Peak memory	200276 kb
Host	smart-25e8eea2-87bc-499d-beaa-7b1ab7821b96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4173502618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.4173502618
Directory	/workspace/37.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/37.uart_fifo_reset.1876445592
Short name	T1161
Test name
Test status
Simulation time	88960696500 ps
CPU time	106.06 seconds
Started	May 30 12:52:32 PM PDT 24
Finished	May 30 12:54:19 PM PDT 24
Peak memory	200296 kb
Host	smart-9009b246-90d8-4333-887e-980b77a1fa5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1876445592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1876445592
Directory	/workspace/37.uart_fifo_reset/latest

Test location	/workspace/coverage/default/37.uart_intr.1350655963
Short name	T331
Test name
Test status
Simulation time	18973318024 ps
CPU time	29.4 seconds
Started	May 30 12:52:31 PM PDT 24
Finished	May 30 12:53:02 PM PDT 24
Peak memory	196308 kb
Host	smart-822bbb7b-cc75-42f4-96fd-2a3e9f89cf1c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350655963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1350655963
Directory	/workspace/37.uart_intr/latest

Test location	/workspace/coverage/default/37.uart_long_xfer_wo_dly.4284457865
Short name	T1099
Test name
Test status
Simulation time	125846015190 ps
CPU time	349.54 seconds
Started	May 30 12:52:34 PM PDT 24
Finished	May 30 12:58:24 PM PDT 24
Peak memory	200292 kb
Host	smart-95b5b4d9-872d-4075-ab20-1b782d371e7d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4284457865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4284457865
Directory	/workspace/37.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/37.uart_loopback.2366066885
Short name	T689
Test name
Test status
Simulation time	13395813207 ps
CPU time	15.65 seconds
Started	May 30 12:52:29 PM PDT 24
Finished	May 30 12:52:46 PM PDT 24
Peak memory	200236 kb
Host	smart-ee6337c2-2625-451b-9700-c00925b9307f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2366066885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2366066885
Directory	/workspace/37.uart_loopback/latest

Test location	/workspace/coverage/default/37.uart_noise_filter.1800522976
Short name	T379
Test name
Test status
Simulation time	75210457116 ps
CPU time	32.68 seconds
Started	May 30 12:52:30 PM PDT 24
Finished	May 30 12:53:03 PM PDT 24
Peak memory	198740 kb
Host	smart-18a8c09e-cff1-4372-8554-06817e1e691e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800522976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1800522976
Directory	/workspace/37.uart_noise_filter/latest

Test location	/workspace/coverage/default/37.uart_perf.2168617439
Short name	T429
Test name
Test status
Simulation time	10621170239 ps
CPU time	152 seconds
Started	May 30 12:52:31 PM PDT 24
Finished	May 30 12:55:04 PM PDT 24
Peak memory	200296 kb
Host	smart-1ae45a5e-3940-4148-849d-8e2fd8aa226b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2168617439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2168617439
Directory	/workspace/37.uart_perf/latest

Test location	/workspace/coverage/default/37.uart_rx_oversample.4213543885
Short name	T991
Test name
Test status
Simulation time	5087340755 ps
CPU time	7.7 seconds
Started	May 30 12:52:30 PM PDT 24
Finished	May 30 12:52:39 PM PDT 24
Peak memory	198496 kb
Host	smart-7a677396-682f-4a98-b504-4e62452eebc1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4213543885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.4213543885
Directory	/workspace/37.uart_rx_oversample/latest

Test location	/workspace/coverage/default/37.uart_rx_parity_err.3501948657
Short name	T1084
Test name
Test status
Simulation time	132157194803 ps
CPU time	551.09 seconds
Started	May 30 12:52:30 PM PDT 24
Finished	May 30 01:01:42 PM PDT 24
Peak memory	200360 kb
Host	smart-a40fc96e-cf2f-40f1-b858-44f111f1caa3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501948657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3501948657
Directory	/workspace/37.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/37.uart_rx_start_bit_filter.2350190051
Short name	T609
Test name
Test status
Simulation time	44886649020 ps
CPU time	73.62 seconds
Started	May 30 12:52:29 PM PDT 24
Finished	May 30 12:53:43 PM PDT 24
Peak memory	196088 kb
Host	smart-713012c0-65f9-4ef6-ad62-de961226ec5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2350190051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2350190051
Directory	/workspace/37.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/37.uart_smoke.173524096
Short name	T955
Test name
Test status
Simulation time	564989199 ps
CPU time	2.73 seconds
Started	May 30 12:52:15 PM PDT 24
Finished	May 30 12:52:18 PM PDT 24
Peak memory	198552 kb
Host	smart-e896f983-8e5c-4268-8b76-828b727af7dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=173524096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.173524096
Directory	/workspace/37.uart_smoke/latest

Test location	/workspace/coverage/default/37.uart_stress_all_with_rand_reset.1702122505
Short name	T838
Test name
Test status
Simulation time	266800660326 ps
CPU time	790.45 seconds
Started	May 30 12:52:30 PM PDT 24
Finished	May 30 01:05:42 PM PDT 24
Peak memory	225368 kb
Host	smart-68e8d2ff-2f55-40c0-bc23-c3cb2c84649f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702122505 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1702122505
Directory	/workspace/37.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.uart_tx_ovrd.649041321
Short name	T1070
Test name
Test status
Simulation time	1376377724 ps
CPU time	1.83 seconds
Started	May 30 12:52:32 PM PDT 24
Finished	May 30 12:52:35 PM PDT 24
Peak memory	199860 kb
Host	smart-a4cab3b8-d523-4e13-89a6-de1d6277cf1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=649041321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.649041321
Directory	/workspace/37.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/37.uart_tx_rx.72954274
Short name	T1022
Test name
Test status
Simulation time	113394059252 ps
CPU time	225.06 seconds
Started	May 30 12:52:17 PM PDT 24
Finished	May 30 12:56:03 PM PDT 24
Peak memory	200360 kb
Host	smart-f4232578-e053-4d98-99cb-c75efe6161a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72954274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.72954274
Directory	/workspace/37.uart_tx_rx/latest

Test location	/workspace/coverage/default/38.uart_alert_test.1874981471
Short name	T959
Test name
Test status
Simulation time	76784485 ps
CPU time	0.54 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:52:35 PM PDT 24
Peak memory	195032 kb
Host	smart-1006004c-5001-4e0c-b7f7-39b78564749f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874981471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1874981471
Directory	/workspace/38.uart_alert_test/latest

Test location	/workspace/coverage/default/38.uart_fifo_full.3074321645
Short name	T280
Test name
Test status
Simulation time	65836031887 ps
CPU time	114.51 seconds
Started	May 30 12:52:34 PM PDT 24
Finished	May 30 12:54:29 PM PDT 24
Peak memory	200288 kb
Host	smart-5eda5d92-9b14-4446-9528-0bd5dd2fc8e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3074321645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3074321645
Directory	/workspace/38.uart_fifo_full/latest

Test location	/workspace/coverage/default/38.uart_fifo_overflow.3617759953
Short name	T171
Test name
Test status
Simulation time	30364043153 ps
CPU time	57.55 seconds
Started	May 30 12:52:31 PM PDT 24
Finished	May 30 12:53:29 PM PDT 24
Peak memory	200368 kb
Host	smart-bb46acc2-ac87-4a58-8c61-f857df28b27e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3617759953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3617759953
Directory	/workspace/38.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/38.uart_fifo_reset.2924959617
Short name	T160
Test name
Test status
Simulation time	48988233650 ps
CPU time	22.75 seconds
Started	May 30 12:52:32 PM PDT 24
Finished	May 30 12:52:56 PM PDT 24
Peak memory	200332 kb
Host	smart-970b56fe-c9aa-4270-9c8e-b306ebd9761d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924959617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2924959617
Directory	/workspace/38.uart_fifo_reset/latest

Test location	/workspace/coverage/default/38.uart_intr.2783093165
Short name	T1152
Test name
Test status
Simulation time	51477542143 ps
CPU time	26.75 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:53:01 PM PDT 24
Peak memory	200380 kb
Host	smart-a560a7ba-a416-407d-9f0f-6ab927262248
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783093165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2783093165
Directory	/workspace/38.uart_intr/latest

Test location	/workspace/coverage/default/38.uart_long_xfer_wo_dly.523721013
Short name	T874
Test name
Test status
Simulation time	91333301158 ps
CPU time	212.51 seconds
Started	May 30 12:52:35 PM PDT 24
Finished	May 30 12:56:09 PM PDT 24
Peak memory	200380 kb
Host	smart-2e834cab-3fef-4631-aa70-cc74c8b5f5aa
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=523721013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.523721013
Directory	/workspace/38.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/38.uart_loopback.1781504297
Short name	T900
Test name
Test status
Simulation time	8289206376 ps
CPU time	13.02 seconds
Started	May 30 12:52:35 PM PDT 24
Finished	May 30 12:52:49 PM PDT 24
Peak memory	200320 kb
Host	smart-f8bee18d-3a6f-467d-945f-f51baf50aaf2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1781504297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1781504297
Directory	/workspace/38.uart_loopback/latest

Test location	/workspace/coverage/default/38.uart_noise_filter.2845661376
Short name	T758
Test name
Test status
Simulation time	109621735915 ps
CPU time	193.7 seconds
Started	May 30 12:52:30 PM PDT 24
Finished	May 30 12:55:44 PM PDT 24
Peak memory	200032 kb
Host	smart-d1176f7d-a266-4efe-b00d-fd03b6c5c8bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2845661376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2845661376
Directory	/workspace/38.uart_noise_filter/latest

Test location	/workspace/coverage/default/38.uart_perf.1170108520
Short name	T629
Test name
Test status
Simulation time	18744429625 ps
CPU time	245.39 seconds
Started	May 30 12:52:30 PM PDT 24
Finished	May 30 12:56:36 PM PDT 24
Peak memory	200400 kb
Host	smart-7d62061a-3844-4377-80e9-24a002a8f397
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1170108520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1170108520
Directory	/workspace/38.uart_perf/latest

Test location	/workspace/coverage/default/38.uart_rx_oversample.2681452137
Short name	T435
Test name
Test status
Simulation time	2621027419 ps
CPU time	20.39 seconds
Started	May 30 12:52:32 PM PDT 24
Finished	May 30 12:52:53 PM PDT 24
Peak memory	198396 kb
Host	smart-9018e95a-1c9e-41d3-8649-ea81374b4c2d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2681452137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2681452137
Directory	/workspace/38.uart_rx_oversample/latest

Test location	/workspace/coverage/default/38.uart_rx_parity_err.2214533127
Short name	T1110
Test name
Test status
Simulation time	37315455260 ps
CPU time	33.13 seconds
Started	May 30 12:52:32 PM PDT 24
Finished	May 30 12:53:06 PM PDT 24
Peak memory	200304 kb
Host	smart-8405431a-a156-41df-b45a-7f14a80efedb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2214533127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2214533127
Directory	/workspace/38.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/38.uart_rx_start_bit_filter.3252113123
Short name	T487
Test name
Test status
Simulation time	508973244 ps
CPU time	1.3 seconds
Started	May 30 12:52:39 PM PDT 24
Finished	May 30 12:52:41 PM PDT 24
Peak memory	195728 kb
Host	smart-0ba9eeb9-6c73-47c0-85ab-189d97978458
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3252113123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3252113123
Directory	/workspace/38.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/38.uart_smoke.744120917
Short name	T729
Test name
Test status
Simulation time	5966192555 ps
CPU time	18.54 seconds
Started	May 30 12:52:30 PM PDT 24
Finished	May 30 12:52:50 PM PDT 24
Peak memory	199868 kb
Host	smart-7f83ae61-291c-4d94-bd07-f132a98a88d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744120917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.744120917
Directory	/workspace/38.uart_smoke/latest

Test location	/workspace/coverage/default/38.uart_stress_all_with_rand_reset.2130797349
Short name	T61
Test name
Test status
Simulation time	43593702229 ps
CPU time	274.43 seconds
Started	May 30 12:52:31 PM PDT 24
Finished	May 30 12:57:06 PM PDT 24
Peak memory	216260 kb
Host	smart-577910fd-13de-4e84-9980-db6dc65ab852
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130797349 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2130797349
Directory	/workspace/38.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.uart_tx_ovrd.1886835913
Short name	T1016
Test name
Test status
Simulation time	7495307136 ps
CPU time	8.67 seconds
Started	May 30 12:52:30 PM PDT 24
Finished	May 30 12:52:40 PM PDT 24
Peak memory	199532 kb
Host	smart-017ae0c0-0245-45fd-8c54-62c6592dbbf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886835913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1886835913
Directory	/workspace/38.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/39.uart_alert_test.3144146767
Short name	T580
Test name
Test status
Simulation time	12948098 ps
CPU time	0.55 seconds
Started	May 30 12:52:32 PM PDT 24
Finished	May 30 12:52:34 PM PDT 24
Peak memory	195120 kb
Host	smart-b6544361-595b-47e5-8a66-06e1f1dacfcd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144146767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3144146767
Directory	/workspace/39.uart_alert_test/latest

Test location	/workspace/coverage/default/39.uart_fifo_full.3363977936
Short name	T158
Test name
Test status
Simulation time	403439032315 ps
CPU time	99.56 seconds
Started	May 30 12:52:30 PM PDT 24
Finished	May 30 12:54:11 PM PDT 24
Peak memory	200292 kb
Host	smart-3732adfb-4db1-4ee4-ade7-0a59e5aa632a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363977936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3363977936
Directory	/workspace/39.uart_fifo_full/latest

Test location	/workspace/coverage/default/39.uart_fifo_overflow.3514367372
Short name	T944
Test name
Test status
Simulation time	31732844722 ps
CPU time	13.43 seconds
Started	May 30 12:52:32 PM PDT 24
Finished	May 30 12:52:46 PM PDT 24
Peak memory	200352 kb
Host	smart-11adc5d5-a293-47aa-973b-e4c701367bfa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3514367372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3514367372
Directory	/workspace/39.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/39.uart_fifo_reset.2471037881
Short name	T477
Test name
Test status
Simulation time	10534019228 ps
CPU time	10.95 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:52:45 PM PDT 24
Peak memory	200332 kb
Host	smart-10100a50-cb67-407c-bee9-c591de5da758
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2471037881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2471037881
Directory	/workspace/39.uart_fifo_reset/latest

Test location	/workspace/coverage/default/39.uart_intr.3775940421
Short name	T282
Test name
Test status
Simulation time	33972401623 ps
CPU time	9.99 seconds
Started	May 30 12:52:31 PM PDT 24
Finished	May 30 12:52:42 PM PDT 24
Peak memory	200380 kb
Host	smart-8b57313a-db0d-4d99-a24d-f97843e6543f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775940421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3775940421
Directory	/workspace/39.uart_intr/latest

Test location	/workspace/coverage/default/39.uart_long_xfer_wo_dly.2553288202
Short name	T1051
Test name
Test status
Simulation time	60452906441 ps
CPU time	167.29 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:55:21 PM PDT 24
Peak memory	200224 kb
Host	smart-5c71cfb2-2c3b-4ad4-8bf6-a80b29018630
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2553288202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2553288202
Directory	/workspace/39.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/39.uart_loopback.3564396534
Short name	T962
Test name
Test status
Simulation time	4042530919 ps
CPU time	10.68 seconds
Started	May 30 12:52:29 PM PDT 24
Finished	May 30 12:52:41 PM PDT 24
Peak memory	200068 kb
Host	smart-3f812687-8afd-4f2a-9bd1-8b26e41d119e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3564396534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3564396534
Directory	/workspace/39.uart_loopback/latest

Test location	/workspace/coverage/default/39.uart_noise_filter.1194780728
Short name	T354
Test name
Test status
Simulation time	50409827283 ps
CPU time	58.79 seconds
Started	May 30 12:52:30 PM PDT 24
Finished	May 30 12:53:29 PM PDT 24
Peak memory	200460 kb
Host	smart-4cb1ab56-53e5-4976-80dd-0edf96bfe024
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1194780728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1194780728
Directory	/workspace/39.uart_noise_filter/latest

Test location	/workspace/coverage/default/39.uart_perf.2923802981
Short name	T707
Test name
Test status
Simulation time	15745548095 ps
CPU time	802.84 seconds
Started	May 30 12:52:31 PM PDT 24
Finished	May 30 01:05:55 PM PDT 24
Peak memory	200324 kb
Host	smart-76d940d9-de35-4538-be41-86eac74edfaa
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2923802981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2923802981
Directory	/workspace/39.uart_perf/latest

Test location	/workspace/coverage/default/39.uart_rx_oversample.3978742423
Short name	T357
Test name
Test status
Simulation time	1278833453 ps
CPU time	2.44 seconds
Started	May 30 12:52:31 PM PDT 24
Finished	May 30 12:52:34 PM PDT 24
Peak memory	198316 kb
Host	smart-ee001576-0a4d-44a0-b93a-0245ba565c13
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3978742423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3978742423
Directory	/workspace/39.uart_rx_oversample/latest

Test location	/workspace/coverage/default/39.uart_rx_parity_err.428183166
Short name	T771
Test name
Test status
Simulation time	61307260802 ps
CPU time	89.14 seconds
Started	May 30 12:52:35 PM PDT 24
Finished	May 30 12:54:05 PM PDT 24
Peak memory	200220 kb
Host	smart-17073c17-42f6-4fb1-8387-546307838312
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=428183166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.428183166
Directory	/workspace/39.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/39.uart_rx_start_bit_filter.2543711081
Short name	T721
Test name
Test status
Simulation time	3139116220 ps
CPU time	1.6 seconds
Started	May 30 12:52:32 PM PDT 24
Finished	May 30 12:52:35 PM PDT 24
Peak memory	196336 kb
Host	smart-ab3e1ff3-71e6-451e-b89b-b0523adf90d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2543711081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2543711081
Directory	/workspace/39.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/39.uart_smoke.1937993328
Short name	T476
Test name
Test status
Simulation time	907937858 ps
CPU time	1.92 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:52:36 PM PDT 24
Peak memory	198616 kb
Host	smart-2f343e11-1b64-47e0-8b9c-b70445321d1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937993328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1937993328
Directory	/workspace/39.uart_smoke/latest

Test location	/workspace/coverage/default/39.uart_stress_all.704847092
Short name	T756
Test name
Test status
Simulation time	476254805570 ps
CPU time	491.42 seconds
Started	May 30 12:52:31 PM PDT 24
Finished	May 30 01:00:44 PM PDT 24
Peak memory	208696 kb
Host	smart-9f0adfa2-5923-4a11-b97d-8766bb642100
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704847092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.704847092
Directory	/workspace/39.uart_stress_all/latest

Test location	/workspace/coverage/default/39.uart_stress_all_with_rand_reset.783165870
Short name	T209
Test name
Test status
Simulation time	88560808904 ps
CPU time	1032.57 seconds
Started	May 30 12:52:31 PM PDT 24
Finished	May 30 01:09:44 PM PDT 24
Peak memory	225124 kb
Host	smart-a55d368e-a756-460a-a8da-9d96100c20c9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783165870 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.783165870
Directory	/workspace/39.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.uart_tx_ovrd.3748574956
Short name	T1044
Test name
Test status
Simulation time	3104026190 ps
CPU time	3.08 seconds
Started	May 30 12:52:29 PM PDT 24
Finished	May 30 12:52:33 PM PDT 24
Peak memory	199288 kb
Host	smart-b7e6a878-5212-470a-90b7-e317b46c21c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748574956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3748574956
Directory	/workspace/39.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/39.uart_tx_rx.1045502750
Short name	T751
Test name
Test status
Simulation time	16442933386 ps
CPU time	29.38 seconds
Started	May 30 12:52:30 PM PDT 24
Finished	May 30 12:53:00 PM PDT 24
Peak memory	200364 kb
Host	smart-3473a9e3-daf2-4c08-b5af-c9026b056e67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1045502750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1045502750
Directory	/workspace/39.uart_tx_rx/latest

Test location	/workspace/coverage/default/4.uart_alert_test.1318206789
Short name	T841
Test name
Test status
Simulation time	11269318 ps
CPU time	0.58 seconds
Started	May 30 12:50:25 PM PDT 24
Finished	May 30 12:50:26 PM PDT 24
Peak memory	194752 kb
Host	smart-2ba26003-8e48-46e4-9923-a72e0b0198a3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318206789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1318206789
Directory	/workspace/4.uart_alert_test/latest

Test location	/workspace/coverage/default/4.uart_fifo_full.2422982843
Short name	T173
Test name
Test status
Simulation time	93401621067 ps
CPU time	30.55 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:50:44 PM PDT 24
Peak memory	200376 kb
Host	smart-54889a88-97a6-43c9-9d4d-1df41ca6774a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2422982843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2422982843
Directory	/workspace/4.uart_fifo_full/latest

Test location	/workspace/coverage/default/4.uart_fifo_overflow.1222543068
Short name	T492
Test name
Test status
Simulation time	84092961380 ps
CPU time	69.96 seconds
Started	May 30 12:50:13 PM PDT 24
Finished	May 30 12:51:25 PM PDT 24
Peak memory	200196 kb
Host	smart-97644ec3-946b-4cad-94dd-1a2986518959
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222543068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1222543068
Directory	/workspace/4.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/4.uart_fifo_reset.3482660885
Short name	T947
Test name
Test status
Simulation time	236277716168 ps
CPU time	55.94 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:51:09 PM PDT 24
Peak memory	200380 kb
Host	smart-ab31bbb0-c809-485c-9a3c-17f59cfec582
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3482660885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3482660885
Directory	/workspace/4.uart_fifo_reset/latest

Test location	/workspace/coverage/default/4.uart_intr.2613300905
Short name	T828
Test name
Test status
Simulation time	16042593810 ps
CPU time	19.24 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:50:32 PM PDT 24
Peak memory	200268 kb
Host	smart-3a09064d-276d-49ea-8046-824c6fc39334
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613300905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2613300905
Directory	/workspace/4.uart_intr/latest

Test location	/workspace/coverage/default/4.uart_long_xfer_wo_dly.3733102876
Short name	T56
Test name
Test status
Simulation time	132683291056 ps
CPU time	1000.97 seconds
Started	May 30 12:50:25 PM PDT 24
Finished	May 30 01:07:07 PM PDT 24
Peak memory	200400 kb
Host	smart-26fc77db-cc9b-4569-b01a-fd2449fde43f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3733102876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3733102876
Directory	/workspace/4.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/4.uart_loopback.2001884389
Short name	T437
Test name
Test status
Simulation time	4831766831 ps
CPU time	4.9 seconds
Started	May 30 12:50:24 PM PDT 24
Finished	May 30 12:50:30 PM PDT 24
Peak memory	198260 kb
Host	smart-9d7bcaea-bec2-49b7-8100-437847a1c28e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2001884389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2001884389
Directory	/workspace/4.uart_loopback/latest

Test location	/workspace/coverage/default/4.uart_noise_filter.868804837
Short name	T939
Test name
Test status
Simulation time	87832522912 ps
CPU time	44.54 seconds
Started	May 30 12:50:09 PM PDT 24
Finished	May 30 12:50:56 PM PDT 24
Peak memory	200532 kb
Host	smart-4b513b6d-8281-42ba-a868-2dbdf3aa06f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=868804837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.868804837
Directory	/workspace/4.uart_noise_filter/latest

Test location	/workspace/coverage/default/4.uart_perf.3276129223
Short name	T1003
Test name
Test status
Simulation time	9555658652 ps
CPU time	110.95 seconds
Started	May 30 12:50:24 PM PDT 24
Finished	May 30 12:52:16 PM PDT 24
Peak memory	200236 kb
Host	smart-5ccd307e-93a9-43ca-85a4-6ae0109daa75
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3276129223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3276129223
Directory	/workspace/4.uart_perf/latest

Test location	/workspace/coverage/default/4.uart_rx_oversample.2668858227
Short name	T531
Test name
Test status
Simulation time	4210407392 ps
CPU time	33.98 seconds
Started	May 30 12:50:10 PM PDT 24
Finished	May 30 12:50:46 PM PDT 24
Peak memory	198280 kb
Host	smart-8a6f00b3-61e2-4ac3-9d99-1deeefe31ce4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2668858227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2668858227
Directory	/workspace/4.uart_rx_oversample/latest

Test location	/workspace/coverage/default/4.uart_rx_parity_err.2729917576
Short name	T416
Test name
Test status
Simulation time	120073076506 ps
CPU time	55.6 seconds
Started	May 30 12:50:25 PM PDT 24
Finished	May 30 12:51:22 PM PDT 24
Peak memory	200380 kb
Host	smart-6e09ecd6-0e39-4cac-893b-939eec4eb300
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2729917576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2729917576
Directory	/workspace/4.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/4.uart_rx_start_bit_filter.3836456459
Short name	T316
Test name
Test status
Simulation time	3283458295 ps
CPU time	1.82 seconds
Started	May 30 12:50:11 PM PDT 24
Finished	May 30 12:50:15 PM PDT 24
Peak memory	196164 kb
Host	smart-d66f01a7-8265-461f-aca0-f2ce57647ac8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3836456459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3836456459
Directory	/workspace/4.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/4.uart_smoke.3067126074
Short name	T1054
Test name
Test status
Simulation time	5813844079 ps
CPU time	20.34 seconds
Started	May 30 12:50:09 PM PDT 24
Finished	May 30 12:50:31 PM PDT 24
Peak memory	199512 kb
Host	smart-1a843105-aae4-4930-976d-d62c3155de8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3067126074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3067126074
Directory	/workspace/4.uart_smoke/latest

Test location	/workspace/coverage/default/4.uart_stress_all.617261999
Short name	T422
Test name
Test status
Simulation time	372405638386 ps
CPU time	163.63 seconds
Started	May 30 12:50:24 PM PDT 24
Finished	May 30 12:53:08 PM PDT 24
Peak memory	200240 kb
Host	smart-06fc5f4d-b001-41eb-b2be-0181619c1ab5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617261999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.617261999
Directory	/workspace/4.uart_stress_all/latest

Test location	/workspace/coverage/default/4.uart_stress_all_with_rand_reset.4188750125
Short name	T1158
Test name
Test status
Simulation time	25319200069 ps
CPU time	294.33 seconds
Started	May 30 12:50:23 PM PDT 24
Finished	May 30 12:55:18 PM PDT 24
Peak memory	216408 kb
Host	smart-25e5ea95-3392-4109-b157-24610c3e7510
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188750125 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.4188750125
Directory	/workspace/4.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.uart_tx_ovrd.3213295897
Short name	T419
Test name
Test status
Simulation time	8088839379 ps
CPU time	11.09 seconds
Started	May 30 12:50:21 PM PDT 24
Finished	May 30 12:50:33 PM PDT 24
Peak memory	200292 kb
Host	smart-c5b0ec20-fef2-401d-944a-a2aa009f435d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3213295897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3213295897
Directory	/workspace/4.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/4.uart_tx_rx.2362642499
Short name	T794
Test name
Test status
Simulation time	35871869205 ps
CPU time	59.81 seconds
Started	May 30 12:50:15 PM PDT 24
Finished	May 30 12:51:16 PM PDT 24
Peak memory	200264 kb
Host	smart-32a4a2a1-0e01-419c-9c5f-3d9f41e01d53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362642499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2362642499
Directory	/workspace/4.uart_tx_rx/latest

Test location	/workspace/coverage/default/40.uart_alert_test.756052742
Short name	T25
Test name
Test status
Simulation time	19610574 ps
CPU time	0.54 seconds
Started	May 30 12:52:35 PM PDT 24
Finished	May 30 12:52:36 PM PDT 24
Peak memory	195752 kb
Host	smart-e59fa7ac-70fe-421d-999c-5effe3a42e75
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756052742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.756052742
Directory	/workspace/40.uart_alert_test/latest

Test location	/workspace/coverage/default/40.uart_fifo_full.512732174
Short name	T579
Test name
Test status
Simulation time	31560062211 ps
CPU time	59.3 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:53:33 PM PDT 24
Peak memory	200388 kb
Host	smart-ba845beb-9f6b-490d-ba80-2db9bb29b47f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=512732174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.512732174
Directory	/workspace/40.uart_fifo_full/latest

Test location	/workspace/coverage/default/40.uart_fifo_overflow.3583421835
Short name	T538
Test name
Test status
Simulation time	67318231733 ps
CPU time	31.32 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:53:05 PM PDT 24
Peak memory	200372 kb
Host	smart-630f3840-2aa5-4b16-938e-70c7069e469f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3583421835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3583421835
Directory	/workspace/40.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/40.uart_fifo_reset.1866660943
Short name	T696
Test name
Test status
Simulation time	138160587791 ps
CPU time	118.76 seconds
Started	May 30 12:52:34 PM PDT 24
Finished	May 30 12:54:33 PM PDT 24
Peak memory	200316 kb
Host	smart-2cf85aff-e6f4-446d-a8a8-817938c3841a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1866660943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1866660943
Directory	/workspace/40.uart_fifo_reset/latest

Test location	/workspace/coverage/default/40.uart_intr.3633597201
Short name	T1104
Test name
Test status
Simulation time	20857922016 ps
CPU time	7.94 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:52:42 PM PDT 24
Peak memory	197488 kb
Host	smart-7de6c8a1-e13b-4ffa-8d4f-ffc348d91325
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633597201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3633597201
Directory	/workspace/40.uart_intr/latest

Test location	/workspace/coverage/default/40.uart_long_xfer_wo_dly.3794596069
Short name	T992
Test name
Test status
Simulation time	58206264523 ps
CPU time	242.06 seconds
Started	May 30 12:52:32 PM PDT 24
Finished	May 30 12:56:35 PM PDT 24
Peak memory	200320 kb
Host	smart-ffc2a56d-1a2e-44f2-8649-23b563c43ca9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3794596069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3794596069
Directory	/workspace/40.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/40.uart_loopback.660186363
Short name	T1098
Test name
Test status
Simulation time	2881956042 ps
CPU time	10.36 seconds
Started	May 30 12:52:32 PM PDT 24
Finished	May 30 12:52:43 PM PDT 24
Peak memory	199308 kb
Host	smart-46c13c30-a082-4ff1-b0f0-f20b072daf0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660186363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.660186363
Directory	/workspace/40.uart_loopback/latest

Test location	/workspace/coverage/default/40.uart_noise_filter.756143348
Short name	T964
Test name
Test status
Simulation time	26249853531 ps
CPU time	79.67 seconds
Started	May 30 12:52:32 PM PDT 24
Finished	May 30 12:53:53 PM PDT 24
Peak memory	200160 kb
Host	smart-218b58d3-1a44-4b3d-a2ba-accc9c86e179
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756143348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.756143348
Directory	/workspace/40.uart_noise_filter/latest

Test location	/workspace/coverage/default/40.uart_perf.1877954948
Short name	T967
Test name
Test status
Simulation time	18891939799 ps
CPU time	269.91 seconds
Started	May 30 12:52:35 PM PDT 24
Finished	May 30 12:57:05 PM PDT 24
Peak memory	200272 kb
Host	smart-a8d41caf-94f4-48d9-a9ed-418defe8e188
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1877954948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1877954948
Directory	/workspace/40.uart_perf/latest

Test location	/workspace/coverage/default/40.uart_rx_oversample.4175435618
Short name	T393
Test name
Test status
Simulation time	2548254063 ps
CPU time	5.32 seconds
Started	May 30 12:52:34 PM PDT 24
Finished	May 30 12:52:40 PM PDT 24
Peak memory	198752 kb
Host	smart-a321a3d6-3d78-41dd-9271-26b3d04d285c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4175435618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.4175435618
Directory	/workspace/40.uart_rx_oversample/latest

Test location	/workspace/coverage/default/40.uart_rx_parity_err.1500294056
Short name	T449
Test name
Test status
Simulation time	23946482122 ps
CPU time	21.45 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:52:56 PM PDT 24
Peak memory	200328 kb
Host	smart-7f409b89-7cf1-442b-b6e0-f73281a22fa3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1500294056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1500294056
Directory	/workspace/40.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/40.uart_rx_start_bit_filter.2873391253
Short name	T796
Test name
Test status
Simulation time	3523975971 ps
CPU time	2.28 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:52:36 PM PDT 24
Peak memory	196640 kb
Host	smart-e2216185-5775-4335-9c37-110f7c62259e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2873391253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2873391253
Directory	/workspace/40.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/40.uart_smoke.3285761944
Short name	T953
Test name
Test status
Simulation time	5547807513 ps
CPU time	7.68 seconds
Started	May 30 12:52:31 PM PDT 24
Finished	May 30 12:52:40 PM PDT 24
Peak memory	200132 kb
Host	smart-f1e559b6-9875-4b17-a6c4-50c51da9698c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3285761944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3285761944
Directory	/workspace/40.uart_smoke/latest

Test location	/workspace/coverage/default/40.uart_stress_all.406428140
Short name	T340
Test name
Test status
Simulation time	389464421072 ps
CPU time	615.4 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 01:02:50 PM PDT 24
Peak memory	200236 kb
Host	smart-050ea185-9d2e-4eb4-aab0-2588618ba2de
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406428140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.406428140
Directory	/workspace/40.uart_stress_all/latest

Test location	/workspace/coverage/default/40.uart_stress_all_with_rand_reset.4075176726
Short name	T1059
Test name
Test status
Simulation time	217227143721 ps
CPU time	1475.31 seconds
Started	May 30 12:52:38 PM PDT 24
Finished	May 30 01:17:14 PM PDT 24
Peak memory	217076 kb
Host	smart-3f50f105-8116-4e6a-8dda-7b8cfc3d1077
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075176726 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.4075176726
Directory	/workspace/40.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.uart_tx_ovrd.897878604
Short name	T1123
Test name
Test status
Simulation time	619184971 ps
CPU time	1.96 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:52:36 PM PDT 24
Peak memory	198596 kb
Host	smart-6764c112-5f29-4527-a053-5acc4d00198c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=897878604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.897878604
Directory	/workspace/40.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/40.uart_tx_rx.2664829669
Short name	T106
Test name
Test status
Simulation time	17089420557 ps
CPU time	16.36 seconds
Started	May 30 12:52:35 PM PDT 24
Finished	May 30 12:52:52 PM PDT 24
Peak memory	200380 kb
Host	smart-eeca6e70-be1b-4e84-8cbd-13c025ed6a09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2664829669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2664829669
Directory	/workspace/40.uart_tx_rx/latest

Test location	/workspace/coverage/default/41.uart_alert_test.206537294
Short name	T26
Test name
Test status
Simulation time	20254852 ps
CPU time	0.54 seconds
Started	May 30 12:52:32 PM PDT 24
Finished	May 30 12:52:34 PM PDT 24
Peak memory	195756 kb
Host	smart-c306c4b0-a457-4491-807c-7c0f0d12acd0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206537294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.206537294
Directory	/workspace/41.uart_alert_test/latest

Test location	/workspace/coverage/default/41.uart_fifo_full.819424464
Short name	T977
Test name
Test status
Simulation time	54464714031 ps
CPU time	26.79 seconds
Started	May 30 12:52:37 PM PDT 24
Finished	May 30 12:53:05 PM PDT 24
Peak memory	200396 kb
Host	smart-8d785bde-5651-4ca5-97aa-b9ac7fcb998b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=819424464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.819424464
Directory	/workspace/41.uart_fifo_full/latest

Test location	/workspace/coverage/default/41.uart_fifo_overflow.927010645
Short name	T1024
Test name
Test status
Simulation time	13431037872 ps
CPU time	25.33 seconds
Started	May 30 12:52:32 PM PDT 24
Finished	May 30 12:52:58 PM PDT 24
Peak memory	200300 kb
Host	smart-008012a4-ef51-46ab-a478-038c84f90d79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927010645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.927010645
Directory	/workspace/41.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/41.uart_fifo_reset.4235783164
Short name	T674
Test name
Test status
Simulation time	97677821265 ps
CPU time	78.95 seconds
Started	May 30 12:52:37 PM PDT 24
Finished	May 30 12:53:56 PM PDT 24
Peak memory	200268 kb
Host	smart-c0391418-ba75-46e5-9227-45a316a0a3c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235783164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.4235783164
Directory	/workspace/41.uart_fifo_reset/latest

Test location	/workspace/coverage/default/41.uart_intr.1287073151
Short name	T676
Test name
Test status
Simulation time	6905785085 ps
CPU time	3.49 seconds
Started	May 30 12:52:31 PM PDT 24
Finished	May 30 12:52:35 PM PDT 24
Peak memory	197184 kb
Host	smart-e1902bf2-bcac-4536-9339-f2fc3bb92238
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287073151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1287073151
Directory	/workspace/41.uart_intr/latest

Test location	/workspace/coverage/default/41.uart_long_xfer_wo_dly.436725900
Short name	T480
Test name
Test status
Simulation time	26573375824 ps
CPU time	163.55 seconds
Started	May 30 12:52:38 PM PDT 24
Finished	May 30 12:55:22 PM PDT 24
Peak memory	200356 kb
Host	smart-1da5e054-bba0-4e84-9805-03fdd5ef01e4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=436725900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.436725900
Directory	/workspace/41.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/41.uart_loopback.370438146
Short name	T338
Test name
Test status
Simulation time	5114077946 ps
CPU time	3.4 seconds
Started	May 30 12:52:38 PM PDT 24
Finished	May 30 12:52:42 PM PDT 24
Peak memory	198172 kb
Host	smart-b94cbd25-7bce-420e-98ad-9f61f2bd7578
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=370438146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.370438146
Directory	/workspace/41.uart_loopback/latest

Test location	/workspace/coverage/default/41.uart_noise_filter.2777918898
Short name	T555
Test name
Test status
Simulation time	19233292799 ps
CPU time	14.87 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:52:49 PM PDT 24
Peak memory	198160 kb
Host	smart-1b1864f0-c740-4900-aa20-d77d08792de1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777918898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2777918898
Directory	/workspace/41.uart_noise_filter/latest

Test location	/workspace/coverage/default/41.uart_perf.2247326213
Short name	T591
Test name
Test status
Simulation time	5701989363 ps
CPU time	89.46 seconds
Started	May 30 12:52:38 PM PDT 24
Finished	May 30 12:54:08 PM PDT 24
Peak memory	200336 kb
Host	smart-c1db93f2-b2dd-4d77-aba4-d2877eeb620b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2247326213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2247326213
Directory	/workspace/41.uart_perf/latest

Test location	/workspace/coverage/default/41.uart_rx_oversample.2452720540
Short name	T1076
Test name
Test status
Simulation time	5281972800 ps
CPU time	11.53 seconds
Started	May 30 12:52:37 PM PDT 24
Finished	May 30 12:52:49 PM PDT 24
Peak memory	198524 kb
Host	smart-98dd6203-05f1-4642-806b-8082f77949d5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2452720540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2452720540
Directory	/workspace/41.uart_rx_oversample/latest

Test location	/workspace/coverage/default/41.uart_rx_parity_err.2637990139
Short name	T110
Test name
Test status
Simulation time	27821247381 ps
CPU time	13.86 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:52:48 PM PDT 24
Peak memory	200336 kb
Host	smart-e418d516-b017-43c5-889c-c7f7cc4c33e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637990139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2637990139
Directory	/workspace/41.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/41.uart_rx_start_bit_filter.2663118818
Short name	T448
Test name
Test status
Simulation time	4340810005 ps
CPU time	7.6 seconds
Started	May 30 12:52:36 PM PDT 24
Finished	May 30 12:52:44 PM PDT 24
Peak memory	196252 kb
Host	smart-d37fbf1c-1631-4707-8bb2-58b2fb5e330e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2663118818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2663118818
Directory	/workspace/41.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/41.uart_smoke.497874265
Short name	T1120
Test name
Test status
Simulation time	143481299 ps
CPU time	0.83 seconds
Started	May 30 12:52:36 PM PDT 24
Finished	May 30 12:52:38 PM PDT 24
Peak memory	198620 kb
Host	smart-83076ea6-69f7-4dd4-ad8f-39da96e29ba9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=497874265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.497874265
Directory	/workspace/41.uart_smoke/latest

Test location	/workspace/coverage/default/41.uart_stress_all.1005493878
Short name	T789
Test name
Test status
Simulation time	181610844632 ps
CPU time	532.12 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 01:01:26 PM PDT 24
Peak memory	200552 kb
Host	smart-e954fc2e-7b90-400f-9cc9-d1f41030414f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005493878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1005493878
Directory	/workspace/41.uart_stress_all/latest

Test location	/workspace/coverage/default/41.uart_stress_all_with_rand_reset.2534964123
Short name	T781
Test name
Test status
Simulation time	70201245120 ps
CPU time	689.69 seconds
Started	May 30 12:52:35 PM PDT 24
Finished	May 30 01:04:06 PM PDT 24
Peak memory	225152 kb
Host	smart-ad52b54f-7cd8-4800-86c7-9757aa6463ce
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534964123 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2534964123
Directory	/workspace/41.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.uart_tx_ovrd.692502573
Short name	T15
Test name
Test status
Simulation time	1552076984 ps
CPU time	1.78 seconds
Started	May 30 12:52:35 PM PDT 24
Finished	May 30 12:52:37 PM PDT 24
Peak memory	199096 kb
Host	smart-26815e32-1043-4b0d-9dcc-c13d420086c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=692502573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.692502573
Directory	/workspace/41.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/41.uart_tx_rx.918091328
Short name	T1074
Test name
Test status
Simulation time	78183242743 ps
CPU time	17.03 seconds
Started	May 30 12:52:36 PM PDT 24
Finished	May 30 12:52:53 PM PDT 24
Peak memory	196636 kb
Host	smart-543a35c2-4a40-4280-b591-502d283d49b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918091328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.918091328
Directory	/workspace/41.uart_tx_rx/latest

Test location	/workspace/coverage/default/42.uart_alert_test.2519963278
Short name	T714
Test name
Test status
Simulation time	56013203 ps
CPU time	0.54 seconds
Started	May 30 12:52:43 PM PDT 24
Finished	May 30 12:52:45 PM PDT 24
Peak memory	195752 kb
Host	smart-b4ffb4b5-532b-4969-98b4-63ad55d32255
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519963278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2519963278
Directory	/workspace/42.uart_alert_test/latest

Test location	/workspace/coverage/default/42.uart_fifo_overflow.539135837
Short name	T646
Test name
Test status
Simulation time	197739181801 ps
CPU time	26.85 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:53:01 PM PDT 24
Peak memory	199188 kb
Host	smart-e9a10737-0aed-4f78-b983-414a31661a1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=539135837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.539135837
Directory	/workspace/42.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/42.uart_intr.138801682
Short name	T600
Test name
Test status
Simulation time	50911466645 ps
CPU time	110.08 seconds
Started	May 30 12:52:42 PM PDT 24
Finished	May 30 12:54:33 PM PDT 24
Peak memory	200300 kb
Host	smart-c1e2d629-c5b0-48de-8309-db13f7879dc3
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138801682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.138801682
Directory	/workspace/42.uart_intr/latest

Test location	/workspace/coverage/default/42.uart_long_xfer_wo_dly.652986821
Short name	T950
Test name
Test status
Simulation time	114812903909 ps
CPU time	387.51 seconds
Started	May 30 12:52:48 PM PDT 24
Finished	May 30 12:59:16 PM PDT 24
Peak memory	199996 kb
Host	smart-576c06a4-7e30-4e83-b7ee-580ed1318b74
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=652986821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.652986821
Directory	/workspace/42.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/42.uart_loopback.182361453
Short name	T743
Test name
Test status
Simulation time	8137748811 ps
CPU time	10.14 seconds
Started	May 30 12:52:42 PM PDT 24
Finished	May 30 12:52:53 PM PDT 24
Peak memory	199976 kb
Host	smart-aa013a26-8be1-4a8e-989e-c4997180bc93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=182361453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.182361453
Directory	/workspace/42.uart_loopback/latest

Test location	/workspace/coverage/default/42.uart_noise_filter.2723130729
Short name	T910
Test name
Test status
Simulation time	67249282402 ps
CPU time	34.87 seconds
Started	May 30 12:52:43 PM PDT 24
Finished	May 30 12:53:19 PM PDT 24
Peak memory	200580 kb
Host	smart-999c36df-c29d-4e44-9bc8-254dbcd5cf4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2723130729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2723130729
Directory	/workspace/42.uart_noise_filter/latest

Test location	/workspace/coverage/default/42.uart_perf.2945101828
Short name	T496
Test name
Test status
Simulation time	14400115733 ps
CPU time	372.62 seconds
Started	May 30 12:52:43 PM PDT 24
Finished	May 30 12:58:57 PM PDT 24
Peak memory	200216 kb
Host	smart-e4a16da2-dfc5-4702-b09f-4fed7be02e9f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2945101828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2945101828
Directory	/workspace/42.uart_perf/latest

Test location	/workspace/coverage/default/42.uart_rx_oversample.2192560092
Short name	T872
Test name
Test status
Simulation time	1537684215 ps
CPU time	1.02 seconds
Started	May 30 12:52:48 PM PDT 24
Finished	May 30 12:52:50 PM PDT 24
Peak memory	198112 kb
Host	smart-7e28c26a-9189-4147-8058-875ff31c47c2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2192560092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2192560092
Directory	/workspace/42.uart_rx_oversample/latest

Test location	/workspace/coverage/default/42.uart_rx_parity_err.1941350133
Short name	T389
Test name
Test status
Simulation time	26827882680 ps
CPU time	43.04 seconds
Started	May 30 12:52:48 PM PDT 24
Finished	May 30 12:53:31 PM PDT 24
Peak memory	200120 kb
Host	smart-fdb9312c-0667-42f0-89d7-a20d628fe146
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1941350133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1941350133
Directory	/workspace/42.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/42.uart_rx_start_bit_filter.3631950178
Short name	T842
Test name
Test status
Simulation time	68786514046 ps
CPU time	113.33 seconds
Started	May 30 12:52:46 PM PDT 24
Finished	May 30 12:54:40 PM PDT 24
Peak memory	196356 kb
Host	smart-2231e0a6-5653-423e-b0f3-1c572d7825a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3631950178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3631950178
Directory	/workspace/42.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/42.uart_smoke.3543356231
Short name	T713
Test name
Test status
Simulation time	296475830 ps
CPU time	1.47 seconds
Started	May 30 12:52:37 PM PDT 24
Finished	May 30 12:52:39 PM PDT 24
Peak memory	199052 kb
Host	smart-b6c6f3a8-9381-484a-9050-1c0d278bf8ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3543356231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3543356231
Directory	/workspace/42.uart_smoke/latest

Test location	/workspace/coverage/default/42.uart_stress_all.2360611545
Short name	T708
Test name
Test status
Simulation time	408542244279 ps
CPU time	93.38 seconds
Started	May 30 12:52:42 PM PDT 24
Finished	May 30 12:54:15 PM PDT 24
Peak memory	200412 kb
Host	smart-ff076932-0566-49b3-a9dd-7d76c9864c85
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360611545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2360611545
Directory	/workspace/42.uart_stress_all/latest

Test location	/workspace/coverage/default/42.uart_tx_ovrd.897710471
Short name	T1171
Test name
Test status
Simulation time	2752191942 ps
CPU time	2.35 seconds
Started	May 30 12:52:52 PM PDT 24
Finished	May 30 12:52:55 PM PDT 24
Peak memory	198760 kb
Host	smart-f11a566b-8fed-49d9-82d9-4dfb16823462
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=897710471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.897710471
Directory	/workspace/42.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/42.uart_tx_rx.2125612101
Short name	T343
Test name
Test status
Simulation time	51290219569 ps
CPU time	45.73 seconds
Started	May 30 12:52:33 PM PDT 24
Finished	May 30 12:53:20 PM PDT 24
Peak memory	200308 kb
Host	smart-6a23dabf-a780-4d63-a8a2-3990e50d2c9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125612101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2125612101
Directory	/workspace/42.uart_tx_rx/latest

Test location	/workspace/coverage/default/43.uart_alert_test.1720328461
Short name	T719
Test name
Test status
Simulation time	15137182 ps
CPU time	0.57 seconds
Started	May 30 12:52:42 PM PDT 24
Finished	May 30 12:52:43 PM PDT 24
Peak memory	195756 kb
Host	smart-92bdb76d-87fc-4cd3-8954-9af2531ab9cb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720328461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1720328461
Directory	/workspace/43.uart_alert_test/latest

Test location	/workspace/coverage/default/43.uart_fifo_full.1813621302
Short name	T166
Test name
Test status
Simulation time	63132406255 ps
CPU time	115.21 seconds
Started	May 30 12:52:43 PM PDT 24
Finished	May 30 12:54:39 PM PDT 24
Peak memory	200336 kb
Host	smart-a2916ccf-4bb1-4528-a23f-4f394677966f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1813621302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1813621302
Directory	/workspace/43.uart_fifo_full/latest

Test location	/workspace/coverage/default/43.uart_fifo_overflow.1615083876
Short name	T679
Test name
Test status
Simulation time	26449110202 ps
CPU time	15.24 seconds
Started	May 30 12:52:43 PM PDT 24
Finished	May 30 12:52:58 PM PDT 24
Peak memory	198876 kb
Host	smart-1d34059a-45e0-4e0c-872c-cba7f8a61568
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1615083876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1615083876
Directory	/workspace/43.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/43.uart_fifo_reset.510395883
Short name	T908
Test name
Test status
Simulation time	29499359518 ps
CPU time	25.19 seconds
Started	May 30 12:52:42 PM PDT 24
Finished	May 30 12:53:08 PM PDT 24
Peak memory	200304 kb
Host	smart-624be796-fb2f-4e94-973f-690b737a09e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=510395883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.510395883
Directory	/workspace/43.uart_fifo_reset/latest

Test location	/workspace/coverage/default/43.uart_intr.1601624095
Short name	T125
Test name
Test status
Simulation time	135099426098 ps
CPU time	78.27 seconds
Started	May 30 12:52:44 PM PDT 24
Finished	May 30 12:54:03 PM PDT 24
Peak memory	200340 kb
Host	smart-85a2a582-2445-445f-8eb4-8e523f53c727
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601624095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1601624095
Directory	/workspace/43.uart_intr/latest

Test location	/workspace/coverage/default/43.uart_long_xfer_wo_dly.1502284032
Short name	T907
Test name
Test status
Simulation time	53133598065 ps
CPU time	148.26 seconds
Started	May 30 12:52:48 PM PDT 24
Finished	May 30 12:55:17 PM PDT 24
Peak memory	200396 kb
Host	smart-48ecadda-e3b3-486c-a996-85f0d6f3be4d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1502284032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1502284032
Directory	/workspace/43.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/43.uart_loopback.4089408182
Short name	T886
Test name
Test status
Simulation time	3034974585 ps
CPU time	5.97 seconds
Started	May 30 12:52:52 PM PDT 24
Finished	May 30 12:52:59 PM PDT 24
Peak memory	198116 kb
Host	smart-d64bd9a6-ab68-4869-b90f-9c8a0ff77254
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4089408182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.4089408182
Directory	/workspace/43.uart_loopback/latest

Test location	/workspace/coverage/default/43.uart_noise_filter.3534999049
Short name	T528
Test name
Test status
Simulation time	114457808579 ps
CPU time	26.66 seconds
Started	May 30 12:52:43 PM PDT 24
Finished	May 30 12:53:11 PM PDT 24
Peak memory	199756 kb
Host	smart-14d25f8a-aaa3-4b48-99e4-5ca0a793c8a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3534999049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3534999049
Directory	/workspace/43.uart_noise_filter/latest

Test location	/workspace/coverage/default/43.uart_perf.4217460318
Short name	T830
Test name
Test status
Simulation time	6393444328 ps
CPU time	113.2 seconds
Started	May 30 12:52:52 PM PDT 24
Finished	May 30 12:54:46 PM PDT 24
Peak memory	200332 kb
Host	smart-1852d53e-8967-4510-bba0-130c673be418
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4217460318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.4217460318
Directory	/workspace/43.uart_perf/latest

Test location	/workspace/coverage/default/43.uart_rx_oversample.3678452243
Short name	T812
Test name
Test status
Simulation time	1609409294 ps
CPU time	1.92 seconds
Started	May 30 12:52:42 PM PDT 24
Finished	May 30 12:52:44 PM PDT 24
Peak memory	197804 kb
Host	smart-b16f7e9e-b128-4be2-a24d-b8b7bd55e403
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3678452243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3678452243
Directory	/workspace/43.uart_rx_oversample/latest

Test location	/workspace/coverage/default/43.uart_rx_parity_err.2083568318
Short name	T10
Test name
Test status
Simulation time	24122121401 ps
CPU time	26.08 seconds
Started	May 30 12:52:46 PM PDT 24
Finished	May 30 12:53:13 PM PDT 24
Peak memory	200236 kb
Host	smart-aff9d26f-e3e8-4642-a244-f077c62204dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083568318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2083568318
Directory	/workspace/43.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/43.uart_rx_start_bit_filter.3915596817
Short name	T525
Test name
Test status
Simulation time	3500838834 ps
CPU time	1.34 seconds
Started	May 30 12:52:45 PM PDT 24
Finished	May 30 12:52:47 PM PDT 24
Peak memory	196380 kb
Host	smart-c3ad8900-bcf9-4259-914b-a51d00538dd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915596817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3915596817
Directory	/workspace/43.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/43.uart_smoke.1524797997
Short name	T436
Test name
Test status
Simulation time	159225221 ps
CPU time	0.78 seconds
Started	May 30 12:52:43 PM PDT 24
Finished	May 30 12:52:44 PM PDT 24
Peak memory	197392 kb
Host	smart-d2549c91-6a1d-46bf-9c31-4f6f2cb29602
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1524797997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1524797997
Directory	/workspace/43.uart_smoke/latest

Test location	/workspace/coverage/default/43.uart_stress_all.1933423109
Short name	T861
Test name
Test status
Simulation time	197755247723 ps
CPU time	421.36 seconds
Started	May 30 12:52:43 PM PDT 24
Finished	May 30 12:59:45 PM PDT 24
Peak memory	208656 kb
Host	smart-3855c2e3-d3a2-48f0-9ea4-fab83b8cea45
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933423109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1933423109
Directory	/workspace/43.uart_stress_all/latest

Test location	/workspace/coverage/default/43.uart_stress_all_with_rand_reset.2806214337
Short name	T112
Test name
Test status
Simulation time	111699605978 ps
CPU time	991.1 seconds
Started	May 30 12:52:43 PM PDT 24
Finished	May 30 01:09:16 PM PDT 24
Peak memory	226184 kb
Host	smart-9be55966-1615-4fd2-b146-b0ec8b3df43a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806214337 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2806214337
Directory	/workspace/43.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.uart_tx_ovrd.3259705487
Short name	T355
Test name
Test status
Simulation time	12213516346 ps
CPU time	15.4 seconds
Started	May 30 12:52:45 PM PDT 24
Finished	May 30 12:53:02 PM PDT 24
Peak memory	200288 kb
Host	smart-b42a8fad-7835-47e6-95c4-162e589a979b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3259705487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3259705487
Directory	/workspace/43.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/43.uart_tx_rx.3154167866
Short name	T347
Test name
Test status
Simulation time	37164866487 ps
CPU time	9.98 seconds
Started	May 30 12:52:46 PM PDT 24
Finished	May 30 12:52:56 PM PDT 24
Peak memory	200296 kb
Host	smart-3379ef4b-8159-45e6-9a75-2f46171bda0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3154167866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3154167866
Directory	/workspace/43.uart_tx_rx/latest

Test location	/workspace/coverage/default/44.uart_alert_test.3586604702
Short name	T574
Test name
Test status
Simulation time	16332536 ps
CPU time	0.53 seconds
Started	May 30 12:52:47 PM PDT 24
Finished	May 30 12:52:48 PM PDT 24
Peak memory	195768 kb
Host	smart-a04f4716-3431-4448-b85c-a6ea919a444c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586604702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3586604702
Directory	/workspace/44.uart_alert_test/latest

Test location	/workspace/coverage/default/44.uart_fifo_full.1640052758
Short name	T622
Test name
Test status
Simulation time	31099953701 ps
CPU time	48.57 seconds
Started	May 30 12:52:43 PM PDT 24
Finished	May 30 12:53:32 PM PDT 24
Peak memory	200364 kb
Host	smart-e7d952c8-8b71-406f-bcc0-7c51cd42ceb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640052758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1640052758
Directory	/workspace/44.uart_fifo_full/latest

Test location	/workspace/coverage/default/44.uart_fifo_overflow.3205464630
Short name	T1010
Test name
Test status
Simulation time	120450963968 ps
CPU time	179.62 seconds
Started	May 30 12:52:44 PM PDT 24
Finished	May 30 12:55:45 PM PDT 24
Peak memory	200360 kb
Host	smart-c858dd1c-ab9c-49ad-822e-21be9f610f85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3205464630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3205464630
Directory	/workspace/44.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/44.uart_fifo_reset.177315058
Short name	T899
Test name
Test status
Simulation time	169348334413 ps
CPU time	17.38 seconds
Started	May 30 12:52:47 PM PDT 24
Finished	May 30 12:53:05 PM PDT 24
Peak memory	200340 kb
Host	smart-b415a295-0f42-428f-bfae-df2932676290
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177315058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.177315058
Directory	/workspace/44.uart_fifo_reset/latest

Test location	/workspace/coverage/default/44.uart_intr.1345470187
Short name	T18
Test name
Test status
Simulation time	19140182131 ps
CPU time	34.36 seconds
Started	May 30 12:52:44 PM PDT 24
Finished	May 30 12:53:19 PM PDT 24
Peak memory	197416 kb
Host	smart-1fe2bec8-e6e9-4b1f-bbee-1ada64f99801
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345470187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1345470187
Directory	/workspace/44.uart_intr/latest

Test location	/workspace/coverage/default/44.uart_long_xfer_wo_dly.1474032184
Short name	T458
Test name
Test status
Simulation time	120418081047 ps
CPU time	378.22 seconds
Started	May 30 12:52:51 PM PDT 24
Finished	May 30 12:59:10 PM PDT 24
Peak memory	200400 kb
Host	smart-9ed77155-d3a9-473d-99d9-0747cee8f9eb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1474032184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1474032184
Directory	/workspace/44.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/44.uart_loopback.505421503
Short name	T1021
Test name
Test status
Simulation time	4085732670 ps
CPU time	3.54 seconds
Started	May 30 12:52:48 PM PDT 24
Finished	May 30 12:52:53 PM PDT 24
Peak memory	200388 kb
Host	smart-476c5305-61de-4bdc-9e4e-5b65d5364cea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=505421503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.505421503
Directory	/workspace/44.uart_loopback/latest

Test location	/workspace/coverage/default/44.uart_noise_filter.1741274424
Short name	T1085
Test name
Test status
Simulation time	480539513702 ps
CPU time	91.58 seconds
Started	May 30 12:52:48 PM PDT 24
Finished	May 30 12:54:20 PM PDT 24
Peak memory	208632 kb
Host	smart-06e0788c-7e6f-4a3d-aeb7-e8bd78c0c3f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1741274424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1741274424
Directory	/workspace/44.uart_noise_filter/latest

Test location	/workspace/coverage/default/44.uart_perf.1186677127
Short name	T1030
Test name
Test status
Simulation time	16921337668 ps
CPU time	375.49 seconds
Started	May 30 12:52:52 PM PDT 24
Finished	May 30 12:59:08 PM PDT 24
Peak memory	200424 kb
Host	smart-51d6de92-2a7d-496e-833d-8abaee4d72ce
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1186677127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1186677127
Directory	/workspace/44.uart_perf/latest

Test location	/workspace/coverage/default/44.uart_rx_oversample.1831059966
Short name	T1018
Test name
Test status
Simulation time	6068525108 ps
CPU time	54.72 seconds
Started	May 30 12:52:47 PM PDT 24
Finished	May 30 12:53:42 PM PDT 24
Peak memory	198572 kb
Host	smart-18ab18c2-3309-4c89-9769-31a5ecec9c7a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1831059966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1831059966
Directory	/workspace/44.uart_rx_oversample/latest

Test location	/workspace/coverage/default/44.uart_rx_parity_err.3861371983
Short name	T470
Test name
Test status
Simulation time	54524909367 ps
CPU time	23.19 seconds
Started	May 30 12:52:48 PM PDT 24
Finished	May 30 12:53:12 PM PDT 24
Peak memory	200372 kb
Host	smart-af407e0c-700d-4b45-8874-add8812503e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861371983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3861371983
Directory	/workspace/44.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/44.uart_rx_start_bit_filter.748948060
Short name	T489
Test name
Test status
Simulation time	7412985462 ps
CPU time	3.69 seconds
Started	May 30 12:52:53 PM PDT 24
Finished	May 30 12:52:57 PM PDT 24
Peak memory	196400 kb
Host	smart-cdea2a1c-6145-4bac-b3a1-001bb612defc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=748948060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.748948060
Directory	/workspace/44.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/44.uart_smoke.63364128
Short name	T479
Test name
Test status
Simulation time	933047078 ps
CPU time	1.2 seconds
Started	May 30 12:52:46 PM PDT 24
Finished	May 30 12:52:48 PM PDT 24
Peak memory	198764 kb
Host	smart-34082dbf-4906-43c0-83ae-dd107c69184d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63364128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.63364128
Directory	/workspace/44.uart_smoke/latest

Test location	/workspace/coverage/default/44.uart_stress_all.3326582499
Short name	T165
Test name
Test status
Simulation time	349346093497 ps
CPU time	1558.85 seconds
Started	May 30 12:52:50 PM PDT 24
Finished	May 30 01:18:50 PM PDT 24
Peak memory	208740 kb
Host	smart-561fddcc-7191-4546-a412-6a076e6a8c84
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326582499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3326582499
Directory	/workspace/44.uart_stress_all/latest

Test location	/workspace/coverage/default/44.uart_stress_all_with_rand_reset.4123734825
Short name	T188
Test name
Test status
Simulation time	102409876794 ps
CPU time	270.33 seconds
Started	May 30 12:52:52 PM PDT 24
Finished	May 30 12:57:23 PM PDT 24
Peak memory	216844 kb
Host	smart-8d86a637-044f-45ac-aa17-86db22d73233
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123734825 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.4123734825
Directory	/workspace/44.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.uart_tx_ovrd.1776095730
Short name	T755
Test name
Test status
Simulation time	728993672 ps
CPU time	1.88 seconds
Started	May 30 12:52:51 PM PDT 24
Finished	May 30 12:52:54 PM PDT 24
Peak memory	198676 kb
Host	smart-ce2a193a-c850-4734-9489-28038af9d385
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1776095730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1776095730
Directory	/workspace/44.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/44.uart_tx_rx.1338107029
Short name	T291
Test name
Test status
Simulation time	46650823861 ps
CPU time	82.3 seconds
Started	May 30 12:52:43 PM PDT 24
Finished	May 30 12:54:06 PM PDT 24
Peak memory	200284 kb
Host	smart-9a32fe3b-c64e-4761-b939-1b90fe5d49c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1338107029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1338107029
Directory	/workspace/44.uart_tx_rx/latest

Test location	/workspace/coverage/default/45.uart_alert_test.1152107590
Short name	T958
Test name
Test status
Simulation time	39857475 ps
CPU time	0.55 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 12:52:58 PM PDT 24
Peak memory	195744 kb
Host	smart-b3dc4289-0861-4ae1-9146-63dffed4c764
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152107590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1152107590
Directory	/workspace/45.uart_alert_test/latest

Test location	/workspace/coverage/default/45.uart_fifo_full.1832905524
Short name	T55
Test name
Test status
Simulation time	198141144643 ps
CPU time	188.26 seconds
Started	May 30 12:52:44 PM PDT 24
Finished	May 30 12:55:53 PM PDT 24
Peak memory	200396 kb
Host	smart-27abf6e3-4019-4a2a-a66a-0bfe42d8b25c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832905524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1832905524
Directory	/workspace/45.uart_fifo_full/latest

Test location	/workspace/coverage/default/45.uart_fifo_overflow.2804058809
Short name	T109
Test name
Test status
Simulation time	69546475359 ps
CPU time	111 seconds
Started	May 30 12:52:44 PM PDT 24
Finished	May 30 12:54:36 PM PDT 24
Peak memory	200336 kb
Host	smart-367d51b4-dedb-4830-9702-7edfdff842df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2804058809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2804058809
Directory	/workspace/45.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/45.uart_fifo_reset.2087482503
Short name	T915
Test name
Test status
Simulation time	43461169605 ps
CPU time	46.88 seconds
Started	May 30 12:52:44 PM PDT 24
Finished	May 30 12:53:32 PM PDT 24
Peak memory	200276 kb
Host	smart-5dd7e3b2-7a86-431a-9e30-b5ac75f022c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2087482503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2087482503
Directory	/workspace/45.uart_fifo_reset/latest

Test location	/workspace/coverage/default/45.uart_intr.1361130414
Short name	T502
Test name
Test status
Simulation time	2505089410 ps
CPU time	6 seconds
Started	May 30 12:52:43 PM PDT 24
Finished	May 30 12:52:50 PM PDT 24
Peak memory	199828 kb
Host	smart-be30bc46-8503-4800-8acf-9f7f19f94787
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361130414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1361130414
Directory	/workspace/45.uart_intr/latest

Test location	/workspace/coverage/default/45.uart_long_xfer_wo_dly.1646527976
Short name	T661
Test name
Test status
Simulation time	214843569489 ps
CPU time	291.86 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 12:57:48 PM PDT 24
Peak memory	200368 kb
Host	smart-edcd7b22-2268-482b-8ac5-0a6d1b9aba0a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1646527976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1646527976
Directory	/workspace/45.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/45.uart_loopback.2295633074
Short name	T451
Test name
Test status
Simulation time	3157265215 ps
CPU time	2.3 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 12:52:59 PM PDT 24
Peak memory	199804 kb
Host	smart-dafccc44-1221-4e3b-b1a1-682afe1c70f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2295633074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2295633074
Directory	/workspace/45.uart_loopback/latest

Test location	/workspace/coverage/default/45.uart_noise_filter.1130404945
Short name	T564
Test name
Test status
Simulation time	38291860117 ps
CPU time	17.91 seconds
Started	May 30 12:52:55 PM PDT 24
Finished	May 30 12:53:13 PM PDT 24
Peak memory	200400 kb
Host	smart-822fe99d-01a5-4949-af18-f359aad68da8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130404945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1130404945
Directory	/workspace/45.uart_noise_filter/latest

Test location	/workspace/coverage/default/45.uart_perf.2596845829
Short name	T262
Test name
Test status
Simulation time	19501316185 ps
CPU time	429.13 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 01:00:06 PM PDT 24
Peak memory	200308 kb
Host	smart-f90f8921-ede3-4763-be7c-a41196651aca
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2596845829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2596845829
Directory	/workspace/45.uart_perf/latest

Test location	/workspace/coverage/default/45.uart_rx_oversample.2882226685
Short name	T442
Test name
Test status
Simulation time	6228196997 ps
CPU time	54.15 seconds
Started	May 30 12:52:45 PM PDT 24
Finished	May 30 12:53:40 PM PDT 24
Peak memory	198972 kb
Host	smart-84ef553e-f26d-4978-9147-a5cc6d8cdf6b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2882226685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2882226685
Directory	/workspace/45.uart_rx_oversample/latest

Test location	/workspace/coverage/default/45.uart_rx_parity_err.3539835313
Short name	T271
Test name
Test status
Simulation time	62133800395 ps
CPU time	85.59 seconds
Started	May 30 12:52:58 PM PDT 24
Finished	May 30 12:54:24 PM PDT 24
Peak memory	200192 kb
Host	smart-e4a7cbb2-6898-49ec-8e97-41e93c9cce33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3539835313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3539835313
Directory	/workspace/45.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/45.uart_rx_start_bit_filter.1936284437
Short name	T572
Test name
Test status
Simulation time	3138056494 ps
CPU time	4.99 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 12:53:02 PM PDT 24
Peak memory	196136 kb
Host	smart-a97d4481-37be-40f4-8ee4-2734f3be931b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936284437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1936284437
Directory	/workspace/45.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/45.uart_smoke.488822005
Short name	T649
Test name
Test status
Simulation time	5915179940 ps
CPU time	23.31 seconds
Started	May 30 12:52:52 PM PDT 24
Finished	May 30 12:53:16 PM PDT 24
Peak memory	200132 kb
Host	smart-cd62b5f1-aecd-4dd6-90be-ce0d8d1ff80f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=488822005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.488822005
Directory	/workspace/45.uart_smoke/latest

Test location	/workspace/coverage/default/45.uart_stress_all.2769847304
Short name	T272
Test name
Test status
Simulation time	96936618733 ps
CPU time	132.27 seconds
Started	May 30 12:52:57 PM PDT 24
Finished	May 30 12:55:10 PM PDT 24
Peak memory	200332 kb
Host	smart-cd895a7d-3215-4dd2-8c08-571dace382f1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769847304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2769847304
Directory	/workspace/45.uart_stress_all/latest

Test location	/workspace/coverage/default/45.uart_stress_all_with_rand_reset.1112625412
Short name	T111
Test name
Test status
Simulation time	47779851229 ps
CPU time	410.54 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 12:59:48 PM PDT 24
Peak memory	216472 kb
Host	smart-73eb431c-6003-4e1c-92e4-89a52ccdf200
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112625412 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1112625412
Directory	/workspace/45.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.uart_tx_ovrd.3478535640
Short name	T384
Test name
Test status
Simulation time	741002660 ps
CPU time	4.8 seconds
Started	May 30 12:52:57 PM PDT 24
Finished	May 30 12:53:02 PM PDT 24
Peak memory	199404 kb
Host	smart-ee30a2e9-3e14-41d0-8200-42fa7d4fe34a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3478535640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3478535640
Directory	/workspace/45.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/45.uart_tx_rx.2336434196
Short name	T1145
Test name
Test status
Simulation time	152975329650 ps
CPU time	475.25 seconds
Started	May 30 12:52:44 PM PDT 24
Finished	May 30 01:00:40 PM PDT 24
Peak memory	200380 kb
Host	smart-2b3ac5ca-d0bc-4e8b-aa8d-8b8027a53791
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2336434196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2336434196
Directory	/workspace/45.uart_tx_rx/latest

Test location	/workspace/coverage/default/46.uart_alert_test.2254331244
Short name	T585
Test name
Test status
Simulation time	52640545 ps
CPU time	0.56 seconds
Started	May 30 12:52:57 PM PDT 24
Finished	May 30 12:52:59 PM PDT 24
Peak memory	194732 kb
Host	smart-27589e6a-6096-477e-afb5-37e467510838
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254331244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2254331244
Directory	/workspace/46.uart_alert_test/latest

Test location	/workspace/coverage/default/46.uart_fifo_full.87887854
Short name	T117
Test name
Test status
Simulation time	331796067098 ps
CPU time	190.79 seconds
Started	May 30 12:52:55 PM PDT 24
Finished	May 30 12:56:07 PM PDT 24
Peak memory	200324 kb
Host	smart-0cb0d087-84cb-42ff-aefc-9574836563b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87887854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.87887854
Directory	/workspace/46.uart_fifo_full/latest

Test location	/workspace/coverage/default/46.uart_fifo_overflow.3854374399
Short name	T1034
Test name
Test status
Simulation time	149760055672 ps
CPU time	56.42 seconds
Started	May 30 12:52:57 PM PDT 24
Finished	May 30 12:53:54 PM PDT 24
Peak memory	200256 kb
Host	smart-1e53a18b-2e1e-4ddc-9a2a-85aae91f340d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3854374399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3854374399
Directory	/workspace/46.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/46.uart_fifo_reset.2479483058
Short name	T857
Test name
Test status
Simulation time	75875058201 ps
CPU time	28.92 seconds
Started	May 30 12:52:57 PM PDT 24
Finished	May 30 12:53:27 PM PDT 24
Peak memory	200216 kb
Host	smart-ec0d19e5-8034-4262-b847-5b58c21f8bfe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479483058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2479483058
Directory	/workspace/46.uart_fifo_reset/latest

Test location	/workspace/coverage/default/46.uart_intr.1251860309
Short name	T727
Test name
Test status
Simulation time	24753091409 ps
CPU time	25.66 seconds
Started	May 30 12:52:57 PM PDT 24
Finished	May 30 12:53:23 PM PDT 24
Peak memory	200320 kb
Host	smart-2f3e2b0f-35dc-4857-9528-761cb708b029
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251860309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1251860309
Directory	/workspace/46.uart_intr/latest

Test location	/workspace/coverage/default/46.uart_long_xfer_wo_dly.403404056
Short name	T773
Test name
Test status
Simulation time	220090412640 ps
CPU time	304.54 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 12:58:02 PM PDT 24
Peak memory	200380 kb
Host	smart-597969ca-8253-4d04-9ff2-301e1d67b51c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=403404056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.403404056
Directory	/workspace/46.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/46.uart_loopback.921989314
Short name	T917
Test name
Test status
Simulation time	4201701349 ps
CPU time	2.67 seconds
Started	May 30 12:52:55 PM PDT 24
Finished	May 30 12:52:58 PM PDT 24
Peak memory	199464 kb
Host	smart-3d5c47a8-a32a-4ee4-b13f-1912c727b777
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=921989314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.921989314
Directory	/workspace/46.uart_loopback/latest

Test location	/workspace/coverage/default/46.uart_noise_filter.1529421959
Short name	T618
Test name
Test status
Simulation time	23273384884 ps
CPU time	24.89 seconds
Started	May 30 12:52:55 PM PDT 24
Finished	May 30 12:53:21 PM PDT 24
Peak memory	198664 kb
Host	smart-b0f140ec-4ac4-446b-9376-239a130d6150
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529421959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1529421959
Directory	/workspace/46.uart_noise_filter/latest

Test location	/workspace/coverage/default/46.uart_perf.887436664
Short name	T299
Test name
Test status
Simulation time	17808552617 ps
CPU time	230.01 seconds
Started	May 30 12:52:55 PM PDT 24
Finished	May 30 12:56:45 PM PDT 24
Peak memory	200340 kb
Host	smart-7adbeecb-174c-4572-aaed-f84c0e1aa9ba
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=887436664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.887436664
Directory	/workspace/46.uart_perf/latest

Test location	/workspace/coverage/default/46.uart_rx_oversample.4276241425
Short name	T865
Test name
Test status
Simulation time	3376337255 ps
CPU time	13.4 seconds
Started	May 30 12:52:54 PM PDT 24
Finished	May 30 12:53:08 PM PDT 24
Peak memory	199304 kb
Host	smart-85c1f756-6afb-4000-9cad-f7b4e72216e2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4276241425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.4276241425
Directory	/workspace/46.uart_rx_oversample/latest

Test location	/workspace/coverage/default/46.uart_rx_parity_err.1025234036
Short name	T718
Test name
Test status
Simulation time	55455699928 ps
CPU time	86.34 seconds
Started	May 30 12:52:55 PM PDT 24
Finished	May 30 12:54:23 PM PDT 24
Peak memory	200048 kb
Host	smart-a9da460e-7917-42f4-83cf-18d5010349aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1025234036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1025234036
Directory	/workspace/46.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/46.uart_rx_start_bit_filter.35784538
Short name	T784
Test name
Test status
Simulation time	65393963310 ps
CPU time	26.31 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 12:53:24 PM PDT 24
Peak memory	196360 kb
Host	smart-e167077f-f7b4-489f-9d2f-7791a06601bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=35784538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.35784538
Directory	/workspace/46.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/46.uart_smoke.1201116241
Short name	T396
Test name
Test status
Simulation time	963023152 ps
CPU time	1.28 seconds
Started	May 30 12:52:55 PM PDT 24
Finished	May 30 12:52:57 PM PDT 24
Peak memory	198972 kb
Host	smart-f7973645-1597-4a0a-a7cb-c90ed4df5dcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201116241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1201116241
Directory	/workspace/46.uart_smoke/latest

Test location	/workspace/coverage/default/46.uart_stress_all.1693970246
Short name	T131
Test name
Test status
Simulation time	159514830233 ps
CPU time	495.75 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 01:01:13 PM PDT 24
Peak memory	200256 kb
Host	smart-404c6f29-29ec-4b78-bec1-6998019e5fe7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693970246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1693970246
Directory	/workspace/46.uart_stress_all/latest

Test location	/workspace/coverage/default/46.uart_stress_all_with_rand_reset.2429567697
Short name	T1094
Test name
Test status
Simulation time	59162262395 ps
CPU time	579.28 seconds
Started	May 30 12:52:58 PM PDT 24
Finished	May 30 01:02:38 PM PDT 24
Peak memory	216768 kb
Host	smart-f6d31c95-da2a-4b75-9882-21592549d147
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429567697 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2429567697
Directory	/workspace/46.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.uart_tx_ovrd.3527041778
Short name	T391
Test name
Test status
Simulation time	817290964 ps
CPU time	2.01 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 12:52:59 PM PDT 24
Peak memory	198880 kb
Host	smart-843d8244-b600-4099-a178-a09fcc71cec9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3527041778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3527041778
Directory	/workspace/46.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/46.uart_tx_rx.3190016713
Short name	T850
Test name
Test status
Simulation time	23692739666 ps
CPU time	40.32 seconds
Started	May 30 12:52:53 PM PDT 24
Finished	May 30 12:53:34 PM PDT 24
Peak memory	200376 kb
Host	smart-3a6ffa0b-c76f-44ce-bde5-add363fd1f21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3190016713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3190016713
Directory	/workspace/46.uart_tx_rx/latest

Test location	/workspace/coverage/default/47.uart_alert_test.3660369968
Short name	T423
Test name
Test status
Simulation time	117618385 ps
CPU time	0.54 seconds
Started	May 30 12:53:20 PM PDT 24
Finished	May 30 12:53:22 PM PDT 24
Peak memory	195704 kb
Host	smart-6150c570-9336-4ad0-b0cc-25d148c1cfa2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660369968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3660369968
Directory	/workspace/47.uart_alert_test/latest

Test location	/workspace/coverage/default/47.uart_fifo_full.1617219427
Short name	T107
Test name
Test status
Simulation time	13525778022 ps
CPU time	13.54 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 12:53:10 PM PDT 24
Peak memory	200268 kb
Host	smart-0351e5b0-4ca8-49d7-abb1-f343cb7e0c96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1617219427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1617219427
Directory	/workspace/47.uart_fifo_full/latest

Test location	/workspace/coverage/default/47.uart_fifo_overflow.1891717917
Short name	T644
Test name
Test status
Simulation time	19384855779 ps
CPU time	35.6 seconds
Started	May 30 12:52:54 PM PDT 24
Finished	May 30 12:53:31 PM PDT 24
Peak memory	200172 kb
Host	smart-a6f3872c-4a90-40c1-95ea-c02ea1282025
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1891717917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1891717917
Directory	/workspace/47.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/47.uart_fifo_reset.3673779481
Short name	T881
Test name
Test status
Simulation time	91021586284 ps
CPU time	39.34 seconds
Started	May 30 12:52:54 PM PDT 24
Finished	May 30 12:53:34 PM PDT 24
Peak memory	200320 kb
Host	smart-45d89996-61dd-4933-b5f7-68004ba5c1da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673779481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3673779481
Directory	/workspace/47.uart_fifo_reset/latest

Test location	/workspace/coverage/default/47.uart_intr.207108319
Short name	T656
Test name
Test status
Simulation time	264660212729 ps
CPU time	444 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 01:00:21 PM PDT 24
Peak memory	198800 kb
Host	smart-3354e9eb-72d1-4776-a40e-14257c028680
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207108319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.207108319
Directory	/workspace/47.uart_intr/latest

Test location	/workspace/coverage/default/47.uart_long_xfer_wo_dly.3978817063
Short name	T514
Test name
Test status
Simulation time	218275291402 ps
CPU time	255.7 seconds
Started	May 30 12:53:08 PM PDT 24
Finished	May 30 12:57:25 PM PDT 24
Peak memory	200364 kb
Host	smart-b784cda6-c429-43c6-a330-0f65a4469b60
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3978817063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3978817063
Directory	/workspace/47.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/47.uart_loopback.3575805494
Short name	T643
Test name
Test status
Simulation time	5159881762 ps
CPU time	5.34 seconds
Started	May 30 12:53:20 PM PDT 24
Finished	May 30 12:53:26 PM PDT 24
Peak memory	200280 kb
Host	smart-82ca60b2-ef92-4d51-8f2a-b2e92ed192c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3575805494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3575805494
Directory	/workspace/47.uart_loopback/latest

Test location	/workspace/coverage/default/47.uart_noise_filter.1664564368
Short name	T909
Test name
Test status
Simulation time	161455278043 ps
CPU time	23.61 seconds
Started	May 30 12:52:54 PM PDT 24
Finished	May 30 12:53:18 PM PDT 24
Peak memory	208740 kb
Host	smart-61e30cba-03a1-4da6-9ed6-a23e9a89489d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664564368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1664564368
Directory	/workspace/47.uart_noise_filter/latest

Test location	/workspace/coverage/default/47.uart_perf.3324554281
Short name	T1002
Test name
Test status
Simulation time	28179232460 ps
CPU time	1331.87 seconds
Started	May 30 12:53:20 PM PDT 24
Finished	May 30 01:15:33 PM PDT 24
Peak memory	200276 kb
Host	smart-eb2bf906-234d-40d5-8a56-dbb4b82c5c7e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3324554281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3324554281
Directory	/workspace/47.uart_perf/latest

Test location	/workspace/coverage/default/47.uart_rx_oversample.2408854169
Short name	T1072
Test name
Test status
Simulation time	6891504796 ps
CPU time	16.12 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 12:53:13 PM PDT 24
Peak memory	199532 kb
Host	smart-d2a1641c-698f-48bc-8a85-5eff82be1adf
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2408854169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2408854169
Directory	/workspace/47.uart_rx_oversample/latest

Test location	/workspace/coverage/default/47.uart_rx_parity_err.286323372
Short name	T1130
Test name
Test status
Simulation time	125993182570 ps
CPU time	56.1 seconds
Started	May 30 12:53:07 PM PDT 24
Finished	May 30 12:54:04 PM PDT 24
Peak memory	200216 kb
Host	smart-34bab6cf-0171-48b2-a626-118da9263010
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=286323372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.286323372
Directory	/workspace/47.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/47.uart_rx_start_bit_filter.2797930223
Short name	T927
Test name
Test status
Simulation time	3339503051 ps
CPU time	3.91 seconds
Started	May 30 12:53:11 PM PDT 24
Finished	May 30 12:53:16 PM PDT 24
Peak memory	196272 kb
Host	smart-d7e7a36b-9912-47cb-bec8-d32ce4607e9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2797930223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2797930223
Directory	/workspace/47.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/47.uart_smoke.1530064418
Short name	T310
Test name
Test status
Simulation time	6102081549 ps
CPU time	68.32 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 12:54:05 PM PDT 24
Peak memory	200296 kb
Host	smart-18eecbb0-4380-4807-8623-f2e559403c5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530064418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1530064418
Directory	/workspace/47.uart_smoke/latest

Test location	/workspace/coverage/default/47.uart_stress_all.1638076197
Short name	T998
Test name
Test status
Simulation time	188604235920 ps
CPU time	1111.14 seconds
Started	May 30 12:53:09 PM PDT 24
Finished	May 30 01:11:42 PM PDT 24
Peak memory	208764 kb
Host	smart-58f1d71c-bf03-483e-8024-9a1b222ce279
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638076197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1638076197
Directory	/workspace/47.uart_stress_all/latest

Test location	/workspace/coverage/default/47.uart_stress_all_with_rand_reset.656240455
Short name	T752
Test name
Test status
Simulation time	365217917281 ps
CPU time	1038.74 seconds
Started	May 30 12:53:09 PM PDT 24
Finished	May 30 01:10:29 PM PDT 24
Peak memory	233396 kb
Host	smart-775795f3-1216-4688-8a8b-62cbc451aaf5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656240455 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.656240455
Directory	/workspace/47.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.uart_tx_ovrd.3665068616
Short name	T659
Test name
Test status
Simulation time	758062459 ps
CPU time	2.62 seconds
Started	May 30 12:53:09 PM PDT 24
Finished	May 30 12:53:14 PM PDT 24
Peak memory	199740 kb
Host	smart-3cab4463-0f72-432d-9912-5a32d792e4e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3665068616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3665068616
Directory	/workspace/47.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/47.uart_tx_rx.2291478791
Short name	T322
Test name
Test status
Simulation time	74974810041 ps
CPU time	65.33 seconds
Started	May 30 12:52:56 PM PDT 24
Finished	May 30 12:54:02 PM PDT 24
Peak memory	200304 kb
Host	smart-8661da1a-95cc-4a2b-9900-ab8121ddf392
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2291478791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2291478791
Directory	/workspace/47.uart_tx_rx/latest

Test location	/workspace/coverage/default/48.uart_alert_test.1677643222
Short name	T497
Test name
Test status
Simulation time	14909906 ps
CPU time	0.55 seconds
Started	May 30 12:53:08 PM PDT 24
Finished	May 30 12:53:10 PM PDT 24
Peak memory	194724 kb
Host	smart-ac68e134-c335-4d4a-8425-9f546795fd58
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677643222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1677643222
Directory	/workspace/48.uart_alert_test/latest

Test location	/workspace/coverage/default/48.uart_fifo_full.2374104559
Short name	T573
Test name
Test status
Simulation time	17554475420 ps
CPU time	27.54 seconds
Started	May 30 12:53:10 PM PDT 24
Finished	May 30 12:53:39 PM PDT 24
Peak memory	200416 kb
Host	smart-0d45d924-1151-469d-a767-17961ea8d1ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374104559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2374104559
Directory	/workspace/48.uart_fifo_full/latest

Test location	/workspace/coverage/default/48.uart_fifo_overflow.3724837342
Short name	T287
Test name
Test status
Simulation time	71853992796 ps
CPU time	286.23 seconds
Started	May 30 12:53:07 PM PDT 24
Finished	May 30 12:57:54 PM PDT 24
Peak memory	200352 kb
Host	smart-7752c70c-58bb-4774-abca-3b7de3b80c17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724837342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3724837342
Directory	/workspace/48.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/48.uart_fifo_reset.286282382
Short name	T273
Test name
Test status
Simulation time	14085718539 ps
CPU time	6.03 seconds
Started	May 30 12:53:09 PM PDT 24
Finished	May 30 12:53:17 PM PDT 24
Peak memory	199968 kb
Host	smart-6c1127b5-4ef4-4c92-90d2-b626ebfdeabd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=286282382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.286282382
Directory	/workspace/48.uart_fifo_reset/latest

Test location	/workspace/coverage/default/48.uart_intr.3203934591
Short name	T744
Test name
Test status
Simulation time	31456956986 ps
CPU time	51.24 seconds
Started	May 30 12:53:08 PM PDT 24
Finished	May 30 12:54:00 PM PDT 24
Peak memory	200384 kb
Host	smart-bf57fd13-c9a4-460c-b43c-f507f4ca7c8e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203934591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3203934591
Directory	/workspace/48.uart_intr/latest

Test location	/workspace/coverage/default/48.uart_long_xfer_wo_dly.2400623845
Short name	T692
Test name
Test status
Simulation time	68196226138 ps
CPU time	175.43 seconds
Started	May 30 12:53:10 PM PDT 24
Finished	May 30 12:56:07 PM PDT 24
Peak memory	200296 kb
Host	smart-46bea93f-d8c9-4afd-9486-7ec6b9fc1897
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2400623845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2400623845
Directory	/workspace/48.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/48.uart_loopback.586882811
Short name	T386
Test name
Test status
Simulation time	9162769242 ps
CPU time	19.55 seconds
Started	May 30 12:53:11 PM PDT 24
Finished	May 30 12:53:32 PM PDT 24
Peak memory	200400 kb
Host	smart-c5ead707-f3fd-4a62-907c-1a8375363c7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586882811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.586882811
Directory	/workspace/48.uart_loopback/latest

Test location	/workspace/coverage/default/48.uart_noise_filter.2650232321
Short name	T1082
Test name
Test status
Simulation time	570637696407 ps
CPU time	109.98 seconds
Started	May 30 12:53:07 PM PDT 24
Finished	May 30 12:54:58 PM PDT 24
Peak memory	208296 kb
Host	smart-b06c8bc6-225a-4a68-9b4b-591650b6cd61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2650232321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2650232321
Directory	/workspace/48.uart_noise_filter/latest

Test location	/workspace/coverage/default/48.uart_perf.2703363630
Short name	T315
Test name
Test status
Simulation time	12655664674 ps
CPU time	116.31 seconds
Started	May 30 12:53:07 PM PDT 24
Finished	May 30 12:55:04 PM PDT 24
Peak memory	200316 kb
Host	smart-2b878b99-441b-42bb-8953-c21e979ed0cd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2703363630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2703363630
Directory	/workspace/48.uart_perf/latest

Test location	/workspace/coverage/default/48.uart_rx_oversample.1427036662
Short name	T613
Test name
Test status
Simulation time	5577388322 ps
CPU time	13.79 seconds
Started	May 30 12:53:09 PM PDT 24
Finished	May 30 12:53:24 PM PDT 24
Peak memory	199456 kb
Host	smart-0878f443-61dc-4de7-97c5-a90a4f318fb5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1427036662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1427036662
Directory	/workspace/48.uart_rx_oversample/latest

Test location	/workspace/coverage/default/48.uart_rx_parity_err.3522071467
Short name	T882
Test name
Test status
Simulation time	16394343176 ps
CPU time	29.39 seconds
Started	May 30 12:53:10 PM PDT 24
Finished	May 30 12:53:41 PM PDT 24
Peak memory	200228 kb
Host	smart-c60103bc-3ecb-4969-a273-5a9f623ac4df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3522071467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3522071467
Directory	/workspace/48.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/48.uart_rx_start_bit_filter.703610604
Short name	T593
Test name
Test status
Simulation time	45404044929 ps
CPU time	27.99 seconds
Started	May 30 12:53:11 PM PDT 24
Finished	May 30 12:53:40 PM PDT 24
Peak memory	196388 kb
Host	smart-bcd8ab73-7ada-4aad-b5cb-52968ce0247d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=703610604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.703610604
Directory	/workspace/48.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/48.uart_smoke.3566319294
Short name	T377
Test name
Test status
Simulation time	495852548 ps
CPU time	2.15 seconds
Started	May 30 12:53:09 PM PDT 24
Finished	May 30 12:53:12 PM PDT 24
Peak memory	198680 kb
Host	smart-eb60b990-db30-4f54-98a3-d57d53961f80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3566319294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3566319294
Directory	/workspace/48.uart_smoke/latest

Test location	/workspace/coverage/default/48.uart_stress_all_with_rand_reset.2396761041
Short name	T32
Test name
Test status
Simulation time	53859894181 ps
CPU time	251.96 seconds
Started	May 30 12:53:10 PM PDT 24
Finished	May 30 12:57:23 PM PDT 24
Peak memory	216952 kb
Host	smart-981b9934-be94-4d2c-859a-a64a3cfa065e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396761041 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2396761041
Directory	/workspace/48.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.uart_tx_ovrd.1760747335
Short name	T414
Test name
Test status
Simulation time	536326732 ps
CPU time	3.57 seconds
Started	May 30 12:53:11 PM PDT 24
Finished	May 30 12:53:16 PM PDT 24
Peak memory	199104 kb
Host	smart-59225f3b-641d-49ea-8992-2edc423ec97a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760747335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1760747335
Directory	/workspace/48.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/48.uart_tx_rx.2058730404
Short name	T431
Test name
Test status
Simulation time	93057057243 ps
CPU time	77.46 seconds
Started	May 30 12:53:07 PM PDT 24
Finished	May 30 12:54:26 PM PDT 24
Peak memory	200384 kb
Host	smart-aa09619a-6ab2-42c1-b151-312204b2efbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058730404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2058730404
Directory	/workspace/48.uart_tx_rx/latest

Test location	/workspace/coverage/default/49.uart_alert_test.2125760467
Short name	T530
Test name
Test status
Simulation time	13200720 ps
CPU time	0.54 seconds
Started	May 30 12:53:10 PM PDT 24
Finished	May 30 12:53:12 PM PDT 24
Peak memory	195760 kb
Host	smart-14be0c5f-8533-4c27-8c66-1ed672301425
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125760467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2125760467
Directory	/workspace/49.uart_alert_test/latest

Test location	/workspace/coverage/default/49.uart_fifo_full.3801070231
Short name	T835
Test name
Test status
Simulation time	110246634690 ps
CPU time	83.67 seconds
Started	May 30 12:53:08 PM PDT 24
Finished	May 30 12:54:33 PM PDT 24
Peak memory	200348 kb
Host	smart-2a286157-3d31-4af3-8dc3-4736eb3f3331
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3801070231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3801070231
Directory	/workspace/49.uart_fifo_full/latest

Test location	/workspace/coverage/default/49.uart_fifo_overflow.1881346472
Short name	T279
Test name
Test status
Simulation time	118416147452 ps
CPU time	179.36 seconds
Started	May 30 12:53:10 PM PDT 24
Finished	May 30 12:56:11 PM PDT 24
Peak memory	200320 kb
Host	smart-9ae6674c-f5a8-46df-be98-b30ce787502a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1881346472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1881346472
Directory	/workspace/49.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/49.uart_intr.1885782459
Short name	T57
Test name
Test status
Simulation time	58307629957 ps
CPU time	29.24 seconds
Started	May 30 12:53:09 PM PDT 24
Finished	May 30 12:53:40 PM PDT 24
Peak memory	200360 kb
Host	smart-440aa787-6300-4f33-a8ed-9cf0919d09de
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885782459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1885782459
Directory	/workspace/49.uart_intr/latest

Test location	/workspace/coverage/default/49.uart_loopback.480340523
Short name	T641
Test name
Test status
Simulation time	4432510240 ps
CPU time	8.43 seconds
Started	May 30 12:53:19 PM PDT 24
Finished	May 30 12:53:28 PM PDT 24
Peak memory	197836 kb
Host	smart-e12fe465-e330-455d-a146-0d5f4a6b6b18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480340523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.480340523
Directory	/workspace/49.uart_loopback/latest

Test location	/workspace/coverage/default/49.uart_noise_filter.4129562756
Short name	T1013
Test name
Test status
Simulation time	29891579723 ps
CPU time	10.73 seconds
Started	May 30 12:53:10 PM PDT 24
Finished	May 30 12:53:23 PM PDT 24
Peak memory	194968 kb
Host	smart-6114c481-e7d8-40b8-bb69-f58525e21a9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4129562756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.4129562756
Directory	/workspace/49.uart_noise_filter/latest

Test location	/workspace/coverage/default/49.uart_perf.4186228644
Short name	T486
Test name
Test status
Simulation time	13406846407 ps
CPU time	178.25 seconds
Started	May 30 12:53:09 PM PDT 24
Finished	May 30 12:56:09 PM PDT 24
Peak memory	200372 kb
Host	smart-a1e24485-400e-456f-a006-c1ba5554552b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4186228644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.4186228644
Directory	/workspace/49.uart_perf/latest

Test location	/workspace/coverage/default/49.uart_rx_oversample.603198049
Short name	T1091
Test name
Test status
Simulation time	4223291769 ps
CPU time	35.45 seconds
Started	May 30 12:53:21 PM PDT 24
Finished	May 30 12:53:57 PM PDT 24
Peak memory	199612 kb
Host	smart-aa595ea4-9cd3-4df1-bfe3-f357db6e0894
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=603198049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.603198049
Directory	/workspace/49.uart_rx_oversample/latest

Test location	/workspace/coverage/default/49.uart_rx_parity_err.1528825855
Short name	T294
Test name
Test status
Simulation time	61834407503 ps
CPU time	103.75 seconds
Started	May 30 12:53:11 PM PDT 24
Finished	May 30 12:54:56 PM PDT 24
Peak memory	200300 kb
Host	smart-be7ffafb-d108-499d-b9f1-f20fb4d18ee0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1528825855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1528825855
Directory	/workspace/49.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/49.uart_rx_start_bit_filter.1797934065
Short name	T474
Test name
Test status
Simulation time	37514840588 ps
CPU time	36.99 seconds
Started	May 30 12:53:06 PM PDT 24
Finished	May 30 12:53:44 PM PDT 24
Peak memory	196644 kb
Host	smart-b32fb199-f2a3-4ecf-a4b5-1a2936280e7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1797934065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1797934065
Directory	/workspace/49.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/49.uart_smoke.2138792856
Short name	T583
Test name
Test status
Simulation time	542502651 ps
CPU time	1.92 seconds
Started	May 30 12:53:20 PM PDT 24
Finished	May 30 12:53:22 PM PDT 24
Peak memory	199920 kb
Host	smart-9ac6582a-82c7-4859-b2c7-fe8071b49759
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2138792856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2138792856
Directory	/workspace/49.uart_smoke/latest

Test location	/workspace/coverage/default/49.uart_stress_all.1406913461
Short name	T859
Test name
Test status
Simulation time	118478957855 ps
CPU time	59.99 seconds
Started	May 30 12:53:10 PM PDT 24
Finished	May 30 12:54:12 PM PDT 24
Peak memory	200300 kb
Host	smart-955adbc9-a32c-4229-a32c-42ffc72a0cbd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406913461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1406913461
Directory	/workspace/49.uart_stress_all/latest

Test location	/workspace/coverage/default/49.uart_stress_all_with_rand_reset.1581967433
Short name	T747
Test name
Test status
Simulation time	114766305386 ps
CPU time	511.07 seconds
Started	May 30 12:53:10 PM PDT 24
Finished	May 30 01:01:43 PM PDT 24
Peak memory	217068 kb
Host	smart-de66504f-bf22-42c2-8691-9f2d7324871e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581967433 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1581967433
Directory	/workspace/49.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.uart_tx_ovrd.4288114756
Short name	T259
Test name
Test status
Simulation time	817370137 ps
CPU time	3.65 seconds
Started	May 30 12:53:06 PM PDT 24
Finished	May 30 12:53:11 PM PDT 24
Peak memory	199788 kb
Host	smart-a7578678-a305-45d9-8900-b763a5b3d2aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288114756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4288114756
Directory	/workspace/49.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/49.uart_tx_rx.1537510033
Short name	T415
Test name
Test status
Simulation time	37051891722 ps
CPU time	63.96 seconds
Started	May 30 12:53:10 PM PDT 24
Finished	May 30 12:54:16 PM PDT 24
Peak memory	200212 kb
Host	smart-abac0513-bcca-41f2-8831-e4d5c2502a70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537510033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1537510033
Directory	/workspace/49.uart_tx_rx/latest

Test location	/workspace/coverage/default/5.uart_alert_test.2574740141
Short name	T657
Test name
Test status
Simulation time	13548234 ps
CPU time	0.53 seconds
Started	May 30 12:50:25 PM PDT 24
Finished	May 30 12:50:27 PM PDT 24
Peak memory	194740 kb
Host	smart-d93cc9f2-3dc6-4bfb-91da-34e9dcd11157
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574740141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2574740141
Directory	/workspace/5.uart_alert_test/latest

Test location	/workspace/coverage/default/5.uart_fifo_full.3219421909
Short name	T792
Test name
Test status
Simulation time	52585099487 ps
CPU time	47.82 seconds
Started	May 30 12:50:22 PM PDT 24
Finished	May 30 12:51:10 PM PDT 24
Peak memory	200300 kb
Host	smart-89bb2cae-9c86-436d-84cd-834417e950be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3219421909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3219421909
Directory	/workspace/5.uart_fifo_full/latest

Test location	/workspace/coverage/default/5.uart_fifo_overflow.66977740
Short name	T1108
Test name
Test status
Simulation time	34497115323 ps
CPU time	55.73 seconds
Started	May 30 12:50:24 PM PDT 24
Finished	May 30 12:51:21 PM PDT 24
Peak memory	200400 kb
Host	smart-944a7f79-7ca1-484b-a6e6-cf97e7edfe8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66977740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.66977740
Directory	/workspace/5.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/5.uart_fifo_reset.2967397570
Short name	T134
Test name
Test status
Simulation time	33053183373 ps
CPU time	15.86 seconds
Started	May 30 12:50:18 PM PDT 24
Finished	May 30 12:50:35 PM PDT 24
Peak memory	200016 kb
Host	smart-9c2c12c5-a753-4c4d-a118-7c2263e84cc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2967397570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2967397570
Directory	/workspace/5.uart_fifo_reset/latest

Test location	/workspace/coverage/default/5.uart_intr.4130926016
Short name	T1168
Test name
Test status
Simulation time	207275304124 ps
CPU time	238.31 seconds
Started	May 30 12:50:22 PM PDT 24
Finished	May 30 12:54:21 PM PDT 24
Peak memory	200160 kb
Host	smart-d37c5a08-e6e4-43e5-abd3-ec28306e7dd1
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130926016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.4130926016
Directory	/workspace/5.uart_intr/latest

Test location	/workspace/coverage/default/5.uart_long_xfer_wo_dly.1858780343
Short name	T577
Test name
Test status
Simulation time	297701364780 ps
CPU time	210.14 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 12:53:57 PM PDT 24
Peak memory	200272 kb
Host	smart-ce38747e-9158-48c7-bce1-5616cbbd2cac
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1858780343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1858780343
Directory	/workspace/5.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/5.uart_loopback.2270305975
Short name	T385
Test name
Test status
Simulation time	6213686792 ps
CPU time	12.6 seconds
Started	May 30 12:50:23 PM PDT 24
Finished	May 30 12:50:37 PM PDT 24
Peak memory	199168 kb
Host	smart-b3227eae-293e-4c61-84d1-1659de3b3270
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270305975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2270305975
Directory	/workspace/5.uart_loopback/latest

Test location	/workspace/coverage/default/5.uart_noise_filter.3294367018
Short name	T834
Test name
Test status
Simulation time	28142474768 ps
CPU time	22.71 seconds
Started	May 30 12:50:28 PM PDT 24
Finished	May 30 12:50:52 PM PDT 24
Peak memory	200528 kb
Host	smart-4cf53a57-6989-4e1e-908f-11d17da72027
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3294367018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3294367018
Directory	/workspace/5.uart_noise_filter/latest

Test location	/workspace/coverage/default/5.uart_perf.791950051
Short name	T39
Test name
Test status
Simulation time	3831841907 ps
CPU time	107.92 seconds
Started	May 30 12:50:27 PM PDT 24
Finished	May 30 12:52:16 PM PDT 24
Peak memory	200392 kb
Host	smart-5da92a87-3c50-40bb-8a7d-f29a40ea545c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=791950051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.791950051
Directory	/workspace/5.uart_perf/latest

Test location	/workspace/coverage/default/5.uart_rx_oversample.2720694895
Short name	T876
Test name
Test status
Simulation time	6109552098 ps
CPU time	53.89 seconds
Started	May 30 12:50:21 PM PDT 24
Finished	May 30 12:51:16 PM PDT 24
Peak memory	199924 kb
Host	smart-463e36b2-0d87-4f98-9b82-341163fc3d23
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2720694895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2720694895
Directory	/workspace/5.uart_rx_oversample/latest

Test location	/workspace/coverage/default/5.uart_rx_parity_err.4170339725
Short name	T270
Test name
Test status
Simulation time	292975317780 ps
CPU time	51.09 seconds
Started	May 30 12:50:22 PM PDT 24
Finished	May 30 12:51:14 PM PDT 24
Peak memory	200368 kb
Host	smart-df9da2f2-085a-45c9-8b4b-837dbbeb5f22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4170339725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.4170339725
Directory	/workspace/5.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/5.uart_rx_start_bit_filter.486011245
Short name	T1008
Test name
Test status
Simulation time	4494385879 ps
CPU time	2.24 seconds
Started	May 30 12:50:23 PM PDT 24
Finished	May 30 12:50:26 PM PDT 24
Peak memory	196660 kb
Host	smart-f4001522-bc55-41f8-b575-59bac546b122
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=486011245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.486011245
Directory	/workspace/5.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/5.uart_smoke.1074650039
Short name	T596
Test name
Test status
Simulation time	660235905 ps
CPU time	3.36 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 12:50:30 PM PDT 24
Peak memory	200180 kb
Host	smart-b2d33b08-e218-42f5-ad23-4445161ac53d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1074650039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1074650039
Directory	/workspace/5.uart_smoke/latest

Test location	/workspace/coverage/default/5.uart_stress_all_with_rand_reset.368111849
Short name	T114
Test name
Test status
Simulation time	27845556216 ps
CPU time	388.26 seconds
Started	May 30 12:50:24 PM PDT 24
Finished	May 30 12:56:53 PM PDT 24
Peak memory	208676 kb
Host	smart-e7170441-727d-4456-94a0-17a8f1ac61c3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368111849 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.368111849
Directory	/workspace/5.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.uart_tx_ovrd.1067836667
Short name	T1053
Test name
Test status
Simulation time	6597779192 ps
CPU time	23.18 seconds
Started	May 30 12:50:23 PM PDT 24
Finished	May 30 12:50:48 PM PDT 24
Peak memory	200232 kb
Host	smart-8bdf6aa9-8cf9-4592-84cc-e7431ecfdfc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067836667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1067836667
Directory	/workspace/5.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/5.uart_tx_rx.1935918809
Short name	T864
Test name
Test status
Simulation time	101042311758 ps
CPU time	76.19 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 12:51:43 PM PDT 24
Peak memory	200332 kb
Host	smart-307a0eaf-32f7-48b4-b212-949a3fa9116b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1935918809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1935918809
Directory	/workspace/5.uart_tx_rx/latest

Test location	/workspace/coverage/default/50.uart_fifo_reset.1747487974
Short name	T151
Test name
Test status
Simulation time	192456184467 ps
CPU time	74.3 seconds
Started	May 30 12:53:06 PM PDT 24
Finished	May 30 12:54:21 PM PDT 24
Peak memory	200272 kb
Host	smart-687a1f64-90bd-48dd-82c0-d192be6c1484
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1747487974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1747487974
Directory	/workspace/50.uart_fifo_reset/latest

Test location	/workspace/coverage/default/50.uart_stress_all_with_rand_reset.3442052969
Short name	T839
Test name
Test status
Simulation time	30812531486 ps
CPU time	283.69 seconds
Started	May 30 12:53:11 PM PDT 24
Finished	May 30 12:57:56 PM PDT 24
Peak memory	216972 kb
Host	smart-98244bcc-e891-4a11-afe7-f2f3bfb47148
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442052969 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3442052969
Directory	/workspace/50.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/51.uart_fifo_reset.662746406
Short name	T697
Test name
Test status
Simulation time	20227194848 ps
CPU time	32.48 seconds
Started	May 30 12:53:08 PM PDT 24
Finished	May 30 12:53:41 PM PDT 24
Peak memory	200384 kb
Host	smart-9c676965-ad20-40a6-a410-bd4c0752a5bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=662746406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.662746406
Directory	/workspace/51.uart_fifo_reset/latest

Test location	/workspace/coverage/default/51.uart_stress_all_with_rand_reset.2758242913
Short name	T1121
Test name
Test status
Simulation time	579302394385 ps
CPU time	865.47 seconds
Started	May 30 12:53:20 PM PDT 24
Finished	May 30 01:07:46 PM PDT 24
Peak memory	216788 kb
Host	smart-b52fd94b-e9bd-4d04-8aab-37474fec39da
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758242913 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2758242913
Directory	/workspace/51.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/52.uart_fifo_reset.183774132
Short name	T202
Test name
Test status
Simulation time	20694868385 ps
CPU time	20.72 seconds
Started	May 30 12:53:19 PM PDT 24
Finished	May 30 12:53:40 PM PDT 24
Peak memory	200284 kb
Host	smart-8c8cf6ac-ba75-4874-9e9a-bc7268fc36c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=183774132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.183774132
Directory	/workspace/52.uart_fifo_reset/latest

Test location	/workspace/coverage/default/53.uart_fifo_reset.3480294158
Short name	T412
Test name
Test status
Simulation time	15179515733 ps
CPU time	12.32 seconds
Started	May 30 12:53:09 PM PDT 24
Finished	May 30 12:53:23 PM PDT 24
Peak memory	200344 kb
Host	smart-a5e55ef0-8369-4b2b-829f-aa0e205b935e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3480294158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3480294158
Directory	/workspace/53.uart_fifo_reset/latest

Test location	/workspace/coverage/default/53.uart_stress_all_with_rand_reset.3341463625
Short name	T826
Test name
Test status
Simulation time	73303416630 ps
CPU time	453.28 seconds
Started	May 30 12:53:08 PM PDT 24
Finished	May 30 01:00:43 PM PDT 24
Peak memory	216408 kb
Host	smart-f78a7975-f96a-40d4-8205-9a7a5c66b6be
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341463625 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3341463625
Directory	/workspace/53.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/54.uart_fifo_reset.2167135446
Short name	T266
Test name
Test status
Simulation time	192123672528 ps
CPU time	109.39 seconds
Started	May 30 12:53:08 PM PDT 24
Finished	May 30 12:54:59 PM PDT 24
Peak memory	200324 kb
Host	smart-3bdc16eb-1940-4aa0-9fad-00ceb4a5d60d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167135446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2167135446
Directory	/workspace/54.uart_fifo_reset/latest

Test location	/workspace/coverage/default/54.uart_stress_all_with_rand_reset.1518948713
Short name	T539
Test name
Test status
Simulation time	367871401840 ps
CPU time	715.93 seconds
Started	May 30 12:53:09 PM PDT 24
Finished	May 30 01:05:06 PM PDT 24
Peak memory	217184 kb
Host	smart-71d4c5dc-0ce0-410c-8601-ea33e256969e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518948713 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1518948713
Directory	/workspace/54.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/55.uart_fifo_reset.852459341
Short name	T954
Test name
Test status
Simulation time	28614876056 ps
CPU time	16.17 seconds
Started	May 30 12:53:21 PM PDT 24
Finished	May 30 12:53:38 PM PDT 24
Peak memory	200340 kb
Host	smart-5e837e11-e14b-4813-ba5f-c358137de326
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852459341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.852459341
Directory	/workspace/55.uart_fifo_reset/latest

Test location	/workspace/coverage/default/55.uart_stress_all_with_rand_reset.3318442348
Short name	T739
Test name
Test status
Simulation time	55586676035 ps
CPU time	714.37 seconds
Started	May 30 12:53:21 PM PDT 24
Finished	May 30 01:05:16 PM PDT 24
Peak memory	225064 kb
Host	smart-d5130e72-a187-43f0-b105-a6de46ef062f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318442348 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3318442348
Directory	/workspace/55.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/56.uart_fifo_reset.1218081123
Short name	T827
Test name
Test status
Simulation time	112840420665 ps
CPU time	165.43 seconds
Started	May 30 12:53:23 PM PDT 24
Finished	May 30 12:56:09 PM PDT 24
Peak memory	200308 kb
Host	smart-86213083-4376-4301-8ab4-c4ce80864332
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1218081123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1218081123
Directory	/workspace/56.uart_fifo_reset/latest

Test location	/workspace/coverage/default/56.uart_stress_all_with_rand_reset.1672643069
Short name	T971
Test name
Test status
Simulation time	65468431134 ps
CPU time	751.91 seconds
Started	May 30 12:53:22 PM PDT 24
Finished	May 30 01:05:55 PM PDT 24
Peak memory	216112 kb
Host	smart-44f0e7d3-8eac-4234-bd29-ad869afe2ccd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672643069 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1672643069
Directory	/workspace/56.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/57.uart_stress_all_with_rand_reset.2364150154
Short name	T1117
Test name
Test status
Simulation time	18495645836 ps
CPU time	296.61 seconds
Started	May 30 12:53:22 PM PDT 24
Finished	May 30 12:58:19 PM PDT 24
Peak memory	208632 kb
Host	smart-32a8b743-b16e-4365-ba4f-8f83a658ed9b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364150154 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2364150154
Directory	/workspace/57.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/58.uart_fifo_reset.2311599357
Short name	T905
Test name
Test status
Simulation time	76426112056 ps
CPU time	380.24 seconds
Started	May 30 12:53:20 PM PDT 24
Finished	May 30 12:59:41 PM PDT 24
Peak memory	200224 kb
Host	smart-096b59a9-7ab5-4334-b7d7-dd6ad74debd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2311599357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2311599357
Directory	/workspace/58.uart_fifo_reset/latest

Test location	/workspace/coverage/default/58.uart_stress_all_with_rand_reset.3448402129
Short name	T478
Test name
Test status
Simulation time	211916644555 ps
CPU time	540.19 seconds
Started	May 30 12:53:21 PM PDT 24
Finished	May 30 01:02:22 PM PDT 24
Peak memory	217044 kb
Host	smart-3ece44c6-7563-4cd6-92cc-eec7fe9834ed
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448402129 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3448402129
Directory	/workspace/58.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/59.uart_fifo_reset.3919606677
Short name	T320
Test name
Test status
Simulation time	110363123090 ps
CPU time	48.68 seconds
Started	May 30 12:53:23 PM PDT 24
Finished	May 30 12:54:13 PM PDT 24
Peak memory	200380 kb
Host	smart-a53b84cf-39d4-4062-bd16-5fbb86fe6389
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3919606677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3919606677
Directory	/workspace/59.uart_fifo_reset/latest

Test location	/workspace/coverage/default/59.uart_stress_all_with_rand_reset.1592648342
Short name	T1180
Test name
Test status
Simulation time	616889130740 ps
CPU time	777.67 seconds
Started	May 30 12:53:21 PM PDT 24
Finished	May 30 01:06:19 PM PDT 24
Peak memory	216836 kb
Host	smart-3cd5d015-eb8f-4ac4-84de-fedf3f09d1b0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592648342 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1592648342
Directory	/workspace/59.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.uart_alert_test.3485041392
Short name	T468
Test name
Test status
Simulation time	13258923 ps
CPU time	0.59 seconds
Started	May 30 12:50:27 PM PDT 24
Finished	May 30 12:50:29 PM PDT 24
Peak memory	195152 kb
Host	smart-2c098103-f193-4c66-b5d8-eab06ee509b3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485041392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3485041392
Directory	/workspace/6.uart_alert_test/latest

Test location	/workspace/coverage/default/6.uart_fifo_full.1008189246
Short name	T1055
Test name
Test status
Simulation time	48742046435 ps
CPU time	22.92 seconds
Started	May 30 12:50:23 PM PDT 24
Finished	May 30 12:50:47 PM PDT 24
Peak memory	199804 kb
Host	smart-da40b201-046d-4f07-b6b0-290c96f4207e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008189246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1008189246
Directory	/workspace/6.uart_fifo_full/latest

Test location	/workspace/coverage/default/6.uart_fifo_overflow.777516661
Short name	T1127
Test name
Test status
Simulation time	166047848731 ps
CPU time	134.94 seconds
Started	May 30 12:50:25 PM PDT 24
Finished	May 30 12:52:41 PM PDT 24
Peak memory	200344 kb
Host	smart-3496e9a0-6513-45c9-a46e-7444540583ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777516661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.777516661
Directory	/workspace/6.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/6.uart_fifo_reset.2367120202
Short name	T767
Test name
Test status
Simulation time	128236501644 ps
CPU time	190.73 seconds
Started	May 30 12:50:22 PM PDT 24
Finished	May 30 12:53:33 PM PDT 24
Peak memory	200384 kb
Host	smart-0b0dfe98-f10e-4a5c-99c7-e0e55cb84280
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367120202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2367120202
Directory	/workspace/6.uart_fifo_reset/latest

Test location	/workspace/coverage/default/6.uart_intr.2054229006
Short name	T770
Test name
Test status
Simulation time	24973201196 ps
CPU time	7.7 seconds
Started	May 30 12:50:22 PM PDT 24
Finished	May 30 12:50:30 PM PDT 24
Peak memory	198632 kb
Host	smart-3acabaad-2696-4fd6-82ac-9616504cf65f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054229006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2054229006
Directory	/workspace/6.uart_intr/latest

Test location	/workspace/coverage/default/6.uart_long_xfer_wo_dly.630859110
Short name	T1141
Test name
Test status
Simulation time	83431966868 ps
CPU time	400.57 seconds
Started	May 30 12:50:24 PM PDT 24
Finished	May 30 12:57:06 PM PDT 24
Peak memory	200372 kb
Host	smart-9249bb3f-afda-49fb-b615-f49cdf25f7d5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=630859110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.630859110
Directory	/workspace/6.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/6.uart_loopback.2467746567
Short name	T1177
Test name
Test status
Simulation time	61497999 ps
CPU time	0.58 seconds
Started	May 30 12:50:30 PM PDT 24
Finished	May 30 12:50:31 PM PDT 24
Peak memory	196172 kb
Host	smart-564aa476-1439-42d0-9826-f3c9ed1a05a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2467746567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2467746567
Directory	/workspace/6.uart_loopback/latest

Test location	/workspace/coverage/default/6.uart_noise_filter.505504702
Short name	T459
Test name
Test status
Simulation time	81011680445 ps
CPU time	76.96 seconds
Started	May 30 12:50:21 PM PDT 24
Finished	May 30 12:51:39 PM PDT 24
Peak memory	200460 kb
Host	smart-6eae1887-b54c-43e7-9dbe-35ce246bb8ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=505504702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.505504702
Directory	/workspace/6.uart_noise_filter/latest

Test location	/workspace/coverage/default/6.uart_perf.1649921092
Short name	T1124
Test name
Test status
Simulation time	26736157509 ps
CPU time	319.91 seconds
Started	May 30 12:50:20 PM PDT 24
Finished	May 30 12:55:42 PM PDT 24
Peak memory	200352 kb
Host	smart-214f1183-5521-47a5-a3ae-d1d5e4258141
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1649921092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1649921092
Directory	/workspace/6.uart_perf/latest

Test location	/workspace/coverage/default/6.uart_rx_oversample.3473843507
Short name	T334
Test name
Test status
Simulation time	2242748225 ps
CPU time	3.46 seconds
Started	May 30 12:50:18 PM PDT 24
Finished	May 30 12:50:22 PM PDT 24
Peak memory	198496 kb
Host	smart-ce74250d-d03a-48c5-89e8-5b961b71c171
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3473843507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3473843507
Directory	/workspace/6.uart_rx_oversample/latest

Test location	/workspace/coverage/default/6.uart_rx_parity_err.2048062164
Short name	T178
Test name
Test status
Simulation time	238211796550 ps
CPU time	30.06 seconds
Started	May 30 12:50:18 PM PDT 24
Finished	May 30 12:50:48 PM PDT 24
Peak memory	200176 kb
Host	smart-709acd2a-5981-4e6d-9d50-a872328e37bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2048062164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2048062164
Directory	/workspace/6.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/6.uart_rx_start_bit_filter.3526029094
Short name	T668
Test name
Test status
Simulation time	3724432794 ps
CPU time	2.39 seconds
Started	May 30 12:50:21 PM PDT 24
Finished	May 30 12:50:25 PM PDT 24
Peak memory	196176 kb
Host	smart-11d3aadf-a7aa-4e5e-9864-2f6ed1a0c541
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526029094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3526029094
Directory	/workspace/6.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/6.uart_smoke.384282063
Short name	T428
Test name
Test status
Simulation time	801123990 ps
CPU time	0.99 seconds
Started	May 30 12:50:23 PM PDT 24
Finished	May 30 12:50:25 PM PDT 24
Peak memory	198812 kb
Host	smart-eca0d253-3e1a-4ef0-a504-7eb96f73655b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384282063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.384282063
Directory	/workspace/6.uart_smoke/latest

Test location	/workspace/coverage/default/6.uart_stress_all.2616210945
Short name	T327
Test name
Test status
Simulation time	114409211484 ps
CPU time	340.12 seconds
Started	May 30 12:50:32 PM PDT 24
Finished	May 30 12:56:13 PM PDT 24
Peak memory	200368 kb
Host	smart-705b3014-b766-4752-993c-2a546e19513d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616210945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2616210945
Directory	/workspace/6.uart_stress_all/latest

Test location	/workspace/coverage/default/6.uart_stress_all_with_rand_reset.932435601
Short name	T584
Test name
Test status
Simulation time	22387854480 ps
CPU time	630.54 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 01:00:58 PM PDT 24
Peak memory	216760 kb
Host	smart-6c5216ee-83cc-4d16-a49e-d00a5243ab92
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932435601 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.932435601
Directory	/workspace/6.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.uart_tx_ovrd.107790702
Short name	T803
Test name
Test status
Simulation time	6081695649 ps
CPU time	20.62 seconds
Started	May 30 12:50:28 PM PDT 24
Finished	May 30 12:50:50 PM PDT 24
Peak memory	199688 kb
Host	smart-fee1f4c4-7108-4fb1-9eb5-cfa5e3a3fcdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107790702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.107790702
Directory	/workspace/6.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/6.uart_tx_rx.2403215436
Short name	T297
Test name
Test status
Simulation time	77609401980 ps
CPU time	135.75 seconds
Started	May 30 12:50:21 PM PDT 24
Finished	May 30 12:52:38 PM PDT 24
Peak memory	200292 kb
Host	smart-66d179a4-a252-4d2b-a505-293e09e3ddd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2403215436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2403215436
Directory	/workspace/6.uart_tx_rx/latest

Test location	/workspace/coverage/default/60.uart_fifo_reset.2071579966
Short name	T135
Test name
Test status
Simulation time	102699500101 ps
CPU time	39.62 seconds
Started	May 30 12:53:20 PM PDT 24
Finished	May 30 12:54:01 PM PDT 24
Peak memory	200212 kb
Host	smart-a8376dc3-aa50-4151-a4a3-bc2e27baad67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2071579966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2071579966
Directory	/workspace/60.uart_fifo_reset/latest

Test location	/workspace/coverage/default/60.uart_stress_all_with_rand_reset.2359748952
Short name	T34
Test name
Test status
Simulation time	35760843071 ps
CPU time	349.03 seconds
Started	May 30 12:53:23 PM PDT 24
Finished	May 30 12:59:14 PM PDT 24
Peak memory	215976 kb
Host	smart-31786a4b-6e0b-48c9-87b8-d6a6883cb8e3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359748952 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2359748952
Directory	/workspace/60.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/61.uart_fifo_reset.1643673207
Short name	T233
Test name
Test status
Simulation time	23037570618 ps
CPU time	56.8 seconds
Started	May 30 12:53:22 PM PDT 24
Finished	May 30 12:54:20 PM PDT 24
Peak memory	200316 kb
Host	smart-650d1138-8530-4590-806b-c92b751328c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1643673207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1643673207
Directory	/workspace/61.uart_fifo_reset/latest

Test location	/workspace/coverage/default/61.uart_stress_all_with_rand_reset.3101993687
Short name	T184
Test name
Test status
Simulation time	131147303036 ps
CPU time	1490.88 seconds
Started	May 30 12:53:22 PM PDT 24
Finished	May 30 01:18:13 PM PDT 24
Peak memory	229996 kb
Host	smart-ea09d42d-e14c-49b9-b1c1-0da8c6402800
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101993687 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3101993687
Directory	/workspace/61.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/62.uart_fifo_reset.1506417942
Short name	T348
Test name
Test status
Simulation time	45009575120 ps
CPU time	27.67 seconds
Started	May 30 12:53:21 PM PDT 24
Finished	May 30 12:53:50 PM PDT 24
Peak memory	200400 kb
Host	smart-e79c332f-cf14-4b80-967f-abdd14c08853
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1506417942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1506417942
Directory	/workspace/62.uart_fifo_reset/latest

Test location	/workspace/coverage/default/62.uart_stress_all_with_rand_reset.3088883887
Short name	T725
Test name
Test status
Simulation time	95738568140 ps
CPU time	318.83 seconds
Started	May 30 12:53:24 PM PDT 24
Finished	May 30 12:58:44 PM PDT 24
Peak memory	208872 kb
Host	smart-b675c316-2ea8-4c77-b763-90577f4886ef
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088883887 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3088883887
Directory	/workspace/62.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/63.uart_fifo_reset.2515472002
Short name	T1058
Test name
Test status
Simulation time	10835935112 ps
CPU time	16.37 seconds
Started	May 30 12:53:23 PM PDT 24
Finished	May 30 12:53:40 PM PDT 24
Peak memory	200308 kb
Host	smart-4b6615ec-383f-4da6-b914-f84ae8fef1d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2515472002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2515472002
Directory	/workspace/63.uart_fifo_reset/latest

Test location	/workspace/coverage/default/63.uart_stress_all_with_rand_reset.1585140021
Short name	T902
Test name
Test status
Simulation time	59274541539 ps
CPU time	111.6 seconds
Started	May 30 12:53:23 PM PDT 24
Finished	May 30 12:55:15 PM PDT 24
Peak memory	217076 kb
Host	smart-ec032992-f0ed-4f04-9f23-fa8df059aafc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585140021 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1585140021
Directory	/workspace/63.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/64.uart_fifo_reset.3066457947
Short name	T430
Test name
Test status
Simulation time	44556020092 ps
CPU time	77.46 seconds
Started	May 30 12:53:23 PM PDT 24
Finished	May 30 12:54:42 PM PDT 24
Peak memory	200212 kb
Host	smart-87d88395-637a-47dd-9645-3289fb67bc5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066457947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3066457947
Directory	/workspace/64.uart_fifo_reset/latest

Test location	/workspace/coverage/default/64.uart_stress_all_with_rand_reset.1759736588
Short name	T78
Test name
Test status
Simulation time	273087166682 ps
CPU time	914.45 seconds
Started	May 30 12:53:22 PM PDT 24
Finished	May 30 01:08:38 PM PDT 24
Peak memory	226768 kb
Host	smart-8db82ef0-08cf-4880-baf1-49c63a67bc91
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759736588 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1759736588
Directory	/workspace/64.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/65.uart_fifo_reset.3493223596
Short name	T481
Test name
Test status
Simulation time	29247106806 ps
CPU time	52.58 seconds
Started	May 30 12:53:22 PM PDT 24
Finished	May 30 12:54:15 PM PDT 24
Peak memory	200352 kb
Host	smart-6f4dfdbd-ec98-4010-968c-1914cc0cb3fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493223596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3493223596
Directory	/workspace/65.uart_fifo_reset/latest

Test location	/workspace/coverage/default/65.uart_stress_all_with_rand_reset.4086596067
Short name	T980
Test name
Test status
Simulation time	55349899701 ps
CPU time	151.09 seconds
Started	May 30 12:53:23 PM PDT 24
Finished	May 30 12:55:55 PM PDT 24
Peak memory	208596 kb
Host	smart-64ce4006-147e-427f-b49c-be7ac760ae94
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086596067 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.4086596067
Directory	/workspace/65.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/66.uart_fifo_reset.3843280265
Short name	T20
Test name
Test status
Simulation time	13166721983 ps
CPU time	29.06 seconds
Started	May 30 12:53:24 PM PDT 24
Finished	May 30 12:53:54 PM PDT 24
Peak memory	200380 kb
Host	smart-cd6c3c80-acad-45db-88e2-3689030c3ecb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843280265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3843280265
Directory	/workspace/66.uart_fifo_reset/latest

Test location	/workspace/coverage/default/66.uart_stress_all_with_rand_reset.4196514873
Short name	T1132
Test name
Test status
Simulation time	99950503163 ps
CPU time	276.63 seconds
Started	May 30 12:53:24 PM PDT 24
Finished	May 30 12:58:02 PM PDT 24
Peak memory	216556 kb
Host	smart-4d7a8762-66d5-4915-ab21-473b3e264a71
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196514873 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.4196514873
Directory	/workspace/66.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/67.uart_fifo_reset.3466822760
Short name	T565
Test name
Test status
Simulation time	38137067756 ps
CPU time	25.52 seconds
Started	May 30 12:53:24 PM PDT 24
Finished	May 30 12:53:50 PM PDT 24
Peak memory	200380 kb
Host	smart-34694edc-beb9-4697-bba6-f68805e59b89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466822760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3466822760
Directory	/workspace/67.uart_fifo_reset/latest

Test location	/workspace/coverage/default/67.uart_stress_all_with_rand_reset.1311552156
Short name	T1095
Test name
Test status
Simulation time	692328855725 ps
CPU time	858.93 seconds
Started	May 30 12:53:21 PM PDT 24
Finished	May 30 01:07:41 PM PDT 24
Peak memory	225128 kb
Host	smart-fc7a6150-aadc-44e3-81f4-fd8bfd2129b0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311552156 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1311552156
Directory	/workspace/67.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/68.uart_fifo_reset.2094696974
Short name	T912
Test name
Test status
Simulation time	118355794876 ps
CPU time	226.16 seconds
Started	May 30 12:53:24 PM PDT 24
Finished	May 30 12:57:11 PM PDT 24
Peak memory	200380 kb
Host	smart-1f7cb4d4-b47d-4cf0-a49b-6e7b0b0d0a8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2094696974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2094696974
Directory	/workspace/68.uart_fifo_reset/latest

Test location	/workspace/coverage/default/69.uart_fifo_reset.4077813721
Short name	T204
Test name
Test status
Simulation time	41524567087 ps
CPU time	72.67 seconds
Started	May 30 12:53:22 PM PDT 24
Finished	May 30 12:54:36 PM PDT 24
Peak memory	200460 kb
Host	smart-b3d3e2cf-1579-471a-8a86-dde267ec46f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4077813721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.4077813721
Directory	/workspace/69.uart_fifo_reset/latest

Test location	/workspace/coverage/default/69.uart_stress_all_with_rand_reset.810698056
Short name	T516
Test name
Test status
Simulation time	32983538946 ps
CPU time	600.28 seconds
Started	May 30 12:53:22 PM PDT 24
Finished	May 30 01:03:24 PM PDT 24
Peak memory	208772 kb
Host	smart-4d303f0d-e3ca-47cb-b697-ef25d124f491
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810698056 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.810698056
Directory	/workspace/69.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.uart_alert_test.1473845126
Short name	T698
Test name
Test status
Simulation time	15141178 ps
CPU time	0.61 seconds
Started	May 30 12:50:23 PM PDT 24
Finished	May 30 12:50:25 PM PDT 24
Peak memory	195744 kb
Host	smart-ce99f4bf-4f64-4745-b2c9-39f414e41d89
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473845126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1473845126
Directory	/workspace/7.uart_alert_test/latest

Test location	/workspace/coverage/default/7.uart_fifo_full.3070608850
Short name	T608
Test name
Test status
Simulation time	37719135826 ps
CPU time	57.01 seconds
Started	May 30 12:50:23 PM PDT 24
Finished	May 30 12:51:21 PM PDT 24
Peak memory	200372 kb
Host	smart-c431dd33-f346-474a-9784-29fd29a10c60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3070608850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3070608850
Directory	/workspace/7.uart_fifo_full/latest

Test location	/workspace/coverage/default/7.uart_fifo_overflow.4089655405
Short name	T140
Test name
Test status
Simulation time	62889848171 ps
CPU time	19.8 seconds
Started	May 30 12:50:18 PM PDT 24
Finished	May 30 12:50:38 PM PDT 24
Peak memory	200180 kb
Host	smart-47d16c62-8f77-44d0-8e9c-a8df707113a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4089655405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.4089655405
Directory	/workspace/7.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/7.uart_fifo_reset.2773017179
Short name	T346
Test name
Test status
Simulation time	73701862042 ps
CPU time	153.18 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 12:53:00 PM PDT 24
Peak memory	200348 kb
Host	smart-e65af40a-08c3-4c73-a27c-1bab65e6fd0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2773017179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2773017179
Directory	/workspace/7.uart_fifo_reset/latest

Test location	/workspace/coverage/default/7.uart_intr.410735631
Short name	T691
Test name
Test status
Simulation time	200411560019 ps
CPU time	95.98 seconds
Started	May 30 12:50:20 PM PDT 24
Finished	May 30 12:51:57 PM PDT 24
Peak memory	200368 kb
Host	smart-187c3cb6-bce3-4e5b-94c5-c9f9ba0434da
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410735631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.410735631
Directory	/workspace/7.uart_intr/latest

Test location	/workspace/coverage/default/7.uart_long_xfer_wo_dly.407562856
Short name	T541
Test name
Test status
Simulation time	95743615454 ps
CPU time	116.07 seconds
Started	May 30 12:50:23 PM PDT 24
Finished	May 30 12:52:20 PM PDT 24
Peak memory	200272 kb
Host	smart-cf162b64-0f5e-4879-84de-00fc35b83d42
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=407562856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.407562856
Directory	/workspace/7.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/7.uart_loopback.2209728263
Short name	T460
Test name
Test status
Simulation time	3905042495 ps
CPU time	3.82 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 12:50:31 PM PDT 24
Peak memory	200332 kb
Host	smart-59c918ec-a538-4da0-973e-9b7a10c66a25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2209728263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2209728263
Directory	/workspace/7.uart_loopback/latest

Test location	/workspace/coverage/default/7.uart_noise_filter.3705822875
Short name	T434
Test name
Test status
Simulation time	114666457455 ps
CPU time	19.13 seconds
Started	May 30 12:50:23 PM PDT 24
Finished	May 30 12:50:43 PM PDT 24
Peak memory	198780 kb
Host	smart-09938280-f457-4bc6-b9f8-564e5d1af8b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705822875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3705822875
Directory	/workspace/7.uart_noise_filter/latest

Test location	/workspace/coverage/default/7.uart_perf.3987017941
Short name	T960
Test name
Test status
Simulation time	9269727553 ps
CPU time	528.15 seconds
Started	May 30 12:50:29 PM PDT 24
Finished	May 30 12:59:18 PM PDT 24
Peak memory	200364 kb
Host	smart-acf22932-db58-4695-a34a-525014a1af0e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3987017941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3987017941
Directory	/workspace/7.uart_perf/latest

Test location	/workspace/coverage/default/7.uart_rx_oversample.720986842
Short name	T675
Test name
Test status
Simulation time	6522553033 ps
CPU time	52.62 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 12:51:20 PM PDT 24
Peak memory	198072 kb
Host	smart-b5d88ff6-40c6-435d-b02e-68333576127a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=720986842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.720986842
Directory	/workspace/7.uart_rx_oversample/latest

Test location	/workspace/coverage/default/7.uart_rx_parity_err.3057769514
Short name	T567
Test name
Test status
Simulation time	254971640940 ps
CPU time	98.46 seconds
Started	May 30 12:50:22 PM PDT 24
Finished	May 30 12:52:01 PM PDT 24
Peak memory	200384 kb
Host	smart-8dc8b6cd-8a52-425a-bf44-0767fc5f45d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057769514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3057769514
Directory	/workspace/7.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/7.uart_rx_start_bit_filter.294588716
Short name	T1009
Test name
Test status
Simulation time	3217087195 ps
CPU time	5.98 seconds
Started	May 30 12:50:23 PM PDT 24
Finished	May 30 12:50:30 PM PDT 24
Peak memory	196640 kb
Host	smart-2720bcdc-6240-4775-b28a-10c3ba9148fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294588716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.294588716
Directory	/workspace/7.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/7.uart_smoke.1380501000
Short name	T302
Test name
Test status
Simulation time	139732650 ps
CPU time	0.77 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 12:50:27 PM PDT 24
Peak memory	197424 kb
Host	smart-a5c4de34-86c8-4f24-863b-addaef5bd0ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1380501000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1380501000
Directory	/workspace/7.uart_smoke/latest

Test location	/workspace/coverage/default/7.uart_stress_all.1204517333
Short name	T319
Test name
Test status
Simulation time	299721977741 ps
CPU time	54.08 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 12:51:21 PM PDT 24
Peak memory	216740 kb
Host	smart-76c241c6-f551-47fd-a437-29a3ba8a9e32
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204517333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1204517333
Directory	/workspace/7.uart_stress_all/latest

Test location	/workspace/coverage/default/7.uart_stress_all_with_rand_reset.1537799142
Short name	T740
Test name
Test status
Simulation time	134781703330 ps
CPU time	655.61 seconds
Started	May 30 12:50:25 PM PDT 24
Finished	May 30 01:01:21 PM PDT 24
Peak memory	217000 kb
Host	smart-51b308f9-ce68-4ef7-847f-13a26a70c185
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537799142 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1537799142
Directory	/workspace/7.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.uart_tx_ovrd.3265914578
Short name	T616
Test name
Test status
Simulation time	6945863171 ps
CPU time	10.38 seconds
Started	May 30 12:50:25 PM PDT 24
Finished	May 30 12:50:37 PM PDT 24
Peak memory	200132 kb
Host	smart-c78ea245-9f06-4613-90fc-629779c8e7c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3265914578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3265914578
Directory	/workspace/7.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/7.uart_tx_rx.3747833185
Short name	T926
Test name
Test status
Simulation time	38182252334 ps
CPU time	36.5 seconds
Started	May 30 12:50:21 PM PDT 24
Finished	May 30 12:50:59 PM PDT 24
Peak memory	200304 kb
Host	smart-0498289e-d9ff-4c34-85a7-d79c901edffd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747833185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3747833185
Directory	/workspace/7.uart_tx_rx/latest

Test location	/workspace/coverage/default/70.uart_fifo_reset.1633092047
Short name	T1048
Test name
Test status
Simulation time	61064176169 ps
CPU time	46.3 seconds
Started	May 30 12:53:21 PM PDT 24
Finished	May 30 12:54:09 PM PDT 24
Peak memory	200172 kb
Host	smart-657ebdde-8d29-428e-bc6b-2ca87bc809d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633092047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1633092047
Directory	/workspace/70.uart_fifo_reset/latest

Test location	/workspace/coverage/default/70.uart_stress_all_with_rand_reset.3878311951
Short name	T219
Test name
Test status
Simulation time	310206561567 ps
CPU time	542.83 seconds
Started	May 30 12:53:24 PM PDT 24
Finished	May 30 01:02:28 PM PDT 24
Peak memory	216700 kb
Host	smart-d2c42257-eabb-4f8a-980e-045701e471f4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878311951 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3878311951
Directory	/workspace/70.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/71.uart_fifo_reset.2374593804
Short name	T407
Test name
Test status
Simulation time	123204106467 ps
CPU time	51.62 seconds
Started	May 30 12:53:21 PM PDT 24
Finished	May 30 12:54:14 PM PDT 24
Peak memory	200104 kb
Host	smart-63586379-cfa4-4249-9fff-f14069f4af4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374593804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2374593804
Directory	/workspace/71.uart_fifo_reset/latest

Test location	/workspace/coverage/default/71.uart_stress_all_with_rand_reset.462850807
Short name	T570
Test name
Test status
Simulation time	14891763391 ps
CPU time	88.27 seconds
Started	May 30 12:53:24 PM PDT 24
Finished	May 30 12:54:54 PM PDT 24
Peak memory	216656 kb
Host	smart-9d9d159a-45e3-47b0-92a2-c59a097a66fd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462850807 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.462850807
Directory	/workspace/71.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/72.uart_fifo_reset.4108657710
Short name	T314
Test name
Test status
Simulation time	185969484563 ps
CPU time	197.13 seconds
Started	May 30 12:53:22 PM PDT 24
Finished	May 30 12:56:40 PM PDT 24
Peak memory	200324 kb
Host	smart-52f33b19-2aaa-4a38-8598-2acc2c8bde1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4108657710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.4108657710
Directory	/workspace/72.uart_fifo_reset/latest

Test location	/workspace/coverage/default/72.uart_stress_all_with_rand_reset.2847080422
Short name	T63
Test name
Test status
Simulation time	180531837565 ps
CPU time	756.95 seconds
Started	May 30 12:53:21 PM PDT 24
Finished	May 30 01:05:59 PM PDT 24
Peak memory	216720 kb
Host	smart-337101a6-9b88-4682-9045-b9d9d7b66faf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847080422 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2847080422
Directory	/workspace/72.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/73.uart_fifo_reset.1259613172
Short name	T14
Test name
Test status
Simulation time	46255538783 ps
CPU time	21.82 seconds
Started	May 30 12:53:21 PM PDT 24
Finished	May 30 12:53:43 PM PDT 24
Peak memory	200312 kb
Host	smart-49e35597-d1d3-4420-92e1-7470c08a97a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1259613172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1259613172
Directory	/workspace/73.uart_fifo_reset/latest

Test location	/workspace/coverage/default/73.uart_stress_all_with_rand_reset.2250282191
Short name	T76
Test name
Test status
Simulation time	175419048290 ps
CPU time	2653.08 seconds
Started	May 30 12:53:23 PM PDT 24
Finished	May 30 01:37:38 PM PDT 24
Peak memory	233456 kb
Host	smart-96626c4c-96b5-4db2-ab88-1667bbaa328e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250282191 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2250282191
Directory	/workspace/73.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/74.uart_fifo_reset.2014652257
Short name	T1050
Test name
Test status
Simulation time	362832123555 ps
CPU time	34.33 seconds
Started	May 30 12:53:35 PM PDT 24
Finished	May 30 12:54:11 PM PDT 24
Peak memory	200288 kb
Host	smart-bc88e2ea-e020-441c-ba60-5d244cc5f4c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014652257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2014652257
Directory	/workspace/74.uart_fifo_reset/latest

Test location	/workspace/coverage/default/74.uart_stress_all_with_rand_reset.2688448876
Short name	T1077
Test name
Test status
Simulation time	83422503935 ps
CPU time	259.51 seconds
Started	May 30 12:53:34 PM PDT 24
Finished	May 30 12:57:54 PM PDT 24
Peak memory	216652 kb
Host	smart-a50a5c59-60d8-404b-b054-4af8e04d9875
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688448876 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2688448876
Directory	/workspace/74.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/75.uart_fifo_reset.3769626664
Short name	T667
Test name
Test status
Simulation time	21513509034 ps
CPU time	44.86 seconds
Started	May 30 12:53:33 PM PDT 24
Finished	May 30 12:54:19 PM PDT 24
Peak memory	200364 kb
Host	smart-942b1941-fd37-4195-b0a9-1669f1d4b21d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3769626664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3769626664
Directory	/workspace/75.uart_fifo_reset/latest

Test location	/workspace/coverage/default/76.uart_fifo_reset.866697359
Short name	T366
Test name
Test status
Simulation time	35404789342 ps
CPU time	15.8 seconds
Started	May 30 12:53:36 PM PDT 24
Finished	May 30 12:53:53 PM PDT 24
Peak memory	200404 kb
Host	smart-0d06d2ab-902b-4b53-bda5-af9adb75c3f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866697359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.866697359
Directory	/workspace/76.uart_fifo_reset/latest

Test location	/workspace/coverage/default/77.uart_fifo_reset.723797455
Short name	T949
Test name
Test status
Simulation time	12282462687 ps
CPU time	24.12 seconds
Started	May 30 12:53:35 PM PDT 24
Finished	May 30 12:54:00 PM PDT 24
Peak memory	200400 kb
Host	smart-d3176ba5-f5b9-4e02-ab73-001686c95c60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=723797455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.723797455
Directory	/workspace/77.uart_fifo_reset/latest

Test location	/workspace/coverage/default/78.uart_fifo_reset.875907448
Short name	T922
Test name
Test status
Simulation time	45280158092 ps
CPU time	80.9 seconds
Started	May 30 12:53:36 PM PDT 24
Finished	May 30 12:54:58 PM PDT 24
Peak memory	200340 kb
Host	smart-33a3788a-b1eb-45ab-93c6-4a210076e858
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=875907448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.875907448
Directory	/workspace/78.uart_fifo_reset/latest

Test location	/workspace/coverage/default/78.uart_stress_all_with_rand_reset.73983948
Short name	T67
Test name
Test status
Simulation time	133274186474 ps
CPU time	1476.77 seconds
Started	May 30 12:53:36 PM PDT 24
Finished	May 30 01:18:14 PM PDT 24
Peak memory	216968 kb
Host	smart-b5ed162d-c5e1-4117-828b-2ded26941d37
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73983948 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.73983948
Directory	/workspace/78.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/79.uart_fifo_reset.1905790388
Short name	T552
Test name
Test status
Simulation time	114330662078 ps
CPU time	87.48 seconds
Started	May 30 12:53:36 PM PDT 24
Finished	May 30 12:55:05 PM PDT 24
Peak memory	200376 kb
Host	smart-3fe829e7-69ef-495e-9ff4-c75f760258da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1905790388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1905790388
Directory	/workspace/79.uart_fifo_reset/latest

Test location	/workspace/coverage/default/79.uart_stress_all_with_rand_reset.2189520005
Short name	T790
Test name
Test status
Simulation time	54640616261 ps
CPU time	1028.27 seconds
Started	May 30 12:53:35 PM PDT 24
Finished	May 30 01:10:45 PM PDT 24
Peak memory	216972 kb
Host	smart-e79cd279-449a-4455-88dd-9d53ddca92d7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189520005 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2189520005
Directory	/workspace/79.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.uart_alert_test.154360093
Short name	T611
Test name
Test status
Simulation time	12913591 ps
CPU time	0.57 seconds
Started	May 30 12:50:24 PM PDT 24
Finished	May 30 12:50:26 PM PDT 24
Peak memory	195728 kb
Host	smart-bd43017e-3280-4aad-98fa-e22a8e56319e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154360093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.154360093
Directory	/workspace/8.uart_alert_test/latest

Test location	/workspace/coverage/default/8.uart_fifo_full.397701787
Short name	T1035
Test name
Test status
Simulation time	25548296806 ps
CPU time	23.14 seconds
Started	May 30 12:50:22 PM PDT 24
Finished	May 30 12:50:46 PM PDT 24
Peak memory	199992 kb
Host	smart-37c7e713-ee0a-495f-b1c1-74dd114970a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=397701787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.397701787
Directory	/workspace/8.uart_fifo_full/latest

Test location	/workspace/coverage/default/8.uart_fifo_overflow.3313231102
Short name	T290
Test name
Test status
Simulation time	10924145562 ps
CPU time	16.82 seconds
Started	May 30 12:50:23 PM PDT 24
Finished	May 30 12:50:40 PM PDT 24
Peak memory	200324 kb
Host	smart-7065bf9c-f8ec-4ad6-88a3-7e8d87d950ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3313231102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3313231102
Directory	/workspace/8.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/8.uart_fifo_reset.1955795619
Short name	T517
Test name
Test status
Simulation time	48754171788 ps
CPU time	81.07 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 12:51:48 PM PDT 24
Peak memory	200284 kb
Host	smart-576b958d-8a93-41b0-be7f-4e88b62416a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1955795619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1955795619
Directory	/workspace/8.uart_fifo_reset/latest

Test location	/workspace/coverage/default/8.uart_intr.2144020340
Short name	T537
Test name
Test status
Simulation time	19641207809 ps
CPU time	41.76 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 12:51:09 PM PDT 24
Peak memory	200072 kb
Host	smart-8622970a-708e-4b88-92ae-b8150660e25a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144020340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2144020340
Directory	/workspace/8.uart_intr/latest

Test location	/workspace/coverage/default/8.uart_loopback.3658089521
Short name	T1151
Test name
Test status
Simulation time	6405940959 ps
CPU time	5.67 seconds
Started	May 30 12:50:29 PM PDT 24
Finished	May 30 12:50:35 PM PDT 24
Peak memory	199644 kb
Host	smart-47879ee7-9c1e-43a8-aeb0-97fdb0d7c959
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3658089521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3658089521
Directory	/workspace/8.uart_loopback/latest

Test location	/workspace/coverage/default/8.uart_noise_filter.3752078262
Short name	T440
Test name
Test status
Simulation time	47998836260 ps
CPU time	71.7 seconds
Started	May 30 12:50:23 PM PDT 24
Finished	May 30 12:51:36 PM PDT 24
Peak memory	200180 kb
Host	smart-c0ece40d-b193-473a-8cfc-f8a6042fadae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3752078262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3752078262
Directory	/workspace/8.uart_noise_filter/latest

Test location	/workspace/coverage/default/8.uart_perf.2963553533
Short name	T256
Test name
Test status
Simulation time	13157090028 ps
CPU time	411.81 seconds
Started	May 30 12:50:23 PM PDT 24
Finished	May 30 12:57:16 PM PDT 24
Peak memory	200320 kb
Host	smart-06083664-baca-4fef-8260-1751c9f36285
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2963553533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2963553533
Directory	/workspace/8.uart_perf/latest

Test location	/workspace/coverage/default/8.uart_rx_oversample.570819311
Short name	T777
Test name
Test status
Simulation time	3352419261 ps
CPU time	7.07 seconds
Started	May 30 12:50:29 PM PDT 24
Finished	May 30 12:50:36 PM PDT 24
Peak memory	199484 kb
Host	smart-4d840cda-673d-4f80-bed4-9b56c3347dfe
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=570819311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.570819311
Directory	/workspace/8.uart_rx_oversample/latest

Test location	/workspace/coverage/default/8.uart_rx_parity_err.1511032164
Short name	T965
Test name
Test status
Simulation time	398659322859 ps
CPU time	31.78 seconds
Started	May 30 12:50:25 PM PDT 24
Finished	May 30 12:50:58 PM PDT 24
Peak memory	200296 kb
Host	smart-9cf20196-58e2-4bac-a1c7-b0e352bc3bd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1511032164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1511032164
Directory	/workspace/8.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/8.uart_rx_start_bit_filter.4187391163
Short name	T23
Test name
Test status
Simulation time	43439508591 ps
CPU time	3.93 seconds
Started	May 30 12:50:24 PM PDT 24
Finished	May 30 12:50:28 PM PDT 24
Peak memory	196360 kb
Host	smart-b5bf902d-c176-4326-b41b-60c617b6907f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187391163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.4187391163
Directory	/workspace/8.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/8.uart_smoke.2580604085
Short name	T945
Test name
Test status
Simulation time	5866987118 ps
CPU time	37.4 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 12:51:04 PM PDT 24
Peak memory	200176 kb
Host	smart-f5dd743a-54bf-4e82-88da-3835b0470ae1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2580604085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2580604085
Directory	/workspace/8.uart_smoke/latest

Test location	/workspace/coverage/default/8.uart_stress_all.4141050164
Short name	T1007
Test name
Test status
Simulation time	306450304995 ps
CPU time	569.69 seconds
Started	May 30 12:50:29 PM PDT 24
Finished	May 30 12:59:59 PM PDT 24
Peak memory	200264 kb
Host	smart-bdada53c-6576-4f9a-a327-ab8b339d6ca3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141050164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.4141050164
Directory	/workspace/8.uart_stress_all/latest

Test location	/workspace/coverage/default/8.uart_stress_all_with_rand_reset.1169676456
Short name	T35
Test name
Test status
Simulation time	43547644151 ps
CPU time	488.76 seconds
Started	May 30 12:50:28 PM PDT 24
Finished	May 30 12:58:38 PM PDT 24
Peak memory	216748 kb
Host	smart-c714cc41-a5e9-4819-a4f0-e1cec4d2c291
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169676456 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1169676456
Directory	/workspace/8.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.uart_tx_ovrd.2056626860
Short name	T1162
Test name
Test status
Simulation time	2709206983 ps
CPU time	2.16 seconds
Started	May 30 12:50:26 PM PDT 24
Finished	May 30 12:50:29 PM PDT 24
Peak memory	199288 kb
Host	smart-67f188e5-c1f2-4ede-b168-4a54d414aa81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056626860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2056626860
Directory	/workspace/8.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/8.uart_tx_rx.1150611529
Short name	T274
Test name
Test status
Simulation time	49188242306 ps
CPU time	18.51 seconds
Started	May 30 12:50:24 PM PDT 24
Finished	May 30 12:50:44 PM PDT 24
Peak memory	199980 kb
Host	smart-f345dd77-94a2-4148-bfc8-42706ed8693d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150611529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1150611529
Directory	/workspace/8.uart_tx_rx/latest

Test location	/workspace/coverage/default/80.uart_fifo_reset.104306387
Short name	T505
Test name
Test status
Simulation time	78912697051 ps
CPU time	642.26 seconds
Started	May 30 12:53:35 PM PDT 24
Finished	May 30 01:04:18 PM PDT 24
Peak memory	200412 kb
Host	smart-74ff3a2c-eca6-4b71-b25b-6c94279a9292
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104306387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.104306387
Directory	/workspace/80.uart_fifo_reset/latest

Test location	/workspace/coverage/default/80.uart_stress_all_with_rand_reset.642997357
Short name	T726
Test name
Test status
Simulation time	276475191152 ps
CPU time	203.61 seconds
Started	May 30 12:53:35 PM PDT 24
Finished	May 30 12:57:00 PM PDT 24
Peak memory	214612 kb
Host	smart-1a751418-4f7d-401f-82e2-617d185e0fff
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642997357 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.642997357
Directory	/workspace/80.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/81.uart_fifo_reset.903361834
Short name	T1097
Test name
Test status
Simulation time	399027324065 ps
CPU time	37.98 seconds
Started	May 30 12:53:33 PM PDT 24
Finished	May 30 12:54:12 PM PDT 24
Peak memory	200372 kb
Host	smart-14a44351-8da3-437b-8eda-871f284908b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=903361834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.903361834
Directory	/workspace/81.uart_fifo_reset/latest

Test location	/workspace/coverage/default/81.uart_stress_all_with_rand_reset.926513636
Short name	T628
Test name
Test status
Simulation time	79127699939 ps
CPU time	877.92 seconds
Started	May 30 12:53:35 PM PDT 24
Finished	May 30 01:08:14 PM PDT 24
Peak memory	216876 kb
Host	smart-82532ae5-a2fd-4946-bbc2-8f4380f6397a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926513636 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.926513636
Directory	/workspace/81.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/82.uart_fifo_reset.3153767606
Short name	T544
Test name
Test status
Simulation time	153702193798 ps
CPU time	78.59 seconds
Started	May 30 12:53:36 PM PDT 24
Finished	May 30 12:54:56 PM PDT 24
Peak memory	200296 kb
Host	smart-ffac6b75-d97a-41da-b8b1-0737ce12e88c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153767606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3153767606
Directory	/workspace/82.uart_fifo_reset/latest

Test location	/workspace/coverage/default/82.uart_stress_all_with_rand_reset.4134564033
Short name	T985
Test name
Test status
Simulation time	89481426147 ps
CPU time	588.08 seconds
Started	May 30 12:53:35 PM PDT 24
Finished	May 30 01:03:24 PM PDT 24
Peak memory	225220 kb
Host	smart-fa43be79-3bc8-4149-891b-54ec85c2cd51
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134564033 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.4134564033
Directory	/workspace/82.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/83.uart_fifo_reset.3997439477
Short name	T1006
Test name
Test status
Simulation time	146750413914 ps
CPU time	229.22 seconds
Started	May 30 12:53:34 PM PDT 24
Finished	May 30 12:57:24 PM PDT 24
Peak memory	200312 kb
Host	smart-325cef00-7589-4abb-b200-32da32756910
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3997439477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3997439477
Directory	/workspace/83.uart_fifo_reset/latest

Test location	/workspace/coverage/default/83.uart_stress_all_with_rand_reset.681899164
Short name	T31
Test name
Test status
Simulation time	94210974471 ps
CPU time	228.98 seconds
Started	May 30 12:53:35 PM PDT 24
Finished	May 30 12:57:25 PM PDT 24
Peak memory	217036 kb
Host	smart-ac130fde-898d-4ab2-a21b-d863f129a059
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681899164 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.681899164
Directory	/workspace/83.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/84.uart_fifo_reset.1283034881
Short name	T930
Test name
Test status
Simulation time	223626498262 ps
CPU time	96.95 seconds
Started	May 30 12:53:34 PM PDT 24
Finished	May 30 12:55:12 PM PDT 24
Peak memory	200384 kb
Host	smart-18b7bcb5-9555-45f3-acab-1be37d90701b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283034881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1283034881
Directory	/workspace/84.uart_fifo_reset/latest

Test location	/workspace/coverage/default/84.uart_stress_all_with_rand_reset.458619551
Short name	T571
Test name
Test status
Simulation time	67956145995 ps
CPU time	289.16 seconds
Started	May 30 12:53:34 PM PDT 24
Finished	May 30 12:58:24 PM PDT 24
Peak memory	216832 kb
Host	smart-a3c50b2e-6f17-432e-aec1-a548d7792c95
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458619551 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.458619551
Directory	/workspace/84.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/85.uart_fifo_reset.2564084682
Short name	T683
Test name
Test status
Simulation time	29929657076 ps
CPU time	17.51 seconds
Started	May 30 12:53:35 PM PDT 24
Finished	May 30 12:53:54 PM PDT 24
Peak memory	200368 kb
Host	smart-37e7eb65-b3fa-48db-aeff-cb8f07a620f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2564084682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2564084682
Directory	/workspace/85.uart_fifo_reset/latest

Test location	/workspace/coverage/default/85.uart_stress_all_with_rand_reset.3168465773
Short name	T1062
Test name
Test status
Simulation time	22720637568 ps
CPU time	245.58 seconds
Started	May 30 12:53:34 PM PDT 24
Finished	May 30 12:57:40 PM PDT 24
Peak memory	213000 kb
Host	smart-256bad3c-aa70-41ca-bc62-11975ce39b2e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168465773 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3168465773
Directory	/workspace/85.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/86.uart_fifo_reset.391303785
Short name	T666
Test name
Test status
Simulation time	39510521460 ps
CPU time	18.23 seconds
Started	May 30 12:53:34 PM PDT 24
Finished	May 30 12:53:54 PM PDT 24
Peak memory	200324 kb
Host	smart-418079bd-69a0-4a87-a8c1-5c1406260dca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391303785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.391303785
Directory	/workspace/86.uart_fifo_reset/latest

Test location	/workspace/coverage/default/86.uart_stress_all_with_rand_reset.830281854
Short name	T549
Test name
Test status
Simulation time	57213167032 ps
CPU time	1013.93 seconds
Started	May 30 12:53:35 PM PDT 24
Finished	May 30 01:10:31 PM PDT 24
Peak memory	225048 kb
Host	smart-6a2ccc55-4d71-4d86-8c05-fc8d5f6b8eb9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830281854 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.830281854
Directory	/workspace/86.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/87.uart_fifo_reset.4120655627
Short name	T205
Test name
Test status
Simulation time	76009409834 ps
CPU time	10.48 seconds
Started	May 30 12:53:37 PM PDT 24
Finished	May 30 12:53:48 PM PDT 24
Peak memory	200296 kb
Host	smart-1dc6b5a7-c8f7-40a7-b6c5-583c40c641e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4120655627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.4120655627
Directory	/workspace/87.uart_fifo_reset/latest

Test location	/workspace/coverage/default/87.uart_stress_all_with_rand_reset.992774657
Short name	T33
Test name
Test status
Simulation time	56408962866 ps
CPU time	171.87 seconds
Started	May 30 12:53:34 PM PDT 24
Finished	May 30 12:56:27 PM PDT 24
Peak memory	208636 kb
Host	smart-dd92e256-0d17-4c58-ae1a-35ed5e75050c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992774657 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.992774657
Directory	/workspace/87.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/88.uart_fifo_reset.1808531370
Short name	T170
Test name
Test status
Simulation time	15867012496 ps
CPU time	21.65 seconds
Started	May 30 12:53:37 PM PDT 24
Finished	May 30 12:53:59 PM PDT 24
Peak memory	200340 kb
Host	smart-3a6fdcba-c49b-4961-8044-1fd49ef12022
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1808531370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1808531370
Directory	/workspace/88.uart_fifo_reset/latest

Test location	/workspace/coverage/default/88.uart_stress_all_with_rand_reset.2632917416
Short name	T1157
Test name
Test status
Simulation time	356903049726 ps
CPU time	1047.95 seconds
Started	May 30 12:53:34 PM PDT 24
Finished	May 30 01:11:03 PM PDT 24
Peak memory	225144 kb
Host	smart-a39f871a-b018-408d-ac66-dac6a69c68ad
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632917416 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2632917416
Directory	/workspace/88.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/89.uart_fifo_reset.3983782446
Short name	T342
Test name
Test status
Simulation time	12123774000 ps
CPU time	22.07 seconds
Started	May 30 12:53:33 PM PDT 24
Finished	May 30 12:53:56 PM PDT 24
Peak memory	200296 kb
Host	smart-5ffbd21f-927a-4fe6-b41b-152ea8c8ac03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3983782446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3983782446
Directory	/workspace/89.uart_fifo_reset/latest

Test location	/workspace/coverage/default/89.uart_stress_all_with_rand_reset.677468273
Short name	T772
Test name
Test status
Simulation time	35192585839 ps
CPU time	420.51 seconds
Started	May 30 12:53:35 PM PDT 24
Finished	May 30 01:00:37 PM PDT 24
Peak memory	217048 kb
Host	smart-5711e13f-f446-4921-a56b-9d2460a839cd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677468273 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.677468273
Directory	/workspace/89.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.uart_alert_test.2946550294
Short name	T1148
Test name
Test status
Simulation time	40136092 ps
CPU time	0.58 seconds
Started	May 30 12:50:37 PM PDT 24
Finished	May 30 12:50:39 PM PDT 24
Peak memory	195660 kb
Host	smart-489f0863-1517-44fb-a553-c4d4223ae1e8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946550294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2946550294
Directory	/workspace/9.uart_alert_test/latest

Test location	/workspace/coverage/default/9.uart_fifo_full.1793022539
Short name	T374
Test name
Test status
Simulation time	103482620708 ps
CPU time	160.89 seconds
Started	May 30 12:50:34 PM PDT 24
Finished	May 30 12:53:16 PM PDT 24
Peak memory	200388 kb
Host	smart-8b7bb7f9-89b5-496d-817a-ac3b3715eed5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1793022539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1793022539
Directory	/workspace/9.uart_fifo_full/latest

Test location	/workspace/coverage/default/9.uart_fifo_overflow.3364738874
Short name	T443
Test name
Test status
Simulation time	15015433222 ps
CPU time	26.09 seconds
Started	May 30 12:50:33 PM PDT 24
Finished	May 30 12:51:00 PM PDT 24
Peak memory	200364 kb
Host	smart-1db4d582-062f-4eb0-95a8-2b318883a093
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3364738874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3364738874
Directory	/workspace/9.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/9.uart_intr.731637422
Short name	T1011
Test name
Test status
Simulation time	37049640088 ps
CPU time	53.64 seconds
Started	May 30 12:50:39 PM PDT 24
Finished	May 30 12:51:34 PM PDT 24
Peak memory	200320 kb
Host	smart-016748ed-2ec3-4b38-8a2d-fee262aff722
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731637422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.731637422
Directory	/workspace/9.uart_intr/latest

Test location	/workspace/coverage/default/9.uart_long_xfer_wo_dly.1814980773
Short name	T655
Test name
Test status
Simulation time	249733349482 ps
CPU time	1769.12 seconds
Started	May 30 12:50:30 PM PDT 24
Finished	May 30 01:20:00 PM PDT 24
Peak memory	200204 kb
Host	smart-7631f017-5b9c-4953-af24-d40a0464ba16
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1814980773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1814980773
Directory	/workspace/9.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/9.uart_loopback.939880729
Short name	T352
Test name
Test status
Simulation time	6762095667 ps
CPU time	10.2 seconds
Started	May 30 12:50:37 PM PDT 24
Finished	May 30 12:50:49 PM PDT 24
Peak memory	200032 kb
Host	smart-acde7023-4e50-43b7-a943-3b4f628df7ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=939880729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.939880729
Directory	/workspace/9.uart_loopback/latest

Test location	/workspace/coverage/default/9.uart_noise_filter.148229931
Short name	T817
Test name
Test status
Simulation time	8992549934 ps
CPU time	13.65 seconds
Started	May 30 12:50:33 PM PDT 24
Finished	May 30 12:50:48 PM PDT 24
Peak memory	197560 kb
Host	smart-5922034d-fe6b-44c9-b3a2-765008226842
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=148229931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.148229931
Directory	/workspace/9.uart_noise_filter/latest

Test location	/workspace/coverage/default/9.uart_perf.1327945205
Short name	T1160
Test name
Test status
Simulation time	9068669057 ps
CPU time	591.82 seconds
Started	May 30 12:50:33 PM PDT 24
Finished	May 30 01:00:26 PM PDT 24
Peak memory	200400 kb
Host	smart-21b2c3ed-227e-46b4-9b8f-14a5cf39619c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1327945205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1327945205
Directory	/workspace/9.uart_perf/latest

Test location	/workspace/coverage/default/9.uart_rx_oversample.576216056
Short name	T1079
Test name
Test status
Simulation time	2739457742 ps
CPU time	1.74 seconds
Started	May 30 12:50:34 PM PDT 24
Finished	May 30 12:50:37 PM PDT 24
Peak memory	198740 kb
Host	smart-59c0d369-9af7-4963-b3fd-a2727f62d280
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=576216056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.576216056
Directory	/workspace/9.uart_rx_oversample/latest

Test location	/workspace/coverage/default/9.uart_rx_parity_err.2840771956
Short name	T167
Test name
Test status
Simulation time	218162283884 ps
CPU time	35.98 seconds
Started	May 30 12:50:38 PM PDT 24
Finished	May 30 12:51:16 PM PDT 24
Peak memory	200288 kb
Host	smart-c20cef88-dfcb-47e9-8a1c-6d955989a313
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2840771956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2840771956
Directory	/workspace/9.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/9.uart_rx_start_bit_filter.3273054764
Short name	T843
Test name
Test status
Simulation time	3745633519 ps
CPU time	1.78 seconds
Started	May 30 12:50:30 PM PDT 24
Finished	May 30 12:50:33 PM PDT 24
Peak memory	196296 kb
Host	smart-752f971c-f42b-4ea7-8a46-511dabdf825a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3273054764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3273054764
Directory	/workspace/9.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/9.uart_smoke.1324641929
Short name	T809
Test name
Test status
Simulation time	6237553974 ps
CPU time	6.27 seconds
Started	May 30 12:50:40 PM PDT 24
Finished	May 30 12:50:47 PM PDT 24
Peak memory	200032 kb
Host	smart-2b0a46c7-aa7e-4da7-ab47-1db33a4199e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1324641929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1324641929
Directory	/workspace/9.uart_smoke/latest

Test location	/workspace/coverage/default/9.uart_stress_all.1954421114
Short name	T417
Test name
Test status
Simulation time	55766710583 ps
CPU time	36.54 seconds
Started	May 30 12:50:39 PM PDT 24
Finished	May 30 12:51:17 PM PDT 24
Peak memory	200408 kb
Host	smart-e86dcda1-eea2-4b94-a097-0ef79bbf10f8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954421114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1954421114
Directory	/workspace/9.uart_stress_all/latest

Test location	/workspace/coverage/default/9.uart_tx_ovrd.3789839675
Short name	T840
Test name
Test status
Simulation time	7141975230 ps
CPU time	26.12 seconds
Started	May 30 12:50:32 PM PDT 24
Finished	May 30 12:51:00 PM PDT 24
Peak memory	200308 kb
Host	smart-da4d368a-120c-4767-ac22-27492e5167f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3789839675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3789839675
Directory	/workspace/9.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/9.uart_tx_rx.960043953
Short name	T399
Test name
Test status
Simulation time	115646483760 ps
CPU time	116.65 seconds
Started	May 30 12:50:30 PM PDT 24
Finished	May 30 12:52:27 PM PDT 24
Peak memory	200304 kb
Host	smart-259ce80e-23fa-43dc-a7e1-334551c745fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=960043953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.960043953
Directory	/workspace/9.uart_tx_rx/latest

Test location	/workspace/coverage/default/90.uart_fifo_reset.149630536
Short name	T933
Test name
Test status
Simulation time	14185087505 ps
CPU time	30.48 seconds
Started	May 30 12:53:36 PM PDT 24
Finished	May 30 12:54:08 PM PDT 24
Peak memory	200416 kb
Host	smart-315c135b-f06e-4d4b-a98a-70727cd79cce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=149630536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.149630536
Directory	/workspace/90.uart_fifo_reset/latest

Test location	/workspace/coverage/default/90.uart_stress_all_with_rand_reset.2158326062
Short name	T1172
Test name
Test status
Simulation time	465779452193 ps
CPU time	1088.3 seconds
Started	May 30 12:53:36 PM PDT 24
Finished	May 30 01:11:45 PM PDT 24
Peak memory	227028 kb
Host	smart-6eec3720-2125-45ea-851f-8da843d92703
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158326062 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2158326062
Directory	/workspace/90.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/91.uart_fifo_reset.3994978053
Short name	T8
Test name
Test status
Simulation time	12186807304 ps
CPU time	13.64 seconds
Started	May 30 12:53:35 PM PDT 24
Finished	May 30 12:53:49 PM PDT 24
Peak memory	200116 kb
Host	smart-2118aef2-7ffa-48a6-9e1d-af69f35f663b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994978053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3994978053
Directory	/workspace/91.uart_fifo_reset/latest

Test location	/workspace/coverage/default/91.uart_stress_all_with_rand_reset.2929849751
Short name	T113
Test name
Test status
Simulation time	164860268616 ps
CPU time	194.61 seconds
Started	May 30 12:53:37 PM PDT 24
Finished	May 30 12:56:53 PM PDT 24
Peak memory	216592 kb
Host	smart-1cfcf68d-0089-4cff-9dd3-c95d148f630c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929849751 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2929849751
Directory	/workspace/91.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/92.uart_fifo_reset.1334047064
Short name	T658
Test name
Test status
Simulation time	10031598494 ps
CPU time	5.49 seconds
Started	May 30 12:53:37 PM PDT 24
Finished	May 30 12:53:43 PM PDT 24
Peak memory	200308 kb
Host	smart-a1e097fb-6401-411c-ba9a-053dac5775d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1334047064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1334047064
Directory	/workspace/92.uart_fifo_reset/latest

Test location	/workspace/coverage/default/92.uart_stress_all_with_rand_reset.123220751
Short name	T66
Test name
Test status
Simulation time	62957043391 ps
CPU time	340.01 seconds
Started	May 30 12:53:36 PM PDT 24
Finished	May 30 12:59:17 PM PDT 24
Peak memory	209288 kb
Host	smart-d01a1ce8-e1a8-4d88-b6b4-c309d745e87a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123220751 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.123220751
Directory	/workspace/92.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/93.uart_fifo_reset.2301530500
Short name	T800
Test name
Test status
Simulation time	41807282843 ps
CPU time	9.37 seconds
Started	May 30 12:53:38 PM PDT 24
Finished	May 30 12:53:49 PM PDT 24
Peak memory	200264 kb
Host	smart-d423ecd2-c839-475e-ab32-2af205192c24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2301530500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2301530500
Directory	/workspace/93.uart_fifo_reset/latest

Test location	/workspace/coverage/default/94.uart_fifo_reset.1188261432
Short name	T869
Test name
Test status
Simulation time	165198321692 ps
CPU time	52.34 seconds
Started	May 30 12:53:34 PM PDT 24
Finished	May 30 12:54:28 PM PDT 24
Peak memory	200240 kb
Host	smart-05c2a227-966a-4a36-9172-15ae8ce1da55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188261432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1188261432
Directory	/workspace/94.uart_fifo_reset/latest

Test location	/workspace/coverage/default/95.uart_fifo_reset.4223951050
Short name	T941
Test name
Test status
Simulation time	90611829551 ps
CPU time	79.86 seconds
Started	May 30 12:53:37 PM PDT 24
Finished	May 30 12:54:58 PM PDT 24
Peak memory	200340 kb
Host	smart-cb045be7-05fa-460f-b377-ff4b95105dfa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4223951050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.4223951050
Directory	/workspace/95.uart_fifo_reset/latest

Test location	/workspace/coverage/default/95.uart_stress_all_with_rand_reset.585937171
Short name	T65
Test name
Test status
Simulation time	199896300964 ps
CPU time	987.05 seconds
Started	May 30 12:53:38 PM PDT 24
Finished	May 30 01:10:06 PM PDT 24
Peak memory	216772 kb
Host	smart-85d15ec4-a040-4e9f-a462-8fee252aff10
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585937171 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.585937171
Directory	/workspace/95.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/96.uart_fifo_reset.3628009887
Short name	T206
Test name
Test status
Simulation time	23219915142 ps
CPU time	38.71 seconds
Started	May 30 12:53:37 PM PDT 24
Finished	May 30 12:54:16 PM PDT 24
Peak memory	200336 kb
Host	smart-3d61887a-643b-474f-9cf2-ff130316be28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628009887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3628009887
Directory	/workspace/96.uart_fifo_reset/latest

Test location	/workspace/coverage/default/97.uart_fifo_reset.267470486
Short name	T1139
Test name
Test status
Simulation time	13853796282 ps
CPU time	21.18 seconds
Started	May 30 12:53:40 PM PDT 24
Finished	May 30 12:54:02 PM PDT 24
Peak memory	200340 kb
Host	smart-2d7c173c-af9f-496b-b839-b9cd328b5e6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267470486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.267470486
Directory	/workspace/97.uart_fifo_reset/latest

Test location	/workspace/coverage/default/97.uart_stress_all_with_rand_reset.2696184800
Short name	T932
Test name
Test status
Simulation time	37485040521 ps
CPU time	232.2 seconds
Started	May 30 12:53:39 PM PDT 24
Finished	May 30 12:57:32 PM PDT 24
Peak memory	208748 kb
Host	smart-8b5151f9-e427-43cb-a698-154f0dce4973
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696184800 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2696184800
Directory	/workspace/97.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/98.uart_fifo_reset.646760377
Short name	T231
Test name
Test status
Simulation time	53217079107 ps
CPU time	83.94 seconds
Started	May 30 12:53:38 PM PDT 24
Finished	May 30 12:55:03 PM PDT 24
Peak memory	200244 kb
Host	smart-8f7ff35c-8540-4718-8aef-ec8a78681ece
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=646760377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.646760377
Directory	/workspace/98.uart_fifo_reset/latest

Test location	/workspace/coverage/default/98.uart_stress_all_with_rand_reset.2965724698
Short name	T594
Test name
Test status
Simulation time	35511724220 ps
CPU time	847.13 seconds
Started	May 30 12:53:37 PM PDT 24
Finished	May 30 01:07:45 PM PDT 24
Peak memory	217068 kb
Host	smart-929fe9fb-8f27-4479-b982-8257e7580365
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965724698 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2965724698
Directory	/workspace/98.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/99.uart_fifo_reset.404761096
Short name	T711
Test name
Test status
Simulation time	242036232480 ps
CPU time	221.25 seconds
Started	May 30 12:53:38 PM PDT 24
Finished	May 30 12:57:20 PM PDT 24
Peak memory	200248 kb
Host	smart-459b3e7f-5c79-4cb1-bb24-48c9abf2df1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=404761096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.404761096
Directory	/workspace/99.uart_fifo_reset/latest

Test location	/workspace/coverage/default/99.uart_stress_all_with_rand_reset.248559541
Short name	T1037
Test name
Test status
Simulation time	179056657335 ps
CPU time	871.59 seconds
Started	May 30 12:53:36 PM PDT 24
Finished	May 30 01:08:09 PM PDT 24
Peak memory	216820 kb
Host	smart-eceb0e92-1128-4513-84bf-d7645590fb43
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248559541 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.248559541
Directory	/workspace/99.uart_stress_all_with_rand_reset/latest