Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	113430	1			T1	33		T2	48		T3	5
all_values[1]	113430	1			T1	33		T2	48		T3	5
all_values[2]	113430	1			T1	33		T2	48		T3	5
all_values[3]	113430	1			T1	33		T2	48		T3	5
all_values[4]	113430	1			T1	33		T2	48		T3	5
all_values[5]	113430	1			T1	33		T2	48		T3	5
all_values[6]	113430	1			T1	33		T2	48		T3	5
all_values[7]	113430	1			T1	33		T2	48		T3	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

455663

1

T1

198

T2

254

T3

21

auto[1]

451777

1

T1

66

T2

130

T3

19

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

851496

1

T1

254

T2

309

T3

34

auto[1]

55944

1

T1

10

T2

75

T3

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	33403	1			T2	3		T4	13		T7	3
all_values[0]	auto[0]	auto[1]	22427	1			T1	3		T2	14		T4	2
all_values[0]	auto[1]	auto[0]	35224	1			T1	25		T2	1		T3	3
all_values[0]	auto[1]	auto[1]	22376	1			T1	5		T2	30		T3	2
all_values[1]	auto[0]	auto[0]	57642	1			T1	33		T2	44		T3	3
all_values[1]	auto[0]	auto[1]	1669	1			T2	1		T5	3		T7	3
all_values[1]	auto[1]	auto[0]	52539	1			T2	2		T3	2		T5	3
all_values[1]	auto[1]	auto[1]	1580	1			T2	1		T9	1		T11	35
all_values[2]	auto[0]	auto[0]	52718	1			T1	30		T2	31		T3	1
all_values[2]	auto[0]	auto[1]	2800	1			T1	1		T2	4		T3	2
all_values[2]	auto[1]	auto[0]	55588	1			T1	1		T2	8		T5	15
all_values[2]	auto[1]	auto[1]	2324	1			T1	1		T2	5		T3	2
all_values[3]	auto[0]	auto[0]	59590	1			T1	3		T2	38		T3	2
all_values[3]	auto[0]	auto[1]	285	1			T2	2		T6	1		T13	6
all_values[3]	auto[1]	auto[0]	53247	1			T1	30		T2	5		T3	3
all_values[3]	auto[1]	auto[1]	308	1			T2	3		T11	1		T13	1
all_values[4]	auto[0]	auto[0]	57335	1			T1	31		T2	30		T3	5
all_values[4]	auto[0]	auto[1]	387	1			T2	2		T13	2		T30	3
all_values[4]	auto[1]	auto[0]	55164	1			T1	2		T2	15		T4	15
all_values[4]	auto[1]	auto[1]	544	1			T2	1		T13	9		T15	5
all_values[5]	auto[0]	auto[0]	55695	1			T1	31		T2	19		T4	15
all_values[5]	auto[0]	auto[1]	140	1			T2	2		T29	1		T30	2
all_values[5]	auto[1]	auto[0]	57427	1			T1	2		T2	23		T3	5
all_values[5]	auto[1]	auto[1]	168	1			T2	4		T13	2		T29	1
all_values[6]	auto[0]	auto[0]	54618	1			T1	33		T2	40		T3	3
all_values[6]	auto[0]	auto[1]	164	1			T2	1		T13	3		T29	2
all_values[6]	auto[1]	auto[0]	58507	1			T2	6		T3	2		T5	1
all_values[6]	auto[1]	auto[1]	141	1			T2	1		T13	1		T30	2
all_values[7]	auto[0]	auto[0]	56430	1			T1	33		T2	21		T3	5
all_values[7]	auto[0]	auto[1]	360	1			T2	2		T5	6		T13	3
all_values[7]	auto[1]	auto[0]	56369	1			T2	23		T4	15		T6	3
all_values[7]	auto[1]	auto[1]	271	1			T2	2		T13	5		T99	2