Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2618

1

T1

1

T2

6

T3

1

auto[UartRx]

2618

1

T1

1

T2

6

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4580	1			T1	2		T2	10		T3	2
values[1]	47	1			T10	2		T13	1		T29	1
values[2]	56	1			T29	1		T34	1		T274	2
values[3]	47	1			T13	1		T34	2		T274	1
values[4]	63	1			T10	2		T13	2		T30	1
values[5]	68	1			T22	1		T29	1		T30	1
values[6]	55	1			T13	1		T22	2		T274	1
values[7]	66	1			T2	1		T22	2		T33	2
values[8]	66	1			T2	1		T22	4		T30	2
values[9]	74	1			T10	2		T31	2		T32	1
values[10]	65	1			T22	1		T33	2		T93	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2404	1			T1	1		T2	6		T3	1
auto[UartTx]	values[1]	11	1			T34	1		T135	1		T317	1
auto[UartTx]	values[2]	17	1			T29	1		T88	1		T44	1
auto[UartTx]	values[3]	18	1			T34	1		T274	1		T92	1
auto[UartTx]	values[4]	12	1			T10	1		T13	1		T93	1
auto[UartTx]	values[5]	27	1			T30	1		T32	1		T92	1
auto[UartTx]	values[6]	15	1			T22	1		T274	1		T94	2
auto[UartTx]	values[7]	26	1			T33	1		T274	1		T318	3
auto[UartTx]	values[8]	21	1			T22	1		T30	1		T92	1
auto[UartTx]	values[9]	23	1			T10	1		T31	1		T33	1
auto[UartTx]	values[10]	26	1			T22	1		T33	1		T93	1
auto[UartRx]	values[0]	2176	1			T1	1		T2	4		T3	1
auto[UartRx]	values[1]	36	1			T10	2		T13	1		T29	1
auto[UartRx]	values[2]	39	1			T34	1		T274	2		T92	2
auto[UartRx]	values[3]	29	1			T13	1		T34	1		T88	1
auto[UartRx]	values[4]	51	1			T10	1		T13	1		T30	1
auto[UartRx]	values[5]	41	1			T22	1		T29	1		T34	1
auto[UartRx]	values[6]	40	1			T13	1		T22	1		T91	1
auto[UartRx]	values[7]	40	1			T2	1		T22	2		T33	1
auto[UartRx]	values[8]	45	1			T2	1		T22	3		T30	1
auto[UartRx]	values[9]	51	1			T10	1		T31	1		T32	1
auto[UartRx]	values[10]	39	1			T33	1		T94	1		T305	1