Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2231	1			T1	3		T2	1		T3	1
auto[BaudRate115200]	1916	1			T1	1		T2	5		T4	1
auto[BaudRate230400]	1966	1			T1	2		T2	4		T3	3
auto[BaudRate128Kbps]	1946	1			T1	1		T2	8		T3	3
auto[BaudRate256Kbps]	2015	1			T2	2		T5	2		T6	1
auto[BaudRate1Mbps]	1739	1			T1	2		T2	3		T4	2
auto[BaudRate1p5Mbps]	1369	1			T1	1		T2	1		T4	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1052	1			T275	1		T293	2		T319	1
freqs[25]	1504	1			T4	5		T13	81		T40	5
freqs[48]	529	1			T320	2		T321	8		T322	2
freqs[50]	521	1			T7	10		T22	27		T39	8
freqs[100]	1352	1			T41	9		T20	5		T285	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	234	1			T319	1		T252	1		T298	2
auto[BaudRate9600]	freqs[25]	217	1			T4	1		T13	16		T40	2
auto[BaudRate9600]	freqs[48]	71	1			T322	1		T311	5		T203	1
auto[BaudRate9600]	freqs[50]	104	1			T22	2		T39	1		T323	1
auto[BaudRate9600]	freqs[100]	218	1			T41	1		T20	5		T18	18
auto[BaudRate115200]	freqs[24]	153	1			T275	1		T293	1		T298	1
auto[BaudRate115200]	freqs[25]	243	1			T4	1		T13	11		T105	1
auto[BaudRate115200]	freqs[48]	65	1			T321	3		T322	1		T324	1
auto[BaudRate115200]	freqs[50]	56	1			T7	3		T22	4		T39	1
auto[BaudRate115200]	freqs[100]	203	1			T41	1		T30	14		T246	2
auto[BaudRate230400]	freqs[24]	139	1			T252	2		T257	4		T141	2
auto[BaudRate230400]	freqs[25]	243	1			T13	6		T40	1		T105	2
auto[BaudRate230400]	freqs[48]	80	1			T320	1		T321	2		T324	2
auto[BaudRate230400]	freqs[50]	85	1			T7	2		T22	2		T39	4
auto[BaudRate230400]	freqs[100]	190	1			T30	11		T101	2		T325	3
auto[BaudRate128Kbps]	freqs[24]	136	1			T141	1		T142	1		T326	1
auto[BaudRate128Kbps]	freqs[25]	216	1			T13	16		T32	4		T33	19
auto[BaudRate128Kbps]	freqs[48]	64	1			T320	1		T324	1		T327	3
auto[BaudRate128Kbps]	freqs[50]	67	1			T7	1		T22	5		T15	1
auto[BaudRate128Kbps]	freqs[100]	182	1			T41	5		T285	1		T30	11
auto[BaudRate256Kbps]	freqs[24]	158	1			T293	1		T298	1		T257	3
auto[BaudRate256Kbps]	freqs[25]	254	1			T13	7		T40	1		T105	1
auto[BaudRate256Kbps]	freqs[48]	59	1			T324	1		T327	6		T328	1
auto[BaudRate256Kbps]	freqs[50]	78	1			T7	3		T22	6		T249	2
auto[BaudRate256Kbps]	freqs[100]	192	1			T41	1		T30	7		T282	1
auto[BaudRate1Mbps]	freqs[24]	157	1			T298	1		T257	1		T142	2
auto[BaudRate1Mbps]	freqs[25]	220	1			T4	2		T13	18		T105	1
auto[BaudRate1Mbps]	freqs[48]	92	1			T321	3		T324	3		T327	12
auto[BaudRate1Mbps]	freqs[50]	74	1			T22	4		T39	1		T250	1
auto[BaudRate1Mbps]	freqs[100]	177	1			T41	1		T30	6		T101	2
auto[BaudRate1p5Mbps]	freqs[25]	111	1			T4	1		T13	7		T40	1
auto[BaudRate1p5Mbps]	freqs[48]	98	1			T324	2		T327	21		T329	1
auto[BaudRate1p5Mbps]	freqs[50]	57	1			T7	1		T22	4		T39	1
auto[BaudRate1p5Mbps]	freqs[100]	190	1			T285	1		T30	13		T101	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded