Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.89	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	14	116	89.23

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	14	116	89.23	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	32050363	1			T1	53		T2	407		T3	39
all_levels[1]	178671	1			T2	10		T3	2		T4	7
all_levels[2]	2555	1			T2	8		T4	5		T9	7
all_levels[3]	1111	1			T2	2		T4	1		T5	3
all_levels[4]	731	1			T5	1		T7	2		T10	2
all_levels[5]	502	1			T4	2		T5	2		T9	2
all_levels[6]	396	1			T9	2		T11	2		T42	1
all_levels[7]	336	1			T2	1		T7	2		T11	4
all_levels[8]	255	1			T41	1		T105	2		T29	2
all_levels[9]	248	1			T4	1		T30	1		T106	1
all_levels[10]	213	1			T5	1		T11	3		T13	1
all_levels[11]	213	1			T4	1		T11	4		T41	1
all_levels[12]	152	1			T7	1		T11	1		T13	1
all_levels[13]	203	1			T41	1		T99	1		T107	1
all_levels[14]	118	1			T35	2		T31	2		T108	1
all_levels[15]	101	1			T1	4		T7	1		T11	1
all_levels[16]	126	1			T3	1		T5	2		T6	1
all_levels[17]	106	1			T5	1		T41	3		T107	1
all_levels[18]	112	1			T8	1		T41	4		T107	3
all_levels[19]	86	1			T109	1		T110	1		T111	1
all_levels[20]	79	1			T101	4		T112	1		T113	1
all_levels[21]	72	1			T6	1		T13	2		T107	1
all_levels[22]	62	1			T105	2		T101	1		T34	1
all_levels[23]	62	1			T5	1		T7	4		T13	1
all_levels[24]	59	1			T5	1		T6	2		T41	2
all_levels[25]	60	1			T100	1		T108	2		T109	1
all_levels[26]	45	1			T3	1		T100	1		T101	2
all_levels[27]	40	1			T5	1		T7	1		T111	1
all_levels[28]	44	1			T7	1		T13	1		T107	1
all_levels[29]	38	1			T31	1		T32	1		T114	2
all_levels[30]	50	1			T3	1		T115	1		T116	1
all_levels[31]	41	1			T117	1		T118	1		T119	1
all_levels[32]	25	1			T44	1		T120	1		T121	1
all_levels[33]	23	1			T122	1		T123	1		T124	1
all_levels[34]	27	1			T33	1		T125	1		T126	3
all_levels[35]	21	1			T33	1		T127	1		T85	1
all_levels[36]	20	1			T128	1		T129	1		T130	1
all_levels[37]	20	1			T131	1		T125	1		T132	1
all_levels[38]	32	1			T7	1		T133	1		T134	1
all_levels[39]	19	1			T7	2		T32	1		T85	1
all_levels[40]	14	1			T135	1		T121	2		T136	1
all_levels[41]	31	1			T5	1		T6	1		T7	2
all_levels[42]	27	1			T137	1		T127	1		T138	1
all_levels[43]	16	1			T111	1		T138	1		T139	1
all_levels[44]	19	1			T140	1		T141	1		T142	3
all_levels[45]	11	1			T143	1		T33	1		T144	2
all_levels[46]	13	1			T13	1		T12	1		T34	1
all_levels[47]	13	1			T145	1		T146	1		T147	1
all_levels[48]	7	1			T148	1		T149	1		T150	1
all_levels[49]	7	1			T151	1		T152	1		T153	1
all_levels[50]	14	1			T154	1		T139	2		T155	1
all_levels[51]	5	1			T108	1		T156	1		T157	1
all_levels[52]	10	1			T109	2		T158	1		T159	1
all_levels[53]	8	1			T140	1		T148	1		T160	1
all_levels[54]	3	1			T122	1		T161	1		T162	1
all_levels[55]	11	1			T100	2		T124	1		T163	1
all_levels[56]	7	1			T44	1		T164	1		T165	1
all_levels[57]	5	1			T166	1		T167	1		T168	1
all_levels[58]	5	1			T47	1		T169	1		T170	1
all_levels[59]	1	1			T171	1		-	-		-	-
all_levels[60]	8	1			T172	1		T148	1		T173	1
all_levels[61]	5	1			T148	1		T163	1		T174	1
all_levels[62]	10	1			T175	1		T176	1		T149	1
all_levels[63]	11	1			T6	1		T103	1		T134	2
all_levels[64]	116	1			T6	1		T11	2		T12	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32233103

1

T1

47

T2

427

T3

44

auto[1]

4711

1

T1

10

T2

1

T4

4

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	14	116	89.23	14

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[37]]	[auto[1]]	0	1	1
[all_levels[48] , all_levels[49]]	[auto[1]]	--	--	2
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[53] , all_levels[54]]	[auto[1]]	--	--	2
[all_levels[56] , all_levels[57] , all_levels[58] , all_levels[59]]	[auto[1]]	--	--	4
[all_levels[61] , all_levels[62]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	32046162	1			T1	46		T2	406		T3	39
all_levels[0]	auto[1]	4201	1			T1	7		T2	1		T4	2
all_levels[1]	auto[0]	178590	1			T2	10		T3	2		T4	5
all_levels[1]	auto[1]	81	1			T4	2		T12	1		T128	2
all_levels[2]	auto[0]	2536	1			T2	8		T4	5		T9	7
all_levels[2]	auto[1]	19	1			T177	1		T113	1		T133	1
all_levels[3]	auto[0]	1073	1			T2	2		T4	1		T5	3
all_levels[3]	auto[1]	38	1			T178	1		T179	2		T142	3
all_levels[4]	auto[0]	702	1			T5	1		T7	2		T10	2
all_levels[4]	auto[1]	29	1			T11	1		T180	3		T172	1
all_levels[5]	auto[0]	488	1			T4	2		T5	2		T9	2
all_levels[5]	auto[1]	14	1			T177	1		T154	2		T181	1
all_levels[6]	auto[0]	374	1			T9	2		T11	2		T42	1
all_levels[6]	auto[1]	22	1			T100	4		T182	3		T133	1
all_levels[7]	auto[0]	321	1			T2	1		T7	1		T11	4
all_levels[7]	auto[1]	15	1			T7	1		T84	2		T183	1
all_levels[8]	auto[0]	243	1			T41	1		T105	1		T29	2
all_levels[8]	auto[1]	12	1			T105	1		T184	1		T185	1
all_levels[9]	auto[0]	230	1			T4	1		T30	1		T106	1
all_levels[9]	auto[1]	18	1			T186	3		T121	2		T187	4
all_levels[10]	auto[0]	206	1			T5	1		T11	3		T13	1
all_levels[10]	auto[1]	7	1			T128	1		T188	1		T189	1
all_levels[11]	auto[0]	198	1			T4	1		T11	4		T41	1
all_levels[11]	auto[1]	15	1			T101	1		T190	2		T191	1
all_levels[12]	auto[0]	145	1			T7	1		T11	1		T13	1
all_levels[12]	auto[1]	7	1			T112	1		T127	1		T156	2
all_levels[13]	auto[0]	194	1			T41	1		T99	1		T107	1
all_levels[13]	auto[1]	9	1			T132	2		T192	1		T193	2
all_levels[14]	auto[0]	108	1			T35	1		T31	1		T108	1
all_levels[14]	auto[1]	10	1			T35	1		T31	1		T194	1
all_levels[15]	auto[0]	90	1			T1	1		T7	1		T11	1
all_levels[15]	auto[1]	11	1			T1	3		T195	1		T196	1
all_levels[16]	auto[0]	108	1			T3	1		T5	2		T6	1
all_levels[16]	auto[1]	18	1			T7	1		T197	4		T198	1
all_levels[17]	auto[0]	99	1			T5	1		T41	1		T107	1
all_levels[17]	auto[1]	7	1			T41	2		T199	1		T200	1
all_levels[18]	auto[0]	94	1			T8	1		T41	2		T107	3
all_levels[18]	auto[1]	18	1			T41	2		T109	2		T123	8
all_levels[19]	auto[0]	79	1			T109	1		T110	1		T111	1
all_levels[19]	auto[1]	7	1			T155	1		T201	4		T202	1
all_levels[20]	auto[0]	69	1			T101	1		T112	1		T113	1
all_levels[20]	auto[1]	10	1			T101	3		T203	3		T204	1
all_levels[21]	auto[0]	61	1			T6	1		T13	2		T107	1
all_levels[21]	auto[1]	11	1			T184	1		T205	1		T206	1
all_levels[22]	auto[0]	58	1			T105	1		T101	1		T34	1
all_levels[22]	auto[1]	4	1			T105	1		T207	1		T208	1
all_levels[23]	auto[0]	54	1			T5	1		T7	3		T13	1
all_levels[23]	auto[1]	8	1			T7	1		T209	1		T156	2
all_levels[24]	auto[0]	53	1			T5	1		T6	2		T41	1
all_levels[24]	auto[1]	6	1			T41	1		T210	1		T211	1
all_levels[25]	auto[0]	51	1			T100	1		T108	1		T109	1
all_levels[25]	auto[1]	9	1			T108	1		T123	1		T212	1
all_levels[26]	auto[0]	41	1			T3	1		T100	1		T101	2
all_levels[26]	auto[1]	4	1			T213	1		T211	2		T214	1
all_levels[27]	auto[0]	36	1			T5	1		T7	1		T111	1
all_levels[27]	auto[1]	4	1			T149	1		T215	1		T216	2
all_levels[28]	auto[0]	43	1			T7	1		T13	1		T107	1
all_levels[28]	auto[1]	1	1			T217	1		-	-		-	-
all_levels[29]	auto[0]	35	1			T31	1		T32	1		T114	1
all_levels[29]	auto[1]	3	1			T114	1		T218	2		-	-
all_levels[30]	auto[0]	46	1			T3	1		T115	1		T116	1
all_levels[30]	auto[1]	4	1			T155	1		T219	1		T220	1
all_levels[31]	auto[0]	32	1			T117	1		T118	1		T119	1
all_levels[31]	auto[1]	9	1			T94	1		T221	7		T222	1
all_levels[32]	auto[0]	23	1			T44	1		T120	1		T121	1
all_levels[32]	auto[1]	2	1			T223	1		T199	1		-	-
all_levels[33]	auto[0]	23	1			T122	1		T123	1		T124	1
all_levels[34]	auto[0]	22	1			T33	1		T125	1		T126	1
all_levels[34]	auto[1]	5	1			T126	2		T224	3		-	-
all_levels[35]	auto[0]	21	1			T33	1		T127	1		T85	1
all_levels[36]	auto[0]	16	1			T128	1		T129	1		T130	1
all_levels[36]	auto[1]	4	1			T225	2		T226	1		T227	1
all_levels[37]	auto[0]	20	1			T131	1		T125	1		T132	1
all_levels[38]	auto[0]	24	1			T7	1		T133	1		T134	1
all_levels[38]	auto[1]	8	1			T228	2		T229	1		T230	2
all_levels[39]	auto[0]	16	1			T7	2		T32	1		T85	1
all_levels[39]	auto[1]	3	1			T231	1		T232	2		-	-
all_levels[40]	auto[0]	13	1			T135	1		T121	2		T136	1
all_levels[40]	auto[1]	1	1			T233	1		-	-		-	-
all_levels[41]	auto[0]	23	1			T5	1		T6	1		T7	1
all_levels[41]	auto[1]	8	1			T7	1		T31	2		T234	3
all_levels[42]	auto[0]	23	1			T137	1		T127	1		T138	1
all_levels[42]	auto[1]	4	1			T136	1		T150	1		T195	2
all_levels[43]	auto[0]	15	1			T111	1		T138	1		T139	1
all_levels[43]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[44]	auto[0]	15	1			T140	1		T141	1		T142	1
all_levels[44]	auto[1]	4	1			T142	2		T150	1		T236	1
all_levels[45]	auto[0]	10	1			T143	1		T33	1		T144	1
all_levels[45]	auto[1]	1	1			T144	1		-	-		-	-
all_levels[46]	auto[0]	12	1			T13	1		T12	1		T34	1
all_levels[46]	auto[1]	1	1			T237	1		-	-		-	-
all_levels[47]	auto[0]	8	1			T145	1		T146	1		T147	1
all_levels[47]	auto[1]	5	1			T238	1		T239	4		-	-
all_levels[48]	auto[0]	7	1			T148	1		T149	1		T150	1
all_levels[49]	auto[0]	7	1			T151	1		T152	1		T153	1
all_levels[50]	auto[0]	11	1			T154	1		T139	2		T155	1
all_levels[50]	auto[1]	3	1			T240	3		-	-		-	-
all_levels[51]	auto[0]	5	1			T108	1		T156	1		T157	1
all_levels[52]	auto[0]	6	1			T109	1		T158	1		T159	1
all_levels[52]	auto[1]	4	1			T109	1		T241	3		-	-
all_levels[53]	auto[0]	8	1			T140	1		T148	1		T160	1
all_levels[54]	auto[0]	3	1			T122	1		T161	1		T162	1
all_levels[55]	auto[0]	8	1			T100	1		T124	1		T163	1
all_levels[55]	auto[1]	3	1			T100	1		T242	2		-	-
all_levels[56]	auto[0]	7	1			T44	1		T164	1		T165	1
all_levels[57]	auto[0]	5	1			T166	1		T167	1		T168	1
all_levels[58]	auto[0]	5	1			T47	1		T169	1		T170	1
all_levels[59]	auto[0]	1	1			T171	1		-	-		-	-
all_levels[60]	auto[0]	7	1			T172	1		T148	1		T173	1
all_levels[60]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[61]	auto[0]	5	1			T148	1		T163	1		T174	1
all_levels[62]	auto[0]	10	1			T175	1		T176	1		T149	1
all_levels[63]	auto[0]	10	1			T6	1		T103	1		T134	1
all_levels[63]	auto[1]	1	1			T134	1		-	-		-	-
all_levels[64]	auto[0]	95	1			T6	1		T11	1		T12	1
all_levels[64]	auto[1]	21	1			T11	1		T180	1		T143	1