Group : uart_env_pkg::uart_env_cov::rx_timeout_cg
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Group : uart_env_pkg::uart_env_cov::rx_timeout_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_timeout_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_timeout_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timeout 3 0 3 100.00 100 1 1 0


Summary for Variable cp_timeout

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_timeout

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
large_timeout 805 1 T4 3 T6 1 T7 11
medium_timeout 526 1 T1 1 T3 2 T6 1
small_timeout 427 1 T2 2 T13 4 T99 1

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