Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	113430	1			T1	33		T2	48		T3	5
all_pins[1]	113430	1			T1	33		T2	48		T3	5
all_pins[2]	113430	1			T1	33		T2	48		T3	5
all_pins[3]	113430	1			T1	33		T2	48		T3	5
all_pins[4]	113430	1			T1	33		T2	48		T3	5
all_pins[5]	113430	1			T1	33		T2	48		T3	5
all_pins[6]	113430	1			T1	33		T2	48		T3	5
all_pins[7]	113430	1			T1	33		T2	48		T3	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	878817	1			T1	258		T2	337		T3	35
values[0x1]	28623	1			T1	6		T2	47		T3	5
transitions[0x0=>0x1]	27466	1			T1	6		T2	42		T3	5
transitions[0x1=>0x0]	27021	1			T1	6		T2	42		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	90975	1			T1	28		T2	18		T3	3
all_pins[0]	values[0x1]	22455	1			T1	5		T2	30		T3	2
all_pins[0]	transitions[0x0=>0x1]	21819	1			T1	5		T2	30		T3	2
all_pins[0]	transitions[0x1=>0x0]	946	1			T2	1		T9	1		T11	20
all_pins[1]	values[0x0]	111848	1			T1	33		T2	47		T3	5
all_pins[1]	values[0x1]	1582	1			T2	1		T9	1		T11	35
all_pins[1]	transitions[0x0=>0x1]	1480	1			T9	1		T11	33		T13	7
all_pins[1]	transitions[0x1=>0x0]	2277	1			T1	1		T2	4		T3	2
all_pins[2]	values[0x0]	111051	1			T1	32		T2	43		T3	3
all_pins[2]	values[0x1]	2379	1			T1	1		T2	5		T3	2
all_pins[2]	transitions[0x0=>0x1]	2319	1			T1	1		T2	3		T3	2
all_pins[2]	transitions[0x1=>0x0]	248	1			T2	1		T13	1		T12	1
all_pins[3]	values[0x0]	113122	1			T1	33		T2	45		T3	5
all_pins[3]	values[0x1]	308	1			T2	3		T11	1		T13	1
all_pins[3]	transitions[0x0=>0x1]	249	1			T2	3		T11	1		T13	1
all_pins[3]	transitions[0x1=>0x0]	485	1			T2	1		T13	9		T15	5
all_pins[4]	values[0x0]	112886	1			T1	33		T2	47		T3	5
all_pins[4]	values[0x1]	544	1			T2	1		T13	9		T15	5
all_pins[4]	transitions[0x0=>0x1]	461	1			T13	6		T15	5		T29	2
all_pins[4]	transitions[0x1=>0x0]	138	1			T2	3		T29	1		T30	2
all_pins[5]	values[0x0]	113209	1			T1	33		T2	44		T3	5
all_pins[5]	values[0x1]	221	1			T2	4		T13	3		T29	1
all_pins[5]	transitions[0x0=>0x1]	183	1			T2	3		T13	3		T29	1
all_pins[5]	transitions[0x1=>0x0]	825	1			T3	1		T6	2		T7	1
all_pins[6]	values[0x0]	112567	1			T1	33		T2	47		T3	4
all_pins[6]	values[0x1]	863	1			T2	1		T3	1		T6	2
all_pins[6]	transitions[0x0=>0x1]	818	1			T2	1		T3	1		T6	2
all_pins[6]	transitions[0x1=>0x0]	226	1			T2	2		T13	5		T99	2
all_pins[7]	values[0x0]	113159	1			T1	33		T2	46		T3	5
all_pins[7]	values[0x1]	271	1			T2	2		T13	5		T99	2
all_pins[7]	transitions[0x0=>0x1]	137	1			T2	2		T99	2		T29	1
all_pins[7]	transitions[0x1=>0x0]	21876	1			T1	5		T2	30		T3	1