Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8362281	1			T1	15		T2	27		T3	8
all_levels[1]	1169242	1			T1	3		T2	49		T3	3
all_levels[2]	614707	1			T1	2		T2	2		T3	2
all_levels[3]	314179	1			T1	2		T2	8		T4	2
all_levels[4]	304647	1			T1	3		T2	4		T4	1
all_levels[5]	451446	1			T1	2		T2	10		T6	1
all_levels[6]	288056	1			T1	4		T2	29		T6	2
all_levels[7]	432068	1			T2	14		T6	5		T9	1
all_levels[8]	281247	1			T1	1		T2	27		T7	5
all_levels[9]	325413	1			T2	25		T6	2		T10	4215
all_levels[10]	445026	1			T2	16		T6	2		T9	3
all_levels[11]	241233	1			T2	54		T3	3		T7	1
all_levels[12]	222618	1			T1	3		T2	31		T3	1
all_levels[13]	222298	1			T1	1		T2	20		T7	8
all_levels[14]	378922	1			T2	35		T10	4208		T13	646
all_levels[15]	269604	1			T2	5		T7	2		T10	4225
all_levels[16]	417836	1			T10	4231		T13	705		T42	3
all_levels[17]	421236	1			T2	2		T10	4232		T13	441
all_levels[18]	265429	1			T1	1		T2	1		T5	1
all_levels[19]	517903	1			T10	3920		T13	399		T12	5
all_levels[20]	265640	1			T1	4		T2	2		T10	484
all_levels[21]	236618	1			T1	2		T10	480		T13	743
all_levels[22]	200571	1			T1	1		T2	1		T8	3
all_levels[23]	195257	1			T2	2		T10	482		T13	546
all_levels[24]	467933	1			T1	2		T10	493		T13	373
all_levels[25]	255273	1			T1	5		T10	484		T13	476
all_levels[26]	191787	1			T1	2		T10	494		T13	713
all_levels[27]	194082	1			T5	6		T6	2		T10	482
all_levels[28]	488251	1			T10	480		T13	311		T41	7
all_levels[29]	191264	1			T1	1		T10	2047		T13	551
all_levels[30]	185904	1			T2	4		T3	3		T5	1
all_levels[31]	742221	1			T1	2		T2	59		T3	8
all_levels[32]	12677238	1			T3	17		T4	22		T7	18

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32233103

1

T1

47

T2

427

T3

44

auto[1]

4327

1

T1

9

T3

1

T4

6

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8359996	1			T1	9		T2	27		T3	8
all_levels[0]	auto[1]	2285	1			T1	6		T4	3		T7	3
all_levels[1]	auto[0]	1168877	1			T1	3		T2	49		T3	3
all_levels[1]	auto[1]	365	1			T8	2		T42	1		T12	3
all_levels[2]	auto[0]	614675	1			T1	1		T2	2		T3	2
all_levels[2]	auto[1]	32	1			T1	1		T41	1		T99	1
all_levels[3]	auto[0]	313930	1			T1	2		T2	8		T4	1
all_levels[3]	auto[1]	249	1			T4	1		T154	1		T178	1
all_levels[4]	auto[0]	304619	1			T1	3		T2	4		T4	1
all_levels[4]	auto[1]	28	1			T35	1		T42	2		T112	2
all_levels[5]	auto[0]	451427	1			T1	2		T2	10		T6	1
all_levels[5]	auto[1]	19	1			T94	1		T330	1		T149	1
all_levels[6]	auto[0]	288033	1			T1	3		T2	29		T6	2
all_levels[6]	auto[1]	23	1			T1	1		T11	1		T177	1
all_levels[7]	auto[0]	431964	1			T2	14		T6	5		T9	1
all_levels[7]	auto[1]	104	1			T112	1		T102	12		T234	1
all_levels[8]	auto[0]	281230	1			T1	1		T2	27		T7	4
all_levels[8]	auto[1]	17	1			T7	1		T132	1		T121	1
all_levels[9]	auto[0]	325363	1			T2	25		T6	2		T10	4215
all_levels[9]	auto[1]	50	1			T35	2		T131	1		T191	1
all_levels[10]	auto[0]	444975	1			T2	16		T6	2		T9	3
all_levels[10]	auto[1]	51	1			T40	1		T249	3		T270	1
all_levels[11]	auto[0]	241215	1			T2	54		T3	3		T7	1
all_levels[11]	auto[1]	18	1			T108	1		T298	1		T331	1
all_levels[12]	auto[0]	222588	1			T1	3		T2	31		T3	1
all_levels[12]	auto[1]	30	1			T109	1		T257	1		T266	2
all_levels[13]	auto[0]	222265	1			T1	1		T2	20		T7	7
all_levels[13]	auto[1]	33	1			T7	1		T249	3		T127	2
all_levels[14]	auto[0]	378898	1			T2	35		T10	4208		T13	646
all_levels[14]	auto[1]	24	1			T140	1		T143	1		T93	1
all_levels[15]	auto[0]	269452	1			T2	5		T7	1		T10	4225
all_levels[15]	auto[1]	152	1			T7	1		T30	5		T259	1
all_levels[16]	auto[0]	417816	1			T10	4231		T13	705		T42	2
all_levels[16]	auto[1]	20	1			T42	1		T180	3		T332	2
all_levels[17]	auto[0]	421212	1			T2	2		T10	4232		T13	441
all_levels[17]	auto[1]	24	1			T12	1		T109	2		T263	1
all_levels[18]	auto[0]	265406	1			T1	1		T2	1		T5	1
all_levels[18]	auto[1]	23	1			T172	2		T333	2		T334	1
all_levels[19]	auto[0]	517886	1			T10	3920		T13	399		T12	5
all_levels[19]	auto[1]	17	1			T259	1		T124	2		T335	1
all_levels[20]	auto[0]	265627	1			T1	4		T2	2		T10	484
all_levels[20]	auto[1]	13	1			T134	2		T84	4		T336	3
all_levels[21]	auto[0]	236599	1			T1	2		T10	480		T13	743
all_levels[21]	auto[1]	19	1			T108	1		T178	1		T132	1
all_levels[22]	auto[0]	200555	1			T1	1		T2	1		T8	2
all_levels[22]	auto[1]	16	1			T8	1		T249	2		T154	2
all_levels[23]	auto[0]	195225	1			T2	2		T10	482		T13	546
all_levels[23]	auto[1]	32	1			T137	2		T89	1		T119	2
all_levels[24]	auto[0]	467905	1			T1	2		T10	493		T13	373
all_levels[24]	auto[1]	28	1			T179	1		T283	1		T197	3
all_levels[25]	auto[0]	255261	1			T1	5		T10	484		T13	476
all_levels[25]	auto[1]	12	1			T144	1		T337	2		T338	1
all_levels[26]	auto[0]	191772	1			T1	2		T10	494		T13	713
all_levels[26]	auto[1]	15	1			T172	2		T339	1		T340	4
all_levels[27]	auto[0]	194055	1			T5	5		T6	2		T10	482
all_levels[27]	auto[1]	27	1			T5	1		T273	1		T280	2
all_levels[28]	auto[0]	488232	1			T10	480		T13	311		T41	6
all_levels[28]	auto[1]	19	1			T41	1		T102	3		T114	2
all_levels[29]	auto[0]	191245	1			T1	1		T10	2047		T13	551
all_levels[29]	auto[1]	19	1			T182	3		T113	1		T266	1
all_levels[30]	auto[0]	185888	1			T2	4		T3	3		T5	1
all_levels[30]	auto[1]	16	1			T41	1		T37	1		T259	1
all_levels[31]	auto[0]	742191	1			T1	1		T2	59		T3	8
all_levels[31]	auto[1]	30	1			T1	1		T178	1		T91	1
all_levels[32]	auto[0]	12676721	1			T3	16		T4	20		T7	16
all_levels[32]	auto[1]	517	1			T3	1		T4	2		T7	2