Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	697	1			T2	7		T13	7		T29	4
all_values[1]	697	1			T2	7		T13	7		T29	4
all_values[2]	697	1			T2	7		T13	7		T29	4
all_values[3]	697	1			T2	7		T13	7		T29	4
all_values[4]	697	1			T2	7		T13	7		T29	4
all_values[5]	697	1			T2	7		T13	7		T29	4
all_values[6]	697	1			T2	7		T13	7		T29	4
all_values[7]	697	1			T2	7		T13	7		T29	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2962

1

T2

29

T13

29

T29

20

auto[1]

2614

1

T2

27

T13

27

T29

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2027

1

T2

16

T13

19

T29

11

auto[1]

3549

1

T2

40

T13

37

T29

21

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3323

1

T2

32

T13

31

T29

17

auto[1]

2253

1

T2

24

T13

25

T29

15

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	224	1			T2	3		T13	2		T29	1
all_values[0]	auto[0]	auto[1]	auto[1]	206	1			T2	1		T13	2		T29	1
all_values[0]	auto[1]	auto[0]	auto[1]	142	1			T2	1		T13	2		T29	2
all_values[0]	auto[1]	auto[1]	auto[1]	125	1			T2	2		T13	1		T30	2
all_values[1]	auto[0]	auto[0]	auto[0]	226	1			T2	3		T29	1		T33	2
all_values[1]	auto[0]	auto[1]	auto[0]	173	1			T2	2		T13	3		T30	2
all_values[1]	auto[1]	auto[0]	auto[1]	160	1			T2	1		T13	2		T29	3
all_values[1]	auto[1]	auto[1]	auto[1]	138	1			T2	1		T13	2		T30	1
all_values[2]	auto[0]	auto[0]	auto[0]	155	1			T13	4		T29	2		T93	1
all_values[2]	auto[0]	auto[0]	auto[1]	79	1			T2	2		T30	2		T92	1
all_values[2]	auto[0]	auto[1]	auto[0]	110	1			T13	2		T29	2		T88	3
all_values[2]	auto[0]	auto[1]	auto[1]	64	1			T2	1		T30	2		T33	2
all_values[2]	auto[1]	auto[0]	auto[1]	140	1			T2	1		T13	1		T30	2
all_values[2]	auto[1]	auto[1]	auto[1]	149	1			T2	3		T30	1		T33	1
all_values[3]	auto[0]	auto[0]	auto[0]	142	1			T29	1		T33	2		T92	2
all_values[3]	auto[0]	auto[0]	auto[1]	80	1			T13	2		T33	1		T88	1
all_values[3]	auto[0]	auto[1]	auto[0]	124	1			T2	2		T29	2		T92	1
all_values[3]	auto[0]	auto[1]	auto[1]	74	1			T2	1		T30	5		T88	2
all_values[3]	auto[1]	auto[0]	auto[1]	150	1			T2	4		T13	4		T29	1
all_values[3]	auto[1]	auto[1]	auto[1]	127	1			T13	1		T30	2		T88	4
all_values[4]	auto[0]	auto[0]	auto[0]	146	1			T2	2		T13	1		T30	1
all_values[4]	auto[0]	auto[0]	auto[1]	72	1			T2	2		T13	1		T30	2
all_values[4]	auto[0]	auto[1]	auto[0]	111	1			T2	1		T33	1		T92	3
all_values[4]	auto[0]	auto[1]	auto[1]	91	1			T13	2		T29	1		T30	2
all_values[4]	auto[1]	auto[0]	auto[1]	142	1			T2	1		T13	2		T29	2
all_values[4]	auto[1]	auto[1]	auto[1]	135	1			T2	1		T13	1		T29	1
all_values[5]	auto[0]	auto[0]	auto[0]	167	1			T13	2		T30	1		T33	2
all_values[5]	auto[0]	auto[0]	auto[1]	62	1			T2	1		T29	1		T88	2
all_values[5]	auto[0]	auto[1]	auto[0]	127	1			T13	1		T29	1		T33	1
all_values[5]	auto[0]	auto[1]	auto[1]	71	1			T2	3		T13	1		T30	1
all_values[5]	auto[1]	auto[0]	auto[1]	133	1			T29	1		T30	3		T33	1
all_values[5]	auto[1]	auto[1]	auto[1]	137	1			T2	3		T13	3		T29	1
all_values[6]	auto[0]	auto[0]	auto[0]	144	1			T2	1		T29	1		T33	1
all_values[6]	auto[0]	auto[0]	auto[1]	54	1			T13	1		T29	1		T30	1
all_values[6]	auto[0]	auto[1]	auto[0]	129	1			T2	2		T13	1		T29	1
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T13	1		T30	1		T93	1
all_values[6]	auto[1]	auto[0]	auto[1]	159	1			T2	2		T13	2		T29	1
all_values[6]	auto[1]	auto[1]	auto[1]	132	1			T2	2		T13	2		T30	2
all_values[7]	auto[0]	auto[0]	auto[0]	140	1			T2	2		T13	2		T33	2
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T2	1		T30	1		T33	1
all_values[7]	auto[0]	auto[1]	auto[0]	133	1			T2	1		T13	3		T92	1
all_values[7]	auto[0]	auto[1]	auto[1]	61	1			T2	1		T29	1		T93	2
all_values[7]	auto[1]	auto[0]	auto[1]	166	1			T2	2		T13	1		T29	2
all_values[7]	auto[1]	auto[1]	auto[1]	118	1			T13	1		T29	1		T30	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal