Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.25 99.27 97.95 100.00 98.80 100.00 99.50


Total test records in report: 1315
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T1256 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2820980961 Jun 02 12:52:38 PM PDT 24 Jun 02 12:52:40 PM PDT 24 37480311 ps
T1257 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2789626471 Jun 02 12:52:30 PM PDT 24 Jun 02 12:52:31 PM PDT 24 14860106 ps
T1258 /workspace/coverage/cover_reg_top/3.uart_intr_test.2884843997 Jun 02 12:52:22 PM PDT 24 Jun 02 12:52:23 PM PDT 24 16932115 ps
T53 /workspace/coverage/cover_reg_top/5.uart_csr_rw.866442357 Jun 02 12:52:18 PM PDT 24 Jun 02 12:52:19 PM PDT 24 14642520 ps
T1259 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1856015626 Jun 02 12:52:17 PM PDT 24 Jun 02 12:52:18 PM PDT 24 95783915 ps
T1260 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2051682948 Jun 02 12:52:13 PM PDT 24 Jun 02 12:52:15 PM PDT 24 129244126 ps
T1261 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3717555736 Jun 02 12:52:33 PM PDT 24 Jun 02 12:52:34 PM PDT 24 27978427 ps
T1262 /workspace/coverage/cover_reg_top/26.uart_intr_test.529036184 Jun 02 12:52:44 PM PDT 24 Jun 02 12:52:46 PM PDT 24 46534664 ps
T79 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3635981917 Jun 02 12:52:30 PM PDT 24 Jun 02 12:52:32 PM PDT 24 164181346 ps
T1263 /workspace/coverage/cover_reg_top/1.uart_intr_test.2771422279 Jun 02 12:52:13 PM PDT 24 Jun 02 12:52:14 PM PDT 24 46910096 ps
T1264 /workspace/coverage/cover_reg_top/30.uart_intr_test.1767699945 Jun 02 12:52:44 PM PDT 24 Jun 02 12:52:45 PM PDT 24 139495823 ps
T1265 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2701683303 Jun 02 12:52:38 PM PDT 24 Jun 02 12:52:40 PM PDT 24 260884456 ps
T78 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.643813922 Jun 02 12:52:36 PM PDT 24 Jun 02 12:52:38 PM PDT 24 328034270 ps
T1266 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3908015359 Jun 02 12:52:37 PM PDT 24 Jun 02 12:52:38 PM PDT 24 301865200 ps
T1267 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2973648301 Jun 02 12:52:12 PM PDT 24 Jun 02 12:52:13 PM PDT 24 39944267 ps
T1268 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4291823949 Jun 02 12:52:19 PM PDT 24 Jun 02 12:52:22 PM PDT 24 170192052 ps
T1269 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3186585608 Jun 02 12:52:40 PM PDT 24 Jun 02 12:52:41 PM PDT 24 321916400 ps
T1270 /workspace/coverage/cover_reg_top/11.uart_tl_errors.287085487 Jun 02 12:52:29 PM PDT 24 Jun 02 12:52:32 PM PDT 24 211034783 ps
T1271 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2579765180 Jun 02 12:52:38 PM PDT 24 Jun 02 12:52:40 PM PDT 24 277308829 ps
T1272 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1123162262 Jun 02 12:52:23 PM PDT 24 Jun 02 12:52:24 PM PDT 24 122476649 ps
T1273 /workspace/coverage/cover_reg_top/22.uart_intr_test.708467407 Jun 02 12:52:37 PM PDT 24 Jun 02 12:52:38 PM PDT 24 104463424 ps
T1274 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1123667169 Jun 02 12:52:24 PM PDT 24 Jun 02 12:52:25 PM PDT 24 23932209 ps
T1275 /workspace/coverage/cover_reg_top/19.uart_intr_test.3169515209 Jun 02 12:52:40 PM PDT 24 Jun 02 12:52:41 PM PDT 24 36596016 ps
T54 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2220146262 Jun 02 12:52:43 PM PDT 24 Jun 02 12:52:44 PM PDT 24 20731224 ps
T1276 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3398693256 Jun 02 12:52:30 PM PDT 24 Jun 02 12:52:32 PM PDT 24 182475023 ps
T1277 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3956042272 Jun 02 12:52:13 PM PDT 24 Jun 02 12:52:15 PM PDT 24 414887593 ps
T1278 /workspace/coverage/cover_reg_top/46.uart_intr_test.2697443988 Jun 02 12:52:45 PM PDT 24 Jun 02 12:52:46 PM PDT 24 35922265 ps
T1279 /workspace/coverage/cover_reg_top/0.uart_intr_test.3415430794 Jun 02 12:52:14 PM PDT 24 Jun 02 12:52:15 PM PDT 24 11390535 ps
T1280 /workspace/coverage/cover_reg_top/18.uart_intr_test.1160046361 Jun 02 12:52:38 PM PDT 24 Jun 02 12:52:40 PM PDT 24 23548031 ps
T1281 /workspace/coverage/cover_reg_top/45.uart_intr_test.3727684960 Jun 02 12:52:44 PM PDT 24 Jun 02 12:52:46 PM PDT 24 16841268 ps
T1282 /workspace/coverage/cover_reg_top/17.uart_intr_test.3496513913 Jun 02 12:52:38 PM PDT 24 Jun 02 12:52:39 PM PDT 24 29631886 ps
T1283 /workspace/coverage/cover_reg_top/18.uart_csr_rw.1155297430 Jun 02 12:52:37 PM PDT 24 Jun 02 12:52:39 PM PDT 24 14189383 ps
T1284 /workspace/coverage/cover_reg_top/35.uart_intr_test.1985378922 Jun 02 12:52:43 PM PDT 24 Jun 02 12:52:44 PM PDT 24 35511948 ps
T1285 /workspace/coverage/cover_reg_top/2.uart_intr_test.1407288405 Jun 02 12:52:15 PM PDT 24 Jun 02 12:52:16 PM PDT 24 15783201 ps
T1286 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4235082628 Jun 02 12:52:20 PM PDT 24 Jun 02 12:52:21 PM PDT 24 61079165 ps
T1287 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2967578984 Jun 02 12:52:19 PM PDT 24 Jun 02 12:52:20 PM PDT 24 75338881 ps
T1288 /workspace/coverage/cover_reg_top/6.uart_intr_test.2154157610 Jun 02 12:52:25 PM PDT 24 Jun 02 12:52:26 PM PDT 24 42134451 ps
T1289 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3727871587 Jun 02 12:52:38 PM PDT 24 Jun 02 12:52:39 PM PDT 24 45406976 ps
T1290 /workspace/coverage/cover_reg_top/34.uart_intr_test.1550187117 Jun 02 12:52:43 PM PDT 24 Jun 02 12:52:44 PM PDT 24 11338417 ps
T1291 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1116589768 Jun 02 12:52:43 PM PDT 24 Jun 02 12:52:45 PM PDT 24 116295534 ps
T1292 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2854055648 Jun 02 12:52:36 PM PDT 24 Jun 02 12:52:36 PM PDT 24 47507025 ps
T1293 /workspace/coverage/cover_reg_top/24.uart_intr_test.1260930875 Jun 02 12:52:38 PM PDT 24 Jun 02 12:52:39 PM PDT 24 13008166 ps
T1294 /workspace/coverage/cover_reg_top/8.uart_csr_rw.964516206 Jun 02 12:52:27 PM PDT 24 Jun 02 12:52:28 PM PDT 24 13051568 ps
T1295 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.374679437 Jun 02 12:52:20 PM PDT 24 Jun 02 12:52:22 PM PDT 24 281106191 ps
T1296 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3229835205 Jun 02 12:52:44 PM PDT 24 Jun 02 12:52:47 PM PDT 24 60133359 ps
T1297 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2488797056 Jun 02 12:52:31 PM PDT 24 Jun 02 12:52:33 PM PDT 24 476115470 ps
T1298 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2000382527 Jun 02 12:52:38 PM PDT 24 Jun 02 12:52:39 PM PDT 24 191611150 ps
T1299 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2727634883 Jun 02 12:52:38 PM PDT 24 Jun 02 12:52:39 PM PDT 24 105874566 ps
T1300 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.281764967 Jun 02 12:52:30 PM PDT 24 Jun 02 12:52:32 PM PDT 24 87359794 ps
T1301 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1946227959 Jun 02 12:52:19 PM PDT 24 Jun 02 12:52:20 PM PDT 24 85285086 ps
T1302 /workspace/coverage/cover_reg_top/8.uart_intr_test.323523895 Jun 02 12:52:24 PM PDT 24 Jun 02 12:52:25 PM PDT 24 44959758 ps
T1303 /workspace/coverage/cover_reg_top/33.uart_intr_test.1054809241 Jun 02 12:52:43 PM PDT 24 Jun 02 12:52:44 PM PDT 24 11946029 ps
T1304 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1258909497 Jun 02 12:52:19 PM PDT 24 Jun 02 12:52:20 PM PDT 24 81698050 ps
T1305 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3758607996 Jun 02 12:52:44 PM PDT 24 Jun 02 12:52:45 PM PDT 24 32027309 ps
T55 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.276138669 Jun 02 12:52:14 PM PDT 24 Jun 02 12:52:15 PM PDT 24 30716070 ps
T1306 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.4257113607 Jun 02 12:52:37 PM PDT 24 Jun 02 12:52:38 PM PDT 24 29422957 ps
T1307 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.723868503 Jun 02 12:52:35 PM PDT 24 Jun 02 12:52:37 PM PDT 24 74935495 ps
T1308 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1820004297 Jun 02 12:52:38 PM PDT 24 Jun 02 12:52:39 PM PDT 24 32503549 ps
T1309 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.499170605 Jun 02 12:52:37 PM PDT 24 Jun 02 12:52:38 PM PDT 24 15936018 ps
T1310 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2457268412 Jun 02 12:52:10 PM PDT 24 Jun 02 12:52:11 PM PDT 24 70774480 ps
T1311 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3731614671 Jun 02 12:52:14 PM PDT 24 Jun 02 12:52:16 PM PDT 24 20561237 ps
T1312 /workspace/coverage/cover_reg_top/10.uart_csr_rw.952811275 Jun 02 12:52:31 PM PDT 24 Jun 02 12:52:32 PM PDT 24 33575443 ps
T1313 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.267870304 Jun 02 12:52:38 PM PDT 24 Jun 02 12:52:40 PM PDT 24 93763281 ps
T1314 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.277350984 Jun 02 12:52:13 PM PDT 24 Jun 02 12:52:16 PM PDT 24 217639655 ps
T1315 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1995506596 Jun 02 12:52:16 PM PDT 24 Jun 02 12:52:18 PM PDT 24 184088757 ps

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3780793087
Short name T2
Test name
Test status
Simulation time 44305807501 ps
CPU time 274.11 seconds
Started Jun 02 01:20:01 PM PDT 24
Finished Jun 02 01:24:35 PM PDT 24
Peak memory 217032 kb
Host smart-0c6afe87-b6a0-4899-8373-309b2ceb9dc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780793087 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3780793087
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2668296218
Short name T13
Test name
Test status
Simulation time 152544057270 ps
CPU time 389.03 seconds
Started Jun 02 01:13:40 PM PDT 24
Finished Jun 02 01:20:09 PM PDT 24
Peak memory 216856 kb
Host smart-ddb31551-9096-49a1-a427-1126807226e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668296218 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2668296218
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1720718488
Short name T34
Test name
Test status
Simulation time 203769232396 ps
CPU time 1063.68 seconds
Started Jun 02 01:11:42 PM PDT 24
Finished Jun 02 01:29:26 PM PDT 24
Peak memory 216888 kb
Host smart-a255c7b8-a165-4bca-9b45-04025e3a7067
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720718488 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1720718488
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2642487819
Short name T22
Test name
Test status
Simulation time 141735838304 ps
CPU time 1003.36 seconds
Started Jun 02 01:15:44 PM PDT 24
Finished Jun 02 01:32:28 PM PDT 24
Peak memory 225224 kb
Host smart-f2cac8c8-f82c-4dfa-8075-552de7c78a07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642487819 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2642487819
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1318299986
Short name T33
Test name
Test status
Simulation time 278061679128 ps
CPU time 589.27 seconds
Started Jun 02 01:20:19 PM PDT 24
Finished Jun 02 01:30:09 PM PDT 24
Peak memory 225208 kb
Host smart-2b545ac2-871f-4dd0-bbc9-20df49a77cad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318299986 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1318299986
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2408792667
Short name T260
Test name
Test status
Simulation time 41392324328 ps
CPU time 143.1 seconds
Started Jun 02 01:12:58 PM PDT 24
Finished Jun 02 01:15:22 PM PDT 24
Peak memory 200340 kb
Host smart-4b30537e-a10c-4985-9c64-6b6c0625f200
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2408792667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2408792667
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_stress_all.336690687
Short name T148
Test name
Test status
Simulation time 341132198167 ps
CPU time 313.51 seconds
Started Jun 02 01:14:02 PM PDT 24
Finished Jun 02 01:19:16 PM PDT 24
Peak memory 200332 kb
Host smart-869275c3-228d-4b41-b8af-dc614f1b9162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336690687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.336690687
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3567050491
Short name T101
Test name
Test status
Simulation time 95596442209 ps
CPU time 167.12 seconds
Started Jun 02 01:21:27 PM PDT 24
Finished Jun 02 01:24:15 PM PDT 24
Peak memory 200428 kb
Host smart-d5720fdd-3988-4fbc-8abb-f8e3dae6930a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567050491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3567050491
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3734571762
Short name T26
Test name
Test status
Simulation time 75138056 ps
CPU time 0.77 seconds
Started Jun 02 01:11:15 PM PDT 24
Finished Jun 02 01:11:16 PM PDT 24
Peak memory 218616 kb
Host smart-49c6ea03-e189-43bd-affe-8e68e80f984b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734571762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3734571762
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.4261299195
Short name T38
Test name
Test status
Simulation time 172411670219 ps
CPU time 552.97 seconds
Started Jun 02 01:14:00 PM PDT 24
Finished Jun 02 01:23:14 PM PDT 24
Peak memory 200372 kb
Host smart-e771c81b-44dc-4707-9e8c-6a2a01b3f702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4261299195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4261299195
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2214552427
Short name T1
Test name
Test status
Simulation time 67542955978 ps
CPU time 138.28 seconds
Started Jun 02 01:21:39 PM PDT 24
Finished Jun 02 01:23:58 PM PDT 24
Peak memory 200396 kb
Host smart-cff0ad37-52fb-4fc5-b0cc-4473403202c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214552427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2214552427
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.381058044
Short name T37
Test name
Test status
Simulation time 246296611562 ps
CPU time 554.47 seconds
Started Jun 02 01:13:19 PM PDT 24
Finished Jun 02 01:22:34 PM PDT 24
Peak memory 200504 kb
Host smart-191e1be4-e3cc-4f52-84f1-6818c85ce415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381058044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.381058044
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all.4140009788
Short name T378
Test name
Test status
Simulation time 86599337934 ps
CPU time 476.22 seconds
Started Jun 02 01:12:30 PM PDT 24
Finished Jun 02 01:20:27 PM PDT 24
Peak memory 200368 kb
Host smart-859798b3-b922-47fd-8017-7a8de6baf2d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140009788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.4140009788
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1102871430
Short name T90
Test name
Test status
Simulation time 173662970639 ps
CPU time 78.09 seconds
Started Jun 02 01:17:49 PM PDT 24
Finished Jun 02 01:19:08 PM PDT 24
Peak memory 200340 kb
Host smart-956315ba-d9f4-41da-8f5a-662847f54559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102871430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1102871430
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1675365090
Short name T109
Test name
Test status
Simulation time 196197295422 ps
CPU time 18.32 seconds
Started Jun 02 01:21:45 PM PDT 24
Finished Jun 02 01:22:04 PM PDT 24
Peak memory 200328 kb
Host smart-4a656ced-1739-47cf-8b5f-d1ab48c45568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675365090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1675365090
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1285596283
Short name T316
Test name
Test status
Simulation time 318307920453 ps
CPU time 122.03 seconds
Started Jun 02 01:21:45 PM PDT 24
Finished Jun 02 01:23:48 PM PDT 24
Peak memory 200356 kb
Host smart-a5f2c58c-c998-4857-8699-dda55920c7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285596283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1285596283
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2876243332
Short name T92
Test name
Test status
Simulation time 117885131476 ps
CPU time 331.47 seconds
Started Jun 02 01:20:21 PM PDT 24
Finished Jun 02 01:25:53 PM PDT 24
Peak memory 216688 kb
Host smart-1e392b08-d3d8-4ea2-a9a1-741dd5517a76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876243332 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2876243332
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.560493837
Short name T76
Test name
Test status
Simulation time 162914717 ps
CPU time 1.33 seconds
Started Jun 02 12:52:36 PM PDT 24
Finished Jun 02 12:52:37 PM PDT 24
Peak memory 199492 kb
Host smart-dc3aa7dd-c4a8-4733-a312-05c3b1b94ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560493837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.560493837
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/15.uart_alert_test.1349059198
Short name T381
Test name
Test status
Simulation time 46070126 ps
CPU time 0.59 seconds
Started Jun 02 01:13:29 PM PDT 24
Finished Jun 02 01:13:30 PM PDT 24
Peak memory 195688 kb
Host smart-5b2244d2-aff5-4b19-8cd6-23b3101b9e2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349059198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1349059198
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3573423711
Short name T112
Test name
Test status
Simulation time 78949482224 ps
CPU time 121.88 seconds
Started Jun 02 01:21:47 PM PDT 24
Finished Jun 02 01:23:49 PM PDT 24
Peak memory 200432 kb
Host smart-a0fa88a9-a677-4e01-8cc5-017b34b5269f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573423711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3573423711
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3741164516
Short name T7
Test name
Test status
Simulation time 51622259723 ps
CPU time 41.46 seconds
Started Jun 02 01:22:01 PM PDT 24
Finished Jun 02 01:22:43 PM PDT 24
Peak memory 200244 kb
Host smart-9b4b226a-74d0-46f2-947b-c04a87396bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741164516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3741164516
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2163316936
Short name T51
Test name
Test status
Simulation time 17782881 ps
CPU time 0.62 seconds
Started Jun 02 12:52:17 PM PDT 24
Finished Jun 02 12:52:18 PM PDT 24
Peak memory 195292 kb
Host smart-b4ce7809-7ae4-4993-b751-38b4f3ba56a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163316936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2163316936
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1706780615
Short name T41
Test name
Test status
Simulation time 98711302768 ps
CPU time 339.34 seconds
Started Jun 02 01:22:18 PM PDT 24
Finished Jun 02 01:27:58 PM PDT 24
Peak memory 200328 kb
Host smart-79526323-aefc-46d6-862e-ec5610f04bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706780615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1706780615
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.864312073
Short name T135
Test name
Test status
Simulation time 400344024899 ps
CPU time 653.84 seconds
Started Jun 02 01:19:54 PM PDT 24
Finished Jun 02 01:30:48 PM PDT 24
Peak memory 216772 kb
Host smart-390cc87c-edf3-40be-ac10-e2e24ba5aa4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864312073 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.864312073
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.164501696
Short name T119
Test name
Test status
Simulation time 76690424034 ps
CPU time 211.44 seconds
Started Jun 02 01:20:46 PM PDT 24
Finished Jun 02 01:24:18 PM PDT 24
Peak memory 200424 kb
Host smart-ae81683e-520c-4bfa-b1c5-896906991db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164501696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.164501696
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1243249492
Short name T132
Test name
Test status
Simulation time 98650067575 ps
CPU time 241.75 seconds
Started Jun 02 01:22:28 PM PDT 24
Finished Jun 02 01:26:31 PM PDT 24
Peak memory 200396 kb
Host smart-17eeb9b9-7171-484a-995b-69ae96a4a2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243249492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1243249492
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2538320784
Short name T127
Test name
Test status
Simulation time 245586072675 ps
CPU time 63.79 seconds
Started Jun 02 01:21:40 PM PDT 24
Finished Jun 02 01:22:44 PM PDT 24
Peak memory 200412 kb
Host smart-62e645ac-793e-4802-8114-e051783e1b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538320784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2538320784
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3823127354
Short name T142
Test name
Test status
Simulation time 139942356614 ps
CPU time 65.07 seconds
Started Jun 02 01:19:46 PM PDT 24
Finished Jun 02 01:20:51 PM PDT 24
Peak memory 200324 kb
Host smart-a34c5780-5f9d-4245-a56f-6932a63e3f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823127354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3823127354
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all.3702026207
Short name T124
Test name
Test status
Simulation time 290279674141 ps
CPU time 567.58 seconds
Started Jun 02 01:12:52 PM PDT 24
Finished Jun 02 01:22:20 PM PDT 24
Peak memory 200624 kb
Host smart-ac1b7886-573e-4f10-b9ae-b45de5fe0825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702026207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3702026207
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.374679437
Short name T1295
Test name
Test status
Simulation time 281106191 ps
CPU time 1.27 seconds
Started Jun 02 12:52:20 PM PDT 24
Finished Jun 02 12:52:22 PM PDT 24
Peak memory 199584 kb
Host smart-778e9207-5358-4793-ac0d-6df55c438e94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374679437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.374679437
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.900204179
Short name T149
Test name
Test status
Simulation time 68666637637 ps
CPU time 106.5 seconds
Started Jun 02 01:19:46 PM PDT 24
Finished Jun 02 01:21:32 PM PDT 24
Peak memory 200368 kb
Host smart-cfdaaf7c-c0e8-4558-89a8-3ffabff7de70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900204179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.900204179
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1035729659
Short name T31
Test name
Test status
Simulation time 253172797290 ps
CPU time 506.27 seconds
Started Jun 02 01:20:20 PM PDT 24
Finished Jun 02 01:28:46 PM PDT 24
Peak memory 225232 kb
Host smart-2a2c6cfc-e99f-4138-92e0-a0728afca1b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035729659 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1035729659
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.3647458563
Short name T10
Test name
Test status
Simulation time 34574100108 ps
CPU time 451.64 seconds
Started Jun 02 01:14:01 PM PDT 24
Finished Jun 02 01:21:33 PM PDT 24
Peak memory 216276 kb
Host smart-42a98d56-6509-4af6-a5d3-5b2665f2f9cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647458563 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.3647458563
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.4021633990
Short name T29
Test name
Test status
Simulation time 305585055218 ps
CPU time 883.44 seconds
Started Jun 02 01:18:30 PM PDT 24
Finished Jun 02 01:33:14 PM PDT 24
Peak memory 225244 kb
Host smart-4c9e89e9-8dc6-4160-b8d0-7ebc924721af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021633990 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.4021633990
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all.1510413751
Short name T328
Test name
Test status
Simulation time 61458544829 ps
CPU time 61.14 seconds
Started Jun 02 01:19:09 PM PDT 24
Finished Jun 02 01:20:10 PM PDT 24
Peak memory 200284 kb
Host smart-fc0da48f-f331-4451-82de-a5b5cc5372ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510413751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1510413751
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all.2756320011
Short name T281
Test name
Test status
Simulation time 259253753392 ps
CPU time 648.02 seconds
Started Jun 02 01:11:41 PM PDT 24
Finished Jun 02 01:22:30 PM PDT 24
Peak memory 200560 kb
Host smart-df9596eb-496f-449c-8906-8d2d653ae963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756320011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2756320011
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.95870897
Short name T154
Test name
Test status
Simulation time 13159062451 ps
CPU time 8.79 seconds
Started Jun 02 01:20:01 PM PDT 24
Finished Jun 02 01:20:10 PM PDT 24
Peak memory 200268 kb
Host smart-91f1c371-6d15-4a32-adaa-1ebb62128205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95870897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.95870897
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2244892299
Short name T1155
Test name
Test status
Simulation time 88280617867 ps
CPU time 40.55 seconds
Started Jun 02 01:11:14 PM PDT 24
Finished Jun 02 01:11:55 PM PDT 24
Peak memory 200292 kb
Host smart-d32aace5-c270-480f-b910-44074b8554c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244892299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2244892299
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1833892938
Short name T246
Test name
Test status
Simulation time 144375986818 ps
CPU time 253.59 seconds
Started Jun 02 01:21:06 PM PDT 24
Finished Jun 02 01:25:22 PM PDT 24
Peak memory 200308 kb
Host smart-9832cbd6-b569-4287-b342-a34c421ea31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833892938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1833892938
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1511752976
Short name T227
Test name
Test status
Simulation time 131442061235 ps
CPU time 69.6 seconds
Started Jun 02 01:21:12 PM PDT 24
Finished Jun 02 01:22:22 PM PDT 24
Peak memory 200360 kb
Host smart-0ac60eb1-88ef-4fab-ab00-fca9d20c5af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511752976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1511752976
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1016408059
Short name T108
Test name
Test status
Simulation time 41109577176 ps
CPU time 71.27 seconds
Started Jun 02 01:21:55 PM PDT 24
Finished Jun 02 01:23:06 PM PDT 24
Peak memory 200288 kb
Host smart-e9c8f0bb-2558-477f-a579-3c19bfd731db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016408059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1016408059
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.371059327
Short name T172
Test name
Test status
Simulation time 31850054757 ps
CPU time 28.36 seconds
Started Jun 02 01:16:05 PM PDT 24
Finished Jun 02 01:16:34 PM PDT 24
Peak memory 200400 kb
Host smart-732da31b-83db-4e65-978b-6633655bfa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371059327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.371059327
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3517015173
Short name T167
Test name
Test status
Simulation time 141413127599 ps
CPU time 234.02 seconds
Started Jun 02 01:16:21 PM PDT 24
Finished Jun 02 01:20:16 PM PDT 24
Peak memory 200324 kb
Host smart-f8307587-7762-4f8e-82e1-34d5e59be1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517015173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3517015173
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3263025915
Short name T262
Test name
Test status
Simulation time 59601230274 ps
CPU time 49.61 seconds
Started Jun 02 01:21:41 PM PDT 24
Finished Jun 02 01:22:31 PM PDT 24
Peak memory 200340 kb
Host smart-dee5504f-9e69-429c-86a5-ce47acf5a601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263025915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3263025915
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3966912296
Short name T94
Test name
Test status
Simulation time 296941957633 ps
CPU time 884.23 seconds
Started Jun 02 01:16:45 PM PDT 24
Finished Jun 02 01:31:30 PM PDT 24
Peak memory 217036 kb
Host smart-050e69e5-15d6-4d62-8ec4-cc11ef08aa46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966912296 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3966912296
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_perf.528358640
Short name T321
Test name
Test status
Simulation time 24060821701 ps
CPU time 557.25 seconds
Started Jun 02 01:12:30 PM PDT 24
Finished Jun 02 01:21:48 PM PDT 24
Peak memory 200292 kb
Host smart-3ceb1b96-bb00-40b9-8511-4cf2a3b1875f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=528358640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.528358640
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2257667938
Short name T223
Test name
Test status
Simulation time 140085397312 ps
CPU time 45.24 seconds
Started Jun 02 01:20:36 PM PDT 24
Finished Jun 02 01:21:22 PM PDT 24
Peak memory 200360 kb
Host smart-171840cc-fd05-4dbd-89ca-4d7988f1172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257667938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2257667938
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2723247216
Short name T1067
Test name
Test status
Simulation time 103014612743 ps
CPU time 43.69 seconds
Started Jun 02 01:20:46 PM PDT 24
Finished Jun 02 01:21:30 PM PDT 24
Peak memory 200324 kb
Host smart-162f9ef8-ab9d-4fc1-8c81-ee6124b6faeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723247216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2723247216
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3127725588
Short name T280
Test name
Test status
Simulation time 50140081994 ps
CPU time 116.05 seconds
Started Jun 02 01:20:45 PM PDT 24
Finished Jun 02 01:22:41 PM PDT 24
Peak memory 200372 kb
Host smart-01a9aeb5-2d01-4334-bdf5-3b6b98cda238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127725588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3127725588
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.278855215
Short name T931
Test name
Test status
Simulation time 23651513241 ps
CPU time 37 seconds
Started Jun 02 01:21:05 PM PDT 24
Finished Jun 02 01:21:42 PM PDT 24
Peak memory 200432 kb
Host smart-0213e92e-d1d5-401d-961f-8628aec1346d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278855215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.278855215
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3578704640
Short name T171
Test name
Test status
Simulation time 35234672065 ps
CPU time 15.84 seconds
Started Jun 02 01:13:18 PM PDT 24
Finished Jun 02 01:13:34 PM PDT 24
Peak memory 199704 kb
Host smart-39e7d54a-4b3e-4be2-8754-42152217ad30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578704640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3578704640
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.632666578
Short name T242
Test name
Test status
Simulation time 22571249479 ps
CPU time 36.76 seconds
Started Jun 02 01:21:24 PM PDT 24
Finished Jun 02 01:22:01 PM PDT 24
Peak memory 200448 kb
Host smart-2ec08ef4-3d7d-4d3a-96a1-0886e83f10b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632666578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.632666578
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3353375123
Short name T155
Test name
Test status
Simulation time 39076045101 ps
CPU time 16.23 seconds
Started Jun 02 01:22:24 PM PDT 24
Finished Jun 02 01:22:41 PM PDT 24
Peak memory 200292 kb
Host smart-931e2a8b-e040-41aa-85a9-7e83e0b69179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353375123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3353375123
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1496090497
Short name T162
Test name
Test status
Simulation time 35031640023 ps
CPU time 19.52 seconds
Started Jun 02 01:22:30 PM PDT 24
Finished Jun 02 01:22:50 PM PDT 24
Peak memory 200380 kb
Host smart-98f6b5fd-c053-4bee-804a-86244cfdabee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496090497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1496090497
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2072326472
Short name T126
Test name
Test status
Simulation time 34774585986 ps
CPU time 6.14 seconds
Started Jun 02 01:20:07 PM PDT 24
Finished Jun 02 01:20:13 PM PDT 24
Peak memory 200320 kb
Host smart-55ac642a-971e-4873-82f8-968edf55b6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072326472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2072326472
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2820912520
Short name T150
Test name
Test status
Simulation time 87433114505 ps
CPU time 43.04 seconds
Started Jun 02 01:11:14 PM PDT 24
Finished Jun 02 01:11:57 PM PDT 24
Peak memory 200432 kb
Host smart-37d3c251-10ae-4ebd-8445-82e0a73e226f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820912520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2820912520
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2658441520
Short name T695
Test name
Test status
Simulation time 66903491065 ps
CPU time 755.2 seconds
Started Jun 02 01:11:21 PM PDT 24
Finished Jun 02 01:23:56 PM PDT 24
Peak memory 216800 kb
Host smart-9d2f8fbc-57db-40e3-a89b-d854f0639c49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658441520 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2658441520
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2187450649
Short name T780
Test name
Test status
Simulation time 92396869429 ps
CPU time 151.46 seconds
Started Jun 02 01:20:34 PM PDT 24
Finished Jun 02 01:23:06 PM PDT 24
Peak memory 200288 kb
Host smart-356c40fe-053a-4820-aa66-581952249883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187450649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2187450649
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2525124224
Short name T283
Test name
Test status
Simulation time 95534150051 ps
CPU time 304.13 seconds
Started Jun 02 01:20:40 PM PDT 24
Finished Jun 02 01:25:44 PM PDT 24
Peak memory 200416 kb
Host smart-4109ee3c-8f62-4d8c-aee6-939f71093d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525124224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2525124224
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2119456049
Short name T231
Test name
Test status
Simulation time 30471641516 ps
CPU time 11.68 seconds
Started Jun 02 01:20:46 PM PDT 24
Finished Jun 02 01:20:57 PM PDT 24
Peak memory 200204 kb
Host smart-bbe348b5-1d24-4f9f-a011-d9be34a48bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119456049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2119456049
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2562637138
Short name T211
Test name
Test status
Simulation time 54812750116 ps
CPU time 43.26 seconds
Started Jun 02 01:20:52 PM PDT 24
Finished Jun 02 01:21:35 PM PDT 24
Peak memory 200408 kb
Host smart-add0dc50-5291-40b6-8bd1-515bbf42a4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562637138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2562637138
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3161486223
Short name T180
Test name
Test status
Simulation time 202998676896 ps
CPU time 68.69 seconds
Started Jun 02 01:20:58 PM PDT 24
Finished Jun 02 01:22:07 PM PDT 24
Peak memory 200320 kb
Host smart-f0e0278c-cf20-4c6c-99ea-8f2139bcdca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161486223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3161486223
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1739760427
Short name T208
Test name
Test status
Simulation time 31922117176 ps
CPU time 54.85 seconds
Started Jun 02 01:21:19 PM PDT 24
Finished Jun 02 01:22:14 PM PDT 24
Peak memory 200364 kb
Host smart-70327d8c-234f-458f-8440-12dedf27f93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739760427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1739760427
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3605123496
Short name T217
Test name
Test status
Simulation time 123339118956 ps
CPU time 104.71 seconds
Started Jun 02 01:21:17 PM PDT 24
Finished Jun 02 01:23:02 PM PDT 24
Peak memory 200412 kb
Host smart-fc9e8c60-9688-4164-841a-ae5bef3e529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605123496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3605123496
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3355770318
Short name T114
Test name
Test status
Simulation time 138458636319 ps
CPU time 139.47 seconds
Started Jun 02 01:21:27 PM PDT 24
Finished Jun 02 01:23:47 PM PDT 24
Peak memory 200444 kb
Host smart-f5d6bab0-9e3d-418b-99e4-41906954d05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355770318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3355770318
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2667018777
Short name T238
Test name
Test status
Simulation time 9894359747 ps
CPU time 18.17 seconds
Started Jun 02 01:21:40 PM PDT 24
Finished Jun 02 01:21:58 PM PDT 24
Peak memory 200292 kb
Host smart-3d77b5f0-7634-4976-8878-91cad48568f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667018777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2667018777
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2245151417
Short name T144
Test name
Test status
Simulation time 26651207210 ps
CPU time 26.49 seconds
Started Jun 02 01:21:39 PM PDT 24
Finished Jun 02 01:22:06 PM PDT 24
Peak memory 200412 kb
Host smart-efe03809-83e3-4383-a677-507cf771b679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245151417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2245151417
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2165937570
Short name T134
Test name
Test status
Simulation time 41737924904 ps
CPU time 23.04 seconds
Started Jun 02 01:22:00 PM PDT 24
Finished Jun 02 01:22:23 PM PDT 24
Peak memory 200504 kb
Host smart-b6edcfbb-c7d6-4250-bf1a-98c553850cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165937570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2165937570
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3522887725
Short name T233
Test name
Test status
Simulation time 50424689866 ps
CPU time 26.95 seconds
Started Jun 02 01:22:10 PM PDT 24
Finished Jun 02 01:22:38 PM PDT 24
Peak memory 200380 kb
Host smart-5bfedadc-5b4d-494a-a096-1ff555e79d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522887725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3522887725
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1162127590
Short name T237
Test name
Test status
Simulation time 81636952010 ps
CPU time 31.28 seconds
Started Jun 02 01:15:10 PM PDT 24
Finished Jun 02 01:15:41 PM PDT 24
Peak memory 200332 kb
Host smart-40ed1ad9-0a68-48f1-bd7f-3c43eb111722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162127590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1162127590
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2459435776
Short name T235
Test name
Test status
Simulation time 48135390235 ps
CPU time 28.07 seconds
Started Jun 02 01:15:14 PM PDT 24
Finished Jun 02 01:15:42 PM PDT 24
Peak memory 200436 kb
Host smart-205dd0f9-0389-48e4-8dc7-020d02dbf6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459435776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2459435776
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2344178312
Short name T243
Test name
Test status
Simulation time 12209327995 ps
CPU time 24.74 seconds
Started Jun 02 01:22:30 PM PDT 24
Finished Jun 02 01:22:55 PM PDT 24
Peak memory 200416 kb
Host smart-2d72a658-d9cf-47ba-8473-a5d185bf1e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344178312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2344178312
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2427822449
Short name T240
Test name
Test status
Simulation time 20598552857 ps
CPU time 32.36 seconds
Started Jun 02 01:20:20 PM PDT 24
Finished Jun 02 01:20:52 PM PDT 24
Peak memory 200136 kb
Host smart-c1a19270-4a38-47e0-9e1e-d2e57c4ba636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427822449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2427822449
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1789090285
Short name T59
Test name
Test status
Simulation time 51350460 ps
CPU time 0.74 seconds
Started Jun 02 12:52:11 PM PDT 24
Finished Jun 02 12:52:12 PM PDT 24
Peak memory 196464 kb
Host smart-40da60ef-25b1-49d4-ba2a-6a85836e2ae9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789090285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1789090285
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.277350984
Short name T1314
Test name
Test status
Simulation time 217639655 ps
CPU time 2.32 seconds
Started Jun 02 12:52:13 PM PDT 24
Finished Jun 02 12:52:16 PM PDT 24
Peak memory 198080 kb
Host smart-6c0ec46f-2b22-4430-8438-12c4d40d7651
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277350984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.277350984
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3731614671
Short name T1311
Test name
Test status
Simulation time 20561237 ps
CPU time 0.65 seconds
Started Jun 02 12:52:14 PM PDT 24
Finished Jun 02 12:52:16 PM PDT 24
Peak memory 195644 kb
Host smart-68ec363d-7ba4-42a7-85ff-71950f980c6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731614671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3731614671
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3956042272
Short name T1277
Test name
Test status
Simulation time 414887593 ps
CPU time 0.86 seconds
Started Jun 02 12:52:13 PM PDT 24
Finished Jun 02 12:52:15 PM PDT 24
Peak memory 200068 kb
Host smart-e2777c89-ffe2-4694-9886-5bd1ab554acd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956042272 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3956042272
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2047879987
Short name T58
Test name
Test status
Simulation time 11257951 ps
CPU time 0.62 seconds
Started Jun 02 12:52:12 PM PDT 24
Finished Jun 02 12:52:13 PM PDT 24
Peak memory 195652 kb
Host smart-51777d6f-4d06-468b-b7b3-43ab9b144062
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047879987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2047879987
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3415430794
Short name T1279
Test name
Test status
Simulation time 11390535 ps
CPU time 0.59 seconds
Started Jun 02 12:52:14 PM PDT 24
Finished Jun 02 12:52:15 PM PDT 24
Peak memory 194648 kb
Host smart-ba1d0f6c-7f08-4120-b62a-ee2c7df56042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415430794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3415430794
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1856015626
Short name T1259
Test name
Test status
Simulation time 95783915 ps
CPU time 0.65 seconds
Started Jun 02 12:52:17 PM PDT 24
Finished Jun 02 12:52:18 PM PDT 24
Peak memory 194476 kb
Host smart-b1fdb63e-8c42-4521-9f45-b32eb331afb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856015626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1856015626
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1547003187
Short name T1231
Test name
Test status
Simulation time 75554137 ps
CPU time 1.86 seconds
Started Jun 02 12:52:09 PM PDT 24
Finished Jun 02 12:52:12 PM PDT 24
Peak memory 200256 kb
Host smart-71ee4f5b-2f05-44cc-b3c8-9bca3f2e51f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547003187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1547003187
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1326975923
Short name T104
Test name
Test status
Simulation time 281582433 ps
CPU time 1.33 seconds
Started Jun 02 12:52:09 PM PDT 24
Finished Jun 02 12:52:11 PM PDT 24
Peak memory 199416 kb
Host smart-d16d6714-a442-4631-9bde-eba6fd25a918
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326975923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1326975923
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.817062295
Short name T1244
Test name
Test status
Simulation time 64365451 ps
CPU time 0.68 seconds
Started Jun 02 12:52:12 PM PDT 24
Finished Jun 02 12:52:13 PM PDT 24
Peak memory 195720 kb
Host smart-526b26cf-3b99-467a-b096-d641fc57781e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817062295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.817062295
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.804072719
Short name T1199
Test name
Test status
Simulation time 1110707466 ps
CPU time 2.45 seconds
Started Jun 02 12:52:14 PM PDT 24
Finished Jun 02 12:52:17 PM PDT 24
Peak memory 198184 kb
Host smart-4671b6e0-8c50-408b-9f2a-ddfb8949b664
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804072719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.804072719
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.520891968
Short name T1226
Test name
Test status
Simulation time 36450547 ps
CPU time 0.58 seconds
Started Jun 02 12:52:13 PM PDT 24
Finished Jun 02 12:52:14 PM PDT 24
Peak memory 195488 kb
Host smart-eb9d4001-0918-4fb0-843f-7d31e5181219
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520891968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.520891968
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2973648301
Short name T1267
Test name
Test status
Simulation time 39944267 ps
CPU time 1.01 seconds
Started Jun 02 12:52:12 PM PDT 24
Finished Jun 02 12:52:13 PM PDT 24
Peak memory 199996 kb
Host smart-c5bd3f1b-71ed-4bd6-8431-909eaaf04b95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973648301 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2973648301
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2195825668
Short name T1255
Test name
Test status
Simulation time 53689342 ps
CPU time 0.61 seconds
Started Jun 02 12:52:13 PM PDT 24
Finished Jun 02 12:52:14 PM PDT 24
Peak memory 195680 kb
Host smart-419eae85-c1b1-4c8e-b416-229e023cc5a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195825668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2195825668
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2771422279
Short name T1263
Test name
Test status
Simulation time 46910096 ps
CPU time 0.54 seconds
Started Jun 02 12:52:13 PM PDT 24
Finished Jun 02 12:52:14 PM PDT 24
Peak memory 194528 kb
Host smart-64cc656e-7383-427a-b624-248b75781f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771422279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2771422279
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2457268412
Short name T1310
Test name
Test status
Simulation time 70774480 ps
CPU time 0.69 seconds
Started Jun 02 12:52:10 PM PDT 24
Finished Jun 02 12:52:11 PM PDT 24
Peak memory 197076 kb
Host smart-e8588e54-3eca-47fa-8364-76891e73874c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457268412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2457268412
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1824936481
Short name T1234
Test name
Test status
Simulation time 360821643 ps
CPU time 1.72 seconds
Started Jun 02 12:52:17 PM PDT 24
Finished Jun 02 12:52:19 PM PDT 24
Peak memory 200084 kb
Host smart-1f41a9de-4a89-499d-b5e2-0769a5f03bc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824936481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1824936481
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.4014414330
Short name T70
Test name
Test status
Simulation time 153598162 ps
CPU time 0.91 seconds
Started Jun 02 12:52:14 PM PDT 24
Finished Jun 02 12:52:16 PM PDT 24
Peak memory 198988 kb
Host smart-c813d4e6-b003-4ea5-9b26-34d05d2db7f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014414330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.4014414330
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1529536781
Short name T1254
Test name
Test status
Simulation time 101713180 ps
CPU time 0.81 seconds
Started Jun 02 12:52:30 PM PDT 24
Finished Jun 02 12:52:31 PM PDT 24
Peak memory 200136 kb
Host smart-04d05b68-61b8-40b4-9103-051970cc74d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529536781 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1529536781
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.952811275
Short name T1312
Test name
Test status
Simulation time 33575443 ps
CPU time 0.64 seconds
Started Jun 02 12:52:31 PM PDT 24
Finished Jun 02 12:52:32 PM PDT 24
Peak memory 195780 kb
Host smart-13778282-128e-4dcd-91d3-510d711cf063
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952811275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.952811275
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3115420135
Short name T1223
Test name
Test status
Simulation time 13489217 ps
CPU time 0.59 seconds
Started Jun 02 12:52:36 PM PDT 24
Finished Jun 02 12:52:37 PM PDT 24
Peak memory 194564 kb
Host smart-bb51179a-4c05-4e2f-b155-79ef966686ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115420135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3115420135
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1851218329
Short name T1250
Test name
Test status
Simulation time 55542586 ps
CPU time 0.7 seconds
Started Jun 02 12:52:29 PM PDT 24
Finished Jun 02 12:52:30 PM PDT 24
Peak memory 197296 kb
Host smart-f2f47ff3-604a-46cd-a356-75b2d0f771f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851218329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1851218329
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1732613201
Short name T1230
Test name
Test status
Simulation time 187306783 ps
CPU time 1.79 seconds
Started Jun 02 12:52:29 PM PDT 24
Finished Jun 02 12:52:32 PM PDT 24
Peak memory 200440 kb
Host smart-7a850eae-dab6-4345-87c3-a96a5c19aca5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732613201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1732613201
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.281764967
Short name T1300
Test name
Test status
Simulation time 87359794 ps
CPU time 1.27 seconds
Started Jun 02 12:52:30 PM PDT 24
Finished Jun 02 12:52:32 PM PDT 24
Peak memory 199512 kb
Host smart-dfbf873d-d560-489c-91f9-5eb87500b3f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281764967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.281764967
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3127371569
Short name T1240
Test name
Test status
Simulation time 100910091 ps
CPU time 0.81 seconds
Started Jun 02 12:52:29 PM PDT 24
Finished Jun 02 12:52:30 PM PDT 24
Peak memory 199960 kb
Host smart-328ea4f6-4ad5-4c86-9ec1-c7fd12f1a007
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127371569 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3127371569
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2789626471
Short name T1257
Test name
Test status
Simulation time 14860106 ps
CPU time 0.61 seconds
Started Jun 02 12:52:30 PM PDT 24
Finished Jun 02 12:52:31 PM PDT 24
Peak memory 195720 kb
Host smart-d4caccb2-e289-47f0-ad94-58d080b86bea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789626471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2789626471
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1313932787
Short name T1237
Test name
Test status
Simulation time 42170960 ps
CPU time 0.55 seconds
Started Jun 02 12:52:33 PM PDT 24
Finished Jun 02 12:52:34 PM PDT 24
Peak memory 194568 kb
Host smart-680890e5-7052-4069-a4bc-ddb4465d7944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313932787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1313932787
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2727634883
Short name T1299
Test name
Test status
Simulation time 105874566 ps
CPU time 0.74 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:39 PM PDT 24
Peak memory 196620 kb
Host smart-701ccb2d-267c-4ae3-9826-8c310aea5245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727634883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2727634883
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.287085487
Short name T1270
Test name
Test status
Simulation time 211034783 ps
CPU time 2.3 seconds
Started Jun 02 12:52:29 PM PDT 24
Finished Jun 02 12:52:32 PM PDT 24
Peak memory 200300 kb
Host smart-a5d2c777-adff-4213-82e6-3c927d18e44e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287085487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.287085487
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3398693256
Short name T1276
Test name
Test status
Simulation time 182475023 ps
CPU time 1.39 seconds
Started Jun 02 12:52:30 PM PDT 24
Finished Jun 02 12:52:32 PM PDT 24
Peak memory 199396 kb
Host smart-55506e97-f234-4c9c-9f0c-a44d18c2c279
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398693256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3398693256
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.60567398
Short name T1218
Test name
Test status
Simulation time 24273228 ps
CPU time 0.8 seconds
Started Jun 02 12:52:33 PM PDT 24
Finished Jun 02 12:52:34 PM PDT 24
Peak memory 199872 kb
Host smart-e25d4e99-3c7d-42a7-aa74-01db09567bd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60567398 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.60567398
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2721976629
Short name T1182
Test name
Test status
Simulation time 14733189 ps
CPU time 0.57 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:39 PM PDT 24
Peak memory 195596 kb
Host smart-b3f0b4a6-0c05-4620-886c-3b68e4ee1335
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721976629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2721976629
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1638472043
Short name T1243
Test name
Test status
Simulation time 40893567 ps
CPU time 0.55 seconds
Started Jun 02 12:52:34 PM PDT 24
Finished Jun 02 12:52:35 PM PDT 24
Peak memory 194576 kb
Host smart-886a9e3a-4c7a-4e76-a6fa-8f839cb723ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638472043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1638472043
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2458969497
Short name T69
Test name
Test status
Simulation time 120920841 ps
CPU time 0.78 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:40 PM PDT 24
Peak memory 196296 kb
Host smart-4f5c42ee-84f4-44ac-9a88-6ee4050c4ff2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458969497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2458969497
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2646071186
Short name T1192
Test name
Test status
Simulation time 101962564 ps
CPU time 2.03 seconds
Started Jun 02 12:52:37 PM PDT 24
Finished Jun 02 12:52:39 PM PDT 24
Peak memory 200264 kb
Host smart-9e3dde85-6b6f-4bc9-bb0a-9163ace513ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646071186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2646071186
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2488797056
Short name T1297
Test name
Test status
Simulation time 476115470 ps
CPU time 1.32 seconds
Started Jun 02 12:52:31 PM PDT 24
Finished Jun 02 12:52:33 PM PDT 24
Peak memory 199372 kb
Host smart-9b3215b4-56e8-41ac-97a3-023f4d9eb0cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488797056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2488797056
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3727871587
Short name T1289
Test name
Test status
Simulation time 45406976 ps
CPU time 0.7 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:39 PM PDT 24
Peak memory 198436 kb
Host smart-e6c2867e-6c6a-421d-bef8-acf472d5adc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727871587 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3727871587
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3710936634
Short name T1224
Test name
Test status
Simulation time 11399463 ps
CPU time 0.62 seconds
Started Jun 02 12:52:30 PM PDT 24
Finished Jun 02 12:52:31 PM PDT 24
Peak memory 195636 kb
Host smart-b9456f47-4e8f-4514-8f63-5bb416fd7827
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710936634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3710936634
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1189437636
Short name T1241
Test name
Test status
Simulation time 36634401 ps
CPU time 0.59 seconds
Started Jun 02 12:52:30 PM PDT 24
Finished Jun 02 12:52:32 PM PDT 24
Peak memory 194684 kb
Host smart-2ff2ab60-6bc9-4798-a02e-63afaee8bac7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189437636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1189437636
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3717555736
Short name T1261
Test name
Test status
Simulation time 27978427 ps
CPU time 0.65 seconds
Started Jun 02 12:52:33 PM PDT 24
Finished Jun 02 12:52:34 PM PDT 24
Peak memory 196744 kb
Host smart-f0f58e57-f589-4f1d-a850-6e1720898d92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717555736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3717555736
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.574883022
Short name T1247
Test name
Test status
Simulation time 588009633 ps
CPU time 1.63 seconds
Started Jun 02 12:52:32 PM PDT 24
Finished Jun 02 12:52:34 PM PDT 24
Peak memory 200288 kb
Host smart-e3a7ee8e-3cab-4246-a8dc-8b1d55533fe3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574883022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.574883022
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.723868503
Short name T1307
Test name
Test status
Simulation time 74935495 ps
CPU time 0.71 seconds
Started Jun 02 12:52:35 PM PDT 24
Finished Jun 02 12:52:37 PM PDT 24
Peak memory 199240 kb
Host smart-ff5b7ade-e8d1-4259-9e35-296542b0315d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723868503 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.723868503
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1820004297
Short name T1308
Test name
Test status
Simulation time 32503549 ps
CPU time 0.61 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:39 PM PDT 24
Peak memory 195688 kb
Host smart-a5a10d2e-7701-434d-9329-601f1756ecdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820004297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1820004297
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2357020252
Short name T1238
Test name
Test status
Simulation time 51624597 ps
CPU time 0.58 seconds
Started Jun 02 12:52:29 PM PDT 24
Finished Jun 02 12:52:30 PM PDT 24
Peak memory 194632 kb
Host smart-6f344ccd-c08d-4932-b48e-ec875e7503f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357020252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2357020252
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.499170605
Short name T1309
Test name
Test status
Simulation time 15936018 ps
CPU time 0.63 seconds
Started Jun 02 12:52:37 PM PDT 24
Finished Jun 02 12:52:38 PM PDT 24
Peak memory 195852 kb
Host smart-4e7da482-8709-4591-84d8-cc980e8a0094
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499170605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.499170605
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3431909330
Short name T1194
Test name
Test status
Simulation time 82131232 ps
CPU time 1.85 seconds
Started Jun 02 12:52:33 PM PDT 24
Finished Jun 02 12:52:35 PM PDT 24
Peak memory 200316 kb
Host smart-d5f9a313-e1f7-42c6-a9dc-072d8f716b69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431909330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3431909330
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4170145571
Short name T74
Test name
Test status
Simulation time 347021356 ps
CPU time 1.32 seconds
Started Jun 02 12:52:31 PM PDT 24
Finished Jun 02 12:52:33 PM PDT 24
Peak memory 199496 kb
Host smart-9e4610ac-fdf3-4476-99c6-bec4b87dde57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170145571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4170145571
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2346121493
Short name T1203
Test name
Test status
Simulation time 60164783 ps
CPU time 0.71 seconds
Started Jun 02 12:52:44 PM PDT 24
Finished Jun 02 12:52:46 PM PDT 24
Peak memory 197816 kb
Host smart-4bef2cee-58cb-4afa-a991-48a227b041db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346121493 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2346121493
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2220146262
Short name T54
Test name
Test status
Simulation time 20731224 ps
CPU time 0.6 seconds
Started Jun 02 12:52:43 PM PDT 24
Finished Jun 02 12:52:44 PM PDT 24
Peak memory 195704 kb
Host smart-274b5924-bedf-4d0a-b402-31eeb9974c5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220146262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2220146262
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.913883239
Short name T1216
Test name
Test status
Simulation time 12609849 ps
CPU time 0.59 seconds
Started Jun 02 12:52:37 PM PDT 24
Finished Jun 02 12:52:38 PM PDT 24
Peak memory 194596 kb
Host smart-c16462ba-5919-463f-a677-26314f48dd36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913883239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.913883239
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.330197539
Short name T66
Test name
Test status
Simulation time 34415964 ps
CPU time 0.78 seconds
Started Jun 02 12:52:39 PM PDT 24
Finished Jun 02 12:52:40 PM PDT 24
Peak memory 197440 kb
Host smart-c1e5d3e3-0582-435a-a2c6-144a508ce286
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330197539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.330197539
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1405498013
Short name T1251
Test name
Test status
Simulation time 103326701 ps
CPU time 2.05 seconds
Started Jun 02 12:52:37 PM PDT 24
Finished Jun 02 12:52:40 PM PDT 24
Peak memory 200280 kb
Host smart-09b37d5c-a923-44ed-a9f6-2011067de719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405498013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1405498013
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2579765180
Short name T1271
Test name
Test status
Simulation time 277308829 ps
CPU time 0.98 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:40 PM PDT 24
Peak memory 199076 kb
Host smart-c4677e95-af99-4820-b1c0-a01d97fd5b58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579765180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2579765180
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1910215158
Short name T1215
Test name
Test status
Simulation time 19489851 ps
CPU time 0.93 seconds
Started Jun 02 12:52:47 PM PDT 24
Finished Jun 02 12:52:48 PM PDT 24
Peak memory 199984 kb
Host smart-e7a217b2-1129-4fd1-a892-f38b68489892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910215158 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1910215158
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1969948048
Short name T68
Test name
Test status
Simulation time 28486415 ps
CPU time 0.65 seconds
Started Jun 02 12:52:44 PM PDT 24
Finished Jun 02 12:52:46 PM PDT 24
Peak memory 195752 kb
Host smart-f11a97e2-3ea7-47f9-adc0-e8ada15cbb92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969948048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1969948048
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3239698730
Short name T1239
Test name
Test status
Simulation time 89569342 ps
CPU time 0.57 seconds
Started Jun 02 12:52:39 PM PDT 24
Finished Jun 02 12:52:40 PM PDT 24
Peak memory 194612 kb
Host smart-f6c45140-b2de-44e2-a42a-d22415224dc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239698730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3239698730
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1116589768
Short name T1291
Test name
Test status
Simulation time 116295534 ps
CPU time 0.76 seconds
Started Jun 02 12:52:43 PM PDT 24
Finished Jun 02 12:52:45 PM PDT 24
Peak memory 197136 kb
Host smart-44449bce-eb47-4d67-877e-27a464ad2dbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116589768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1116589768
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3229835205
Short name T1296
Test name
Test status
Simulation time 60133359 ps
CPU time 1.35 seconds
Started Jun 02 12:52:44 PM PDT 24
Finished Jun 02 12:52:47 PM PDT 24
Peak memory 200248 kb
Host smart-69e9ee12-f986-4773-a548-7e0cd9756a28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229835205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3229835205
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2000382527
Short name T1298
Test name
Test status
Simulation time 191611150 ps
CPU time 0.96 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:39 PM PDT 24
Peak memory 199224 kb
Host smart-902fb62c-7557-4f73-9241-a101f59e2192
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000382527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2000382527
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4013686540
Short name T1225
Test name
Test status
Simulation time 187903230 ps
CPU time 1.11 seconds
Started Jun 02 12:52:36 PM PDT 24
Finished Jun 02 12:52:38 PM PDT 24
Peak memory 200336 kb
Host smart-46961201-63bc-494d-a420-c7205fa12f59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013686540 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.4013686540
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3758607996
Short name T1305
Test name
Test status
Simulation time 32027309 ps
CPU time 0.58 seconds
Started Jun 02 12:52:44 PM PDT 24
Finished Jun 02 12:52:45 PM PDT 24
Peak memory 195492 kb
Host smart-d5568b63-d0f6-4a50-a437-67ae130f9781
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758607996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3758607996
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3496513913
Short name T1282
Test name
Test status
Simulation time 29631886 ps
CPU time 0.58 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:39 PM PDT 24
Peak memory 194668 kb
Host smart-79404564-6ed7-4017-ada2-bddd3427cedd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496513913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3496513913
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3187567781
Short name T67
Test name
Test status
Simulation time 23183030 ps
CPU time 0.63 seconds
Started Jun 02 12:52:43 PM PDT 24
Finished Jun 02 12:52:44 PM PDT 24
Peak memory 195772 kb
Host smart-66f2d217-665a-4170-90a9-2743a0d77c94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187567781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3187567781
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3301618095
Short name T1198
Test name
Test status
Simulation time 114868404 ps
CPU time 2.23 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:41 PM PDT 24
Peak memory 200312 kb
Host smart-465ad160-7201-4d67-939e-b44d0a8fdda8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301618095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3301618095
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3908015359
Short name T1266
Test name
Test status
Simulation time 301865200 ps
CPU time 1.22 seconds
Started Jun 02 12:52:37 PM PDT 24
Finished Jun 02 12:52:38 PM PDT 24
Peak memory 199256 kb
Host smart-69f49781-8afa-4057-be7e-1665e310de79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908015359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3908015359
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3186585608
Short name T1269
Test name
Test status
Simulation time 321916400 ps
CPU time 0.82 seconds
Started Jun 02 12:52:40 PM PDT 24
Finished Jun 02 12:52:41 PM PDT 24
Peak memory 200104 kb
Host smart-217a1eeb-5cd0-4b12-aeee-f12e0fe7b24f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186585608 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3186585608
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1155297430
Short name T1283
Test name
Test status
Simulation time 14189383 ps
CPU time 0.57 seconds
Started Jun 02 12:52:37 PM PDT 24
Finished Jun 02 12:52:39 PM PDT 24
Peak memory 195496 kb
Host smart-0777a153-fe68-4f71-9a5e-299b2232c262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155297430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1155297430
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1160046361
Short name T1280
Test name
Test status
Simulation time 23548031 ps
CPU time 0.59 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:40 PM PDT 24
Peak memory 194628 kb
Host smart-c9dcda4d-7976-4c32-88cd-78bf283eecf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160046361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1160046361
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.4257113607
Short name T1306
Test name
Test status
Simulation time 29422957 ps
CPU time 0.78 seconds
Started Jun 02 12:52:37 PM PDT 24
Finished Jun 02 12:52:38 PM PDT 24
Peak memory 197304 kb
Host smart-ad7e9695-f0a2-4a78-8605-1aae216b5aaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257113607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.4257113607
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.4018097965
Short name T1202
Test name
Test status
Simulation time 131333236 ps
CPU time 1.89 seconds
Started Jun 02 12:52:37 PM PDT 24
Finished Jun 02 12:52:39 PM PDT 24
Peak memory 200208 kb
Host smart-965848a1-5294-4615-ac7a-df7a29946887
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018097965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.4018097965
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.643813922
Short name T78
Test name
Test status
Simulation time 328034270 ps
CPU time 1.34 seconds
Started Jun 02 12:52:36 PM PDT 24
Finished Jun 02 12:52:38 PM PDT 24
Peak memory 199616 kb
Host smart-b9b1bc57-356c-4d9e-a4f1-0ef837c9597f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643813922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.643813922
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2701683303
Short name T1265
Test name
Test status
Simulation time 260884456 ps
CPU time 1.15 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:40 PM PDT 24
Peak memory 200316 kb
Host smart-2a1cbbc6-eeae-4167-b0ac-8fef1df754f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701683303 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2701683303
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2854055648
Short name T1292
Test name
Test status
Simulation time 47507025 ps
CPU time 0.58 seconds
Started Jun 02 12:52:36 PM PDT 24
Finished Jun 02 12:52:36 PM PDT 24
Peak memory 195624 kb
Host smart-f89eee3f-bfd1-4d74-a1a7-9798e8331c63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854055648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2854055648
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3169515209
Short name T1275
Test name
Test status
Simulation time 36596016 ps
CPU time 0.61 seconds
Started Jun 02 12:52:40 PM PDT 24
Finished Jun 02 12:52:41 PM PDT 24
Peak memory 194616 kb
Host smart-c00b3275-0726-4e01-aeb9-b6e8a15546c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169515209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3169515209
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2843433960
Short name T65
Test name
Test status
Simulation time 20113631 ps
CPU time 0.65 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:40 PM PDT 24
Peak memory 195884 kb
Host smart-167a239b-1852-4f7e-b786-8cc3b5a71513
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843433960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2843433960
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2820980961
Short name T1256
Test name
Test status
Simulation time 37480311 ps
CPU time 1.06 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:40 PM PDT 24
Peak memory 200120 kb
Host smart-a9ec4b3f-4bd8-4f82-b648-6dbe91c75aeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820980961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2820980961
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.267870304
Short name T1313
Test name
Test status
Simulation time 93763281 ps
CPU time 1.04 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:40 PM PDT 24
Peak memory 199308 kb
Host smart-8171bc18-6639-44b8-a364-0acdbee00824
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267870304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.267870304
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.276138669
Short name T55
Test name
Test status
Simulation time 30716070 ps
CPU time 0.8 seconds
Started Jun 02 12:52:14 PM PDT 24
Finished Jun 02 12:52:15 PM PDT 24
Peak memory 196568 kb
Host smart-8e32c69e-469d-4585-a1b5-db76eaf7a2fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276138669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.276138669
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2051682948
Short name T1260
Test name
Test status
Simulation time 129244126 ps
CPU time 1.41 seconds
Started Jun 02 12:52:13 PM PDT 24
Finished Jun 02 12:52:15 PM PDT 24
Peak memory 198096 kb
Host smart-85c8bb35-5a34-43c9-b406-a593c96e5b73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051682948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2051682948
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2111413512
Short name T1229
Test name
Test status
Simulation time 18335421 ps
CPU time 0.61 seconds
Started Jun 02 12:52:13 PM PDT 24
Finished Jun 02 12:52:14 PM PDT 24
Peak memory 195640 kb
Host smart-45cef046-ea19-4141-883b-bb1bc7d0d7a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111413512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2111413512
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4235082628
Short name T1286
Test name
Test status
Simulation time 61079165 ps
CPU time 0.91 seconds
Started Jun 02 12:52:20 PM PDT 24
Finished Jun 02 12:52:21 PM PDT 24
Peak memory 200004 kb
Host smart-522deb16-d770-41be-aa89-f936fd36d974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235082628 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.4235082628
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1407288405
Short name T1285
Test name
Test status
Simulation time 15783201 ps
CPU time 0.55 seconds
Started Jun 02 12:52:15 PM PDT 24
Finished Jun 02 12:52:16 PM PDT 24
Peak memory 194556 kb
Host smart-132c8fed-66d7-4263-8098-e3caf7b8cff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407288405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1407288405
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1529521336
Short name T62
Test name
Test status
Simulation time 27249663 ps
CPU time 0.78 seconds
Started Jun 02 12:52:15 PM PDT 24
Finished Jun 02 12:52:16 PM PDT 24
Peak memory 197408 kb
Host smart-1c938a95-c89a-4079-91d3-b5fdd6d76e8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529521336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1529521336
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.4141868791
Short name T1210
Test name
Test status
Simulation time 41854024 ps
CPU time 2.05 seconds
Started Jun 02 12:52:14 PM PDT 24
Finished Jun 02 12:52:17 PM PDT 24
Peak memory 200444 kb
Host smart-4ea33c4b-34f7-4dd5-84e4-9ca071ffd7e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141868791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4141868791
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1995506596
Short name T1315
Test name
Test status
Simulation time 184088757 ps
CPU time 0.97 seconds
Started Jun 02 12:52:16 PM PDT 24
Finished Jun 02 12:52:18 PM PDT 24
Peak memory 199656 kb
Host smart-e3abfb88-6654-4282-8814-ba406b662f22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995506596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1995506596
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2719283723
Short name T1184
Test name
Test status
Simulation time 15632264 ps
CPU time 0.56 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:39 PM PDT 24
Peak memory 194556 kb
Host smart-0a998e21-ab7b-4253-a054-6e225e323bf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719283723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2719283723
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1099923746
Short name T1201
Test name
Test status
Simulation time 24009113 ps
CPU time 0.6 seconds
Started Jun 02 12:52:45 PM PDT 24
Finished Jun 02 12:52:46 PM PDT 24
Peak memory 194608 kb
Host smart-cdf7f0db-9e40-4b30-aead-2c9eb7b9c555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099923746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1099923746
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.708467407
Short name T1273
Test name
Test status
Simulation time 104463424 ps
CPU time 0.57 seconds
Started Jun 02 12:52:37 PM PDT 24
Finished Jun 02 12:52:38 PM PDT 24
Peak memory 194516 kb
Host smart-03a91304-4073-4ebe-b465-19017fbd7f07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708467407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.708467407
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.557795219
Short name T1197
Test name
Test status
Simulation time 46997808 ps
CPU time 0.59 seconds
Started Jun 02 12:52:36 PM PDT 24
Finished Jun 02 12:52:37 PM PDT 24
Peak memory 194608 kb
Host smart-080e3af1-5b44-4d89-bb3e-c6f92adfbc4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557795219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.557795219
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1260930875
Short name T1293
Test name
Test status
Simulation time 13008166 ps
CPU time 0.56 seconds
Started Jun 02 12:52:38 PM PDT 24
Finished Jun 02 12:52:39 PM PDT 24
Peak memory 194564 kb
Host smart-6e40c6ca-e458-4c5d-a2a0-e58f72421eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260930875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1260930875
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1233350246
Short name T1211
Test name
Test status
Simulation time 22916499 ps
CPU time 0.6 seconds
Started Jun 02 12:52:40 PM PDT 24
Finished Jun 02 12:52:41 PM PDT 24
Peak memory 194684 kb
Host smart-67b7984c-d989-4e79-a318-ca925e696f34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233350246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1233350246
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.529036184
Short name T1262
Test name
Test status
Simulation time 46534664 ps
CPU time 0.58 seconds
Started Jun 02 12:52:44 PM PDT 24
Finished Jun 02 12:52:46 PM PDT 24
Peak memory 194432 kb
Host smart-cb5ca18a-e80b-415e-8a25-38bf058fa2cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529036184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.529036184
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2598142153
Short name T1228
Test name
Test status
Simulation time 12446712 ps
CPU time 0.56 seconds
Started Jun 02 12:52:44 PM PDT 24
Finished Jun 02 12:52:45 PM PDT 24
Peak memory 194612 kb
Host smart-e8c2f339-dd8a-43fa-a8d4-16ba3748cb11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598142153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2598142153
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3271770016
Short name T1204
Test name
Test status
Simulation time 43579723 ps
CPU time 0.55 seconds
Started Jun 02 12:52:42 PM PDT 24
Finished Jun 02 12:52:43 PM PDT 24
Peak memory 194604 kb
Host smart-005a0678-44c7-45f9-8716-5f87a386cf24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271770016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3271770016
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3904609830
Short name T1207
Test name
Test status
Simulation time 40054051 ps
CPU time 0.59 seconds
Started Jun 02 12:52:43 PM PDT 24
Finished Jun 02 12:52:44 PM PDT 24
Peak memory 194648 kb
Host smart-fc80db45-e80d-4c66-9958-68b14233e836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904609830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3904609830
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1016745236
Short name T1235
Test name
Test status
Simulation time 17199627 ps
CPU time 0.75 seconds
Started Jun 02 12:52:22 PM PDT 24
Finished Jun 02 12:52:23 PM PDT 24
Peak memory 196472 kb
Host smart-286625da-d60f-4663-ab9b-99dae561c378
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016745236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1016745236
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3579383080
Short name T1205
Test name
Test status
Simulation time 94401999 ps
CPU time 1.54 seconds
Started Jun 02 12:52:20 PM PDT 24
Finished Jun 02 12:52:22 PM PDT 24
Peak memory 197900 kb
Host smart-985d201d-3dcb-4179-8d39-3fdf45f69737
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579383080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3579383080
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4092982690
Short name T1253
Test name
Test status
Simulation time 19120865 ps
CPU time 0.6 seconds
Started Jun 02 12:52:21 PM PDT 24
Finished Jun 02 12:52:22 PM PDT 24
Peak memory 195644 kb
Host smart-efe8232b-2d70-498c-8368-67c075a19296
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092982690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.4092982690
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2998596068
Short name T1181
Test name
Test status
Simulation time 23428328 ps
CPU time 0.8 seconds
Started Jun 02 12:52:20 PM PDT 24
Finished Jun 02 12:52:21 PM PDT 24
Peak memory 199100 kb
Host smart-90ba9712-2ffe-4e8b-be0b-c9e2cce2f21e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998596068 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2998596068
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3580793946
Short name T60
Test name
Test status
Simulation time 93175168 ps
CPU time 0.56 seconds
Started Jun 02 12:52:19 PM PDT 24
Finished Jun 02 12:52:20 PM PDT 24
Peak memory 195640 kb
Host smart-7e7f891e-50d8-4f87-89f5-7fbdea9baf93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580793946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3580793946
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2884843997
Short name T1258
Test name
Test status
Simulation time 16932115 ps
CPU time 0.61 seconds
Started Jun 02 12:52:22 PM PDT 24
Finished Jun 02 12:52:23 PM PDT 24
Peak memory 194648 kb
Host smart-292e6c10-665a-409a-b5b7-726bbb83078d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884843997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2884843997
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1123162262
Short name T1272
Test name
Test status
Simulation time 122476649 ps
CPU time 0.8 seconds
Started Jun 02 12:52:23 PM PDT 24
Finished Jun 02 12:52:24 PM PDT 24
Peak memory 197180 kb
Host smart-c900e03b-5669-4fe2-b203-84053e39e1f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123162262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1123162262
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3602108506
Short name T1222
Test name
Test status
Simulation time 48849643 ps
CPU time 2.3 seconds
Started Jun 02 12:52:19 PM PDT 24
Finished Jun 02 12:52:22 PM PDT 24
Peak memory 200240 kb
Host smart-78d57a3a-2873-4512-a75c-91b2767229be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602108506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3602108506
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1716350106
Short name T75
Test name
Test status
Simulation time 87783266 ps
CPU time 1.32 seconds
Started Jun 02 12:52:20 PM PDT 24
Finished Jun 02 12:52:22 PM PDT 24
Peak memory 199456 kb
Host smart-71061a28-3aa7-4ed8-a454-681da72f5ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716350106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1716350106
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1767699945
Short name T1264
Test name
Test status
Simulation time 139495823 ps
CPU time 0.56 seconds
Started Jun 02 12:52:44 PM PDT 24
Finished Jun 02 12:52:45 PM PDT 24
Peak memory 194612 kb
Host smart-6bc0f875-fb56-48b9-bb88-55032bb060b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767699945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1767699945
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1465925995
Short name T1213
Test name
Test status
Simulation time 13371384 ps
CPU time 0.57 seconds
Started Jun 02 12:52:50 PM PDT 24
Finished Jun 02 12:52:52 PM PDT 24
Peak memory 194464 kb
Host smart-efdcedc2-4fd1-4168-a4db-acd0d752611b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465925995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1465925995
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3383064750
Short name T1248
Test name
Test status
Simulation time 15366905 ps
CPU time 0.61 seconds
Started Jun 02 12:52:46 PM PDT 24
Finished Jun 02 12:52:47 PM PDT 24
Peak memory 194596 kb
Host smart-ee80cd1e-164b-4584-b16e-d73015a0dc31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383064750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3383064750
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1054809241
Short name T1303
Test name
Test status
Simulation time 11946029 ps
CPU time 0.55 seconds
Started Jun 02 12:52:43 PM PDT 24
Finished Jun 02 12:52:44 PM PDT 24
Peak memory 194556 kb
Host smart-f07764dc-7094-48a1-a9f8-235d89058015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054809241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1054809241
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1550187117
Short name T1290
Test name
Test status
Simulation time 11338417 ps
CPU time 0.58 seconds
Started Jun 02 12:52:43 PM PDT 24
Finished Jun 02 12:52:44 PM PDT 24
Peak memory 194688 kb
Host smart-16df6577-e4ef-4ce5-abc8-1a3c1b4cec4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550187117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1550187117
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1985378922
Short name T1284
Test name
Test status
Simulation time 35511948 ps
CPU time 0.56 seconds
Started Jun 02 12:52:43 PM PDT 24
Finished Jun 02 12:52:44 PM PDT 24
Peak memory 194600 kb
Host smart-35c046f1-3f55-41a0-ac9d-7db65823178e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985378922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1985378922
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3085414226
Short name T1219
Test name
Test status
Simulation time 11020338 ps
CPU time 0.56 seconds
Started Jun 02 12:52:45 PM PDT 24
Finished Jun 02 12:52:46 PM PDT 24
Peak memory 194620 kb
Host smart-e9355a50-bf48-4fe7-a28f-a8dc21f9489b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085414226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3085414226
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1098352586
Short name T1186
Test name
Test status
Simulation time 10425217 ps
CPU time 0.58 seconds
Started Jun 02 12:52:44 PM PDT 24
Finished Jun 02 12:52:45 PM PDT 24
Peak memory 194640 kb
Host smart-3f11de1f-65f4-4446-a039-8410808c82dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098352586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1098352586
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1623885582
Short name T1185
Test name
Test status
Simulation time 16643872 ps
CPU time 0.61 seconds
Started Jun 02 12:52:48 PM PDT 24
Finished Jun 02 12:52:49 PM PDT 24
Peak memory 194624 kb
Host smart-6639ce60-557e-4c16-8fe0-a1eef6d37b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623885582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1623885582
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.4071620053
Short name T1188
Test name
Test status
Simulation time 22426885 ps
CPU time 0.59 seconds
Started Jun 02 12:52:45 PM PDT 24
Finished Jun 02 12:52:46 PM PDT 24
Peak memory 194560 kb
Host smart-5d1aa3dd-db4a-42ea-81c6-47ea0e53d039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071620053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.4071620053
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2967578984
Short name T1287
Test name
Test status
Simulation time 75338881 ps
CPU time 0.66 seconds
Started Jun 02 12:52:19 PM PDT 24
Finished Jun 02 12:52:20 PM PDT 24
Peak memory 194924 kb
Host smart-2965361d-f141-4e56-b7d8-ac4227d57a68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967578984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2967578984
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4291823949
Short name T1268
Test name
Test status
Simulation time 170192052 ps
CPU time 2.51 seconds
Started Jun 02 12:52:19 PM PDT 24
Finished Jun 02 12:52:22 PM PDT 24
Peak memory 198080 kb
Host smart-a26665eb-f2c6-4c53-8358-a942a456e269
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291823949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.4291823949
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.812437604
Short name T1187
Test name
Test status
Simulation time 12356154 ps
CPU time 0.62 seconds
Started Jun 02 12:52:19 PM PDT 24
Finished Jun 02 12:52:21 PM PDT 24
Peak memory 195636 kb
Host smart-f6e3a83e-b7d1-441d-8141-3507da19d7f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812437604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.812437604
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1258909497
Short name T1304
Test name
Test status
Simulation time 81698050 ps
CPU time 0.71 seconds
Started Jun 02 12:52:19 PM PDT 24
Finished Jun 02 12:52:20 PM PDT 24
Peak memory 199080 kb
Host smart-4e9f6b8c-b5b7-4da5-b443-c0062247ea3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258909497 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1258909497
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3379158728
Short name T64
Test name
Test status
Simulation time 52320526 ps
CPU time 0.62 seconds
Started Jun 02 12:52:19 PM PDT 24
Finished Jun 02 12:52:20 PM PDT 24
Peak memory 195712 kb
Host smart-9b75fc52-ed0d-4238-9ffb-62c66326a6a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379158728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3379158728
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2457885340
Short name T1214
Test name
Test status
Simulation time 13474069 ps
CPU time 0.57 seconds
Started Jun 02 12:52:19 PM PDT 24
Finished Jun 02 12:52:20 PM PDT 24
Peak memory 194568 kb
Host smart-d23da0b3-7874-4b88-83cd-827464d2f692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457885340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2457885340
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1946227959
Short name T1301
Test name
Test status
Simulation time 85285086 ps
CPU time 0.65 seconds
Started Jun 02 12:52:19 PM PDT 24
Finished Jun 02 12:52:20 PM PDT 24
Peak memory 195916 kb
Host smart-4e6978e2-fe55-4656-9d89-7e9470067e3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946227959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1946227959
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1142156448
Short name T1180
Test name
Test status
Simulation time 586193048 ps
CPU time 1.91 seconds
Started Jun 02 12:52:22 PM PDT 24
Finished Jun 02 12:52:25 PM PDT 24
Peak memory 200264 kb
Host smart-3088c282-4653-445e-ae58-2578b42f6748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142156448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1142156448
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3898051325
Short name T71
Test name
Test status
Simulation time 46115912 ps
CPU time 0.94 seconds
Started Jun 02 12:52:21 PM PDT 24
Finished Jun 02 12:52:22 PM PDT 24
Peak memory 199184 kb
Host smart-d6656e77-1767-4709-a44d-5cee8dc56fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898051325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3898051325
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2999281624
Short name T1221
Test name
Test status
Simulation time 14599747 ps
CPU time 0.59 seconds
Started Jun 02 12:52:44 PM PDT 24
Finished Jun 02 12:52:45 PM PDT 24
Peak memory 194564 kb
Host smart-33f62921-3779-4424-b220-73b9d8286922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999281624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2999281624
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2928499747
Short name T1206
Test name
Test status
Simulation time 61572438 ps
CPU time 0.64 seconds
Started Jun 02 12:52:45 PM PDT 24
Finished Jun 02 12:52:46 PM PDT 24
Peak memory 194624 kb
Host smart-f780477e-ba54-4bc4-b348-c1be419fc5b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928499747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2928499747
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1306777912
Short name T1212
Test name
Test status
Simulation time 38967036 ps
CPU time 0.57 seconds
Started Jun 02 12:52:46 PM PDT 24
Finished Jun 02 12:52:47 PM PDT 24
Peak memory 194512 kb
Host smart-2504cc00-5088-4d9d-9950-f9cc1e26d2a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306777912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1306777912
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1979356241
Short name T1209
Test name
Test status
Simulation time 13042573 ps
CPU time 0.56 seconds
Started Jun 02 12:52:43 PM PDT 24
Finished Jun 02 12:52:44 PM PDT 24
Peak memory 194600 kb
Host smart-8558b6c0-c1cb-4e6f-b41f-33b7b58881df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979356241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1979356241
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3342309832
Short name T1200
Test name
Test status
Simulation time 13940476 ps
CPU time 0.57 seconds
Started Jun 02 12:52:46 PM PDT 24
Finished Jun 02 12:52:47 PM PDT 24
Peak memory 194684 kb
Host smart-f44a07e1-c547-44b7-88f2-c535659498a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342309832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3342309832
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3727684960
Short name T1281
Test name
Test status
Simulation time 16841268 ps
CPU time 0.59 seconds
Started Jun 02 12:52:44 PM PDT 24
Finished Jun 02 12:52:46 PM PDT 24
Peak memory 194684 kb
Host smart-8c6e803d-b268-477a-9119-0fad12279bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727684960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3727684960
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2697443988
Short name T1278
Test name
Test status
Simulation time 35922265 ps
CPU time 0.54 seconds
Started Jun 02 12:52:45 PM PDT 24
Finished Jun 02 12:52:46 PM PDT 24
Peak memory 194568 kb
Host smart-b40c7b6f-b643-45fd-ac3b-4dd195cace32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697443988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2697443988
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.760662302
Short name T1196
Test name
Test status
Simulation time 23259339 ps
CPU time 0.61 seconds
Started Jun 02 12:52:43 PM PDT 24
Finished Jun 02 12:52:44 PM PDT 24
Peak memory 194532 kb
Host smart-f663e31f-13f1-492b-8b4e-e3e01747743d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760662302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.760662302
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1049435515
Short name T1183
Test name
Test status
Simulation time 14549967 ps
CPU time 0.57 seconds
Started Jun 02 12:52:43 PM PDT 24
Finished Jun 02 12:52:44 PM PDT 24
Peak memory 194860 kb
Host smart-6af6cad4-30ea-4044-a897-b3a70b4d9b29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049435515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1049435515
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.302694030
Short name T1236
Test name
Test status
Simulation time 41014814 ps
CPU time 0.58 seconds
Started Jun 02 12:52:50 PM PDT 24
Finished Jun 02 12:52:51 PM PDT 24
Peak memory 194592 kb
Host smart-26027188-e910-49f2-b066-576a3d013b1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302694030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.302694030
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3905449949
Short name T1220
Test name
Test status
Simulation time 40443180 ps
CPU time 0.87 seconds
Started Jun 02 12:52:25 PM PDT 24
Finished Jun 02 12:52:27 PM PDT 24
Peak memory 199012 kb
Host smart-9e26f59d-76c2-4bbe-a4ed-7f5ea6f04d43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905449949 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3905449949
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.866442357
Short name T53
Test name
Test status
Simulation time 14642520 ps
CPU time 0.59 seconds
Started Jun 02 12:52:18 PM PDT 24
Finished Jun 02 12:52:19 PM PDT 24
Peak memory 195568 kb
Host smart-ae94bfbb-566b-4816-a63e-c9e0bc9a2ff7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866442357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.866442357
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2599181962
Short name T1208
Test name
Test status
Simulation time 12418226 ps
CPU time 0.56 seconds
Started Jun 02 12:52:20 PM PDT 24
Finished Jun 02 12:52:21 PM PDT 24
Peak memory 194596 kb
Host smart-2fc66b13-c4f8-453e-8ba3-17b6c8091d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599181962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2599181962
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1098362793
Short name T1249
Test name
Test status
Simulation time 12701020 ps
CPU time 0.65 seconds
Started Jun 02 12:52:29 PM PDT 24
Finished Jun 02 12:52:30 PM PDT 24
Peak memory 196112 kb
Host smart-c663fbdc-585d-48a4-8b78-1e7af56c9f14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098362793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1098362793
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2115437314
Short name T1193
Test name
Test status
Simulation time 316367343 ps
CPU time 1.79 seconds
Started Jun 02 12:52:20 PM PDT 24
Finished Jun 02 12:52:23 PM PDT 24
Peak memory 200588 kb
Host smart-23cd14f2-4cad-45a5-a779-7b69ec60070e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115437314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2115437314
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2949815587
Short name T1189
Test name
Test status
Simulation time 54892250 ps
CPU time 0.85 seconds
Started Jun 02 12:52:30 PM PDT 24
Finished Jun 02 12:52:32 PM PDT 24
Peak memory 199960 kb
Host smart-84ecac11-9fe4-4e95-a5aa-a46b27c2c27b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949815587 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2949815587
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1639895206
Short name T50
Test name
Test status
Simulation time 15779443 ps
CPU time 0.58 seconds
Started Jun 02 12:52:25 PM PDT 24
Finished Jun 02 12:52:26 PM PDT 24
Peak memory 195628 kb
Host smart-f2fc774f-bd9a-4564-b457-5d7467e7c02c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639895206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1639895206
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2154157610
Short name T1288
Test name
Test status
Simulation time 42134451 ps
CPU time 0.59 seconds
Started Jun 02 12:52:25 PM PDT 24
Finished Jun 02 12:52:26 PM PDT 24
Peak memory 194572 kb
Host smart-bc39bbc4-1749-454c-9eb3-50340ae4b77e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154157610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2154157610
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1901162449
Short name T61
Test name
Test status
Simulation time 25305621 ps
CPU time 0.65 seconds
Started Jun 02 12:52:25 PM PDT 24
Finished Jun 02 12:52:26 PM PDT 24
Peak memory 195100 kb
Host smart-82d6b358-d381-4c0b-9016-2c81804ce5a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901162449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1901162449
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.592776152
Short name T1245
Test name
Test status
Simulation time 293917551 ps
CPU time 1.35 seconds
Started Jun 02 12:52:25 PM PDT 24
Finished Jun 02 12:52:26 PM PDT 24
Peak memory 200308 kb
Host smart-96eb3fce-09ea-4375-8c8b-001350b9d039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592776152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.592776152
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2829543436
Short name T80
Test name
Test status
Simulation time 89943592 ps
CPU time 1.42 seconds
Started Jun 02 12:52:28 PM PDT 24
Finished Jun 02 12:52:30 PM PDT 24
Peak memory 199272 kb
Host smart-502b9065-46b3-40a8-8508-85554472db77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829543436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2829543436
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1123667169
Short name T1274
Test name
Test status
Simulation time 23932209 ps
CPU time 0.75 seconds
Started Jun 02 12:52:24 PM PDT 24
Finished Jun 02 12:52:25 PM PDT 24
Peak memory 199028 kb
Host smart-c6b54df7-b51b-4285-ae85-a87fe9f685b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123667169 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1123667169
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1635011100
Short name T52
Test name
Test status
Simulation time 39345639 ps
CPU time 0.6 seconds
Started Jun 02 12:52:44 PM PDT 24
Finished Jun 02 12:52:45 PM PDT 24
Peak memory 195688 kb
Host smart-e31ba1e8-9ea4-4dca-ae52-45466bb73bf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635011100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1635011100
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.694993972
Short name T1195
Test name
Test status
Simulation time 30557672 ps
CPU time 0.54 seconds
Started Jun 02 12:52:28 PM PDT 24
Finished Jun 02 12:52:29 PM PDT 24
Peak memory 194528 kb
Host smart-36493984-9def-44ef-bb94-5a7b3b741ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694993972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.694993972
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.4008282931
Short name T1246
Test name
Test status
Simulation time 23144119 ps
CPU time 0.68 seconds
Started Jun 02 12:52:25 PM PDT 24
Finished Jun 02 12:52:26 PM PDT 24
Peak memory 194824 kb
Host smart-6a844164-82b0-490f-8522-51c249c79f9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008282931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.4008282931
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3900916957
Short name T1190
Test name
Test status
Simulation time 51919027 ps
CPU time 1.31 seconds
Started Jun 02 12:52:31 PM PDT 24
Finished Jun 02 12:52:33 PM PDT 24
Peak memory 200288 kb
Host smart-b0c84eee-816e-47c3-8401-7bf29813f0a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900916957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3900916957
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3635981917
Short name T79
Test name
Test status
Simulation time 164181346 ps
CPU time 0.97 seconds
Started Jun 02 12:52:30 PM PDT 24
Finished Jun 02 12:52:32 PM PDT 24
Peak memory 199220 kb
Host smart-a0ad7692-8533-4778-bc88-e83f26c90396
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635981917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3635981917
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1883968799
Short name T1233
Test name
Test status
Simulation time 162197487 ps
CPU time 0.76 seconds
Started Jun 02 12:52:25 PM PDT 24
Finished Jun 02 12:52:26 PM PDT 24
Peak memory 198964 kb
Host smart-f419ebbd-0aaf-4b2a-8854-0a2161661843
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883968799 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1883968799
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.964516206
Short name T1294
Test name
Test status
Simulation time 13051568 ps
CPU time 0.6 seconds
Started Jun 02 12:52:27 PM PDT 24
Finished Jun 02 12:52:28 PM PDT 24
Peak memory 195688 kb
Host smart-24a43d19-0904-4f62-8395-2cd835af8c9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964516206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.964516206
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.323523895
Short name T1302
Test name
Test status
Simulation time 44959758 ps
CPU time 0.55 seconds
Started Jun 02 12:52:24 PM PDT 24
Finished Jun 02 12:52:25 PM PDT 24
Peak memory 194608 kb
Host smart-1e5bcdb9-b815-459a-85e0-583c3cdde169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323523895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.323523895
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3264085141
Short name T1242
Test name
Test status
Simulation time 29164450 ps
CPU time 0.61 seconds
Started Jun 02 12:52:30 PM PDT 24
Finished Jun 02 12:52:31 PM PDT 24
Peak memory 195752 kb
Host smart-24b70171-1a87-4545-a13c-4f9bb69da45d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264085141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3264085141
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2082780386
Short name T1217
Test name
Test status
Simulation time 378755483 ps
CPU time 1.96 seconds
Started Jun 02 12:52:26 PM PDT 24
Finished Jun 02 12:52:28 PM PDT 24
Peak memory 200536 kb
Host smart-b7c928b0-da20-4c02-8a44-2275a4114d34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082780386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2082780386
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1203929599
Short name T77
Test name
Test status
Simulation time 42977634 ps
CPU time 0.91 seconds
Started Jun 02 12:52:24 PM PDT 24
Finished Jun 02 12:52:25 PM PDT 24
Peak memory 199088 kb
Host smart-777d9eb6-8044-4d6c-ba8d-e68642a57c34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203929599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1203929599
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2155468218
Short name T1252
Test name
Test status
Simulation time 132537480 ps
CPU time 1.4 seconds
Started Jun 02 12:52:25 PM PDT 24
Finished Jun 02 12:52:27 PM PDT 24
Peak memory 200260 kb
Host smart-be4c9e01-69c7-4a3d-aa36-0253918ee4f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155468218 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2155468218
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1240804225
Short name T63
Test name
Test status
Simulation time 48937498 ps
CPU time 0.68 seconds
Started Jun 02 12:52:26 PM PDT 24
Finished Jun 02 12:52:27 PM PDT 24
Peak memory 195760 kb
Host smart-c45c56df-7917-4754-b4fa-af043268787d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240804225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1240804225
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.4046724930
Short name T1232
Test name
Test status
Simulation time 14575606 ps
CPU time 0.58 seconds
Started Jun 02 12:52:25 PM PDT 24
Finished Jun 02 12:52:26 PM PDT 24
Peak memory 194608 kb
Host smart-6ae757f0-27f6-4442-817a-64d705a61f09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046724930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.4046724930
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.114777565
Short name T1227
Test name
Test status
Simulation time 26663550 ps
CPU time 0.74 seconds
Started Jun 02 12:52:24 PM PDT 24
Finished Jun 02 12:52:25 PM PDT 24
Peak memory 197376 kb
Host smart-c8e6a206-6f5b-43e9-8d5c-ba951d3cd8c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114777565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.114777565
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.4175991707
Short name T1191
Test name
Test status
Simulation time 71209696 ps
CPU time 1.7 seconds
Started Jun 02 12:52:30 PM PDT 24
Finished Jun 02 12:52:32 PM PDT 24
Peak memory 200244 kb
Host smart-a2ff053a-d9f2-4e2b-8721-115da44a6a68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175991707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.4175991707
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3145638122
Short name T72
Test name
Test status
Simulation time 76093988 ps
CPU time 1.32 seconds
Started Jun 02 12:52:24 PM PDT 24
Finished Jun 02 12:52:26 PM PDT 24
Peak memory 199780 kb
Host smart-aa9699e7-3024-4169-84cd-c43bc14c1cc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145638122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3145638122
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2937494895
Short name T692
Test name
Test status
Simulation time 28334875 ps
CPU time 0.57 seconds
Started Jun 02 01:11:14 PM PDT 24
Finished Jun 02 01:11:15 PM PDT 24
Peak memory 194728 kb
Host smart-6e4578b9-df6c-4ec6-a2f7-4bdc6c1faf7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937494895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2937494895
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.4069335934
Short name T118
Test name
Test status
Simulation time 141884044985 ps
CPU time 90.76 seconds
Started Jun 02 01:11:15 PM PDT 24
Finished Jun 02 01:12:46 PM PDT 24
Peak memory 200412 kb
Host smart-10836054-a92b-46ac-883e-ea2e6bee83fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069335934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.4069335934
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.4291667820
Short name T1172
Test name
Test status
Simulation time 26782146135 ps
CPU time 12.4 seconds
Started Jun 02 01:11:15 PM PDT 24
Finished Jun 02 01:11:28 PM PDT 24
Peak memory 200116 kb
Host smart-d73d1b0c-b33e-46c1-8ca0-cc387b05b8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291667820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.4291667820
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1704643116
Short name T784
Test name
Test status
Simulation time 113900646593 ps
CPU time 210.82 seconds
Started Jun 02 01:11:14 PM PDT 24
Finished Jun 02 01:14:46 PM PDT 24
Peak memory 200388 kb
Host smart-72bf305f-9583-4678-869b-0d0733a0f79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704643116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1704643116
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1046765043
Short name T679
Test name
Test status
Simulation time 13945357556 ps
CPU time 5.94 seconds
Started Jun 02 01:11:15 PM PDT 24
Finished Jun 02 01:11:21 PM PDT 24
Peak memory 199600 kb
Host smart-42a2092d-2d7b-4f46-86e9-c3a754fb8af8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046765043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1046765043
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2167594187
Short name T751
Test name
Test status
Simulation time 75569865470 ps
CPU time 237.38 seconds
Started Jun 02 01:11:14 PM PDT 24
Finished Jun 02 01:15:12 PM PDT 24
Peak memory 200532 kb
Host smart-3cc90f48-36ca-4d57-b61f-e3d044d7ed4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167594187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2167594187
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.4259754872
Short name T558
Test name
Test status
Simulation time 5923113669 ps
CPU time 8.87 seconds
Started Jun 02 01:11:14 PM PDT 24
Finished Jun 02 01:11:23 PM PDT 24
Peak memory 200572 kb
Host smart-4d62ffce-06f0-4aad-bc64-3f01eaaec4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259754872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.4259754872
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1371308591
Short name T470
Test name
Test status
Simulation time 18066552168 ps
CPU time 31.54 seconds
Started Jun 02 01:11:14 PM PDT 24
Finished Jun 02 01:11:46 PM PDT 24
Peak memory 198912 kb
Host smart-915fbe8b-fc6f-4d29-be06-950ea5f10320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371308591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1371308591
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2041207607
Short name T373
Test name
Test status
Simulation time 4277677784 ps
CPU time 106.45 seconds
Started Jun 02 01:11:13 PM PDT 24
Finished Jun 02 01:13:00 PM PDT 24
Peak memory 200396 kb
Host smart-2b1e4596-22c7-44b4-b9a9-28114e85279d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041207607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2041207607
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1024669709
Short name T642
Test name
Test status
Simulation time 5500024354 ps
CPU time 33.77 seconds
Started Jun 02 01:11:13 PM PDT 24
Finished Jun 02 01:11:47 PM PDT 24
Peak memory 198492 kb
Host smart-0e31e31e-e86b-4e7f-9087-7c5bf2ff143c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1024669709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1024669709
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1174975229
Short name T1100
Test name
Test status
Simulation time 1768521891 ps
CPU time 3.94 seconds
Started Jun 02 01:11:14 PM PDT 24
Finished Jun 02 01:11:19 PM PDT 24
Peak memory 195752 kb
Host smart-1e3a0766-3757-4e2f-8f12-311b8ff8894b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174975229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1174975229
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.1317847088
Short name T720
Test name
Test status
Simulation time 1036995220 ps
CPU time 1.36 seconds
Started Jun 02 01:11:08 PM PDT 24
Finished Jun 02 01:11:10 PM PDT 24
Peak memory 199096 kb
Host smart-1d2bdab0-53c4-4ec8-a944-3129b5671ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317847088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1317847088
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2567329189
Short name T1045
Test name
Test status
Simulation time 279334480060 ps
CPU time 1562.58 seconds
Started Jun 02 01:11:14 PM PDT 24
Finished Jun 02 01:37:17 PM PDT 24
Peak memory 200344 kb
Host smart-fe87c0ca-6397-43c5-8993-1d76b055414b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567329189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2567329189
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3863377248
Short name T1051
Test name
Test status
Simulation time 44681711542 ps
CPU time 544.54 seconds
Started Jun 02 01:11:14 PM PDT 24
Finished Jun 02 01:20:19 PM PDT 24
Peak memory 217076 kb
Host smart-e95d682d-833c-42e3-90e1-8b95674a6925
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863377248 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3863377248
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2195908791
Short name T918
Test name
Test status
Simulation time 2130670330 ps
CPU time 2.51 seconds
Started Jun 02 01:11:13 PM PDT 24
Finished Jun 02 01:11:16 PM PDT 24
Peak memory 198848 kb
Host smart-84ba4d4d-1441-4a37-be87-ffbb1331ed6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195908791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2195908791
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3209574988
Short name T793
Test name
Test status
Simulation time 58868653713 ps
CPU time 52.63 seconds
Started Jun 02 01:11:05 PM PDT 24
Finished Jun 02 01:11:58 PM PDT 24
Peak memory 200240 kb
Host smart-977336a5-997b-42f8-9880-d825114cccdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209574988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3209574988
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3929222020
Short name T512
Test name
Test status
Simulation time 26588430 ps
CPU time 0.57 seconds
Started Jun 02 01:11:23 PM PDT 24
Finished Jun 02 01:11:24 PM PDT 24
Peak memory 195996 kb
Host smart-19a70fef-74ba-4b51-b8ec-2e10a46e7933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929222020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3929222020
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.849589071
Short name T358
Test name
Test status
Simulation time 19248611473 ps
CPU time 28.61 seconds
Started Jun 02 01:11:14 PM PDT 24
Finished Jun 02 01:11:43 PM PDT 24
Peak memory 200260 kb
Host smart-98532bc2-3c2e-4f30-b887-0b787ee9b3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849589071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.849589071
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3616262348
Short name T6
Test name
Test status
Simulation time 124093015313 ps
CPU time 28.76 seconds
Started Jun 02 01:11:12 PM PDT 24
Finished Jun 02 01:11:41 PM PDT 24
Peak memory 200388 kb
Host smart-d831fc7c-edab-4dba-a7c3-856c6f2d47d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616262348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3616262348
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.1412591618
Short name T1030
Test name
Test status
Simulation time 275015514641 ps
CPU time 392.18 seconds
Started Jun 02 01:11:14 PM PDT 24
Finished Jun 02 01:17:47 PM PDT 24
Peak memory 197392 kb
Host smart-847fbfb6-0820-4127-962d-81a32383421d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412591618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1412591618
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3827317832
Short name T384
Test name
Test status
Simulation time 278630238890 ps
CPU time 97.28 seconds
Started Jun 02 01:11:22 PM PDT 24
Finished Jun 02 01:12:59 PM PDT 24
Peak memory 200372 kb
Host smart-3e356b83-bd46-447b-84ca-fba9f592b5d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3827317832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3827317832
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.759442338
Short name T325
Test name
Test status
Simulation time 5772561056 ps
CPU time 10.78 seconds
Started Jun 02 01:11:23 PM PDT 24
Finished Jun 02 01:11:34 PM PDT 24
Peak memory 200260 kb
Host smart-b510a122-9f5d-4dbb-988e-ff9dbda2a48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759442338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.759442338
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2547326905
Short name T888
Test name
Test status
Simulation time 24358400560 ps
CPU time 23.21 seconds
Started Jun 02 01:11:14 PM PDT 24
Finished Jun 02 01:11:37 PM PDT 24
Peak memory 200500 kb
Host smart-9c1e3c07-ade3-48d7-959e-a5143c73e627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547326905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2547326905
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.507172765
Short name T678
Test name
Test status
Simulation time 16564626178 ps
CPU time 444.7 seconds
Started Jun 02 01:11:22 PM PDT 24
Finished Jun 02 01:18:47 PM PDT 24
Peak memory 200404 kb
Host smart-e7ae7ab0-fdfd-4564-9ccb-c372134bdc0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=507172765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.507172765
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.4091531997
Short name T942
Test name
Test status
Simulation time 6309843850 ps
CPU time 15.01 seconds
Started Jun 02 01:11:15 PM PDT 24
Finished Jun 02 01:11:30 PM PDT 24
Peak memory 198584 kb
Host smart-1fb93e15-3904-4a62-b771-c01eee83400f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4091531997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.4091531997
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1812927674
Short name T750
Test name
Test status
Simulation time 123038158216 ps
CPU time 93.23 seconds
Started Jun 02 01:11:23 PM PDT 24
Finished Jun 02 01:12:57 PM PDT 24
Peak memory 200336 kb
Host smart-821d7532-45d4-415f-b119-31cde70fedf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812927674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1812927674
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2428506096
Short name T722
Test name
Test status
Simulation time 3067204149 ps
CPU time 4.99 seconds
Started Jun 02 01:11:14 PM PDT 24
Finished Jun 02 01:11:19 PM PDT 24
Peak memory 196424 kb
Host smart-5bcb2985-19d4-43a6-94f8-98c850b5d2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428506096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2428506096
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.163926990
Short name T27
Test name
Test status
Simulation time 62751287 ps
CPU time 0.89 seconds
Started Jun 02 01:11:27 PM PDT 24
Finished Jun 02 01:11:28 PM PDT 24
Peak memory 218428 kb
Host smart-01d6e601-1f9a-43ac-b578-bea077625bd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163926990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.163926990
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2214548398
Short name T789
Test name
Test status
Simulation time 269869873 ps
CPU time 1.47 seconds
Started Jun 02 01:11:15 PM PDT 24
Finished Jun 02 01:11:17 PM PDT 24
Peak memory 199076 kb
Host smart-bc42ba1f-48d5-4dcc-a74d-cc0400d25923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214548398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2214548398
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1155704114
Short name T545
Test name
Test status
Simulation time 241676301977 ps
CPU time 481.47 seconds
Started Jun 02 01:11:22 PM PDT 24
Finished Jun 02 01:19:24 PM PDT 24
Peak memory 215992 kb
Host smart-abd153d4-fea5-40d5-805f-3c28c218a131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155704114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1155704114
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2836069372
Short name T805
Test name
Test status
Simulation time 1010500696 ps
CPU time 2.5 seconds
Started Jun 02 01:11:20 PM PDT 24
Finished Jun 02 01:11:23 PM PDT 24
Peak memory 198700 kb
Host smart-37c1c780-2e40-4f0d-9e30-c911de5206f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836069372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2836069372
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3253514647
Short name T383
Test name
Test status
Simulation time 19060500258 ps
CPU time 31.21 seconds
Started Jun 02 01:11:13 PM PDT 24
Finished Jun 02 01:11:44 PM PDT 24
Peak memory 200400 kb
Host smart-2d3a8dc5-2331-4470-bb42-c033fee812da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253514647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3253514647
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3317552670
Short name T497
Test name
Test status
Simulation time 22600852 ps
CPU time 0.56 seconds
Started Jun 02 01:12:30 PM PDT 24
Finished Jun 02 01:12:31 PM PDT 24
Peak memory 195760 kb
Host smart-cef51d9d-1034-479f-b8b1-f5b050d51684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317552670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3317552670
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2499990104
Short name T176
Test name
Test status
Simulation time 174113948954 ps
CPU time 141.75 seconds
Started Jun 02 01:12:24 PM PDT 24
Finished Jun 02 01:14:47 PM PDT 24
Peak memory 200308 kb
Host smart-fbe85815-1357-41c0-98bb-335570870f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499990104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2499990104
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.4129327097
Short name T865
Test name
Test status
Simulation time 97381147817 ps
CPU time 69.17 seconds
Started Jun 02 01:12:23 PM PDT 24
Finished Jun 02 01:13:33 PM PDT 24
Peak memory 200324 kb
Host smart-e685d843-6346-4c59-8a3e-4d64d7c83775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129327097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.4129327097
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1046651060
Short name T190
Test name
Test status
Simulation time 10097848764 ps
CPU time 17.29 seconds
Started Jun 02 01:12:23 PM PDT 24
Finished Jun 02 01:12:40 PM PDT 24
Peak memory 200308 kb
Host smart-86247435-78f1-4ffb-b4d1-77eda94bb995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046651060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1046651060
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1767913675
Short name T1107
Test name
Test status
Simulation time 15463962339 ps
CPU time 6.88 seconds
Started Jun 02 01:12:25 PM PDT 24
Finished Jun 02 01:12:32 PM PDT 24
Peak memory 198780 kb
Host smart-dd24b142-0edf-4f75-af2a-7d117786ec96
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767913675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1767913675
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1937845660
Short name T927
Test name
Test status
Simulation time 142249229413 ps
CPU time 411.68 seconds
Started Jun 02 01:12:30 PM PDT 24
Finished Jun 02 01:19:22 PM PDT 24
Peak memory 200356 kb
Host smart-2d53b726-8502-45af-8d3f-559f85dd50b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937845660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1937845660
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.4158097810
Short name T1068
Test name
Test status
Simulation time 4178554284 ps
CPU time 9.21 seconds
Started Jun 02 01:12:31 PM PDT 24
Finished Jun 02 01:12:40 PM PDT 24
Peak memory 199904 kb
Host smart-ec8f6b37-3a4e-4d71-91c8-960e7d76e293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158097810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.4158097810
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.4145589548
Short name T739
Test name
Test status
Simulation time 162106016894 ps
CPU time 221.11 seconds
Started Jun 02 01:12:24 PM PDT 24
Finished Jun 02 01:16:05 PM PDT 24
Peak memory 199260 kb
Host smart-d9f1f7fa-3287-4de3-9c79-db0b90b7ea9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145589548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.4145589548
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.984243616
Short name T902
Test name
Test status
Simulation time 1695113197 ps
CPU time 3.44 seconds
Started Jun 02 01:12:22 PM PDT 24
Finished Jun 02 01:12:26 PM PDT 24
Peak memory 199400 kb
Host smart-8beaeee7-5945-40af-bd5f-bfdd97caa88d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=984243616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.984243616
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2499481104
Short name T747
Test name
Test status
Simulation time 10850884733 ps
CPU time 24.5 seconds
Started Jun 02 01:12:29 PM PDT 24
Finished Jun 02 01:12:54 PM PDT 24
Peak memory 200384 kb
Host smart-4a29a7f3-a657-46d8-b04a-41dc0c90c194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499481104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2499481104
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1388047491
Short name T601
Test name
Test status
Simulation time 1750354460 ps
CPU time 3.45 seconds
Started Jun 02 01:12:22 PM PDT 24
Finished Jun 02 01:12:26 PM PDT 24
Peak memory 195744 kb
Host smart-ee63d47e-e473-471b-a749-38ee642117ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388047491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1388047491
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3664324675
Short name T312
Test name
Test status
Simulation time 5757653352 ps
CPU time 11.61 seconds
Started Jun 02 01:12:24 PM PDT 24
Finished Jun 02 01:12:36 PM PDT 24
Peak memory 200400 kb
Host smart-af59c6e5-42fb-4cce-9c0c-f010f6072575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664324675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3664324675
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.4219710003
Short name T774
Test name
Test status
Simulation time 442110002455 ps
CPU time 374.85 seconds
Started Jun 02 01:12:30 PM PDT 24
Finished Jun 02 01:18:45 PM PDT 24
Peak memory 216840 kb
Host smart-f346153c-58cc-4f8b-9167-fcb0910e1a35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219710003 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.4219710003
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1131954844
Short name T406
Test name
Test status
Simulation time 1072244761 ps
CPU time 1.97 seconds
Started Jun 02 01:12:29 PM PDT 24
Finished Jun 02 01:12:31 PM PDT 24
Peak memory 198760 kb
Host smart-dcdcd1df-552c-4c33-a2f6-153820bc8364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131954844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1131954844
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.569901454
Short name T1103
Test name
Test status
Simulation time 15103233650 ps
CPU time 29.95 seconds
Started Jun 02 01:12:24 PM PDT 24
Finished Jun 02 01:12:54 PM PDT 24
Peak memory 200412 kb
Host smart-7b66ef22-5ea8-48b6-a1ea-ec74ef3de653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569901454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.569901454
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.134710691
Short name T540
Test name
Test status
Simulation time 92762233239 ps
CPU time 63.71 seconds
Started Jun 02 01:20:34 PM PDT 24
Finished Jun 02 01:21:38 PM PDT 24
Peak memory 200320 kb
Host smart-56503e9c-a76a-4da0-8e54-d0d5c3675563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134710691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.134710691
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1225811929
Short name T372
Test name
Test status
Simulation time 76126035381 ps
CPU time 29.25 seconds
Started Jun 02 01:20:36 PM PDT 24
Finished Jun 02 01:21:06 PM PDT 24
Peak memory 198700 kb
Host smart-ce3b795f-5e04-46f4-93d4-cbfe9708179e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225811929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1225811929
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3523661664
Short name T266
Test name
Test status
Simulation time 18038075021 ps
CPU time 32.64 seconds
Started Jun 02 01:20:34 PM PDT 24
Finished Jun 02 01:21:07 PM PDT 24
Peak memory 200320 kb
Host smart-b1cff7b1-04f5-4472-a6eb-413af219133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523661664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3523661664
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1363794348
Short name T143
Test name
Test status
Simulation time 69177711710 ps
CPU time 18.97 seconds
Started Jun 02 01:20:36 PM PDT 24
Finished Jun 02 01:20:56 PM PDT 24
Peak memory 200388 kb
Host smart-518bc2b4-26e4-483b-8a39-475adfa88558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363794348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1363794348
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1021128302
Short name T1151
Test name
Test status
Simulation time 178419350295 ps
CPU time 355.98 seconds
Started Jun 02 01:20:32 PM PDT 24
Finished Jun 02 01:26:28 PM PDT 24
Peak memory 200384 kb
Host smart-0dcb4390-be83-4dd1-83f3-ee81bc2faf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021128302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1021128302
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2135494744
Short name T1016
Test name
Test status
Simulation time 149445372406 ps
CPU time 76.83 seconds
Started Jun 02 01:20:35 PM PDT 24
Finished Jun 02 01:21:53 PM PDT 24
Peak memory 200364 kb
Host smart-780b3120-e04f-4d90-bc83-0914f9267918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135494744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2135494744
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1454057337
Short name T125
Test name
Test status
Simulation time 73355366077 ps
CPU time 57.87 seconds
Started Jun 02 01:20:38 PM PDT 24
Finished Jun 02 01:21:36 PM PDT 24
Peak memory 200404 kb
Host smart-2b55eec0-5acf-49dc-9cce-f02a9b9b60cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454057337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1454057337
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1758781542
Short name T212
Test name
Test status
Simulation time 54651711750 ps
CPU time 16.49 seconds
Started Jun 02 01:20:39 PM PDT 24
Finished Jun 02 01:20:56 PM PDT 24
Peak memory 200364 kb
Host smart-b4d0899d-0b91-44e5-97e5-4b0ab78b7490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758781542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1758781542
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.287414473
Short name T860
Test name
Test status
Simulation time 12622719 ps
CPU time 0.56 seconds
Started Jun 02 01:12:45 PM PDT 24
Finished Jun 02 01:12:45 PM PDT 24
Peak memory 195776 kb
Host smart-09990353-cd4c-464b-95b6-33379762c908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287414473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.287414473
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2750504780
Short name T107
Test name
Test status
Simulation time 152120329167 ps
CPU time 310.76 seconds
Started Jun 02 01:12:31 PM PDT 24
Finished Jun 02 01:17:42 PM PDT 24
Peak memory 200356 kb
Host smart-4c11b8f2-7125-4952-8393-58edbd1fedef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750504780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2750504780
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.169644807
Short name T423
Test name
Test status
Simulation time 68263201424 ps
CPU time 58.4 seconds
Started Jun 02 01:12:30 PM PDT 24
Finished Jun 02 01:13:29 PM PDT 24
Peak memory 200328 kb
Host smart-cdf45c47-879c-4642-9629-26f34c8e691c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169644807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.169644807
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2142838264
Short name T298
Test name
Test status
Simulation time 85862696500 ps
CPU time 39.16 seconds
Started Jun 02 01:12:30 PM PDT 24
Finished Jun 02 01:13:09 PM PDT 24
Peak memory 200412 kb
Host smart-9ebe69be-7be1-48ba-ae1e-3ea2527111a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142838264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2142838264
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2090232694
Short name T468
Test name
Test status
Simulation time 73106671389 ps
CPU time 36.15 seconds
Started Jun 02 01:12:39 PM PDT 24
Finished Jun 02 01:13:15 PM PDT 24
Peak memory 200204 kb
Host smart-345f17e1-cdeb-4c33-a3a9-ba80e4225a44
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090232694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2090232694
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.342054761
Short name T509
Test name
Test status
Simulation time 94420414504 ps
CPU time 235.94 seconds
Started Jun 02 01:12:36 PM PDT 24
Finished Jun 02 01:16:33 PM PDT 24
Peak memory 200256 kb
Host smart-7920cfa4-bd86-4a18-b95c-3b01c1358c13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=342054761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.342054761
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2775903652
Short name T599
Test name
Test status
Simulation time 7472031406 ps
CPU time 12.72 seconds
Started Jun 02 01:12:40 PM PDT 24
Finished Jun 02 01:12:53 PM PDT 24
Peak memory 199364 kb
Host smart-b570d9bd-a2b1-45bd-9e03-f49318442bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775903652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2775903652
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3686536332
Short name T557
Test name
Test status
Simulation time 121923440047 ps
CPU time 129.94 seconds
Started Jun 02 01:12:39 PM PDT 24
Finished Jun 02 01:14:50 PM PDT 24
Peak memory 208344 kb
Host smart-c4cb294c-879d-4e10-bcb7-7cec169be055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686536332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3686536332
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.4102535207
Short name T477
Test name
Test status
Simulation time 12298808732 ps
CPU time 103.88 seconds
Started Jun 02 01:12:38 PM PDT 24
Finished Jun 02 01:14:22 PM PDT 24
Peak memory 200384 kb
Host smart-95dc7816-2cb6-4c1c-a450-fcd54cabcd98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102535207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.4102535207
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.4199153711
Short name T932
Test name
Test status
Simulation time 2726984729 ps
CPU time 5.64 seconds
Started Jun 02 01:12:30 PM PDT 24
Finished Jun 02 01:12:37 PM PDT 24
Peak memory 198656 kb
Host smart-5195ee29-ddc2-4017-9665-167465b3ef0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199153711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.4199153711
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.83550010
Short name T556
Test name
Test status
Simulation time 112685851082 ps
CPU time 67.98 seconds
Started Jun 02 01:12:35 PM PDT 24
Finished Jun 02 01:13:44 PM PDT 24
Peak memory 200368 kb
Host smart-7e13c0ec-a328-4b6a-9090-2b06d811c8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83550010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.83550010
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3497342826
Short name T297
Test name
Test status
Simulation time 2953132010 ps
CPU time 4.9 seconds
Started Jun 02 01:12:40 PM PDT 24
Finished Jun 02 01:12:46 PM PDT 24
Peak memory 196380 kb
Host smart-883c6411-b6eb-4e5d-997c-2e5846e59a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497342826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3497342826
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3202735330
Short name T369
Test name
Test status
Simulation time 305636078 ps
CPU time 1.11 seconds
Started Jun 02 01:12:31 PM PDT 24
Finished Jun 02 01:12:33 PM PDT 24
Peak memory 198716 kb
Host smart-07ee9aa0-1b44-48b7-af8a-874d1bdc4c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202735330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3202735330
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.704391535
Short name T1112
Test name
Test status
Simulation time 65069450107 ps
CPU time 185.22 seconds
Started Jun 02 01:12:42 PM PDT 24
Finished Jun 02 01:15:48 PM PDT 24
Peak memory 200336 kb
Host smart-f01895e2-0926-4622-ac1c-1339a1b27097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704391535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.704391535
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.4258874260
Short name T221
Test name
Test status
Simulation time 190466534174 ps
CPU time 570.09 seconds
Started Jun 02 01:12:37 PM PDT 24
Finished Jun 02 01:22:08 PM PDT 24
Peak memory 225284 kb
Host smart-fcbf8a58-ca00-4e4a-b852-5af0467ec874
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258874260 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.4258874260
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3623623155
Short name T1061
Test name
Test status
Simulation time 3707721757 ps
CPU time 1.44 seconds
Started Jun 02 01:12:39 PM PDT 24
Finished Jun 02 01:12:41 PM PDT 24
Peak memory 198800 kb
Host smart-736192d8-3bc5-4959-a8a1-cd179a9e5626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623623155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3623623155
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2262024182
Short name T907
Test name
Test status
Simulation time 122517077281 ps
CPU time 62.23 seconds
Started Jun 02 01:12:30 PM PDT 24
Finished Jun 02 01:13:32 PM PDT 24
Peak memory 200400 kb
Host smart-a8794cd5-c198-4395-83d6-907d0b529073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262024182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2262024182
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1841004941
Short name T200
Test name
Test status
Simulation time 33122571019 ps
CPU time 35.87 seconds
Started Jun 02 01:20:39 PM PDT 24
Finished Jun 02 01:21:16 PM PDT 24
Peak memory 200380 kb
Host smart-3446e6af-13b8-463c-911a-9f441e2c0512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841004941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1841004941
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.4060800632
Short name T716
Test name
Test status
Simulation time 69057097197 ps
CPU time 28.42 seconds
Started Jun 02 01:20:40 PM PDT 24
Finished Jun 02 01:21:09 PM PDT 24
Peak memory 200420 kb
Host smart-4b3f7323-ee7d-4ab8-ba1a-dc4d589f7e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060800632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.4060800632
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.742261329
Short name T1012
Test name
Test status
Simulation time 122313857051 ps
CPU time 237.77 seconds
Started Jun 02 01:20:39 PM PDT 24
Finished Jun 02 01:24:37 PM PDT 24
Peak memory 200360 kb
Host smart-ed4ab6cb-f9d0-475c-905d-367a77920f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742261329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.742261329
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3986192162
Short name T187
Test name
Test status
Simulation time 35998085424 ps
CPU time 74.4 seconds
Started Jun 02 01:20:45 PM PDT 24
Finished Jun 02 01:21:59 PM PDT 24
Peak memory 200364 kb
Host smart-1a63641f-178a-4ca1-bfce-a14b4f88d258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986192162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3986192162
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1772877470
Short name T858
Test name
Test status
Simulation time 18365018422 ps
CPU time 34.81 seconds
Started Jun 02 01:20:46 PM PDT 24
Finished Jun 02 01:21:21 PM PDT 24
Peak memory 200312 kb
Host smart-5524d5dc-b2fe-42e0-913c-592f1c82a074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772877470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1772877470
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1755941776
Short name T462
Test name
Test status
Simulation time 43226629889 ps
CPU time 18.64 seconds
Started Jun 02 01:20:46 PM PDT 24
Finished Jun 02 01:21:05 PM PDT 24
Peak memory 200420 kb
Host smart-682efd5c-95bf-4b1b-97da-5eebb5d902a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755941776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1755941776
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1754608472
Short name T1137
Test name
Test status
Simulation time 117129896 ps
CPU time 0.56 seconds
Started Jun 02 01:12:51 PM PDT 24
Finished Jun 02 01:12:52 PM PDT 24
Peak memory 195864 kb
Host smart-026551ee-7c13-46d3-966d-2efd4d0c1c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754608472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1754608472
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3084169480
Short name T753
Test name
Test status
Simulation time 207787214925 ps
CPU time 425.5 seconds
Started Jun 02 01:12:45 PM PDT 24
Finished Jun 02 01:19:51 PM PDT 24
Peak memory 200368 kb
Host smart-a48c6938-95a7-436a-a06b-0affd58de5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084169480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3084169480
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.27861830
Short name T1119
Test name
Test status
Simulation time 140584072935 ps
CPU time 113.31 seconds
Started Jun 02 01:12:45 PM PDT 24
Finished Jun 02 01:14:39 PM PDT 24
Peak memory 200332 kb
Host smart-205ece3b-589e-4078-960e-8ae87c4eed51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27861830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.27861830
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1680550950
Short name T727
Test name
Test status
Simulation time 31789416702 ps
CPU time 44.26 seconds
Started Jun 02 01:12:44 PM PDT 24
Finished Jun 02 01:13:29 PM PDT 24
Peak memory 200400 kb
Host smart-ac597798-6008-4dfc-ba4e-91623d849a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680550950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1680550950
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.798361339
Short name T681
Test name
Test status
Simulation time 40291394859 ps
CPU time 31.37 seconds
Started Jun 02 01:12:52 PM PDT 24
Finished Jun 02 01:13:23 PM PDT 24
Peak memory 200520 kb
Host smart-3581e76a-b555-4b9f-b012-54cc2695ff1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798361339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.798361339
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.464479986
Short name T969
Test name
Test status
Simulation time 83031101220 ps
CPU time 279.77 seconds
Started Jun 02 01:12:51 PM PDT 24
Finished Jun 02 01:17:31 PM PDT 24
Peak memory 200352 kb
Host smart-aa33ca56-8e98-4d31-89ba-75f30b8be114
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=464479986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.464479986
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.4077921350
Short name T494
Test name
Test status
Simulation time 3963976636 ps
CPU time 4.86 seconds
Started Jun 02 01:12:53 PM PDT 24
Finished Jun 02 01:12:58 PM PDT 24
Peak memory 199768 kb
Host smart-ad39e258-532a-4d78-821e-e7b3cecb06a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077921350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.4077921350
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1231559491
Short name T620
Test name
Test status
Simulation time 39655718989 ps
CPU time 67.95 seconds
Started Jun 02 01:12:51 PM PDT 24
Finished Jun 02 01:13:59 PM PDT 24
Peak memory 200544 kb
Host smart-a90c6052-65fa-435a-acf4-a9ae96c482a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231559491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1231559491
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3444122948
Short name T851
Test name
Test status
Simulation time 18329946918 ps
CPU time 517.05 seconds
Started Jun 02 01:12:51 PM PDT 24
Finished Jun 02 01:21:28 PM PDT 24
Peak memory 200396 kb
Host smart-686638d5-1deb-4fdc-88dd-b1edb408a31c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3444122948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3444122948
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.4000772986
Short name T828
Test name
Test status
Simulation time 4893474563 ps
CPU time 37.59 seconds
Started Jun 02 01:12:44 PM PDT 24
Finished Jun 02 01:13:22 PM PDT 24
Peak memory 199448 kb
Host smart-f2b0b367-fd75-42da-9571-4b7436733351
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4000772986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.4000772986
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.973706827
Short name T957
Test name
Test status
Simulation time 211968464030 ps
CPU time 100.26 seconds
Started Jun 02 01:12:50 PM PDT 24
Finished Jun 02 01:14:31 PM PDT 24
Peak memory 200236 kb
Host smart-65aef531-1f65-4f76-8f15-2ce310b1f69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973706827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.973706827
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1088258941
Short name T21
Test name
Test status
Simulation time 64490109474 ps
CPU time 21.7 seconds
Started Jun 02 01:12:51 PM PDT 24
Finished Jun 02 01:13:13 PM PDT 24
Peak memory 196380 kb
Host smart-67569f60-b59c-4956-84c5-079e3855ce2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088258941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1088258941
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3062227637
Short name T613
Test name
Test status
Simulation time 743071566 ps
CPU time 1.49 seconds
Started Jun 02 01:12:44 PM PDT 24
Finished Jun 02 01:12:46 PM PDT 24
Peak memory 199116 kb
Host smart-aa75c08e-f9ed-40e2-b603-95cae0d3cf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062227637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3062227637
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.891196697
Short name T978
Test name
Test status
Simulation time 119584633148 ps
CPU time 560.73 seconds
Started Jun 02 01:12:50 PM PDT 24
Finished Jun 02 01:22:11 PM PDT 24
Peak memory 211504 kb
Host smart-c991b407-d640-46c2-806b-ad4f6367a1e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891196697 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.891196697
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1171491092
Short name T856
Test name
Test status
Simulation time 712434062 ps
CPU time 1.35 seconds
Started Jun 02 01:12:50 PM PDT 24
Finished Jun 02 01:12:52 PM PDT 24
Peak memory 197504 kb
Host smart-2e135ccb-001e-468d-8a86-fce953ea37c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171491092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1171491092
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.199481693
Short name T623
Test name
Test status
Simulation time 20901140756 ps
CPU time 19.27 seconds
Started Jun 02 01:12:45 PM PDT 24
Finished Jun 02 01:13:05 PM PDT 24
Peak memory 200364 kb
Host smart-06017efc-9be4-4214-86b0-aa241cc77774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199481693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.199481693
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1148922623
Short name T376
Test name
Test status
Simulation time 176077425923 ps
CPU time 78.02 seconds
Started Jun 02 01:20:45 PM PDT 24
Finished Jun 02 01:22:03 PM PDT 24
Peak memory 200348 kb
Host smart-242e81df-030a-44ed-863f-718625a74fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148922623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1148922623
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.365286482
Short name T1130
Test name
Test status
Simulation time 53375182042 ps
CPU time 41.83 seconds
Started Jun 02 01:20:45 PM PDT 24
Finished Jun 02 01:21:27 PM PDT 24
Peak memory 200340 kb
Host smart-1ce3610d-959f-43c5-b803-644874142f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365286482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.365286482
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1106283725
Short name T843
Test name
Test status
Simulation time 123037603981 ps
CPU time 234.34 seconds
Started Jun 02 01:20:52 PM PDT 24
Finished Jun 02 01:24:46 PM PDT 24
Peak memory 200144 kb
Host smart-ae3e6d1c-e508-4a55-9aca-573384188570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106283725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1106283725
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.4015799605
Short name T826
Test name
Test status
Simulation time 7503735431 ps
CPU time 13.37 seconds
Started Jun 02 01:20:51 PM PDT 24
Finished Jun 02 01:21:05 PM PDT 24
Peak memory 200416 kb
Host smart-499d5b4a-6eed-4795-9a1d-fa86f1866adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015799605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.4015799605
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1259702144
Short name T1047
Test name
Test status
Simulation time 24563056242 ps
CPU time 52.55 seconds
Started Jun 02 01:20:52 PM PDT 24
Finished Jun 02 01:21:45 PM PDT 24
Peak memory 200340 kb
Host smart-bc78c48a-3978-49d5-a9b9-edd6cff507b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259702144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1259702144
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.175429121
Short name T197
Test name
Test status
Simulation time 84213233751 ps
CPU time 21.4 seconds
Started Jun 02 01:20:52 PM PDT 24
Finished Jun 02 01:21:14 PM PDT 24
Peak memory 200432 kb
Host smart-3d95f511-0b05-42ca-8faa-7e410da65127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175429121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.175429121
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3605108553
Short name T616
Test name
Test status
Simulation time 59947548201 ps
CPU time 29.95 seconds
Started Jun 02 01:20:52 PM PDT 24
Finished Jun 02 01:21:22 PM PDT 24
Peak memory 200352 kb
Host smart-7adcee53-6514-484d-9f5c-7b5dfdc4fed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605108553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3605108553
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3711107689
Short name T189
Test name
Test status
Simulation time 115197213610 ps
CPU time 225.69 seconds
Started Jun 02 01:20:52 PM PDT 24
Finished Jun 02 01:24:38 PM PDT 24
Peak memory 200260 kb
Host smart-bbfd60b3-e055-4219-a86d-1bfc940d4307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711107689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3711107689
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2588819179
Short name T435
Test name
Test status
Simulation time 16032759 ps
CPU time 0.58 seconds
Started Jun 02 01:13:07 PM PDT 24
Finished Jun 02 01:13:08 PM PDT 24
Peak memory 195768 kb
Host smart-4e069d30-cb52-45f3-a8ff-dbb20d8ac44c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588819179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2588819179
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2591494145
Short name T658
Test name
Test status
Simulation time 33457515846 ps
CPU time 13.21 seconds
Started Jun 02 01:12:58 PM PDT 24
Finished Jun 02 01:13:11 PM PDT 24
Peak memory 200308 kb
Host smart-4857b018-9ba3-4406-8612-62c8b3445e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591494145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2591494145
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3502544757
Short name T949
Test name
Test status
Simulation time 86424904565 ps
CPU time 30.85 seconds
Started Jun 02 01:13:00 PM PDT 24
Finished Jun 02 01:13:31 PM PDT 24
Peak memory 200060 kb
Host smart-a849a6c8-bc40-421d-99e5-5db46e269777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502544757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3502544757
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1777927224
Short name T810
Test name
Test status
Simulation time 56959620309 ps
CPU time 97.19 seconds
Started Jun 02 01:12:58 PM PDT 24
Finished Jun 02 01:14:36 PM PDT 24
Peak memory 200376 kb
Host smart-a5a99de5-99eb-4e20-b45e-9679d6e386a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777927224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1777927224
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2756001136
Short name T315
Test name
Test status
Simulation time 264719467531 ps
CPU time 408.06 seconds
Started Jun 02 01:12:58 PM PDT 24
Finished Jun 02 01:19:47 PM PDT 24
Peak memory 199076 kb
Host smart-888ff397-c5a2-43ee-8fc1-7c05c9bf4d3b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756001136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2756001136
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_loopback.1026982083
Short name T1064
Test name
Test status
Simulation time 9289938327 ps
CPU time 7.09 seconds
Started Jun 02 01:12:58 PM PDT 24
Finished Jun 02 01:13:05 PM PDT 24
Peak memory 199180 kb
Host smart-854d64b9-446d-4f0a-88f7-d53fa101a09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026982083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1026982083
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2809581495
Short name T839
Test name
Test status
Simulation time 164722129732 ps
CPU time 69.45 seconds
Started Jun 02 01:13:00 PM PDT 24
Finished Jun 02 01:14:10 PM PDT 24
Peak memory 200512 kb
Host smart-59bf7343-556b-4175-8ef4-8cc35721d57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809581495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2809581495
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3616152730
Short name T523
Test name
Test status
Simulation time 26789234744 ps
CPU time 134.9 seconds
Started Jun 02 01:12:58 PM PDT 24
Finished Jun 02 01:15:14 PM PDT 24
Peak memory 200404 kb
Host smart-4dd7f9df-1934-4fb2-b43e-79e6e91d1559
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3616152730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3616152730
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3992700437
Short name T1152
Test name
Test status
Simulation time 3071825681 ps
CPU time 24.19 seconds
Started Jun 02 01:12:58 PM PDT 24
Finished Jun 02 01:13:23 PM PDT 24
Peak memory 199344 kb
Host smart-3485453b-277d-4ccd-b79e-445adabd8137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3992700437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3992700437
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1396035927
Short name T446
Test name
Test status
Simulation time 27280621885 ps
CPU time 52.84 seconds
Started Jun 02 01:12:57 PM PDT 24
Finished Jun 02 01:13:50 PM PDT 24
Peak memory 200220 kb
Host smart-bbc4e12e-ec8f-4b5f-b8f9-16ed6a876bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396035927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1396035927
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2341160069
Short name T607
Test name
Test status
Simulation time 37277279547 ps
CPU time 16.43 seconds
Started Jun 02 01:13:00 PM PDT 24
Finished Jun 02 01:13:17 PM PDT 24
Peak memory 196144 kb
Host smart-6eacdc1e-cdd4-4295-a7a0-73b83a034e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341160069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2341160069
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2935903549
Short name T356
Test name
Test status
Simulation time 281636866 ps
CPU time 1.76 seconds
Started Jun 02 01:12:59 PM PDT 24
Finished Jun 02 01:13:01 PM PDT 24
Peak memory 199060 kb
Host smart-82824e47-b5d2-4eac-a65e-ca40fb300849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935903549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2935903549
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.257778081
Short name T979
Test name
Test status
Simulation time 469069619278 ps
CPU time 324.87 seconds
Started Jun 02 01:13:08 PM PDT 24
Finished Jun 02 01:18:34 PM PDT 24
Peak memory 216868 kb
Host smart-86a1a422-38a6-4544-8a4e-d51b5ac19eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257778081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.257778081
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3951010614
Short name T274
Test name
Test status
Simulation time 49426166334 ps
CPU time 718.55 seconds
Started Jun 02 01:13:05 PM PDT 24
Finished Jun 02 01:25:04 PM PDT 24
Peak memory 217044 kb
Host smart-2197d950-d303-403d-9ee5-4fc57481b5db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951010614 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3951010614
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1241645950
Short name T452
Test name
Test status
Simulation time 6712868879 ps
CPU time 10.22 seconds
Started Jun 02 01:12:58 PM PDT 24
Finished Jun 02 01:13:09 PM PDT 24
Peak memory 199948 kb
Host smart-f630f465-c6c1-4c0b-a3c4-e8755550422a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241645950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1241645950
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1848534823
Short name T873
Test name
Test status
Simulation time 17275540467 ps
CPU time 27.88 seconds
Started Jun 02 01:13:00 PM PDT 24
Finished Jun 02 01:13:28 PM PDT 24
Peak memory 200316 kb
Host smart-2fd03b3d-648b-4f53-a8d9-28509d02f9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848534823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1848534823
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.227183436
Short name T478
Test name
Test status
Simulation time 58165966721 ps
CPU time 92.35 seconds
Started Jun 02 01:20:51 PM PDT 24
Finished Jun 02 01:22:24 PM PDT 24
Peak memory 200532 kb
Host smart-f01bd922-922f-4d58-90d6-348d4ad9f3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227183436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.227183436
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3116777566
Short name T133
Test name
Test status
Simulation time 122186562066 ps
CPU time 69.05 seconds
Started Jun 02 01:20:59 PM PDT 24
Finished Jun 02 01:22:08 PM PDT 24
Peak memory 200412 kb
Host smart-2d3b30c9-8a4c-472a-855e-385fb0aaaa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116777566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3116777566
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.22055201
Short name T830
Test name
Test status
Simulation time 19388519549 ps
CPU time 32.76 seconds
Started Jun 02 01:20:59 PM PDT 24
Finished Jun 02 01:21:32 PM PDT 24
Peak memory 200400 kb
Host smart-aa66eead-2c9d-45f4-bfe2-a62a58b433d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22055201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.22055201
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3605846853
Short name T662
Test name
Test status
Simulation time 86653995418 ps
CPU time 38 seconds
Started Jun 02 01:20:59 PM PDT 24
Finished Jun 02 01:21:37 PM PDT 24
Peak memory 200180 kb
Host smart-4e10c829-c017-4e98-8c83-046aa7927006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605846853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3605846853
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.71765405
Short name T1158
Test name
Test status
Simulation time 87633653268 ps
CPU time 146.71 seconds
Started Jun 02 01:20:59 PM PDT 24
Finished Jun 02 01:23:26 PM PDT 24
Peak memory 200504 kb
Host smart-274792bc-1fa0-4f65-a6f0-81f9cd9e942d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71765405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.71765405
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2311446871
Short name T1039
Test name
Test status
Simulation time 23282259638 ps
CPU time 28.3 seconds
Started Jun 02 01:20:59 PM PDT 24
Finished Jun 02 01:21:27 PM PDT 24
Peak memory 200408 kb
Host smart-34986b77-28fe-412b-8cf3-7bcc2f7e8147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311446871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2311446871
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2269233535
Short name T1094
Test name
Test status
Simulation time 127723561958 ps
CPU time 76.48 seconds
Started Jun 02 01:20:59 PM PDT 24
Finished Jun 02 01:22:16 PM PDT 24
Peak memory 200404 kb
Host smart-72ea4f11-c96a-4b4e-a609-e017edd59c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269233535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2269233535
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.960939306
Short name T183
Test name
Test status
Simulation time 49295612740 ps
CPU time 91.55 seconds
Started Jun 02 01:21:00 PM PDT 24
Finished Jun 02 01:22:32 PM PDT 24
Peak memory 200356 kb
Host smart-53bc5c68-422e-42cd-9fc6-426c638850d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960939306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.960939306
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.4086913686
Short name T184
Test name
Test status
Simulation time 5370533684 ps
CPU time 9.79 seconds
Started Jun 02 01:21:07 PM PDT 24
Finished Jun 02 01:21:17 PM PDT 24
Peak memory 199992 kb
Host smart-c50d02f4-d02a-4ec9-ab26-455d7a4094e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086913686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4086913686
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1828768710
Short name T594
Test name
Test status
Simulation time 49246951 ps
CPU time 0.56 seconds
Started Jun 02 01:13:12 PM PDT 24
Finished Jun 02 01:13:13 PM PDT 24
Peak memory 195712 kb
Host smart-d334d127-e347-4f25-adc5-a4915d6ee721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828768710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1828768710
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2546098968
Short name T440
Test name
Test status
Simulation time 98637270445 ps
CPU time 97.02 seconds
Started Jun 02 01:13:03 PM PDT 24
Finished Jun 02 01:14:41 PM PDT 24
Peak memory 200396 kb
Host smart-86c74593-bfc1-47e0-966c-0eacd1619218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546098968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2546098968
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2807632067
Short name T138
Test name
Test status
Simulation time 29113181961 ps
CPU time 46.63 seconds
Started Jun 02 01:13:09 PM PDT 24
Finished Jun 02 01:13:55 PM PDT 24
Peak memory 200332 kb
Host smart-167ae785-3c59-47fa-a1df-fbe6d38e6869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807632067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2807632067
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.632685836
Short name T947
Test name
Test status
Simulation time 95281902561 ps
CPU time 47.45 seconds
Started Jun 02 01:13:06 PM PDT 24
Finished Jun 02 01:13:54 PM PDT 24
Peak memory 200392 kb
Host smart-7985b2a0-b854-4160-9c81-236155beca68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632685836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.632685836
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.150019928
Short name T551
Test name
Test status
Simulation time 50895764621 ps
CPU time 82.77 seconds
Started Jun 02 01:13:08 PM PDT 24
Finished Jun 02 01:14:31 PM PDT 24
Peak memory 200408 kb
Host smart-fda43035-3dcc-4f91-b02d-b648a8fe0b24
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150019928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.150019928
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.4191328092
Short name T571
Test name
Test status
Simulation time 93517007868 ps
CPU time 597.6 seconds
Started Jun 02 01:13:13 PM PDT 24
Finished Jun 02 01:23:11 PM PDT 24
Peak memory 200392 kb
Host smart-3a2c7613-9406-4cb2-b866-456c556715e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191328092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.4191328092
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3530632101
Short name T711
Test name
Test status
Simulation time 9421304118 ps
CPU time 5.22 seconds
Started Jun 02 01:13:12 PM PDT 24
Finished Jun 02 01:13:18 PM PDT 24
Peak memory 198912 kb
Host smart-c704b95b-8b78-421a-8c14-71d77ec19911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530632101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3530632101
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2704479265
Short name T291
Test name
Test status
Simulation time 145675929605 ps
CPU time 103.07 seconds
Started Jun 02 01:13:13 PM PDT 24
Finished Jun 02 01:14:56 PM PDT 24
Peak memory 208796 kb
Host smart-eb53989a-ed45-4826-8079-478b5eab12ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704479265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2704479265
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.2095376097
Short name T368
Test name
Test status
Simulation time 30253603849 ps
CPU time 414.07 seconds
Started Jun 02 01:13:12 PM PDT 24
Finished Jun 02 01:20:07 PM PDT 24
Peak memory 200396 kb
Host smart-66adb3bc-bc6a-44df-a302-cf02e38299fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095376097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2095376097
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1505492582
Short name T910
Test name
Test status
Simulation time 3260007465 ps
CPU time 26.27 seconds
Started Jun 02 01:13:08 PM PDT 24
Finished Jun 02 01:13:34 PM PDT 24
Peak memory 198840 kb
Host smart-4520a686-d2f2-4d5e-8e78-c799d2a4ae6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505492582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1505492582
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.37417096
Short name T507
Test name
Test status
Simulation time 46760028916 ps
CPU time 42.43 seconds
Started Jun 02 01:13:19 PM PDT 24
Finished Jun 02 01:14:02 PM PDT 24
Peak memory 200324 kb
Host smart-2f756554-8aa3-43fd-b901-0bd59adfb690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37417096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.37417096
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1141564677
Short name T279
Test name
Test status
Simulation time 46644869703 ps
CPU time 75.66 seconds
Started Jun 02 01:13:19 PM PDT 24
Finished Jun 02 01:14:35 PM PDT 24
Peak memory 196388 kb
Host smart-0c755ef4-8b0f-429f-aaa6-1849ce68733c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141564677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1141564677
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1128677997
Short name T457
Test name
Test status
Simulation time 11097833041 ps
CPU time 34.21 seconds
Started Jun 02 01:13:07 PM PDT 24
Finished Jun 02 01:13:41 PM PDT 24
Peak memory 200124 kb
Host smart-9cef49f7-ca3a-40c8-b8cb-ab94a7f4d56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128677997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1128677997
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.176799162
Short name T644
Test name
Test status
Simulation time 76469370084 ps
CPU time 126.77 seconds
Started Jun 02 01:13:17 PM PDT 24
Finished Jun 02 01:15:24 PM PDT 24
Peak memory 200340 kb
Host smart-b1905c9c-8fcd-4e97-9cca-bb8c6b71d510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176799162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.176799162
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3583199761
Short name T699
Test name
Test status
Simulation time 393640293535 ps
CPU time 1227.63 seconds
Started Jun 02 01:13:11 PM PDT 24
Finished Jun 02 01:33:39 PM PDT 24
Peak memory 233404 kb
Host smart-9bae668a-7f4e-4810-b74e-a4fb113b6ea6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583199761 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3583199761
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.459859997
Short name T787
Test name
Test status
Simulation time 1116468882 ps
CPU time 1.68 seconds
Started Jun 02 01:13:12 PM PDT 24
Finished Jun 02 01:13:14 PM PDT 24
Peak memory 198856 kb
Host smart-c1fa258a-fd90-414c-97d4-4de5f23f9fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459859997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.459859997
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2724721987
Short name T832
Test name
Test status
Simulation time 59243164819 ps
CPU time 72.38 seconds
Started Jun 02 01:13:05 PM PDT 24
Finished Jun 02 01:14:19 PM PDT 24
Peak memory 200352 kb
Host smart-37592b35-939a-446b-82d9-0810a82f6f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724721987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2724721987
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.996803933
Short name T837
Test name
Test status
Simulation time 50007682484 ps
CPU time 42.16 seconds
Started Jun 02 01:21:04 PM PDT 24
Finished Jun 02 01:21:47 PM PDT 24
Peak memory 200368 kb
Host smart-5a1d1aef-2641-4081-9d7e-f3b31806ab38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996803933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.996803933
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.142689459
Short name T8
Test name
Test status
Simulation time 9443987209 ps
CPU time 13.98 seconds
Started Jun 02 01:21:05 PM PDT 24
Finished Jun 02 01:21:19 PM PDT 24
Peak memory 198896 kb
Host smart-3dc46fca-10f0-4000-872c-21a35390a525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142689459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.142689459
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3801252735
Short name T1017
Test name
Test status
Simulation time 8711402594 ps
CPU time 15.42 seconds
Started Jun 02 01:21:06 PM PDT 24
Finished Jun 02 01:21:21 PM PDT 24
Peak memory 199260 kb
Host smart-1248e0a5-22ef-42f5-94cb-355f44937536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801252735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3801252735
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3549926079
Short name T897
Test name
Test status
Simulation time 11063601252 ps
CPU time 22.29 seconds
Started Jun 02 01:21:05 PM PDT 24
Finished Jun 02 01:21:27 PM PDT 24
Peak memory 200532 kb
Host smart-b6e170a0-6aa0-47b7-bdf7-4ded9dd4ced9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549926079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3549926079
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1190884141
Short name T848
Test name
Test status
Simulation time 108399568847 ps
CPU time 48.56 seconds
Started Jun 02 01:21:06 PM PDT 24
Finished Jun 02 01:21:54 PM PDT 24
Peak memory 200324 kb
Host smart-b71a9263-00e0-41c4-9d6a-fddad671bbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190884141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1190884141
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.843840744
Short name T923
Test name
Test status
Simulation time 10940351943 ps
CPU time 5.56 seconds
Started Jun 02 01:21:04 PM PDT 24
Finished Jun 02 01:21:10 PM PDT 24
Peak memory 199128 kb
Host smart-043e6684-af57-4857-80a7-fb7285261963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843840744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.843840744
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1149946673
Short name T158
Test name
Test status
Simulation time 110992841911 ps
CPU time 76.98 seconds
Started Jun 02 01:21:12 PM PDT 24
Finished Jun 02 01:22:29 PM PDT 24
Peak memory 200300 kb
Host smart-7fcf603a-b401-4462-8c96-7ab62f608c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149946673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1149946673
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1246875461
Short name T466
Test name
Test status
Simulation time 19137516367 ps
CPU time 36.45 seconds
Started Jun 02 01:21:13 PM PDT 24
Finished Jun 02 01:21:50 PM PDT 24
Peak memory 200316 kb
Host smart-1769cdff-5aab-45aa-abb0-78b9993e4c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246875461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1246875461
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.211159092
Short name T1073
Test name
Test status
Simulation time 109973146687 ps
CPU time 13.67 seconds
Started Jun 02 01:13:22 PM PDT 24
Finished Jun 02 01:13:36 PM PDT 24
Peak memory 200344 kb
Host smart-340f947f-bf63-46c7-ba7f-5adfb76c483c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211159092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.211159092
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_intr.133441090
Short name T254
Test name
Test status
Simulation time 20432318608 ps
CPU time 10.61 seconds
Started Jun 02 01:13:22 PM PDT 24
Finished Jun 02 01:13:33 PM PDT 24
Peak memory 200332 kb
Host smart-ea3a02a8-f429-489f-b23d-2f45c5d4dfcd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133441090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.133441090
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3249060539
Short name T539
Test name
Test status
Simulation time 42640954887 ps
CPU time 120.34 seconds
Started Jun 02 01:13:27 PM PDT 24
Finished Jun 02 01:15:28 PM PDT 24
Peak memory 200320 kb
Host smart-dfea9cd9-5344-4be0-b488-f4dd419ddb8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249060539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3249060539
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2208691284
Short name T1075
Test name
Test status
Simulation time 8402067417 ps
CPU time 16.81 seconds
Started Jun 02 01:13:25 PM PDT 24
Finished Jun 02 01:13:42 PM PDT 24
Peak memory 200348 kb
Host smart-ec3ae05e-3465-46cb-8793-bd97508ed16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208691284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2208691284
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3888818811
Short name T1171
Test name
Test status
Simulation time 92848160506 ps
CPU time 37.2 seconds
Started Jun 02 01:13:18 PM PDT 24
Finished Jun 02 01:13:56 PM PDT 24
Peak memory 200564 kb
Host smart-1fc662b5-d1ab-4716-b225-a1270872d460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888818811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3888818811
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1634827315
Short name T1114
Test name
Test status
Simulation time 12925940917 ps
CPU time 170.32 seconds
Started Jun 02 01:13:26 PM PDT 24
Finished Jun 02 01:16:16 PM PDT 24
Peak memory 200348 kb
Host smart-6e4235f1-e0e2-4aae-a6d7-0e0ee7da9be9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634827315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1634827315
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3318750868
Short name T485
Test name
Test status
Simulation time 4438968072 ps
CPU time 27.51 seconds
Started Jun 02 01:13:22 PM PDT 24
Finished Jun 02 01:13:50 PM PDT 24
Peak memory 199844 kb
Host smart-ae907e87-c4b7-4fbc-b77e-9f7109f97cc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3318750868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3318750868
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2964324801
Short name T276
Test name
Test status
Simulation time 55763894591 ps
CPU time 83.03 seconds
Started Jun 02 01:13:29 PM PDT 24
Finished Jun 02 01:14:52 PM PDT 24
Peak memory 200436 kb
Host smart-877ea3f3-156d-4907-8434-f842f82b0100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964324801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2964324801
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2613864006
Short name T915
Test name
Test status
Simulation time 4211440189 ps
CPU time 2.47 seconds
Started Jun 02 01:13:18 PM PDT 24
Finished Jun 02 01:13:21 PM PDT 24
Peak memory 196628 kb
Host smart-8f545bff-eee4-4aa7-a023-0c57cea94319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613864006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2613864006
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2393339875
Short name T1175
Test name
Test status
Simulation time 843278381 ps
CPU time 3.79 seconds
Started Jun 02 01:13:12 PM PDT 24
Finished Jun 02 01:13:17 PM PDT 24
Peak memory 200260 kb
Host smart-cbee3062-8e98-482e-b9f2-d814eb64b9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393339875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2393339875
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3476020994
Short name T129
Test name
Test status
Simulation time 225399387531 ps
CPU time 534.62 seconds
Started Jun 02 01:13:32 PM PDT 24
Finished Jun 02 01:22:27 PM PDT 24
Peak memory 200380 kb
Host smart-fed8fd97-35f8-47f7-8cc7-0423933e93a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476020994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3476020994
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2302229220
Short name T1164
Test name
Test status
Simulation time 30985445433 ps
CPU time 699.11 seconds
Started Jun 02 01:13:26 PM PDT 24
Finished Jun 02 01:25:05 PM PDT 24
Peak memory 216484 kb
Host smart-8821fc72-8eda-4b4c-8c66-e99bb2a7f1c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302229220 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2302229220
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.252310340
Short name T562
Test name
Test status
Simulation time 1918940789 ps
CPU time 2.06 seconds
Started Jun 02 01:13:34 PM PDT 24
Finished Jun 02 01:13:37 PM PDT 24
Peak memory 200076 kb
Host smart-8f97694a-3bf5-4a24-812c-0fbb73a26d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252310340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.252310340
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2310377458
Short name T548
Test name
Test status
Simulation time 84426019256 ps
CPU time 312.08 seconds
Started Jun 02 01:13:22 PM PDT 24
Finished Jun 02 01:18:34 PM PDT 24
Peak memory 200368 kb
Host smart-4b61fd2f-d456-4b81-bac9-ad965275b540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310377458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2310377458
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1547753098
Short name T224
Test name
Test status
Simulation time 86004695179 ps
CPU time 45.18 seconds
Started Jun 02 01:21:12 PM PDT 24
Finished Jun 02 01:21:57 PM PDT 24
Peak memory 200320 kb
Host smart-94871ac5-a943-47ce-8723-e1e9cf6d4328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547753098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1547753098
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1545070575
Short name T214
Test name
Test status
Simulation time 31089304629 ps
CPU time 15.25 seconds
Started Jun 02 01:21:12 PM PDT 24
Finished Jun 02 01:21:27 PM PDT 24
Peak memory 200192 kb
Host smart-95a5398e-f1e5-43d6-8498-06da7ac2aef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545070575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1545070575
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2500735458
Short name T777
Test name
Test status
Simulation time 128646969343 ps
CPU time 13.86 seconds
Started Jun 02 01:21:12 PM PDT 24
Finished Jun 02 01:21:26 PM PDT 24
Peak memory 200344 kb
Host smart-2be82e5d-e76f-4f91-b19c-8d8cf8c56842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500735458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2500735458
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.4224821046
Short name T952
Test name
Test status
Simulation time 74206375906 ps
CPU time 64.8 seconds
Started Jun 02 01:21:12 PM PDT 24
Finished Jun 02 01:22:18 PM PDT 24
Peak memory 200316 kb
Host smart-f9d2dcf3-2d3a-44b2-9527-642aa7c43955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224821046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.4224821046
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1704020021
Short name T1165
Test name
Test status
Simulation time 222013846537 ps
CPU time 63.98 seconds
Started Jun 02 01:21:13 PM PDT 24
Finished Jun 02 01:22:17 PM PDT 24
Peak memory 200304 kb
Host smart-f8641f16-b7b0-4109-902a-409a356c1b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704020021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1704020021
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2430862219
Short name T1036
Test name
Test status
Simulation time 90788902855 ps
CPU time 46.64 seconds
Started Jun 02 01:21:12 PM PDT 24
Finished Jun 02 01:21:59 PM PDT 24
Peak memory 200348 kb
Host smart-6143a734-f898-49c8-b4b6-b12a0db145cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430862219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2430862219
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2867751526
Short name T156
Test name
Test status
Simulation time 155652056253 ps
CPU time 57.98 seconds
Started Jun 02 01:21:12 PM PDT 24
Finished Jun 02 01:22:11 PM PDT 24
Peak memory 200312 kb
Host smart-10e6ad84-4a4e-426b-8398-8a0c3909c912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867751526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2867751526
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1035171235
Short name T879
Test name
Test status
Simulation time 89257623511 ps
CPU time 161.34 seconds
Started Jun 02 01:21:11 PM PDT 24
Finished Jun 02 01:23:53 PM PDT 24
Peak memory 200404 kb
Host smart-c2d7ccc8-00eb-486b-9cbb-937e4870cd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035171235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1035171235
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.4021300603
Short name T504
Test name
Test status
Simulation time 36585909 ps
CPU time 0.58 seconds
Started Jun 02 01:13:39 PM PDT 24
Finished Jun 02 01:13:40 PM PDT 24
Peak memory 195776 kb
Host smart-c26fbdf5-4ad5-40b6-b0c4-110bd086f996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021300603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.4021300603
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.4110772090
Short name T295
Test name
Test status
Simulation time 144084607077 ps
CPU time 436.41 seconds
Started Jun 02 01:13:31 PM PDT 24
Finished Jun 02 01:20:48 PM PDT 24
Peak memory 200444 kb
Host smart-280f5cd4-5cf5-48b5-bf2c-b347f8b208e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110772090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.4110772090
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1322958933
Short name T300
Test name
Test status
Simulation time 46504741525 ps
CPU time 9.59 seconds
Started Jun 02 01:13:33 PM PDT 24
Finished Jun 02 01:13:43 PM PDT 24
Peak memory 200156 kb
Host smart-dcbd8d9c-acc3-43d9-8e06-471db6e3fd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322958933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1322958933
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2945899661
Short name T362
Test name
Test status
Simulation time 32468265707 ps
CPU time 16.75 seconds
Started Jun 02 01:13:34 PM PDT 24
Finished Jun 02 01:13:51 PM PDT 24
Peak memory 200404 kb
Host smart-796cb414-7220-4fe0-b244-944ccc6b9f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945899661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2945899661
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.407611821
Short name T896
Test name
Test status
Simulation time 44582653474 ps
CPU time 92.49 seconds
Started Jun 02 01:13:33 PM PDT 24
Finished Jun 02 01:15:06 PM PDT 24
Peak memory 200308 kb
Host smart-03aaf621-b82b-4cf6-a95a-ec49bb2753e7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407611821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.407611821
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1057534672
Short name T986
Test name
Test status
Simulation time 174832879527 ps
CPU time 757.69 seconds
Started Jun 02 01:13:40 PM PDT 24
Finished Jun 02 01:26:18 PM PDT 24
Peak memory 200380 kb
Host smart-48736a9a-397b-4027-a45b-7e1f833f4dc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057534672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1057534672
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2257101030
Short name T396
Test name
Test status
Simulation time 8239797097 ps
CPU time 8.07 seconds
Started Jun 02 01:13:42 PM PDT 24
Finished Jun 02 01:13:50 PM PDT 24
Peak memory 198108 kb
Host smart-2b414098-d79c-485d-a4ec-cb57dbabaa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257101030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2257101030
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1590737751
Short name T385
Test name
Test status
Simulation time 19834479654 ps
CPU time 21.94 seconds
Started Jun 02 01:13:32 PM PDT 24
Finished Jun 02 01:13:55 PM PDT 24
Peak memory 198084 kb
Host smart-ffdb0bd8-c5a2-443f-8051-cde6e2ab791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590737751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1590737751
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.300833410
Short name T351
Test name
Test status
Simulation time 11735978653 ps
CPU time 330.7 seconds
Started Jun 02 01:13:42 PM PDT 24
Finished Jun 02 01:19:13 PM PDT 24
Peak memory 200400 kb
Host smart-7934df14-9fd6-4083-88e8-b8e856644cb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=300833410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.300833410
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2944085927
Short name T792
Test name
Test status
Simulation time 3702466722 ps
CPU time 7.36 seconds
Started Jun 02 01:13:31 PM PDT 24
Finished Jun 02 01:13:39 PM PDT 24
Peak memory 199564 kb
Host smart-04dd1c25-11a9-407f-b149-9cda6bca6a53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2944085927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2944085927
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.710761105
Short name T586
Test name
Test status
Simulation time 49431714130 ps
CPU time 22.61 seconds
Started Jun 02 01:13:39 PM PDT 24
Finished Jun 02 01:14:02 PM PDT 24
Peak memory 200396 kb
Host smart-79357f94-e3d2-4182-a6a8-2c000465914f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710761105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.710761105
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1578598069
Short name T422
Test name
Test status
Simulation time 44022489377 ps
CPU time 20.06 seconds
Started Jun 02 01:13:43 PM PDT 24
Finished Jun 02 01:14:04 PM PDT 24
Peak memory 196096 kb
Host smart-b83e583c-338b-4252-981e-5791b97e8fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578598069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1578598069
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.366541551
Short name T628
Test name
Test status
Simulation time 443663963 ps
CPU time 1.26 seconds
Started Jun 02 01:13:33 PM PDT 24
Finished Jun 02 01:13:35 PM PDT 24
Peak memory 200260 kb
Host smart-af611051-b92a-4f06-855c-d0f7eea83aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366541551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.366541551
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.4100466316
Short name T749
Test name
Test status
Simulation time 184197956423 ps
CPU time 419.02 seconds
Started Jun 02 01:13:42 PM PDT 24
Finished Jun 02 01:20:41 PM PDT 24
Peak memory 200356 kb
Host smart-a0babea6-7793-4604-910d-26541f3bdd0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100466316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.4100466316
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1841813680
Short name T16
Test name
Test status
Simulation time 874098675 ps
CPU time 3.46 seconds
Started Jun 02 01:13:40 PM PDT 24
Finished Jun 02 01:13:44 PM PDT 24
Peak memory 198668 kb
Host smart-7fd7bf75-1a31-43f0-86e2-208a3a673947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841813680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1841813680
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2409357946
Short name T815
Test name
Test status
Simulation time 89931850248 ps
CPU time 274.81 seconds
Started Jun 02 01:13:33 PM PDT 24
Finished Jun 02 01:18:08 PM PDT 24
Peak memory 200260 kb
Host smart-86ef8b66-3b44-4c8f-88c1-2143b58f9125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409357946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2409357946
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.522536908
Short name T564
Test name
Test status
Simulation time 8233066729 ps
CPU time 8.52 seconds
Started Jun 02 01:21:21 PM PDT 24
Finished Jun 02 01:21:29 PM PDT 24
Peak memory 199036 kb
Host smart-44579170-bd24-4721-96ef-44bb135cab42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522536908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.522536908
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.356457612
Short name T1003
Test name
Test status
Simulation time 38437760217 ps
CPU time 21.62 seconds
Started Jun 02 01:21:18 PM PDT 24
Finished Jun 02 01:21:40 PM PDT 24
Peak memory 200368 kb
Host smart-1ebb87f8-03fc-41f8-a086-82972c45c2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356457612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.356457612
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3087895955
Short name T685
Test name
Test status
Simulation time 235192848256 ps
CPU time 369.62 seconds
Started Jun 02 01:21:21 PM PDT 24
Finished Jun 02 01:27:31 PM PDT 24
Peak memory 200284 kb
Host smart-f46ef67f-f064-4d66-870b-64452e0bb8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087895955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3087895955
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3996719156
Short name T206
Test name
Test status
Simulation time 58163104598 ps
CPU time 49.96 seconds
Started Jun 02 01:21:20 PM PDT 24
Finished Jun 02 01:22:10 PM PDT 24
Peak memory 200368 kb
Host smart-da425528-bb3e-422b-8cb3-e0bc2b7ea0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996719156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3996719156
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1178783325
Short name T943
Test name
Test status
Simulation time 83894737239 ps
CPU time 125.64 seconds
Started Jun 02 01:21:21 PM PDT 24
Finished Jun 02 01:23:27 PM PDT 24
Peak memory 200384 kb
Host smart-8f643301-cdbb-469f-ad1c-b4c8cfabe390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178783325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1178783325
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.870624657
Short name T89
Test name
Test status
Simulation time 154580659687 ps
CPU time 40.95 seconds
Started Jun 02 01:21:21 PM PDT 24
Finished Jun 02 01:22:02 PM PDT 24
Peak memory 200292 kb
Host smart-d788a413-77c6-449c-b6cf-e372237a648f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870624657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.870624657
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3813040822
Short name T324
Test name
Test status
Simulation time 15575168871 ps
CPU time 16.55 seconds
Started Jun 02 01:21:19 PM PDT 24
Finished Jun 02 01:21:36 PM PDT 24
Peak memory 200604 kb
Host smart-df130af0-2355-4826-a30c-be2b7f387ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813040822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3813040822
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3969324119
Short name T833
Test name
Test status
Simulation time 127125236433 ps
CPU time 55.03 seconds
Started Jun 02 01:21:19 PM PDT 24
Finished Jun 02 01:22:14 PM PDT 24
Peak memory 200608 kb
Host smart-b45d8425-faf1-4a6d-8e7f-7534ed9a1ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969324119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3969324119
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3549181155
Short name T591
Test name
Test status
Simulation time 106126051667 ps
CPU time 33.4 seconds
Started Jun 02 01:21:21 PM PDT 24
Finished Jun 02 01:21:55 PM PDT 24
Peak memory 200404 kb
Host smart-1cda9bd9-34ef-4d08-b129-f3be04f23b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549181155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3549181155
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.729975576
Short name T428
Test name
Test status
Simulation time 20665908 ps
CPU time 0.58 seconds
Started Jun 02 01:13:53 PM PDT 24
Finished Jun 02 01:13:54 PM PDT 24
Peak memory 195768 kb
Host smart-3ff8974c-1698-4c39-b08f-b78b377a7568
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729975576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.729975576
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2946662642
Short name T525
Test name
Test status
Simulation time 33183543750 ps
CPU time 59.59 seconds
Started Jun 02 01:13:42 PM PDT 24
Finished Jun 02 01:14:42 PM PDT 24
Peak memory 200416 kb
Host smart-03238038-8691-41bf-bb9e-1163b4c684b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946662642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2946662642
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1864407955
Short name T919
Test name
Test status
Simulation time 134559721372 ps
CPU time 33.22 seconds
Started Jun 02 01:13:39 PM PDT 24
Finished Jun 02 01:14:12 PM PDT 24
Peak memory 200152 kb
Host smart-de9941ef-5570-4b95-b2d8-a791ad40aa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864407955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1864407955
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2666258955
Short name T333
Test name
Test status
Simulation time 10442931374 ps
CPU time 23.66 seconds
Started Jun 02 01:13:47 PM PDT 24
Finished Jun 02 01:14:11 PM PDT 24
Peak memory 200392 kb
Host smart-0043e457-858e-4ddb-a12a-e8046b9e2929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666258955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2666258955
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.798569824
Short name T493
Test name
Test status
Simulation time 9916945292 ps
CPU time 14.84 seconds
Started Jun 02 01:13:47 PM PDT 24
Finished Jun 02 01:14:02 PM PDT 24
Peak memory 197244 kb
Host smart-f6faf6b2-0e12-48a7-9dd4-119e03fd1e29
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798569824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.798569824
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2006594419
Short name T835
Test name
Test status
Simulation time 133243628477 ps
CPU time 685.75 seconds
Started Jun 02 01:13:46 PM PDT 24
Finished Jun 02 01:25:13 PM PDT 24
Peak memory 200360 kb
Host smart-24e119bd-e1ff-4ba7-a8b4-8efea01a3fb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2006594419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2006594419
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2058157051
Short name T592
Test name
Test status
Simulation time 3293837368 ps
CPU time 5.3 seconds
Started Jun 02 01:13:49 PM PDT 24
Finished Jun 02 01:13:55 PM PDT 24
Peak memory 197024 kb
Host smart-bebd57ad-4f76-4ccf-baf0-5d3122e5bbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058157051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2058157051
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3427263628
Short name T621
Test name
Test status
Simulation time 136557971461 ps
CPU time 57.97 seconds
Started Jun 02 01:13:47 PM PDT 24
Finished Jun 02 01:14:45 PM PDT 24
Peak memory 200452 kb
Host smart-e0fad5b4-3b15-4574-9c9d-feb041ed0dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427263628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3427263628
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1228325631
Short name T936
Test name
Test status
Simulation time 7906277049 ps
CPU time 203.42 seconds
Started Jun 02 01:13:48 PM PDT 24
Finished Jun 02 01:17:12 PM PDT 24
Peak memory 200336 kb
Host smart-adaacda4-314b-4680-9e42-d2133369397d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1228325631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1228325631
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2308675029
Short name T625
Test name
Test status
Simulation time 2536070377 ps
CPU time 15.94 seconds
Started Jun 02 01:13:47 PM PDT 24
Finished Jun 02 01:14:03 PM PDT 24
Peak memory 199436 kb
Host smart-6ffc727c-6828-4eb3-96b2-f29c16fbf342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2308675029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2308675029
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1472316649
Short name T1145
Test name
Test status
Simulation time 126104548957 ps
CPU time 60.16 seconds
Started Jun 02 01:13:47 PM PDT 24
Finished Jun 02 01:14:47 PM PDT 24
Peak memory 200356 kb
Host smart-3d3addde-cabb-4144-b97a-a81c47c08e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472316649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1472316649
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.320387166
Short name T1143
Test name
Test status
Simulation time 2884278231 ps
CPU time 5.39 seconds
Started Jun 02 01:13:48 PM PDT 24
Finished Jun 02 01:13:54 PM PDT 24
Peak memory 196400 kb
Host smart-e936f9eb-c85b-4c4f-aa91-f880a1a9a2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320387166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.320387166
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3077833557
Short name T576
Test name
Test status
Simulation time 5895672710 ps
CPU time 17.21 seconds
Started Jun 02 01:13:41 PM PDT 24
Finished Jun 02 01:13:59 PM PDT 24
Peak memory 200068 kb
Host smart-98307847-2d5b-42dc-beaa-8f0669596b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077833557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3077833557
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1778481875
Short name T288
Test name
Test status
Simulation time 6481406185 ps
CPU time 19.27 seconds
Started Jun 02 01:13:46 PM PDT 24
Finished Jun 02 01:14:06 PM PDT 24
Peak memory 200168 kb
Host smart-efbe7a84-a26f-414f-96dd-6e1cdd3bf023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778481875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1778481875
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2603187311
Short name T950
Test name
Test status
Simulation time 27338540174 ps
CPU time 14.39 seconds
Started Jun 02 01:13:40 PM PDT 24
Finished Jun 02 01:13:54 PM PDT 24
Peak memory 200392 kb
Host smart-e6a390ea-db2c-4b61-9ffa-e3f88a1a4e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603187311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2603187311
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3484629816
Short name T179
Test name
Test status
Simulation time 22352862069 ps
CPU time 38 seconds
Started Jun 02 01:21:19 PM PDT 24
Finished Jun 02 01:21:57 PM PDT 24
Peak memory 200352 kb
Host smart-21d84711-c7b2-4245-8092-7d534b2475ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484629816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3484629816
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1586723005
Short name T812
Test name
Test status
Simulation time 268657195474 ps
CPU time 64.36 seconds
Started Jun 02 01:21:20 PM PDT 24
Finished Jun 02 01:22:25 PM PDT 24
Peak memory 200288 kb
Host smart-e9b91c25-77ac-444d-9710-128b0801947e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586723005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1586723005
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.41598888
Short name T742
Test name
Test status
Simulation time 36325108159 ps
CPU time 26.61 seconds
Started Jun 02 01:21:27 PM PDT 24
Finished Jun 02 01:21:54 PM PDT 24
Peak memory 200364 kb
Host smart-cce9143e-1b2d-4791-9b82-a8c06577caed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41598888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.41598888
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.384813941
Short name T331
Test name
Test status
Simulation time 95362931800 ps
CPU time 260.02 seconds
Started Jun 02 01:21:27 PM PDT 24
Finished Jun 02 01:25:48 PM PDT 24
Peak memory 200460 kb
Host smart-5f829067-cda6-48e4-9f55-44619547066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384813941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.384813941
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2010340285
Short name T339
Test name
Test status
Simulation time 28661878698 ps
CPU time 14.38 seconds
Started Jun 02 01:21:27 PM PDT 24
Finished Jun 02 01:21:42 PM PDT 24
Peak memory 200420 kb
Host smart-32cd8ac9-f99a-4fbe-aeb5-f3494f47b499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010340285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2010340285
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.399764525
Short name T232
Test name
Test status
Simulation time 177464266748 ps
CPU time 229.28 seconds
Started Jun 02 01:21:24 PM PDT 24
Finished Jun 02 01:25:13 PM PDT 24
Peak memory 200416 kb
Host smart-5ef84f30-e7cb-4953-9bba-153f993f1c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399764525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.399764525
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2074190696
Short name T338
Test name
Test status
Simulation time 44789656079 ps
CPU time 68.27 seconds
Started Jun 02 01:21:26 PM PDT 24
Finished Jun 02 01:22:35 PM PDT 24
Peak memory 200404 kb
Host smart-5209c158-1ffd-4c12-abf1-46307661d2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074190696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2074190696
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3464361616
Short name T437
Test name
Test status
Simulation time 50453977141 ps
CPU time 23.17 seconds
Started Jun 02 01:21:25 PM PDT 24
Finished Jun 02 01:21:49 PM PDT 24
Peak memory 200384 kb
Host smart-b38abf13-7410-4e80-b0d5-717ca9254500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464361616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3464361616
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1541526022
Short name T371
Test name
Test status
Simulation time 31001865 ps
CPU time 0.57 seconds
Started Jun 02 01:14:08 PM PDT 24
Finished Jun 02 01:14:09 PM PDT 24
Peak memory 195748 kb
Host smart-2aca58e5-af34-4753-9b1b-47256005148d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541526022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1541526022
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2556590705
Short name T1043
Test name
Test status
Simulation time 104327177055 ps
CPU time 54.3 seconds
Started Jun 02 01:13:54 PM PDT 24
Finished Jun 02 01:14:49 PM PDT 24
Peak memory 200340 kb
Host smart-7dee0b50-8fd1-4c0a-8938-111b8d26666f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556590705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2556590705
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1017941818
Short name T1057
Test name
Test status
Simulation time 16889927548 ps
CPU time 48.37 seconds
Started Jun 02 01:13:55 PM PDT 24
Finished Jun 02 01:14:43 PM PDT 24
Peak memory 200320 kb
Host smart-ddb317d8-94b5-4148-bc30-01acb5242f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017941818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1017941818
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1439524448
Short name T632
Test name
Test status
Simulation time 288509630299 ps
CPU time 52.12 seconds
Started Jun 02 01:13:54 PM PDT 24
Finished Jun 02 01:14:46 PM PDT 24
Peak memory 200384 kb
Host smart-f57d38f2-d080-46c6-9489-42a44f7dda7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439524448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1439524448
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2100498404
Short name T961
Test name
Test status
Simulation time 17472111942 ps
CPU time 8.18 seconds
Started Jun 02 01:14:01 PM PDT 24
Finished Jun 02 01:14:10 PM PDT 24
Peak memory 199140 kb
Host smart-8b66b871-dec0-43df-b942-ad2020c1370e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100498404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2100498404
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_loopback.2882249321
Short name T677
Test name
Test status
Simulation time 3590058678 ps
CPU time 1.66 seconds
Started Jun 02 01:13:59 PM PDT 24
Finished Jun 02 01:14:01 PM PDT 24
Peak memory 198208 kb
Host smart-1215544a-f49a-4dc8-af52-be1765896ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882249321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2882249321
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1758238161
Short name T287
Test name
Test status
Simulation time 69778321615 ps
CPU time 109.64 seconds
Started Jun 02 01:13:55 PM PDT 24
Finished Jun 02 01:15:45 PM PDT 24
Peak memory 200520 kb
Host smart-4b82efeb-7b40-4b03-876b-3a77d4def92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758238161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1758238161
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1299821239
Short name T596
Test name
Test status
Simulation time 7685447216 ps
CPU time 119.8 seconds
Started Jun 02 01:14:01 PM PDT 24
Finished Jun 02 01:16:02 PM PDT 24
Peak memory 200312 kb
Host smart-898889ad-a6cd-4f12-a783-8bc145b1c75e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299821239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1299821239
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1575643286
Short name T1011
Test name
Test status
Simulation time 5154110494 ps
CPU time 43.31 seconds
Started Jun 02 01:13:53 PM PDT 24
Finished Jun 02 01:14:37 PM PDT 24
Peak memory 199268 kb
Host smart-42242f59-c1ce-4484-8fbd-d779a26b1d0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1575643286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1575643286
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2908174644
Short name T1095
Test name
Test status
Simulation time 177698319995 ps
CPU time 77.38 seconds
Started Jun 02 01:14:00 PM PDT 24
Finished Jun 02 01:15:17 PM PDT 24
Peak memory 200500 kb
Host smart-f2590016-8e41-4a25-81c4-5aefe25d7484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908174644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2908174644
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2950576133
Short name T275
Test name
Test status
Simulation time 6222563536 ps
CPU time 2.98 seconds
Started Jun 02 01:14:01 PM PDT 24
Finished Jun 02 01:14:04 PM PDT 24
Peak memory 196340 kb
Host smart-117ebb78-972a-453c-a546-f3773e33189a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950576133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2950576133
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1835188485
Short name T622
Test name
Test status
Simulation time 5895663828 ps
CPU time 28.6 seconds
Started Jun 02 01:13:53 PM PDT 24
Finished Jun 02 01:14:22 PM PDT 24
Peak memory 199572 kb
Host smart-91df3462-74ae-4fa3-9bbe-e937d45327f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835188485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1835188485
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.2306787824
Short name T778
Test name
Test status
Simulation time 42716746602 ps
CPU time 12.52 seconds
Started Jun 02 01:14:10 PM PDT 24
Finished Jun 02 01:14:22 PM PDT 24
Peak memory 200296 kb
Host smart-01c8d8fc-11bd-486a-8580-38323aea5fb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306787824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2306787824
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.239878262
Short name T1117
Test name
Test status
Simulation time 61576395574 ps
CPU time 602.01 seconds
Started Jun 02 01:14:07 PM PDT 24
Finished Jun 02 01:24:10 PM PDT 24
Peak memory 225276 kb
Host smart-bf9b04f0-c591-4f11-a1d8-022135604be4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239878262 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.239878262
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1604564234
Short name T1170
Test name
Test status
Simulation time 411246571 ps
CPU time 1.36 seconds
Started Jun 02 01:14:03 PM PDT 24
Finished Jun 02 01:14:04 PM PDT 24
Peak memory 197480 kb
Host smart-ffd5e656-5057-4482-873d-6cc1aa08a627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604564234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1604564234
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1677058482
Short name T606
Test name
Test status
Simulation time 30446235149 ps
CPU time 52.83 seconds
Started Jun 02 01:14:01 PM PDT 24
Finished Jun 02 01:14:54 PM PDT 24
Peak memory 200304 kb
Host smart-f8100b6f-1438-45af-82ca-e3b96b5a6a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677058482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1677058482
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2268262283
Short name T340
Test name
Test status
Simulation time 11356192637 ps
CPU time 10.83 seconds
Started Jun 02 01:21:24 PM PDT 24
Finished Jun 02 01:21:36 PM PDT 24
Peak memory 200336 kb
Host smart-94af9e01-bc53-4bf4-8cfc-d58cabbfea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268262283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2268262283
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2198440374
Short name T996
Test name
Test status
Simulation time 67249981063 ps
CPU time 20.29 seconds
Started Jun 02 01:21:27 PM PDT 24
Finished Jun 02 01:21:47 PM PDT 24
Peak memory 200316 kb
Host smart-7aa56080-e020-4e4b-9719-f43c3acc1cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198440374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2198440374
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1333451101
Short name T887
Test name
Test status
Simulation time 45909184894 ps
CPU time 12.52 seconds
Started Jun 02 01:21:24 PM PDT 24
Finished Jun 02 01:21:37 PM PDT 24
Peak memory 200296 kb
Host smart-f39f61d7-30a2-4128-af46-f1523af10eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333451101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1333451101
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2500512848
Short name T1052
Test name
Test status
Simulation time 115567432270 ps
CPU time 57.68 seconds
Started Jun 02 01:21:33 PM PDT 24
Finished Jun 02 01:22:31 PM PDT 24
Peak memory 200416 kb
Host smart-7e9aa732-dda9-47a6-94e1-0e843b263c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500512848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2500512848
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3340449781
Short name T892
Test name
Test status
Simulation time 17119616556 ps
CPU time 30.69 seconds
Started Jun 02 01:21:35 PM PDT 24
Finished Jun 02 01:22:06 PM PDT 24
Peak memory 200332 kb
Host smart-a34b9339-0880-4f45-b683-ec019cda7742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340449781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3340449781
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1228468518
Short name T253
Test name
Test status
Simulation time 39363090840 ps
CPU time 58.88 seconds
Started Jun 02 01:21:33 PM PDT 24
Finished Jun 02 01:22:32 PM PDT 24
Peak memory 200376 kb
Host smart-087c8daf-dc3b-457e-8252-469f33029bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228468518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1228468518
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3994826060
Short name T990
Test name
Test status
Simulation time 56512901463 ps
CPU time 24.94 seconds
Started Jun 02 01:21:33 PM PDT 24
Finished Jun 02 01:21:59 PM PDT 24
Peak memory 200364 kb
Host smart-21144ef8-17b6-4a3f-8dc8-ff45f3fc5605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994826060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3994826060
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2766113389
Short name T1110
Test name
Test status
Simulation time 88887131642 ps
CPU time 36.68 seconds
Started Jun 02 01:21:33 PM PDT 24
Finished Jun 02 01:22:10 PM PDT 24
Peak memory 200304 kb
Host smart-3029d06d-2dd0-4c53-a5a9-101ab26ee092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766113389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2766113389
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.287276519
Short name T1072
Test name
Test status
Simulation time 67748191871 ps
CPU time 62.48 seconds
Started Jun 02 01:21:34 PM PDT 24
Finished Jun 02 01:22:37 PM PDT 24
Peak memory 200256 kb
Host smart-9a122165-03eb-4b47-ac5d-a6fee84c1e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287276519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.287276519
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2079316116
Short name T650
Test name
Test status
Simulation time 58189955 ps
CPU time 0.57 seconds
Started Jun 02 01:14:16 PM PDT 24
Finished Jun 02 01:14:17 PM PDT 24
Peak memory 195760 kb
Host smart-026e61b1-a48d-434c-a35e-d38412aa99c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079316116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2079316116
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1090324639
Short name T637
Test name
Test status
Simulation time 32202253548 ps
CPU time 51.92 seconds
Started Jun 02 01:14:09 PM PDT 24
Finished Jun 02 01:15:01 PM PDT 24
Peak memory 200304 kb
Host smart-d79d94ec-c5d7-4ecb-b2d2-e85cc83641bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090324639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1090324639
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3446171471
Short name T390
Test name
Test status
Simulation time 443179953297 ps
CPU time 46.96 seconds
Started Jun 02 01:14:14 PM PDT 24
Finished Jun 02 01:15:01 PM PDT 24
Peak memory 200324 kb
Host smart-2307aacc-d2c1-45bf-807d-6898c8dd0878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446171471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3446171471
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.4129181344
Short name T414
Test name
Test status
Simulation time 43942392268 ps
CPU time 33.04 seconds
Started Jun 02 01:14:07 PM PDT 24
Finished Jun 02 01:14:40 PM PDT 24
Peak memory 200348 kb
Host smart-5f8c1224-738f-4eff-96aa-34a8f3d73d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129181344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.4129181344
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1423147759
Short name T992
Test name
Test status
Simulation time 56934740737 ps
CPU time 9.28 seconds
Started Jun 02 01:14:14 PM PDT 24
Finished Jun 02 01:14:24 PM PDT 24
Peak memory 200304 kb
Host smart-7f186d08-655d-4bc2-976f-2c385bcde17e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423147759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1423147759
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2852632610
Short name T785
Test name
Test status
Simulation time 92167586256 ps
CPU time 850.86 seconds
Started Jun 02 01:14:15 PM PDT 24
Finished Jun 02 01:28:26 PM PDT 24
Peak memory 200284 kb
Host smart-d728980d-85c5-4fe4-8ce6-8bca10c627a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2852632610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2852632610
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.4132732223
Short name T615
Test name
Test status
Simulation time 10105535158 ps
CPU time 8.93 seconds
Started Jun 02 01:14:14 PM PDT 24
Finished Jun 02 01:14:24 PM PDT 24
Peak memory 200172 kb
Host smart-57fa1361-443c-4547-93f9-15af0496eb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132732223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.4132732223
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.846736910
Short name T9
Test name
Test status
Simulation time 32803825548 ps
CPU time 42.63 seconds
Started Jun 02 01:14:17 PM PDT 24
Finished Jun 02 01:15:00 PM PDT 24
Peak memory 200096 kb
Host smart-79649aa9-2486-4df3-94cd-d52705bcf427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846736910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.846736910
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1545938752
Short name T864
Test name
Test status
Simulation time 13759481164 ps
CPU time 246.12 seconds
Started Jun 02 01:14:16 PM PDT 24
Finished Jun 02 01:18:22 PM PDT 24
Peak memory 200396 kb
Host smart-ffe486cc-0247-48d6-8897-900937f2615d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1545938752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1545938752
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1763029856
Short name T464
Test name
Test status
Simulation time 7250967430 ps
CPU time 65.19 seconds
Started Jun 02 01:14:08 PM PDT 24
Finished Jun 02 01:15:13 PM PDT 24
Peak memory 198536 kb
Host smart-b6d3ee27-5a24-4ab6-aa18-64d8fc4d5979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1763029856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1763029856
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1024813963
Short name T895
Test name
Test status
Simulation time 81832680346 ps
CPU time 304.43 seconds
Started Jun 02 01:14:15 PM PDT 24
Finished Jun 02 01:19:19 PM PDT 24
Peak memory 200380 kb
Host smart-f75d6756-f1df-48dc-9ac4-e788817721da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024813963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1024813963
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2807682851
Short name T634
Test name
Test status
Simulation time 4565491225 ps
CPU time 4.7 seconds
Started Jun 02 01:14:15 PM PDT 24
Finished Jun 02 01:14:20 PM PDT 24
Peak memory 196400 kb
Host smart-0ad63a0a-94f4-4e34-81ba-c2b38852753d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807682851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2807682851
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3829968073
Short name T496
Test name
Test status
Simulation time 639189604 ps
CPU time 2 seconds
Started Jun 02 01:14:07 PM PDT 24
Finished Jun 02 01:14:10 PM PDT 24
Peak memory 199524 kb
Host smart-05db2afc-b0f0-40ab-adba-19e7a9d9e688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829968073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3829968073
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.934538408
Short name T995
Test name
Test status
Simulation time 133476950308 ps
CPU time 585.79 seconds
Started Jun 02 01:14:14 PM PDT 24
Finished Jun 02 01:24:00 PM PDT 24
Peak memory 208676 kb
Host smart-19f94302-eeb3-489c-82e0-60a86a46d440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934538408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.934538408
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1775596014
Short name T57
Test name
Test status
Simulation time 60780259949 ps
CPU time 385.2 seconds
Started Jun 02 01:14:15 PM PDT 24
Finished Jun 02 01:20:40 PM PDT 24
Peak memory 217044 kb
Host smart-32fcd092-275f-4183-a85c-646ac057a198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775596014 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1775596014
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3945942237
Short name T272
Test name
Test status
Simulation time 7991630174 ps
CPU time 7.47 seconds
Started Jun 02 01:14:15 PM PDT 24
Finished Jun 02 01:14:23 PM PDT 24
Peak memory 199832 kb
Host smart-86193f74-b10e-4155-8772-eded58ff75d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945942237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3945942237
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.294616852
Short name T928
Test name
Test status
Simulation time 307962721604 ps
CPU time 27.83 seconds
Started Jun 02 01:14:09 PM PDT 24
Finished Jun 02 01:14:38 PM PDT 24
Peak memory 200264 kb
Host smart-a303f2ca-7d99-4647-988d-31e7aa6c9986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294616852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.294616852
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2793267705
Short name T656
Test name
Test status
Simulation time 76627530280 ps
CPU time 35.05 seconds
Started Jun 02 01:21:35 PM PDT 24
Finished Jun 02 01:22:10 PM PDT 24
Peak memory 200368 kb
Host smart-89ec5d2a-1ac7-4e92-886c-be99319bef8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793267705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2793267705
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.841249365
Short name T1177
Test name
Test status
Simulation time 35712797119 ps
CPU time 16.16 seconds
Started Jun 02 01:21:38 PM PDT 24
Finished Jun 02 01:21:54 PM PDT 24
Peak memory 200224 kb
Host smart-06db0fd9-d7ad-4f0c-9068-63450ac3d2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841249365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.841249365
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2543053613
Short name T675
Test name
Test status
Simulation time 11613192653 ps
CPU time 21.24 seconds
Started Jun 02 01:21:33 PM PDT 24
Finished Jun 02 01:21:54 PM PDT 24
Peak memory 200352 kb
Host smart-9d0aff3e-c079-4181-9724-30e8c2df8b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543053613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2543053613
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1261608341
Short name T445
Test name
Test status
Simulation time 118152207313 ps
CPU time 69.32 seconds
Started Jun 02 01:21:35 PM PDT 24
Finished Jun 02 01:22:44 PM PDT 24
Peak memory 200168 kb
Host smart-9ca86f82-f757-4f94-b8c9-1cd5c1a2a377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261608341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1261608341
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.687830948
Short name T209
Test name
Test status
Simulation time 102908625665 ps
CPU time 74.16 seconds
Started Jun 02 01:21:34 PM PDT 24
Finished Jun 02 01:22:48 PM PDT 24
Peak memory 200204 kb
Host smart-cca81bf5-77d3-4d5c-9dba-edb90ac0e0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687830948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.687830948
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1448391693
Short name T229
Test name
Test status
Simulation time 29323700811 ps
CPU time 42.47 seconds
Started Jun 02 01:21:39 PM PDT 24
Finished Jun 02 01:22:22 PM PDT 24
Peak memory 200172 kb
Host smart-9dd33fad-92fb-4e41-9c39-8f26844f5e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448391693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1448391693
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3939064842
Short name T668
Test name
Test status
Simulation time 13594042 ps
CPU time 0.58 seconds
Started Jun 02 01:11:31 PM PDT 24
Finished Jun 02 01:11:31 PM PDT 24
Peak memory 195776 kb
Host smart-62a73c40-67fb-46b8-8e24-3d6a0d469418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939064842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3939064842
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2293621856
Short name T587
Test name
Test status
Simulation time 105527176630 ps
CPU time 181.43 seconds
Started Jun 02 01:11:24 PM PDT 24
Finished Jun 02 01:14:26 PM PDT 24
Peak memory 200396 kb
Host smart-b9616f80-5b15-4b16-873f-089572403086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293621856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2293621856
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2437583791
Short name T531
Test name
Test status
Simulation time 60776938183 ps
CPU time 108.39 seconds
Started Jun 02 01:11:23 PM PDT 24
Finished Jun 02 01:13:11 PM PDT 24
Peak memory 200412 kb
Host smart-1f651ae1-7c8a-481a-a3d7-e27db7ce9f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437583791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2437583791
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3944578795
Short name T382
Test name
Test status
Simulation time 150933145111 ps
CPU time 109.72 seconds
Started Jun 02 01:11:24 PM PDT 24
Finished Jun 02 01:13:14 PM PDT 24
Peak memory 200332 kb
Host smart-734318ee-e429-4a20-9be0-1e47cebe995c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944578795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3944578795
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2149071433
Short name T627
Test name
Test status
Simulation time 13408560534 ps
CPU time 4.94 seconds
Started Jun 02 01:11:31 PM PDT 24
Finished Jun 02 01:11:37 PM PDT 24
Peak memory 196944 kb
Host smart-792ab5d7-67b5-454b-a27f-901d1cb1eacb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149071433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2149071433
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.4122240737
Short name T822
Test name
Test status
Simulation time 111127913121 ps
CPU time 473.2 seconds
Started Jun 02 01:11:36 PM PDT 24
Finished Jun 02 01:19:30 PM PDT 24
Peak memory 200248 kb
Host smart-d3e66aa9-d8ff-4822-aa76-a1fd17b93795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122240737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4122240737
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1825752914
Short name T434
Test name
Test status
Simulation time 1263051560 ps
CPU time 4.69 seconds
Started Jun 02 01:11:29 PM PDT 24
Finished Jun 02 01:11:34 PM PDT 24
Peak memory 198908 kb
Host smart-e824e14c-be0f-486a-ad6c-d3efa3ab7961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825752914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1825752914
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3130872433
Short name T83
Test name
Test status
Simulation time 379711116809 ps
CPU time 43.43 seconds
Started Jun 02 01:11:29 PM PDT 24
Finished Jun 02 01:12:13 PM PDT 24
Peak memory 200788 kb
Host smart-c4cf18cd-8e47-4af6-9bec-da4ce34c68d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130872433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3130872433
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.4053322592
Short name T1069
Test name
Test status
Simulation time 16701651789 ps
CPU time 258.01 seconds
Started Jun 02 01:11:30 PM PDT 24
Finished Jun 02 01:15:48 PM PDT 24
Peak memory 200412 kb
Host smart-86c4c250-cb17-4fff-816c-c97d499cfd84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053322592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.4053322592
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1406047145
Short name T1115
Test name
Test status
Simulation time 6816366875 ps
CPU time 15.69 seconds
Started Jun 02 01:11:29 PM PDT 24
Finished Jun 02 01:11:45 PM PDT 24
Peak memory 198532 kb
Host smart-538d08b1-7eb6-410e-951a-414c47c3da4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1406047145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1406047145
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2372676216
Short name T248
Test name
Test status
Simulation time 10716519815 ps
CPU time 7.22 seconds
Started Jun 02 01:11:36 PM PDT 24
Finished Jun 02 01:11:44 PM PDT 24
Peak memory 200260 kb
Host smart-f9880e93-2b55-4050-ad24-a71d2a6cbcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372676216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2372676216
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.133014802
Short name T308
Test name
Test status
Simulation time 36202346425 ps
CPU time 13.01 seconds
Started Jun 02 01:11:28 PM PDT 24
Finished Jun 02 01:11:42 PM PDT 24
Peak memory 196636 kb
Host smart-a43948b3-d713-4ea0-92c1-ac20d35129d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133014802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.133014802
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1211500796
Short name T82
Test name
Test status
Simulation time 315219783 ps
CPU time 1.02 seconds
Started Jun 02 01:11:30 PM PDT 24
Finished Jun 02 01:11:31 PM PDT 24
Peak memory 218700 kb
Host smart-03343a93-b2fb-483e-be4e-eb7e2eec5e1f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211500796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1211500796
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2644737619
Short name T296
Test name
Test status
Simulation time 511026861 ps
CPU time 1.31 seconds
Started Jun 02 01:11:24 PM PDT 24
Finished Jun 02 01:11:25 PM PDT 24
Peak memory 199148 kb
Host smart-2435a042-a598-46b8-992f-428f0f7426c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644737619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2644737619
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3011047356
Short name T239
Test name
Test status
Simulation time 373215552776 ps
CPU time 785.27 seconds
Started Jun 02 01:11:27 PM PDT 24
Finished Jun 02 01:24:33 PM PDT 24
Peak memory 200316 kb
Host smart-b71a23df-84a0-4943-8a24-a59bf6e714e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011047356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3011047356
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3998363884
Short name T402
Test name
Test status
Simulation time 8854710710 ps
CPU time 49.76 seconds
Started Jun 02 01:11:28 PM PDT 24
Finished Jun 02 01:12:18 PM PDT 24
Peak memory 215856 kb
Host smart-ebc46f49-3589-406e-b778-b17d13506b2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998363884 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3998363884
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.129158865
Short name T956
Test name
Test status
Simulation time 2659410745 ps
CPU time 2.32 seconds
Started Jun 02 01:11:28 PM PDT 24
Finished Jun 02 01:11:31 PM PDT 24
Peak memory 199340 kb
Host smart-6353189e-70a5-4875-b203-89b4edcb75cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129158865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.129158865
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3462102940
Short name T569
Test name
Test status
Simulation time 24051617145 ps
CPU time 21.1 seconds
Started Jun 02 01:11:25 PM PDT 24
Finished Jun 02 01:11:46 PM PDT 24
Peak memory 200132 kb
Host smart-5e8ab2d3-a100-47e7-8af3-47e365a26438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462102940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3462102940
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2289819969
Short name T646
Test name
Test status
Simulation time 14784227 ps
CPU time 0.58 seconds
Started Jun 02 01:14:28 PM PDT 24
Finished Jun 02 01:14:29 PM PDT 24
Peak memory 195772 kb
Host smart-607c0817-6790-4a36-bb49-75c128294634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289819969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2289819969
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1721320491
Short name T891
Test name
Test status
Simulation time 80971051715 ps
CPU time 80.54 seconds
Started Jun 02 01:14:23 PM PDT 24
Finished Jun 02 01:15:43 PM PDT 24
Peak memory 200356 kb
Host smart-fedf62a2-91d2-4624-951d-96b25a413709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721320491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1721320491
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1315173292
Short name T660
Test name
Test status
Simulation time 110422153682 ps
CPU time 46.9 seconds
Started Jun 02 01:14:23 PM PDT 24
Finished Jun 02 01:15:10 PM PDT 24
Peak memory 200136 kb
Host smart-7b8cd4d5-685e-4f4c-8951-e6e48266ed6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315173292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1315173292
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.4079868924
Short name T1031
Test name
Test status
Simulation time 61796639915 ps
CPU time 26.02 seconds
Started Jun 02 01:14:22 PM PDT 24
Finished Jun 02 01:14:48 PM PDT 24
Peak memory 200268 kb
Host smart-43009c2c-f88b-4b06-ba08-24ba004b5906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079868924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.4079868924
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3982596881
Short name T651
Test name
Test status
Simulation time 48153547059 ps
CPU time 42.78 seconds
Started Jun 02 01:14:22 PM PDT 24
Finished Jun 02 01:15:05 PM PDT 24
Peak memory 200132 kb
Host smart-4ecd78d5-e2f7-4bb0-8ecc-7eee6d3f7ba8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982596881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3982596881
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.4212369693
Short name T303
Test name
Test status
Simulation time 100868979155 ps
CPU time 198.42 seconds
Started Jun 02 01:14:22 PM PDT 24
Finished Jun 02 01:17:40 PM PDT 24
Peak memory 200388 kb
Host smart-e05054d4-aa91-4a65-ba9c-b7da4c606ae9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4212369693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.4212369693
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.847469177
Short name T345
Test name
Test status
Simulation time 4587881405 ps
CPU time 4.25 seconds
Started Jun 02 01:14:23 PM PDT 24
Finished Jun 02 01:14:27 PM PDT 24
Peak memory 200324 kb
Host smart-795cf881-6b47-4998-9eaa-ceae8c1330d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847469177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.847469177
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2734473236
Short name T801
Test name
Test status
Simulation time 67581352740 ps
CPU time 24.36 seconds
Started Jun 02 01:14:24 PM PDT 24
Finished Jun 02 01:14:48 PM PDT 24
Peak memory 200548 kb
Host smart-348e9d7e-6878-4511-8f50-9bb044be2435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734473236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2734473236
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.2190514164
Short name T1084
Test name
Test status
Simulation time 19574404911 ps
CPU time 1019.19 seconds
Started Jun 02 01:14:23 PM PDT 24
Finished Jun 02 01:31:23 PM PDT 24
Peak memory 200372 kb
Host smart-701b932e-93ab-418d-85cb-7cbe41873710
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190514164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2190514164
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2520514513
Short name T1111
Test name
Test status
Simulation time 7375114070 ps
CPU time 6.8 seconds
Started Jun 02 01:14:21 PM PDT 24
Finished Jun 02 01:14:29 PM PDT 24
Peak memory 198456 kb
Host smart-513fc41a-db37-4d19-9d03-91ea30d013db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2520514513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2520514513
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1964744991
Short name T5
Test name
Test status
Simulation time 34908234667 ps
CPU time 38.08 seconds
Started Jun 02 01:14:21 PM PDT 24
Finished Jun 02 01:14:59 PM PDT 24
Peak memory 200356 kb
Host smart-02bb171d-69d5-4e0c-b593-439b5521856c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964744991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1964744991
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3790621416
Short name T922
Test name
Test status
Simulation time 4071298012 ps
CPU time 4.46 seconds
Started Jun 02 01:14:21 PM PDT 24
Finished Jun 02 01:14:25 PM PDT 24
Peak memory 196376 kb
Host smart-159e7c39-4f2d-4f9c-9550-aab62a0efafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790621416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3790621416
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2906332652
Short name T1099
Test name
Test status
Simulation time 296091581 ps
CPU time 1.5 seconds
Started Jun 02 01:14:15 PM PDT 24
Finished Jun 02 01:14:17 PM PDT 24
Peak memory 199268 kb
Host smart-0273eb18-b6ff-4a8f-8ff8-7e341b5d715e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906332652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2906332652
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.302180101
Short name T337
Test name
Test status
Simulation time 281349507576 ps
CPU time 386.05 seconds
Started Jun 02 01:14:30 PM PDT 24
Finished Jun 02 01:20:56 PM PDT 24
Peak memory 208976 kb
Host smart-09c63ae8-f092-47ea-bd60-0607441607da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302180101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.302180101
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.488941352
Short name T46
Test name
Test status
Simulation time 142315399581 ps
CPU time 859.98 seconds
Started Jun 02 01:14:28 PM PDT 24
Finished Jun 02 01:28:49 PM PDT 24
Peak memory 225348 kb
Host smart-14ba2b49-2671-4c7d-8a20-260f21633e39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488941352 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.488941352
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.4001878893
Short name T610
Test name
Test status
Simulation time 2016113907 ps
CPU time 3.78 seconds
Started Jun 02 01:14:22 PM PDT 24
Finished Jun 02 01:14:26 PM PDT 24
Peak memory 199028 kb
Host smart-35e3b631-ee82-4945-8053-955dd2205a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001878893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.4001878893
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.106410905
Short name T442
Test name
Test status
Simulation time 23527595447 ps
CPU time 11.52 seconds
Started Jun 02 01:14:16 PM PDT 24
Finished Jun 02 01:14:27 PM PDT 24
Peak memory 200340 kb
Host smart-3d422325-f994-45ae-ad85-d5af254d5631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106410905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.106410905
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2600783524
Short name T719
Test name
Test status
Simulation time 6744600142 ps
CPU time 7.11 seconds
Started Jun 02 01:21:41 PM PDT 24
Finished Jun 02 01:21:48 PM PDT 24
Peak memory 200344 kb
Host smart-99ad85b7-23a0-4d1a-8a5f-b9d834e4fbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600783524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2600783524
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3792274164
Short name T547
Test name
Test status
Simulation time 218353463746 ps
CPU time 232.97 seconds
Started Jun 02 01:21:40 PM PDT 24
Finished Jun 02 01:25:33 PM PDT 24
Peak memory 200344 kb
Host smart-3db7abbd-8418-469f-b473-0527c2b36ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792274164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3792274164
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3482773849
Short name T1169
Test name
Test status
Simulation time 92034209529 ps
CPU time 160.22 seconds
Started Jun 02 01:21:46 PM PDT 24
Finished Jun 02 01:24:27 PM PDT 24
Peak memory 200328 kb
Host smart-c13fa815-b85e-49fc-8cc5-8a29de02de75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482773849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3482773849
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1236878219
Short name T1037
Test name
Test status
Simulation time 24305613484 ps
CPU time 49.32 seconds
Started Jun 02 01:21:47 PM PDT 24
Finished Jun 02 01:22:36 PM PDT 24
Peak memory 200392 kb
Host smart-0f8e446b-e7fd-41ec-82b7-256243227966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236878219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1236878219
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3533502889
Short name T567
Test name
Test status
Simulation time 22409404865 ps
CPU time 8.99 seconds
Started Jun 02 01:21:47 PM PDT 24
Finished Jun 02 01:21:56 PM PDT 24
Peak memory 199400 kb
Host smart-ad335f1c-8de2-4b74-b8da-3936b4823dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533502889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3533502889
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1955405742
Short name T219
Test name
Test status
Simulation time 107416190214 ps
CPU time 170.32 seconds
Started Jun 02 01:21:46 PM PDT 24
Finished Jun 02 01:24:37 PM PDT 24
Peak memory 200412 kb
Host smart-b2344b8f-218d-4566-a285-fc3eb2134cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955405742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1955405742
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.960080600
Short name T23
Test name
Test status
Simulation time 11485048 ps
CPU time 0.56 seconds
Started Jun 02 01:14:36 PM PDT 24
Finished Jun 02 01:14:37 PM PDT 24
Peak memory 195788 kb
Host smart-d4171bfa-1984-4ab8-bfe1-6ee05e79eb70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960080600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.960080600
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2507465587
Short name T648
Test name
Test status
Simulation time 119361735667 ps
CPU time 21.65 seconds
Started Jun 02 01:14:28 PM PDT 24
Finished Jun 02 01:14:50 PM PDT 24
Peak memory 200380 kb
Host smart-8c98b5ae-1c13-4968-8641-ac6384bc3eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507465587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2507465587
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.592498907
Short name T443
Test name
Test status
Simulation time 36143444564 ps
CPU time 31.02 seconds
Started Jun 02 01:14:28 PM PDT 24
Finished Jun 02 01:14:59 PM PDT 24
Peak memory 200232 kb
Host smart-45f00c61-87db-4ea8-88eb-908815054ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592498907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.592498907
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1052364682
Short name T1086
Test name
Test status
Simulation time 134934050257 ps
CPU time 56.49 seconds
Started Jun 02 01:14:28 PM PDT 24
Finished Jun 02 01:15:25 PM PDT 24
Peak memory 200412 kb
Host smart-09166f68-12db-4a27-93c4-113332ee4f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052364682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1052364682
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.4060546502
Short name T1127
Test name
Test status
Simulation time 27767991465 ps
CPU time 12.12 seconds
Started Jun 02 01:14:35 PM PDT 24
Finished Jun 02 01:14:48 PM PDT 24
Peak memory 198328 kb
Host smart-7e6e97d6-2e52-4e96-882a-8b227235cf7c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060546502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.4060546502
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2241270312
Short name T976
Test name
Test status
Simulation time 231987950618 ps
CPU time 189.32 seconds
Started Jun 02 01:14:36 PM PDT 24
Finished Jun 02 01:17:46 PM PDT 24
Peak memory 200344 kb
Host smart-b9b89c84-c056-4953-b0f7-b12ccff257ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2241270312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2241270312
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.728469301
Short name T574
Test name
Test status
Simulation time 4912145232 ps
CPU time 10.59 seconds
Started Jun 02 01:14:36 PM PDT 24
Finished Jun 02 01:14:47 PM PDT 24
Peak memory 198964 kb
Host smart-99afdf6e-a488-45f8-bee7-899fbf2517eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728469301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.728469301
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.2000588903
Short name T588
Test name
Test status
Simulation time 58185722049 ps
CPU time 98.03 seconds
Started Jun 02 01:14:37 PM PDT 24
Finished Jun 02 01:16:15 PM PDT 24
Peak memory 200312 kb
Host smart-cb63c7cd-4b00-44ea-b2ab-50e519a83321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000588903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2000588903
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.726475079
Short name T759
Test name
Test status
Simulation time 11772876601 ps
CPU time 604.35 seconds
Started Jun 02 01:14:35 PM PDT 24
Finished Jun 02 01:24:39 PM PDT 24
Peak memory 200312 kb
Host smart-320164f5-3fae-4e23-a073-94cd7a210b2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726475079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.726475079
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.543073023
Short name T904
Test name
Test status
Simulation time 7441585665 ps
CPU time 33.36 seconds
Started Jun 02 01:14:35 PM PDT 24
Finished Jun 02 01:15:09 PM PDT 24
Peak memory 199688 kb
Host smart-110be3af-9d65-495a-836c-29321c2d06dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=543073023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.543073023
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3087337235
Short name T1134
Test name
Test status
Simulation time 15572879597 ps
CPU time 31.28 seconds
Started Jun 02 01:14:37 PM PDT 24
Finished Jun 02 01:15:09 PM PDT 24
Peak memory 200344 kb
Host smart-615c53e0-3a23-43c8-90ec-8d4c77230a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087337235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3087337235
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2318213705
Short name T743
Test name
Test status
Simulation time 4047911475 ps
CPU time 4.05 seconds
Started Jun 02 01:14:37 PM PDT 24
Finished Jun 02 01:14:41 PM PDT 24
Peak memory 196304 kb
Host smart-a6d24049-10c1-4da8-b08f-80eee28d44f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318213705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2318213705
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2898965566
Short name T671
Test name
Test status
Simulation time 290469467 ps
CPU time 1.53 seconds
Started Jun 02 01:14:30 PM PDT 24
Finished Jun 02 01:14:32 PM PDT 24
Peak memory 198904 kb
Host smart-5bc4ef41-44fa-40e3-86ca-dc392687af89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898965566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2898965566
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2024760976
Short name T934
Test name
Test status
Simulation time 454083819121 ps
CPU time 123.06 seconds
Started Jun 02 01:14:34 PM PDT 24
Finished Jun 02 01:16:38 PM PDT 24
Peak memory 208740 kb
Host smart-8abbfc0e-ae96-4e1c-8dca-6a367e6bbede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024760976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2024760976
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3395487156
Short name T781
Test name
Test status
Simulation time 15092977667 ps
CPU time 201.88 seconds
Started Jun 02 01:14:35 PM PDT 24
Finished Jun 02 01:17:57 PM PDT 24
Peak memory 215864 kb
Host smart-9ce00d3d-8938-4539-80e2-78180aa01bfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395487156 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3395487156
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3148265740
Short name T514
Test name
Test status
Simulation time 7377935602 ps
CPU time 7.48 seconds
Started Jun 02 01:14:35 PM PDT 24
Finished Jun 02 01:14:43 PM PDT 24
Peak memory 199776 kb
Host smart-85e57a68-1aaf-4d2e-8ead-afb374a5391b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148265740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3148265740
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2264274119
Short name T86
Test name
Test status
Simulation time 118245912600 ps
CPU time 72.36 seconds
Started Jun 02 01:14:30 PM PDT 24
Finished Jun 02 01:15:43 PM PDT 24
Peak memory 200352 kb
Host smart-89d678ad-86c0-473f-bb65-dae7f75bbd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264274119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2264274119
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1498456359
Short name T1025
Test name
Test status
Simulation time 113384013730 ps
CPU time 31.07 seconds
Started Jun 02 01:21:46 PM PDT 24
Finished Jun 02 01:22:18 PM PDT 24
Peak memory 200416 kb
Host smart-bba689eb-eb07-49a7-adf8-a4447a8688c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498456359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1498456359
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3524047903
Short name T249
Test name
Test status
Simulation time 20368043137 ps
CPU time 18.45 seconds
Started Jun 02 01:21:54 PM PDT 24
Finished Jun 02 01:22:13 PM PDT 24
Peak memory 200424 kb
Host smart-cbdde90c-9d7e-427e-bc01-e00f02eaa9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524047903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3524047903
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.420823872
Short name T772
Test name
Test status
Simulation time 61829168677 ps
CPU time 19.38 seconds
Started Jun 02 01:21:55 PM PDT 24
Finished Jun 02 01:22:14 PM PDT 24
Peak memory 200336 kb
Host smart-7eeaaf6b-94ea-4f69-b734-c21ba2da8565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420823872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.420823872
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2332528764
Short name T723
Test name
Test status
Simulation time 146553574732 ps
CPU time 165.73 seconds
Started Jun 02 01:21:54 PM PDT 24
Finished Jun 02 01:24:40 PM PDT 24
Peak memory 200424 kb
Host smart-2ac1bbe8-fe8b-403b-bc43-a71fe0ff677d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332528764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2332528764
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.4034509988
Short name T218
Test name
Test status
Simulation time 48020774057 ps
CPU time 18.93 seconds
Started Jun 02 01:21:56 PM PDT 24
Finished Jun 02 01:22:15 PM PDT 24
Peak memory 200364 kb
Host smart-dfb9a1fd-aa89-4964-9d0e-2cfaaacbc23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034509988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.4034509988
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2905599287
Short name T958
Test name
Test status
Simulation time 151639380294 ps
CPU time 29.32 seconds
Started Jun 02 01:21:53 PM PDT 24
Finished Jun 02 01:22:23 PM PDT 24
Peak memory 200448 kb
Host smart-594cd8ca-1034-4b19-b868-eb78890206d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905599287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2905599287
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1846347824
Short name T87
Test name
Test status
Simulation time 61433198608 ps
CPU time 56.48 seconds
Started Jun 02 01:21:54 PM PDT 24
Finished Jun 02 01:22:50 PM PDT 24
Peak memory 200076 kb
Host smart-7d1e3a92-f725-4352-b14d-69ffd744259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846347824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1846347824
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1596061018
Short name T203
Test name
Test status
Simulation time 20974736738 ps
CPU time 20.21 seconds
Started Jun 02 01:21:55 PM PDT 24
Finished Jun 02 01:22:15 PM PDT 24
Peak memory 200364 kb
Host smart-cce8dcec-c0aa-4304-8727-8b0bddc6207d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596061018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1596061018
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1443969015
Short name T1106
Test name
Test status
Simulation time 90640594386 ps
CPU time 164.58 seconds
Started Jun 02 01:22:02 PM PDT 24
Finished Jun 02 01:24:47 PM PDT 24
Peak memory 200404 kb
Host smart-3fd02cb7-9771-4b98-a034-4d4f3a85fb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443969015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1443969015
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.586710999
Short name T1126
Test name
Test status
Simulation time 20202032 ps
CPU time 0.56 seconds
Started Jun 02 01:14:51 PM PDT 24
Finished Jun 02 01:14:52 PM PDT 24
Peak memory 195760 kb
Host smart-13510aca-21ff-442e-9196-1e3b32f5dbb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586710999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.586710999
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.401253241
Short name T603
Test name
Test status
Simulation time 39991236590 ps
CPU time 51.51 seconds
Started Jun 02 01:14:41 PM PDT 24
Finished Jun 02 01:15:32 PM PDT 24
Peak memory 200356 kb
Host smart-5d0ed033-7e29-4581-a724-96a2488a8652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401253241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.401253241
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.4098283494
Short name T146
Test name
Test status
Simulation time 75069894811 ps
CPU time 73.85 seconds
Started Jun 02 01:14:43 PM PDT 24
Finished Jun 02 01:15:57 PM PDT 24
Peak memory 200412 kb
Host smart-6d4a2c12-b1ca-4606-8211-c6852c22695f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098283494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.4098283494
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3844888657
Short name T773
Test name
Test status
Simulation time 76997037017 ps
CPU time 60.69 seconds
Started Jun 02 01:14:41 PM PDT 24
Finished Jun 02 01:15:42 PM PDT 24
Peak memory 200264 kb
Host smart-3a1174a9-dead-4521-ba57-dfc42fdce5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844888657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3844888657
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.4073182192
Short name T838
Test name
Test status
Simulation time 11762707299 ps
CPU time 3.23 seconds
Started Jun 02 01:14:43 PM PDT 24
Finished Jun 02 01:14:47 PM PDT 24
Peak memory 197048 kb
Host smart-a861006a-7e85-4f3b-b4c6-210f4572bd1c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073182192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.4073182192
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3171831685
Short name T712
Test name
Test status
Simulation time 80838896844 ps
CPU time 197.06 seconds
Started Jun 02 01:14:50 PM PDT 24
Finished Jun 02 01:18:07 PM PDT 24
Peak memory 200360 kb
Host smart-69ae1eca-a1a6-4423-8ca0-77d28d2765c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3171831685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3171831685
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2707536400
Short name T985
Test name
Test status
Simulation time 4344918753 ps
CPU time 3.1 seconds
Started Jun 02 01:14:48 PM PDT 24
Finished Jun 02 01:14:52 PM PDT 24
Peak memory 199088 kb
Host smart-e826bbd6-92a0-421e-9eeb-4d76875afc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707536400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2707536400
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3459183313
Short name T482
Test name
Test status
Simulation time 331818835322 ps
CPU time 125.13 seconds
Started Jun 02 01:14:43 PM PDT 24
Finished Jun 02 01:16:49 PM PDT 24
Peak memory 208760 kb
Host smart-779e1bfd-f532-4894-bcce-450425783258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459183313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3459183313
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1588876236
Short name T971
Test name
Test status
Simulation time 9013890742 ps
CPU time 398.72 seconds
Started Jun 02 01:14:48 PM PDT 24
Finished Jun 02 01:21:27 PM PDT 24
Peak memory 200356 kb
Host smart-2a0fd5b0-5562-4038-b8a1-3f1af4b7c59b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1588876236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1588876236
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2357201528
Short name T554
Test name
Test status
Simulation time 5555080360 ps
CPU time 46.53 seconds
Started Jun 02 01:14:42 PM PDT 24
Finished Jun 02 01:15:28 PM PDT 24
Peak memory 198436 kb
Host smart-f6c79dda-d148-4b22-83c4-f73a1df441fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2357201528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2357201528
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1087067296
Short name T269
Test name
Test status
Simulation time 62514834745 ps
CPU time 46.44 seconds
Started Jun 02 01:14:43 PM PDT 24
Finished Jun 02 01:15:30 PM PDT 24
Peak memory 200320 kb
Host smart-dfda11e9-ee25-4bb9-9fb7-53b2ba189f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087067296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1087067296
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.217249358
Short name T250
Test name
Test status
Simulation time 2027740511 ps
CPU time 2.34 seconds
Started Jun 02 01:14:44 PM PDT 24
Finished Jun 02 01:14:46 PM PDT 24
Peak memory 195732 kb
Host smart-99510a3c-6b26-4e2d-a591-dce8221ce1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217249358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.217249358
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.494106792
Short name T1001
Test name
Test status
Simulation time 718573777 ps
CPU time 4.16 seconds
Started Jun 02 01:14:43 PM PDT 24
Finished Jun 02 01:14:48 PM PDT 24
Peak memory 199292 kb
Host smart-92598c59-9bd6-4b92-99bb-aa59f9ce74f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494106792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.494106792
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.123481890
Short name T169
Test name
Test status
Simulation time 462244142076 ps
CPU time 75.93 seconds
Started Jun 02 01:14:47 PM PDT 24
Finished Jun 02 01:16:03 PM PDT 24
Peak memory 200356 kb
Host smart-90b11ec2-9724-4976-953b-7cb09ea75bf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123481890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.123481890
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1740775588
Short name T44
Test name
Test status
Simulation time 58513718705 ps
CPU time 399.41 seconds
Started Jun 02 01:14:49 PM PDT 24
Finished Jun 02 01:21:29 PM PDT 24
Peak memory 217056 kb
Host smart-a625683d-0923-43fd-b2c0-c4a0fb9cb70d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740775588 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1740775588
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1250042070
Short name T1014
Test name
Test status
Simulation time 2045848753 ps
CPU time 1.99 seconds
Started Jun 02 01:14:41 PM PDT 24
Finished Jun 02 01:14:44 PM PDT 24
Peak memory 199544 kb
Host smart-ef2180d5-ac24-4fb1-8ca6-5f9027461dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250042070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1250042070
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.144301581
Short name T549
Test name
Test status
Simulation time 11167567869 ps
CPU time 18.15 seconds
Started Jun 02 01:14:42 PM PDT 24
Finished Jun 02 01:15:01 PM PDT 24
Peak memory 200356 kb
Host smart-ed7cc97f-3322-489a-9935-57967c7942bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144301581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.144301581
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.51123693
Short name T194
Test name
Test status
Simulation time 18710239623 ps
CPU time 29.27 seconds
Started Jun 02 01:22:01 PM PDT 24
Finished Jun 02 01:22:30 PM PDT 24
Peak memory 200372 kb
Host smart-55d7adff-9a16-4d10-890e-53b3933d24c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51123693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.51123693
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.826384477
Short name T763
Test name
Test status
Simulation time 51454290130 ps
CPU time 24.68 seconds
Started Jun 02 01:22:01 PM PDT 24
Finished Jun 02 01:22:26 PM PDT 24
Peak memory 200348 kb
Host smart-10c5f840-c372-410c-a5f7-e6d30d6d3dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826384477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.826384477
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.65645723
Short name T222
Test name
Test status
Simulation time 71212225550 ps
CPU time 134.23 seconds
Started Jun 02 01:22:00 PM PDT 24
Finished Jun 02 01:24:14 PM PDT 24
Peak memory 200300 kb
Host smart-4d724659-5b26-4ad1-b5e3-bcd3bdeb8c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65645723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.65645723
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1438203337
Short name T225
Test name
Test status
Simulation time 23636634763 ps
CPU time 17.36 seconds
Started Jun 02 01:22:00 PM PDT 24
Finished Jun 02 01:22:17 PM PDT 24
Peak memory 200200 kb
Host smart-5f53779a-938f-40a4-b1d2-525070ee9b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438203337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1438203337
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.143469271
Short name T709
Test name
Test status
Simulation time 32717165575 ps
CPU time 69.19 seconds
Started Jun 02 01:21:59 PM PDT 24
Finished Jun 02 01:23:09 PM PDT 24
Peak memory 200416 kb
Host smart-f41becb2-cc55-4198-8c9f-494eec64eaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143469271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.143469271
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.194919190
Short name T42
Test name
Test status
Simulation time 8698965967 ps
CPU time 17.23 seconds
Started Jun 02 01:22:01 PM PDT 24
Finished Jun 02 01:22:18 PM PDT 24
Peak memory 200384 kb
Host smart-7762e799-ee1e-45ff-8e06-e14aa5bf5ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194919190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.194919190
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.4181088897
Short name T570
Test name
Test status
Simulation time 163068377295 ps
CPU time 26.9 seconds
Started Jun 02 01:22:00 PM PDT 24
Finished Jun 02 01:22:28 PM PDT 24
Peak memory 200292 kb
Host smart-b740b7df-ab87-4813-977c-b4b783454466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181088897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.4181088897
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3260963404
Short name T847
Test name
Test status
Simulation time 238428792838 ps
CPU time 133.16 seconds
Started Jun 02 01:22:00 PM PDT 24
Finished Jun 02 01:24:14 PM PDT 24
Peak memory 200340 kb
Host smart-d7d865d4-7803-48c2-8e35-2cfcc956c268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260963404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3260963404
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3117703679
Short name T24
Test name
Test status
Simulation time 14798011 ps
CPU time 0.56 seconds
Started Jun 02 01:15:04 PM PDT 24
Finished Jun 02 01:15:05 PM PDT 24
Peak memory 195696 kb
Host smart-73bd02ef-f3d2-44eb-af22-ea07de7d826f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117703679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3117703679
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3168467229
Short name T946
Test name
Test status
Simulation time 116753326728 ps
CPU time 82.53 seconds
Started Jun 02 01:14:57 PM PDT 24
Finished Jun 02 01:16:20 PM PDT 24
Peak memory 200348 kb
Host smart-383febd7-a972-4a24-b2fb-d73a6f80ca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168467229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3168467229
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3705870906
Short name T1125
Test name
Test status
Simulation time 21915431199 ps
CPU time 35.64 seconds
Started Jun 02 01:14:55 PM PDT 24
Finished Jun 02 01:15:31 PM PDT 24
Peak memory 199972 kb
Host smart-5eaceb25-4f90-40f4-baf9-718b0fd4f498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705870906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3705870906
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.442080896
Short name T1109
Test name
Test status
Simulation time 218638032764 ps
CPU time 106.86 seconds
Started Jun 02 01:14:57 PM PDT 24
Finished Jun 02 01:16:44 PM PDT 24
Peak memory 200300 kb
Host smart-d6c4daf0-4cf5-49d5-b421-a246c11d8a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442080896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.442080896
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.4156965914
Short name T871
Test name
Test status
Simulation time 15720228326 ps
CPU time 15.88 seconds
Started Jun 02 01:14:54 PM PDT 24
Finished Jun 02 01:15:10 PM PDT 24
Peak memory 197808 kb
Host smart-9bdff5c3-f84f-43e9-8f7f-a11ea49be0d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156965914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.4156965914
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1439597727
Short name T492
Test name
Test status
Simulation time 81805352245 ps
CPU time 213.7 seconds
Started Jun 02 01:15:01 PM PDT 24
Finished Jun 02 01:18:35 PM PDT 24
Peak memory 200400 kb
Host smart-89c83f9d-a15c-4535-892f-8669297ab134
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1439597727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1439597727
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.346941467
Short name T840
Test name
Test status
Simulation time 12219867394 ps
CPU time 13.49 seconds
Started Jun 02 01:15:03 PM PDT 24
Finished Jun 02 01:15:17 PM PDT 24
Peak memory 200344 kb
Host smart-b61e6995-ef92-46db-a691-d88847d9a7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346941467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.346941467
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3744000265
Short name T1179
Test name
Test status
Simulation time 22686180091 ps
CPU time 40.29 seconds
Started Jun 02 01:14:55 PM PDT 24
Finished Jun 02 01:15:36 PM PDT 24
Peak memory 198816 kb
Host smart-18ac2223-a337-412f-95e3-666de125ac24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744000265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3744000265
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.3993613331
Short name T867
Test name
Test status
Simulation time 26571063673 ps
CPU time 128.42 seconds
Started Jun 02 01:15:01 PM PDT 24
Finished Jun 02 01:17:10 PM PDT 24
Peak memory 200384 kb
Host smart-dc178f0e-35e7-40aa-b1b4-0db77cdf2745
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3993613331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3993613331
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3387973541
Short name T360
Test name
Test status
Simulation time 6509169053 ps
CPU time 16.06 seconds
Started Jun 02 01:14:55 PM PDT 24
Finished Jun 02 01:15:12 PM PDT 24
Peak memory 199704 kb
Host smart-3f6d7886-8082-403f-abd7-cf37b3763f77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387973541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3387973541
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.329163355
Short name T680
Test name
Test status
Simulation time 180368184367 ps
CPU time 108.23 seconds
Started Jun 02 01:15:01 PM PDT 24
Finished Jun 02 01:16:50 PM PDT 24
Peak memory 200284 kb
Host smart-ba68f5ca-e9c4-4ffb-9ea0-64b19931f15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329163355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.329163355
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1024644634
Short name T349
Test name
Test status
Simulation time 4391537252 ps
CPU time 7.98 seconds
Started Jun 02 01:15:02 PM PDT 24
Finished Jun 02 01:15:10 PM PDT 24
Peak memory 196420 kb
Host smart-115565f5-dcd3-401e-9079-838f04384422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024644634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1024644634
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3324768340
Short name T282
Test name
Test status
Simulation time 622825625 ps
CPU time 3.05 seconds
Started Jun 02 01:14:48 PM PDT 24
Finished Jun 02 01:14:52 PM PDT 24
Peak memory 198596 kb
Host smart-c6afbbae-1b7d-4c86-8935-175a7e115329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324768340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3324768340
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.2707092990
Short name T728
Test name
Test status
Simulation time 28018784599 ps
CPU time 982.17 seconds
Started Jun 02 01:15:07 PM PDT 24
Finished Jun 02 01:31:30 PM PDT 24
Peak memory 200268 kb
Host smart-6b1b04df-6132-4b3f-a520-92893bd158a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707092990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2707092990
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3014119580
Short name T886
Test name
Test status
Simulation time 25776004010 ps
CPU time 247.56 seconds
Started Jun 02 01:15:03 PM PDT 24
Finished Jun 02 01:19:11 PM PDT 24
Peak memory 214760 kb
Host smart-502d9c79-3fda-411b-b811-466da2435f7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014119580 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3014119580
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.784901956
Short name T566
Test name
Test status
Simulation time 7483803541 ps
CPU time 21.53 seconds
Started Jun 02 01:15:01 PM PDT 24
Finished Jun 02 01:15:23 PM PDT 24
Peak memory 200352 kb
Host smart-69229f73-a703-4b7d-94fb-fb59e40b7c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784901956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.784901956
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.4220951645
Short name T612
Test name
Test status
Simulation time 105605400558 ps
CPU time 14.06 seconds
Started Jun 02 01:14:50 PM PDT 24
Finished Jun 02 01:15:04 PM PDT 24
Peak memory 199964 kb
Host smart-7f9efd38-4a28-4064-805c-f8001863a733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220951645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.4220951645
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2426502276
Short name T202
Test name
Test status
Simulation time 102949861841 ps
CPU time 37.19 seconds
Started Jun 02 01:22:01 PM PDT 24
Finished Jun 02 01:22:38 PM PDT 24
Peak memory 200084 kb
Host smart-45ce4684-fa53-4a93-98c1-7e601be526a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426502276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2426502276
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1776941654
Short name T733
Test name
Test status
Simulation time 153275646280 ps
CPU time 239.55 seconds
Started Jun 02 01:22:02 PM PDT 24
Finished Jun 02 01:26:02 PM PDT 24
Peak memory 200404 kb
Host smart-d44fec21-069e-4b0a-a85a-adc4fea60bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776941654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1776941654
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.4016007910
Short name T1022
Test name
Test status
Simulation time 156906106204 ps
CPU time 119.92 seconds
Started Jun 02 01:22:03 PM PDT 24
Finished Jun 02 01:24:04 PM PDT 24
Peak memory 200360 kb
Host smart-65c8803a-2768-445d-b59f-60fae0d54e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016007910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.4016007910
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2826851439
Short name T783
Test name
Test status
Simulation time 20623229111 ps
CPU time 36.39 seconds
Started Jun 02 01:22:00 PM PDT 24
Finished Jun 02 01:22:37 PM PDT 24
Peak memory 200392 kb
Host smart-6f76a134-0983-41de-8366-bfb03af36c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826851439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2826851439
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2651427861
Short name T100
Test name
Test status
Simulation time 160565685607 ps
CPU time 32.16 seconds
Started Jun 02 01:22:08 PM PDT 24
Finished Jun 02 01:22:41 PM PDT 24
Peak memory 200408 kb
Host smart-cac077f9-472b-4b8e-a8be-798557731a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651427861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2651427861
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.567534986
Short name T178
Test name
Test status
Simulation time 99373540651 ps
CPU time 31.76 seconds
Started Jun 02 01:22:10 PM PDT 24
Finished Jun 02 01:22:42 PM PDT 24
Peak memory 200292 kb
Host smart-d60ee17d-1c46-4751-a702-d5ad28863ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567534986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.567534986
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3710356791
Short name T487
Test name
Test status
Simulation time 103719619844 ps
CPU time 49.79 seconds
Started Jun 02 01:22:09 PM PDT 24
Finished Jun 02 01:22:59 PM PDT 24
Peak memory 200340 kb
Host smart-aa6c6854-ac3c-4183-ba17-5589bd96cbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710356791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3710356791
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.483791651
Short name T105
Test name
Test status
Simulation time 67264046670 ps
CPU time 28 seconds
Started Jun 02 01:22:09 PM PDT 24
Finished Jun 02 01:22:38 PM PDT 24
Peak memory 200336 kb
Host smart-01042137-55ef-4611-a706-b3c10e4e338c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483791651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.483791651
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2016013875
Short name T1089
Test name
Test status
Simulation time 89020788805 ps
CPU time 145.55 seconds
Started Jun 02 01:22:08 PM PDT 24
Finished Jun 02 01:24:34 PM PDT 24
Peak memory 200352 kb
Host smart-a1a099d5-9b81-4043-b348-005ecda8ac95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016013875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2016013875
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1470244182
Short name T577
Test name
Test status
Simulation time 21950423 ps
CPU time 0.54 seconds
Started Jun 02 01:15:16 PM PDT 24
Finished Jun 02 01:15:16 PM PDT 24
Peak memory 195244 kb
Host smart-dca470b6-b650-4e32-ab88-a6d0db368d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470244182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1470244182
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3296100940
Short name T130
Test name
Test status
Simulation time 56091313828 ps
CPU time 21.39 seconds
Started Jun 02 01:15:05 PM PDT 24
Finished Jun 02 01:15:26 PM PDT 24
Peak memory 200316 kb
Host smart-9879573e-739e-4211-98ea-31be08c63f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296100940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3296100940
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3595183632
Short name T889
Test name
Test status
Simulation time 186346468733 ps
CPU time 14.18 seconds
Started Jun 02 01:15:12 PM PDT 24
Finished Jun 02 01:15:26 PM PDT 24
Peak memory 198060 kb
Host smart-a267bcbf-74aa-4689-9980-cf11f5eb0900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595183632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3595183632
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.3401147980
Short name T299
Test name
Test status
Simulation time 61975353357 ps
CPU time 115.7 seconds
Started Jun 02 01:15:10 PM PDT 24
Finished Jun 02 01:17:06 PM PDT 24
Peak memory 200320 kb
Host smart-cf29edd8-21be-40b1-9605-a4e0b381b08a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401147980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3401147980
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1787867256
Short name T963
Test name
Test status
Simulation time 137347752109 ps
CPU time 1122.76 seconds
Started Jun 02 01:15:14 PM PDT 24
Finished Jun 02 01:33:58 PM PDT 24
Peak memory 200376 kb
Host smart-09e4ea1e-9b79-4912-9d82-f5c65800a89f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787867256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1787867256
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.4089363532
Short name T960
Test name
Test status
Simulation time 9082157849 ps
CPU time 4.85 seconds
Started Jun 02 01:15:12 PM PDT 24
Finished Jun 02 01:15:17 PM PDT 24
Peak memory 198756 kb
Host smart-84060cce-eb9c-4177-b2e3-908b48fc5a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089363532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.4089363532
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.948493888
Short name T704
Test name
Test status
Simulation time 87399330912 ps
CPU time 42.6 seconds
Started Jun 02 01:15:10 PM PDT 24
Finished Jun 02 01:15:53 PM PDT 24
Peak memory 199272 kb
Host smart-47226783-e581-4867-8108-d9e73d944248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948493888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.948493888
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2353031851
Short name T965
Test name
Test status
Simulation time 15492527666 ps
CPU time 874.15 seconds
Started Jun 02 01:15:11 PM PDT 24
Finished Jun 02 01:29:46 PM PDT 24
Peak memory 200412 kb
Host smart-757a9e5c-e4d1-44b1-8c07-844466ec7015
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353031851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2353031851
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.323959763
Short name T729
Test name
Test status
Simulation time 1592287740 ps
CPU time 1.9 seconds
Started Jun 02 01:15:10 PM PDT 24
Finished Jun 02 01:15:13 PM PDT 24
Peak memory 199192 kb
Host smart-9ac8822c-1541-4f19-8528-bb36905ddd26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323959763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.323959763
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.814128310
Short name T853
Test name
Test status
Simulation time 34415119032 ps
CPU time 60.99 seconds
Started Jun 02 01:15:10 PM PDT 24
Finished Jun 02 01:16:12 PM PDT 24
Peak memory 200268 kb
Host smart-927790c1-e653-4689-8b92-4d59082f8b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814128310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.814128310
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.4168710864
Short name T438
Test name
Test status
Simulation time 4082115185 ps
CPU time 7.65 seconds
Started Jun 02 01:15:11 PM PDT 24
Finished Jun 02 01:15:18 PM PDT 24
Peak memory 196380 kb
Host smart-611e6515-7fdb-44de-a0b5-6d64fb10dbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168710864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.4168710864
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.947008973
Short name T676
Test name
Test status
Simulation time 854297231 ps
CPU time 2.29 seconds
Started Jun 02 01:15:01 PM PDT 24
Finished Jun 02 01:15:03 PM PDT 24
Peak memory 199072 kb
Host smart-12eef48d-6ad1-4eb7-a112-296ca0aa3009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947008973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.947008973
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.751465270
Short name T1141
Test name
Test status
Simulation time 610818555399 ps
CPU time 192.51 seconds
Started Jun 02 01:15:14 PM PDT 24
Finished Jun 02 01:18:26 PM PDT 24
Peak memory 200328 kb
Host smart-26e78d7f-dbe4-4cd1-8306-8bf0d06f4048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751465270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.751465270
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.235126817
Short name T95
Test name
Test status
Simulation time 89354889568 ps
CPU time 493.93 seconds
Started Jun 02 01:15:15 PM PDT 24
Finished Jun 02 01:23:30 PM PDT 24
Peak memory 228588 kb
Host smart-b93cc14e-369a-4466-a9bb-0074745b3eb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235126817 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.235126817
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1866630642
Short name T1163
Test name
Test status
Simulation time 8841454750 ps
CPU time 5.49 seconds
Started Jun 02 01:15:12 PM PDT 24
Finished Jun 02 01:15:18 PM PDT 24
Peak memory 200036 kb
Host smart-ffbd7387-a2f8-4c0f-949e-620cbed68c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866630642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1866630642
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.764865809
Short name T330
Test name
Test status
Simulation time 54387893188 ps
CPU time 25.96 seconds
Started Jun 02 01:15:03 PM PDT 24
Finished Jun 02 01:15:29 PM PDT 24
Peak memory 200632 kb
Host smart-7e91ab7c-8cb6-49ba-a3ec-109d34f2449e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764865809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.764865809
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.4006080312
Short name T755
Test name
Test status
Simulation time 15689961131 ps
CPU time 25.45 seconds
Started Jun 02 01:22:11 PM PDT 24
Finished Jun 02 01:22:36 PM PDT 24
Peak memory 200348 kb
Host smart-e9ffc854-fef8-4663-bcb2-9422414bd99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006080312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.4006080312
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3351137404
Short name T535
Test name
Test status
Simulation time 27390900790 ps
CPU time 42.39 seconds
Started Jun 02 01:22:11 PM PDT 24
Finished Jun 02 01:22:54 PM PDT 24
Peak memory 199932 kb
Host smart-0ff1250c-0c14-4914-9a2b-44f95f95572f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351137404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3351137404
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1260608383
Short name T913
Test name
Test status
Simulation time 176110680520 ps
CPU time 157.53 seconds
Started Jun 02 01:22:09 PM PDT 24
Finished Jun 02 01:24:47 PM PDT 24
Peak memory 200348 kb
Host smart-82960b64-3d56-4850-b8b7-371628601aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260608383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1260608383
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2282081552
Short name T818
Test name
Test status
Simulation time 153040541991 ps
CPU time 71.73 seconds
Started Jun 02 01:22:09 PM PDT 24
Finished Jun 02 01:23:21 PM PDT 24
Peak memory 200356 kb
Host smart-2339e9db-c467-46bc-b17f-a6997b5f942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282081552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2282081552
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2993633339
Short name T816
Test name
Test status
Simulation time 186142589519 ps
CPU time 55.83 seconds
Started Jun 02 01:22:08 PM PDT 24
Finished Jun 02 01:23:05 PM PDT 24
Peak memory 200388 kb
Host smart-07ab8635-7d34-4f40-9886-d21ee35aab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993633339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2993633339
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.4156501012
Short name T1146
Test name
Test status
Simulation time 89154777569 ps
CPU time 290.51 seconds
Started Jun 02 01:22:13 PM PDT 24
Finished Jun 02 01:27:04 PM PDT 24
Peak memory 200364 kb
Host smart-c1c95d38-ec40-42ac-bdfc-72973d2c85a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156501012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.4156501012
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2147448819
Short name T471
Test name
Test status
Simulation time 86194226074 ps
CPU time 126.72 seconds
Started Jun 02 01:22:10 PM PDT 24
Finished Jun 02 01:24:17 PM PDT 24
Peak memory 200500 kb
Host smart-a0157779-b1e2-41da-966c-16650fe12dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147448819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2147448819
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1760485668
Short name T1077
Test name
Test status
Simulation time 102017773509 ps
CPU time 62.25 seconds
Started Jun 02 01:22:09 PM PDT 24
Finished Jun 02 01:23:12 PM PDT 24
Peak memory 200320 kb
Host smart-284de5a1-a0ca-4d2c-aac3-5c3bb516f98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760485668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1760485668
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.56586708
Short name T226
Test name
Test status
Simulation time 60684688126 ps
CPU time 56.4 seconds
Started Jun 02 01:22:10 PM PDT 24
Finished Jun 02 01:23:06 PM PDT 24
Peak memory 200432 kb
Host smart-67bb35e9-47de-4a33-be2a-f41fbbdb88a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56586708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.56586708
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1630343924
Short name T771
Test name
Test status
Simulation time 27765515191 ps
CPU time 22.37 seconds
Started Jun 02 01:22:09 PM PDT 24
Finished Jun 02 01:22:32 PM PDT 24
Peak memory 200420 kb
Host smart-b67af674-f51c-41a6-b3d6-4f769ade70a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630343924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1630343924
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.4179273078
Short name T657
Test name
Test status
Simulation time 14689603 ps
CPU time 0.57 seconds
Started Jun 02 01:15:21 PM PDT 24
Finished Jun 02 01:15:22 PM PDT 24
Peak memory 195784 kb
Host smart-7c3cbd29-59c9-44e6-80d3-7cb973f27bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179273078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.4179273078
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2146728524
Short name T988
Test name
Test status
Simulation time 152089774644 ps
CPU time 251.74 seconds
Started Jun 02 01:15:13 PM PDT 24
Finished Jun 02 01:19:25 PM PDT 24
Peak memory 200324 kb
Host smart-3b191809-02d1-4cfa-b747-385ebbfcf322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146728524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2146728524
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2217029593
Short name T152
Test name
Test status
Simulation time 53704516924 ps
CPU time 88.69 seconds
Started Jun 02 01:15:15 PM PDT 24
Finished Jun 02 01:16:44 PM PDT 24
Peak memory 200344 kb
Host smart-850bfe45-b92e-4a94-b41a-f5f812b0abd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217029593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2217029593
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_intr.2919012621
Short name T764
Test name
Test status
Simulation time 83958707540 ps
CPU time 149.12 seconds
Started Jun 02 01:15:21 PM PDT 24
Finished Jun 02 01:17:50 PM PDT 24
Peak memory 200360 kb
Host smart-518036fc-d99f-4f2b-a45d-c4f1abef2bda
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919012621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2919012621
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.259150799
Short name T277
Test name
Test status
Simulation time 139537245742 ps
CPU time 201.01 seconds
Started Jun 02 01:15:24 PM PDT 24
Finished Jun 02 01:18:45 PM PDT 24
Peak memory 200336 kb
Host smart-340c4100-25de-410f-afbd-2f4d64074b07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=259150799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.259150799
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.977407217
Short name T1002
Test name
Test status
Simulation time 5159091741 ps
CPU time 7.47 seconds
Started Jun 02 01:15:22 PM PDT 24
Finished Jun 02 01:15:30 PM PDT 24
Peak memory 198828 kb
Host smart-6251a3fd-1279-4961-a9e2-11fc233ab462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977407217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.977407217
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.990199063
Short name T1008
Test name
Test status
Simulation time 136804036517 ps
CPU time 63.6 seconds
Started Jun 02 01:15:23 PM PDT 24
Finished Jun 02 01:16:27 PM PDT 24
Peak memory 200580 kb
Host smart-3e4c7799-7f7f-48db-90da-ad8c9ad877fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990199063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.990199063
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1711841667
Short name T1000
Test name
Test status
Simulation time 15948242500 ps
CPU time 215.55 seconds
Started Jun 02 01:15:24 PM PDT 24
Finished Jun 02 01:19:00 PM PDT 24
Peak memory 200312 kb
Host smart-b061705d-8c84-43eb-b712-0dfe7758f525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711841667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1711841667
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2245576235
Short name T20
Test name
Test status
Simulation time 2733162642 ps
CPU time 19.95 seconds
Started Jun 02 01:15:15 PM PDT 24
Finished Jun 02 01:15:35 PM PDT 24
Peak memory 198456 kb
Host smart-cc1230df-ef0f-4745-a957-b3b124b82901
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2245576235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2245576235
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1099999568
Short name T939
Test name
Test status
Simulation time 16457224813 ps
CPU time 26.01 seconds
Started Jun 02 01:15:22 PM PDT 24
Finished Jun 02 01:15:48 PM PDT 24
Peak memory 200124 kb
Host smart-5ee31e86-a334-43b7-a818-58af146152ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099999568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1099999568
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1352422890
Short name T293
Test name
Test status
Simulation time 5312791672 ps
CPU time 2.89 seconds
Started Jun 02 01:15:22 PM PDT 24
Finished Jun 02 01:15:25 PM PDT 24
Peak memory 196380 kb
Host smart-a2b5f23c-518b-47dc-9743-2b0ee36a108a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352422890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1352422890
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.4147680885
Short name T630
Test name
Test status
Simulation time 626379661 ps
CPU time 2.52 seconds
Started Jun 02 01:15:15 PM PDT 24
Finished Jun 02 01:15:18 PM PDT 24
Peak memory 200252 kb
Host smart-528ca7e4-04cf-4657-89c9-fc5347da3563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147680885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.4147680885
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1866196316
Short name T914
Test name
Test status
Simulation time 193264916661 ps
CPU time 147.18 seconds
Started Jun 02 01:15:21 PM PDT 24
Finished Jun 02 01:17:49 PM PDT 24
Peak memory 200420 kb
Host smart-da480f07-afa4-448f-9ecb-6840c4c6c41f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866196316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1866196316
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2712649986
Short name T938
Test name
Test status
Simulation time 119530097543 ps
CPU time 889.24 seconds
Started Jun 02 01:15:24 PM PDT 24
Finished Jun 02 01:30:13 PM PDT 24
Peak memory 216900 kb
Host smart-731ebb92-41b4-4bdd-b356-a5411c737897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712649986 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2712649986
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3123312358
Short name T994
Test name
Test status
Simulation time 6723282743 ps
CPU time 17.74 seconds
Started Jun 02 01:15:23 PM PDT 24
Finished Jun 02 01:15:41 PM PDT 24
Peak memory 200152 kb
Host smart-6c3d3bf9-3deb-4395-b7db-54b7e48916c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123312358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3123312358
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2860610619
Short name T831
Test name
Test status
Simulation time 28208062631 ps
CPU time 35.56 seconds
Started Jun 02 01:15:15 PM PDT 24
Finished Jun 02 01:15:51 PM PDT 24
Peak memory 200396 kb
Host smart-15d430e5-f221-4181-9ddf-0175332db084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860610619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2860610619
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.213048399
Short name T116
Test name
Test status
Simulation time 190203713405 ps
CPU time 40.74 seconds
Started Jun 02 01:22:16 PM PDT 24
Finished Jun 02 01:22:57 PM PDT 24
Peak memory 200548 kb
Host smart-18ec4b4a-fa0d-48a9-8212-8410105914c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213048399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.213048399
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2867549699
Short name T1005
Test name
Test status
Simulation time 9421429323 ps
CPU time 16.16 seconds
Started Jun 02 01:22:16 PM PDT 24
Finished Jun 02 01:22:33 PM PDT 24
Peak memory 200160 kb
Host smart-9f174e7f-4432-4b09-b5d5-46315b9f9a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867549699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2867549699
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2089775853
Short name T665
Test name
Test status
Simulation time 53037999500 ps
CPU time 15.84 seconds
Started Jun 02 01:22:17 PM PDT 24
Finished Jun 02 01:22:33 PM PDT 24
Peak memory 200344 kb
Host smart-75a89a6c-c0dc-49b0-aba9-ce01d5d2197f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089775853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2089775853
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1737854097
Short name T732
Test name
Test status
Simulation time 7868580099 ps
CPU time 8.27 seconds
Started Jun 02 01:22:15 PM PDT 24
Finished Jun 02 01:22:24 PM PDT 24
Peak memory 200348 kb
Host smart-4476d569-0843-4181-9725-c8bfc1bb9f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737854097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1737854097
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1306282150
Short name T186
Test name
Test status
Simulation time 56553207377 ps
CPU time 93.25 seconds
Started Jun 02 01:22:18 PM PDT 24
Finished Jun 02 01:23:52 PM PDT 24
Peak memory 200384 kb
Host smart-9d5eaf22-a888-4ff1-892e-d7e75e303717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306282150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1306282150
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2904323007
Short name T268
Test name
Test status
Simulation time 83259231860 ps
CPU time 130.32 seconds
Started Jun 02 01:22:17 PM PDT 24
Finished Jun 02 01:24:27 PM PDT 24
Peak memory 200372 kb
Host smart-b9f6acba-e046-4a6e-ad18-a767ec750c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904323007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2904323007
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1835473732
Short name T230
Test name
Test status
Simulation time 110924799119 ps
CPU time 86.9 seconds
Started Jun 02 01:22:16 PM PDT 24
Finished Jun 02 01:23:43 PM PDT 24
Peak memory 200360 kb
Host smart-0acded04-06b6-43cb-b231-ed85409c584d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835473732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1835473732
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3802054502
Short name T11
Test name
Test status
Simulation time 159550058115 ps
CPU time 45.18 seconds
Started Jun 02 01:22:17 PM PDT 24
Finished Jun 02 01:23:03 PM PDT 24
Peak memory 200420 kb
Host smart-23febed8-d562-478c-a3d4-da557defb722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802054502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3802054502
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3011767857
Short name T199
Test name
Test status
Simulation time 9496942310 ps
CPU time 16.28 seconds
Started Jun 02 01:22:15 PM PDT 24
Finished Jun 02 01:22:32 PM PDT 24
Peak memory 200152 kb
Host smart-f89555ea-a718-44a3-af7d-2fdcfaffafc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011767857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3011767857
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1478594530
Short name T884
Test name
Test status
Simulation time 13448413 ps
CPU time 0.57 seconds
Started Jun 02 01:15:29 PM PDT 24
Finished Jun 02 01:15:30 PM PDT 24
Peak memory 195748 kb
Host smart-ccec6581-3019-421a-8550-7e80b5f5e5a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478594530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1478594530
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.9625262
Short name T872
Test name
Test status
Simulation time 68836554336 ps
CPU time 85.97 seconds
Started Jun 02 01:15:22 PM PDT 24
Finished Jun 02 01:16:48 PM PDT 24
Peak memory 200448 kb
Host smart-5db3d81b-f929-4bab-a07e-0cae9abb8d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9625262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.9625262
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2525881987
Short name T745
Test name
Test status
Simulation time 231931703248 ps
CPU time 47.59 seconds
Started Jun 02 01:15:28 PM PDT 24
Finished Jun 02 01:16:16 PM PDT 24
Peak memory 200308 kb
Host smart-b1f8bcda-d88f-4d8d-86b1-7d618a2620ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525881987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2525881987
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1192993825
Short name T817
Test name
Test status
Simulation time 11276824009 ps
CPU time 20.36 seconds
Started Jun 02 01:15:26 PM PDT 24
Finished Jun 02 01:15:47 PM PDT 24
Peak memory 200248 kb
Host smart-7e4ad8f9-7ca5-475d-94a3-cac36cc9833a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192993825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1192993825
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.977018953
Short name T731
Test name
Test status
Simulation time 35079469384 ps
CPU time 32.21 seconds
Started Jun 02 01:15:28 PM PDT 24
Finished Jun 02 01:16:01 PM PDT 24
Peak memory 199444 kb
Host smart-6f827771-de63-4139-82aa-bd471aaf1b46
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977018953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.977018953
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.406042153
Short name T600
Test name
Test status
Simulation time 109707530491 ps
CPU time 166.58 seconds
Started Jun 02 01:15:28 PM PDT 24
Finished Jun 02 01:18:15 PM PDT 24
Peak memory 200312 kb
Host smart-cd993ec1-395e-415b-9b90-6d8751c177fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=406042153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.406042153
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2838943165
Short name T765
Test name
Test status
Simulation time 7201963860 ps
CPU time 4.64 seconds
Started Jun 02 01:15:27 PM PDT 24
Finished Jun 02 01:15:32 PM PDT 24
Peak memory 200208 kb
Host smart-90677822-711c-42a2-a42c-c784e12e663b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838943165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2838943165
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2568572839
Short name T528
Test name
Test status
Simulation time 156082442081 ps
CPU time 71.56 seconds
Started Jun 02 01:15:26 PM PDT 24
Finished Jun 02 01:16:38 PM PDT 24
Peak memory 208748 kb
Host smart-5e6c3dd7-cc13-4000-bad1-d4e080698260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568572839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2568572839
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1684860689
Short name T1033
Test name
Test status
Simulation time 14118798408 ps
CPU time 187.27 seconds
Started Jun 02 01:15:28 PM PDT 24
Finished Jun 02 01:18:36 PM PDT 24
Peak memory 200332 kb
Host smart-94ea2982-23cd-4a72-bc73-5c38c353ed24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1684860689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1684860689
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.465581723
Short name T417
Test name
Test status
Simulation time 1273173044 ps
CPU time 5.34 seconds
Started Jun 02 01:15:30 PM PDT 24
Finished Jun 02 01:15:35 PM PDT 24
Peak memory 198560 kb
Host smart-66a516fb-65ba-438f-8ee3-3f377d2d7409
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=465581723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.465581723
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2805790489
Short name T638
Test name
Test status
Simulation time 15970974040 ps
CPU time 13.98 seconds
Started Jun 02 01:15:28 PM PDT 24
Finished Jun 02 01:15:42 PM PDT 24
Peak memory 199692 kb
Host smart-4fa1cab2-0017-46aa-8433-25216280fd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805790489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2805790489
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.989837630
Short name T1178
Test name
Test status
Simulation time 3124050473 ps
CPU time 5.43 seconds
Started Jun 02 01:15:28 PM PDT 24
Finished Jun 02 01:15:34 PM PDT 24
Peak memory 196348 kb
Host smart-8790b6b8-11dd-4995-a291-731d710578ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989837630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.989837630
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.19205246
Short name T36
Test name
Test status
Simulation time 671622414 ps
CPU time 2.09 seconds
Started Jun 02 01:15:22 PM PDT 24
Finished Jun 02 01:15:24 PM PDT 24
Peak memory 199988 kb
Host smart-ebb8a065-2d67-488d-8949-7b29602e4274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19205246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.19205246
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2725229170
Short name T581
Test name
Test status
Simulation time 110687510278 ps
CPU time 546.28 seconds
Started Jun 02 01:15:28 PM PDT 24
Finished Jun 02 01:24:34 PM PDT 24
Peak memory 200388 kb
Host smart-26f5e19e-a488-407a-865e-7a72b33b9565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725229170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2725229170
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2289814818
Short name T47
Test name
Test status
Simulation time 359318152436 ps
CPU time 782.18 seconds
Started Jun 02 01:15:28 PM PDT 24
Finished Jun 02 01:28:31 PM PDT 24
Peak memory 225240 kb
Host smart-2d76efc5-e1ac-446f-8e41-15cfdea289a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289814818 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2289814818
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.4223170064
Short name T584
Test name
Test status
Simulation time 1035467462 ps
CPU time 3.44 seconds
Started Jun 02 01:15:28 PM PDT 24
Finished Jun 02 01:15:31 PM PDT 24
Peak memory 199584 kb
Host smart-8cb806d6-34ed-47be-8836-a59de97673e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223170064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4223170064
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2040875333
Short name T925
Test name
Test status
Simulation time 78769744399 ps
CPU time 109.63 seconds
Started Jun 02 01:15:23 PM PDT 24
Finished Jun 02 01:17:13 PM PDT 24
Peak memory 200400 kb
Host smart-96944039-9d8b-447e-901a-af781368e52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040875333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2040875333
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1851723781
Short name T508
Test name
Test status
Simulation time 107281085177 ps
CPU time 62.65 seconds
Started Jun 02 01:22:18 PM PDT 24
Finished Jun 02 01:23:20 PM PDT 24
Peak memory 200336 kb
Host smart-04b6d000-0416-4246-807b-773a8cdb4823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851723781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1851723781
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1429817202
Short name T726
Test name
Test status
Simulation time 13092051990 ps
CPU time 25 seconds
Started Jun 02 01:22:16 PM PDT 24
Finished Jun 02 01:22:42 PM PDT 24
Peak memory 200420 kb
Host smart-a5da9155-6d43-45a8-9180-8997c276f729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429817202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1429817202
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3891189243
Short name T589
Test name
Test status
Simulation time 25634108487 ps
CPU time 40.5 seconds
Started Jun 02 01:22:17 PM PDT 24
Finished Jun 02 01:22:58 PM PDT 24
Peak memory 200036 kb
Host smart-0cf00e7c-8bd3-4ffd-9a24-b94fd415e6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891189243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3891189243
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1917190955
Short name T131
Test name
Test status
Simulation time 124470511476 ps
CPU time 71.2 seconds
Started Jun 02 01:22:16 PM PDT 24
Finished Jun 02 01:23:28 PM PDT 24
Peak memory 200360 kb
Host smart-0d28202f-b917-47a9-a8a7-593d3fd7b00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917190955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1917190955
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1823761969
Short name T335
Test name
Test status
Simulation time 35183687899 ps
CPU time 16.27 seconds
Started Jun 02 01:22:16 PM PDT 24
Finished Jun 02 01:22:32 PM PDT 24
Peak memory 200472 kb
Host smart-0aad4922-bd65-4160-ac62-175d106d1144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823761969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1823761969
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.205302516
Short name T1085
Test name
Test status
Simulation time 5880997974 ps
CPU time 10.53 seconds
Started Jun 02 01:22:17 PM PDT 24
Finished Jun 02 01:22:28 PM PDT 24
Peak memory 200340 kb
Host smart-73b7b496-6b3b-46c6-ae9b-12982138e297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205302516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.205302516
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.360829814
Short name T1136
Test name
Test status
Simulation time 74089333317 ps
CPU time 110.82 seconds
Started Jun 02 01:22:22 PM PDT 24
Finished Jun 02 01:24:14 PM PDT 24
Peak memory 200236 kb
Host smart-c3329cf7-6d76-4338-a37d-4d8a82a8d328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360829814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.360829814
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1879392092
Short name T583
Test name
Test status
Simulation time 23082316274 ps
CPU time 37.13 seconds
Started Jun 02 01:22:22 PM PDT 24
Finished Jun 02 01:22:59 PM PDT 24
Peak memory 200308 kb
Host smart-066bdc82-5c65-4972-87fb-a33eedd0dc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879392092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1879392092
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1656853133
Short name T195
Test name
Test status
Simulation time 134169592816 ps
CPU time 81.94 seconds
Started Jun 02 01:22:22 PM PDT 24
Finished Jun 02 01:23:44 PM PDT 24
Peak memory 200424 kb
Host smart-fda5a37b-4a78-4e90-b12b-12a78821d35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656853133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1656853133
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.998952514
Short name T552
Test name
Test status
Simulation time 233050498740 ps
CPU time 31.55 seconds
Started Jun 02 01:22:23 PM PDT 24
Finished Jun 02 01:22:55 PM PDT 24
Peak memory 200368 kb
Host smart-8c87c7ee-3f3e-4b38-b811-e171e3207c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998952514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.998952514
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.820189072
Short name T714
Test name
Test status
Simulation time 11858100 ps
CPU time 0.57 seconds
Started Jun 02 01:15:42 PM PDT 24
Finished Jun 02 01:15:43 PM PDT 24
Peak memory 195764 kb
Host smart-654a4b4d-eda5-48d0-a3f8-1dd63e5c395d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820189072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.820189072
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1849624700
Short name T1018
Test name
Test status
Simulation time 165428733201 ps
CPU time 112.44 seconds
Started Jun 02 01:15:35 PM PDT 24
Finished Jun 02 01:17:28 PM PDT 24
Peak memory 200420 kb
Host smart-f2edce66-3638-4fdd-a2d8-fb745642889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849624700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1849624700
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2578988536
Short name T503
Test name
Test status
Simulation time 34947935648 ps
CPU time 60.6 seconds
Started Jun 02 01:15:35 PM PDT 24
Finished Jun 02 01:16:36 PM PDT 24
Peak memory 200332 kb
Host smart-c43f35bb-daa7-4183-9d0d-43ef96e7136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578988536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2578988536
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.205280703
Short name T159
Test name
Test status
Simulation time 81888583479 ps
CPU time 71.46 seconds
Started Jun 02 01:15:34 PM PDT 24
Finished Jun 02 01:16:46 PM PDT 24
Peak memory 200420 kb
Host smart-20cd62bc-4f89-425e-bcd3-c36fd90761b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205280703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.205280703
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3830646062
Short name T456
Test name
Test status
Simulation time 30580408459 ps
CPU time 15.71 seconds
Started Jun 02 01:15:37 PM PDT 24
Finished Jun 02 01:15:53 PM PDT 24
Peak memory 200356 kb
Host smart-d359daba-b954-4f67-936c-6b4a76592b30
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830646062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3830646062
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2980005616
Short name T989
Test name
Test status
Simulation time 69966922651 ps
CPU time 149.61 seconds
Started Jun 02 01:15:42 PM PDT 24
Finished Jun 02 01:18:12 PM PDT 24
Peak memory 200324 kb
Host smart-72f360fa-5627-4e1c-87cd-86311c6b83ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2980005616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2980005616
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1070788386
Short name T1156
Test name
Test status
Simulation time 8132142336 ps
CPU time 16.77 seconds
Started Jun 02 01:15:40 PM PDT 24
Finished Jun 02 01:15:57 PM PDT 24
Peak memory 199072 kb
Host smart-2d953a90-8da3-489d-82aa-17e3083f59ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070788386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1070788386
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.280173742
Short name T263
Test name
Test status
Simulation time 106100111254 ps
CPU time 92.28 seconds
Started Jun 02 01:15:37 PM PDT 24
Finished Jun 02 01:17:09 PM PDT 24
Peak memory 199640 kb
Host smart-27515777-8e5c-480a-99ac-dba8811a0478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280173742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.280173742
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3555568148
Short name T824
Test name
Test status
Simulation time 11494043044 ps
CPU time 293.75 seconds
Started Jun 02 01:15:40 PM PDT 24
Finished Jun 02 01:20:34 PM PDT 24
Peak memory 200312 kb
Host smart-92d23c43-810e-4e4c-9eaa-95e4fe2178d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3555568148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3555568148
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.43236141
Short name T354
Test name
Test status
Simulation time 5599556848 ps
CPU time 11.04 seconds
Started Jun 02 01:15:36 PM PDT 24
Finished Jun 02 01:15:47 PM PDT 24
Peak memory 198532 kb
Host smart-5b68bb9f-913a-46e0-8232-280b7c1efc87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=43236141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.43236141
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1240517205
Short name T515
Test name
Test status
Simulation time 134338954611 ps
CPU time 64.04 seconds
Started Jun 02 01:15:43 PM PDT 24
Finished Jun 02 01:16:47 PM PDT 24
Peak memory 200300 kb
Host smart-ce3ef55b-c460-4344-9e34-ff6aa28bcd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240517205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1240517205
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1965293112
Short name T573
Test name
Test status
Simulation time 29790543780 ps
CPU time 16.81 seconds
Started Jun 02 01:15:41 PM PDT 24
Finished Jun 02 01:15:58 PM PDT 24
Peak memory 196668 kb
Host smart-ac66482a-7212-47e0-9b2f-7cc4ddad0abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965293112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1965293112
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3200050403
Short name T1124
Test name
Test status
Simulation time 506186058 ps
CPU time 1.74 seconds
Started Jun 02 01:15:28 PM PDT 24
Finished Jun 02 01:15:30 PM PDT 24
Peak memory 200196 kb
Host smart-688405e3-2b3d-4845-bab1-9fe0da54f0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200050403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3200050403
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.2939219151
Short name T439
Test name
Test status
Simulation time 18745673835 ps
CPU time 23.14 seconds
Started Jun 02 01:15:41 PM PDT 24
Finished Jun 02 01:16:05 PM PDT 24
Peak memory 200376 kb
Host smart-7804ac04-16e1-4dbf-a2d7-0911689902df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939219151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2939219151
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2956237042
Short name T788
Test name
Test status
Simulation time 1281428417 ps
CPU time 3.95 seconds
Started Jun 02 01:15:40 PM PDT 24
Finished Jun 02 01:15:44 PM PDT 24
Peak memory 200228 kb
Host smart-0a883b36-3cd9-4353-a72e-6c6fa9b2dd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956237042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2956237042
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3046100471
Short name T395
Test name
Test status
Simulation time 85443149042 ps
CPU time 108.57 seconds
Started Jun 02 01:15:34 PM PDT 24
Finished Jun 02 01:17:23 PM PDT 24
Peak memory 200356 kb
Host smart-f681fc31-64e7-435a-a8c6-d554cff13ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046100471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3046100471
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3243048677
Short name T980
Test name
Test status
Simulation time 17068386579 ps
CPU time 29.83 seconds
Started Jun 02 01:22:23 PM PDT 24
Finished Jun 02 01:22:53 PM PDT 24
Peak memory 200376 kb
Host smart-3b37dcec-1be8-422a-854a-666b8c6b3249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243048677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3243048677
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2933040581
Short name T188
Test name
Test status
Simulation time 15755587142 ps
CPU time 12.98 seconds
Started Jun 02 01:22:24 PM PDT 24
Finished Jun 02 01:22:37 PM PDT 24
Peak memory 200156 kb
Host smart-e2de43ac-3b1d-435d-a10e-874d1284ece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933040581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2933040581
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3474735028
Short name T397
Test name
Test status
Simulation time 7232426808 ps
CPU time 12.16 seconds
Started Jun 02 01:22:24 PM PDT 24
Finished Jun 02 01:22:36 PM PDT 24
Peak memory 200360 kb
Host smart-e89d8242-3e3a-49da-b66c-6f750a68f378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474735028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3474735028
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1381005228
Short name T185
Test name
Test status
Simulation time 98525042241 ps
CPU time 158.83 seconds
Started Jun 02 01:22:22 PM PDT 24
Finished Jun 02 01:25:01 PM PDT 24
Peak memory 200400 kb
Host smart-bcf6359b-9194-4085-83c2-9cefcbf206bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381005228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1381005228
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3469332343
Short name T204
Test name
Test status
Simulation time 39684489638 ps
CPU time 56.6 seconds
Started Jun 02 01:22:30 PM PDT 24
Finished Jun 02 01:23:27 PM PDT 24
Peak memory 200260 kb
Host smart-20de547b-2a3f-4cd2-bc61-a45c2ed3d8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469332343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3469332343
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2164828893
Short name T177
Test name
Test status
Simulation time 22625199367 ps
CPU time 11.79 seconds
Started Jun 02 01:22:29 PM PDT 24
Finished Jun 02 01:22:41 PM PDT 24
Peak memory 200408 kb
Host smart-6e8867d4-d3a7-4322-a111-164595a2ef0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164828893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2164828893
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1094640498
Short name T241
Test name
Test status
Simulation time 57444960342 ps
CPU time 50.03 seconds
Started Jun 02 01:22:30 PM PDT 24
Finished Jun 02 01:23:20 PM PDT 24
Peak memory 200340 kb
Host smart-e4304c7d-432b-4ccc-8f80-370aacd627fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094640498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1094640498
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3176043923
Short name T1101
Test name
Test status
Simulation time 23110582 ps
CPU time 0.58 seconds
Started Jun 02 01:15:58 PM PDT 24
Finished Jun 02 01:15:59 PM PDT 24
Peak memory 195772 kb
Host smart-dfb0f599-688c-475c-b4d6-ae3c1d3c15c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176043923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3176043923
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1279214805
Short name T174
Test name
Test status
Simulation time 58138838058 ps
CPU time 25.05 seconds
Started Jun 02 01:15:52 PM PDT 24
Finished Jun 02 01:16:17 PM PDT 24
Peak memory 200400 kb
Host smart-54a20036-d5d3-4952-b8b9-37614d0e7ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279214805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1279214805
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1844146841
Short name T500
Test name
Test status
Simulation time 53476825213 ps
CPU time 14.53 seconds
Started Jun 02 01:15:50 PM PDT 24
Finished Jun 02 01:16:05 PM PDT 24
Peak memory 200372 kb
Host smart-8cfbe2cf-209e-47e7-a0ee-0d6f3e5b6d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844146841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1844146841
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3908564041
Short name T1063
Test name
Test status
Simulation time 41641035169 ps
CPU time 18.38 seconds
Started Jun 02 01:15:51 PM PDT 24
Finished Jun 02 01:16:10 PM PDT 24
Peak memory 200288 kb
Host smart-b79cada1-9548-40a2-8475-e6f4d209fd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908564041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3908564041
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3071218622
Short name T17
Test name
Test status
Simulation time 33116434586 ps
CPU time 10.58 seconds
Started Jun 02 01:15:51 PM PDT 24
Finished Jun 02 01:16:02 PM PDT 24
Peak memory 199824 kb
Host smart-4a7911e6-5f01-459f-8232-7c082c985834
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071218622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3071218622
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.883388183
Short name T901
Test name
Test status
Simulation time 82203998849 ps
CPU time 585.13 seconds
Started Jun 02 01:16:00 PM PDT 24
Finished Jun 02 01:25:45 PM PDT 24
Peak memory 200412 kb
Host smart-35fcaac4-1147-42a8-893b-bce0ab2709e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883388183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.883388183
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3231569002
Short name T911
Test name
Test status
Simulation time 5824979464 ps
CPU time 6.21 seconds
Started Jun 02 01:15:51 PM PDT 24
Finished Jun 02 01:15:58 PM PDT 24
Peak memory 198912 kb
Host smart-5c2b46b5-ef42-4a71-836c-0144ebaa8879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231569002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3231569002
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1908434243
Short name T484
Test name
Test status
Simulation time 54865164412 ps
CPU time 50.28 seconds
Started Jun 02 01:15:53 PM PDT 24
Finished Jun 02 01:16:44 PM PDT 24
Peak memory 198868 kb
Host smart-5e784ce7-509e-4d91-b257-e428d8b8f41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908434243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1908434243
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1211171535
Short name T430
Test name
Test status
Simulation time 17199972033 ps
CPU time 1020.93 seconds
Started Jun 02 01:15:51 PM PDT 24
Finished Jun 02 01:32:52 PM PDT 24
Peak memory 200372 kb
Host smart-36749070-1a9e-4ef2-b820-a226a1c26d38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211171535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1211171535
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3187147454
Short name T1093
Test name
Test status
Simulation time 1732272708 ps
CPU time 2.5 seconds
Started Jun 02 01:15:50 PM PDT 24
Finished Jun 02 01:15:53 PM PDT 24
Peak memory 198444 kb
Host smart-1c4f2a51-9faf-44e4-b98b-a1545b62349b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3187147454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3187147454
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3583434686
Short name T451
Test name
Test status
Simulation time 71040553247 ps
CPU time 121.36 seconds
Started Jun 02 01:15:52 PM PDT 24
Finished Jun 02 01:17:54 PM PDT 24
Peak memory 200012 kb
Host smart-434e9d86-62de-4d2d-8923-238e20c11ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583434686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3583434686
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.889975923
Short name T399
Test name
Test status
Simulation time 2851324575 ps
CPU time 5.56 seconds
Started Jun 02 01:15:51 PM PDT 24
Finished Jun 02 01:15:57 PM PDT 24
Peak memory 196392 kb
Host smart-bd1a5094-96a8-448c-b381-00a3f03a2d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889975923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.889975923
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1275347079
Short name T1007
Test name
Test status
Simulation time 87622460 ps
CPU time 0.9 seconds
Started Jun 02 01:15:42 PM PDT 24
Finished Jun 02 01:15:43 PM PDT 24
Peak memory 197620 kb
Host smart-e66298f6-0e10-478b-a93b-397198acae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275347079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1275347079
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3983559717
Short name T999
Test name
Test status
Simulation time 89920890756 ps
CPU time 111.85 seconds
Started Jun 02 01:16:00 PM PDT 24
Finished Jun 02 01:17:52 PM PDT 24
Peak memory 208824 kb
Host smart-31d50f07-1c3e-4e66-a3c2-5ee4b3c7db8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983559717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3983559717
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1716838417
Short name T85
Test name
Test status
Simulation time 27503401267 ps
CPU time 211.12 seconds
Started Jun 02 01:15:59 PM PDT 24
Finished Jun 02 01:19:30 PM PDT 24
Peak memory 216988 kb
Host smart-c1476cd9-ce0a-487b-b435-885380b52e57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716838417 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1716838417
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1316253737
Short name T43
Test name
Test status
Simulation time 6628535456 ps
CPU time 32.23 seconds
Started Jun 02 01:15:51 PM PDT 24
Finished Jun 02 01:16:24 PM PDT 24
Peak memory 200220 kb
Host smart-30983748-1a2e-44be-a3f1-af1c71fd4237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316253737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1316253737
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.80070283
Short name T455
Test name
Test status
Simulation time 67469911291 ps
CPU time 95.39 seconds
Started Jun 02 01:15:40 PM PDT 24
Finished Jun 02 01:17:16 PM PDT 24
Peak memory 200400 kb
Host smart-6b42e05b-9e83-4d27-94bc-8a7bde0f47c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80070283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.80070283
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1751755865
Short name T543
Test name
Test status
Simulation time 74265853488 ps
CPU time 47.18 seconds
Started Jun 02 01:22:31 PM PDT 24
Finished Jun 02 01:23:19 PM PDT 24
Peak memory 200172 kb
Host smart-ddb39abe-e824-4c70-a9d1-1374a77ebaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751755865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1751755865
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3080736550
Short name T518
Test name
Test status
Simulation time 119680046304 ps
CPU time 238.97 seconds
Started Jun 02 01:22:30 PM PDT 24
Finished Jun 02 01:26:29 PM PDT 24
Peak memory 200404 kb
Host smart-46996e39-bc27-41a3-bae8-537afbe2161e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080736550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3080736550
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.4086595618
Short name T930
Test name
Test status
Simulation time 78261626872 ps
CPU time 111.43 seconds
Started Jun 02 01:22:29 PM PDT 24
Finished Jun 02 01:24:21 PM PDT 24
Peak memory 200388 kb
Host smart-acd6417f-9885-4074-9eb9-2bd274f9e681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086595618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.4086595618
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2496660316
Short name T122
Test name
Test status
Simulation time 20836927885 ps
CPU time 32.74 seconds
Started Jun 02 01:22:37 PM PDT 24
Finished Jun 02 01:23:11 PM PDT 24
Peak memory 200344 kb
Host smart-8fc07c23-087a-4606-ade1-6a1023b3f9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496660316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2496660316
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1715647722
Short name T193
Test name
Test status
Simulation time 190766453766 ps
CPU time 73.72 seconds
Started Jun 02 01:22:37 PM PDT 24
Finished Jun 02 01:23:51 PM PDT 24
Peak memory 200336 kb
Host smart-768ba14a-0530-4dbc-b9a5-68a401799878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715647722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1715647722
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.443216539
Short name T841
Test name
Test status
Simulation time 34075990198 ps
CPU time 13.91 seconds
Started Jun 02 01:22:36 PM PDT 24
Finished Jun 02 01:22:50 PM PDT 24
Peak memory 200388 kb
Host smart-59e7c1d8-89bd-4090-9c3e-7c067587abfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443216539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.443216539
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1542802359
Short name T35
Test name
Test status
Simulation time 21384544438 ps
CPU time 43.7 seconds
Started Jun 02 01:22:35 PM PDT 24
Finished Jun 02 01:23:19 PM PDT 24
Peak memory 200344 kb
Host smart-716cebb3-7cb3-43da-b268-f9e3b293580c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542802359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1542802359
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.19137094
Short name T1055
Test name
Test status
Simulation time 25099786701 ps
CPU time 11.52 seconds
Started Jun 02 01:22:37 PM PDT 24
Finished Jun 02 01:22:49 PM PDT 24
Peak memory 200308 kb
Host smart-0ef2d4a8-1c8b-4956-a3da-b68be76d0b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19137094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.19137094
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2450996746
Short name T1154
Test name
Test status
Simulation time 109581731650 ps
CPU time 52.68 seconds
Started Jun 02 01:22:36 PM PDT 24
Finished Jun 02 01:23:30 PM PDT 24
Peak memory 200356 kb
Host smart-93c1cb6f-cd62-4da3-8da7-649f4eeda9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450996746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2450996746
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1556135988
Short name T808
Test name
Test status
Simulation time 45589606 ps
CPU time 0.57 seconds
Started Jun 02 01:16:05 PM PDT 24
Finished Jun 02 01:16:06 PM PDT 24
Peak memory 195692 kb
Host smart-128ff74b-f267-4f83-873f-4673c274d513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556135988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1556135988
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3201292875
Short name T469
Test name
Test status
Simulation time 73289549623 ps
CPU time 31.93 seconds
Started Jun 02 01:15:59 PM PDT 24
Finished Jun 02 01:16:32 PM PDT 24
Peak memory 200412 kb
Host smart-7d240c7c-2128-40b7-9459-1261eecfdbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201292875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3201292875
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2163016545
Short name T1129
Test name
Test status
Simulation time 88654780048 ps
CPU time 299.18 seconds
Started Jun 02 01:15:59 PM PDT 24
Finished Jun 02 01:20:58 PM PDT 24
Peak memory 200284 kb
Host smart-678daf83-a22e-43a6-a0ec-b0eaea9eddd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163016545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2163016545
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.892382283
Short name T1080
Test name
Test status
Simulation time 42401689324 ps
CPU time 68.94 seconds
Started Jun 02 01:15:57 PM PDT 24
Finished Jun 02 01:17:06 PM PDT 24
Peak memory 200420 kb
Host smart-67baf464-0827-4d53-bcdc-bc32c3fad34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892382283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.892382283
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.911784882
Short name T546
Test name
Test status
Simulation time 4655243890 ps
CPU time 2.47 seconds
Started Jun 02 01:15:58 PM PDT 24
Finished Jun 02 01:16:01 PM PDT 24
Peak memory 196916 kb
Host smart-65e451a8-b25c-468f-adc6-aa13e440acfd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911784882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.911784882
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2455184182
Short name T585
Test name
Test status
Simulation time 61298362972 ps
CPU time 414.3 seconds
Started Jun 02 01:16:07 PM PDT 24
Finished Jun 02 01:23:02 PM PDT 24
Peak memory 200344 kb
Host smart-c5669187-eede-400f-8df3-c27a2d72dc50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2455184182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2455184182
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2738599350
Short name T861
Test name
Test status
Simulation time 3747911161 ps
CPU time 2.26 seconds
Started Jun 02 01:16:06 PM PDT 24
Finished Jun 02 01:16:09 PM PDT 24
Peak memory 198072 kb
Host smart-1cf3d017-14f5-4195-ae1c-24f669cc5625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738599350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2738599350
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.4158319666
Short name T258
Test name
Test status
Simulation time 81054695597 ps
CPU time 84.51 seconds
Started Jun 02 01:16:08 PM PDT 24
Finished Jun 02 01:17:33 PM PDT 24
Peak memory 208824 kb
Host smart-82458b30-a333-4471-a94f-8c9737593791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158319666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.4158319666
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.1995612861
Short name T659
Test name
Test status
Simulation time 20652020908 ps
CPU time 1027.6 seconds
Started Jun 02 01:16:06 PM PDT 24
Finished Jun 02 01:33:14 PM PDT 24
Peak memory 200420 kb
Host smart-64ea38e2-d1e3-42f6-80c3-3e7ad2bed942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1995612861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1995612861
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1525363132
Short name T1070
Test name
Test status
Simulation time 5695928132 ps
CPU time 8.58 seconds
Started Jun 02 01:15:57 PM PDT 24
Finished Jun 02 01:16:06 PM PDT 24
Peak memory 199844 kb
Host smart-f09cebeb-14c5-43b3-bf4b-18d6254f5bb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525363132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1525363132
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1631402196
Short name T937
Test name
Test status
Simulation time 191202439266 ps
CPU time 189.37 seconds
Started Jun 02 01:16:06 PM PDT 24
Finished Jun 02 01:19:15 PM PDT 24
Peak memory 200352 kb
Host smart-4c583dd8-6192-4d4c-9750-d2bb23ac4c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631402196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1631402196
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3678491556
Short name T542
Test name
Test status
Simulation time 45918158973 ps
CPU time 19.23 seconds
Started Jun 02 01:16:07 PM PDT 24
Finished Jun 02 01:16:26 PM PDT 24
Peak memory 196364 kb
Host smart-95419139-e26b-4f2a-970f-cfcaa5b6aba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678491556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3678491556
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.4071574915
Short name T1015
Test name
Test status
Simulation time 5721835380 ps
CPU time 5.99 seconds
Started Jun 02 01:15:59 PM PDT 24
Finished Jun 02 01:16:06 PM PDT 24
Peak memory 200216 kb
Host smart-8607dbd8-9354-4b51-a648-65634345fb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071574915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.4071574915
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.162538141
Short name T1092
Test name
Test status
Simulation time 109226777028 ps
CPU time 297.9 seconds
Started Jun 02 01:16:06 PM PDT 24
Finished Jun 02 01:21:04 PM PDT 24
Peak memory 217032 kb
Host smart-aea1fce8-dab7-4448-99e3-934cf6bb876f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162538141 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.162538141
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1402271588
Short name T951
Test name
Test status
Simulation time 12502288605 ps
CPU time 25.41 seconds
Started Jun 02 01:16:05 PM PDT 24
Finished Jun 02 01:16:31 PM PDT 24
Peak memory 200340 kb
Host smart-2248ac35-1fa8-492b-83c9-8908739fb12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402271588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1402271588
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.184493105
Short name T682
Test name
Test status
Simulation time 58418180136 ps
CPU time 113.12 seconds
Started Jun 02 01:15:59 PM PDT 24
Finished Jun 02 01:17:53 PM PDT 24
Peak memory 200376 kb
Host smart-d77e2566-e85b-4e66-9500-ea867959f4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184493105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.184493105
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2024599903
Short name T1009
Test name
Test status
Simulation time 134074891990 ps
CPU time 57.32 seconds
Started Jun 02 01:22:37 PM PDT 24
Finished Jun 02 01:23:35 PM PDT 24
Peak memory 200428 kb
Host smart-acd5aaf9-7e82-4b62-a018-ada829ec3d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024599903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2024599903
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.701039182
Short name T153
Test name
Test status
Simulation time 181925502335 ps
CPU time 85.22 seconds
Started Jun 02 01:22:36 PM PDT 24
Finished Jun 02 01:24:02 PM PDT 24
Peak memory 200336 kb
Host smart-53da5264-8b9f-47ea-a846-a6e2428d4acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701039182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.701039182
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1010620855
Short name T1081
Test name
Test status
Simulation time 99902464053 ps
CPU time 171.88 seconds
Started Jun 02 01:22:37 PM PDT 24
Finished Jun 02 01:25:29 PM PDT 24
Peak memory 200440 kb
Host smart-cc4c3e2a-0c86-4d39-955e-7c6082f1bf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010620855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1010620855
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.600722272
Short name T1131
Test name
Test status
Simulation time 157734808763 ps
CPU time 298.7 seconds
Started Jun 02 01:22:38 PM PDT 24
Finished Jun 02 01:27:37 PM PDT 24
Peak memory 200404 kb
Host smart-457f53b0-6bf3-4af5-a5bc-8f9bcf9a0c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600722272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.600722272
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1126527721
Short name T213
Test name
Test status
Simulation time 97924983843 ps
CPU time 277.84 seconds
Started Jun 02 01:22:36 PM PDT 24
Finished Jun 02 01:27:15 PM PDT 24
Peak memory 200364 kb
Host smart-b03d6647-3a9a-4b77-af77-d29cebdd8e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126527721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1126527721
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1018775157
Short name T619
Test name
Test status
Simulation time 289632367926 ps
CPU time 328.79 seconds
Started Jun 02 01:22:38 PM PDT 24
Finished Jun 02 01:28:07 PM PDT 24
Peak memory 200364 kb
Host smart-36a1cbfe-0bc4-4d1e-be35-cbb1a6d78ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018775157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1018775157
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3652891217
Short name T210
Test name
Test status
Simulation time 59145063070 ps
CPU time 88.93 seconds
Started Jun 02 01:22:44 PM PDT 24
Finished Jun 02 01:24:13 PM PDT 24
Peak memory 200340 kb
Host smart-f6fa4961-3f27-4ee7-8706-d788cdf21f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652891217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3652891217
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2108291833
Short name T84
Test name
Test status
Simulation time 158814649424 ps
CPU time 63.47 seconds
Started Jun 02 01:22:43 PM PDT 24
Finished Jun 02 01:23:47 PM PDT 24
Peak memory 200300 kb
Host smart-b52a2f5e-cdbd-474c-a76a-31990f87e496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108291833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2108291833
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3528030916
Short name T899
Test name
Test status
Simulation time 66025570741 ps
CPU time 29.75 seconds
Started Jun 02 01:22:44 PM PDT 24
Finished Jun 02 01:23:15 PM PDT 24
Peak memory 200060 kb
Host smart-14172a64-6109-4754-86db-62b130520361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528030916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3528030916
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.412517593
Short name T1060
Test name
Test status
Simulation time 24872392600 ps
CPU time 37.76 seconds
Started Jun 02 01:22:44 PM PDT 24
Finished Jun 02 01:23:22 PM PDT 24
Peak memory 200328 kb
Host smart-e1983693-09d7-4460-94b5-8e4f2a0180a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412517593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.412517593
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2958353289
Short name T881
Test name
Test status
Simulation time 19461990 ps
CPU time 0.62 seconds
Started Jun 02 01:11:38 PM PDT 24
Finished Jun 02 01:11:39 PM PDT 24
Peak memory 195760 kb
Host smart-d2204712-bdeb-4bef-a7a6-73f404cfb75f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958353289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2958353289
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.778936743
Short name T164
Test name
Test status
Simulation time 82054584041 ps
CPU time 36.74 seconds
Started Jun 02 01:11:28 PM PDT 24
Finished Jun 02 01:12:05 PM PDT 24
Peak memory 200316 kb
Host smart-06942a47-0e2d-4e50-8f25-06c6071b5930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778936743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.778936743
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.24029888
Short name T420
Test name
Test status
Simulation time 17069085022 ps
CPU time 31.93 seconds
Started Jun 02 01:11:29 PM PDT 24
Finished Jun 02 01:12:01 PM PDT 24
Peak memory 200416 kb
Host smart-289e80fe-4140-44ab-b7a3-5c68a021e4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24029888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.24029888
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.917346878
Short name T215
Test name
Test status
Simulation time 193868565122 ps
CPU time 411.36 seconds
Started Jun 02 01:11:31 PM PDT 24
Finished Jun 02 01:18:23 PM PDT 24
Peak memory 200316 kb
Host smart-5972b829-e825-4d45-b071-4f7adfa998a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917346878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.917346878
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1807971767
Short name T363
Test name
Test status
Simulation time 55606066496 ps
CPU time 118.15 seconds
Started Jun 02 01:11:36 PM PDT 24
Finished Jun 02 01:13:35 PM PDT 24
Peak memory 200308 kb
Host smart-94cc2901-6b17-4ee1-9567-2eff6a65b8db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807971767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1807971767
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1524225620
Short name T1157
Test name
Test status
Simulation time 141836879366 ps
CPU time 1323.52 seconds
Started Jun 02 01:11:39 PM PDT 24
Finished Jun 02 01:33:43 PM PDT 24
Peak memory 200360 kb
Host smart-d335b95d-18f7-47bc-8fa3-7e8c22b4f43e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1524225620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1524225620
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2832447053
Short name T488
Test name
Test status
Simulation time 10465492948 ps
CPU time 8.28 seconds
Started Jun 02 01:11:38 PM PDT 24
Finished Jun 02 01:11:47 PM PDT 24
Peak memory 200388 kb
Host smart-9bf0e240-f0c0-4c17-91af-6fca1e2f4e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832447053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2832447053
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.131218360
Short name T106
Test name
Test status
Simulation time 94797366945 ps
CPU time 148.36 seconds
Started Jun 02 01:11:28 PM PDT 24
Finished Jun 02 01:13:57 PM PDT 24
Peak memory 200420 kb
Host smart-f37c1e96-2bf0-4ddc-8788-c7adbeb670da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131218360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.131218360
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3215115592
Short name T1029
Test name
Test status
Simulation time 23036209985 ps
CPU time 1322.22 seconds
Started Jun 02 01:11:41 PM PDT 24
Finished Jun 02 01:33:44 PM PDT 24
Peak memory 200380 kb
Host smart-a7c27754-fa39-4bf2-a76b-ae55d92a7f5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3215115592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3215115592
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.22000682
Short name T401
Test name
Test status
Simulation time 1402460065 ps
CPU time 0.96 seconds
Started Jun 02 01:11:28 PM PDT 24
Finished Jun 02 01:11:30 PM PDT 24
Peak memory 195852 kb
Host smart-7a850ee0-7855-4570-b3a8-a03874f39d23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22000682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.22000682
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3637601781
Short name T698
Test name
Test status
Simulation time 75445107492 ps
CPU time 36.13 seconds
Started Jun 02 01:11:37 PM PDT 24
Finished Jun 02 01:12:13 PM PDT 24
Peak memory 200232 kb
Host smart-2ce0d10f-d344-411c-8f1d-e2fb3483e938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637601781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3637601781
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3489244771
Short name T490
Test name
Test status
Simulation time 1408688556 ps
CPU time 1.88 seconds
Started Jun 02 01:11:37 PM PDT 24
Finished Jun 02 01:11:39 PM PDT 24
Peak memory 195708 kb
Host smart-cdb821a5-0aa5-4c8d-a644-f8c07308b504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489244771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3489244771
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3721859449
Short name T28
Test name
Test status
Simulation time 447056171 ps
CPU time 1.03 seconds
Started Jun 02 01:11:42 PM PDT 24
Finished Jun 02 01:11:43 PM PDT 24
Peak memory 218616 kb
Host smart-9a4c1932-a6dd-4d35-8210-3b889c952d0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721859449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3721859449
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2576626270
Short name T762
Test name
Test status
Simulation time 508964691 ps
CPU time 1.57 seconds
Started Jun 02 01:11:29 PM PDT 24
Finished Jun 02 01:11:31 PM PDT 24
Peak memory 199852 kb
Host smart-8299b09d-11d5-48c0-bd3e-b530ed5aeb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576626270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2576626270
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2267972192
Short name T306
Test name
Test status
Simulation time 104524858398 ps
CPU time 195.66 seconds
Started Jun 02 01:11:40 PM PDT 24
Finished Jun 02 01:14:56 PM PDT 24
Peak memory 200296 kb
Host smart-23b321d7-fdbe-4230-ac6a-f6bc4caa96d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267972192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2267972192
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2464523551
Short name T693
Test name
Test status
Simulation time 48884164110 ps
CPU time 1166.57 seconds
Started Jun 02 01:11:39 PM PDT 24
Finished Jun 02 01:31:06 PM PDT 24
Peak memory 217000 kb
Host smart-ba9b5293-706d-43c6-8b4d-1eb4dbd7d183
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464523551 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2464523551
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.618012324
Short name T329
Test name
Test status
Simulation time 786431366 ps
CPU time 1.45 seconds
Started Jun 02 01:11:41 PM PDT 24
Finished Jun 02 01:11:43 PM PDT 24
Peak memory 198420 kb
Host smart-b042625c-4d5a-4d22-838e-88ea52a954e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618012324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.618012324
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1867308101
Short name T1139
Test name
Test status
Simulation time 29639918882 ps
CPU time 52.48 seconds
Started Jun 02 01:11:28 PM PDT 24
Finished Jun 02 01:12:21 PM PDT 24
Peak memory 200352 kb
Host smart-b04fea44-e970-49b8-a2fa-b635489553da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867308101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1867308101
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3322583676
Short name T756
Test name
Test status
Simulation time 11857515 ps
CPU time 0.57 seconds
Started Jun 02 01:16:14 PM PDT 24
Finished Jun 02 01:16:15 PM PDT 24
Peak memory 195732 kb
Host smart-c0884e8b-2c4a-4c43-80cf-86417bb7060c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322583676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3322583676
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.873206495
Short name T948
Test name
Test status
Simulation time 62569271108 ps
CPU time 29.42 seconds
Started Jun 02 01:16:06 PM PDT 24
Finished Jun 02 01:16:35 PM PDT 24
Peak memory 200404 kb
Host smart-1a737c88-08f7-4ba6-bab3-6d025e26194b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873206495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.873206495
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.4239385320
Short name T151
Test name
Test status
Simulation time 127697180727 ps
CPU time 220.03 seconds
Started Jun 02 01:16:05 PM PDT 24
Finished Jun 02 01:19:46 PM PDT 24
Peak memory 200280 kb
Host smart-99175b9c-8ff6-467b-9e53-a85fdd90dd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239385320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.4239385320
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_intr.2530811583
Short name T1035
Test name
Test status
Simulation time 22166504937 ps
CPU time 43.52 seconds
Started Jun 02 01:16:12 PM PDT 24
Finished Jun 02 01:16:56 PM PDT 24
Peak memory 200408 kb
Host smart-5eea3f04-510b-401a-9ce2-909cdc2fe299
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530811583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2530811583
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1596504619
Short name T944
Test name
Test status
Simulation time 161533320564 ps
CPU time 151.97 seconds
Started Jun 02 01:16:19 PM PDT 24
Finished Jun 02 01:18:51 PM PDT 24
Peak memory 200560 kb
Host smart-9989e8b7-86f7-44f5-a784-216d46864123
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1596504619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1596504619
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2384670315
Short name T408
Test name
Test status
Simulation time 7800676224 ps
CPU time 5.36 seconds
Started Jun 02 01:16:14 PM PDT 24
Finished Jun 02 01:16:19 PM PDT 24
Peak memory 200336 kb
Host smart-3c074a36-50ca-410a-8092-99d762351c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384670315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2384670315
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2627154405
Short name T521
Test name
Test status
Simulation time 352064526505 ps
CPU time 134.21 seconds
Started Jun 02 01:16:12 PM PDT 24
Finished Jun 02 01:18:26 PM PDT 24
Peak memory 208640 kb
Host smart-8b78a7c4-e790-494c-a631-945d97a33e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627154405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2627154405
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2529846793
Short name T1120
Test name
Test status
Simulation time 27969383648 ps
CPU time 1463.5 seconds
Started Jun 02 01:16:12 PM PDT 24
Finished Jun 02 01:40:35 PM PDT 24
Peak memory 200364 kb
Host smart-603b0ea9-7a1f-4442-bc9d-6eec66e98802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2529846793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2529846793
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1704550494
Short name T629
Test name
Test status
Simulation time 3223582888 ps
CPU time 12.54 seconds
Started Jun 02 01:16:07 PM PDT 24
Finished Jun 02 01:16:20 PM PDT 24
Peak memory 199532 kb
Host smart-d94a6827-068e-49fd-891d-3280a55757b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1704550494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1704550494
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3153324321
Short name T245
Test name
Test status
Simulation time 70761388144 ps
CPU time 109.9 seconds
Started Jun 02 01:16:10 PM PDT 24
Finished Jun 02 01:18:00 PM PDT 24
Peak memory 200408 kb
Host smart-ede19238-9b14-45c3-8e0c-74028c88bcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153324321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3153324321
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2203496097
Short name T738
Test name
Test status
Simulation time 42889355183 ps
CPU time 17.01 seconds
Started Jun 02 01:16:11 PM PDT 24
Finished Jun 02 01:16:28 PM PDT 24
Peak memory 196392 kb
Host smart-b9101fcb-61db-4cb9-8b4f-80b154e41d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203496097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2203496097
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3249986575
Short name T416
Test name
Test status
Simulation time 533474683 ps
CPU time 3.5 seconds
Started Jun 02 01:16:07 PM PDT 24
Finished Jun 02 01:16:11 PM PDT 24
Peak memory 199528 kb
Host smart-634ed1c3-9016-459c-8653-413c4de8ae32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249986575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3249986575
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.4142081118
Short name T163
Test name
Test status
Simulation time 436368054297 ps
CPU time 2091.59 seconds
Started Jun 02 01:16:13 PM PDT 24
Finished Jun 02 01:51:05 PM PDT 24
Peak memory 200332 kb
Host smart-90145079-a0e4-40f3-872f-dac760e31cbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142081118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.4142081118
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3183897898
Short name T519
Test name
Test status
Simulation time 28367295615 ps
CPU time 321.33 seconds
Started Jun 02 01:16:13 PM PDT 24
Finished Jun 02 01:21:35 PM PDT 24
Peak memory 215112 kb
Host smart-45bf0bb5-99db-48c4-bbbe-7915fbd748bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183897898 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3183897898
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2270340986
Short name T823
Test name
Test status
Simulation time 656343792 ps
CPU time 1.89 seconds
Started Jun 02 01:16:14 PM PDT 24
Finished Jun 02 01:16:17 PM PDT 24
Peak memory 199768 kb
Host smart-7c67710c-41d0-47fe-8caa-61b5efaca9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270340986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2270340986
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3465392522
Short name T1059
Test name
Test status
Simulation time 100442681806 ps
CPU time 32.54 seconds
Started Jun 02 01:16:05 PM PDT 24
Finished Jun 02 01:16:38 PM PDT 24
Peak memory 200336 kb
Host smart-984c1c5c-a8d8-4dab-96c5-be9edde5a014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465392522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3465392522
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1584339058
Short name T935
Test name
Test status
Simulation time 10633052 ps
CPU time 0.55 seconds
Started Jun 02 01:16:27 PM PDT 24
Finished Jun 02 01:16:28 PM PDT 24
Peak memory 195176 kb
Host smart-4fd6671d-707c-4d25-b885-1b884b31210c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584339058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1584339058
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.184163540
Short name T863
Test name
Test status
Simulation time 91601561758 ps
CPU time 41.01 seconds
Started Jun 02 01:16:22 PM PDT 24
Finished Jun 02 01:17:03 PM PDT 24
Peak memory 200344 kb
Host smart-5d0f362a-f145-4a61-85d0-41238a4673c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184163540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.184163540
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2132111695
Short name T123
Test name
Test status
Simulation time 234612463535 ps
CPU time 31.07 seconds
Started Jun 02 01:16:23 PM PDT 24
Finished Jun 02 01:16:55 PM PDT 24
Peak memory 200284 kb
Host smart-00958e32-9a92-4447-9f48-a23e4b5803a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132111695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2132111695
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.20610097
Short name T605
Test name
Test status
Simulation time 43657261289 ps
CPU time 28.82 seconds
Started Jun 02 01:16:18 PM PDT 24
Finished Jun 02 01:16:48 PM PDT 24
Peak memory 200424 kb
Host smart-a4e74f9d-661d-4dcc-ae1a-acf29ca7ca58
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20610097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.20610097
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.722780107
Short name T636
Test name
Test status
Simulation time 95100945577 ps
CPU time 413.01 seconds
Started Jun 02 01:16:25 PM PDT 24
Finished Jun 02 01:23:18 PM PDT 24
Peak memory 200380 kb
Host smart-69eda9c3-4864-483a-b662-7939c5a85fc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=722780107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.722780107
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1751094760
Short name T19
Test name
Test status
Simulation time 10886563631 ps
CPU time 12.13 seconds
Started Jun 02 01:16:23 PM PDT 24
Finished Jun 02 01:16:36 PM PDT 24
Peak memory 199556 kb
Host smart-8f925147-8002-41f5-8a87-a22b07489758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751094760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1751094760
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3930303486
Short name T479
Test name
Test status
Simulation time 144804232553 ps
CPU time 58.14 seconds
Started Jun 02 01:16:23 PM PDT 24
Finished Jun 02 01:17:22 PM PDT 24
Peak memory 200900 kb
Host smart-1a97e862-908d-4f6e-8050-6f3a6baafa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930303486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3930303486
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1995310533
Short name T251
Test name
Test status
Simulation time 12510136807 ps
CPU time 528.96 seconds
Started Jun 02 01:16:27 PM PDT 24
Finished Jun 02 01:25:17 PM PDT 24
Peak memory 200272 kb
Host smart-e103050f-94bd-426b-8ef0-183bef084a1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1995310533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1995310533
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.4221275385
Short name T319
Test name
Test status
Simulation time 1191233613 ps
CPU time 1.06 seconds
Started Jun 02 01:16:19 PM PDT 24
Finished Jun 02 01:16:20 PM PDT 24
Peak memory 195864 kb
Host smart-8c880987-589c-4209-884a-6040865a9f3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221275385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.4221275385
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3528047448
Short name T916
Test name
Test status
Simulation time 12237946737 ps
CPU time 20.76 seconds
Started Jun 02 01:16:25 PM PDT 24
Finished Jun 02 01:16:46 PM PDT 24
Peak memory 200276 kb
Host smart-176e5c81-c4b1-4e8d-95aa-495390396ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528047448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3528047448
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3815556917
Short name T1128
Test name
Test status
Simulation time 3966842520 ps
CPU time 3.8 seconds
Started Jun 02 01:16:23 PM PDT 24
Finished Jun 02 01:16:27 PM PDT 24
Peak memory 196304 kb
Host smart-fb6e5fc7-4e7e-48d2-b0f9-869ab27bc1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815556917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3815556917
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.4159088
Short name T561
Test name
Test status
Simulation time 943087403 ps
CPU time 1.65 seconds
Started Jun 02 01:16:20 PM PDT 24
Finished Jun 02 01:16:22 PM PDT 24
Peak memory 199896 kb
Host smart-3aa5de54-7eb2-443d-ab00-7672f3772e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4159088
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1951307814
Short name T870
Test name
Test status
Simulation time 96375771642 ps
CPU time 62.64 seconds
Started Jun 02 01:16:26 PM PDT 24
Finished Jun 02 01:17:28 PM PDT 24
Peak memory 200312 kb
Host smart-675546fd-85f5-48bf-afad-78c6f3d5c5b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951307814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1951307814
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.210355571
Short name T537
Test name
Test status
Simulation time 110001279634 ps
CPU time 696.85 seconds
Started Jun 02 01:16:27 PM PDT 24
Finished Jun 02 01:28:04 PM PDT 24
Peak memory 225272 kb
Host smart-be893841-b0e2-4267-8be2-2e86fd92d455
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210355571 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.210355571
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3000631172
Short name T480
Test name
Test status
Simulation time 719880114 ps
CPU time 1.97 seconds
Started Jun 02 01:16:23 PM PDT 24
Finished Jun 02 01:16:25 PM PDT 24
Peak memory 199152 kb
Host smart-a1c0498c-63c2-4f95-b0f0-f723592b7e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000631172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3000631172
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.4187779391
Short name T982
Test name
Test status
Simulation time 9975935259 ps
CPU time 15.98 seconds
Started Jun 02 01:16:18 PM PDT 24
Finished Jun 02 01:16:35 PM PDT 24
Peak memory 200416 kb
Host smart-7696024d-8e9e-4a0d-90ab-a1b4f8ea4d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187779391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.4187779391
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2789367899
Short name T844
Test name
Test status
Simulation time 27439282 ps
CPU time 0.58 seconds
Started Jun 02 01:16:40 PM PDT 24
Finished Jun 02 01:16:42 PM PDT 24
Peak memory 195760 kb
Host smart-fa850c31-e582-4e4a-868e-af880480f6b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789367899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2789367899
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3894324213
Short name T735
Test name
Test status
Simulation time 123746385770 ps
CPU time 191.67 seconds
Started Jun 02 01:16:34 PM PDT 24
Finished Jun 02 01:19:45 PM PDT 24
Peak memory 200396 kb
Host smart-78693ed5-afa0-40c1-934d-8928e968506e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894324213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3894324213
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2496667542
Short name T141
Test name
Test status
Simulation time 66965136266 ps
CPU time 33.04 seconds
Started Jun 02 01:16:34 PM PDT 24
Finished Jun 02 01:17:07 PM PDT 24
Peak memory 200252 kb
Host smart-cb399047-ac85-4a74-a410-d61f10405970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496667542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2496667542
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3653722855
Short name T1042
Test name
Test status
Simulation time 69719572978 ps
CPU time 38.28 seconds
Started Jun 02 01:16:34 PM PDT 24
Finished Jun 02 01:17:13 PM PDT 24
Peak memory 200348 kb
Host smart-633d30b8-5487-4adb-9e4b-82b57b224615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653722855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3653722855
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3548633749
Short name T421
Test name
Test status
Simulation time 13299740628 ps
CPU time 7.88 seconds
Started Jun 02 01:16:33 PM PDT 24
Finished Jun 02 01:16:41 PM PDT 24
Peak memory 200196 kb
Host smart-4b8b879f-06ef-4e1b-93ea-10cc7797c808
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548633749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3548633749
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2576083420
Short name T352
Test name
Test status
Simulation time 87504273360 ps
CPU time 507.67 seconds
Started Jun 02 01:16:39 PM PDT 24
Finished Jun 02 01:25:08 PM PDT 24
Peak memory 200400 kb
Host smart-5acb188a-7809-4e51-82c4-541483dc4000
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2576083420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2576083420
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.43590387
Short name T327
Test name
Test status
Simulation time 2171057253 ps
CPU time 3.02 seconds
Started Jun 02 01:16:33 PM PDT 24
Finished Jun 02 01:16:36 PM PDT 24
Peak memory 198816 kb
Host smart-0d43e32a-21ea-49e0-baf3-3ecfdd22b98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43590387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.43590387
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1709530827
Short name T1058
Test name
Test status
Simulation time 23023729869 ps
CPU time 33.13 seconds
Started Jun 02 01:16:34 PM PDT 24
Finished Jun 02 01:17:08 PM PDT 24
Peak memory 198572 kb
Host smart-9747926f-b6a8-4541-ad14-cd05de8f2fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709530827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1709530827
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2171740970
Short name T1048
Test name
Test status
Simulation time 14491007550 ps
CPU time 310.87 seconds
Started Jun 02 01:16:35 PM PDT 24
Finished Jun 02 01:21:46 PM PDT 24
Peak memory 200396 kb
Host smart-e92f2f19-d316-4fa7-a6d3-e49d8f2cfd00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2171740970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2171740970
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2482889139
Short name T14
Test name
Test status
Simulation time 5151655296 ps
CPU time 39.65 seconds
Started Jun 02 01:16:35 PM PDT 24
Finished Jun 02 01:17:15 PM PDT 24
Peak memory 199844 kb
Host smart-77e9b2d2-a4a7-47a0-8ef3-231cf2c1af24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2482889139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2482889139
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.154854012
Short name T653
Test name
Test status
Simulation time 10639678642 ps
CPU time 18.73 seconds
Started Jun 02 01:16:34 PM PDT 24
Finished Jun 02 01:16:53 PM PDT 24
Peak memory 200052 kb
Host smart-3c4b76a9-c5a7-4e96-af4f-2d234440ae68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154854012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.154854012
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1146288549
Short name T1096
Test name
Test status
Simulation time 35971597425 ps
CPU time 18.26 seconds
Started Jun 02 01:16:35 PM PDT 24
Finished Jun 02 01:16:53 PM PDT 24
Peak memory 196340 kb
Host smart-7d5599c1-0048-4115-8a43-2e567a692d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146288549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1146288549
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1475338630
Short name T798
Test name
Test status
Simulation time 708554393 ps
CPU time 1.61 seconds
Started Jun 02 01:16:28 PM PDT 24
Finished Jun 02 01:16:29 PM PDT 24
Peak memory 198756 kb
Host smart-22957b29-8946-405e-a316-0ec9cce5096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475338630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1475338630
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3644511610
Short name T510
Test name
Test status
Simulation time 102119712243 ps
CPU time 85.03 seconds
Started Jun 02 01:16:40 PM PDT 24
Finished Jun 02 01:18:05 PM PDT 24
Peak memory 208704 kb
Host smart-4e7fa8ea-bda2-4adc-aced-f2ce1ac94068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644511610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3644511610
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3208083349
Short name T380
Test name
Test status
Simulation time 991777941 ps
CPU time 1.95 seconds
Started Jun 02 01:16:34 PM PDT 24
Finished Jun 02 01:16:36 PM PDT 24
Peak memory 198836 kb
Host smart-2799b6f9-483a-4722-9c6c-101d88b5e769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208083349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3208083349
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.852635181
Short name T1050
Test name
Test status
Simulation time 5050018629 ps
CPU time 8.12 seconds
Started Jun 02 01:16:26 PM PDT 24
Finished Jun 02 01:16:35 PM PDT 24
Peak memory 200336 kb
Host smart-f3cb4ff1-a922-4228-91be-8a85021ae868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852635181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.852635181
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.192090197
Short name T73
Test name
Test status
Simulation time 21410804 ps
CPU time 0.53 seconds
Started Jun 02 01:16:48 PM PDT 24
Finished Jun 02 01:16:49 PM PDT 24
Peak memory 194712 kb
Host smart-5107ebce-42b8-4be4-86ae-e2c74209dea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192090197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.192090197
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3675066123
Short name T271
Test name
Test status
Simulation time 37338978483 ps
CPU time 64.54 seconds
Started Jun 02 01:16:39 PM PDT 24
Finished Jun 02 01:17:44 PM PDT 24
Peak memory 200472 kb
Host smart-499ba587-d9ba-42e1-ac88-e06339bd4675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675066123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3675066123
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3385911663
Short name T761
Test name
Test status
Simulation time 33784577760 ps
CPU time 19.28 seconds
Started Jun 02 01:16:39 PM PDT 24
Finished Jun 02 01:16:59 PM PDT 24
Peak memory 200320 kb
Host smart-32587a17-7afc-4fec-b1ec-8bc8b73238dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385911663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3385911663
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1630593375
Short name T196
Test name
Test status
Simulation time 84242423117 ps
CPU time 125.64 seconds
Started Jun 02 01:16:42 PM PDT 24
Finished Jun 02 01:18:48 PM PDT 24
Peak memory 200400 kb
Host smart-80b9f425-23c1-4d39-9147-9deaeea655b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630593375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1630593375
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.202510929
Short name T516
Test name
Test status
Simulation time 45757092887 ps
CPU time 35.4 seconds
Started Jun 02 01:16:41 PM PDT 24
Finished Jun 02 01:17:17 PM PDT 24
Peak memory 200140 kb
Host smart-a9660fc2-d0a6-45c2-abaa-e72ebf2f248e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202510929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.202510929
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1393881961
Short name T991
Test name
Test status
Simulation time 77662629154 ps
CPU time 665.31 seconds
Started Jun 02 01:16:47 PM PDT 24
Finished Jun 02 01:27:52 PM PDT 24
Peak memory 200292 kb
Host smart-544d807b-b0d2-480b-9f86-2281138240e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393881961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1393881961
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3619398415
Short name T1053
Test name
Test status
Simulation time 2307258987 ps
CPU time 8.55 seconds
Started Jun 02 01:16:46 PM PDT 24
Finished Jun 02 01:16:55 PM PDT 24
Peak memory 200208 kb
Host smart-533eb62d-c4f5-40e6-852b-4022faa0dace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619398415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3619398415
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.387343795
Short name T309
Test name
Test status
Simulation time 71127226569 ps
CPU time 171.14 seconds
Started Jun 02 01:16:41 PM PDT 24
Finished Jun 02 01:19:32 PM PDT 24
Peak memory 200476 kb
Host smart-9e5ddd39-2891-4273-bdc7-cde18a0bb452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387343795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.387343795
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1564301187
Short name T869
Test name
Test status
Simulation time 22006745941 ps
CPU time 516.27 seconds
Started Jun 02 01:16:47 PM PDT 24
Finished Jun 02 01:25:24 PM PDT 24
Peak memory 200396 kb
Host smart-eb3a0d11-3a95-4e08-affa-ca3b7065cf74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1564301187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1564301187
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.791755832
Short name T1041
Test name
Test status
Simulation time 3596960040 ps
CPU time 17.85 seconds
Started Jun 02 01:16:40 PM PDT 24
Finished Jun 02 01:16:58 PM PDT 24
Peak memory 198652 kb
Host smart-f6b863a7-54b8-49cc-9723-9e74b23620fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791755832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.791755832
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3563013852
Short name T538
Test name
Test status
Simulation time 68425731648 ps
CPU time 114.18 seconds
Started Jun 02 01:16:46 PM PDT 24
Finished Jun 02 01:18:40 PM PDT 24
Peak memory 200340 kb
Host smart-19f37dba-15c1-468e-b7dc-c73d8e6c1ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563013852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3563013852
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.4009273292
Short name T661
Test name
Test status
Simulation time 6570268785 ps
CPU time 3.66 seconds
Started Jun 02 01:16:41 PM PDT 24
Finished Jun 02 01:16:45 PM PDT 24
Peak memory 196396 kb
Host smart-bbe92154-fe39-43ba-b909-9e920798a4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009273292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.4009273292
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2729232771
Short name T301
Test name
Test status
Simulation time 5467309865 ps
CPU time 19.62 seconds
Started Jun 02 01:16:40 PM PDT 24
Finished Jun 02 01:17:01 PM PDT 24
Peak memory 200192 kb
Host smart-528e7f66-53eb-4df9-9b6a-cd8b1d1d0d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729232771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2729232771
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3408582471
Short name T1040
Test name
Test status
Simulation time 299852051143 ps
CPU time 432.21 seconds
Started Jun 02 01:16:46 PM PDT 24
Finished Jun 02 01:23:59 PM PDT 24
Peak memory 200484 kb
Host smart-8ed6d203-385a-4a8f-a29c-5ba91e73c1df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408582471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3408582471
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2688892700
Short name T322
Test name
Test status
Simulation time 7441498602 ps
CPU time 13.14 seconds
Started Jun 02 01:16:45 PM PDT 24
Finished Jun 02 01:16:59 PM PDT 24
Peak memory 200216 kb
Host smart-159d5638-7a6d-4fc3-a795-2099cf4d8575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688892700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2688892700
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2946027971
Short name T257
Test name
Test status
Simulation time 66582092741 ps
CPU time 28.26 seconds
Started Jun 02 01:16:42 PM PDT 24
Finished Jun 02 01:17:11 PM PDT 24
Peak memory 200320 kb
Host smart-52386192-946d-4dd6-93c0-6cad7f5ca3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946027971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2946027971
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.4205256537
Short name T987
Test name
Test status
Simulation time 14718072 ps
CPU time 0.59 seconds
Started Jun 02 01:17:01 PM PDT 24
Finished Jun 02 01:17:02 PM PDT 24
Peak memory 195732 kb
Host smart-884656d3-d708-4385-bd67-fbee16bdacc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205256537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.4205256537
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3287087082
Short name T688
Test name
Test status
Simulation time 144162688064 ps
CPU time 210.71 seconds
Started Jun 02 01:16:47 PM PDT 24
Finished Jun 02 01:20:18 PM PDT 24
Peak memory 200400 kb
Host smart-99547d58-5557-4a3a-92c1-d903623f6bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287087082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3287087082
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3148159946
Short name T1142
Test name
Test status
Simulation time 134592815852 ps
CPU time 56.63 seconds
Started Jun 02 01:16:52 PM PDT 24
Finished Jun 02 01:17:48 PM PDT 24
Peak memory 200308 kb
Host smart-660f38b4-5834-4029-bf41-a03e0d13629d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148159946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3148159946
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3837993840
Short name T393
Test name
Test status
Simulation time 91720034306 ps
CPU time 263.16 seconds
Started Jun 02 01:16:52 PM PDT 24
Finished Jun 02 01:21:15 PM PDT 24
Peak memory 200260 kb
Host smart-380ef19d-36e5-47b7-91e9-f45a7d41b0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837993840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3837993840
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3125328978
Short name T15
Test name
Test status
Simulation time 16006173096 ps
CPU time 14.89 seconds
Started Jun 02 01:16:53 PM PDT 24
Finished Jun 02 01:17:08 PM PDT 24
Peak memory 197752 kb
Host smart-79cf2f7c-24c5-4a40-879e-2623ec09a19c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125328978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3125328978
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1778943616
Short name T883
Test name
Test status
Simulation time 59339653555 ps
CPU time 135.82 seconds
Started Jun 02 01:17:01 PM PDT 24
Finished Jun 02 01:19:17 PM PDT 24
Peak memory 200380 kb
Host smart-43ce5afc-1216-4b34-a926-96d60a93e044
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1778943616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1778943616
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3119074162
Short name T1167
Test name
Test status
Simulation time 9842208797 ps
CPU time 3.95 seconds
Started Jun 02 01:17:01 PM PDT 24
Finished Jun 02 01:17:06 PM PDT 24
Peak memory 200340 kb
Host smart-5e506bf0-812a-4715-a6cc-f7d5bd8337bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119074162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3119074162
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.790672896
Short name T1150
Test name
Test status
Simulation time 141017378224 ps
CPU time 347.09 seconds
Started Jun 02 01:16:52 PM PDT 24
Finished Jun 02 01:22:39 PM PDT 24
Peak memory 200268 kb
Host smart-929fa62c-465e-44f1-b0b8-55c2696e1473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790672896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.790672896
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3885351624
Short name T597
Test name
Test status
Simulation time 16655118846 ps
CPU time 233.87 seconds
Started Jun 02 01:17:02 PM PDT 24
Finished Jun 02 01:20:56 PM PDT 24
Peak memory 200348 kb
Host smart-8b204198-1be0-4763-b38e-8ba00a183482
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3885351624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3885351624
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2302152400
Short name T565
Test name
Test status
Simulation time 1830570300 ps
CPU time 1.75 seconds
Started Jun 02 01:16:53 PM PDT 24
Finished Jun 02 01:16:55 PM PDT 24
Peak memory 198432 kb
Host smart-11031112-7aef-49d2-99e4-1f57ff42053d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302152400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2302152400
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1639345546
Short name T467
Test name
Test status
Simulation time 129912829184 ps
CPU time 165.38 seconds
Started Jun 02 01:16:53 PM PDT 24
Finished Jun 02 01:19:38 PM PDT 24
Peak memory 200540 kb
Host smart-dd289130-a8a3-49e3-adfb-3f9b399522e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639345546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1639345546
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.54776204
Short name T717
Test name
Test status
Simulation time 5933424267 ps
CPU time 2.96 seconds
Started Jun 02 01:16:53 PM PDT 24
Finished Jun 02 01:16:56 PM PDT 24
Peak memory 196408 kb
Host smart-cee964b4-4500-4739-8e3a-0d96abae868d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54776204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.54776204
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3965065593
Short name T690
Test name
Test status
Simulation time 6163050050 ps
CPU time 12.34 seconds
Started Jun 02 01:16:45 PM PDT 24
Finished Jun 02 01:16:58 PM PDT 24
Peak memory 200204 kb
Host smart-e6e62d48-5a60-450d-af49-32dbaf86bbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965065593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3965065593
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2259411252
Short name T137
Test name
Test status
Simulation time 107904595622 ps
CPU time 115.53 seconds
Started Jun 02 01:17:01 PM PDT 24
Finished Jun 02 01:18:57 PM PDT 24
Peak memory 216108 kb
Host smart-a8ccf69d-2e35-4031-bfc6-b648aa5e8284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259411252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2259411252
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3238470878
Short name T228
Test name
Test status
Simulation time 79721828701 ps
CPU time 215.65 seconds
Started Jun 02 01:17:00 PM PDT 24
Finished Jun 02 01:20:36 PM PDT 24
Peak memory 215816 kb
Host smart-9d362d9a-9b00-4876-8752-0248238dc46b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238470878 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3238470878
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.4290012372
Short name T387
Test name
Test status
Simulation time 1329049666 ps
CPU time 1.75 seconds
Started Jun 02 01:16:54 PM PDT 24
Finished Jun 02 01:16:56 PM PDT 24
Peak memory 199176 kb
Host smart-cebc2028-a9ae-4461-99f6-880b9a4862d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290012372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.4290012372
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.636511767
Short name T741
Test name
Test status
Simulation time 62231400833 ps
CPU time 22.67 seconds
Started Jun 02 01:16:46 PM PDT 24
Finished Jun 02 01:17:09 PM PDT 24
Peak memory 200312 kb
Host smart-e3234d0a-c435-45d9-9ce9-39fe4ad467d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636511767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.636511767
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1501044342
Short name T350
Test name
Test status
Simulation time 11580002 ps
CPU time 0.55 seconds
Started Jun 02 01:17:14 PM PDT 24
Finished Jun 02 01:17:15 PM PDT 24
Peak memory 195784 kb
Host smart-35635fb3-55a4-4062-85a7-8b14f3b8b108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501044342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1501044342
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1653289718
Short name T433
Test name
Test status
Simulation time 47219839807 ps
CPU time 94.38 seconds
Started Jun 02 01:17:00 PM PDT 24
Finished Jun 02 01:18:35 PM PDT 24
Peak memory 200312 kb
Host smart-77031919-a0dd-475f-a941-1d445609abf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653289718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1653289718
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1832008909
Short name T673
Test name
Test status
Simulation time 10788417679 ps
CPU time 17.61 seconds
Started Jun 02 01:17:00 PM PDT 24
Finished Jun 02 01:17:18 PM PDT 24
Peak memory 200120 kb
Host smart-423ade60-bd2a-4157-bf6e-8fca1c6c471d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832008909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1832008909
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3128973090
Short name T875
Test name
Test status
Simulation time 37027732786 ps
CPU time 66.76 seconds
Started Jun 02 01:17:07 PM PDT 24
Finished Jun 02 01:18:14 PM PDT 24
Peak memory 200180 kb
Host smart-659457cb-5fb1-4257-8eca-0145c1f4f8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128973090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3128973090
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3992718198
Short name T489
Test name
Test status
Simulation time 24879303013 ps
CPU time 39.77 seconds
Started Jun 02 01:17:06 PM PDT 24
Finished Jun 02 01:17:46 PM PDT 24
Peak memory 200216 kb
Host smart-cf6cbcc1-ac19-47e4-9399-fa7cc50d57dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992718198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3992718198
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.4173863039
Short name T1098
Test name
Test status
Simulation time 253399486222 ps
CPU time 151.5 seconds
Started Jun 02 01:17:09 PM PDT 24
Finished Jun 02 01:19:41 PM PDT 24
Peak memory 200320 kb
Host smart-1639fbb3-a5ec-4e08-b3b5-0eae58389a88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4173863039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.4173863039
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2352462624
Short name T740
Test name
Test status
Simulation time 5635897158 ps
CPU time 10.82 seconds
Started Jun 02 01:17:08 PM PDT 24
Finished Jun 02 01:17:19 PM PDT 24
Peak memory 199400 kb
Host smart-0e222500-55f2-4d33-886b-a1d4f97be78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352462624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2352462624
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1609095528
Short name T563
Test name
Test status
Simulation time 132279374551 ps
CPU time 209.75 seconds
Started Jun 02 01:17:07 PM PDT 24
Finished Jun 02 01:20:38 PM PDT 24
Peak memory 200564 kb
Host smart-2cabb3d1-53cd-4536-9239-9f654921fbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609095528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1609095528
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.994328258
Short name T244
Test name
Test status
Simulation time 7881979938 ps
CPU time 329.63 seconds
Started Jun 02 01:17:07 PM PDT 24
Finished Jun 02 01:22:37 PM PDT 24
Peak memory 200244 kb
Host smart-789f5cd1-d975-48fb-a3de-82bd05ee5477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994328258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.994328258
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.759615321
Short name T984
Test name
Test status
Simulation time 4396604639 ps
CPU time 9.59 seconds
Started Jun 02 01:17:06 PM PDT 24
Finished Jun 02 01:17:16 PM PDT 24
Peak memory 199676 kb
Host smart-e1ea958d-c624-4c76-b34f-6e29542720ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759615321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.759615321
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2898837469
Short name T654
Test name
Test status
Simulation time 44757442519 ps
CPU time 12.08 seconds
Started Jun 02 01:17:07 PM PDT 24
Finished Jun 02 01:17:20 PM PDT 24
Peak memory 199944 kb
Host smart-3f8af439-609e-4dfd-8ee3-dd272909773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898837469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2898837469
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2017525002
Short name T544
Test name
Test status
Simulation time 440611620 ps
CPU time 1.52 seconds
Started Jun 02 01:17:05 PM PDT 24
Finished Jun 02 01:17:07 PM PDT 24
Peak memory 195728 kb
Host smart-15b15526-e162-4136-995d-cc8d9fe5f3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017525002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2017525002
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2367127701
Short name T859
Test name
Test status
Simulation time 558741103 ps
CPU time 1.96 seconds
Started Jun 02 01:17:01 PM PDT 24
Finished Jun 02 01:17:03 PM PDT 24
Peak memory 199680 kb
Host smart-459e8f0e-a6da-494d-98f9-9104246a57f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367127701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2367127701
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.356922218
Short name T820
Test name
Test status
Simulation time 9387487205 ps
CPU time 10.22 seconds
Started Jun 02 01:17:12 PM PDT 24
Finished Jun 02 01:17:23 PM PDT 24
Peak memory 200416 kb
Host smart-cd1c73a5-fed6-4ea4-bce3-a00a276a87be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356922218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.356922218
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.952830342
Short name T48
Test name
Test status
Simulation time 203937369264 ps
CPU time 369.32 seconds
Started Jun 02 01:17:06 PM PDT 24
Finished Jun 02 01:23:16 PM PDT 24
Peak memory 216548 kb
Host smart-48d4bd92-e7d0-4273-870e-198bca30ec9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952830342 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.952830342
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.581394561
Short name T878
Test name
Test status
Simulation time 783935166 ps
CPU time 1.5 seconds
Started Jun 02 01:17:07 PM PDT 24
Finished Jun 02 01:17:09 PM PDT 24
Peak memory 199272 kb
Host smart-94f8e5a2-896e-478c-badc-79724a40d3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581394561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.581394561
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.252353089
Short name T683
Test name
Test status
Simulation time 28162802445 ps
CPU time 65.21 seconds
Started Jun 02 01:16:58 PM PDT 24
Finished Jun 02 01:18:04 PM PDT 24
Peak memory 200324 kb
Host smart-5e78c06d-a734-4c4d-9622-80cd9771d169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252353089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.252353089
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3054504911
Short name T410
Test name
Test status
Simulation time 39300264 ps
CPU time 0.56 seconds
Started Jun 02 01:17:20 PM PDT 24
Finished Jun 02 01:17:21 PM PDT 24
Peak memory 195784 kb
Host smart-95ce5126-7faa-4b80-86df-524674bf740b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054504911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3054504911
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2582058586
Short name T794
Test name
Test status
Simulation time 30089395078 ps
CPU time 52.17 seconds
Started Jun 02 01:17:15 PM PDT 24
Finished Jun 02 01:18:08 PM PDT 24
Peak memory 200380 kb
Host smart-89014384-644c-4897-b3c3-235415670230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582058586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2582058586
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2774809944
Short name T1116
Test name
Test status
Simulation time 22391651692 ps
CPU time 41.37 seconds
Started Jun 02 01:17:16 PM PDT 24
Finished Jun 02 01:17:57 PM PDT 24
Peak memory 200360 kb
Host smart-3210dffe-c1e2-4e2f-ad51-aa14781ff577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774809944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2774809944
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.108256173
Short name T481
Test name
Test status
Simulation time 72402809708 ps
CPU time 61.21 seconds
Started Jun 02 01:17:12 PM PDT 24
Finished Jun 02 01:18:13 PM PDT 24
Peak memory 200336 kb
Host smart-98ba6d82-b9c8-4976-bb36-2a17c531a48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108256173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.108256173
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.444540676
Short name T972
Test name
Test status
Simulation time 12897822997 ps
CPU time 10.56 seconds
Started Jun 02 01:17:13 PM PDT 24
Finished Jun 02 01:17:24 PM PDT 24
Peak memory 196480 kb
Host smart-6c5b060d-2e64-4962-bec9-9ac3ffab4a46
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444540676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.444540676
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.974386167
Short name T770
Test name
Test status
Simulation time 84773549949 ps
CPU time 693.3 seconds
Started Jun 02 01:17:16 PM PDT 24
Finished Jun 02 01:28:49 PM PDT 24
Peak memory 200416 kb
Host smart-7c4069ed-2951-46e8-8d4f-d5463c89c4e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=974386167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.974386167
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.721816360
Short name T448
Test name
Test status
Simulation time 2840953033 ps
CPU time 7.74 seconds
Started Jun 02 01:17:15 PM PDT 24
Finished Jun 02 01:17:23 PM PDT 24
Peak memory 198908 kb
Host smart-4569a1da-2893-4a36-8fe2-9eefc3f82204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721816360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.721816360
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.258943293
Short name T803
Test name
Test status
Simulation time 113743063054 ps
CPU time 148.41 seconds
Started Jun 02 01:17:14 PM PDT 24
Finished Jun 02 01:19:43 PM PDT 24
Peak memory 216040 kb
Host smart-44981e10-e2cf-4e49-b8d3-bc1f48bf12cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258943293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.258943293
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.2018430563
Short name T502
Test name
Test status
Simulation time 19156197690 ps
CPU time 202 seconds
Started Jun 02 01:17:14 PM PDT 24
Finished Jun 02 01:20:37 PM PDT 24
Peak memory 200408 kb
Host smart-e7350ab3-8892-4c60-b042-100fa7c0c932
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2018430563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2018430563
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.344562156
Short name T877
Test name
Test status
Simulation time 3078961468 ps
CPU time 7.08 seconds
Started Jun 02 01:17:13 PM PDT 24
Finished Jun 02 01:17:21 PM PDT 24
Peak memory 198456 kb
Host smart-c9e72147-7ecb-4837-b4b8-9c2b2ec27cb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=344562156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.344562156
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1761631992
Short name T708
Test name
Test status
Simulation time 20967539026 ps
CPU time 37.1 seconds
Started Jun 02 01:17:14 PM PDT 24
Finished Jun 02 01:17:51 PM PDT 24
Peak memory 200316 kb
Host smart-89833941-9048-4178-ac36-a5094e470d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761631992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1761631992
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.903130587
Short name T882
Test name
Test status
Simulation time 3705946734 ps
CPU time 6.78 seconds
Started Jun 02 01:17:12 PM PDT 24
Finished Jun 02 01:17:19 PM PDT 24
Peak memory 196388 kb
Host smart-e308e797-1b82-4747-8e7c-5a8b691f0b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903130587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.903130587
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2747927499
Short name T320
Test name
Test status
Simulation time 637087894 ps
CPU time 2.35 seconds
Started Jun 02 01:17:14 PM PDT 24
Finished Jun 02 01:17:17 PM PDT 24
Peak memory 199132 kb
Host smart-e066eec2-5134-4bfa-ad97-0e3a4d5c3df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747927499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2747927499
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3648505510
Short name T687
Test name
Test status
Simulation time 144731224552 ps
CPU time 289.18 seconds
Started Jun 02 01:17:25 PM PDT 24
Finished Jun 02 01:22:14 PM PDT 24
Peak memory 200424 kb
Host smart-3505c3f0-6106-4596-a6fa-441b91756ed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648505510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3648505510
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1120007984
Short name T424
Test name
Test status
Simulation time 30382779584 ps
CPU time 583.87 seconds
Started Jun 02 01:17:20 PM PDT 24
Finished Jun 02 01:27:04 PM PDT 24
Peak memory 216884 kb
Host smart-e27d42d4-2302-4a1c-9f17-d37430d1f573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120007984 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1120007984
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3006156964
Short name T1091
Test name
Test status
Simulation time 2956598800 ps
CPU time 1.31 seconds
Started Jun 02 01:17:13 PM PDT 24
Finished Jun 02 01:17:14 PM PDT 24
Peak memory 199652 kb
Host smart-85671c70-74c1-465d-8490-d69a053cadf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006156964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3006156964
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3826451624
Short name T1153
Test name
Test status
Simulation time 15195557074 ps
CPU time 25.68 seconds
Started Jun 02 01:17:12 PM PDT 24
Finished Jun 02 01:17:38 PM PDT 24
Peak memory 200416 kb
Host smart-c469fab4-463f-4f3f-b222-da9726eb5b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826451624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3826451624
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2324763787
Short name T797
Test name
Test status
Simulation time 109718342 ps
CPU time 0.56 seconds
Started Jun 02 01:17:36 PM PDT 24
Finished Jun 02 01:17:37 PM PDT 24
Peak memory 195788 kb
Host smart-35ef7a75-14a5-4f3d-899a-914481f08f45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324763787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2324763787
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1440622534
Short name T120
Test name
Test status
Simulation time 72825113760 ps
CPU time 31.14 seconds
Started Jun 02 01:17:22 PM PDT 24
Finished Jun 02 01:17:53 PM PDT 24
Peak memory 200392 kb
Host smart-5556c287-9f8b-4b56-9d7b-b2ce95cbaf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440622534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1440622534
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3539545036
Short name T640
Test name
Test status
Simulation time 34327796487 ps
CPU time 16.55 seconds
Started Jun 02 01:17:25 PM PDT 24
Finished Jun 02 01:17:42 PM PDT 24
Peak memory 200280 kb
Host smart-105e75bc-8e66-47bc-bb78-4bc332ea761a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539545036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3539545036
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.4186355386
Short name T746
Test name
Test status
Simulation time 184849663526 ps
CPU time 43.32 seconds
Started Jun 02 01:17:25 PM PDT 24
Finished Jun 02 01:18:08 PM PDT 24
Peak memory 200416 kb
Host smart-e3f25c16-38a8-4df9-a2ca-594f1da1dd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186355386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.4186355386
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.939190809
Short name T582
Test name
Test status
Simulation time 25193748084 ps
CPU time 41.6 seconds
Started Jun 02 01:17:25 PM PDT 24
Finished Jun 02 01:18:07 PM PDT 24
Peak memory 200084 kb
Host smart-467bf02e-fa36-4699-8aac-9bb2bee1740c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939190809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.939190809
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.350067050
Short name T444
Test name
Test status
Simulation time 295541023029 ps
CPU time 145.58 seconds
Started Jun 02 01:17:34 PM PDT 24
Finished Jun 02 01:20:00 PM PDT 24
Peak memory 200372 kb
Host smart-66d7b8e1-62ac-4cff-9165-4df21ac397c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=350067050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.350067050
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.263318929
Short name T347
Test name
Test status
Simulation time 9160841248 ps
CPU time 6 seconds
Started Jun 02 01:17:27 PM PDT 24
Finished Jun 02 01:17:33 PM PDT 24
Peak memory 200264 kb
Host smart-ee4f7dad-0358-49f0-8e7b-1153749677ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263318929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.263318929
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2586743973
Short name T641
Test name
Test status
Simulation time 139716284258 ps
CPU time 334.72 seconds
Started Jun 02 01:17:26 PM PDT 24
Finished Jun 02 01:23:01 PM PDT 24
Peak memory 215984 kb
Host smart-eeb15a02-5e14-4ca2-a2ce-35841b6f7929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586743973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2586743973
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.3914177193
Short name T1123
Test name
Test status
Simulation time 12555487056 ps
CPU time 703.52 seconds
Started Jun 02 01:17:27 PM PDT 24
Finished Jun 02 01:29:11 PM PDT 24
Peak memory 200312 kb
Host smart-5328892e-ea11-4129-96b2-5e7ae55f30a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3914177193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3914177193
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3855678364
Short name T364
Test name
Test status
Simulation time 4005610640 ps
CPU time 8.89 seconds
Started Jun 02 01:17:22 PM PDT 24
Finished Jun 02 01:17:31 PM PDT 24
Peak memory 199576 kb
Host smart-c387beb6-d3f3-47b1-98f2-e1ffdbaaa7ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3855678364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3855678364
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1446650067
Short name T474
Test name
Test status
Simulation time 190096763919 ps
CPU time 60.43 seconds
Started Jun 02 01:17:26 PM PDT 24
Finished Jun 02 01:18:27 PM PDT 24
Peak memory 200300 kb
Host smart-091a586c-1709-4c5c-a540-66154a7eeb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446650067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1446650067
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.244441653
Short name T366
Test name
Test status
Simulation time 816936131 ps
CPU time 1.85 seconds
Started Jun 02 01:17:27 PM PDT 24
Finished Jun 02 01:17:29 PM PDT 24
Peak memory 196032 kb
Host smart-755e33c2-b85f-4b6e-9847-bfeffd8183a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244441653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.244441653
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.4034556606
Short name T903
Test name
Test status
Simulation time 744237214 ps
CPU time 1 seconds
Started Jun 02 01:17:20 PM PDT 24
Finished Jun 02 01:17:21 PM PDT 24
Peak memory 198916 kb
Host smart-9df16391-bd27-4e69-b62e-5064ce5ae886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034556606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.4034556606
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1608412390
Short name T173
Test name
Test status
Simulation time 233373161741 ps
CPU time 139.1 seconds
Started Jun 02 01:17:33 PM PDT 24
Finished Jun 02 01:19:52 PM PDT 24
Peak memory 200356 kb
Host smart-54b2f750-75ce-4717-8641-c8e5680c6129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608412390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1608412390
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1618963931
Short name T1160
Test name
Test status
Simulation time 192834909754 ps
CPU time 793.81 seconds
Started Jun 02 01:17:35 PM PDT 24
Finished Jun 02 01:30:49 PM PDT 24
Peak memory 225224 kb
Host smart-7993cd90-5f2e-4aab-8fc2-677a77bfaaf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618963931 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1618963931
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3172247225
Short name T694
Test name
Test status
Simulation time 1014676948 ps
CPU time 3.55 seconds
Started Jun 02 01:17:28 PM PDT 24
Finished Jun 02 01:17:32 PM PDT 24
Peak memory 199184 kb
Host smart-e44342e4-75af-41f1-a69e-f0d97f9f3134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172247225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3172247225
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2350304950
Short name T906
Test name
Test status
Simulation time 8737943999 ps
CPU time 4.58 seconds
Started Jun 02 01:17:21 PM PDT 24
Finished Jun 02 01:17:26 PM PDT 24
Peak memory 199140 kb
Host smart-5ce630c3-d532-4516-99ef-b921bd810673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350304950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2350304950
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1649445614
Short name T1013
Test name
Test status
Simulation time 39507522 ps
CPU time 0.53 seconds
Started Jun 02 01:17:40 PM PDT 24
Finished Jun 02 01:17:40 PM PDT 24
Peak memory 195760 kb
Host smart-4bd4dde4-1f8e-4bbc-84e9-2b4e752646ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649445614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1649445614
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.759416961
Short name T166
Test name
Test status
Simulation time 71560306109 ps
CPU time 33.16 seconds
Started Jun 02 01:17:34 PM PDT 24
Finished Jun 02 01:18:07 PM PDT 24
Peak memory 200356 kb
Host smart-b967f377-31ef-422f-b5a1-e7063ba98edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759416961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.759416961
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3954219432
Short name T261
Test name
Test status
Simulation time 135395307967 ps
CPU time 198.61 seconds
Started Jun 02 01:17:34 PM PDT 24
Finished Jun 02 01:20:53 PM PDT 24
Peak memory 200372 kb
Host smart-95de629b-c3e1-434c-8cf5-3a1f99385202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954219432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3954219432
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1669345418
Short name T633
Test name
Test status
Simulation time 81684490140 ps
CPU time 39.24 seconds
Started Jun 02 01:17:33 PM PDT 24
Finished Jun 02 01:18:13 PM PDT 24
Peak memory 200260 kb
Host smart-293931f5-22c3-426b-b68e-0ce89ee3af67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669345418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1669345418
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3012985198
Short name T766
Test name
Test status
Simulation time 18949266234 ps
CPU time 15.89 seconds
Started Jun 02 01:17:34 PM PDT 24
Finished Jun 02 01:17:50 PM PDT 24
Peak memory 197528 kb
Host smart-a7bd9095-9085-476f-ab91-efe6f5962249
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012985198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3012985198
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2278165939
Short name T917
Test name
Test status
Simulation time 186475708221 ps
CPU time 299.71 seconds
Started Jun 02 01:17:41 PM PDT 24
Finished Jun 02 01:22:41 PM PDT 24
Peak memory 200260 kb
Host smart-89437476-f354-4271-9257-63e7c0de705f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2278165939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2278165939
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2626452716
Short name T343
Test name
Test status
Simulation time 1060381157 ps
CPU time 1.81 seconds
Started Jun 02 01:17:41 PM PDT 24
Finished Jun 02 01:17:43 PM PDT 24
Peak memory 195796 kb
Host smart-11fba011-4eee-40b5-bf81-a85a86d05512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626452716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2626452716
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2251243336
Short name T334
Test name
Test status
Simulation time 179291457041 ps
CPU time 131.24 seconds
Started Jun 02 01:17:33 PM PDT 24
Finished Jun 02 01:19:44 PM PDT 24
Peak memory 200500 kb
Host smart-6bd9bc77-df4b-450a-b672-06e1cdde88d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251243336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2251243336
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1683856718
Short name T1166
Test name
Test status
Simulation time 31860909489 ps
CPU time 428.4 seconds
Started Jun 02 01:17:41 PM PDT 24
Finished Jun 02 01:24:50 PM PDT 24
Peak memory 200324 kb
Host smart-dbb42780-f5a6-49de-9a57-a1575b4bf4fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1683856718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1683856718
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3450069875
Short name T18
Test name
Test status
Simulation time 7759157121 ps
CPU time 66.72 seconds
Started Jun 02 01:17:34 PM PDT 24
Finished Jun 02 01:18:41 PM PDT 24
Peak memory 198688 kb
Host smart-ba2918d2-7797-481e-b787-6de64f680adf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3450069875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3450069875
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2061461734
Short name T147
Test name
Test status
Simulation time 30156579521 ps
CPU time 14.39 seconds
Started Jun 02 01:17:41 PM PDT 24
Finished Jun 02 01:17:56 PM PDT 24
Peak memory 200344 kb
Host smart-aabd73ba-4f34-4da2-b26a-1769a59cbfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061461734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2061461734
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2306734300
Short name T593
Test name
Test status
Simulation time 3954556459 ps
CPU time 1.21 seconds
Started Jun 02 01:17:40 PM PDT 24
Finished Jun 02 01:17:41 PM PDT 24
Peak memory 196320 kb
Host smart-41e2fb18-6a2e-4abd-96c6-f49a179ebe3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306734300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2306734300
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3236298654
Short name T624
Test name
Test status
Simulation time 5885615593 ps
CPU time 16.08 seconds
Started Jun 02 01:17:34 PM PDT 24
Finished Jun 02 01:17:50 PM PDT 24
Peak memory 199524 kb
Host smart-a80b59a4-13cb-4ebd-9ea5-c5705e65b5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236298654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3236298654
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.478504306
Short name T532
Test name
Test status
Simulation time 42159212482 ps
CPU time 47.31 seconds
Started Jun 02 01:17:40 PM PDT 24
Finished Jun 02 01:18:28 PM PDT 24
Peak memory 200392 kb
Host smart-ffc247f8-8c8f-4a21-8e9e-c41b295b8ca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478504306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.478504306
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1450181975
Short name T96
Test name
Test status
Simulation time 32921110055 ps
CPU time 334.55 seconds
Started Jun 02 01:17:43 PM PDT 24
Finished Jun 02 01:23:18 PM PDT 24
Peak memory 209784 kb
Host smart-918c4463-13dd-48db-bcb9-4112e15b0ae5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450181975 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1450181975
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1566378320
Short name T697
Test name
Test status
Simulation time 1753924562 ps
CPU time 1.79 seconds
Started Jun 02 01:17:43 PM PDT 24
Finished Jun 02 01:17:45 PM PDT 24
Peak memory 198668 kb
Host smart-765bb884-f84a-4497-921d-769949e64186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566378320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1566378320
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.965124823
Short name T1074
Test name
Test status
Simulation time 58578829527 ps
CPU time 152.39 seconds
Started Jun 02 01:17:34 PM PDT 24
Finished Jun 02 01:20:07 PM PDT 24
Peak memory 200356 kb
Host smart-1ab54e75-f147-4eb8-9af0-709adb2c80d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965124823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.965124823
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2767706333
Short name T579
Test name
Test status
Simulation time 85496585 ps
CPU time 0.55 seconds
Started Jun 02 01:17:55 PM PDT 24
Finished Jun 02 01:17:56 PM PDT 24
Peak memory 195772 kb
Host smart-fc710354-b037-4f86-8d9d-7f8ca5f8ae44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767706333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2767706333
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.289612913
Short name T391
Test name
Test status
Simulation time 149956200842 ps
CPU time 253.25 seconds
Started Jun 02 01:17:50 PM PDT 24
Finished Jun 02 01:22:04 PM PDT 24
Peak memory 200372 kb
Host smart-d42610af-0f48-4162-954a-30dc1f6037f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289612913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.289612913
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2269062426
Short name T786
Test name
Test status
Simulation time 124585534361 ps
CPU time 65.39 seconds
Started Jun 02 01:17:48 PM PDT 24
Finished Jun 02 01:18:54 PM PDT 24
Peak memory 200344 kb
Host smart-1373ba42-b7aa-43b7-832f-d263c160bacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269062426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2269062426
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.4018736799
Short name T1168
Test name
Test status
Simulation time 41612628466 ps
CPU time 42.04 seconds
Started Jun 02 01:17:48 PM PDT 24
Finished Jun 02 01:18:30 PM PDT 24
Peak memory 200368 kb
Host smart-9f32d60d-305e-41c6-bf06-75d176fcc087
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018736799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.4018736799
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.568395993
Short name T267
Test name
Test status
Simulation time 56449010533 ps
CPU time 518.57 seconds
Started Jun 02 01:17:58 PM PDT 24
Finished Jun 02 01:26:37 PM PDT 24
Peak memory 200412 kb
Host smart-ffb12407-c8cb-4ae5-8bad-2e94edc06186
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=568395993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.568395993
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.636181933
Short name T941
Test name
Test status
Simulation time 3168515920 ps
CPU time 3.58 seconds
Started Jun 02 01:17:56 PM PDT 24
Finished Jun 02 01:18:00 PM PDT 24
Peak memory 197896 kb
Host smart-6e2e8c21-02b2-4d17-8584-0db609da1848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636181933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.636181933
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1862284633
Short name T617
Test name
Test status
Simulation time 28303814682 ps
CPU time 22.19 seconds
Started Jun 02 01:17:49 PM PDT 24
Finished Jun 02 01:18:12 PM PDT 24
Peak memory 197672 kb
Host smart-b0a92d81-9910-4b0e-b585-dfd77df45d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862284633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1862284633
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2144011394
Short name T974
Test name
Test status
Simulation time 24700497277 ps
CPU time 704 seconds
Started Jun 02 01:17:59 PM PDT 24
Finished Jun 02 01:29:43 PM PDT 24
Peak memory 200412 kb
Host smart-63bb1978-0110-4da2-9ab8-fbc367e0e2c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2144011394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2144011394
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2872448171
Short name T802
Test name
Test status
Simulation time 1378227562 ps
CPU time 2.81 seconds
Started Jun 02 01:17:48 PM PDT 24
Finished Jun 02 01:17:51 PM PDT 24
Peak memory 198548 kb
Host smart-6b16961f-8a34-40c1-95b9-dcab10ce952a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2872448171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2872448171
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3996670258
Short name T170
Test name
Test status
Simulation time 118380074129 ps
CPU time 276.59 seconds
Started Jun 02 01:17:48 PM PDT 24
Finished Jun 02 01:22:24 PM PDT 24
Peak memory 200368 kb
Host smart-c6ed8cae-6993-4c84-b8d7-30caf0ed6385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996670258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3996670258
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2600488856
Short name T920
Test name
Test status
Simulation time 4310486772 ps
CPU time 2.32 seconds
Started Jun 02 01:17:48 PM PDT 24
Finished Jun 02 01:17:51 PM PDT 24
Peak memory 196392 kb
Host smart-4c37f0b4-1e27-480b-a713-1371160343ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600488856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2600488856
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.636722812
Short name T744
Test name
Test status
Simulation time 533117205 ps
CPU time 2.16 seconds
Started Jun 02 01:17:48 PM PDT 24
Finished Jun 02 01:17:51 PM PDT 24
Peak memory 199896 kb
Host smart-194e6d30-d25e-4fb9-a1fd-676afcbc720e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636722812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.636722812
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3208137192
Short name T311
Test name
Test status
Simulation time 343971011613 ps
CPU time 385.5 seconds
Started Jun 02 01:17:56 PM PDT 24
Finished Jun 02 01:24:22 PM PDT 24
Peak memory 200508 kb
Host smart-b30b9df2-9d35-47d1-8651-899367046e9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208137192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3208137192
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1037956234
Short name T821
Test name
Test status
Simulation time 18154877039 ps
CPU time 59.81 seconds
Started Jun 02 01:17:56 PM PDT 24
Finished Jun 02 01:18:56 PM PDT 24
Peak memory 210112 kb
Host smart-39f2b072-731f-42e8-9a28-50204600b062
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037956234 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1037956234
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.770537097
Short name T795
Test name
Test status
Simulation time 1363435301 ps
CPU time 2.7 seconds
Started Jun 02 01:17:57 PM PDT 24
Finished Jun 02 01:18:00 PM PDT 24
Peak memory 200032 kb
Host smart-c82cb86a-a333-48c1-b1d7-78777bf30d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770537097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.770537097
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2110239617
Short name T721
Test name
Test status
Simulation time 53960186623 ps
CPU time 70.1 seconds
Started Jun 02 01:17:49 PM PDT 24
Finished Jun 02 01:18:59 PM PDT 24
Peak memory 200392 kb
Host smart-6cfdcba5-d282-45ef-8ebf-fea65419afaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110239617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2110239617
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.776625058
Short name T405
Test name
Test status
Simulation time 13560110 ps
CPU time 0.54 seconds
Started Jun 02 01:11:42 PM PDT 24
Finished Jun 02 01:11:43 PM PDT 24
Peak memory 194728 kb
Host smart-c75dd6fb-ac27-432b-a8be-438d2ac7605c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776625058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.776625058
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1662569936
Short name T811
Test name
Test status
Simulation time 108231430750 ps
CPU time 105.65 seconds
Started Jun 02 01:11:41 PM PDT 24
Finished Jun 02 01:13:27 PM PDT 24
Peak memory 200240 kb
Host smart-733b6109-1919-4dcf-9736-66fda41c76a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662569936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1662569936
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1560629115
Short name T110
Test name
Test status
Simulation time 25898841122 ps
CPU time 44.75 seconds
Started Jun 02 01:11:42 PM PDT 24
Finished Jun 02 01:12:27 PM PDT 24
Peak memory 200352 kb
Host smart-828611f5-a454-4685-9168-78356d0a3352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560629115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1560629115
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2592898947
Short name T449
Test name
Test status
Simulation time 50162596848 ps
CPU time 57.4 seconds
Started Jun 02 01:11:40 PM PDT 24
Finished Jun 02 01:12:38 PM PDT 24
Peak memory 200372 kb
Host smart-75b3271f-8d21-4aba-a383-eed510af05ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592898947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2592898947
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1127066789
Short name T921
Test name
Test status
Simulation time 23813672555 ps
CPU time 7.32 seconds
Started Jun 02 01:11:40 PM PDT 24
Finished Jun 02 01:11:48 PM PDT 24
Peak memory 197840 kb
Host smart-5c8a8a6d-cd09-4e8e-a73d-dddd95386b17
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127066789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1127066789
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1599756656
Short name T560
Test name
Test status
Simulation time 344686186987 ps
CPU time 164.48 seconds
Started Jun 02 01:11:39 PM PDT 24
Finished Jun 02 01:14:24 PM PDT 24
Peak memory 200300 kb
Host smart-dcecf7e6-3d22-49d7-8aaf-c44b862d4355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1599756656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1599756656
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.331497672
Short name T432
Test name
Test status
Simulation time 700126232 ps
CPU time 1.12 seconds
Started Jun 02 01:11:38 PM PDT 24
Finished Jun 02 01:11:40 PM PDT 24
Peak memory 195836 kb
Host smart-db97f9ef-d9fd-43aa-9997-6aa73d2e392d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331497672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.331497672
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3699323815
Short name T247
Test name
Test status
Simulation time 70421762650 ps
CPU time 169.17 seconds
Started Jun 02 01:11:40 PM PDT 24
Finished Jun 02 01:14:30 PM PDT 24
Peak memory 200396 kb
Host smart-58485811-4db4-40ec-aafd-a98e874a0c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699323815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3699323815
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3687305557
Short name T286
Test name
Test status
Simulation time 14359585162 ps
CPU time 254.61 seconds
Started Jun 02 01:11:38 PM PDT 24
Finished Jun 02 01:15:53 PM PDT 24
Peak memory 200432 kb
Host smart-19d5a32b-f0f2-4178-8ce2-ffd5080a6ae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3687305557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3687305557
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2448163558
Short name T578
Test name
Test status
Simulation time 4097187710 ps
CPU time 40.44 seconds
Started Jun 02 01:11:39 PM PDT 24
Finished Jun 02 01:12:20 PM PDT 24
Peak memory 198348 kb
Host smart-0a151cdb-ebc2-48d0-945a-feda39ca695e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2448163558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2448163558
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.4194817930
Short name T1105
Test name
Test status
Simulation time 45829417888 ps
CPU time 21.24 seconds
Started Jun 02 01:11:40 PM PDT 24
Finished Jun 02 01:12:02 PM PDT 24
Peak memory 200328 kb
Host smart-7c7aae6c-896a-461b-a5f3-a435846e54a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194817930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.4194817930
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.4213056569
Short name T407
Test name
Test status
Simulation time 3758072429 ps
CPU time 1.48 seconds
Started Jun 02 01:11:39 PM PDT 24
Finished Jun 02 01:11:41 PM PDT 24
Peak memory 196400 kb
Host smart-c5140085-b9a4-4be5-9c50-7fd38a3d285f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213056569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.4213056569
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1769113285
Short name T81
Test name
Test status
Simulation time 397678087 ps
CPU time 0.76 seconds
Started Jun 02 01:11:39 PM PDT 24
Finished Jun 02 01:11:40 PM PDT 24
Peak memory 218564 kb
Host smart-1ebd984e-3701-47cb-b890-3d3398e11db1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769113285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1769113285
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1549627941
Short name T304
Test name
Test status
Simulation time 515627049 ps
CPU time 1.47 seconds
Started Jun 02 01:11:39 PM PDT 24
Finished Jun 02 01:11:41 PM PDT 24
Peak memory 199600 kb
Host smart-6bf2bdef-88db-4749-b167-b978fddf0716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549627941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1549627941
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2269083817
Short name T1056
Test name
Test status
Simulation time 6537968261 ps
CPU time 19.27 seconds
Started Jun 02 01:11:40 PM PDT 24
Finished Jun 02 01:12:00 PM PDT 24
Peak memory 199728 kb
Host smart-56a3a19a-b3af-45b4-bf49-ad5b11bc3bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269083817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2269083817
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.4174950807
Short name T413
Test name
Test status
Simulation time 103306457233 ps
CPU time 122.34 seconds
Started Jun 02 01:11:39 PM PDT 24
Finished Jun 02 01:13:42 PM PDT 24
Peak memory 200316 kb
Host smart-f39ea01d-279e-4101-a91c-375fe023df13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174950807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.4174950807
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2044938943
Short name T1176
Test name
Test status
Simulation time 13194422 ps
CPU time 0.59 seconds
Started Jun 02 01:18:02 PM PDT 24
Finished Jun 02 01:18:03 PM PDT 24
Peak memory 195760 kb
Host smart-726f1f4b-8097-4dbf-9a9b-c559700bf3d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044938943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2044938943
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3839264870
Short name T431
Test name
Test status
Simulation time 118124509619 ps
CPU time 38.9 seconds
Started Jun 02 01:17:56 PM PDT 24
Finished Jun 02 01:18:35 PM PDT 24
Peak memory 200404 kb
Host smart-4132cce2-6ed6-4377-92d9-3b7bfe9bacb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839264870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3839264870
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.989000885
Short name T890
Test name
Test status
Simulation time 6230962031 ps
CPU time 11.62 seconds
Started Jun 02 01:17:55 PM PDT 24
Finished Jun 02 01:18:07 PM PDT 24
Peak memory 199800 kb
Host smart-61070db1-5148-4202-936d-3f0d486411f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989000885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.989000885
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.206199027
Short name T718
Test name
Test status
Simulation time 208906161355 ps
CPU time 84.54 seconds
Started Jun 02 01:17:57 PM PDT 24
Finished Jun 02 01:19:21 PM PDT 24
Peak memory 200204 kb
Host smart-6acd5790-e0d4-491e-9a93-9af6a11b0094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206199027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.206199027
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1932897261
Short name T1019
Test name
Test status
Simulation time 30570243381 ps
CPU time 25.91 seconds
Started Jun 02 01:17:55 PM PDT 24
Finished Jun 02 01:18:22 PM PDT 24
Peak memory 200280 kb
Host smart-935c7985-5659-410a-9729-2178e4920cef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932897261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1932897261
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2839029359
Short name T1083
Test name
Test status
Simulation time 64886165863 ps
CPU time 71.96 seconds
Started Jun 02 01:18:01 PM PDT 24
Finished Jun 02 01:19:13 PM PDT 24
Peak memory 200324 kb
Host smart-01ae40d4-149d-4d86-9229-8d87f8d522f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839029359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2839029359
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3873175850
Short name T476
Test name
Test status
Simulation time 11124104679 ps
CPU time 3.7 seconds
Started Jun 02 01:17:55 PM PDT 24
Finished Jun 02 01:17:59 PM PDT 24
Peak memory 198892 kb
Host smart-5aac329b-ccef-4bad-b9d1-7d55239ec97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873175850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3873175850
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1406050812
Short name T429
Test name
Test status
Simulation time 148165321272 ps
CPU time 255.66 seconds
Started Jun 02 01:17:56 PM PDT 24
Finished Jun 02 01:22:12 PM PDT 24
Peak memory 200536 kb
Host smart-2fb562e5-6199-4fc7-ac3f-d55b909dc35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406050812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1406050812
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3220817450
Short name T829
Test name
Test status
Simulation time 20827155286 ps
CPU time 988.64 seconds
Started Jun 02 01:18:02 PM PDT 24
Finished Jun 02 01:34:31 PM PDT 24
Peak memory 200340 kb
Host smart-4d82c610-fba1-4cb2-9444-e1f04040dbd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3220817450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3220817450
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.4237515924
Short name T359
Test name
Test status
Simulation time 1271774971 ps
CPU time 2.76 seconds
Started Jun 02 01:17:56 PM PDT 24
Finished Jun 02 01:17:59 PM PDT 24
Peak memory 197524 kb
Host smart-4749dd61-bee5-4499-8ca8-00aafe3c5480
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4237515924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.4237515924
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3684112126
Short name T1132
Test name
Test status
Simulation time 169563759915 ps
CPU time 279.73 seconds
Started Jun 02 01:17:55 PM PDT 24
Finished Jun 02 01:22:35 PM PDT 24
Peak memory 200220 kb
Host smart-676b1700-9520-4440-a698-d1e94f698415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684112126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3684112126
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3443758626
Short name T1066
Test name
Test status
Simulation time 2160187724 ps
CPU time 2.55 seconds
Started Jun 02 01:17:56 PM PDT 24
Finished Jun 02 01:17:59 PM PDT 24
Peak memory 195724 kb
Host smart-26441364-f954-42d5-8d62-8806b1f8f5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443758626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3443758626
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2524357538
Short name T1023
Test name
Test status
Simulation time 480146414 ps
CPU time 1.24 seconds
Started Jun 02 01:17:55 PM PDT 24
Finished Jun 02 01:17:56 PM PDT 24
Peak memory 198892 kb
Host smart-22852619-572e-43c8-9e66-bcd89e6bae9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524357538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2524357538
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3498529377
Short name T966
Test name
Test status
Simulation time 299762041842 ps
CPU time 638.96 seconds
Started Jun 02 01:18:01 PM PDT 24
Finished Jun 02 01:28:40 PM PDT 24
Peak memory 200400 kb
Host smart-29222d3c-66b6-4255-b0fd-d4784e023128
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498529377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3498529377
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1002978716
Short name T850
Test name
Test status
Simulation time 62144301390 ps
CPU time 264.38 seconds
Started Jun 02 01:18:02 PM PDT 24
Finished Jun 02 01:22:27 PM PDT 24
Peak memory 214540 kb
Host smart-0a9f9d80-0309-4f55-8139-ba990044b34c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002978716 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1002978716
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2039141577
Short name T631
Test name
Test status
Simulation time 6147993337 ps
CPU time 13.76 seconds
Started Jun 02 01:17:58 PM PDT 24
Finished Jun 02 01:18:12 PM PDT 24
Peak memory 199812 kb
Host smart-41cc15f8-df4c-49cc-8684-aefe45528eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039141577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2039141577
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.298263167
Short name T696
Test name
Test status
Simulation time 104457033888 ps
CPU time 207.08 seconds
Started Jun 02 01:17:57 PM PDT 24
Finished Jun 02 01:21:24 PM PDT 24
Peak memory 200292 kb
Host smart-b3da8bf3-6249-4335-90bd-51c7c1c19017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298263167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.298263167
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2129620559
Short name T475
Test name
Test status
Simulation time 14595021 ps
CPU time 0.57 seconds
Started Jun 02 01:18:13 PM PDT 24
Finished Jun 02 01:18:14 PM PDT 24
Peak memory 195236 kb
Host smart-ce49a19a-3f2b-4978-bac1-96833106ac92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129620559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2129620559
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3311465307
Short name T459
Test name
Test status
Simulation time 6353943670 ps
CPU time 3.58 seconds
Started Jun 02 01:18:01 PM PDT 24
Finished Jun 02 01:18:05 PM PDT 24
Peak memory 199908 kb
Host smart-1ef5b421-708f-4989-b23e-561731da6061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311465307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3311465307
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.4010673589
Short name T465
Test name
Test status
Simulation time 24914094455 ps
CPU time 50.13 seconds
Started Jun 02 01:18:02 PM PDT 24
Finished Jun 02 01:18:53 PM PDT 24
Peak memory 200332 kb
Host smart-9c163162-b7da-4ad4-8932-256d245fdb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010673589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.4010673589
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.543831937
Short name T192
Test name
Test status
Simulation time 105656169654 ps
CPU time 50.2 seconds
Started Jun 02 01:18:08 PM PDT 24
Finished Jun 02 01:18:59 PM PDT 24
Peak memory 200376 kb
Host smart-01182376-b9d2-44c2-8a2e-3c38cf84015c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543831937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.543831937
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2509548632
Short name T647
Test name
Test status
Simulation time 43061060555 ps
CPU time 22.63 seconds
Started Jun 02 01:18:07 PM PDT 24
Finished Jun 02 01:18:30 PM PDT 24
Peak memory 200432 kb
Host smart-2ee31a30-2073-4e04-91ab-1ebd255db3a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509548632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2509548632
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.923033107
Short name T981
Test name
Test status
Simulation time 37211971508 ps
CPU time 134.31 seconds
Started Jun 02 01:18:13 PM PDT 24
Finished Jun 02 01:20:28 PM PDT 24
Peak memory 200560 kb
Host smart-367c14d7-3286-44aa-a114-259bcc12a027
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=923033107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.923033107
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.436027607
Short name T703
Test name
Test status
Simulation time 7598519076 ps
CPU time 16.52 seconds
Started Jun 02 01:18:16 PM PDT 24
Finished Jun 02 01:18:33 PM PDT 24
Peak memory 198840 kb
Host smart-78ffc3d3-b006-4c83-8cab-a008df8e6d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436027607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.436027607
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.698658685
Short name T289
Test name
Test status
Simulation time 50120526809 ps
CPU time 37.68 seconds
Started Jun 02 01:18:09 PM PDT 24
Finished Jun 02 01:18:47 PM PDT 24
Peak memory 198984 kb
Host smart-31db35b0-6f4e-4062-9908-1e427351d3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698658685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.698658685
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3842122821
Short name T1078
Test name
Test status
Simulation time 9335715711 ps
CPU time 484.88 seconds
Started Jun 02 01:18:14 PM PDT 24
Finished Jun 02 01:26:19 PM PDT 24
Peak memory 200416 kb
Host smart-e66f8101-4cb8-4e21-b836-1f7f1bbb4e8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3842122821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3842122821
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3490607705
Short name T458
Test name
Test status
Simulation time 4568551355 ps
CPU time 2.99 seconds
Started Jun 02 01:18:06 PM PDT 24
Finished Jun 02 01:18:09 PM PDT 24
Peak memory 198540 kb
Host smart-391898b5-22c9-4870-ab65-da8f5565c5b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3490607705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3490607705
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3433002344
Short name T99
Test name
Test status
Simulation time 112075359750 ps
CPU time 76.2 seconds
Started Jun 02 01:18:07 PM PDT 24
Finished Jun 02 01:19:24 PM PDT 24
Peak memory 200336 kb
Host smart-c84c3524-f8dc-4ca0-af46-02e9b988c0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433002344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3433002344
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1363640834
Short name T294
Test name
Test status
Simulation time 2915625300 ps
CPU time 1.8 seconds
Started Jun 02 01:18:08 PM PDT 24
Finished Jun 02 01:18:10 PM PDT 24
Peak memory 196012 kb
Host smart-02f9cb28-2d85-4820-a7f0-25b25a923145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363640834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1363640834
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2777032265
Short name T940
Test name
Test status
Simulation time 113970228 ps
CPU time 0.87 seconds
Started Jun 02 01:18:03 PM PDT 24
Finished Jun 02 01:18:04 PM PDT 24
Peak memory 198456 kb
Host smart-89bc1086-e4bf-45e0-a96f-304f9cd92495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777032265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2777032265
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3830079649
Short name T460
Test name
Test status
Simulation time 86069745502 ps
CPU time 73.61 seconds
Started Jun 02 01:18:14 PM PDT 24
Finished Jun 02 01:19:28 PM PDT 24
Peak memory 200408 kb
Host smart-d0f3583a-114b-45ce-9bf7-422d9be5f4e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830079649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3830079649
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2928300068
Short name T409
Test name
Test status
Simulation time 49150505723 ps
CPU time 644.32 seconds
Started Jun 02 01:18:15 PM PDT 24
Finished Jun 02 01:29:00 PM PDT 24
Peak memory 216880 kb
Host smart-59b6c438-2036-4c2f-90f4-cd443ff56876
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928300068 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2928300068
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1558133188
Short name T527
Test name
Test status
Simulation time 6683899985 ps
CPU time 24.35 seconds
Started Jun 02 01:18:07 PM PDT 24
Finished Jun 02 01:18:31 PM PDT 24
Peak memory 199708 kb
Host smart-0f3a9a8c-4176-45df-8cb6-9cccb9a95b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558133188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1558133188
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.223170624
Short name T307
Test name
Test status
Simulation time 98154361074 ps
CPU time 159.12 seconds
Started Jun 02 01:18:00 PM PDT 24
Finished Jun 02 01:20:40 PM PDT 24
Peak memory 200336 kb
Host smart-aee87da4-65d2-40a9-8aa5-000066a4847a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223170624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.223170624
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2820854501
Short name T968
Test name
Test status
Simulation time 106888864 ps
CPU time 0.55 seconds
Started Jun 02 01:18:28 PM PDT 24
Finished Jun 02 01:18:29 PM PDT 24
Peak memory 195736 kb
Host smart-c42c5e3d-511d-4be0-a398-6577b59ff48e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820854501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2820854501
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2812103311
Short name T909
Test name
Test status
Simulation time 89663916658 ps
CPU time 33.17 seconds
Started Jun 02 01:18:19 PM PDT 24
Finished Jun 02 01:18:52 PM PDT 24
Peak memory 200384 kb
Host smart-21519ce2-a7e7-422c-b6fa-ecce0cdc9164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812103311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2812103311
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3746852700
Short name T1079
Test name
Test status
Simulation time 33050263247 ps
CPU time 15.36 seconds
Started Jun 02 01:18:21 PM PDT 24
Finished Jun 02 01:18:36 PM PDT 24
Peak memory 199368 kb
Host smart-852681b0-cec1-4579-bf6b-68c8645ccb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746852700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3746852700
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3580699673
Short name T1173
Test name
Test status
Simulation time 28780185955 ps
CPU time 23.27 seconds
Started Jun 02 01:18:20 PM PDT 24
Finished Jun 02 01:18:43 PM PDT 24
Peak memory 200084 kb
Host smart-fd14caeb-b645-4e2e-a047-93b3c08de891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580699673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3580699673
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1255991848
Short name T529
Test name
Test status
Simulation time 6440847602 ps
CPU time 3.49 seconds
Started Jun 02 01:18:20 PM PDT 24
Finished Jun 02 01:18:24 PM PDT 24
Peak memory 199524 kb
Host smart-0bbb1162-160a-4f66-bf8f-550a5c441ffe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255991848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1255991848
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3852877507
Short name T724
Test name
Test status
Simulation time 223899736894 ps
CPU time 208.49 seconds
Started Jun 02 01:18:20 PM PDT 24
Finished Jun 02 01:21:48 PM PDT 24
Peak memory 200396 kb
Host smart-e1969c5b-b2a9-4087-8a71-eedb1fff5d98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852877507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3852877507
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.4116070129
Short name T752
Test name
Test status
Simulation time 6640436567 ps
CPU time 7.13 seconds
Started Jun 02 01:18:22 PM PDT 24
Finished Jun 02 01:18:29 PM PDT 24
Peak memory 200248 kb
Host smart-d39f43be-449a-41fe-8b54-44776719aeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116070129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.4116070129
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1308677723
Short name T1076
Test name
Test status
Simulation time 122153620882 ps
CPU time 324.83 seconds
Started Jun 02 01:18:21 PM PDT 24
Finished Jun 02 01:23:46 PM PDT 24
Peak memory 200680 kb
Host smart-5cb68869-cf79-443f-8fb4-cd6ac2a23445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308677723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1308677723
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2883293387
Short name T834
Test name
Test status
Simulation time 18812623233 ps
CPU time 541.22 seconds
Started Jun 02 01:18:21 PM PDT 24
Finished Jun 02 01:27:23 PM PDT 24
Peak memory 200320 kb
Host smart-26d6b3c7-6fe1-4b65-ae09-5f84bf8d673f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2883293387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2883293387
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3080736188
Short name T1159
Test name
Test status
Simulation time 2851308440 ps
CPU time 22.92 seconds
Started Jun 02 01:18:21 PM PDT 24
Finished Jun 02 01:18:44 PM PDT 24
Peak memory 198960 kb
Host smart-f594f281-c97a-4740-93cc-8abeab80a325
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080736188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3080736188
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1884500176
Short name T598
Test name
Test status
Simulation time 11429657452 ps
CPU time 5.9 seconds
Started Jun 02 01:18:22 PM PDT 24
Finished Jun 02 01:18:28 PM PDT 24
Peak memory 199956 kb
Host smart-be29df3c-de18-47d7-b425-6b3122cca2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884500176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1884500176
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1037526138
Short name T614
Test name
Test status
Simulation time 4335822880 ps
CPU time 6.81 seconds
Started Jun 02 01:18:21 PM PDT 24
Finished Jun 02 01:18:29 PM PDT 24
Peak memory 196360 kb
Host smart-521fdb6c-4f49-46a2-a8dd-4fade0df7eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037526138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1037526138
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1685909584
Short name T463
Test name
Test status
Simulation time 5762828238 ps
CPU time 18.18 seconds
Started Jun 02 01:18:14 PM PDT 24
Finished Jun 02 01:18:33 PM PDT 24
Peak memory 200336 kb
Host smart-f2cf2f4c-1120-42cc-a594-af03fced0151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685909584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1685909584
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2671230613
Short name T713
Test name
Test status
Simulation time 129108435600 ps
CPU time 223.55 seconds
Started Jun 02 01:18:28 PM PDT 24
Finished Jun 02 01:22:12 PM PDT 24
Peak memory 200404 kb
Host smart-a6bcac92-7fe8-47e2-bd1b-091e136a19d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671230613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2671230613
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2940674127
Short name T663
Test name
Test status
Simulation time 64225476713 ps
CPU time 1180.09 seconds
Started Jun 02 01:18:21 PM PDT 24
Finished Jun 02 01:38:02 PM PDT 24
Peak memory 216900 kb
Host smart-c62e3142-a440-44bc-a327-55fcec676927
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940674127 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2940674127
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3621154155
Short name T684
Test name
Test status
Simulation time 6642071814 ps
CPU time 25.98 seconds
Started Jun 02 01:18:21 PM PDT 24
Finished Jun 02 01:18:47 PM PDT 24
Peak memory 200156 kb
Host smart-a0962b53-cfc0-457d-a4ff-c62861428b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621154155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3621154155
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.631799160
Short name T252
Test name
Test status
Simulation time 17036670287 ps
CPU time 17.06 seconds
Started Jun 02 01:18:14 PM PDT 24
Finished Jun 02 01:18:32 PM PDT 24
Peak memory 200308 kb
Host smart-3d3a9201-1be3-491e-afac-a7b833dd0ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631799160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.631799160
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1103592367
Short name T25
Test name
Test status
Simulation time 22743778 ps
CPU time 0.57 seconds
Started Jun 02 01:18:34 PM PDT 24
Finished Jun 02 01:18:35 PM PDT 24
Peak memory 195768 kb
Host smart-7d672505-1d76-43ae-a2b0-cf467044b91f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103592367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1103592367
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2812379769
Short name T168
Test name
Test status
Simulation time 52988357851 ps
CPU time 14.19 seconds
Started Jun 02 01:18:29 PM PDT 24
Finished Jun 02 01:18:44 PM PDT 24
Peak memory 200432 kb
Host smart-6aab3d6c-908c-4711-b809-fa6300bb1ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812379769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2812379769
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.180244290
Short name T524
Test name
Test status
Simulation time 25757232842 ps
CPU time 42.9 seconds
Started Jun 02 01:18:30 PM PDT 24
Finished Jun 02 01:19:13 PM PDT 24
Peak memory 200256 kb
Host smart-8450a954-9c4b-49e4-9740-34e0f336f78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180244290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.180244290
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3956112819
Short name T912
Test name
Test status
Simulation time 25526448009 ps
CPU time 36.71 seconds
Started Jun 02 01:18:27 PM PDT 24
Finished Jun 02 01:19:04 PM PDT 24
Peak memory 200320 kb
Host smart-15ffeceb-9bca-4380-8939-869bd01327e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956112819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3956112819
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2025993320
Short name T473
Test name
Test status
Simulation time 33018784181 ps
CPU time 32.56 seconds
Started Jun 02 01:18:27 PM PDT 24
Finished Jun 02 01:19:00 PM PDT 24
Peak memory 200356 kb
Host smart-625a1d6e-505e-4f15-a302-df03590b83fe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025993320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2025993320
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.161515384
Short name T256
Test name
Test status
Simulation time 94390653918 ps
CPU time 795.35 seconds
Started Jun 02 01:18:27 PM PDT 24
Finished Jun 02 01:31:43 PM PDT 24
Peak memory 200332 kb
Host smart-312a4241-0cdf-4ee8-8ff1-e36032f6edb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=161515384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.161515384
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3071544492
Short name T450
Test name
Test status
Simulation time 4042898327 ps
CPU time 7.98 seconds
Started Jun 02 01:18:31 PM PDT 24
Finished Jun 02 01:18:39 PM PDT 24
Peak memory 198028 kb
Host smart-3000175e-5b62-45ef-a4fc-5c7894a2fba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071544492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3071544492
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3436883863
Short name T758
Test name
Test status
Simulation time 50271997397 ps
CPU time 43.16 seconds
Started Jun 02 01:18:28 PM PDT 24
Finished Jun 02 01:19:12 PM PDT 24
Peak memory 200524 kb
Host smart-125ef53c-4358-4c4c-a53c-e6e5735e33ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436883863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3436883863
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2886998689
Short name T836
Test name
Test status
Simulation time 19846816914 ps
CPU time 218.55 seconds
Started Jun 02 01:18:26 PM PDT 24
Finished Jun 02 01:22:05 PM PDT 24
Peak memory 200320 kb
Host smart-46f8ce75-b0de-4f06-bba5-33a116dc58b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886998689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2886998689
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2253099591
Short name T970
Test name
Test status
Simulation time 2630376965 ps
CPU time 16.37 seconds
Started Jun 02 01:18:26 PM PDT 24
Finished Jun 02 01:18:43 PM PDT 24
Peak memory 199248 kb
Host smart-4c5f981f-5d87-4d40-b9aa-f5d0e002ec25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2253099591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2253099591
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3924706767
Short name T175
Test name
Test status
Simulation time 109809567139 ps
CPU time 26.04 seconds
Started Jun 02 01:18:28 PM PDT 24
Finished Jun 02 01:18:54 PM PDT 24
Peak memory 200396 kb
Host smart-4890c081-af5d-47d1-902d-c45ee03a8f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924706767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3924706767
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3710976417
Short name T955
Test name
Test status
Simulation time 44913993468 ps
CPU time 39.42 seconds
Started Jun 02 01:18:27 PM PDT 24
Finished Jun 02 01:19:06 PM PDT 24
Peak memory 196088 kb
Host smart-e1476379-f839-452a-b3d1-0edfc70a2662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710976417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3710976417
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3877393350
Short name T505
Test name
Test status
Simulation time 570361201 ps
CPU time 1.29 seconds
Started Jun 02 01:18:30 PM PDT 24
Finished Jun 02 01:18:32 PM PDT 24
Peak memory 199760 kb
Host smart-ca4aff96-ee1f-40bc-a5d5-57db450df4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877393350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3877393350
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.152478709
Short name T855
Test name
Test status
Simulation time 42848542802 ps
CPU time 141.51 seconds
Started Jun 02 01:18:27 PM PDT 24
Finished Jun 02 01:20:49 PM PDT 24
Peak memory 200360 kb
Host smart-4844437b-e075-4375-8859-8a7ccd0c1e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152478709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.152478709
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2872399327
Short name T998
Test name
Test status
Simulation time 2069656833 ps
CPU time 1.72 seconds
Started Jun 02 01:18:27 PM PDT 24
Finished Jun 02 01:18:29 PM PDT 24
Peak memory 198776 kb
Host smart-699207b1-7537-494e-8e6f-b42b9f8bbe35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872399327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2872399327
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1216849903
Short name T734
Test name
Test status
Simulation time 57837015903 ps
CPU time 112.5 seconds
Started Jun 02 01:18:27 PM PDT 24
Finished Jun 02 01:20:19 PM PDT 24
Peak memory 200400 kb
Host smart-014ef3fe-7a94-4c79-993f-92f1e93dfde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216849903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1216849903
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1664515631
Short name T898
Test name
Test status
Simulation time 14998121 ps
CPU time 0.55 seconds
Started Jun 02 01:18:42 PM PDT 24
Finished Jun 02 01:18:43 PM PDT 24
Peak memory 195692 kb
Host smart-8bb2bd4a-f793-45d1-aaad-a6d7d17c7c50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664515631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1664515631
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1592096792
Short name T161
Test name
Test status
Simulation time 115956361495 ps
CPU time 31.06 seconds
Started Jun 02 01:18:36 PM PDT 24
Finished Jun 02 01:19:07 PM PDT 24
Peak memory 200392 kb
Host smart-7b1a725b-db04-4730-ba75-73d9afc1e5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592096792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1592096792
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3209637961
Short name T1162
Test name
Test status
Simulation time 67468665970 ps
CPU time 29.63 seconds
Started Jun 02 01:18:35 PM PDT 24
Finished Jun 02 01:19:05 PM PDT 24
Peak memory 200244 kb
Host smart-3f4c144e-4494-43fd-bbb1-09ad9764f5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209637961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3209637961
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1750982771
Short name T365
Test name
Test status
Simulation time 276496785522 ps
CPU time 25.29 seconds
Started Jun 02 01:18:34 PM PDT 24
Finished Jun 02 01:19:00 PM PDT 24
Peak memory 200112 kb
Host smart-a000a93e-0a22-4dbd-a501-366b01716c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750982771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1750982771
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.4248678072
Short name T511
Test name
Test status
Simulation time 56702514386 ps
CPU time 23.11 seconds
Started Jun 02 01:18:34 PM PDT 24
Finished Jun 02 01:18:58 PM PDT 24
Peak memory 200268 kb
Host smart-f3ad9d4e-478a-4c3c-8fb4-17a465295d9d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248678072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.4248678072
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.909212047
Short name T580
Test name
Test status
Simulation time 157402721525 ps
CPU time 1406.85 seconds
Started Jun 02 01:18:43 PM PDT 24
Finished Jun 02 01:42:10 PM PDT 24
Peak memory 200396 kb
Host smart-1816fe66-6255-4337-9739-3a6a7b8e9e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=909212047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.909212047
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2272286099
Short name T700
Test name
Test status
Simulation time 9330529178 ps
CPU time 11.28 seconds
Started Jun 02 01:18:34 PM PDT 24
Finished Jun 02 01:18:46 PM PDT 24
Peak memory 199224 kb
Host smart-b42993d0-1382-45c7-ac59-4188bc50e65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272286099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2272286099
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.340084281
Short name T1090
Test name
Test status
Simulation time 348703801848 ps
CPU time 64.57 seconds
Started Jun 02 01:18:34 PM PDT 24
Finished Jun 02 01:19:39 PM PDT 24
Peak memory 216228 kb
Host smart-019dc789-882a-4603-8426-a885efec722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340084281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.340084281
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2730335596
Short name T265
Test name
Test status
Simulation time 21739799611 ps
CPU time 550.86 seconds
Started Jun 02 01:18:43 PM PDT 24
Finished Jun 02 01:27:54 PM PDT 24
Peak memory 200372 kb
Host smart-bd554d94-c29e-41d6-a8b1-b8789e105975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2730335596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2730335596
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.607287062
Short name T760
Test name
Test status
Simulation time 1602425955 ps
CPU time 3.21 seconds
Started Jun 02 01:18:34 PM PDT 24
Finished Jun 02 01:18:38 PM PDT 24
Peak memory 198356 kb
Host smart-44c78f1e-b6b3-4ed5-992a-c0d240b58deb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607287062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.607287062
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1333121305
Short name T791
Test name
Test status
Simulation time 15932761157 ps
CPU time 29.89 seconds
Started Jun 02 01:18:37 PM PDT 24
Finished Jun 02 01:19:08 PM PDT 24
Peak memory 200336 kb
Host smart-9bf4e772-ee0e-46c5-9387-e9d47b72a89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333121305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1333121305
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1725731413
Short name T392
Test name
Test status
Simulation time 2678287140 ps
CPU time 1.73 seconds
Started Jun 02 01:18:35 PM PDT 24
Finished Jun 02 01:18:37 PM PDT 24
Peak memory 196836 kb
Host smart-90ec7dfe-ba5f-4adc-a8ff-84518c5c45a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725731413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1725731413
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2870807058
Short name T572
Test name
Test status
Simulation time 468372503 ps
CPU time 2.24 seconds
Started Jun 02 01:18:34 PM PDT 24
Finished Jun 02 01:18:37 PM PDT 24
Peak memory 199188 kb
Host smart-e812ba70-7d2d-490a-9f32-e5de194d8ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870807058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2870807058
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3388354966
Short name T1032
Test name
Test status
Simulation time 28174115682 ps
CPU time 50.28 seconds
Started Jun 02 01:18:40 PM PDT 24
Finished Jun 02 01:19:31 PM PDT 24
Peak memory 200304 kb
Host smart-1d7d4f93-c88f-45e9-81f2-0e5ed5bbff7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388354966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3388354966
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3626788834
Short name T91
Test name
Test status
Simulation time 374663091417 ps
CPU time 554.04 seconds
Started Jun 02 01:18:42 PM PDT 24
Finished Jun 02 01:27:56 PM PDT 24
Peak memory 227400 kb
Host smart-358b89a4-d634-41ce-8be6-66f844089a5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626788834 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3626788834
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3025290033
Short name T313
Test name
Test status
Simulation time 6335423535 ps
CPU time 19.78 seconds
Started Jun 02 01:18:35 PM PDT 24
Finished Jun 02 01:18:55 PM PDT 24
Peak memory 200260 kb
Host smart-7afa1761-dea8-46c1-b692-4c43310fbf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025290033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3025290033
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2702786828
Short name T517
Test name
Test status
Simulation time 143118129334 ps
CPU time 69.72 seconds
Started Jun 02 01:18:33 PM PDT 24
Finished Jun 02 01:19:44 PM PDT 24
Peak memory 200344 kb
Host smart-9e97a957-2270-4669-95b1-1777b9118b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702786828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2702786828
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1855969609
Short name T975
Test name
Test status
Simulation time 18828666 ps
CPU time 0.54 seconds
Started Jun 02 01:18:49 PM PDT 24
Finished Jun 02 01:18:50 PM PDT 24
Peak memory 194764 kb
Host smart-446cae6e-5d7a-4ad2-ab63-f615bbf5c4e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855969609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1855969609
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2453312541
Short name T1006
Test name
Test status
Simulation time 36093136255 ps
CPU time 62.16 seconds
Started Jun 02 01:18:43 PM PDT 24
Finished Jun 02 01:19:46 PM PDT 24
Peak memory 200392 kb
Host smart-33e1593e-db6a-4415-a077-5cef9a13b1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453312541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2453312541
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.326105587
Short name T730
Test name
Test status
Simulation time 10110340345 ps
CPU time 7.11 seconds
Started Jun 02 01:18:42 PM PDT 24
Finished Jun 02 01:18:49 PM PDT 24
Peak memory 200220 kb
Host smart-a0db03d3-d51d-4815-bfbc-f3808c7252c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326105587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.326105587
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3319253387
Short name T553
Test name
Test status
Simulation time 158856397653 ps
CPU time 71.64 seconds
Started Jun 02 01:18:42 PM PDT 24
Finished Jun 02 01:19:54 PM PDT 24
Peak memory 200292 kb
Host smart-464c4044-3acc-4d29-b174-e199ca8026d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319253387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3319253387
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.998979700
Short name T674
Test name
Test status
Simulation time 22617125817 ps
CPU time 43.57 seconds
Started Jun 02 01:18:47 PM PDT 24
Finished Jun 02 01:19:31 PM PDT 24
Peak memory 200164 kb
Host smart-8f2991eb-6066-4ae7-82a6-48e7418c0853
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998979700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.998979700
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1498026962
Short name T415
Test name
Test status
Simulation time 118958481398 ps
CPU time 882.97 seconds
Started Jun 02 01:18:49 PM PDT 24
Finished Jun 02 01:33:32 PM PDT 24
Peak memory 200392 kb
Host smart-a5f30eff-fa10-407c-8c62-cf16bf848b67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1498026962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1498026962
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3169069301
Short name T342
Test name
Test status
Simulation time 7277760624 ps
CPU time 1.55 seconds
Started Jun 02 01:18:48 PM PDT 24
Finished Jun 02 01:18:50 PM PDT 24
Peak memory 197896 kb
Host smart-85e08289-f4f8-4bb9-a84c-f565780f58ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169069301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3169069301
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.4176544415
Short name T1038
Test name
Test status
Simulation time 327590255606 ps
CPU time 70.87 seconds
Started Jun 02 01:18:47 PM PDT 24
Finished Jun 02 01:19:59 PM PDT 24
Peak memory 208776 kb
Host smart-99e2ab95-4b19-413b-acf3-40113b313731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176544415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.4176544415
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2604018621
Short name T1071
Test name
Test status
Simulation time 16618882057 ps
CPU time 728.59 seconds
Started Jun 02 01:18:47 PM PDT 24
Finished Jun 02 01:30:56 PM PDT 24
Peak memory 200396 kb
Host smart-d9c18b84-5836-4849-a807-97f754087101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2604018621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2604018621
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1059839903
Short name T419
Test name
Test status
Simulation time 4342855843 ps
CPU time 41.43 seconds
Started Jun 02 01:18:40 PM PDT 24
Finished Jun 02 01:19:22 PM PDT 24
Peak memory 198160 kb
Host smart-955c92b7-1f07-4402-93f1-68b1382b89d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1059839903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1059839903
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3800261388
Short name T639
Test name
Test status
Simulation time 59290178463 ps
CPU time 31.28 seconds
Started Jun 02 01:18:48 PM PDT 24
Finished Jun 02 01:19:20 PM PDT 24
Peak memory 200368 kb
Host smart-8c7a4182-2cd9-4ff8-bab2-a82a877f3b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800261388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3800261388
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.4066539376
Short name T1082
Test name
Test status
Simulation time 41190960159 ps
CPU time 17.72 seconds
Started Jun 02 01:18:46 PM PDT 24
Finished Jun 02 01:19:04 PM PDT 24
Peak memory 196072 kb
Host smart-b1c3b614-5de7-4f10-be2e-cfe4117fe5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066539376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.4066539376
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2333736616
Short name T926
Test name
Test status
Simulation time 673585607 ps
CPU time 1.41 seconds
Started Jun 02 01:18:41 PM PDT 24
Finished Jun 02 01:18:43 PM PDT 24
Peak memory 199660 kb
Host smart-4a1a05aa-2976-4a30-bc4d-21a9471ea0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333736616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2333736616
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2162186131
Short name T273
Test name
Test status
Simulation time 463286906824 ps
CPU time 181.52 seconds
Started Jun 02 01:18:48 PM PDT 24
Finished Jun 02 01:21:50 PM PDT 24
Peak memory 208872 kb
Host smart-2844537a-fc68-4fa6-9323-a3c39eda2755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162186131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2162186131
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.90084468
Short name T49
Test name
Test status
Simulation time 76327804428 ps
CPU time 574.14 seconds
Started Jun 02 01:18:49 PM PDT 24
Finished Jun 02 01:28:23 PM PDT 24
Peak memory 216660 kb
Host smart-0f56d237-7c45-4ad5-8d8c-a7cff1a85b9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90084468 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.90084468
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2630726820
Short name T412
Test name
Test status
Simulation time 12363157067 ps
CPU time 37.97 seconds
Started Jun 02 01:18:48 PM PDT 24
Finished Jun 02 01:19:27 PM PDT 24
Peak memory 200256 kb
Host smart-bb466996-7c31-4b4a-9ab7-0472b84dd17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630726820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2630726820
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2582718681
Short name T541
Test name
Test status
Simulation time 103901725446 ps
CPU time 203.58 seconds
Started Jun 02 01:18:41 PM PDT 24
Finished Jun 02 01:22:05 PM PDT 24
Peak memory 200296 kb
Host smart-387efc55-c228-4998-9b77-3cee1b97f5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582718681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2582718681
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.4007984328
Short name T959
Test name
Test status
Simulation time 24342257 ps
CPU time 0.53 seconds
Started Jun 02 01:19:10 PM PDT 24
Finished Jun 02 01:19:11 PM PDT 24
Peak memory 195768 kb
Host smart-3c3702b4-a16b-42a0-98d4-22674b64b28a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007984328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.4007984328
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.134600435
Short name T1024
Test name
Test status
Simulation time 69387976407 ps
CPU time 100.66 seconds
Started Jun 02 01:18:55 PM PDT 24
Finished Jun 02 01:20:36 PM PDT 24
Peak memory 200356 kb
Host smart-5d244bfa-bffa-4561-8c4d-f55116874a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134600435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.134600435
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1639990426
Short name T441
Test name
Test status
Simulation time 18643775592 ps
CPU time 32.02 seconds
Started Jun 02 01:18:56 PM PDT 24
Finished Jun 02 01:19:28 PM PDT 24
Peak memory 200384 kb
Host smart-bb3ac223-82d8-4169-bbaf-df44006f9ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639990426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1639990426
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1044554420
Short name T259
Test name
Test status
Simulation time 58959851898 ps
CPU time 37.51 seconds
Started Jun 02 01:19:05 PM PDT 24
Finished Jun 02 01:19:43 PM PDT 24
Peak memory 200396 kb
Host smart-fe31924b-f6c2-48a7-b870-c0703fc9dedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044554420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1044554420
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2439258696
Short name T1026
Test name
Test status
Simulation time 20883455343 ps
CPU time 29.53 seconds
Started Jun 02 01:19:02 PM PDT 24
Finished Jun 02 01:19:32 PM PDT 24
Peak memory 197460 kb
Host smart-8e25e930-17d4-498f-a72b-29f4b050889c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439258696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2439258696
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3178774674
Short name T1004
Test name
Test status
Simulation time 30485668399 ps
CPU time 246.22 seconds
Started Jun 02 01:19:07 PM PDT 24
Finished Jun 02 01:23:13 PM PDT 24
Peak memory 200368 kb
Host smart-cd592aba-cfc1-4749-bf35-74e6c51c4001
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3178774674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3178774674
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.881062413
Short name T346
Test name
Test status
Simulation time 6748174232 ps
CPU time 13.69 seconds
Started Jun 02 01:19:06 PM PDT 24
Finished Jun 02 01:19:20 PM PDT 24
Peak memory 198956 kb
Host smart-7fccf16a-8b05-4361-86c1-4535cc921b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881062413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.881062413
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2260103956
Short name T900
Test name
Test status
Simulation time 62204447009 ps
CPU time 54.39 seconds
Started Jun 02 01:19:03 PM PDT 24
Finished Jun 02 01:19:58 PM PDT 24
Peak memory 200472 kb
Host smart-265e024a-8eda-4ee0-b19b-2171388e05b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260103956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2260103956
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2372748598
Short name T1118
Test name
Test status
Simulation time 4928179049 ps
CPU time 143.69 seconds
Started Jun 02 01:19:02 PM PDT 24
Finished Jun 02 01:21:26 PM PDT 24
Peak memory 200396 kb
Host smart-e5a21ace-8f82-4f18-bf10-128a796ad85b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2372748598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2372748598
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3575312426
Short name T344
Test name
Test status
Simulation time 3273916072 ps
CPU time 5.96 seconds
Started Jun 02 01:19:07 PM PDT 24
Finished Jun 02 01:19:13 PM PDT 24
Peak memory 198280 kb
Host smart-712ab509-22ce-4bdd-80da-a6bdcd3a9cf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3575312426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3575312426
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3868114127
Short name T667
Test name
Test status
Simulation time 75500258030 ps
CPU time 36.55 seconds
Started Jun 02 01:19:03 PM PDT 24
Finished Jun 02 01:19:40 PM PDT 24
Peak memory 200244 kb
Host smart-4e9da759-fce1-49bd-ad3a-49672ea92f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868114127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3868114127
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.988810559
Short name T454
Test name
Test status
Simulation time 3924076768 ps
CPU time 7 seconds
Started Jun 02 01:19:07 PM PDT 24
Finished Jun 02 01:19:14 PM PDT 24
Peak memory 196328 kb
Host smart-f0360467-096b-4bf5-8cfc-f72c2ea31165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988810559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.988810559
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.909904561
Short name T1049
Test name
Test status
Simulation time 536343656 ps
CPU time 2.44 seconds
Started Jun 02 01:18:56 PM PDT 24
Finished Jun 02 01:18:59 PM PDT 24
Peak memory 198596 kb
Host smart-5e323ff7-62f9-4216-b208-4c2dfcbef7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909904561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.909904561
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.121596947
Short name T1097
Test name
Test status
Simulation time 67527428312 ps
CPU time 682.8 seconds
Started Jun 02 01:19:10 PM PDT 24
Finished Jun 02 01:30:33 PM PDT 24
Peak memory 216852 kb
Host smart-0480a03c-0b93-48a0-8a5c-5b967017d325
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121596947 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.121596947
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.4091005634
Short name T827
Test name
Test status
Simulation time 835519467 ps
CPU time 2.66 seconds
Started Jun 02 01:19:02 PM PDT 24
Finished Jun 02 01:19:05 PM PDT 24
Peak memory 198628 kb
Host smart-9863fef4-25df-4375-b6f5-23063dcc79d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091005634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.4091005634
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1741199752
Short name T536
Test name
Test status
Simulation time 50187912056 ps
CPU time 35.27 seconds
Started Jun 02 01:18:56 PM PDT 24
Finished Jun 02 01:19:32 PM PDT 24
Peak memory 200348 kb
Host smart-b04727c1-4f14-4c56-98b8-b75138b00369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741199752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1741199752
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.750758699
Short name T702
Test name
Test status
Simulation time 13242221 ps
CPU time 0.55 seconds
Started Jun 02 01:19:16 PM PDT 24
Finished Jun 02 01:19:17 PM PDT 24
Peak memory 194748 kb
Host smart-0ebe15a3-5433-43aa-bbba-16df8b0e5952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750758699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.750758699
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3163868107
Short name T3
Test name
Test status
Simulation time 95822535490 ps
CPU time 44.22 seconds
Started Jun 02 01:19:10 PM PDT 24
Finished Jun 02 01:19:55 PM PDT 24
Peak memory 200316 kb
Host smart-76ae6f43-108c-4a33-a664-3c29b32b5cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163868107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3163868107
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2244135687
Short name T1010
Test name
Test status
Simulation time 31641758660 ps
CPU time 52.16 seconds
Started Jun 02 01:19:10 PM PDT 24
Finished Jun 02 01:20:02 PM PDT 24
Peak memory 200368 kb
Host smart-b418198a-bc5f-4c35-a8cb-f7d1f19ad200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244135687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2244135687
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.4225167711
Short name T846
Test name
Test status
Simulation time 187977004525 ps
CPU time 40.07 seconds
Started Jun 02 01:19:11 PM PDT 24
Finished Jun 02 01:19:51 PM PDT 24
Peak memory 200316 kb
Host smart-a0c0107a-bec7-4193-b085-f3aaa75251e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225167711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.4225167711
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2485094978
Short name T513
Test name
Test status
Simulation time 31403598898 ps
CPU time 26.96 seconds
Started Jun 02 01:19:08 PM PDT 24
Finished Jun 02 01:19:35 PM PDT 24
Peak memory 200436 kb
Host smart-62b96ce9-4563-4ad7-8434-61bd6523d7df
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485094978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2485094978
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2904564214
Short name T1062
Test name
Test status
Simulation time 129442023563 ps
CPU time 1349.59 seconds
Started Jun 02 01:19:17 PM PDT 24
Finished Jun 02 01:41:47 PM PDT 24
Peak memory 200404 kb
Host smart-4543a504-1d66-47f2-9a22-17cb5fda4e76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2904564214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2904564214
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1913486766
Short name T495
Test name
Test status
Simulation time 1908023695 ps
CPU time 4.19 seconds
Started Jun 02 01:19:13 PM PDT 24
Finished Jun 02 01:19:18 PM PDT 24
Peak memory 198408 kb
Host smart-ce7fc140-8766-4034-9f13-eb81c6ce0f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913486766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1913486766
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.56297100
Short name T533
Test name
Test status
Simulation time 91805468559 ps
CPU time 52.35 seconds
Started Jun 02 01:19:08 PM PDT 24
Finished Jun 02 01:20:01 PM PDT 24
Peak memory 200604 kb
Host smart-d5ee3b9a-509f-4c98-8d3b-7bab4ed460d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56297100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.56297100
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.347556685
Short name T472
Test name
Test status
Simulation time 15689979428 ps
CPU time 215.68 seconds
Started Jun 02 01:19:10 PM PDT 24
Finished Jun 02 01:22:46 PM PDT 24
Peak memory 200348 kb
Host smart-757a7bbc-adcd-4048-97c7-49075b163acb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=347556685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.347556685
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.583624502
Short name T550
Test name
Test status
Simulation time 4119869638 ps
CPU time 4.9 seconds
Started Jun 02 01:19:09 PM PDT 24
Finished Jun 02 01:19:14 PM PDT 24
Peak memory 199304 kb
Host smart-6e35aa03-a4e2-49b1-ac05-2d63de30c7fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=583624502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.583624502
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1390070957
Short name T880
Test name
Test status
Simulation time 34812247368 ps
CPU time 68.51 seconds
Started Jun 02 01:19:09 PM PDT 24
Finished Jun 02 01:20:18 PM PDT 24
Peak memory 200356 kb
Host smart-a3fbd12f-129d-4361-963b-130cb67c6efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390070957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1390070957
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.854222631
Short name T323
Test name
Test status
Simulation time 41775594627 ps
CPU time 33.59 seconds
Started Jun 02 01:19:09 PM PDT 24
Finished Jun 02 01:19:43 PM PDT 24
Peak memory 196148 kb
Host smart-8d517eb6-5ae5-49cd-8c60-574a5ef591d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854222631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.854222631
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.963817574
Short name T379
Test name
Test status
Simulation time 5373616396 ps
CPU time 13.15 seconds
Started Jun 02 01:19:11 PM PDT 24
Finished Jun 02 01:19:24 PM PDT 24
Peak memory 200332 kb
Host smart-f2cbeffe-8c74-4802-9730-ea1cd488f399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963817574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.963817574
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3780921813
Short name T207
Test name
Test status
Simulation time 28682695425 ps
CPU time 37.59 seconds
Started Jun 02 01:19:15 PM PDT 24
Finished Jun 02 01:19:53 PM PDT 24
Peak memory 200456 kb
Host smart-1fc0d3a6-e8f4-4a5e-9051-ab32cc030be9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780921813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3780921813
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1554496058
Short name T626
Test name
Test status
Simulation time 174119884887 ps
CPU time 1409.4 seconds
Started Jun 02 01:19:17 PM PDT 24
Finished Jun 02 01:42:46 PM PDT 24
Peak memory 233432 kb
Host smart-1f13e321-8ec4-4bb7-9e31-6d81d3e54817
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554496058 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1554496058
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.615919118
Short name T701
Test name
Test status
Simulation time 2241337231 ps
CPU time 1.73 seconds
Started Jun 02 01:19:08 PM PDT 24
Finished Jun 02 01:19:10 PM PDT 24
Peak memory 198808 kb
Host smart-62f1f0db-d5aa-489e-b6cd-276ff378c9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615919118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.615919118
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2345441406
Short name T645
Test name
Test status
Simulation time 52853078454 ps
CPU time 22.68 seconds
Started Jun 02 01:19:15 PM PDT 24
Finished Jun 02 01:19:38 PM PDT 24
Peak memory 200276 kb
Host smart-76ef0fb6-f8b0-4582-b0db-3a46eadac9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345441406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2345441406
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2721348262
Short name T357
Test name
Test status
Simulation time 15039134 ps
CPU time 0.58 seconds
Started Jun 02 01:19:23 PM PDT 24
Finished Jun 02 01:19:24 PM PDT 24
Peak memory 195780 kb
Host smart-e231c7c2-cbc8-405b-bb69-b1cfd8da128b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721348262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2721348262
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.4266307906
Short name T140
Test name
Test status
Simulation time 68481041957 ps
CPU time 27.35 seconds
Started Jun 02 01:19:17 PM PDT 24
Finished Jun 02 01:19:44 PM PDT 24
Peak memory 200376 kb
Host smart-15aae660-caad-47c5-895c-513fdb44ba12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266307906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.4266307906
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2368308720
Short name T649
Test name
Test status
Simulation time 20967780060 ps
CPU time 33.75 seconds
Started Jun 02 01:19:26 PM PDT 24
Finished Jun 02 01:20:00 PM PDT 24
Peak memory 200320 kb
Host smart-291943f2-087f-4064-9e68-06a2a2863a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368308720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2368308720
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3281239598
Short name T234
Test name
Test status
Simulation time 176209661339 ps
CPU time 253.34 seconds
Started Jun 02 01:19:15 PM PDT 24
Finished Jun 02 01:23:29 PM PDT 24
Peak memory 200388 kb
Host smart-860e468a-e801-479e-9ce9-969651ecc83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281239598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3281239598
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1035561167
Short name T526
Test name
Test status
Simulation time 9817539180 ps
CPU time 3.34 seconds
Started Jun 02 01:19:22 PM PDT 24
Finished Jun 02 01:19:26 PM PDT 24
Peak memory 199892 kb
Host smart-31084cf8-eee3-4a6d-b2b5-7ce0ef456bfc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035561167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1035561167
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.4003212792
Short name T255
Test name
Test status
Simulation time 79052280856 ps
CPU time 355.61 seconds
Started Jun 02 01:19:23 PM PDT 24
Finished Jun 02 01:25:19 PM PDT 24
Peak memory 200372 kb
Host smart-233234be-8edc-498b-a90b-f0692faaebd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4003212792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.4003212792
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3010745153
Short name T1144
Test name
Test status
Simulation time 945844643 ps
CPU time 0.94 seconds
Started Jun 02 01:19:23 PM PDT 24
Finished Jun 02 01:19:24 PM PDT 24
Peak memory 196020 kb
Host smart-b7d34b62-1d5d-42cf-abf3-51dc8e0992fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010745153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3010745153
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.4082265323
Short name T736
Test name
Test status
Simulation time 34418242651 ps
CPU time 61.86 seconds
Started Jun 02 01:19:22 PM PDT 24
Finished Jun 02 01:20:24 PM PDT 24
Peak memory 198572 kb
Host smart-13497384-572f-4ecc-a778-5b0c7073e31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082265323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.4082265323
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2645907146
Short name T814
Test name
Test status
Simulation time 18545222875 ps
CPU time 428.08 seconds
Started Jun 02 01:19:22 PM PDT 24
Finished Jun 02 01:26:30 PM PDT 24
Peak memory 200392 kb
Host smart-cbb875de-040e-401a-ab11-44ba9b47cb16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2645907146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2645907146
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2966351228
Short name T370
Test name
Test status
Simulation time 7207197459 ps
CPU time 64.47 seconds
Started Jun 02 01:19:16 PM PDT 24
Finished Jun 02 01:20:21 PM PDT 24
Peak memory 199560 kb
Host smart-7fee97a5-ea66-4444-9005-5e11df324be2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966351228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2966351228
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1582403093
Short name T652
Test name
Test status
Simulation time 24442156930 ps
CPU time 20.37 seconds
Started Jun 02 01:19:22 PM PDT 24
Finished Jun 02 01:19:43 PM PDT 24
Peak memory 199664 kb
Host smart-8dfa5055-2e98-4562-ad7d-ad828021b248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582403093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1582403093
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3029427447
Short name T375
Test name
Test status
Simulation time 5167041491 ps
CPU time 2.07 seconds
Started Jun 02 01:19:23 PM PDT 24
Finished Jun 02 01:19:25 PM PDT 24
Peak memory 196340 kb
Host smart-9ec9925c-ea70-4239-97f7-5c470ad4474e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029427447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3029427447
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.591853508
Short name T425
Test name
Test status
Simulation time 693170989 ps
CPU time 2.49 seconds
Started Jun 02 01:19:18 PM PDT 24
Finished Jun 02 01:19:21 PM PDT 24
Peak memory 199672 kb
Host smart-625dfbb2-2b44-488c-b23f-402dfa9d5531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591853508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.591853508
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.486642413
Short name T643
Test name
Test status
Simulation time 196959336431 ps
CPU time 496.29 seconds
Started Jun 02 01:19:23 PM PDT 24
Finished Jun 02 01:27:40 PM PDT 24
Peak memory 209092 kb
Host smart-6b296fa1-e2f0-4647-95b0-c3b0d5e16973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486642413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.486642413
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3110010081
Short name T757
Test name
Test status
Simulation time 146237964352 ps
CPU time 1550.74 seconds
Started Jun 02 01:19:23 PM PDT 24
Finished Jun 02 01:45:15 PM PDT 24
Peak memory 225272 kb
Host smart-4b4d095b-ad00-4d62-a27a-4dc529fcd5e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110010081 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3110010081
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3814168055
Short name T876
Test name
Test status
Simulation time 813883849 ps
CPU time 2.41 seconds
Started Jun 02 01:19:23 PM PDT 24
Finished Jun 02 01:19:25 PM PDT 24
Peak memory 198768 kb
Host smart-3fb3b6e9-df1b-4472-ac78-3d770bf8bbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814168055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3814168055
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3957564510
Short name T874
Test name
Test status
Simulation time 155861933490 ps
CPU time 79.51 seconds
Started Jun 02 01:19:16 PM PDT 24
Finished Jun 02 01:20:36 PM PDT 24
Peak memory 200316 kb
Host smart-50aacb46-2a70-4159-a4c3-582f57585f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957564510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3957564510
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.895021726
Short name T1044
Test name
Test status
Simulation time 27009935 ps
CPU time 0.54 seconds
Started Jun 02 01:19:38 PM PDT 24
Finished Jun 02 01:19:39 PM PDT 24
Peak memory 194744 kb
Host smart-ed1d63e7-9d1c-4172-9eb6-35e33392269b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895021726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.895021726
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3908018281
Short name T270
Test name
Test status
Simulation time 22661555836 ps
CPU time 45.56 seconds
Started Jun 02 01:19:22 PM PDT 24
Finished Jun 02 01:20:08 PM PDT 24
Peak memory 200356 kb
Host smart-ab90e810-c42a-4174-a656-73308353a046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908018281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3908018281
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1663177342
Short name T776
Test name
Test status
Simulation time 64452367922 ps
CPU time 30.11 seconds
Started Jun 02 01:19:31 PM PDT 24
Finished Jun 02 01:20:01 PM PDT 24
Peak memory 200328 kb
Host smart-1de0fea0-cc66-426e-98c3-7a1a8e6156cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663177342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1663177342
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1807100292
Short name T977
Test name
Test status
Simulation time 59321901305 ps
CPU time 17.08 seconds
Started Jun 02 01:19:31 PM PDT 24
Finished Jun 02 01:19:48 PM PDT 24
Peak memory 200360 kb
Host smart-22e85f75-7f11-4ae3-b9bf-5581a15098e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807100292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1807100292
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.4211371984
Short name T326
Test name
Test status
Simulation time 16511094209 ps
CPU time 9.34 seconds
Started Jun 02 01:19:30 PM PDT 24
Finished Jun 02 01:19:39 PM PDT 24
Peak memory 200112 kb
Host smart-98281e29-6670-473a-87e7-41ed045f25fe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211371984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.4211371984
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.4164204277
Short name T748
Test name
Test status
Simulation time 162953336949 ps
CPU time 404.49 seconds
Started Jun 02 01:19:37 PM PDT 24
Finished Jun 02 01:26:21 PM PDT 24
Peak memory 200400 kb
Host smart-40493d02-c992-4088-afe5-9fcfd80e68b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164204277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.4164204277
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2026691770
Short name T710
Test name
Test status
Simulation time 351455225 ps
CPU time 0.88 seconds
Started Jun 02 01:19:31 PM PDT 24
Finished Jun 02 01:19:32 PM PDT 24
Peak memory 198136 kb
Host smart-bb8fc739-a5a6-449e-a808-fe78d98e1144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026691770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2026691770
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1160846754
Short name T868
Test name
Test status
Simulation time 249424314205 ps
CPU time 57.68 seconds
Started Jun 02 01:19:30 PM PDT 24
Finished Jun 02 01:20:28 PM PDT 24
Peak memory 199524 kb
Host smart-81b97549-84a6-4e64-a019-f90806b49ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160846754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1160846754
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1859557616
Short name T388
Test name
Test status
Simulation time 11683700947 ps
CPU time 517.63 seconds
Started Jun 02 01:19:31 PM PDT 24
Finished Jun 02 01:28:09 PM PDT 24
Peak memory 200412 kb
Host smart-dbab4ccf-0e6d-41c2-8730-ba7a02ba802a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859557616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1859557616
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3262340896
Short name T427
Test name
Test status
Simulation time 1486724137 ps
CPU time 0.72 seconds
Started Jun 02 01:19:30 PM PDT 24
Finished Jun 02 01:19:31 PM PDT 24
Peak memory 196000 kb
Host smart-3c30705f-a394-45d7-bcad-6514d0a7f31f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3262340896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3262340896
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3184240342
Short name T145
Test name
Test status
Simulation time 114646807319 ps
CPU time 48.55 seconds
Started Jun 02 01:19:30 PM PDT 24
Finished Jun 02 01:20:19 PM PDT 24
Peak memory 200440 kb
Host smart-d8184c00-70d2-41c8-9c20-44d7ec91ed91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184240342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3184240342
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3633771056
Short name T284
Test name
Test status
Simulation time 1412627586 ps
CPU time 3.16 seconds
Started Jun 02 01:19:30 PM PDT 24
Finished Jun 02 01:19:33 PM PDT 24
Peak memory 196056 kb
Host smart-32ca8941-33dc-4610-b325-87fec972fc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633771056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3633771056
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.247659917
Short name T404
Test name
Test status
Simulation time 5462463567 ps
CPU time 8.08 seconds
Started Jun 02 01:19:23 PM PDT 24
Finished Jun 02 01:19:31 PM PDT 24
Peak memory 200284 kb
Host smart-63cea774-728f-4108-93cc-f59cd4ecc05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247659917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.247659917
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3604841816
Short name T1027
Test name
Test status
Simulation time 131621498417 ps
CPU time 201.06 seconds
Started Jun 02 01:19:39 PM PDT 24
Finished Jun 02 01:23:00 PM PDT 24
Peak memory 200620 kb
Host smart-46faab6d-f486-41d8-bb1a-edb2c4522bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604841816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3604841816
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.4127486209
Short name T348
Test name
Test status
Simulation time 1086940201 ps
CPU time 1.53 seconds
Started Jun 02 01:19:31 PM PDT 24
Finished Jun 02 01:19:32 PM PDT 24
Peak memory 199112 kb
Host smart-1499a12a-8963-4896-8b51-d88fc73d3cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127486209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4127486209
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1626933453
Short name T862
Test name
Test status
Simulation time 93073149910 ps
CPU time 91.15 seconds
Started Jun 02 01:19:23 PM PDT 24
Finished Jun 02 01:20:54 PM PDT 24
Peak memory 200400 kb
Host smart-6534b38f-7d9c-4adf-9f5a-f48ee995005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626933453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1626933453
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2878614167
Short name T501
Test name
Test status
Simulation time 22595360 ps
CPU time 0.55 seconds
Started Jun 02 01:11:48 PM PDT 24
Finished Jun 02 01:11:49 PM PDT 24
Peak memory 194764 kb
Host smart-7a997e0f-0fc0-40e0-8ee1-ad9a8a183ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878614167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2878614167
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1484440452
Short name T782
Test name
Test status
Simulation time 220815093564 ps
CPU time 108.98 seconds
Started Jun 02 01:11:49 PM PDT 24
Finished Jun 02 01:13:39 PM PDT 24
Peak memory 200396 kb
Host smart-46aea8c6-9ff4-4d20-8c82-cf63ac13d73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484440452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1484440452
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.4111174563
Short name T160
Test name
Test status
Simulation time 153197023090 ps
CPU time 18.28 seconds
Started Jun 02 01:11:48 PM PDT 24
Finished Jun 02 01:12:06 PM PDT 24
Peak memory 200400 kb
Host smart-e9c88530-423e-4a64-a275-87731958e887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111174563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.4111174563
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.363597524
Short name T216
Test name
Test status
Simulation time 30061190870 ps
CPU time 51.53 seconds
Started Jun 02 01:11:50 PM PDT 24
Finished Jun 02 01:12:42 PM PDT 24
Peak memory 200516 kb
Host smart-d925f86d-2228-450e-90e2-720811bf5ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363597524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.363597524
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.2693446292
Short name T945
Test name
Test status
Simulation time 34603151839 ps
CPU time 19.95 seconds
Started Jun 02 01:11:49 PM PDT 24
Finished Jun 02 01:12:10 PM PDT 24
Peak memory 200300 kb
Host smart-4f4ea9b5-8432-41a4-833a-0ad057e603db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693446292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2693446292
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.668214715
Short name T290
Test name
Test status
Simulation time 103295746801 ps
CPU time 327 seconds
Started Jun 02 01:11:50 PM PDT 24
Finished Jun 02 01:17:18 PM PDT 24
Peak memory 200316 kb
Host smart-f969c099-4c0b-4d51-8562-6390d5303d81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=668214715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.668214715
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3267848213
Short name T341
Test name
Test status
Simulation time 6980554238 ps
CPU time 12.78 seconds
Started Jun 02 01:11:48 PM PDT 24
Finished Jun 02 01:12:02 PM PDT 24
Peak memory 200348 kb
Host smart-baa6348a-0248-4601-be94-cf00559b6ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267848213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3267848213
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.1517389220
Short name T559
Test name
Test status
Simulation time 68136439424 ps
CPU time 99.9 seconds
Started Jun 02 01:11:50 PM PDT 24
Finished Jun 02 01:13:30 PM PDT 24
Peak memory 200536 kb
Host smart-950f6800-9e3c-4a97-907e-20d0c40d3c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517389220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1517389220
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.1203063071
Short name T664
Test name
Test status
Simulation time 11265756297 ps
CPU time 576.01 seconds
Started Jun 02 01:11:49 PM PDT 24
Finished Jun 02 01:21:25 PM PDT 24
Peak memory 200352 kb
Host smart-f2376071-8c08-4735-b3bd-75e14a2a46b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203063071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1203063071
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3047284645
Short name T725
Test name
Test status
Simulation time 5976183567 ps
CPU time 25.91 seconds
Started Jun 02 01:11:49 PM PDT 24
Finished Jun 02 01:12:15 PM PDT 24
Peak memory 198484 kb
Host smart-5ebf8903-7621-40e4-8c8a-7ec4dbaf1e9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047284645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3047284645
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1569260180
Short name T1140
Test name
Test status
Simulation time 58731366730 ps
CPU time 103.58 seconds
Started Jun 02 01:11:48 PM PDT 24
Finished Jun 02 01:13:32 PM PDT 24
Peak memory 200340 kb
Host smart-5783faae-310d-4441-9cd7-fadc2a6ea04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569260180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1569260180
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1629078835
Short name T1088
Test name
Test status
Simulation time 36332180200 ps
CPU time 29.14 seconds
Started Jun 02 01:11:48 PM PDT 24
Finished Jun 02 01:12:17 PM PDT 24
Peak memory 196100 kb
Host smart-7c4ba6fd-fa08-4cf0-9246-fe5f0990f4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629078835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1629078835
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1571420701
Short name T568
Test name
Test status
Simulation time 670368784 ps
CPU time 2.02 seconds
Started Jun 02 01:11:40 PM PDT 24
Finished Jun 02 01:11:42 PM PDT 24
Peak memory 199140 kb
Host smart-b33fa97d-4dab-4ce2-bf39-fe5e27b44633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571420701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1571420701
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1403364976
Short name T115
Test name
Test status
Simulation time 135673566676 ps
CPU time 445.88 seconds
Started Jun 02 01:11:50 PM PDT 24
Finished Jun 02 01:19:17 PM PDT 24
Peak memory 200340 kb
Host smart-ff9ff2d4-779a-4608-bc95-c323fa0649ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403364976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1403364976
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2153853570
Short name T305
Test name
Test status
Simulation time 103848472287 ps
CPU time 526.69 seconds
Started Jun 02 01:11:53 PM PDT 24
Finished Jun 02 01:20:40 PM PDT 24
Peak memory 216816 kb
Host smart-d736b65b-8308-420c-86d4-10b02eae634e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153853570 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2153853570
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1534841031
Short name T361
Test name
Test status
Simulation time 7009565977 ps
CPU time 26.63 seconds
Started Jun 02 01:11:48 PM PDT 24
Finished Jun 02 01:12:16 PM PDT 24
Peak memory 200324 kb
Host smart-4dec4988-a415-4947-90aa-225e0ea1ff24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534841031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1534841031
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1761392252
Short name T655
Test name
Test status
Simulation time 71018745272 ps
CPU time 124.22 seconds
Started Jun 02 01:11:39 PM PDT 24
Finished Jun 02 01:13:44 PM PDT 24
Peak memory 200376 kb
Host smart-963ad969-6afd-486e-9880-a39fb7dc84fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761392252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1761392252
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2814779408
Short name T403
Test name
Test status
Simulation time 38199154684 ps
CPU time 31.61 seconds
Started Jun 02 01:19:37 PM PDT 24
Finished Jun 02 01:20:09 PM PDT 24
Peak memory 200364 kb
Host smart-c829e570-70c9-4d80-acba-47e8a12aa745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814779408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2814779408
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3462357874
Short name T737
Test name
Test status
Simulation time 255129940441 ps
CPU time 398.13 seconds
Started Jun 02 01:19:36 PM PDT 24
Finished Jun 02 01:26:15 PM PDT 24
Peak memory 216728 kb
Host smart-ad1e6904-fda9-4752-a101-b15ae421d96f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462357874 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3462357874
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1197658514
Short name T117
Test name
Test status
Simulation time 86456711561 ps
CPU time 56.13 seconds
Started Jun 02 01:19:37 PM PDT 24
Finished Jun 02 01:20:34 PM PDT 24
Peak memory 200392 kb
Host smart-cd284e17-3b03-4126-98b1-d5604463fa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197658514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1197658514
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.810575191
Short name T97
Test name
Test status
Simulation time 55092763167 ps
CPU time 643.21 seconds
Started Jun 02 01:19:39 PM PDT 24
Finished Jun 02 01:30:22 PM PDT 24
Peak memory 215932 kb
Host smart-f2284cd5-fef3-4097-a99a-cac7405f1e76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810575191 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.810575191
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3343075321
Short name T278
Test name
Test status
Simulation time 66619075627 ps
CPU time 19.21 seconds
Started Jun 02 01:19:37 PM PDT 24
Finished Jun 02 01:19:57 PM PDT 24
Peak memory 200384 kb
Host smart-cb57c865-4f2d-4bca-a61f-9f1fee4f0d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343075321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3343075321
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2017880198
Short name T800
Test name
Test status
Simulation time 319765208543 ps
CPU time 959 seconds
Started Jun 02 01:19:37 PM PDT 24
Finished Jun 02 01:35:36 PM PDT 24
Peak memory 225068 kb
Host smart-42ace50d-76bd-4dc8-ab7b-de589ac07032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017880198 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2017880198
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3205296090
Short name T426
Test name
Test status
Simulation time 20265738514 ps
CPU time 30.68 seconds
Started Jun 02 01:19:43 PM PDT 24
Finished Jun 02 01:20:14 PM PDT 24
Peak memory 200324 kb
Host smart-4ece3ad8-0833-46c5-bd14-939f3f3ca001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205296090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3205296090
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2191381843
Short name T491
Test name
Test status
Simulation time 262156949063 ps
CPU time 655.59 seconds
Started Jun 02 01:19:44 PM PDT 24
Finished Jun 02 01:30:40 PM PDT 24
Peak memory 217056 kb
Host smart-54a0ee77-7a74-426e-b857-26876573e90b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191381843 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2191381843
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3164886858
Short name T973
Test name
Test status
Simulation time 84133031757 ps
CPU time 541.05 seconds
Started Jun 02 01:19:44 PM PDT 24
Finished Jun 02 01:28:46 PM PDT 24
Peak memory 227560 kb
Host smart-29e4b9f9-8032-42d2-b2d2-5128a69ae8da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164886858 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3164886858
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3679430290
Short name T929
Test name
Test status
Simulation time 42368769802 ps
CPU time 485.82 seconds
Started Jun 02 01:19:44 PM PDT 24
Finished Jun 02 01:27:50 PM PDT 24
Peak memory 217004 kb
Host smart-1cf69940-1e12-4389-9c60-f793eb19544e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679430290 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3679430290
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.4090604264
Short name T1138
Test name
Test status
Simulation time 47430169777 ps
CPU time 189.72 seconds
Started Jun 02 01:19:44 PM PDT 24
Finished Jun 02 01:22:54 PM PDT 24
Peak memory 200416 kb
Host smart-0ccb85d0-6156-4e6a-a46e-0899c803d442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090604264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.4090604264
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1771921111
Short name T705
Test name
Test status
Simulation time 35400916758 ps
CPU time 415.3 seconds
Started Jun 02 01:19:44 PM PDT 24
Finished Jun 02 01:26:40 PM PDT 24
Peak memory 215288 kb
Host smart-2461ad94-2089-42ce-a9a6-2e1f35f4892b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771921111 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1771921111
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.4176007051
Short name T181
Test name
Test status
Simulation time 28146889990 ps
CPU time 55.82 seconds
Started Jun 02 01:19:44 PM PDT 24
Finished Jun 02 01:20:40 PM PDT 24
Peak memory 200376 kb
Host smart-0750b9ed-57a3-4e53-8c3b-77722fee0ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176007051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.4176007051
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2585504400
Short name T453
Test name
Test status
Simulation time 99256982617 ps
CPU time 1047.49 seconds
Started Jun 02 01:19:43 PM PDT 24
Finished Jun 02 01:37:11 PM PDT 24
Peak memory 216872 kb
Host smart-d0a8e5aa-f1f8-49dd-acd4-1e082974eef7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585504400 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2585504400
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1143231955
Short name T113
Test name
Test status
Simulation time 18559067771 ps
CPU time 35.4 seconds
Started Jun 02 01:19:50 PM PDT 24
Finished Jun 02 01:20:26 PM PDT 24
Peak memory 200304 kb
Host smart-3866e9d7-7b0b-4a2a-bba7-ece1307bebdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143231955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1143231955
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.944347678
Short name T849
Test name
Test status
Simulation time 121218348199 ps
CPU time 702.33 seconds
Started Jun 02 01:19:50 PM PDT 24
Finished Jun 02 01:31:32 PM PDT 24
Peak memory 217060 kb
Host smart-005af33c-47e5-4d7d-b088-5dc6f0e01c22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944347678 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.944347678
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1271731265
Short name T1087
Test name
Test status
Simulation time 360930168587 ps
CPU time 87.27 seconds
Started Jun 02 01:19:52 PM PDT 24
Finished Jun 02 01:21:20 PM PDT 24
Peak memory 200396 kb
Host smart-a0d1b3e3-13bf-4e28-aa73-bbca5307cc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271731265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1271731265
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.793654632
Short name T602
Test name
Test status
Simulation time 58065126 ps
CPU time 0.57 seconds
Started Jun 02 01:11:48 PM PDT 24
Finished Jun 02 01:11:49 PM PDT 24
Peak memory 195712 kb
Host smart-4b8cd56e-2437-4c03-9373-8c7b4924469f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793654632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.793654632
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3815070690
Short name T111
Test name
Test status
Simulation time 59762797936 ps
CPU time 31.6 seconds
Started Jun 02 01:11:48 PM PDT 24
Finished Jun 02 01:12:20 PM PDT 24
Peak memory 200380 kb
Host smart-cc5fb51b-ebab-413b-8dd0-c5214b489929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815070690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3815070690
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2498141337
Short name T436
Test name
Test status
Simulation time 54785410279 ps
CPU time 23.84 seconds
Started Jun 02 01:11:47 PM PDT 24
Finished Jun 02 01:12:11 PM PDT 24
Peak memory 200396 kb
Host smart-3ecab147-8c35-4c65-af14-faa4575e4f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498141337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2498141337
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.896629182
Short name T39
Test name
Test status
Simulation time 90159689265 ps
CPU time 74.08 seconds
Started Jun 02 01:11:47 PM PDT 24
Finished Jun 02 01:13:01 PM PDT 24
Peak memory 200356 kb
Host smart-103bd40b-856a-4e1f-91b2-f4e5004e89ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896629182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.896629182
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2374365647
Short name T310
Test name
Test status
Simulation time 318281556749 ps
CPU time 855.37 seconds
Started Jun 02 01:11:48 PM PDT 24
Finished Jun 02 01:26:04 PM PDT 24
Peak memory 200056 kb
Host smart-75b3c5df-ae76-4463-bd15-58f20793fe57
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374365647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2374365647
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.41867435
Short name T809
Test name
Test status
Simulation time 83771809603 ps
CPU time 582.54 seconds
Started Jun 02 01:11:48 PM PDT 24
Finished Jun 02 01:21:31 PM PDT 24
Peak memory 200364 kb
Host smart-39a30d28-0d39-4006-ad3c-8ffaa2159c3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41867435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.41867435
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.456853574
Short name T1135
Test name
Test status
Simulation time 182041910 ps
CPU time 0.71 seconds
Started Jun 02 01:11:47 PM PDT 24
Finished Jun 02 01:11:48 PM PDT 24
Peak memory 196452 kb
Host smart-96e24d86-d312-403a-8a27-0731d689b227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456853574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.456853574
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3232392076
Short name T967
Test name
Test status
Simulation time 39874974042 ps
CPU time 37.86 seconds
Started Jun 02 01:11:49 PM PDT 24
Finished Jun 02 01:12:27 PM PDT 24
Peak memory 200576 kb
Host smart-b747c56f-7f8a-4998-a4c6-02403cfb6cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232392076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3232392076
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3993095888
Short name T1149
Test name
Test status
Simulation time 21920693857 ps
CPU time 1081.34 seconds
Started Jun 02 01:11:49 PM PDT 24
Finished Jun 02 01:29:51 PM PDT 24
Peak memory 200396 kb
Host smart-75d26d62-b87a-4f0e-8a2d-5b8967f4b94d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3993095888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3993095888
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.87434347
Short name T1028
Test name
Test status
Simulation time 5848533953 ps
CPU time 49.28 seconds
Started Jun 02 01:11:47 PM PDT 24
Finished Jun 02 01:12:36 PM PDT 24
Peak memory 199828 kb
Host smart-a5ba3e7a-9809-4890-91ed-c5059f71da75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=87434347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.87434347
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3977585226
Short name T499
Test name
Test status
Simulation time 35712838410 ps
CPU time 23.87 seconds
Started Jun 02 01:11:48 PM PDT 24
Finished Jun 02 01:12:12 PM PDT 24
Peak memory 200228 kb
Host smart-e3a26705-067c-46ec-886e-43bb6960fb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977585226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3977585226
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2416218362
Short name T715
Test name
Test status
Simulation time 5138545398 ps
CPU time 2.74 seconds
Started Jun 02 01:11:48 PM PDT 24
Finished Jun 02 01:11:52 PM PDT 24
Peak memory 196344 kb
Host smart-7bcbf0aa-0ef9-465a-b5fb-3a4834876bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416218362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2416218362
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.827974110
Short name T618
Test name
Test status
Simulation time 845665819 ps
CPU time 3.83 seconds
Started Jun 02 01:11:48 PM PDT 24
Finished Jun 02 01:11:52 PM PDT 24
Peak memory 199120 kb
Host smart-91019bc6-0bdc-4082-856f-bc3cc1aa8db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827974110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.827974110
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.548347492
Short name T609
Test name
Test status
Simulation time 302118002387 ps
CPU time 280.2 seconds
Started Jun 02 01:11:49 PM PDT 24
Finished Jun 02 01:16:30 PM PDT 24
Peak memory 200416 kb
Host smart-e8e7aa86-a7bb-43cc-bfa6-1d26225dd107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548347492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.548347492
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.97185735
Short name T635
Test name
Test status
Simulation time 44879676149 ps
CPU time 1045.83 seconds
Started Jun 02 01:11:53 PM PDT 24
Finished Jun 02 01:29:19 PM PDT 24
Peak memory 216792 kb
Host smart-ea5499b8-ac37-4176-892a-ecc71c681f06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97185735 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.97185735
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.694670583
Short name T285
Test name
Test status
Simulation time 577048888 ps
CPU time 2.19 seconds
Started Jun 02 01:11:50 PM PDT 24
Finished Jun 02 01:11:52 PM PDT 24
Peak memory 198948 kb
Host smart-48acdacb-b95a-4fb2-aaff-03b4d7f9c834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694670583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.694670583
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1882473422
Short name T522
Test name
Test status
Simulation time 13631318329 ps
CPU time 14.44 seconds
Started Jun 02 01:11:49 PM PDT 24
Finished Jun 02 01:12:04 PM PDT 24
Peak memory 198104 kb
Host smart-9d0bfe99-e999-4f3c-85cc-13544f491fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882473422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1882473422
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3621280818
Short name T983
Test name
Test status
Simulation time 48719189000 ps
CPU time 22.25 seconds
Started Jun 02 01:19:52 PM PDT 24
Finished Jun 02 01:20:14 PM PDT 24
Peak memory 200420 kb
Host smart-d2327062-ad2e-480a-94b2-a6474001ff62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621280818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3621280818
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2243550648
Short name T483
Test name
Test status
Simulation time 181303072995 ps
CPU time 837.33 seconds
Started Jun 02 01:19:50 PM PDT 24
Finished Jun 02 01:33:48 PM PDT 24
Peak memory 216364 kb
Host smart-ae0eb9db-2251-43e5-9e61-3dfe16e876ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243550648 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2243550648
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2788382351
Short name T4
Test name
Test status
Simulation time 56379680131 ps
CPU time 25.66 seconds
Started Jun 02 01:19:50 PM PDT 24
Finished Jun 02 01:20:16 PM PDT 24
Peak memory 200344 kb
Host smart-ad72917a-cf5c-4e2f-9cb4-48631d9e672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788382351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2788382351
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1638597002
Short name T769
Test name
Test status
Simulation time 260944345334 ps
CPU time 604.6 seconds
Started Jun 02 01:19:51 PM PDT 24
Finished Jun 02 01:29:56 PM PDT 24
Peak memory 225240 kb
Host smart-fc6f9304-5147-4536-a4ab-ec4f19fe4915
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638597002 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1638597002
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2265239851
Short name T136
Test name
Test status
Simulation time 20765796318 ps
CPU time 43.68 seconds
Started Jun 02 01:19:50 PM PDT 24
Finished Jun 02 01:20:34 PM PDT 24
Peak memory 200396 kb
Host smart-d4815cba-e04f-436b-9bb5-3ca3b7105e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265239851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2265239851
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1106444655
Short name T768
Test name
Test status
Simulation time 24257819755 ps
CPU time 299.73 seconds
Started Jun 02 01:19:54 PM PDT 24
Finished Jun 02 01:24:54 PM PDT 24
Peak memory 216416 kb
Host smart-7a19ed7d-6d04-4f74-b5a8-ff0563dcd1d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106444655 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1106444655
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1766793253
Short name T894
Test name
Test status
Simulation time 14595957411 ps
CPU time 14.75 seconds
Started Jun 02 01:19:50 PM PDT 24
Finished Jun 02 01:20:05 PM PDT 24
Peak memory 200232 kb
Host smart-c3116eba-24a8-434f-a2e3-fbb7fe47392e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766793253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1766793253
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1043084682
Short name T198
Test name
Test status
Simulation time 152462849247 ps
CPU time 257.33 seconds
Started Jun 02 01:19:51 PM PDT 24
Finished Jun 02 01:24:09 PM PDT 24
Peak memory 200416 kb
Host smart-f2a19c0f-ca74-49ec-8547-07deb185e0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043084682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1043084682
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.131871947
Short name T88
Test name
Test status
Simulation time 22404091640 ps
CPU time 261.61 seconds
Started Jun 02 01:19:54 PM PDT 24
Finished Jun 02 01:24:16 PM PDT 24
Peak memory 208596 kb
Host smart-b1ed1f31-a6b7-4905-bf00-587f88089157
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131871947 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.131871947
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.4259290698
Short name T854
Test name
Test status
Simulation time 124962070181 ps
CPU time 55.11 seconds
Started Jun 02 01:19:50 PM PDT 24
Finished Jun 02 01:20:45 PM PDT 24
Peak memory 200340 kb
Host smart-329ac68a-ea0e-438b-a8db-ebdaad6e74c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259290698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.4259290698
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.340982857
Short name T1122
Test name
Test status
Simulation time 46872367406 ps
CPU time 430.96 seconds
Started Jun 02 01:19:59 PM PDT 24
Finished Jun 02 01:27:11 PM PDT 24
Peak memory 208680 kb
Host smart-7deb5fe4-eca3-4638-b9c4-e8d36ce86776
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340982857 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.340982857
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.607687706
Short name T336
Test name
Test status
Simulation time 179094617193 ps
CPU time 130.51 seconds
Started Jun 02 01:19:58 PM PDT 24
Finished Jun 02 01:22:09 PM PDT 24
Peak memory 200356 kb
Host smart-fd169bba-4675-4c77-bc2d-9c818282b3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607687706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.607687706
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1231969051
Short name T706
Test name
Test status
Simulation time 50201173545 ps
CPU time 71.95 seconds
Started Jun 02 01:20:01 PM PDT 24
Finished Jun 02 01:21:13 PM PDT 24
Peak memory 200416 kb
Host smart-a166faa9-535e-48c8-ba48-3ad63fa11300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231969051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1231969051
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.661730255
Short name T530
Test name
Test status
Simulation time 53918098015 ps
CPU time 952.15 seconds
Started Jun 02 01:19:59 PM PDT 24
Finished Jun 02 01:35:51 PM PDT 24
Peak memory 212844 kb
Host smart-efa86dee-c1fe-45e5-905a-8ae1494b8f05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661730255 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.661730255
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2877673372
Short name T962
Test name
Test status
Simulation time 53306360838 ps
CPU time 90.38 seconds
Started Jun 02 01:19:59 PM PDT 24
Finished Jun 02 01:21:30 PM PDT 24
Peak memory 200328 kb
Host smart-b33fbca7-e52f-4971-9245-a7d347692f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877673372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2877673372
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3090796022
Short name T804
Test name
Test status
Simulation time 55990515962 ps
CPU time 285.87 seconds
Started Jun 02 01:20:03 PM PDT 24
Finished Jun 02 01:24:49 PM PDT 24
Peak memory 215996 kb
Host smart-0ab9e8b3-99c6-489a-b138-d4fb7eb18a55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090796022 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3090796022
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2276560991
Short name T165
Test name
Test status
Simulation time 36049442323 ps
CPU time 224.22 seconds
Started Jun 02 01:19:59 PM PDT 24
Finished Jun 02 01:23:44 PM PDT 24
Peak memory 208704 kb
Host smart-e87e53b5-ff90-474b-8348-86d46c1034f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276560991 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2276560991
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.4273727223
Short name T691
Test name
Test status
Simulation time 11051775 ps
CPU time 0.63 seconds
Started Jun 02 01:12:01 PM PDT 24
Finished Jun 02 01:12:01 PM PDT 24
Peak memory 195776 kb
Host smart-21f5509e-5641-4b48-a585-6d676c7bddc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273727223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.4273727223
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.4206857632
Short name T825
Test name
Test status
Simulation time 119720598997 ps
CPU time 25.15 seconds
Started Jun 02 01:11:53 PM PDT 24
Finished Jun 02 01:12:19 PM PDT 24
Peak memory 200352 kb
Host smart-ceb7e4ce-edb2-4576-ad1d-fd617c851510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206857632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.4206857632
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.70340852
Short name T1147
Test name
Test status
Simulation time 33433833441 ps
CPU time 26.69 seconds
Started Jun 02 01:11:55 PM PDT 24
Finished Jun 02 01:12:22 PM PDT 24
Peak memory 200256 kb
Host smart-5f887501-7919-4ac1-bc14-3d58d7fbe041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70340852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.70340852
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1632349207
Short name T857
Test name
Test status
Simulation time 341043780588 ps
CPU time 44.09 seconds
Started Jun 02 01:11:57 PM PDT 24
Finished Jun 02 01:12:41 PM PDT 24
Peak memory 200432 kb
Host smart-ae4340e4-d68f-4161-b29a-6d1b785431e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632349207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1632349207
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3592583312
Short name T355
Test name
Test status
Simulation time 110091554952 ps
CPU time 161.52 seconds
Started Jun 02 01:11:53 PM PDT 24
Finished Jun 02 01:14:35 PM PDT 24
Peak memory 198552 kb
Host smart-cdab3df5-5907-425d-98cc-589f0da4bc36
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592583312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3592583312
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.118258000
Short name T893
Test name
Test status
Simulation time 60316937517 ps
CPU time 202.97 seconds
Started Jun 02 01:12:03 PM PDT 24
Finished Jun 02 01:15:27 PM PDT 24
Peak memory 200352 kb
Host smart-dc9c8b4d-5983-4c3d-8fb1-b22a92d498c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=118258000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.118258000
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.353851496
Short name T386
Test name
Test status
Simulation time 591665188 ps
CPU time 1.04 seconds
Started Jun 02 01:12:01 PM PDT 24
Finished Jun 02 01:12:03 PM PDT 24
Peak memory 197748 kb
Host smart-ca282dc9-397b-4b15-8c98-a99611e5cd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353851496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.353851496
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2570561369
Short name T1065
Test name
Test status
Simulation time 120863284221 ps
CPU time 30.71 seconds
Started Jun 02 01:11:53 PM PDT 24
Finished Jun 02 01:12:24 PM PDT 24
Peak memory 198196 kb
Host smart-e5dd34bf-e0a3-4993-881c-ade3d3580145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570561369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2570561369
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.861447111
Short name T1108
Test name
Test status
Simulation time 18296324685 ps
CPU time 972.76 seconds
Started Jun 02 01:12:02 PM PDT 24
Finished Jun 02 01:28:15 PM PDT 24
Peak memory 200352 kb
Host smart-6a214253-e940-4966-9e93-514858e22a14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=861447111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.861447111
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3122197883
Short name T953
Test name
Test status
Simulation time 2513705862 ps
CPU time 13.09 seconds
Started Jun 02 01:11:54 PM PDT 24
Finished Jun 02 01:12:07 PM PDT 24
Peak memory 198688 kb
Host smart-63423ac4-e2b2-49a1-b849-ccf20f268627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3122197883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3122197883
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.237603554
Short name T461
Test name
Test status
Simulation time 50707325324 ps
CPU time 22.47 seconds
Started Jun 02 01:11:54 PM PDT 24
Finished Jun 02 01:12:17 PM PDT 24
Peak memory 200256 kb
Host smart-09937039-2980-4c32-a948-eefe09de9ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237603554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.237603554
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1414462798
Short name T790
Test name
Test status
Simulation time 33766691886 ps
CPU time 52.14 seconds
Started Jun 02 01:11:54 PM PDT 24
Finished Jun 02 01:12:47 PM PDT 24
Peak memory 196204 kb
Host smart-e440f385-dc52-40d2-9122-7c68c704b53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414462798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1414462798
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3609150718
Short name T486
Test name
Test status
Simulation time 555340183 ps
CPU time 2.54 seconds
Started Jun 02 01:11:51 PM PDT 24
Finished Jun 02 01:11:54 PM PDT 24
Peak memory 199224 kb
Host smart-76e02d5c-fc9c-488c-ac28-e320dd3b990f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609150718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3609150718
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2830819844
Short name T102
Test name
Test status
Simulation time 212158742935 ps
CPU time 102.32 seconds
Started Jun 02 01:12:02 PM PDT 24
Finished Jun 02 01:13:45 PM PDT 24
Peak memory 200376 kb
Host smart-cb0d2582-b1c5-4f12-b1c6-fdd8f83ce1c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830819844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2830819844
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.366760168
Short name T1021
Test name
Test status
Simulation time 96046264952 ps
CPU time 258.56 seconds
Started Jun 02 01:12:03 PM PDT 24
Finished Jun 02 01:16:22 PM PDT 24
Peak memory 216852 kb
Host smart-ee9fe781-3ac6-48eb-992b-587f63e3ecaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366760168 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.366760168
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2194374562
Short name T400
Test name
Test status
Simulation time 851441511 ps
CPU time 2.6 seconds
Started Jun 02 01:12:03 PM PDT 24
Finished Jun 02 01:12:05 PM PDT 24
Peak memory 199084 kb
Host smart-81394e14-3164-43b4-aa66-cc43d8bcbd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194374562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2194374562
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2103476312
Short name T779
Test name
Test status
Simulation time 4025240136 ps
CPU time 7.58 seconds
Started Jun 02 01:11:54 PM PDT 24
Finished Jun 02 01:12:02 PM PDT 24
Peak memory 197920 kb
Host smart-4bfa90fa-6749-4b8c-b1ba-2b2b06905cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103476312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2103476312
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1030015238
Short name T367
Test name
Test status
Simulation time 32464359461 ps
CPU time 55.85 seconds
Started Jun 02 01:19:59 PM PDT 24
Finished Jun 02 01:20:55 PM PDT 24
Peak memory 200348 kb
Host smart-84a2d2ba-7f7c-481c-8253-b492c688a682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030015238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1030015238
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.260400157
Short name T498
Test name
Test status
Simulation time 21638310889 ps
CPU time 63.7 seconds
Started Jun 02 01:19:59 PM PDT 24
Finished Jun 02 01:21:03 PM PDT 24
Peak memory 200360 kb
Host smart-f1c535b7-8337-49f4-9aa3-2d584d5af81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260400157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.260400157
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1614172782
Short name T32
Test name
Test status
Simulation time 158519168845 ps
CPU time 380.46 seconds
Started Jun 02 01:20:07 PM PDT 24
Finished Jun 02 01:26:28 PM PDT 24
Peak memory 217036 kb
Host smart-8d3fbbe7-d221-42c1-ae79-6de289dc4f6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614172782 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1614172782
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1391484494
Short name T964
Test name
Test status
Simulation time 52287906383 ps
CPU time 72.88 seconds
Started Jun 02 01:20:06 PM PDT 24
Finished Jun 02 01:21:19 PM PDT 24
Peak memory 200284 kb
Host smart-20ae16b3-8a64-42b6-b813-f5596e58b4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391484494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1391484494
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.2318723656
Short name T885
Test name
Test status
Simulation time 156638881561 ps
CPU time 1028.23 seconds
Started Jun 02 01:20:06 PM PDT 24
Finished Jun 02 01:37:14 PM PDT 24
Peak memory 225468 kb
Host smart-2ca8fb8e-93c6-4b21-855b-5aa319ed861b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318723656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2318723656
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.4152024883
Short name T767
Test name
Test status
Simulation time 118362762949 ps
CPU time 262.18 seconds
Started Jun 02 01:20:08 PM PDT 24
Finished Jun 02 01:24:31 PM PDT 24
Peak memory 200272 kb
Host smart-939b522e-7b5a-417e-baa3-35e309e45659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152024883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.4152024883
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3774170995
Short name T398
Test name
Test status
Simulation time 26510384735 ps
CPU time 93.99 seconds
Started Jun 02 01:20:07 PM PDT 24
Finished Jun 02 01:21:41 PM PDT 24
Peak memory 210732 kb
Host smart-6cb0c6bd-17b7-40fe-bfe9-7cfbb0efb00a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774170995 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3774170995
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2956362196
Short name T686
Test name
Test status
Simulation time 49924153269 ps
CPU time 22.15 seconds
Started Jun 02 01:20:07 PM PDT 24
Finished Jun 02 01:20:29 PM PDT 24
Peak memory 200116 kb
Host smart-151348ec-8584-45ca-89ad-ebe4106401d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956362196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2956362196
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.505523888
Short name T1054
Test name
Test status
Simulation time 22417560212 ps
CPU time 260.54 seconds
Started Jun 02 01:20:06 PM PDT 24
Finished Jun 02 01:24:27 PM PDT 24
Peak memory 216052 kb
Host smart-0c1aa62c-890e-4f0b-8026-96ef3d5bf7ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505523888 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.505523888
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2066421471
Short name T775
Test name
Test status
Simulation time 22087126577 ps
CPU time 40.55 seconds
Started Jun 02 01:20:06 PM PDT 24
Finished Jun 02 01:20:47 PM PDT 24
Peak memory 200388 kb
Host smart-472d495c-b80d-45dd-8372-84e9d68ad8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066421471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2066421471
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.607391238
Short name T806
Test name
Test status
Simulation time 85282589316 ps
CPU time 359.52 seconds
Started Jun 02 01:20:06 PM PDT 24
Finished Jun 02 01:26:06 PM PDT 24
Peak memory 216280 kb
Host smart-aa98a763-b807-4f14-b37b-3c5d4523e27e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607391238 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.607391238
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.779843145
Short name T604
Test name
Test status
Simulation time 70370205723 ps
CPU time 1016.46 seconds
Started Jun 02 01:20:07 PM PDT 24
Finished Jun 02 01:37:04 PM PDT 24
Peak memory 225284 kb
Host smart-e299e39c-2731-4266-9f57-fe7f39e4d991
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779843145 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.779843145
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1833885243
Short name T666
Test name
Test status
Simulation time 50680835088 ps
CPU time 38.91 seconds
Started Jun 02 01:20:09 PM PDT 24
Finished Jun 02 01:20:48 PM PDT 24
Peak memory 200380 kb
Host smart-5a63e627-c4c1-4881-a70c-f8de4ab37251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833885243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1833885243
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1218109639
Short name T754
Test name
Test status
Simulation time 69293857736 ps
CPU time 202.4 seconds
Started Jun 02 01:20:06 PM PDT 24
Finished Jun 02 01:23:29 PM PDT 24
Peak memory 217040 kb
Host smart-ccc543c2-4ca6-4c0b-9063-070a9b544152
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218109639 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1218109639
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2683637128
Short name T205
Test name
Test status
Simulation time 50856655469 ps
CPU time 42.32 seconds
Started Jun 02 01:20:09 PM PDT 24
Finished Jun 02 01:20:52 PM PDT 24
Peak memory 200376 kb
Host smart-b2e503fa-690e-43e3-8c82-6dde6930ef8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683637128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2683637128
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3962925253
Short name T669
Test name
Test status
Simulation time 44618652934 ps
CPU time 791.17 seconds
Started Jun 02 01:20:07 PM PDT 24
Finished Jun 02 01:33:18 PM PDT 24
Peak memory 214712 kb
Host smart-ffd13cc7-d70d-4dcb-975b-90eea81b4fc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962925253 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3962925253
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3994796532
Short name T799
Test name
Test status
Simulation time 36161303760 ps
CPU time 113.07 seconds
Started Jun 02 01:20:06 PM PDT 24
Finished Jun 02 01:22:00 PM PDT 24
Peak memory 200312 kb
Host smart-3a20f6f3-b2df-4627-b531-1e94d1f6556f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994796532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3994796532
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2573199896
Short name T317
Test name
Test status
Simulation time 23362496438 ps
CPU time 257.44 seconds
Started Jun 02 01:20:06 PM PDT 24
Finished Jun 02 01:24:24 PM PDT 24
Peak memory 216220 kb
Host smart-9738bf73-1b91-4cea-9e0d-cc49e1396ad0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573199896 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2573199896
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1593679750
Short name T353
Test name
Test status
Simulation time 130061875 ps
CPU time 0.59 seconds
Started Jun 02 01:12:20 PM PDT 24
Finished Jun 02 01:12:21 PM PDT 24
Peak memory 195780 kb
Host smart-6d3f8d9c-0d58-482f-82af-c9a55c4f0bd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593679750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1593679750
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2885065713
Short name T520
Test name
Test status
Simulation time 30687637958 ps
CPU time 67.56 seconds
Started Jun 02 01:12:09 PM PDT 24
Finished Jun 02 01:13:17 PM PDT 24
Peak memory 200400 kb
Host smart-783bac3f-d6e4-4cdb-8647-8ab347aceb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885065713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2885065713
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1451286543
Short name T670
Test name
Test status
Simulation time 49198757058 ps
CPU time 136.84 seconds
Started Jun 02 01:12:09 PM PDT 24
Finished Jun 02 01:14:26 PM PDT 24
Peak memory 200336 kb
Host smart-89b9c707-f407-4c59-8d1e-fe13578ce20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451286543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1451286543
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.923182803
Short name T997
Test name
Test status
Simulation time 102084381377 ps
CPU time 50.91 seconds
Started Jun 02 01:12:09 PM PDT 24
Finished Jun 02 01:13:00 PM PDT 24
Peak memory 200400 kb
Host smart-79c1611f-92b3-44df-b11a-dd2b321e7ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923182803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.923182803
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3214223366
Short name T1113
Test name
Test status
Simulation time 37081396652 ps
CPU time 53.66 seconds
Started Jun 02 01:12:07 PM PDT 24
Finished Jun 02 01:13:00 PM PDT 24
Peak memory 200204 kb
Host smart-c0c76535-8c49-4866-b78f-58fd23ddd3b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214223366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3214223366
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3790426205
Short name T314
Test name
Test status
Simulation time 48074486943 ps
CPU time 171.08 seconds
Started Jun 02 01:12:14 PM PDT 24
Finished Jun 02 01:15:05 PM PDT 24
Peak memory 200344 kb
Host smart-28bf3ecd-ada7-4e94-bcbf-ea2f60ada4a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790426205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3790426205
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.22462890
Short name T590
Test name
Test status
Simulation time 7307865504 ps
CPU time 16.89 seconds
Started Jun 02 01:12:09 PM PDT 24
Finished Jun 02 01:12:27 PM PDT 24
Peak memory 200228 kb
Host smart-76c740d3-5aeb-4619-b874-b485c787b99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22462890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.22462890
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1894284175
Short name T506
Test name
Test status
Simulation time 26488881812 ps
CPU time 50.41 seconds
Started Jun 02 01:12:09 PM PDT 24
Finished Jun 02 01:13:00 PM PDT 24
Peak memory 200588 kb
Host smart-e0483591-75ce-4998-8b24-c0633e859e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894284175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1894284175
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2273708972
Short name T595
Test name
Test status
Simulation time 37226214521 ps
CPU time 2067.71 seconds
Started Jun 02 01:12:17 PM PDT 24
Finished Jun 02 01:46:45 PM PDT 24
Peak memory 200272 kb
Host smart-3d897b7d-45f2-4d48-8b32-1f43e4963498
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2273708972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2273708972
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2667139031
Short name T447
Test name
Test status
Simulation time 4841895910 ps
CPU time 41.97 seconds
Started Jun 02 01:12:10 PM PDT 24
Finished Jun 02 01:12:52 PM PDT 24
Peak memory 199132 kb
Host smart-f2ab548c-1f7c-4171-a113-0ff59506f81e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2667139031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2667139031
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.650676423
Short name T103
Test name
Test status
Simulation time 281039871909 ps
CPU time 81.93 seconds
Started Jun 02 01:12:10 PM PDT 24
Finished Jun 02 01:13:32 PM PDT 24
Peak memory 200380 kb
Host smart-636f2d5a-3833-4df7-93a9-d5471b822f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650676423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.650676423
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2797004343
Short name T796
Test name
Test status
Simulation time 5597495859 ps
CPU time 2.72 seconds
Started Jun 02 01:12:09 PM PDT 24
Finished Jun 02 01:12:12 PM PDT 24
Peak memory 196404 kb
Host smart-974af770-44d6-4203-ad59-13479bd019fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797004343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2797004343
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1052239274
Short name T611
Test name
Test status
Simulation time 646314363 ps
CPU time 3.87 seconds
Started Jun 02 01:12:10 PM PDT 24
Finished Jun 02 01:12:15 PM PDT 24
Peak memory 199288 kb
Host smart-d75a2c92-4fc1-45dc-b901-45d083f9909b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052239274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1052239274
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.619985817
Short name T121
Test name
Test status
Simulation time 395613404681 ps
CPU time 779.44 seconds
Started Jun 02 01:12:14 PM PDT 24
Finished Jun 02 01:25:14 PM PDT 24
Peak memory 200368 kb
Host smart-a9690a91-60c0-4031-af00-fd5fc7da48e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619985817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.619985817
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.4200250522
Short name T813
Test name
Test status
Simulation time 49775607588 ps
CPU time 1073.14 seconds
Started Jun 02 01:12:13 PM PDT 24
Finished Jun 02 01:30:07 PM PDT 24
Peak memory 217184 kb
Host smart-75cf563a-4d60-4ffe-b681-eb48b490c344
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200250522 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.4200250522
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.409833579
Short name T292
Test name
Test status
Simulation time 446613184 ps
CPU time 1.6 seconds
Started Jun 02 01:12:09 PM PDT 24
Finished Jun 02 01:12:10 PM PDT 24
Peak memory 198484 kb
Host smart-41c9599b-22bd-4a84-bfc6-2801dc89ecb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409833579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.409833579
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3455113315
Short name T908
Test name
Test status
Simulation time 136149600085 ps
CPU time 70.43 seconds
Started Jun 02 01:12:09 PM PDT 24
Finished Jun 02 01:13:20 PM PDT 24
Peak memory 200312 kb
Host smart-6b470941-268b-4033-8088-624b6155e94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455113315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3455113315
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2165114387
Short name T191
Test name
Test status
Simulation time 45487457204 ps
CPU time 19.6 seconds
Started Jun 02 01:20:05 PM PDT 24
Finished Jun 02 01:20:25 PM PDT 24
Peak memory 200268 kb
Host smart-0ec132c9-d6ea-4f28-9f27-2a184f871dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165114387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2165114387
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.30220774
Short name T689
Test name
Test status
Simulation time 83300329127 ps
CPU time 245.56 seconds
Started Jun 02 01:20:05 PM PDT 24
Finished Jun 02 01:24:11 PM PDT 24
Peak memory 208700 kb
Host smart-84bed862-0648-4850-bbc1-c7692ef5b625
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30220774 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.30220774
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2932921299
Short name T418
Test name
Test status
Simulation time 83824216595 ps
CPU time 198.09 seconds
Started Jun 02 01:20:10 PM PDT 24
Finished Jun 02 01:23:28 PM PDT 24
Peak memory 200412 kb
Host smart-6c8eb87c-9943-424a-b945-1a93ab0738db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932921299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2932921299
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3457750701
Short name T98
Test name
Test status
Simulation time 571995193424 ps
CPU time 685.83 seconds
Started Jun 02 01:20:06 PM PDT 24
Finished Jun 02 01:31:33 PM PDT 24
Peak memory 229504 kb
Host smart-d6002610-3a38-4bb0-bf56-0761c56978aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457750701 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3457750701
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.232784358
Short name T201
Test name
Test status
Simulation time 113954538548 ps
CPU time 62.22 seconds
Started Jun 02 01:20:06 PM PDT 24
Finished Jun 02 01:21:09 PM PDT 24
Peak memory 200340 kb
Host smart-e30d52a0-8f03-4c5b-af43-89bd10245857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232784358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.232784358
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.597868958
Short name T1174
Test name
Test status
Simulation time 58253571719 ps
CPU time 194.5 seconds
Started Jun 02 01:20:08 PM PDT 24
Finished Jun 02 01:23:23 PM PDT 24
Peak memory 216240 kb
Host smart-67b20289-fb6c-44b0-ab9d-3c51de3ea81d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597868958 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.597868958
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2032838214
Short name T1148
Test name
Test status
Simulation time 100759537504 ps
CPU time 201.04 seconds
Started Jun 02 01:20:20 PM PDT 24
Finished Jun 02 01:23:41 PM PDT 24
Peak memory 200284 kb
Host smart-b63a04ec-71d1-4fac-b2a1-83f304064c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032838214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2032838214
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1517118722
Short name T672
Test name
Test status
Simulation time 207691333143 ps
CPU time 817.48 seconds
Started Jun 02 01:20:16 PM PDT 24
Finished Jun 02 01:33:54 PM PDT 24
Peak memory 228924 kb
Host smart-b9841965-7fad-4a91-b9a2-6e621e78c905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517118722 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1517118722
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3180290881
Short name T220
Test name
Test status
Simulation time 8946917589 ps
CPU time 14.95 seconds
Started Jun 02 01:20:14 PM PDT 24
Finished Jun 02 01:20:29 PM PDT 24
Peak memory 200364 kb
Host smart-4660aa96-3e34-40c1-8d0d-71838ef58a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180290881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3180290881
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.112214377
Short name T45
Test name
Test status
Simulation time 108520628372 ps
CPU time 1750.59 seconds
Started Jun 02 01:20:16 PM PDT 24
Finished Jun 02 01:49:27 PM PDT 24
Peak memory 217028 kb
Host smart-97c23ce6-0cc7-4f4a-843c-2b9fc6531d5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112214377 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.112214377
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.904174356
Short name T332
Test name
Test status
Simulation time 25860262315 ps
CPU time 16.57 seconds
Started Jun 02 01:20:12 PM PDT 24
Finished Jun 02 01:20:29 PM PDT 24
Peak memory 200360 kb
Host smart-c4633464-2a1d-4ce9-8d27-410579cf9a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904174356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.904174356
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1855337110
Short name T318
Test name
Test status
Simulation time 42574844065 ps
CPU time 513.22 seconds
Started Jun 02 01:20:12 PM PDT 24
Finished Jun 02 01:28:46 PM PDT 24
Peak memory 216868 kb
Host smart-9ff71ba1-8ece-4cef-b0df-9bff35a4092f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855337110 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1855337110
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3832596410
Short name T12
Test name
Test status
Simulation time 94582254370 ps
CPU time 187.41 seconds
Started Jun 02 01:20:14 PM PDT 24
Finished Jun 02 01:23:22 PM PDT 24
Peak memory 200372 kb
Host smart-081af86d-8165-417b-ad5a-259882f5ddac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832596410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3832596410
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.305957132
Short name T56
Test name
Test status
Simulation time 96759500396 ps
CPU time 997.09 seconds
Started Jun 02 01:20:14 PM PDT 24
Finished Jun 02 01:36:52 PM PDT 24
Peak memory 226468 kb
Host smart-73ea317e-267f-433f-a863-3c00acb23883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305957132 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.305957132
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.583386896
Short name T302
Test name
Test status
Simulation time 61383210165 ps
CPU time 56.68 seconds
Started Jun 02 01:20:13 PM PDT 24
Finished Jun 02 01:21:10 PM PDT 24
Peak memory 200468 kb
Host smart-becb3c29-cc3e-465f-bcd1-48211cf1fcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583386896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.583386896
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2573189524
Short name T807
Test name
Test status
Simulation time 96328088184 ps
CPU time 844.52 seconds
Started Jun 02 01:20:16 PM PDT 24
Finished Jun 02 01:34:21 PM PDT 24
Peak memory 225508 kb
Host smart-15e389fe-0b11-4d91-98e0-e9877c445e49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573189524 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2573189524
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2701705196
Short name T534
Test name
Test status
Simulation time 66697952274 ps
CPU time 28.61 seconds
Started Jun 02 01:20:20 PM PDT 24
Finished Jun 02 01:20:49 PM PDT 24
Peak memory 200340 kb
Host smart-05c952a9-a024-4fb2-8880-89e76f61d55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701705196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2701705196
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.597287784
Short name T389
Test name
Test status
Simulation time 12785013 ps
CPU time 0.55 seconds
Started Jun 02 01:12:23 PM PDT 24
Finished Jun 02 01:12:24 PM PDT 24
Peak memory 195768 kb
Host smart-899b87a4-110f-4a43-a8dc-502bc0f254a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597287784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.597287784
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.837512813
Short name T157
Test name
Test status
Simulation time 323931764783 ps
CPU time 45.94 seconds
Started Jun 02 01:12:13 PM PDT 24
Finished Jun 02 01:12:59 PM PDT 24
Peak memory 200344 kb
Host smart-bef523a6-6ead-4e71-8d33-5351df49c53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837512813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.837512813
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.4155614015
Short name T411
Test name
Test status
Simulation time 11826453648 ps
CPU time 19.74 seconds
Started Jun 02 01:12:15 PM PDT 24
Finished Jun 02 01:12:35 PM PDT 24
Peak memory 200304 kb
Host smart-d3716904-4595-48bd-a09e-ba067959cd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155614015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.4155614015
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.635221671
Short name T1034
Test name
Test status
Simulation time 47437891054 ps
CPU time 35.1 seconds
Started Jun 02 01:12:15 PM PDT 24
Finished Jun 02 01:12:50 PM PDT 24
Peak memory 200416 kb
Host smart-264f9935-9f16-4995-8ab8-d0888ba8ff48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635221671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.635221671
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.4207394128
Short name T845
Test name
Test status
Simulation time 271742822779 ps
CPU time 69.55 seconds
Started Jun 02 01:12:16 PM PDT 24
Finished Jun 02 01:13:25 PM PDT 24
Peak memory 199392 kb
Host smart-c5c83199-3a4b-468c-8640-79142e2841a7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207394128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.4207394128
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2606258611
Short name T394
Test name
Test status
Simulation time 112969976970 ps
CPU time 667.39 seconds
Started Jun 02 01:12:25 PM PDT 24
Finished Jun 02 01:23:33 PM PDT 24
Peak memory 200400 kb
Host smart-f906ad09-2fc1-40f5-8f1e-a5890fc3f0b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606258611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2606258611
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1026773536
Short name T993
Test name
Test status
Simulation time 8647149632 ps
CPU time 2.91 seconds
Started Jun 02 01:12:24 PM PDT 24
Finished Jun 02 01:12:27 PM PDT 24
Peak memory 200392 kb
Host smart-5cd3c79e-473a-4a7e-9fe2-95af0b55f7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026773536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1026773536
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1299010669
Short name T40
Test name
Test status
Simulation time 34333660199 ps
CPU time 17.03 seconds
Started Jun 02 01:12:15 PM PDT 24
Finished Jun 02 01:12:32 PM PDT 24
Peak memory 200520 kb
Host smart-2ffd214e-1cbe-4ef2-b29f-9e01a18b1e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299010669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1299010669
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2558820213
Short name T555
Test name
Test status
Simulation time 7526476973 ps
CPU time 412.5 seconds
Started Jun 02 01:12:24 PM PDT 24
Finished Jun 02 01:19:17 PM PDT 24
Peak memory 200288 kb
Host smart-76487896-e181-4fb4-be66-1565c07bea5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2558820213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2558820213
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.4082281834
Short name T1102
Test name
Test status
Simulation time 1913160558 ps
CPU time 3.14 seconds
Started Jun 02 01:12:15 PM PDT 24
Finished Jun 02 01:12:18 PM PDT 24
Peak memory 198900 kb
Host smart-fc75a86d-21e2-4514-ae9d-0dfa4a523db7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4082281834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4082281834
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2720930470
Short name T377
Test name
Test status
Simulation time 26827699345 ps
CPU time 42.74 seconds
Started Jun 02 01:12:20 PM PDT 24
Finished Jun 02 01:13:03 PM PDT 24
Peak memory 200336 kb
Host smart-248def76-cca3-4373-a5ee-90f485d7162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720930470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2720930470
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.4243700043
Short name T866
Test name
Test status
Simulation time 1861451372 ps
CPU time 2.18 seconds
Started Jun 02 01:12:20 PM PDT 24
Finished Jun 02 01:12:22 PM PDT 24
Peak memory 195764 kb
Host smart-86ec48bd-2334-4e10-b01e-5a1e765ba267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243700043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.4243700043
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.4066476748
Short name T842
Test name
Test status
Simulation time 485823751 ps
CPU time 2.49 seconds
Started Jun 02 01:12:14 PM PDT 24
Finished Jun 02 01:12:17 PM PDT 24
Peak memory 198484 kb
Host smart-712131c9-7445-4345-b613-1c7a636ee836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066476748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.4066476748
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.4264529025
Short name T852
Test name
Test status
Simulation time 18248728091 ps
CPU time 443.87 seconds
Started Jun 02 01:12:26 PM PDT 24
Finished Jun 02 01:19:50 PM PDT 24
Peak memory 200360 kb
Host smart-a2cfb4be-99d6-4596-81be-c43b4b650fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264529025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.4264529025
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3918230450
Short name T933
Test name
Test status
Simulation time 39035876932 ps
CPU time 920.42 seconds
Started Jun 02 01:12:23 PM PDT 24
Finished Jun 02 01:27:43 PM PDT 24
Peak memory 225192 kb
Host smart-e882490b-f8e3-4648-b3d1-7a961242879d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918230450 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3918230450
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.607049488
Short name T1121
Test name
Test status
Simulation time 762471811 ps
CPU time 2.3 seconds
Started Jun 02 01:12:23 PM PDT 24
Finished Jun 02 01:12:26 PM PDT 24
Peak memory 198696 kb
Host smart-9bc54418-2922-4756-a226-8114ab93330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607049488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.607049488
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1832022236
Short name T1020
Test name
Test status
Simulation time 129167692245 ps
CPU time 85 seconds
Started Jun 02 01:12:17 PM PDT 24
Finished Jun 02 01:13:42 PM PDT 24
Peak memory 200376 kb
Host smart-de24e712-e3e4-45b6-890a-299d74155bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832022236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1832022236
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3741426577
Short name T1161
Test name
Test status
Simulation time 19184919920 ps
CPU time 16.02 seconds
Started Jun 02 01:20:19 PM PDT 24
Finished Jun 02 01:20:36 PM PDT 24
Peak memory 200400 kb
Host smart-2dae002c-b70a-4ba8-9d86-f569d835b2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741426577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3741426577
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2549553420
Short name T707
Test name
Test status
Simulation time 7164902474 ps
CPU time 81.33 seconds
Started Jun 02 01:20:19 PM PDT 24
Finished Jun 02 01:21:40 PM PDT 24
Peak memory 216812 kb
Host smart-3657a9db-c68b-4a60-81ea-2eebfff4f24d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549553420 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2549553420
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3339001220
Short name T128
Test name
Test status
Simulation time 54148503943 ps
CPU time 28.55 seconds
Started Jun 02 01:20:20 PM PDT 24
Finished Jun 02 01:20:49 PM PDT 24
Peak memory 200292 kb
Host smart-cd352aff-6cfe-4b28-9d0b-7e4f6038cb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339001220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3339001220
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2373968312
Short name T139
Test name
Test status
Simulation time 109490938106 ps
CPU time 387.49 seconds
Started Jun 02 01:20:19 PM PDT 24
Finished Jun 02 01:26:47 PM PDT 24
Peak memory 210192 kb
Host smart-e9c0d5cb-2c10-4668-9741-350833eaab11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373968312 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2373968312
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3055036590
Short name T1104
Test name
Test status
Simulation time 153745195396 ps
CPU time 138.07 seconds
Started Jun 02 01:20:19 PM PDT 24
Finished Jun 02 01:22:38 PM PDT 24
Peak memory 200300 kb
Host smart-a998825e-72b3-4e1e-bf59-5d2f0964b556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055036590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3055036590
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2839420331
Short name T236
Test name
Test status
Simulation time 80204993583 ps
CPU time 139.16 seconds
Started Jun 02 01:20:21 PM PDT 24
Finished Jun 02 01:22:41 PM PDT 24
Peak memory 200308 kb
Host smart-04392c13-4b6b-45d7-af24-30db92d7b729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839420331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2839420331
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3537391136
Short name T1046
Test name
Test status
Simulation time 67377054015 ps
CPU time 194.95 seconds
Started Jun 02 01:20:21 PM PDT 24
Finished Jun 02 01:23:36 PM PDT 24
Peak memory 216816 kb
Host smart-900f10bf-ce9c-4842-85b1-182eb6914537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537391136 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3537391136
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2613870327
Short name T374
Test name
Test status
Simulation time 13428301373 ps
CPU time 24.15 seconds
Started Jun 02 01:20:20 PM PDT 24
Finished Jun 02 01:20:45 PM PDT 24
Peak memory 200376 kb
Host smart-8127d089-6297-4869-8edc-eea4fd90cd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613870327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2613870327
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2431808574
Short name T1133
Test name
Test status
Simulation time 64082908173 ps
CPU time 625.12 seconds
Started Jun 02 01:20:23 PM PDT 24
Finished Jun 02 01:30:48 PM PDT 24
Peak memory 217036 kb
Host smart-aa926af9-26f9-4c93-ab55-de37d182976a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431808574 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2431808574
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3618553572
Short name T264
Test name
Test status
Simulation time 11224240431 ps
CPU time 23.24 seconds
Started Jun 02 01:20:23 PM PDT 24
Finished Jun 02 01:20:47 PM PDT 24
Peak memory 200412 kb
Host smart-95e871ee-9b40-419c-8cfe-5af934568e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618553572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3618553572
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2332001488
Short name T30
Test name
Test status
Simulation time 55261697162 ps
CPU time 634.46 seconds
Started Jun 02 01:20:20 PM PDT 24
Finished Jun 02 01:30:55 PM PDT 24
Peak memory 216856 kb
Host smart-120649ba-45e9-4809-abe9-d2417274a25d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332001488 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2332001488
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3205932928
Short name T924
Test name
Test status
Simulation time 163350821313 ps
CPU time 65.1 seconds
Started Jun 02 01:20:19 PM PDT 24
Finished Jun 02 01:21:24 PM PDT 24
Peak memory 200412 kb
Host smart-22f316bc-12f7-4e1a-a18e-5bfeb1e31e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205932928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3205932928
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2696944878
Short name T819
Test name
Test status
Simulation time 219338761081 ps
CPU time 718.92 seconds
Started Jun 02 01:20:22 PM PDT 24
Finished Jun 02 01:32:21 PM PDT 24
Peak memory 217108 kb
Host smart-e93eb319-3e7f-40ec-8f3b-02c8d18b80ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696944878 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2696944878
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.4253402203
Short name T575
Test name
Test status
Simulation time 245843027947 ps
CPU time 117.66 seconds
Started Jun 02 01:20:26 PM PDT 24
Finished Jun 02 01:22:24 PM PDT 24
Peak memory 200380 kb
Host smart-328801ee-ca06-47ea-b517-6ef972fd7d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253402203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.4253402203
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.380180155
Short name T954
Test name
Test status
Simulation time 57534432227 ps
CPU time 334.67 seconds
Started Jun 02 01:20:28 PM PDT 24
Finished Jun 02 01:26:03 PM PDT 24
Peak memory 217040 kb
Host smart-6e81b6a0-2c99-43cc-83de-0f790592831a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380180155 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.380180155
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.413697183
Short name T182
Test name
Test status
Simulation time 33683537025 ps
CPU time 15.89 seconds
Started Jun 02 01:20:25 PM PDT 24
Finished Jun 02 01:20:41 PM PDT 24
Peak memory 200404 kb
Host smart-6b8f5331-1fc2-4a06-aac8-0c2f268e3435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413697183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.413697183
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3973083620
Short name T93
Test name
Test status
Simulation time 128211757939 ps
CPU time 627.74 seconds
Started Jun 02 01:20:27 PM PDT 24
Finished Jun 02 01:30:56 PM PDT 24
Peak memory 225272 kb
Host smart-2ddfec5f-92d8-448f-b3c3-6ec8a177ac2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973083620 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3973083620
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2797306984
Short name T608
Test name
Test status
Simulation time 30967787486 ps
CPU time 15.16 seconds
Started Jun 02 01:20:26 PM PDT 24
Finished Jun 02 01:20:41 PM PDT 24
Peak memory 200360 kb
Host smart-81d72e11-bf59-4dbf-a43a-5ff237139652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797306984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2797306984
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2958483336
Short name T905
Test name
Test status
Simulation time 45161091405 ps
CPU time 862.68 seconds
Started Jun 02 01:20:26 PM PDT 24
Finished Jun 02 01:34:49 PM PDT 24
Peak memory 216844 kb
Host smart-525d5f6b-343a-4dc2-b61b-d0260aa26992
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958483336 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2958483336
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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